GCC Code Coverage Report
Directory: ./ Exec Total Coverage
File: lib/libcompiler_rt/clear_cache.c Lines: 0 0 0.0 %
Date: 2017-11-13 Branches: 0 0 0.0 %

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/* ===-- clear_cache.c - Implement __clear_cache ---------------------------===
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 *
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 *                     The LLVM Compiler Infrastructure
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 *
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 * This file is dual licensed under the MIT and the University of Illinois Open
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 * Source Licenses. See LICENSE.TXT for details.
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 *
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 * ===----------------------------------------------------------------------===
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 */
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#include "int_lib.h"
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#include <stddef.h>
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#if __APPLE__
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  #include <libkern/OSCacheControl.h>
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#endif
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#if defined(_WIN32)
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/* Forward declare Win32 APIs since the GCC mode driver does not handle the
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   newer SDKs as well as needed.  */
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uint32_t FlushInstructionCache(uintptr_t hProcess, void *lpBaseAddress,
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                               uintptr_t dwSize);
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uintptr_t GetCurrentProcess(void);
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#endif
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#if (defined(__FreeBSD__) || defined(__Bitrig__)) && defined(__arm__)
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  #include <sys/types.h>
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  #include <machine/sysarch.h>
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#endif
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#if defined(__NetBSD__) && defined(__arm__)
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  #include <machine/sysarch.h>
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#endif
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#if defined(__mips__)
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  #include <sys/cachectl.h>
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  #include <sys/syscall.h>
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  #include <unistd.h>
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  #if defined(__ANDROID__) && defined(__LP64__)
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    /*
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     * clear_mips_cache - Invalidates instruction cache for Mips.
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     */
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    static void clear_mips_cache(const void* Addr, size_t Size) {
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      asm volatile (
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        ".set push\n"
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        ".set noreorder\n"
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        ".set noat\n"
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        "beq %[Size], $zero, 20f\n"          /* If size == 0, branch around. */
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        "nop\n"
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        "daddu %[Size], %[Addr], %[Size]\n"  /* Calculate end address + 1 */
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        "rdhwr $v0, $1\n"                    /* Get step size for SYNCI.
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                                                $1 is $HW_SYNCI_Step */
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        "beq $v0, $zero, 20f\n"              /* If no caches require
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                                                synchronization, branch
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                                                around. */
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        "nop\n"
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        "10:\n"
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        "synci 0(%[Addr])\n"                 /* Synchronize all caches around
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                                                address. */
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        "daddu %[Addr], %[Addr], $v0\n"      /* Add step size. */
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        "sltu $at, %[Addr], %[Size]\n"       /* Compare current with end
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                                                address. */
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        "bne $at, $zero, 10b\n"              /* Branch if more to do. */
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        "nop\n"
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        "sync\n"                             /* Clear memory hazards. */
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        "20:\n"
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        "bal 30f\n"
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        "nop\n"
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        "30:\n"
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        "daddiu $ra, $ra, 12\n"              /* $ra has a value of $pc here.
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                                                Add offset of 12 to point to the
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                                                instruction after the last nop.
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                                              */
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        "jr.hb $ra\n"                        /* Return, clearing instruction
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                                                hazards. */
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        "nop\n"
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        ".set pop\n"
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        : [Addr] "+r"(Addr), [Size] "+r"(Size)
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        :: "at", "ra", "v0", "memory"
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      );
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    }
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  #endif
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#endif
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#if defined(__linux__) && defined(__arm__)
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  #include <asm/unistd.h>
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#endif
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/*
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 * The compiler generates calls to __clear_cache() when creating
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 * trampoline functions on the stack for use with nested functions.
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 * It is expected to invalidate the instruction cache for the
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 * specified range.
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 */
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void __clear_cache(void *start, void *end) {
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#if __i386__ || __x86_64__
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/*
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 * Intel processors have a unified instruction and data cache
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 * so there is nothing to do
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 */
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#elif defined(__arm__) && !defined(__APPLE__)
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    #if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__Bitrig__)
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        struct arm_sync_icache_args arg;
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        arg.addr = (uintptr_t)start;
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        arg.len = (uintptr_t)end - (uintptr_t)start;
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        sysarch(ARM_SYNC_ICACHE, &arg);
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    #elif defined(__linux__)
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         register int start_reg __asm("r0") = (int) (intptr_t) start;
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         const register int end_reg __asm("r1") = (int) (intptr_t) end;
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         const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush;
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         __asm __volatile("svc 0x0"
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                          : "=r"(start_reg)
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                          : "r"(syscall_nr), "r"(start_reg), "r"(end_reg));
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         if (start_reg != 0) {
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             compilerrt_abort();
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         }
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    #elif defined(_WIN32)
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        FlushInstructionCache(GetCurrentProcess(), start, end - start);
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    #else
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        compilerrt_abort();
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    #endif
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#elif defined(__mips__)
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  const uintptr_t start_int = (uintptr_t) start;
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  const uintptr_t end_int = (uintptr_t) end;
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    #if defined(__ANDROID__) && defined(__LP64__)
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        // Call synci implementation for short address range.
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        const uintptr_t address_range_limit = 256;
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        if ((end_int - start_int) <= address_range_limit) {
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            clear_mips_cache(start, (end_int - start_int));
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        } else {
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            syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
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        }
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    #else
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        syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
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    #endif
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#elif defined(__aarch64__) && !defined(__APPLE__)
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  uint64_t xstart = (uint64_t)(uintptr_t) start;
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  uint64_t xend = (uint64_t)(uintptr_t) end;
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  uint64_t addr;
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  // Get Cache Type Info
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  uint64_t ctr_el0;
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  __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0));
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  /*
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   * dc & ic instructions must use 64bit registers so we don't use
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   * uintptr_t in case this runs in an IPL32 environment.
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   */
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  const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15);
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  for (addr = xstart; addr < xend; addr += dcache_line_size)
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    __asm __volatile("dc cvau, %0" :: "r"(addr));
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  __asm __volatile("dsb ish");
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  const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15);
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  for (addr = xstart; addr < xend; addr += icache_line_size)
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    __asm __volatile("ic ivau, %0" :: "r"(addr));
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  __asm __volatile("isb sy");
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#else
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    #if __APPLE__
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        /* On Darwin, sys_icache_invalidate() provides this functionality */
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        sys_icache_invalidate(start, end-start);
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    #else
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        compilerrt_abort();
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    #endif
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#endif
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}
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