GCC Code Coverage Report
Directory: ./ Exec Total Coverage
File: usr.sbin/vmd/pci.c Lines: 0 151 0.0 %
Date: 2017-11-13 Branches: 0 90 0.0 %

Line Branch Exec Source
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/*	$OpenBSD: pci.c,v 1.22 2017/09/17 23:07:56 pd Exp $	*/
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/*
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 * Copyright (c) 2015 Mike Larkin <mlarkin@openbsd.org>
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 *
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 * Permission to use, copy, modify, and distribute this software for any
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 * purpose with or without fee is hereby granted, provided that the above
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 * copyright notice and this permission notice appear in all copies.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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 */
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#include <sys/types.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pv/virtioreg.h>
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#include <machine/vmmvar.h>
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#include <string.h>
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#include <unistd.h>
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#include "vmd.h"
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#include "pci.h"
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#include "vmm.h"
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#include "atomicio.h"
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struct pci pci;
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extern char *__progname;
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/* PIC IRQs, assigned to devices in order */
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const uint8_t pci_pic_irqs[PCI_MAX_PIC_IRQS] = {3, 5, 6, 7, 9, 10, 11, 12,
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    14, 15};
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/*
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 * pci_add_bar
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 *
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 * Adds a BAR for the PCI device 'id'. On access, 'barfn' will be
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 * called, and passed 'cookie' as an identifier.
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 *
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 * BARs are fixed size, meaning all I/O BARs requested have the
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 * same size and all MMIO BARs have the same size.
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 *
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 * Parameters:
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 *  id: PCI device to add the BAR to (local count, eg if id == 4,
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 *      this BAR is to be added to the VM's 5th PCI device)
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 *  type: type of the BAR to add (PCI_MAPREG_TYPE_xxx)
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 *  barfn: callback function invoked on BAR access
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 *  cookie: cookie passed to barfn on access
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 *
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 * Returns 0 if the BAR was added successfully, 1 otherwise.
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 */
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int
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pci_add_bar(uint8_t id, uint32_t type, void *barfn, void *cookie)
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{
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	uint8_t bar_reg_idx, bar_ct;
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	/* Check id */
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	if (id >= pci.pci_dev_ct)
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		return (1);
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	/* Can only add PCI_MAX_BARS BARs to any device */
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	bar_ct = pci.pci_devices[id].pd_bar_ct;
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	if (bar_ct >= PCI_MAX_BARS)
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		return (1);
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73
	/* Compute BAR address and add */
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	bar_reg_idx = (PCI_MAPREG_START + (bar_ct * 4)) / 4;
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	if (type == PCI_MAPREG_TYPE_MEM) {
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		if (pci.pci_next_mmio_bar >= VMM_PCI_MMIO_BAR_END)
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			return (1);
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		pci.pci_devices[id].pd_cfg_space[bar_reg_idx] =
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		    PCI_MAPREG_MEM_ADDR(pci.pci_next_mmio_bar);
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		pci.pci_next_mmio_bar += VMM_PCI_MMIO_BAR_SIZE;
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		pci.pci_devices[id].pd_barfunc[bar_ct] = barfn;
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		pci.pci_devices[id].pd_bar_cookie[bar_ct] = cookie;
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		pci.pci_devices[id].pd_bartype[bar_ct] = PCI_BAR_TYPE_MMIO;
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		pci.pci_devices[id].pd_barsize[bar_ct] = VMM_PCI_MMIO_BAR_SIZE;
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		pci.pci_devices[id].pd_bar_ct++;
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	} else if (type == PCI_MAPREG_TYPE_IO) {
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		if (pci.pci_next_io_bar >= VMM_PCI_IO_BAR_END)
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			return (1);
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		pci.pci_devices[id].pd_cfg_space[bar_reg_idx] =
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		    PCI_MAPREG_IO_ADDR(pci.pci_next_io_bar) |
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		    PCI_MAPREG_TYPE_IO;
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		pci.pci_next_io_bar += VMM_PCI_IO_BAR_SIZE;
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		pci.pci_devices[id].pd_barfunc[bar_ct] = barfn;
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		pci.pci_devices[id].pd_bar_cookie[bar_ct] = cookie;
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		dprintf("%s: adding pci bar cookie for dev %d bar %d = %p",
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		    __progname, id, bar_ct, cookie);
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		pci.pci_devices[id].pd_bartype[bar_ct] = PCI_BAR_TYPE_IO;
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		pci.pci_devices[id].pd_barsize[bar_ct] = VMM_PCI_IO_BAR_SIZE;
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		pci.pci_devices[id].pd_bar_ct++;
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	}
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104
	return (0);
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}
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107
int
108
pci_set_bar_fn(uint8_t id, uint8_t bar_ct, void *barfn, void *cookie)
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{
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	/* Check id */
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	if (id >= pci.pci_dev_ct)
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		return (1);
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	if (bar_ct >= PCI_MAX_BARS)
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		return (1);
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	pci.pci_devices[id].pd_barfunc[bar_ct] = barfn;
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	pci.pci_devices[id].pd_bar_cookie[bar_ct] = cookie;
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	return (0);
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}
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/*
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 * pci_get_dev_irq
125
 *
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 * Returns the IRQ for the specified PCI device
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 *
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 * Parameters:
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 *  id: PCI device id to return IRQ for
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 *
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 * Return values:
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 *  The IRQ for the device, or 0xff if no device IRQ assigned
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 */
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uint8_t
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pci_get_dev_irq(uint8_t id)
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{
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	if (pci.pci_devices[id].pd_int)
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		return pci.pci_devices[id].pd_irq;
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	else
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		return 0xFF;
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}
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/*
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 * pci_add_device
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 *
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 * Adds a PCI device to the guest VM defined by the supplied parameters.
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 *
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 * Parameters:
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 *  id: the new PCI device ID (0 .. PCI_CONFIG_MAX_DEV)
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 *  vid: PCI VID of the new device
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 *  pid: PCI PID of the new device
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 *  class: PCI 'class' of the new device
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 *  subclass: PCI 'subclass' of the new device
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 *  subsys_vid: subsystem VID of the new device
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 *  subsys_id: subsystem ID of the new device
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 *  irq_needed: 1 if an IRQ should be assigned to this PCI device, 0 otherwise
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 *  csfunc: PCI config space callback function when the guest VM accesses
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 *      CS of this PCI device
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 *
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 * Return values:
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 *  0: the PCI device was added successfully. The PCI device ID is in 'id'.
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 *  1: the PCI device addition failed.
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 */
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int
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pci_add_device(uint8_t *id, uint16_t vid, uint16_t pid, uint8_t class,
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    uint8_t subclass, uint16_t subsys_vid, uint16_t subsys_id,
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    uint8_t irq_needed, pci_cs_fn_t csfunc)
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{
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	/* Exceeded max devices? */
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	if (pci.pci_dev_ct >= PCI_CONFIG_MAX_DEV)
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		return (1);
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	/* Exceeded max IRQs? */
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	/* XXX we could share IRQs ... */
175
	if (pci.pci_next_pic_irq >= PCI_MAX_PIC_IRQS && irq_needed)
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		return (1);
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178
	*id = pci.pci_dev_ct;
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	pci.pci_devices[*id].pd_vid = vid;
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	pci.pci_devices[*id].pd_did = pid;
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	pci.pci_devices[*id].pd_class = class;
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	pci.pci_devices[*id].pd_subclass = subclass;
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	pci.pci_devices[*id].pd_subsys_vid = subsys_vid;
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	pci.pci_devices[*id].pd_subsys_id = subsys_id;
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	pci.pci_devices[*id].pd_csfunc = csfunc;
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	if (irq_needed) {
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		pci.pci_devices[*id].pd_irq =
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		    pci_pic_irqs[pci.pci_next_pic_irq];
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		pci.pci_devices[*id].pd_int = 1;
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		pci.pci_next_pic_irq++;
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		dprintf("assigned irq %d to pci dev %d",
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		    pci.pci_devices[*id].pd_irq, *id);
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	}
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	pci.pci_dev_ct ++;
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	return (0);
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}
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/*
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 * pci_init
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 *
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 * Initializes the PCI subsystem for the VM by adding a PCI host bridge
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 * as the first PCI device.
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 */
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void
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pci_init(void)
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{
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	uint8_t id;
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	memset(&pci, 0, sizeof(pci));
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	pci.pci_next_mmio_bar = VMM_PCI_MMIO_BAR_BASE;
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	pci.pci_next_io_bar = VMM_PCI_IO_BAR_BASE;
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	if (pci_add_device(&id, PCI_VENDOR_OPENBSD, PCI_PRODUCT_OPENBSD_PCHB,
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	    PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_HOST,
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	    PCI_VENDOR_OPENBSD, 0, 0, NULL)) {
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		log_warnx("%s: can't add PCI host bridge", __progname);
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		return;
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	}
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}
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void
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pci_handle_address_reg(struct vm_run_params *vrp)
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{
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	union vm_exit *vei = vrp->vrp_exit;
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	/*
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	 * vei_dir == VEI_DIR_OUT : out instruction
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	 *
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	 * The guest wrote to the address register.
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	 */
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	if (vei->vei.vei_dir == VEI_DIR_OUT) {
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		get_input_data(vei, &pci.pci_addr_reg);
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	} else {
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		/*
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		 * vei_dir == VEI_DIR_IN : in instruction
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		 *
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		 * The guest read the address register
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		 */
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		set_return_data(vei, pci.pci_addr_reg);
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	}
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}
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uint8_t
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pci_handle_io(struct vm_run_params *vrp)
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{
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	int i, j, k, l;
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	uint16_t reg, b_hi, b_lo;
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	pci_iobar_fn_t fn;
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	union vm_exit *vei = vrp->vrp_exit;
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	uint8_t intr, dir;
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	k = -1;
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	l = -1;
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	reg = vei->vei.vei_port;
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	dir = vei->vei.vei_dir;
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	intr = 0xFF;
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	for (i = 0 ; i < pci.pci_dev_ct ; i++) {
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		for (j = 0 ; j < pci.pci_devices[i].pd_bar_ct; j++) {
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			b_lo = PCI_MAPREG_IO_ADDR(pci.pci_devices[i].pd_bar[j]);
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			b_hi = b_lo + VMM_PCI_IO_BAR_SIZE;
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			if (reg >= b_lo && reg < b_hi) {
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				if (pci.pci_devices[i].pd_barfunc[j]) {
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					k = j;
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					l = i;
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				}
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			}
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		}
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	}
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	if (k >= 0 && l >= 0) {
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		fn = (pci_iobar_fn_t)pci.pci_devices[l].pd_barfunc[k];
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		if (fn(vei->vei.vei_dir, reg -
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		    PCI_MAPREG_IO_ADDR(pci.pci_devices[l].pd_bar[k]),
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		    &vei->vei.vei_data, &intr,
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		    pci.pci_devices[l].pd_bar_cookie[k],
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		    vei->vei.vei_size)) {
283
			log_warnx("%s: pci i/o access function failed",
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			    __progname);
285
		}
286
	} else {
287
		log_warnx("%s: no pci i/o function for reg 0x%llx",
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		    __progname, (uint64_t)reg);
289
		/* Reads from undefined ports return 0xFF */
290
		if (dir == VEI_DIR_IN)
291
			set_return_data(vei, 0xFFFFFFFF);
292
	}
293
294
	if (intr != 0xFF) {
295
		intr = pci.pci_devices[l].pd_irq;
296
	}
297
298
	return (intr);
299
}
300
301
void
302
pci_handle_data_reg(struct vm_run_params *vrp)
303
{
304
	union vm_exit *vei = vrp->vrp_exit;
305
	uint8_t b, d, f, o, baridx, ofs, sz;
306
	int ret;
307
	pci_cs_fn_t csfunc;
308
309
	/* abort if the address register is wack */
310
	if (!(pci.pci_addr_reg & PCI_MODE1_ENABLE)) {
311
		/* if read, return FFs */
312
		if (vei->vei.vei_dir == VEI_DIR_IN)
313
			set_return_data(vei, 0xFFFFFFFF);
314
		log_warnx("invalid address register during pci read: "
315
		    "0x%llx", (uint64_t)pci.pci_addr_reg);
316
		return;
317
	}
318
319
	/* I/Os to 0xCFC..0xCFF are permitted */
320
	ofs = vei->vei.vei_port - 0xCFC;
321
	sz = vei->vei.vei_size;
322
323
	b = (pci.pci_addr_reg >> 16) & 0xff;
324
	d = (pci.pci_addr_reg >> 11) & 0x1f;
325
	f = (pci.pci_addr_reg >> 8) & 0x7;
326
	o = (pci.pci_addr_reg & 0xfc);
327
328
	csfunc = pci.pci_devices[d].pd_csfunc;
329
	if (csfunc != NULL) {
330
		ret = csfunc(vei->vei.vei_dir, (o / 4), &vei->vei.vei_data);
331
		if (ret)
332
			log_warnx("cfg space access function failed for "
333
			    "pci device %d", d);
334
		return;
335
	}
336
337
	/* No config space function, fallback to default simple r/w impl. */
338
339
	o += ofs;
340
341
	/*
342
	 * vei_dir == VEI_DIR_OUT : out instruction
343
	 *
344
	 * The guest wrote to the config space location denoted by the current
345
	 * value in the address register.
346
	 */
347
	if (vei->vei.vei_dir == VEI_DIR_OUT) {
348
		if ((o >= 0x10 && o <= 0x24) &&
349
		    vei->vei.vei_data == 0xffffffff) {
350
			/*
351
			 * Compute BAR index:
352
			 * o = 0x10 -> baridx = 0
353
			 * o = 0x14 -> baridx = 1
354
			 * o = 0x18 -> baridx = 2
355
			 * o = 0x1c -> baridx = 3
356
			 * o = 0x20 -> baridx = 4
357
			 * o = 0x24 -> baridx = 5
358
			 */
359
			baridx = (o / 4) - 4;
360
			if (baridx < pci.pci_devices[d].pd_bar_ct)
361
				vei->vei.vei_data = 0xfffff000;
362
			else
363
				vei->vei.vei_data = 0;
364
		}
365
366
		/* IOBAR registers must have bit 0 set */
367
		if (o >= 0x10 && o <= 0x24) {
368
			baridx = (o / 4) - 4;
369
			if (baridx < pci.pci_devices[d].pd_bar_ct &&
370
			    pci.pci_devices[d].pd_bartype[baridx] ==
371
			    PCI_BAR_TYPE_IO)
372
				vei->vei.vei_data |= 1;
373
		}
374
375
		/*
376
		 * Discard writes to "option rom base address" as none of our
377
		 * emulated devices have PCI option roms. Accept any other
378
		 * writes and copy data to config space registers.
379
		 */
380
		if (o != PCI_EXROMADDR_0)
381
			get_input_data(vei,
382
			    &pci.pci_devices[d].pd_cfg_space[o / 4]);
383
	} else {
384
		/*
385
		 * vei_dir == VEI_DIR_IN : in instruction
386
		 *
387
		 * The guest read from the config space location determined by
388
		 * the current value in the address register.
389
		 */
390
		if (d > pci.pci_dev_ct || b > 0 || f > 0)
391
			set_return_data(vei, 0xFFFFFFFF);
392
		else {
393
			switch (sz) {
394
			case 4:
395
				set_return_data(vei, pci.pci_devices[d].pd_cfg_space[o / 4]);
396
				break;
397
			case 2:
398
				if (ofs == 0)
399
					set_return_data(vei,
400
					    pci.pci_devices[d].pd_cfg_space[o / 4]);
401
				else
402
					set_return_data(vei,
403
					    pci.pci_devices[d].pd_cfg_space[o / 4] >> 16);
404
				break;
405
			case 1:
406
				set_return_data(vei,
407
				    pci.pci_devices[d].pd_cfg_space[o / 4] >> (ofs * 3));
408
				break;
409
			}
410
		}
411
	}
412
}
413
414
int
415
pci_dump(int fd)
416
{
417
	log_debug("%s: sending pci", __func__);
418
	if (atomicio(vwrite, fd, &pci, sizeof(pci)) != sizeof(pci)) {
419
		log_warnx("%s: error writing pci to fd", __func__);
420
		return (-1);
421
	}
422
	return (0);
423
}
424
425
int
426
pci_restore(int fd)
427
{
428
	log_debug("%s: receiving pci", __func__);
429
	if (atomicio(read, fd, &pci, sizeof(pci)) != sizeof(pci)) {
430
		log_warnx("%s: error reading pci from fd", __func__);
431
		return (-1);
432
	}
433
	return (0);
434
}