Line data Source code
1 : /* $OpenBSD: aic79xx.c,v 1.64 2018/02/06 00:18:38 tedu Exp $ */
2 :
3 : /*
4 : * Copyright (c) 2004 Milos Urbanek, Kenneth R. Westerback & Marco Peereboom
5 : * All rights reserved.
6 : *
7 : * Redistribution and use in source and binary forms, with or without
8 : * modification, are permitted provided that the following conditions
9 : * are met:
10 : * 1. Redistributions of source code must retain the above copyright
11 : * notice, this list of conditions and the following disclaimer.
12 : * 2. Redistributions in binary form must reproduce the above copyright
13 : * notice, this list of conditions and the following disclaimer in the
14 : * documentation and/or other materials provided with the distribution.
15 : *
16 : * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
17 : * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 : * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 : * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR
20 : * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 : * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 : * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 : * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 : * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 : * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 : * SUCH DAMAGE.
27 : *
28 : */
29 :
30 : /*
31 : * Core routines and tables shareable across OS platforms.
32 : *
33 : * Copyright (c) 1994-2002, 2004 Justin T. Gibbs.
34 : * Copyright (c) 2000-2003 Adaptec Inc.
35 : * All rights reserved.
36 : *
37 : * Redistribution and use in source and binary forms, with or without
38 : * modification, are permitted provided that the following conditions
39 : * are met:
40 : * 1. Redistributions of source code must retain the above copyright
41 : * notice, this list of conditions, and the following disclaimer,
42 : * without modification.
43 : * 2. Redistributions in binary form must reproduce at minimum a disclaimer
44 : * substantially similar to the "NO WARRANTY" disclaimer below
45 : * ("Disclaimer") and any redistribution must be conditioned upon
46 : * including a substantially similar Disclaimer requirement for further
47 : * binary redistribution.
48 : * 3. Neither the names of the above-listed copyright holders nor the names
49 : * of any contributors may be used to endorse or promote products derived
50 : * from this software without specific prior written permission.
51 : *
52 : * Alternatively, this software may be distributed under the terms of the
53 : * GNU General Public License ("GPL") version 2 as published by the Free
54 : * Software Foundation.
55 : *
56 : * NO WARRANTY
57 : * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
58 : * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59 : * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
60 : * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
61 : * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 : * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
63 : * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
64 : * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
65 : * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
66 : * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
67 : * POSSIBILITY OF SUCH DAMAGES.
68 : *
69 : * Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246
70 : *
71 : * FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.33 2004/11/18 20:22:30 gibbs Exp
72 : */
73 :
74 : #include <dev/ic/aic79xx_openbsd.h>
75 : #include <dev/ic/aic79xx_inline.h>
76 : #include <dev/ic/aic79xx.h>
77 :
78 : #include <dev/microcode/aic7xxx/aicasm_insformat.h>
79 :
80 : /******************************** Globals *************************************/
81 : struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq);
82 : uint32_t ahd_attach_to_HostRAID_controllers = 1;
83 :
84 : /***************************** Lookup Tables **********************************/
85 : char *ahd_chip_names[] =
86 : {
87 : "NONE",
88 : "aic7901",
89 : "aic7902",
90 : "aic7901A"
91 : };
92 :
93 : /*
94 : * Hardware error codes.
95 : */
96 : struct ahd_hard_error_entry {
97 : uint8_t errno;
98 : char *errmesg;
99 : };
100 :
101 : static struct ahd_hard_error_entry ahd_hard_errors[] = {
102 : { DSCTMOUT, "Discard Timer has timed out" },
103 : { ILLOPCODE, "Illegal Opcode in sequencer program" },
104 : { SQPARERR, "Sequencer Parity Error" },
105 : { DPARERR, "Data-path Parity Error" },
106 : { MPARERR, "Scratch or SCB Memory Parity Error" },
107 : { CIOPARERR, "CIOBUS Parity Error" },
108 : };
109 : static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors);
110 :
111 : static struct ahd_phase_table_entry ahd_phase_table[] =
112 : {
113 : { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
114 : { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
115 : { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
116 : { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
117 : { P_COMMAND, MSG_NOOP, "in Command phase" },
118 : { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
119 : { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
120 : { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
121 : { P_BUSFREE, MSG_NOOP, "while idle" },
122 : { 0, MSG_NOOP, "in unknown phase" }
123 : };
124 :
125 : /*
126 : * In most cases we only wish to itterate over real phases, so
127 : * exclude the last element from the count.
128 : */
129 : static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1;
130 :
131 : /* Our Sequencer Program */
132 : #include <dev/microcode/aic7xxx/aic79xx_seq.h>
133 :
134 : /**************************** Function Declarations ***************************/
135 : void ahd_handle_transmission_error(struct ahd_softc *ahd);
136 : void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
137 : u_int lqistat1);
138 : int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
139 : u_int busfreetime);
140 : int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
141 : void ahd_handle_proto_violation(struct ahd_softc *ahd);
142 : void ahd_force_renegotiation(struct ahd_softc *ahd,
143 : struct ahd_devinfo *devinfo);
144 :
145 : struct ahd_tmode_tstate*
146 : ahd_alloc_tstate(struct ahd_softc *ahd,
147 : u_int scsi_id, char channel);
148 : #ifdef AHD_TARGET_MODE
149 : void ahd_free_tstate(struct ahd_softc *ahd,
150 : u_int scsi_id, char channel, int force);
151 : #endif
152 : void ahd_devlimited_syncrate(struct ahd_softc *ahd,
153 : struct ahd_initiator_tinfo *,
154 : u_int *period,
155 : u_int *ppr_options,
156 : role_t role);
157 : void ahd_update_neg_table(struct ahd_softc *ahd,
158 : struct ahd_devinfo *devinfo,
159 : struct ahd_transinfo *tinfo);
160 : void ahd_update_pending_scbs(struct ahd_softc *ahd);
161 : void ahd_fetch_devinfo(struct ahd_softc *ahd,
162 : struct ahd_devinfo *devinfo);
163 : void ahd_scb_devinfo(struct ahd_softc *ahd,
164 : struct ahd_devinfo *devinfo,
165 : struct scb *scb);
166 : void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
167 : struct ahd_devinfo *devinfo,
168 : struct scb *scb);
169 : void ahd_build_transfer_msg(struct ahd_softc *ahd,
170 : struct ahd_devinfo *devinfo);
171 : void ahd_construct_sdtr(struct ahd_softc *ahd,
172 : struct ahd_devinfo *devinfo,
173 : u_int period, u_int offset);
174 : void ahd_construct_wdtr(struct ahd_softc *ahd,
175 : struct ahd_devinfo *devinfo,
176 : u_int bus_width);
177 : void ahd_construct_ppr(struct ahd_softc *ahd,
178 : struct ahd_devinfo *devinfo,
179 : u_int period, u_int offset,
180 : u_int bus_width, u_int ppr_options);
181 : void ahd_clear_msg_state(struct ahd_softc *ahd);
182 : void ahd_handle_message_phase(struct ahd_softc *ahd);
183 : typedef enum {
184 : AHDMSG_1B,
185 : AHDMSG_2B,
186 : AHDMSG_EXT
187 : } ahd_msgtype;
188 : int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
189 : u_int msgval, int full);
190 : int ahd_parse_msg(struct ahd_softc *ahd,
191 : struct ahd_devinfo *devinfo);
192 : int ahd_handle_msg_reject(struct ahd_softc *ahd,
193 : struct ahd_devinfo *devinfo);
194 : void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
195 : struct ahd_devinfo *devinfo);
196 : void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
197 : void ahd_handle_devreset(struct ahd_softc *ahd,
198 : struct ahd_devinfo *devinfo,
199 : u_int lun, cam_status status,
200 : char *message, int verbose_level);
201 : #if AHD_TARGET_MODE
202 : void ahd_setup_target_msgin(struct ahd_softc *ahd,
203 : struct ahd_devinfo *devinfo,
204 : struct scb *scb);
205 : #endif
206 :
207 : u_int ahd_sglist_size(struct ahd_softc *ahd);
208 : u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
209 : void ahd_initialize_hscbs(struct ahd_softc *ahd);
210 : int ahd_init_scbdata(struct ahd_softc *ahd);
211 : struct scb * ahd_find_scb_by_tag(struct ahd_softc *, u_int);
212 : void ahd_fini_scbdata(struct ahd_softc *ahd);
213 : void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
214 : void ahd_iocell_first_selection(struct ahd_softc *ahd);
215 : void ahd_chip_init(struct ahd_softc *ahd);
216 : void ahd_qinfifo_requeue(struct ahd_softc *ahd,
217 : struct scb *prev_scb,
218 : struct scb *scb);
219 : int ahd_qinfifo_count(struct ahd_softc *ahd);
220 : int ahd_search_scb_list(struct ahd_softc *ahd, int target,
221 : char channel, int lun, u_int tag,
222 : role_t role, uint32_t status,
223 : ahd_search_action action,
224 : u_int *list_head, u_int *list_tail,
225 : u_int tid);
226 : void ahd_stitch_tid_list(struct ahd_softc *ahd,
227 : u_int tid_prev, u_int tid_cur,
228 : u_int tid_next);
229 : void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
230 : u_int scbid);
231 : u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
232 : u_int prev, u_int next, u_int tid);
233 : void ahd_reset_current_bus(struct ahd_softc *ahd);
234 : ahd_callback_t ahd_reset_poll;
235 : ahd_callback_t ahd_stat_timer;
236 : #ifdef AHD_DUMP_SEQ
237 : void ahd_dumpseq(struct ahd_softc *ahd);
238 : #endif
239 : void ahd_loadseq(struct ahd_softc *ahd);
240 : int ahd_check_patch(struct ahd_softc *ahd,
241 : const struct patch **start_patch,
242 : u_int start_instr, u_int *skip_addr);
243 : u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
244 : u_int address);
245 : void ahd_download_instr(struct ahd_softc *ahd,
246 : u_int instrptr, uint8_t *dconsts);
247 : int ahd_probe_stack_size(struct ahd_softc *ahd);
248 : int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
249 : struct scb *scb);
250 : void ahd_run_data_fifo(struct ahd_softc *ahd,
251 : struct scb *scb);
252 :
253 : #ifdef AHD_TARGET_MODE
254 : void ahd_queue_lstate_event(struct ahd_softc *ahd,
255 : struct ahd_tmode_lstate *lstate,
256 : u_int initiator_id,
257 : u_int event_type,
258 : u_int event_arg);
259 : void ahd_update_scsiid(struct ahd_softc *ahd,
260 : u_int targid_mask);
261 : int ahd_handle_target_cmd(struct ahd_softc *ahd,
262 : struct target_cmd *cmd);
263 : #endif
264 :
265 : /************************** Added for porting to NetBSD ***********************/
266 : int ahd_createdmamem(struct ahd_softc *, size_t, struct map_node *,
267 : const char *);
268 :
269 : void ahd_freedmamem(struct ahd_softc *, struct map_node *);
270 :
271 : /******************************** Private Inlines *****************************/
272 : __inline void ahd_assert_atn(struct ahd_softc *ahd);
273 : int ahd_currently_packetized(struct ahd_softc *ahd);
274 : int ahd_set_active_fifo(struct ahd_softc *ahd);
275 :
276 : __inline void
277 0 : ahd_assert_atn(struct ahd_softc *ahd)
278 : {
279 0 : ahd_outb(ahd, SCSISIGO, ATNO);
280 0 : }
281 :
282 : /*
283 : * Determine if the current connection has a packetized
284 : * agreement. This does not necessarily mean that we
285 : * are currently in a packetized transfer. We could
286 : * just as easily be sending or receiving a message.
287 : */
288 : int
289 0 : ahd_currently_packetized(struct ahd_softc *ahd)
290 : {
291 : ahd_mode_state saved_modes;
292 : int packetized;
293 :
294 0 : saved_modes = ahd_save_modes(ahd);
295 0 : if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
296 : /*
297 : * The packetized bit refers to the last
298 : * connection, not the current one. Check
299 : * for non-zero LQISTATE instead.
300 : */
301 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
302 0 : packetized = ahd_inb(ahd, LQISTATE) != 0;
303 0 : } else {
304 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
305 0 : packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
306 : }
307 0 : ahd_restore_modes(ahd, saved_modes);
308 0 : return (packetized);
309 : }
310 :
311 : int
312 0 : ahd_set_active_fifo(struct ahd_softc *ahd)
313 : {
314 : u_int active_fifo;
315 :
316 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
317 0 : active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
318 0 : switch (active_fifo) {
319 : case 0:
320 : case 1:
321 0 : ahd_set_modes(ahd, active_fifo, active_fifo);
322 0 : return (1);
323 : default:
324 0 : return (0);
325 : }
326 0 : }
327 :
328 : /************************* Sequencer Execution Control ************************/
329 : /*
330 : * Restart the sequencer program from address zero
331 : */
332 : void
333 0 : ahd_restart(struct ahd_softc *ahd)
334 : {
335 :
336 0 : ahd_pause(ahd);
337 :
338 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
339 :
340 : /* No more pending messages */
341 0 : ahd_clear_msg_state(ahd);
342 0 : ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
343 0 : ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
344 0 : ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
345 0 : ahd_outb(ahd, SEQINTCTL, 0);
346 0 : ahd_outb(ahd, LASTPHASE, P_BUSFREE);
347 0 : ahd_outb(ahd, SEQ_FLAGS, 0);
348 0 : ahd_outb(ahd, SAVED_SCSIID, 0xFF);
349 0 : ahd_outb(ahd, SAVED_LUN, 0xFF);
350 :
351 : /*
352 : * Ensure that the sequencer's idea of TQINPOS
353 : * matches our own. The sequencer increments TQINPOS
354 : * only after it sees a DMA complete and a reset could
355 : * occur before the increment leaving the kernel to believe
356 : * the command arrived but the sequencer to not.
357 : */
358 0 : ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
359 :
360 : /* Always allow reselection */
361 0 : ahd_outb(ahd, SCSISEQ1,
362 : ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
363 0 : ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
364 :
365 : /*
366 : * Clear any pending sequencer interrupt. It is no
367 : * longer relevant since we're resetting the Program
368 : * Counter.
369 : */
370 0 : ahd_outb(ahd, CLRINT, CLRSEQINT);
371 :
372 0 : ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
373 0 : ahd_unpause(ahd);
374 0 : }
375 :
376 : void
377 0 : ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
378 : {
379 : ahd_mode_state saved_modes;
380 :
381 : #ifdef AHD_DEBUG
382 : if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
383 : printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
384 : #endif
385 0 : saved_modes = ahd_save_modes(ahd);
386 0 : ahd_set_modes(ahd, fifo, fifo);
387 0 : ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
388 0 : if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
389 0 : ahd_outb(ahd, CCSGCTL, CCSGRESET);
390 0 : ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
391 0 : ahd_outb(ahd, SG_STATE, 0);
392 0 : ahd_restore_modes(ahd, saved_modes);
393 0 : }
394 :
395 : /************************* Input/Output Queues ********************************/
396 : /*
397 : * Flush and completed commands that are sitting in the command
398 : * complete queues down on the chip but have yet to be dma'ed back up.
399 : */
400 : void
401 0 : ahd_flush_qoutfifo(struct ahd_softc *ahd)
402 : {
403 : struct scb *scb;
404 : ahd_mode_state saved_modes;
405 : u_int saved_scbptr;
406 : u_int ccscbctl;
407 : u_int scbid;
408 : u_int next_scbid;
409 :
410 0 : saved_modes = ahd_save_modes(ahd);
411 :
412 : /*
413 : * Flush the good status FIFO for completed packetized commands.
414 : */
415 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
416 0 : saved_scbptr = ahd_get_scbptr(ahd);
417 0 : while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
418 : u_int fifo_mode;
419 : u_int i;
420 :
421 0 : scbid = ahd_inw(ahd, GSFIFO);
422 0 : scb = ahd_lookup_scb(ahd, scbid);
423 0 : if (scb == NULL) {
424 0 : printf("%s: Warning - GSFIFO SCB %d invalid\n",
425 0 : ahd_name(ahd), scbid);
426 0 : continue;
427 : }
428 : /*
429 : * Determine if this transaction is still active in
430 : * any FIFO. If it is, we must flush that FIFO to
431 : * the host before completing the command.
432 : */
433 0 : fifo_mode = 0;
434 : rescan_fifos:
435 0 : for (i = 0; i < 2; i++) {
436 : /* Toggle to the other mode. */
437 0 : fifo_mode ^= 1;
438 0 : ahd_set_modes(ahd, fifo_mode, fifo_mode);
439 :
440 0 : if (ahd_scb_active_in_fifo(ahd, scb) == 0)
441 : continue;
442 :
443 0 : ahd_run_data_fifo(ahd, scb);
444 :
445 : /*
446 : * Running this FIFO may cause a CFG4DATA for
447 : * this same transaction to assert in the other
448 : * FIFO or a new snapshot SAVEPTRS interrupt
449 : * in this FIFO. Even running a FIFO may not
450 : * clear the transaction if we are still waiting
451 : * for data to drain to the host. We must loop
452 : * until the transaction is not active in either
453 : * FIFO just to be sure. Reset our loop counter
454 : * so we will visit both FIFOs again before
455 : * declaring this transaction finished. We
456 : * also delay a bit so that status has a chance
457 : * to change before we look at this FIFO again.
458 : */
459 0 : aic_delay(200);
460 0 : goto rescan_fifos;
461 : }
462 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
463 0 : ahd_set_scbptr(ahd, scbid);
464 0 : if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
465 0 : && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
466 0 : || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
467 0 : & SG_LIST_NULL) != 0)) {
468 : u_int comp_head;
469 :
470 : /*
471 : * The transfer completed with a residual.
472 : * Place this SCB on the complete DMA list
473 : * so that we update our in-core copy of the
474 : * SCB before completing the command.
475 : */
476 0 : ahd_outb(ahd, SCB_SCSI_STATUS, 0);
477 0 : ahd_outb(ahd, SCB_SGPTR,
478 : ahd_inb_scbram(ahd, SCB_SGPTR)
479 : | SG_STATUS_VALID);
480 0 : ahd_outw(ahd, SCB_TAG, scbid);
481 0 : ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
482 0 : comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
483 0 : if (SCBID_IS_NULL(comp_head)) {
484 0 : ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
485 0 : ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
486 0 : } else {
487 : u_int tail;
488 :
489 0 : tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
490 0 : ahd_set_scbptr(ahd, tail);
491 0 : ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
492 0 : ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
493 0 : ahd_set_scbptr(ahd, scbid);
494 : }
495 0 : } else
496 0 : ahd_complete_scb(ahd, scb);
497 0 : }
498 0 : ahd_set_scbptr(ahd, saved_scbptr);
499 :
500 : /*
501 : * Setup for command channel portion of flush.
502 : */
503 0 : ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
504 :
505 : /*
506 : * Wait for any inprogress DMA to complete and clear DMA state
507 : * if this if for an SCB in the qinfifo.
508 : */
509 0 : while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
510 :
511 0 : if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
512 0 : if ((ccscbctl & ARRDONE) != 0)
513 : break;
514 0 : } else if ((ccscbctl & CCSCBDONE) != 0)
515 : break;
516 0 : aic_delay(200);
517 : }
518 : /*
519 : * We leave the sequencer to cleanup in the case of DMA's to
520 : * update the qoutfifo. In all other cases (DMA's to the
521 : * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
522 : * we disable the DMA engine so that the sequencer will not
523 : * attempt to handle the DMA completion.
524 : */
525 0 : if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
526 0 : ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
527 :
528 : /*
529 : * Complete any SCBs that just finished
530 : * being DMA'ed into the qoutfifo.
531 : */
532 0 : ahd_run_qoutfifo(ahd);
533 :
534 0 : saved_scbptr = ahd_get_scbptr(ahd);
535 : /*
536 : * Manually update/complete any completed SCBs that are waiting to be
537 : * DMA'ed back up to the host.
538 : */
539 0 : scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
540 0 : while (!SCBID_IS_NULL(scbid)) {
541 : uint8_t *hscb_ptr;
542 : u_int i;
543 :
544 0 : ahd_set_scbptr(ahd, scbid);
545 0 : next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
546 0 : scb = ahd_lookup_scb(ahd, scbid);
547 0 : if (scb == NULL) {
548 0 : printf("%s: Warning - DMA-up and complete "
549 0 : "SCB %d invalid\n", ahd_name(ahd), scbid);
550 0 : continue;
551 : }
552 0 : hscb_ptr = (uint8_t *)scb->hscb;
553 0 : for (i = 0; i < sizeof(struct hardware_scb); i++)
554 0 : *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
555 :
556 0 : ahd_complete_scb(ahd, scb);
557 : scbid = next_scbid;
558 0 : }
559 0 : ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
560 0 : ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
561 :
562 0 : scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
563 0 : while (!SCBID_IS_NULL(scbid)) {
564 :
565 0 : ahd_set_scbptr(ahd, scbid);
566 0 : next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
567 0 : scb = ahd_lookup_scb(ahd, scbid);
568 0 : if (scb == NULL) {
569 0 : printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
570 0 : ahd_name(ahd), scbid);
571 0 : continue;
572 : }
573 :
574 0 : ahd_complete_scb(ahd, scb);
575 : scbid = next_scbid;
576 : }
577 0 : ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
578 :
579 0 : scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
580 0 : while (!SCBID_IS_NULL(scbid)) {
581 :
582 0 : ahd_set_scbptr(ahd, scbid);
583 0 : next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
584 0 : scb = ahd_lookup_scb(ahd, scbid);
585 0 : if (scb == NULL) {
586 0 : printf("%s: Warning - Complete SCB %d invalid\n",
587 0 : ahd_name(ahd), scbid);
588 0 : continue;
589 : }
590 :
591 0 : ahd_complete_scb(ahd, scb);
592 : scbid = next_scbid;
593 : }
594 0 : ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
595 :
596 : /*
597 : * Restore state.
598 : */
599 0 : ahd_set_scbptr(ahd, saved_scbptr);
600 0 : ahd_restore_modes(ahd, saved_modes);
601 0 : ahd->flags |= AHD_UPDATE_PEND_CMDS;
602 0 : }
603 :
604 : /*
605 : * Determine if an SCB for a packetized transaction
606 : * is active in a FIFO.
607 : */
608 : int
609 0 : ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
610 : {
611 :
612 : /*
613 : * The FIFO is only active for our transaction if
614 : * the SCBPTR matches the SCB's ID and the firmware
615 : * has installed a handler for the FIFO or we have
616 : * a pending SAVEPTRS or CFG4DATA interrupt.
617 : */
618 0 : if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
619 0 : || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
620 0 : && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
621 0 : return (0);
622 :
623 0 : return (1);
624 0 : }
625 :
626 : /*
627 : * Run a data fifo to completion for a transaction we know
628 : * has completed across the SCSI bus (good status has been
629 : * received). We are already set to the correct FIFO mode
630 : * on entry to this routine.
631 : *
632 : * This function attempts to operate exactly as the firmware
633 : * would when running this FIFO. Care must be taken to update
634 : * this routine any time the firmware's FIFO algorithm is
635 : * changed.
636 : */
637 : void
638 0 : ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
639 : {
640 : u_int seqintsrc;
641 :
642 0 : seqintsrc = ahd_inb(ahd, SEQINTSRC);
643 0 : if ((seqintsrc & CFG4DATA) != 0) {
644 : uint32_t datacnt;
645 : uint32_t sgptr;
646 :
647 : /*
648 : * Clear full residual flag.
649 : */
650 0 : sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
651 0 : ahd_outb(ahd, SCB_SGPTR, sgptr);
652 :
653 : /*
654 : * Load datacnt and address.
655 : */
656 0 : datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
657 0 : if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
658 0 : sgptr |= LAST_SEG;
659 0 : ahd_outb(ahd, SG_STATE, 0);
660 0 : } else
661 0 : ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
662 0 : ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
663 0 : ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
664 0 : ahd_outb(ahd, SG_CACHE_PRE, sgptr);
665 0 : ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
666 :
667 : /*
668 : * Initialize Residual Fields.
669 : */
670 0 : ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
671 0 : ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
672 :
673 : /*
674 : * Mark the SCB as having a FIFO in use.
675 : */
676 0 : ahd_outb(ahd, SCB_FIFO_USE_COUNT,
677 : ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
678 :
679 : /*
680 : * Install a "fake" handler for this FIFO.
681 : */
682 0 : ahd_outw(ahd, LONGJMP_ADDR, 0);
683 :
684 : /*
685 : * Notify the hardware that we have satisfied
686 : * this sequencer interrupt.
687 : */
688 0 : ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
689 0 : } else if ((seqintsrc & SAVEPTRS) != 0) {
690 : uint32_t sgptr;
691 : uint32_t resid;
692 :
693 0 : if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
694 : /*
695 : * Snapshot Save Pointers. All that
696 : * is necessary to clear the snapshot
697 : * is a CLRCHN.
698 : */
699 0 : goto clrchn;
700 : }
701 :
702 : /*
703 : * Disable S/G fetch so the DMA engine
704 : * is available to future users.
705 : */
706 0 : if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
707 0 : ahd_outb(ahd, CCSGCTL, 0);
708 0 : ahd_outb(ahd, SG_STATE, 0);
709 :
710 : /*
711 : * Flush the data FIFO. Strickly only
712 : * necessary for Rev A parts.
713 : */
714 0 : ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
715 :
716 : /*
717 : * Calculate residual.
718 : */
719 0 : sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
720 0 : resid = ahd_inl(ahd, SHCNT);
721 0 : resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
722 0 : ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
723 0 : if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
724 : /*
725 : * Must back up to the correct S/G element.
726 : * Typically this just means resetting our
727 : * low byte to the offset in the SG_CACHE,
728 : * but if we wrapped, we have to correct
729 : * the other bytes of the sgptr too.
730 : */
731 0 : if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
732 0 : && (sgptr & 0x80) == 0)
733 0 : sgptr -= 0x100;
734 0 : sgptr &= ~0xFF;
735 0 : sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
736 0 : & SG_ADDR_MASK;
737 0 : ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
738 0 : ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
739 0 : } else if ((resid & AHD_SG_LEN_MASK) == 0) {
740 0 : ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
741 : sgptr | SG_LIST_NULL);
742 0 : }
743 : /*
744 : * Save Pointers.
745 : */
746 0 : ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
747 0 : ahd_outl(ahd, SCB_DATACNT, resid);
748 0 : ahd_outl(ahd, SCB_SGPTR, sgptr);
749 0 : ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
750 0 : ahd_outb(ahd, SEQIMODE,
751 : ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
752 : /*
753 : * If the data is to the SCSI bus, we are
754 : * done, otherwise wait for FIFOEMP.
755 : */
756 0 : if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
757 0 : goto clrchn;
758 0 : } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
759 : uint32_t sgptr;
760 : uint64_t data_addr;
761 : uint32_t data_len;
762 : u_int dfcntrl;
763 :
764 : /*
765 : * Disable S/G fetch so the DMA engine
766 : * is available to future users. We won't
767 : * be using the DMA engine to load segments.
768 : */
769 0 : if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
770 0 : ahd_outb(ahd, CCSGCTL, 0);
771 0 : ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
772 0 : }
773 :
774 : /*
775 : * Wait for the DMA engine to notice that the
776 : * host transfer is enabled and that there is
777 : * space in the S/G FIFO for new segments before
778 : * loading more segments.
779 : */
780 0 : if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
781 0 : && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
782 :
783 : /*
784 : * Determine the offset of the next S/G
785 : * element to load.
786 : */
787 0 : sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
788 0 : sgptr &= SG_PTR_MASK;
789 0 : if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
790 : struct ahd_dma64_seg *sg;
791 :
792 0 : sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
793 0 : data_addr = sg->addr;
794 0 : data_len = sg->len;
795 0 : sgptr += sizeof(*sg);
796 0 : } else {
797 : struct ahd_dma_seg *sg;
798 :
799 0 : sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
800 0 : data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
801 0 : data_addr <<= 8;
802 0 : data_addr |= sg->addr;
803 : data_len = sg->len;
804 0 : sgptr += sizeof(*sg);
805 : }
806 :
807 : /*
808 : * Update residual information.
809 : */
810 0 : ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
811 0 : ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
812 :
813 : /*
814 : * Load the S/G.
815 : */
816 0 : if (data_len & AHD_DMA_LAST_SEG) {
817 0 : sgptr |= LAST_SEG;
818 0 : ahd_outb(ahd, SG_STATE, 0);
819 0 : }
820 0 : ahd_outq(ahd, HADDR, data_addr);
821 0 : ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
822 0 : ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
823 :
824 : /*
825 : * Advertise the segment to the hardware.
826 : */
827 0 : dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
828 0 : if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
829 : /*
830 : * Use SCSIENWRDIS so that SCSIEN
831 : * is never modified by this
832 : * operation.
833 : */
834 0 : dfcntrl |= SCSIENWRDIS;
835 0 : }
836 0 : ahd_outb(ahd, DFCNTRL, dfcntrl);
837 0 : }
838 0 : } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
839 :
840 : /*
841 : * Transfer completed to the end of SG list
842 : * and has flushed to the host.
843 : */
844 0 : ahd_outb(ahd, SCB_SGPTR,
845 : ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
846 0 : goto clrchn;
847 0 : } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
848 : clrchn:
849 : /*
850 : * Clear any handler for this FIFO, decrement
851 : * the FIFO use count for the SCB, and release
852 : * the FIFO.
853 : */
854 0 : ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
855 0 : ahd_outb(ahd, SCB_FIFO_USE_COUNT,
856 : ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
857 0 : ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
858 0 : }
859 0 : }
860 :
861 : /*
862 : * Look for entries in the QoutFIFO that have completed.
863 : * The valid_tag completion field indicates the validity
864 : * of the entry - the valid value toggles each time through
865 : * the queue. We use the sg_status field in the completion
866 : * entry to avoid referencing the hscb if the completion
867 : * occurred with no errors and no residual. sg_status is
868 : * a copy of the first byte (little endian) of the sgptr
869 : * hscb field.
870 : */
871 : void
872 0 : ahd_run_qoutfifo(struct ahd_softc *ahd)
873 : {
874 : struct ahd_completion *completion;
875 : struct scb *scb;
876 : u_int scb_index;
877 :
878 0 : if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
879 0 : panic("ahd_run_qoutfifo recursion");
880 0 : ahd->flags |= AHD_RUNNING_QOUTFIFO;
881 0 : ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
882 0 : for (;;) {
883 0 : completion = &ahd->qoutfifo[ahd->qoutfifonext];
884 :
885 0 : if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
886 : break;
887 :
888 0 : scb_index = aic_le16toh(completion->tag);
889 0 : scb = ahd_lookup_scb(ahd, scb_index);
890 0 : if (scb == NULL) {
891 0 : printf("%s: WARNING no command for scb %d "
892 : "(cmdcmplt)\nQOUTPOS = %d\n",
893 0 : ahd_name(ahd), scb_index,
894 0 : ahd->qoutfifonext);
895 0 : ahd_dump_card_state(ahd);
896 0 : } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
897 0 : ahd_handle_scb_status(ahd, scb);
898 0 : } else {
899 0 : ahd_done(ahd, scb);
900 : }
901 :
902 0 : ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
903 0 : if (ahd->qoutfifonext == 0)
904 0 : ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
905 : }
906 0 : ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
907 0 : }
908 :
909 : /************************* Interrupt Handling *********************************/
910 : void
911 0 : ahd_handle_hwerrint(struct ahd_softc *ahd)
912 : {
913 : /*
914 : * Some catastrophic hardware error has occurred.
915 : * Print it for the user and disable the controller.
916 : */
917 : int i;
918 : int error;
919 :
920 0 : error = ahd_inb(ahd, ERROR);
921 0 : for (i = 0; i < num_errors; i++) {
922 0 : if ((error & ahd_hard_errors[i].errno) != 0)
923 0 : printf("%s: hwerrint, %s\n",
924 0 : ahd_name(ahd), ahd_hard_errors[i].errmesg);
925 : }
926 :
927 0 : ahd_dump_card_state(ahd);
928 0 : panic("BRKADRINT");
929 :
930 : /* Tell everyone that this HBA is no longer available */
931 : ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
932 : CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
933 : CAM_NO_HBA);
934 :
935 : /* Tell the system that this controller has gone away. */
936 : ahd_free(ahd);
937 : }
938 :
939 : void
940 0 : ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
941 : {
942 : u_int seqintcode;
943 :
944 : /*
945 : * Save the sequencer interrupt code and clear the SEQINT
946 : * bit. We will unpause the sequencer, if appropriate,
947 : * after servicing the request.
948 : */
949 0 : seqintcode = ahd_inb(ahd, SEQINTCODE);
950 0 : ahd_outb(ahd, CLRINT, CLRSEQINT);
951 0 : if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
952 : /*
953 : * Unpause the sequencer and let it clear
954 : * SEQINT by writing NO_SEQINT to it. This
955 : * will cause the sequencer to be paused again,
956 : * which is the expected state of this routine.
957 : */
958 0 : ahd_unpause(ahd);
959 0 : while (!ahd_is_paused(ahd))
960 : ;
961 0 : ahd_outb(ahd, CLRINT, CLRSEQINT);
962 0 : }
963 0 : ahd_update_modes(ahd);
964 : #ifdef AHD_DEBUG
965 : if ((ahd_debug & AHD_SHOW_MISC) != 0)
966 : printf("%s: Handle Seqint Called for code %d\n",
967 : ahd_name(ahd), seqintcode);
968 : #endif
969 0 : switch (seqintcode) {
970 : case ENTERING_NONPACK:
971 : {
972 : struct scb *scb;
973 : u_int scbid;
974 :
975 0 : AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
976 : ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
977 0 : scbid = ahd_get_scbptr(ahd);
978 0 : scb = ahd_lookup_scb(ahd, scbid);
979 0 : if (scb == NULL) {
980 : /*
981 : * Somehow need to know if this
982 : * is from a selection or reselection.
983 : * From that, we can determine target
984 : * ID so we at least have an I_T nexus.
985 : */
986 : } else {
987 0 : ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
988 0 : ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
989 0 : ahd_outb(ahd, SEQ_FLAGS, 0x0);
990 : }
991 0 : if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
992 0 : && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
993 : /*
994 : * Phase change after read stream with
995 : * CRC error with P0 asserted on last
996 : * packet.
997 : */
998 : #ifdef AHD_DEBUG
999 : if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
1000 : printf("%s: Assuming LQIPHASE_NLQ with "
1001 : "P0 assertion\n", ahd_name(ahd));
1002 : #endif
1003 : }
1004 : #ifdef AHD_DEBUG
1005 : if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
1006 : printf("%s: Entering NONPACK\n", ahd_name(ahd));
1007 : #endif
1008 : break;
1009 : }
1010 : case INVALID_SEQINT:
1011 0 : printf("%s: Invalid Sequencer interrupt occurred.\n",
1012 0 : ahd_name(ahd));
1013 0 : ahd_dump_card_state(ahd);
1014 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1015 0 : break;
1016 : case STATUS_OVERRUN:
1017 : {
1018 : struct scb *scb;
1019 : u_int scbid;
1020 :
1021 0 : scbid = ahd_get_scbptr(ahd);
1022 0 : scb = ahd_lookup_scb(ahd, scbid);
1023 0 : if (scb != NULL)
1024 0 : ahd_print_path(ahd, scb);
1025 : else
1026 0 : printf("%s: ", ahd_name(ahd));
1027 0 : printf("SCB %d Packetized Status Overrun", scbid);
1028 0 : ahd_dump_card_state(ahd);
1029 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1030 : break;
1031 : }
1032 : case CFG4ISTAT_INTR:
1033 : {
1034 : struct scb *scb;
1035 : u_int scbid;
1036 :
1037 0 : scbid = ahd_get_scbptr(ahd);
1038 0 : scb = ahd_lookup_scb(ahd, scbid);
1039 0 : if (scb == NULL) {
1040 0 : ahd_dump_card_state(ahd);
1041 0 : printf("CFG4ISTAT: Free SCB %d referenced", scbid);
1042 0 : panic("For safety");
1043 : }
1044 0 : ahd_outq(ahd, HADDR, scb->sense_busaddr);
1045 0 : ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
1046 0 : ahd_outb(ahd, HCNT + 2, 0);
1047 0 : ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
1048 0 : ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
1049 : break;
1050 : }
1051 : case ILLEGAL_PHASE:
1052 : {
1053 : u_int bus_phase;
1054 :
1055 0 : bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1056 0 : printf("%s: ILLEGAL_PHASE 0x%x\n",
1057 0 : ahd_name(ahd), bus_phase);
1058 :
1059 0 : switch (bus_phase) {
1060 : case P_DATAOUT:
1061 : case P_DATAIN:
1062 : case P_DATAOUT_DT:
1063 : case P_DATAIN_DT:
1064 : case P_MESGOUT:
1065 : case P_STATUS:
1066 : case P_MESGIN:
1067 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1068 0 : printf("%s: Issued Bus Reset.\n", ahd_name(ahd));
1069 0 : break;
1070 : case P_COMMAND:
1071 : {
1072 0 : struct ahd_devinfo devinfo;
1073 : struct scb *scb;
1074 : struct ahd_initiator_tinfo *targ_info;
1075 0 : struct ahd_tmode_tstate *tstate;
1076 : u_int scbid;
1077 :
1078 : /*
1079 : * If a target takes us into the command phase
1080 : * assume that it has been externally reset and
1081 : * has thus lost our previous packetized negotiation
1082 : * agreement. Since we have not sent an identify
1083 : * message and may not have fully qualified the
1084 : * connection, we change our command to TUR, assert
1085 : * ATN and ABORT the task when we go to message in
1086 : * phase. The OSM will see the REQUEUE_REQUEST
1087 : * status and retry the command.
1088 : */
1089 0 : scbid = ahd_get_scbptr(ahd);
1090 0 : scb = ahd_lookup_scb(ahd, scbid);
1091 0 : if (scb == NULL) {
1092 0 : printf("Invalid phase with no valid SCB. "
1093 : "Resetting bus.\n");
1094 0 : ahd_reset_channel(ahd, 'A',
1095 : /*Initiate Reset*/TRUE);
1096 0 : break;
1097 : }
1098 0 : ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1099 0 : SCB_GET_TARGET(ahd, scb),
1100 0 : SCB_GET_LUN(scb),
1101 : SCB_GET_CHANNEL(ahd, scb),
1102 : ROLE_INITIATOR);
1103 0 : targ_info = ahd_fetch_transinfo(ahd,
1104 0 : devinfo.channel,
1105 0 : devinfo.our_scsiid,
1106 0 : devinfo.target,
1107 : &tstate);
1108 0 : ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1109 : AHD_TRANS_ACTIVE, /*paused*/TRUE);
1110 0 : ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1111 : /*offset*/0, /*ppr_options*/0,
1112 : AHD_TRANS_ACTIVE, /*paused*/TRUE);
1113 0 : ahd_outb(ahd, SCB_CDB_STORE, 0);
1114 0 : ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1115 0 : ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1116 0 : ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1117 0 : ahd_outb(ahd, SCB_CDB_STORE+4, 0);
1118 0 : ahd_outb(ahd, SCB_CDB_STORE+5, 0);
1119 0 : ahd_outb(ahd, SCB_CDB_LEN, 6);
1120 0 : scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1121 0 : scb->hscb->control |= MK_MESSAGE;
1122 0 : ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
1123 0 : ahd_outb(ahd, MSG_OUT, HOST_MSG);
1124 0 : ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1125 : /*
1126 : * The lun is 0, regardless of the SCB's lun
1127 : * as we have not sent an identify message.
1128 : */
1129 0 : ahd_outb(ahd, SAVED_LUN, 0);
1130 0 : ahd_outb(ahd, SEQ_FLAGS, 0);
1131 0 : ahd_assert_atn(ahd);
1132 0 : scb->flags &= ~SCB_PACKETIZED;
1133 0 : scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1134 0 : ahd_freeze_devq(ahd, scb);
1135 0 : aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
1136 : aic_freeze_scb(scb);
1137 :
1138 : /*
1139 : * Allow the sequencer to continue with
1140 : * non-pack processing.
1141 : */
1142 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1143 0 : ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1144 0 : if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1145 0 : ahd_outb(ahd, CLRLQOINT1, 0);
1146 0 : }
1147 : #ifdef AHD_DEBUG
1148 : if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1149 : ahd_print_path(ahd, scb);
1150 : printf("Unexpected command phase from "
1151 : "packetized target\n");
1152 : }
1153 : #endif
1154 0 : break;
1155 0 : }
1156 : }
1157 : break;
1158 : }
1159 : case CFG4OVERRUN:
1160 : {
1161 : struct scb *scb;
1162 : u_int scb_index;
1163 :
1164 : #ifdef AHD_DEBUG
1165 : if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1166 : printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1167 : ahd_inb(ahd, MODE_PTR));
1168 : }
1169 : #endif
1170 0 : scb_index = ahd_get_scbptr(ahd);
1171 0 : scb = ahd_lookup_scb(ahd, scb_index);
1172 0 : if (scb == NULL) {
1173 : /*
1174 : * Attempt to transfer to an SCB that is
1175 : * not outstanding.
1176 : */
1177 0 : ahd_assert_atn(ahd);
1178 0 : ahd_outb(ahd, MSG_OUT, HOST_MSG);
1179 0 : ahd->msgout_buf[0] = MSG_ABORT_TASK;
1180 0 : ahd->msgout_len = 1;
1181 0 : ahd->msgout_index = 0;
1182 0 : ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1183 : /*
1184 : * Clear status received flag to prevent any
1185 : * attempt to complete this bogus SCB.
1186 : */
1187 0 : ahd_outb(ahd, SCB_CONTROL,
1188 : ahd_inb_scbram(ahd, SCB_CONTROL)
1189 : & ~STATUS_RCVD);
1190 0 : }
1191 : break;
1192 : }
1193 : case DUMP_CARD_STATE:
1194 : {
1195 0 : ahd_dump_card_state(ahd);
1196 0 : break;
1197 : }
1198 : case PDATA_REINIT:
1199 : {
1200 : #ifdef AHD_DEBUG
1201 : if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1202 : printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1203 : "SG_CACHE_SHADOW = 0x%x\n",
1204 : ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1205 : ahd_inb(ahd, SG_CACHE_SHADOW));
1206 : }
1207 : #endif
1208 0 : ahd_reinitialize_dataptrs(ahd);
1209 0 : break;
1210 : }
1211 : case HOST_MSG_LOOP:
1212 : {
1213 0 : struct ahd_devinfo devinfo;
1214 :
1215 : /*
1216 : * The sequencer has encountered a message phase
1217 : * that requires host assistance for completion.
1218 : * While handling the message phase(s), we will be
1219 : * notified by the sequencer after each byte is
1220 : * transferred so we can track bus phase changes.
1221 : *
1222 : * If this is the first time we've seen a HOST_MSG_LOOP
1223 : * interrupt, initialize the state of the host message
1224 : * loop.
1225 : */
1226 0 : ahd_fetch_devinfo(ahd, &devinfo);
1227 0 : if (ahd->msg_type == MSG_TYPE_NONE) {
1228 : struct scb *scb;
1229 : u_int scb_index;
1230 : u_int bus_phase;
1231 :
1232 0 : bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1233 0 : if (bus_phase != P_MESGIN
1234 0 : && bus_phase != P_MESGOUT) {
1235 0 : printf("ahd_intr: HOST_MSG_LOOP bad "
1236 : "phase 0x%x\n", bus_phase);
1237 : /*
1238 : * Probably transitioned to bus free before
1239 : * we got here. Just punt the message.
1240 : */
1241 0 : ahd_dump_card_state(ahd);
1242 0 : ahd_clear_intstat(ahd);
1243 0 : ahd_restart(ahd);
1244 0 : return;
1245 : }
1246 :
1247 0 : scb_index = ahd_get_scbptr(ahd);
1248 0 : scb = ahd_lookup_scb(ahd, scb_index);
1249 0 : if (devinfo.role == ROLE_INITIATOR) {
1250 0 : if (bus_phase == P_MESGOUT)
1251 0 : ahd_setup_initiator_msgout(ahd,
1252 : &devinfo,
1253 : scb);
1254 : else {
1255 0 : ahd->msg_type =
1256 : MSG_TYPE_INITIATOR_MSGIN;
1257 0 : ahd->msgin_index = 0;
1258 : }
1259 : }
1260 : #if AHD_TARGET_MODE
1261 : else {
1262 : if (bus_phase == P_MESGOUT) {
1263 : ahd->msg_type =
1264 : MSG_TYPE_TARGET_MSGOUT;
1265 : ahd->msgin_index = 0;
1266 : }
1267 : else
1268 : ahd_setup_target_msgin(ahd,
1269 : &devinfo,
1270 : scb);
1271 : }
1272 : #endif
1273 0 : }
1274 :
1275 0 : ahd_handle_message_phase(ahd);
1276 0 : break;
1277 0 : }
1278 : case NO_MATCH:
1279 : {
1280 : /* Ensure we don't leave the selection hardware on */
1281 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1282 0 : ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1283 :
1284 0 : printf("%s:%c:%d: no active SCB for reconnecting "
1285 : "target - issuing BUS DEVICE RESET\n",
1286 0 : ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
1287 0 : printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1288 : "REG0 == 0x%x ACCUM = 0x%x\n",
1289 0 : ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1290 0 : ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
1291 0 : printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1292 : "SINDEX == 0x%x\n",
1293 0 : ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1294 0 : ahd_find_busy_tcl(ahd,
1295 0 : BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1296 : ahd_inb(ahd, SAVED_LUN))),
1297 0 : ahd_inw(ahd, SINDEX));
1298 0 : printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1299 : "SCB_CONTROL == 0x%x\n",
1300 0 : ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1301 0 : ahd_inb_scbram(ahd, SCB_LUN),
1302 0 : ahd_inb_scbram(ahd, SCB_CONTROL));
1303 0 : printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1304 0 : ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1305 0 : printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
1306 0 : printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
1307 0 : ahd_dump_card_state(ahd);
1308 0 : ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
1309 0 : ahd->msgout_len = 1;
1310 0 : ahd->msgout_index = 0;
1311 0 : ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1312 0 : ahd_outb(ahd, MSG_OUT, HOST_MSG);
1313 0 : ahd_assert_atn(ahd);
1314 0 : break;
1315 : }
1316 : case PROTO_VIOLATION:
1317 : {
1318 0 : ahd_handle_proto_violation(ahd);
1319 0 : break;
1320 : }
1321 : case IGN_WIDE_RES:
1322 : {
1323 0 : struct ahd_devinfo devinfo;
1324 :
1325 0 : ahd_fetch_devinfo(ahd, &devinfo);
1326 0 : ahd_handle_ign_wide_residue(ahd, &devinfo);
1327 : break;
1328 0 : }
1329 : case BAD_PHASE:
1330 : {
1331 : u_int lastphase;
1332 :
1333 0 : lastphase = ahd_inb(ahd, LASTPHASE);
1334 0 : printf("%s:%c:%d: unknown scsi bus phase %x, "
1335 : "lastphase = 0x%x. Attempting to continue\n",
1336 0 : ahd_name(ahd), 'A',
1337 0 : SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1338 0 : lastphase, ahd_inb(ahd, SCSISIGI));
1339 : break;
1340 : }
1341 : case MISSED_BUSFREE:
1342 : {
1343 : u_int lastphase;
1344 :
1345 0 : lastphase = ahd_inb(ahd, LASTPHASE);
1346 0 : printf("%s:%c:%d: Missed busfree. "
1347 : "Lastphase = 0x%x, Curphase = 0x%x\n",
1348 0 : ahd_name(ahd), 'A',
1349 0 : SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1350 0 : lastphase, ahd_inb(ahd, SCSISIGI));
1351 0 : ahd_restart(ahd);
1352 : return;
1353 : }
1354 : case DATA_OVERRUN:
1355 : {
1356 : /*
1357 : * When the sequencer detects an overrun, it
1358 : * places the controller in "BITBUCKET" mode
1359 : * and allows the target to complete its transfer.
1360 : * Unfortunately, none of the counters get updated
1361 : * when the controller is in this mode, so we have
1362 : * no way of knowing how large the overrun was.
1363 : */
1364 : struct scb *scb;
1365 : u_int scbindex;
1366 : #ifdef AHD_DEBUG
1367 : u_int lastphase;
1368 : #endif
1369 :
1370 0 : scbindex = ahd_get_scbptr(ahd);
1371 0 : scb = ahd_lookup_scb(ahd, scbindex);
1372 : #ifdef AHD_DEBUG
1373 : lastphase = ahd_inb(ahd, LASTPHASE);
1374 : if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1375 : ahd_print_path(ahd, scb);
1376 : printf("data overrun detected %s. Tag == 0x%x.\n",
1377 : ahd_lookup_phase_entry(lastphase)->phasemsg,
1378 : SCB_GET_TAG(scb));
1379 : ahd_print_path(ahd, scb);
1380 : printf("%s seen Data Phase. Length = %ld. "
1381 : "NumSGs = %d.\n",
1382 : ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1383 : ? "Have" : "Haven't",
1384 : aic_get_transfer_length(scb), scb->sg_count);
1385 : ahd_dump_sglist(scb);
1386 : }
1387 : #endif
1388 :
1389 : /*
1390 : * Set this and it will take effect when the
1391 : * target does a command complete.
1392 : */
1393 0 : ahd_freeze_devq(ahd, scb);
1394 0 : aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1395 : aic_freeze_scb(scb);
1396 : break;
1397 : }
1398 : case MKMSG_FAILED:
1399 : {
1400 0 : struct ahd_devinfo devinfo;
1401 : struct scb *scb;
1402 : u_int scbid;
1403 :
1404 0 : ahd_fetch_devinfo(ahd, &devinfo);
1405 0 : printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1406 0 : ahd_name(ahd), devinfo.channel, devinfo.target,
1407 0 : devinfo.lun);
1408 0 : scbid = ahd_get_scbptr(ahd);
1409 0 : scb = ahd_lookup_scb(ahd, scbid);
1410 0 : if (scb != NULL)
1411 : /*
1412 : * Ensure that we didn't put a second instance of this
1413 : * SCB into the QINFIFO.
1414 : */
1415 0 : ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1416 : SCB_GET_CHANNEL(ahd, scb),
1417 0 : SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1418 : ROLE_INITIATOR, /*status*/0,
1419 : SEARCH_REMOVE);
1420 0 : ahd_outb(ahd, SCB_CONTROL,
1421 : ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1422 : break;
1423 0 : }
1424 : case TASKMGMT_FUNC_COMPLETE:
1425 : {
1426 : u_int scbid;
1427 : struct scb *scb;
1428 :
1429 0 : scbid = ahd_get_scbptr(ahd);
1430 0 : scb = ahd_lookup_scb(ahd, scbid);
1431 0 : if (scb != NULL) {
1432 : u_int lun;
1433 : u_int tag;
1434 : cam_status error;
1435 :
1436 0 : ahd_print_path(ahd, scb);
1437 0 : printf("Task Management Func 0x%x Complete\n",
1438 0 : scb->hscb->task_management);
1439 : lun = CAM_LUN_WILDCARD;
1440 : tag = SCB_LIST_NULL;
1441 :
1442 0 : switch (scb->hscb->task_management) {
1443 : case SIU_TASKMGMT_ABORT_TASK:
1444 0 : tag = SCB_GET_TAG(scb);
1445 : case SIU_TASKMGMT_ABORT_TASK_SET:
1446 : case SIU_TASKMGMT_CLEAR_TASK_SET:
1447 0 : lun = scb->hscb->lun;
1448 : error = CAM_REQ_ABORTED;
1449 0 : ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1450 : 'A', lun, tag, ROLE_INITIATOR,
1451 : error);
1452 0 : break;
1453 : case SIU_TASKMGMT_LUN_RESET:
1454 0 : lun = scb->hscb->lun;
1455 : case SIU_TASKMGMT_TARGET_RESET:
1456 : {
1457 0 : struct ahd_devinfo devinfo;
1458 :
1459 0 : ahd_scb_devinfo(ahd, &devinfo, scb);
1460 : error = CAM_BDR_SENT;
1461 0 : ahd_handle_devreset(ahd, &devinfo, lun,
1462 : CAM_BDR_SENT,
1463 0 : lun != CAM_LUN_WILDCARD
1464 : ? "Lun Reset"
1465 : : "Target Reset",
1466 : /*verbose_level*/0);
1467 : break;
1468 0 : }
1469 : default:
1470 0 : panic("Unexpected TaskMgmt Func");
1471 : break;
1472 : }
1473 0 : }
1474 : break;
1475 : }
1476 : case TASKMGMT_CMD_CMPLT_OKAY:
1477 : {
1478 : u_int scbid;
1479 : struct scb *scb;
1480 :
1481 : /*
1482 : * An ABORT TASK TMF failed to be delivered before
1483 : * the targeted command completed normally.
1484 : */
1485 0 : scbid = ahd_get_scbptr(ahd);
1486 0 : scb = ahd_lookup_scb(ahd, scbid);
1487 0 : if (scb != NULL) {
1488 : /*
1489 : * Remove the second instance of this SCB from
1490 : * the QINFIFO if it is still there.
1491 : */
1492 0 : ahd_print_path(ahd, scb);
1493 0 : printf("SCB completes before TMF\n");
1494 : /*
1495 : * Handle losing the race. Wait until any
1496 : * current selection completes. We will then
1497 : * set the TMF back to zero in this SCB so that
1498 : * the sequencer doesn't bother to issue another
1499 : * sequencer interrupt for its completion.
1500 : */
1501 0 : while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1502 0 : && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1503 0 : && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1504 : ;
1505 0 : ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1506 0 : ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1507 : SCB_GET_CHANNEL(ahd, scb),
1508 0 : SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1509 : ROLE_INITIATOR, /*status*/0,
1510 : SEARCH_REMOVE);
1511 0 : }
1512 : break;
1513 : }
1514 : case TRACEPOINT0:
1515 : case TRACEPOINT1:
1516 : case TRACEPOINT2:
1517 : case TRACEPOINT3:
1518 0 : printf("%s: Tracepoint %d\n", ahd_name(ahd),
1519 0 : seqintcode - TRACEPOINT0);
1520 0 : break;
1521 : case NO_SEQINT:
1522 : break;
1523 : case SAW_HWERR:
1524 0 : ahd_handle_hwerrint(ahd);
1525 0 : break;
1526 : default:
1527 0 : printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1528 : seqintcode);
1529 0 : break;
1530 : }
1531 : /*
1532 : * The sequencer is paused immediately on
1533 : * a SEQINT, so we should restart it when
1534 : * we're done.
1535 : */
1536 0 : ahd_unpause(ahd);
1537 0 : }
1538 :
1539 : void
1540 0 : ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1541 : {
1542 : struct scb *scb;
1543 : u_int status0;
1544 : u_int status3;
1545 : u_int status;
1546 : u_int lqistat1;
1547 : u_int lqostat0;
1548 : u_int scbid;
1549 : u_int busfreetime;
1550 :
1551 0 : ahd_update_modes(ahd);
1552 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1553 :
1554 0 : status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1555 0 : status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1556 0 : status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1557 0 : lqistat1 = ahd_inb(ahd, LQISTAT1);
1558 0 : lqostat0 = ahd_inb(ahd, LQOSTAT0);
1559 0 : busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1560 0 : if ((status0 & (SELDI|SELDO)) != 0) {
1561 : u_int simode0;
1562 :
1563 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1564 0 : simode0 = ahd_inb(ahd, SIMODE0);
1565 0 : status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
1566 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1567 0 : }
1568 0 : scbid = ahd_get_scbptr(ahd);
1569 0 : scb = ahd_lookup_scb(ahd, scbid);
1570 0 : if (scb != NULL
1571 0 : && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1572 0 : scb = NULL;
1573 :
1574 0 : if ((status0 & IOERR) != 0) {
1575 : u_int now_lvd;
1576 :
1577 0 : now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1578 0 : printf("%s: Transceiver State Has Changed to %s mode\n",
1579 0 : ahd_name(ahd), now_lvd ? "LVD" : "SE");
1580 0 : ahd_outb(ahd, CLRSINT0, CLRIOERR);
1581 : /*
1582 : * A change in I/O mode is equivalent to a bus reset.
1583 : */
1584 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1585 0 : ahd_pause(ahd);
1586 0 : ahd_setup_iocell_workaround(ahd);
1587 0 : ahd_unpause(ahd);
1588 0 : } else if ((status0 & OVERRUN) != 0) {
1589 :
1590 0 : printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1591 0 : ahd_name(ahd));
1592 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1593 0 : } else if ((status & SCSIRSTI) != 0) {
1594 :
1595 0 : printf("%s: Someone reset channel A\n", ahd_name(ahd));
1596 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1597 0 : } else if ((status & SCSIPERR) != 0) {
1598 :
1599 : /* Make sure the sequencer is in a safe location. */
1600 0 : ahd_clear_critical_section(ahd);
1601 :
1602 0 : ahd_handle_transmission_error(ahd);
1603 0 : } else if (lqostat0 != 0) {
1604 :
1605 0 : printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1606 0 : ahd_outb(ahd, CLRLQOINT0, lqostat0);
1607 0 : if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1608 0 : ahd_outb(ahd, CLRLQOINT1, 0);
1609 0 : } else if ((status & SELTO) != 0) {
1610 :
1611 : /* Stop the selection */
1612 0 : ahd_outb(ahd, SCSISEQ0, 0);
1613 :
1614 : /* Make sure the sequencer is in a safe location. */
1615 0 : ahd_clear_critical_section(ahd);
1616 :
1617 : /* No more pending messages */
1618 0 : ahd_clear_msg_state(ahd);
1619 :
1620 : /* Clear interrupt state */
1621 0 : ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1622 :
1623 : /*
1624 : * Although the driver does not care about the
1625 : * 'Selection in Progress' status bit, the busy
1626 : * LED does. SELINGO is only cleared by a successful
1627 : * selection, so we must manually clear it to insure
1628 : * the LED turns off just incase no future successful
1629 : * selections occur (e.g. no devices on the bus).
1630 : */
1631 0 : ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1632 :
1633 0 : scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1634 0 : scb = ahd_lookup_scb(ahd, scbid);
1635 0 : if (scb == NULL) {
1636 0 : printf("%s: ahd_intr - referenced scb not "
1637 : "valid during SELTO scb(0x%x)\n",
1638 0 : ahd_name(ahd), scbid);
1639 0 : ahd_dump_card_state(ahd);
1640 0 : } else {
1641 0 : struct ahd_devinfo devinfo;
1642 : #ifdef AHD_DEBUG
1643 : if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1644 : ahd_print_path(ahd, scb);
1645 : printf("Saw Selection Timeout for SCB 0x%x\n",
1646 : scbid);
1647 : }
1648 : #endif
1649 0 : ahd_scb_devinfo(ahd, &devinfo, scb);
1650 0 : aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1651 0 : ahd_freeze_devq(ahd, scb);
1652 :
1653 : /*
1654 : * Cancel any pending transactions on the device
1655 : * now that it seems to be missing. This will
1656 : * also revert us to async/narrow transfers until
1657 : * we can renegotiate with the device.
1658 : */
1659 0 : ahd_handle_devreset(ahd, &devinfo,
1660 : CAM_LUN_WILDCARD,
1661 : CAM_SEL_TIMEOUT,
1662 : "Selection Timeout",
1663 : /*verbose_level*/1);
1664 0 : }
1665 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
1666 0 : ahd_iocell_first_selection(ahd);
1667 0 : ahd_unpause(ahd);
1668 0 : } else if ((status0 & (SELDI|SELDO)) != 0) {
1669 :
1670 0 : ahd_iocell_first_selection(ahd);
1671 0 : ahd_unpause(ahd);
1672 0 : } else if (status3 != 0) {
1673 0 : printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1674 0 : ahd_name(ahd), status3);
1675 0 : ahd_outb(ahd, CLRSINT3, status3);
1676 0 : } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1677 :
1678 : /* Make sure the sequencer is in a safe location. */
1679 0 : ahd_clear_critical_section(ahd);
1680 :
1681 0 : ahd_handle_lqiphase_error(ahd, lqistat1);
1682 0 : } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1683 : /*
1684 : * This status can be delayed during some
1685 : * streaming operations. The SCSIPHASE
1686 : * handler has already dealt with this case
1687 : * so just clear the error.
1688 : */
1689 0 : ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1690 0 : } else if ((status & BUSFREE) != 0
1691 0 : || (lqistat1 & LQOBUSFREE) != 0) {
1692 : u_int lqostat1;
1693 : int restart;
1694 : int clear_fifo;
1695 : int packetized;
1696 : u_int mode;
1697 :
1698 : /*
1699 : * Clear our selection hardware as soon as possible.
1700 : * We may have an entry in the waiting Q for this target,
1701 : * that is affected by this busfree and we don't want to
1702 : * go about selecting the target while we handle the event.
1703 : */
1704 0 : ahd_outb(ahd, SCSISEQ0, 0);
1705 :
1706 : /* Make sure the sequencer is in a safe location. */
1707 0 : ahd_clear_critical_section(ahd);
1708 :
1709 : /*
1710 : * Determine what we were up to at the time of
1711 : * the busfree.
1712 : */
1713 : mode = AHD_MODE_SCSI;
1714 0 : busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1715 0 : lqostat1 = ahd_inb(ahd, LQOSTAT1);
1716 0 : switch (busfreetime) {
1717 : case BUSFREE_DFF0:
1718 : case BUSFREE_DFF1:
1719 0 : mode = busfreetime == BUSFREE_DFF0
1720 : ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1721 0 : ahd_set_modes(ahd, mode, mode);
1722 0 : scbid = ahd_get_scbptr(ahd);
1723 0 : scb = ahd_lookup_scb(ahd, scbid);
1724 0 : if (scb == NULL) {
1725 0 : printf("%s: Invalid SCB %d in DFF%d "
1726 : "during unexpected busfree\n",
1727 0 : ahd_name(ahd), scbid, mode);
1728 : packetized = 0;
1729 0 : } else
1730 0 : packetized = (scb->flags & SCB_PACKETIZED) != 0;
1731 : clear_fifo = 1;
1732 0 : break;
1733 : case BUSFREE_LQO:
1734 : clear_fifo = 0;
1735 : packetized = 1;
1736 0 : break;
1737 : default:
1738 : clear_fifo = 0;
1739 0 : packetized = (lqostat1 & LQOBUSFREE) != 0;
1740 0 : if (!packetized
1741 0 : && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
1742 0 : && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
1743 0 : && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
1744 0 : || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
1745 : /*
1746 : * Assume packetized if we are not
1747 : * on the bus in a non-packetized
1748 : * capacity and any pending selection
1749 : * was a packetized selection.
1750 : */
1751 0 : packetized = 1;
1752 : break;
1753 : }
1754 :
1755 : #ifdef AHD_DEBUG
1756 : if ((ahd_debug & AHD_SHOW_MISC) != 0)
1757 : printf("Saw Busfree. Busfreetime = 0x%x.\n",
1758 : busfreetime);
1759 : #endif
1760 : /*
1761 : * Busfrees that occur in non-packetized phases are
1762 : * handled by the nonpkt_busfree handler.
1763 : */
1764 0 : if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1765 0 : restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1766 0 : } else {
1767 : packetized = 0;
1768 0 : restart = ahd_handle_nonpkt_busfree(ahd);
1769 : }
1770 : /*
1771 : * Clear the busfree interrupt status. The setting of
1772 : * the interrupt is a pulse, so in a perfect world, we
1773 : * would not need to muck with the ENBUSFREE logic. This
1774 : * would ensure that if the bus moves on to another
1775 : * connection, busfree protection is still in force. If
1776 : * BUSFREEREV is broken, however, we must manually clear
1777 : * the ENBUSFREE if the busfree occurred during a non-pack
1778 : * connection so that we don't get false positives during
1779 : * future, packetized, connections.
1780 : */
1781 0 : ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1782 0 : if (packetized == 0
1783 0 : && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1784 0 : ahd_outb(ahd, SIMODE1,
1785 : ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1786 :
1787 0 : if (clear_fifo)
1788 0 : ahd_clear_fifo(ahd, mode);
1789 :
1790 0 : ahd_clear_msg_state(ahd);
1791 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
1792 0 : if (restart) {
1793 0 : ahd_restart(ahd);
1794 0 : } else {
1795 0 : ahd_unpause(ahd);
1796 : }
1797 0 : } else {
1798 0 : printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1799 0 : ahd_name(ahd), status);
1800 0 : ahd_dump_card_state(ahd);
1801 0 : ahd_clear_intstat(ahd);
1802 0 : ahd_unpause(ahd);
1803 : }
1804 0 : }
1805 :
1806 : void
1807 0 : ahd_handle_transmission_error(struct ahd_softc *ahd)
1808 : {
1809 : struct scb *scb;
1810 : u_int scbid;
1811 : u_int lqistat1;
1812 : u_int lqistat2;
1813 : u_int msg_out;
1814 : u_int curphase;
1815 : u_int lastphase;
1816 : u_int perrdiag;
1817 0 : u_int cur_col;
1818 : int silent;
1819 :
1820 : scb = NULL;
1821 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1822 0 : lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1823 0 : lqistat2 = ahd_inb(ahd, LQISTAT2);
1824 0 : if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1825 0 : && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1826 : u_int lqistate;
1827 :
1828 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1829 0 : lqistate = ahd_inb(ahd, LQISTATE);
1830 0 : if ((lqistate >= 0x1E && lqistate <= 0x24)
1831 0 : || (lqistate == 0x29)) {
1832 : #ifdef AHD_DEBUG
1833 : if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1834 : printf("%s: NLQCRC found via LQISTATE\n",
1835 : ahd_name(ahd));
1836 : }
1837 : #endif
1838 0 : lqistat1 |= LQICRCI_NLQ;
1839 0 : }
1840 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1841 0 : }
1842 :
1843 0 : ahd_outb(ahd, CLRLQIINT1, lqistat1);
1844 0 : lastphase = ahd_inb(ahd, LASTPHASE);
1845 0 : curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1846 0 : perrdiag = ahd_inb(ahd, PERRDIAG);
1847 : msg_out = MSG_INITIATOR_DET_ERR;
1848 0 : ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1849 :
1850 : /*
1851 : * Try to find the SCB associated with this error.
1852 : */
1853 : silent = FALSE;
1854 0 : if (lqistat1 == 0
1855 0 : || (lqistat1 & LQICRCI_NLQ) != 0) {
1856 0 : if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1857 0 : ahd_set_active_fifo(ahd);
1858 0 : scbid = ahd_get_scbptr(ahd);
1859 0 : scb = ahd_lookup_scb(ahd, scbid);
1860 0 : if (scb != NULL && SCB_IS_SILENT(scb))
1861 0 : silent = TRUE;
1862 : }
1863 :
1864 0 : cur_col = 0;
1865 0 : if (silent == FALSE) {
1866 0 : printf("%s: Transmission error detected\n", ahd_name(ahd));
1867 0 : ahd_lqistat1_print(lqistat1, &cur_col, 50);
1868 0 : ahd_lastphase_print(lastphase, &cur_col, 50);
1869 0 : ahd_scsisigi_print(curphase, &cur_col, 50);
1870 0 : ahd_perrdiag_print(perrdiag, &cur_col, 50);
1871 0 : printf("\n");
1872 0 : ahd_dump_card_state(ahd);
1873 0 : }
1874 :
1875 0 : if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1876 0 : if (silent == FALSE) {
1877 0 : printf("%s: Gross protocol error during incoming "
1878 : "packet. lqistat1 == 0x%x. Resetting bus.\n",
1879 0 : ahd_name(ahd), lqistat1);
1880 0 : }
1881 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1882 0 : return;
1883 0 : } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1884 : /*
1885 : * A CRC error has been detected on an incoming LQ.
1886 : * The bus is currently hung on the last ACK.
1887 : * Hit LQIRETRY to release the last ack, and
1888 : * wait for the sequencer to determine that ATNO
1889 : * is asserted while in message out to take us
1890 : * to our host message loop. No NONPACKREQ or
1891 : * LQIPHASE type errors will occur in this
1892 : * scenario. After this first LQIRETRY, the LQI
1893 : * manager will be in ISELO where it will
1894 : * happily sit until another packet phase begins.
1895 : * Unexpected bus free detection is enabled
1896 : * through any phases that occur after we release
1897 : * this last ack until the LQI manager sees a
1898 : * packet phase. This implies we may have to
1899 : * ignore a perfectly valid "unexpected busfree"
1900 : * after our "initiator detected error" message is
1901 : * sent. A busfree is the expected response after
1902 : * we tell the target that its L_Q was corrupted.
1903 : * (SPI4R09 10.7.3.3.3)
1904 : */
1905 0 : ahd_outb(ahd, LQCTL2, LQIRETRY);
1906 0 : printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1907 0 : } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1908 : /*
1909 : * We detected a CRC error in a NON-LQ packet.
1910 : * The hardware has varying behavior in this situation
1911 : * depending on whether this packet was part of a
1912 : * stream or not.
1913 : *
1914 : * PKT by PKT mode:
1915 : * The hardware has already acked the complete packet.
1916 : * If the target honors our outstanding ATN condition,
1917 : * we should be (or soon will be) in MSGOUT phase.
1918 : * This will trigger the LQIPHASE_LQ status bit as the
1919 : * hardware was expecting another LQ. Unexpected
1920 : * busfree detection is enabled. Once LQIPHASE_LQ is
1921 : * true (first entry into host message loop is much
1922 : * the same), we must clear LQIPHASE_LQ and hit
1923 : * LQIRETRY so the hardware is ready to handle
1924 : * a future LQ. NONPACKREQ will not be asserted again
1925 : * once we hit LQIRETRY until another packet is
1926 : * processed. The target may either go busfree
1927 : * or start another packet in response to our message.
1928 : *
1929 : * Read Streaming P0 asserted:
1930 : * If we raise ATN and the target completes the entire
1931 : * stream (P0 asserted during the last packet), the
1932 : * hardware will ack all data and return to the ISTART
1933 : * state. When the target reponds to our ATN condition,
1934 : * LQIPHASE_LQ will be asserted. We should respond to
1935 : * this with an LQIRETRY to prepare for any future
1936 : * packets. NONPACKREQ will not be asserted again
1937 : * once we hit LQIRETRY until another packet is
1938 : * processed. The target may either go busfree or
1939 : * start another packet in response to our message.
1940 : * Busfree detection is enabled.
1941 : *
1942 : * Read Streaming P0 not asserted:
1943 : * If we raise ATN and the target transitions to
1944 : * MSGOUT in or after a packet where P0 is not
1945 : * asserted, the hardware will assert LQIPHASE_NLQ.
1946 : * We should respond to the LQIPHASE_NLQ with an
1947 : * LQIRETRY. Should the target stay in a non-pkt
1948 : * phase after we send our message, the hardware
1949 : * will assert LQIPHASE_LQ. Recovery is then just as
1950 : * listed above for the read streaming with P0 asserted.
1951 : * Busfree detection is enabled.
1952 : */
1953 0 : if (silent == FALSE)
1954 0 : printf("LQICRC_NLQ\n");
1955 0 : if (scb == NULL) {
1956 0 : printf("%s: No SCB valid for LQICRC_NLQ. "
1957 0 : "Resetting bus\n", ahd_name(ahd));
1958 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1959 0 : return;
1960 : }
1961 0 : } else if ((lqistat1 & LQIBADLQI) != 0) {
1962 0 : printf("Need to handle BADLQI!\n");
1963 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1964 0 : return;
1965 0 : } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1966 0 : if ((curphase & ~P_DATAIN_DT) != 0) {
1967 : /* Ack the byte. So we can continue. */
1968 0 : if (silent == FALSE)
1969 0 : printf("Acking %s to clear perror\n",
1970 0 : ahd_lookup_phase_entry(curphase)->phasemsg);
1971 0 : ahd_inb(ahd, SCSIDAT);
1972 0 : }
1973 :
1974 0 : if (curphase == P_MESGIN)
1975 0 : msg_out = MSG_PARITY_ERROR;
1976 : }
1977 :
1978 : /*
1979 : * We've set the hardware to assert ATN if we
1980 : * get a parity error on "in" phases, so all we
1981 : * need to do is stuff the message buffer with
1982 : * the appropriate message. "In" phases have set
1983 : * mesg_out to something other than MSG_NOP.
1984 : */
1985 0 : ahd->send_msg_perror = msg_out;
1986 0 : if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
1987 0 : scb->flags |= SCB_TRANSMISSION_ERROR;
1988 0 : ahd_outb(ahd, MSG_OUT, HOST_MSG);
1989 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
1990 0 : ahd_unpause(ahd);
1991 0 : }
1992 :
1993 : void
1994 0 : ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
1995 : {
1996 : /*
1997 : * Clear the sources of the interrupts.
1998 : */
1999 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2000 0 : ahd_outb(ahd, CLRLQIINT1, lqistat1);
2001 :
2002 : /*
2003 : * If the "illegal" phase changes were in response
2004 : * to our ATN to flag a CRC error, AND we ended up
2005 : * on packet boundaries, clear the error, restart the
2006 : * LQI manager as appropriate, and go on our merry
2007 : * way toward sending the message. Otherwise, reset
2008 : * the bus to clear the error.
2009 : */
2010 0 : ahd_set_active_fifo(ahd);
2011 0 : if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
2012 0 : && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
2013 0 : if ((lqistat1 & LQIPHASE_LQ) != 0) {
2014 0 : printf("LQIRETRY for LQIPHASE_LQ\n");
2015 0 : ahd_outb(ahd, LQCTL2, LQIRETRY);
2016 0 : } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
2017 0 : printf("LQIRETRY for LQIPHASE_NLQ\n");
2018 0 : ahd_outb(ahd, LQCTL2, LQIRETRY);
2019 : } else
2020 0 : panic("ahd_handle_lqiphase_error: No phase errors");
2021 0 : ahd_dump_card_state(ahd);
2022 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
2023 0 : ahd_unpause(ahd);
2024 0 : } else {
2025 0 : printf("Resetting Channel for LQI Phase error\n");
2026 0 : ahd_dump_card_state(ahd);
2027 0 : ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
2028 : }
2029 0 : }
2030 :
2031 : /*
2032 : * Packetized unexpected or expected busfree.
2033 : * Entered in mode based on busfreetime.
2034 : */
2035 : int
2036 0 : ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
2037 : {
2038 : u_int lqostat1;
2039 :
2040 0 : AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2041 : ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2042 0 : lqostat1 = ahd_inb(ahd, LQOSTAT1);
2043 0 : if ((lqostat1 & LQOBUSFREE) != 0) {
2044 : struct scb *scb;
2045 : u_int scbid;
2046 : u_int saved_scbptr;
2047 : u_int waiting_h;
2048 : u_int waiting_t;
2049 : u_int next;
2050 :
2051 : /*
2052 : * The LQO manager detected an unexpected busfree
2053 : * either:
2054 : *
2055 : * 1) During an outgoing LQ.
2056 : * 2) After an outgoing LQ but before the first
2057 : * REQ of the command packet.
2058 : * 3) During an outgoing command packet.
2059 : *
2060 : * In all cases, CURRSCB is pointing to the
2061 : * SCB that encountered the failure. Clean
2062 : * up the queue, clear SELDO and LQOBUSFREE,
2063 : * and allow the sequencer to restart the select
2064 : * out at its lesure.
2065 : */
2066 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2067 0 : scbid = ahd_inw(ahd, CURRSCB);
2068 0 : scb = ahd_lookup_scb(ahd, scbid);
2069 0 : if (scb == NULL)
2070 0 : panic("SCB not valid during LQOBUSFREE");
2071 : /*
2072 : * Clear the status.
2073 : */
2074 0 : ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
2075 0 : if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
2076 0 : ahd_outb(ahd, CLRLQOINT1, 0);
2077 0 : ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2078 0 : ahd_flush_device_writes(ahd);
2079 0 : ahd_outb(ahd, CLRSINT0, CLRSELDO);
2080 :
2081 : /*
2082 : * Return the LQO manager to its idle loop. It will
2083 : * not do this automatically if the busfree occurs
2084 : * after the first REQ of either the LQ or command
2085 : * packet or between the LQ and command packet.
2086 : */
2087 0 : ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2088 :
2089 : /*
2090 : * Update the waiting for selection queue so
2091 : * we restart on the correct SCB.
2092 : */
2093 0 : waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2094 0 : saved_scbptr = ahd_get_scbptr(ahd);
2095 0 : if (waiting_h != scbid) {
2096 :
2097 0 : ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2098 0 : waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
2099 0 : if (waiting_t == waiting_h) {
2100 0 : ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2101 : next = SCB_LIST_NULL;
2102 0 : } else {
2103 0 : ahd_set_scbptr(ahd, waiting_h);
2104 0 : next = ahd_inw_scbram(ahd, SCB_NEXT2);
2105 : }
2106 0 : ahd_set_scbptr(ahd, scbid);
2107 0 : ahd_outw(ahd, SCB_NEXT2, next);
2108 0 : }
2109 0 : ahd_set_scbptr(ahd, saved_scbptr);
2110 0 : if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2111 0 : if (SCB_IS_SILENT(scb) == FALSE) {
2112 0 : ahd_print_path(ahd, scb);
2113 0 : printf("Probable outgoing LQ CRC error. "
2114 : "Retrying command\n");
2115 0 : }
2116 0 : scb->crc_retry_count++;
2117 0 : } else {
2118 0 : aic_set_transaction_status(scb, CAM_UNCOR_PARITY);
2119 : aic_freeze_scb(scb);
2120 0 : ahd_freeze_devq(ahd, scb);
2121 : }
2122 : /* Return unpausing the sequencer. */
2123 : return (0);
2124 0 : } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2125 : /*
2126 : * Ignore what are really parity errors that
2127 : * occur on the last REQ of a free running
2128 : * clock prior to going busfree. Some drives
2129 : * do not properly active negate just before
2130 : * going busfree resulting in a parity glitch.
2131 : */
2132 0 : ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2133 : #ifdef AHD_DEBUG
2134 : if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2135 : printf("%s: Parity on last REQ detected "
2136 : "during busfree phase.\n",
2137 : ahd_name(ahd));
2138 : #endif
2139 : /* Return unpausing the sequencer. */
2140 0 : return (0);
2141 : }
2142 0 : if (ahd->src_mode != AHD_MODE_SCSI) {
2143 : u_int scbid;
2144 : struct scb *scb;
2145 :
2146 0 : scbid = ahd_get_scbptr(ahd);
2147 0 : scb = ahd_lookup_scb(ahd, scbid);
2148 0 : ahd_print_path(ahd, scb);
2149 0 : printf("Unexpected PKT busfree condition\n");
2150 0 : ahd_dump_card_state(ahd);
2151 0 : ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2152 0 : SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2153 : ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2154 :
2155 : /* Return restarting the sequencer. */
2156 : return (1);
2157 : }
2158 0 : printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2159 0 : ahd_dump_card_state(ahd);
2160 : /* Restart the sequencer. */
2161 0 : return (1);
2162 0 : }
2163 :
2164 : /*
2165 : * Non-packetized unexpected or expected busfree.
2166 : */
2167 : int
2168 0 : ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2169 : {
2170 0 : struct ahd_devinfo devinfo;
2171 : struct scb *scb;
2172 : u_int lastphase;
2173 : u_int saved_scsiid;
2174 : u_int saved_lun;
2175 : u_int target;
2176 : u_int initiator_role_id;
2177 : u_int scbid;
2178 : u_int ppr_busfree;
2179 : int printerror;
2180 :
2181 : /*
2182 : * Look at what phase we were last in. If its message out,
2183 : * chances are pretty good that the busfree was in response
2184 : * to one of our abort requests.
2185 : */
2186 0 : lastphase = ahd_inb(ahd, LASTPHASE);
2187 0 : saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
2188 0 : saved_lun = ahd_inb(ahd, SAVED_LUN);
2189 0 : target = SCSIID_TARGET(ahd, saved_scsiid);
2190 0 : initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
2191 0 : ahd_compile_devinfo(&devinfo, initiator_role_id,
2192 : target, saved_lun, 'A', ROLE_INITIATOR);
2193 : printerror = 1;
2194 :
2195 0 : scbid = ahd_get_scbptr(ahd);
2196 0 : scb = ahd_lookup_scb(ahd, scbid);
2197 0 : if (scb != NULL
2198 0 : && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2199 0 : scb = NULL;
2200 :
2201 0 : ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2202 0 : if (lastphase == P_MESGOUT) {
2203 : u_int tag;
2204 :
2205 : tag = SCB_LIST_NULL;
2206 0 : if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2207 0 : || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2208 : int found;
2209 : int sent_msg;
2210 :
2211 0 : if (scb == NULL) {
2212 0 : ahd_print_devinfo(ahd, &devinfo);
2213 0 : printf("Abort for unidentified "
2214 : "connection completed.\n");
2215 : /* restart the sequencer. */
2216 0 : return (1);
2217 : }
2218 0 : sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2219 0 : ahd_print_path(ahd, scb);
2220 0 : printf("SCB %d - Abort%s Completed.\n",
2221 0 : SCB_GET_TAG(scb),
2222 0 : sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2223 :
2224 0 : if (sent_msg == MSG_ABORT_TAG)
2225 0 : tag = SCB_GET_TAG(scb);
2226 :
2227 0 : if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) {
2228 : /*
2229 : * This abort is in response to an
2230 : * unexpected switch to command phase
2231 : * for a packetized connection. Since
2232 : * the identify message was never sent,
2233 : * "saved lun" is 0. We really want to
2234 : * abort only the SCB that encountered
2235 : * this error, which could have a different
2236 : * lun. The SCB will be retried so the OS
2237 : * will see the UA after renegotiating to
2238 : * packetized.
2239 : */
2240 0 : tag = SCB_GET_TAG(scb);
2241 0 : saved_lun = scb->hscb->lun;
2242 0 : }
2243 0 : found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
2244 : tag, ROLE_INITIATOR,
2245 : CAM_REQ_ABORTED);
2246 : printerror = 0;
2247 0 : } else if (ahd_sent_msg(ahd, AHDMSG_1B,
2248 : MSG_BUS_DEV_RESET, TRUE)) {
2249 : #ifdef __FreeBSD__
2250 : /*
2251 : * Don't mark the user's request for this BDR
2252 : * as completing with CAM_BDR_SENT. CAM3
2253 : * specifies CAM_REQ_CMP.
2254 : */
2255 : if (scb != NULL
2256 : && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2257 : && ahd_match_scb(ahd, scb, target, 'A',
2258 : CAM_LUN_WILDCARD, SCB_LIST_NULL,
2259 : ROLE_INITIATOR))
2260 : aic_set_transaction_status(scb, CAM_REQ_CMP);
2261 : #endif
2262 0 : ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2263 : CAM_BDR_SENT, "Bus Device Reset",
2264 : /*verbose_level*/0);
2265 : printerror = 0;
2266 0 : } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2267 0 : && ppr_busfree == 0) {
2268 : struct ahd_initiator_tinfo *tinfo;
2269 0 : struct ahd_tmode_tstate *tstate;
2270 :
2271 : /*
2272 : * PPR Rejected.
2273 : *
2274 : * If the previous negotiation was packetized,
2275 : * this could be because the device has been
2276 : * reset without our knowledge. Force our
2277 : * current negotiation to async and retry the
2278 : * negotiation. Otherwise retry the command
2279 : * with non-ppr negotiation.
2280 : */
2281 : #ifdef AHD_DEBUG
2282 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2283 : printf("PPR negotiation rejected busfree.\n");
2284 : #endif
2285 0 : tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2286 0 : devinfo.our_scsiid,
2287 0 : devinfo.target, &tstate);
2288 0 : if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
2289 0 : ahd_set_width(ahd, &devinfo,
2290 : MSG_EXT_WDTR_BUS_8_BIT,
2291 : AHD_TRANS_CUR,
2292 : /*paused*/TRUE);
2293 0 : ahd_set_syncrate(ahd, &devinfo,
2294 : /*period*/0, /*offset*/0,
2295 : /*ppr_options*/0,
2296 : AHD_TRANS_CUR,
2297 : /*paused*/TRUE);
2298 : /*
2299 : * The expect PPR busfree handler below
2300 : * will effect the retry and necessary
2301 : * abort.
2302 : */
2303 0 : } else {
2304 0 : tinfo->curr.transport_version = 2;
2305 0 : tinfo->goal.transport_version = 2;
2306 0 : tinfo->goal.ppr_options = 0;
2307 : /*
2308 : * Remove any SCBs in the waiting for selection
2309 : * queue that may also be for this target so
2310 : * that command ordering is preserved.
2311 : */
2312 0 : ahd_freeze_devq(ahd, scb);
2313 0 : ahd_qinfifo_requeue_tail(ahd, scb);
2314 : printerror = 0;
2315 : }
2316 0 : } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2317 0 : && ppr_busfree == 0) {
2318 : /*
2319 : * Negotiation Rejected. Go-narrow and
2320 : * retry command.
2321 : */
2322 : #ifdef AHD_DEBUG
2323 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2324 : printf("WDTR negotiation rejected busfree.\n");
2325 : #endif
2326 0 : ahd_set_width(ahd, &devinfo,
2327 : MSG_EXT_WDTR_BUS_8_BIT,
2328 : AHD_TRANS_CUR|AHD_TRANS_GOAL,
2329 : /*paused*/TRUE);
2330 : /*
2331 : * Remove any SCBs in the waiting for selection
2332 : * queue that may also be for this target so that
2333 : * command ordering is preserved.
2334 : */
2335 0 : ahd_freeze_devq(ahd, scb);
2336 0 : ahd_qinfifo_requeue_tail(ahd, scb);
2337 : printerror = 0;
2338 0 : } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2339 0 : && ppr_busfree == 0) {
2340 : /*
2341 : * Negotiation Rejected. Go-async and
2342 : * retry command.
2343 : */
2344 : #ifdef AHD_DEBUG
2345 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2346 : printf("SDTR negotiation rejected busfree.\n");
2347 : #endif
2348 0 : ahd_set_syncrate(ahd, &devinfo,
2349 : /*period*/0, /*offset*/0,
2350 : /*ppr_options*/0,
2351 : AHD_TRANS_CUR|AHD_TRANS_GOAL,
2352 : /*paused*/TRUE);
2353 : /*
2354 : * Remove any SCBs in the waiting for selection
2355 : * queue that may also be for this target so that
2356 : * command ordering is preserved.
2357 : */
2358 0 : ahd_freeze_devq(ahd, scb);
2359 0 : ahd_qinfifo_requeue_tail(ahd, scb);
2360 : printerror = 0;
2361 0 : } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2362 0 : && ahd_sent_msg(ahd, AHDMSG_1B,
2363 : MSG_INITIATOR_DET_ERR, TRUE)) {
2364 :
2365 : #ifdef AHD_DEBUG
2366 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2367 : printf("Expected IDE Busfree\n");
2368 : #endif
2369 : printerror = 0;
2370 0 : } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2371 0 : && ahd_sent_msg(ahd, AHDMSG_1B,
2372 : MSG_MESSAGE_REJECT, TRUE)) {
2373 :
2374 : #ifdef AHD_DEBUG
2375 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2376 : printf("Expected QAS Reject Busfree\n");
2377 : #endif
2378 : printerror = 0;
2379 0 : }
2380 0 : }
2381 :
2382 : /*
2383 : * The busfree required flag is honored at the end of
2384 : * the message phases. We check it last in case we
2385 : * had to send some other message that caused a busfree.
2386 : */
2387 0 : if (printerror != 0
2388 0 : && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2389 0 : && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)
2390 0 : && (scb != NULL)) {
2391 :
2392 0 : ahd_freeze_devq(ahd, scb);
2393 0 : aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
2394 : aic_freeze_scb(scb);
2395 0 : if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2396 0 : ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2397 : SCB_GET_CHANNEL(ahd, scb),
2398 0 : SCB_GET_LUN(scb), SCB_LIST_NULL,
2399 : ROLE_INITIATOR, CAM_REQ_ABORTED);
2400 0 : } else {
2401 : #ifdef AHD_DEBUG
2402 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2403 : printf("PPR Negotiation Busfree.\n");
2404 : #endif
2405 0 : ahd_done(ahd, scb);
2406 : }
2407 : printerror = 0;
2408 0 : }
2409 0 : if (printerror != 0) {
2410 : int aborted;
2411 :
2412 : aborted = 0;
2413 0 : if (scb != NULL) {
2414 : u_int tag;
2415 :
2416 0 : if ((scb->hscb->control & TAG_ENB) != 0)
2417 0 : tag = SCB_GET_TAG(scb);
2418 : else
2419 : tag = SCB_LIST_NULL;
2420 0 : ahd_print_path(ahd, scb);
2421 0 : aborted = ahd_abort_scbs(ahd, target, 'A',
2422 0 : SCB_GET_LUN(scb), tag,
2423 : ROLE_INITIATOR,
2424 : CAM_UNEXP_BUSFREE);
2425 0 : } else {
2426 : /*
2427 : * We had not fully identified this connection,
2428 : * so we cannot abort anything.
2429 : */
2430 0 : printf("%s: ", ahd_name(ahd));
2431 : }
2432 0 : printf("Unexpected busfree %s, %d SCBs aborted, "
2433 : "PRGMCNT == 0x%x\n",
2434 0 : ahd_lookup_phase_entry(lastphase)->phasemsg,
2435 : aborted,
2436 0 : ahd_inw(ahd, PRGMCNT));
2437 0 : ahd_dump_card_state(ahd);
2438 0 : if (lastphase != P_BUSFREE)
2439 0 : ahd_force_renegotiation(ahd, &devinfo);
2440 0 : }
2441 : /* Always restart the sequencer. */
2442 0 : return (1);
2443 0 : }
2444 :
2445 : void
2446 0 : ahd_handle_proto_violation(struct ahd_softc *ahd)
2447 : {
2448 0 : struct ahd_devinfo devinfo;
2449 : struct scb *scb;
2450 : u_int scbid;
2451 : u_int seq_flags;
2452 : u_int curphase;
2453 : u_int lastphase;
2454 : int found;
2455 :
2456 0 : ahd_fetch_devinfo(ahd, &devinfo);
2457 0 : scbid = ahd_get_scbptr(ahd);
2458 0 : scb = ahd_lookup_scb(ahd, scbid);
2459 0 : seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2460 0 : curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2461 0 : lastphase = ahd_inb(ahd, LASTPHASE);
2462 0 : if ((seq_flags & NOT_IDENTIFIED) != 0) {
2463 :
2464 : /*
2465 : * The reconnecting target either did not send an
2466 : * identify message, or did, but we didn't find an SCB
2467 : * to match.
2468 : */
2469 0 : ahd_print_devinfo(ahd, &devinfo);
2470 0 : printf("Target did not send an IDENTIFY message. "
2471 : "LASTPHASE = 0x%x.\n", lastphase);
2472 : scb = NULL;
2473 0 : } else if (scb == NULL) {
2474 : /*
2475 : * We don't seem to have an SCB active for this
2476 : * transaction. Print an error and reset the bus.
2477 : */
2478 0 : ahd_print_devinfo(ahd, &devinfo);
2479 0 : printf("No SCB found during protocol violation\n");
2480 0 : goto proto_violation_reset;
2481 : } else {
2482 0 : aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2483 0 : if ((seq_flags & NO_CDB_SENT) != 0) {
2484 0 : ahd_print_path(ahd, scb);
2485 0 : printf("No or incomplete CDB sent to device.\n");
2486 0 : } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2487 0 : & STATUS_RCVD) == 0) {
2488 : /*
2489 : * The target never bothered to provide status to
2490 : * us prior to completing the command. Since we don't
2491 : * know the disposition of this command, we must attempt
2492 : * to abort it. Assert ATN and prepare to send an abort
2493 : * message.
2494 : */
2495 : ahd_print_path(ahd, scb);
2496 0 : printf("Completed command without status.\n");
2497 0 : } else {
2498 : ahd_print_path(ahd, scb);
2499 0 : printf("Unknown protocol violation.\n");
2500 0 : ahd_dump_card_state(ahd);
2501 : }
2502 : }
2503 0 : if ((lastphase & ~P_DATAIN_DT) == 0
2504 0 : || lastphase == P_COMMAND) {
2505 : proto_violation_reset:
2506 : /*
2507 : * Target either went directly to data
2508 : * phase or didn't respond to our ATN.
2509 : * The only safe thing to do is to blow
2510 : * it away with a bus reset.
2511 : */
2512 0 : found = ahd_reset_channel(ahd, 'A', TRUE);
2513 0 : printf("%s: Issued Channel %c Bus Reset. "
2514 0 : "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2515 0 : } else {
2516 : /*
2517 : * Leave the selection hardware off in case
2518 : * this abort attempt will affect yet to
2519 : * be sent commands.
2520 : */
2521 0 : ahd_outb(ahd, SCSISEQ0,
2522 : ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2523 0 : ahd_assert_atn(ahd);
2524 0 : ahd_outb(ahd, MSG_OUT, HOST_MSG);
2525 0 : if (scb == NULL) {
2526 0 : ahd_print_devinfo(ahd, &devinfo);
2527 0 : ahd->msgout_buf[0] = MSG_ABORT_TASK;
2528 0 : ahd->msgout_len = 1;
2529 0 : ahd->msgout_index = 0;
2530 0 : ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2531 0 : } else {
2532 0 : ahd_print_path(ahd, scb);
2533 0 : scb->flags |= SCB_ABORT;
2534 : }
2535 0 : printf("Protocol violation %s. Attempting to abort.\n",
2536 0 : ahd_lookup_phase_entry(curphase)->phasemsg);
2537 : }
2538 0 : }
2539 :
2540 : /*
2541 : * Force renegotiation to occur the next time we initiate
2542 : * a command to the current device.
2543 : */
2544 : void
2545 0 : ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2546 : {
2547 : struct ahd_initiator_tinfo *targ_info;
2548 0 : struct ahd_tmode_tstate *tstate;
2549 :
2550 : #ifdef AHD_DEBUG
2551 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2552 : ahd_print_devinfo(ahd, devinfo);
2553 : printf("Forcing renegotiation\n");
2554 : }
2555 : #endif
2556 0 : targ_info = ahd_fetch_transinfo(ahd,
2557 0 : devinfo->channel,
2558 0 : devinfo->our_scsiid,
2559 0 : devinfo->target,
2560 : &tstate);
2561 0 : ahd_update_neg_request(ahd, devinfo, tstate,
2562 : targ_info, AHD_NEG_IF_NON_ASYNC);
2563 0 : }
2564 :
2565 : #define AHD_MAX_STEPS 2000
2566 : void
2567 0 : ahd_clear_critical_section(struct ahd_softc *ahd)
2568 : {
2569 : ahd_mode_state saved_modes;
2570 : int stepping;
2571 : int steps;
2572 : int first_instr;
2573 : u_int simode0;
2574 : u_int simode1;
2575 : u_int simode3;
2576 : u_int lqimode0;
2577 : u_int lqimode1;
2578 : u_int lqomode0;
2579 : u_int lqomode1;
2580 :
2581 0 : if (ahd->num_critical_sections == 0)
2582 0 : return;
2583 :
2584 : stepping = FALSE;
2585 : steps = 0;
2586 : first_instr = 0;
2587 : simode0 = 0;
2588 : simode1 = 0;
2589 : simode3 = 0;
2590 : lqimode0 = 0;
2591 : lqimode1 = 0;
2592 : lqomode0 = 0;
2593 : lqomode1 = 0;
2594 0 : saved_modes = ahd_save_modes(ahd);
2595 0 : for (;;) {
2596 : struct cs *cs;
2597 : u_int seqaddr;
2598 : u_int i;
2599 :
2600 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2601 0 : seqaddr = ahd_inw(ahd, CURADDR);
2602 :
2603 0 : cs = ahd->critical_sections;
2604 0 : for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2605 :
2606 0 : if (cs->begin < seqaddr && cs->end >= seqaddr)
2607 : break;
2608 : }
2609 :
2610 0 : if (i == ahd->num_critical_sections)
2611 0 : break;
2612 :
2613 0 : if (steps > AHD_MAX_STEPS) {
2614 0 : printf("%s: Infinite loop in critical section\n"
2615 : "%s: First Instruction 0x%x now 0x%x\n",
2616 0 : ahd_name(ahd), ahd_name(ahd), first_instr,
2617 : seqaddr);
2618 0 : ahd_dump_card_state(ahd);
2619 0 : panic("critical section loop");
2620 : }
2621 :
2622 0 : steps++;
2623 : #ifdef AHD_DEBUG
2624 : if ((ahd_debug & AHD_SHOW_MISC) != 0)
2625 : printf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2626 : seqaddr);
2627 : #endif
2628 0 : if (stepping == FALSE) {
2629 :
2630 : first_instr = seqaddr;
2631 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2632 0 : simode0 = ahd_inb(ahd, SIMODE0);
2633 0 : simode3 = ahd_inb(ahd, SIMODE3);
2634 0 : lqimode0 = ahd_inb(ahd, LQIMODE0);
2635 0 : lqimode1 = ahd_inb(ahd, LQIMODE1);
2636 0 : lqomode0 = ahd_inb(ahd, LQOMODE0);
2637 0 : lqomode1 = ahd_inb(ahd, LQOMODE1);
2638 0 : ahd_outb(ahd, SIMODE0, 0);
2639 0 : ahd_outb(ahd, SIMODE3, 0);
2640 0 : ahd_outb(ahd, LQIMODE0, 0);
2641 0 : ahd_outb(ahd, LQIMODE1, 0);
2642 0 : ahd_outb(ahd, LQOMODE0, 0);
2643 0 : ahd_outb(ahd, LQOMODE1, 0);
2644 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2645 0 : simode1 = ahd_inb(ahd, SIMODE1);
2646 : /*
2647 : * We don't clear ENBUSFREE. Unfortunately
2648 : * we cannot re-enable busfree detection within
2649 : * the current connection, so we must leave it
2650 : * on while single stepping.
2651 : */
2652 0 : ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
2653 0 : ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2654 : stepping = TRUE;
2655 0 : }
2656 0 : ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2657 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
2658 0 : ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2659 0 : ahd_outb(ahd, HCNTRL, ahd->unpause);
2660 0 : while (!ahd_is_paused(ahd))
2661 0 : aic_delay(200);
2662 0 : ahd_update_modes(ahd);
2663 0 : }
2664 0 : if (stepping) {
2665 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2666 0 : ahd_outb(ahd, SIMODE0, simode0);
2667 0 : ahd_outb(ahd, SIMODE3, simode3);
2668 0 : ahd_outb(ahd, LQIMODE0, lqimode0);
2669 0 : ahd_outb(ahd, LQIMODE1, lqimode1);
2670 0 : ahd_outb(ahd, LQOMODE0, lqomode0);
2671 0 : ahd_outb(ahd, LQOMODE1, lqomode1);
2672 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2673 0 : ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2674 0 : ahd_outb(ahd, SIMODE1, simode1);
2675 : /*
2676 : * SCSIINT seems to glitch occassionally when
2677 : * the interrupt masks are restored. Clear SCSIINT
2678 : * one more time so that only persistent errors
2679 : * are seen as a real interrupt.
2680 : */
2681 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
2682 0 : }
2683 0 : ahd_restore_modes(ahd, saved_modes);
2684 0 : }
2685 :
2686 : /*
2687 : * Clear any pending interrupt status.
2688 : */
2689 : void
2690 0 : ahd_clear_intstat(struct ahd_softc *ahd)
2691 : {
2692 0 : AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2693 : ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2694 : /* Clear any interrupt conditions this may have caused */
2695 0 : ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2696 : |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2697 0 : ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2698 : |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2699 : |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2700 0 : ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2701 : |CLRLQOATNPKT|CLRLQOTCRC);
2702 0 : ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2703 : |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2704 0 : if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2705 0 : ahd_outb(ahd, CLRLQOINT0, 0);
2706 0 : ahd_outb(ahd, CLRLQOINT1, 0);
2707 0 : }
2708 0 : ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2709 0 : ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2710 : |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2711 0 : ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2712 : |CLRIOERR|CLROVERRUN);
2713 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
2714 0 : }
2715 :
2716 : /**************************** Debugging Routines ******************************/
2717 : #ifdef AHD_DEBUG
2718 : uint32_t ahd_debug = AHD_DEBUG_OPTS;
2719 : #endif
2720 : void
2721 0 : ahd_print_scb(struct scb *scb)
2722 : {
2723 : struct hardware_scb *hscb;
2724 : int i;
2725 :
2726 0 : hscb = scb->hscb;
2727 0 : printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2728 0 : (void *)scb,
2729 0 : hscb->control,
2730 0 : hscb->scsiid,
2731 0 : hscb->lun,
2732 0 : hscb->cdb_len);
2733 0 : printf("Shared Data: ");
2734 0 : for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2735 0 : printf("%#02x", hscb->shared_data.idata.cdb[i]);
2736 0 : printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2737 0 : (uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2738 0 : (uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2739 0 : aic_le32toh(hscb->datacnt),
2740 0 : aic_le32toh(hscb->sgptr),
2741 0 : SCB_GET_TAG(scb));
2742 0 : ahd_dump_sglist(scb);
2743 0 : }
2744 :
2745 : void
2746 0 : ahd_dump_sglist(struct scb *scb)
2747 : {
2748 : int i;
2749 :
2750 0 : if (scb->sg_count > 0) {
2751 0 : if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2752 : struct ahd_dma64_seg *sg_list;
2753 :
2754 0 : sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2755 0 : for (i = 0; i < scb->sg_count; i++) {
2756 : uint64_t addr;
2757 : uint32_t len;
2758 :
2759 0 : addr = aic_le64toh(sg_list[i].addr);
2760 0 : len = aic_le32toh(sg_list[i].len);
2761 0 : printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2762 : i,
2763 0 : (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2764 0 : (uint32_t)(addr & 0xFFFFFFFF),
2765 0 : sg_list[i].len & AHD_SG_LEN_MASK,
2766 0 : (sg_list[i].len & AHD_DMA_LAST_SEG)
2767 : ? " Last" : "");
2768 : }
2769 0 : } else {
2770 : struct ahd_dma_seg *sg_list;
2771 :
2772 0 : sg_list = (struct ahd_dma_seg*)scb->sg_list;
2773 0 : for (i = 0; i < scb->sg_count; i++) {
2774 : uint32_t len;
2775 :
2776 0 : len = aic_le32toh(sg_list[i].len);
2777 0 : printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2778 : i,
2779 0 : (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2780 0 : aic_le32toh(sg_list[i].addr),
2781 0 : len & AHD_SG_LEN_MASK,
2782 0 : len & AHD_DMA_LAST_SEG ? " Last" : "");
2783 : }
2784 : }
2785 : }
2786 0 : }
2787 :
2788 : /************************* Transfer Negotiation *******************************/
2789 : /*
2790 : * Allocate per target mode instance (ID we respond to as a target)
2791 : * transfer negotiation data structures.
2792 : */
2793 : struct ahd_tmode_tstate *
2794 0 : ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
2795 : {
2796 : struct ahd_tmode_tstate *master_tstate;
2797 : struct ahd_tmode_tstate *tstate;
2798 : int i;
2799 :
2800 0 : master_tstate = ahd->enabled_targets[ahd->our_id];
2801 0 : if (ahd->enabled_targets[scsi_id] != NULL
2802 0 : && ahd->enabled_targets[scsi_id] != master_tstate)
2803 0 : panic("%s: ahd_alloc_tstate - Target already allocated",
2804 0 : ahd_name(ahd));
2805 0 : tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO);
2806 0 : if (tstate == NULL)
2807 0 : return (NULL);
2808 :
2809 : /*
2810 : * If we have allocated a master tstate, copy user settings from
2811 : * the master tstate (taken from SRAM or the EEPROM) for this
2812 : * channel, but reset our current and goal settings to async/narrow
2813 : * until an initiator talks to us.
2814 : */
2815 0 : if (master_tstate != NULL) {
2816 0 : memcpy(tstate, master_tstate, sizeof(*tstate));
2817 0 : memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2818 0 : for (i = 0; i < 16; i++) {
2819 0 : memset(&tstate->transinfo[i].curr, 0,
2820 : sizeof(tstate->transinfo[i].curr));
2821 0 : memset(&tstate->transinfo[i].goal, 0,
2822 : sizeof(tstate->transinfo[i].goal));
2823 : }
2824 : }
2825 0 : ahd->enabled_targets[scsi_id] = tstate;
2826 0 : return (tstate);
2827 0 : }
2828 :
2829 : #ifdef AHD_TARGET_MODE
2830 : /*
2831 : * Free per target mode instance (ID we respond to as a target)
2832 : * transfer negotiation data structures.
2833 : */
2834 : void
2835 : ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
2836 : {
2837 : struct ahd_tmode_tstate *tstate;
2838 :
2839 : /*
2840 : * Don't clean up our "master" tstate.
2841 : * It has our default user settings.
2842 : */
2843 : if (scsi_id == ahd->our_id
2844 : && force == FALSE)
2845 : return;
2846 :
2847 : tstate = ahd->enabled_targets[scsi_id];
2848 : if (tstate != NULL)
2849 : free(tstate, M_DEVBUF, 0);
2850 : ahd->enabled_targets[scsi_id] = NULL;
2851 : }
2852 : #endif
2853 :
2854 : /*
2855 : * Called when we have an active connection to a target on the bus,
2856 : * this function finds the nearest period to the input period limited
2857 : * by the capabilities of the bus connectivity of and sync settings for
2858 : * the target.
2859 : */
2860 : void
2861 0 : ahd_devlimited_syncrate(struct ahd_softc *ahd,
2862 : struct ahd_initiator_tinfo *tinfo,
2863 : u_int *period, u_int *ppr_options, role_t role)
2864 : {
2865 : struct ahd_transinfo *transinfo;
2866 : u_int maxsync;
2867 :
2868 0 : if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
2869 0 : && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
2870 : maxsync = AHD_SYNCRATE_PACED;
2871 0 : } else {
2872 : maxsync = AHD_SYNCRATE_ULTRA;
2873 : /* Can't do DT related options on an SE bus */
2874 0 : *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2875 : }
2876 : /*
2877 : * Never allow a value higher than our current goal
2878 : * period otherwise we may allow a target initiated
2879 : * negotiation to go above the limit as set by the
2880 : * user. In the case of an initiator initiated
2881 : * sync negotiation, we limit based on the user
2882 : * setting. This allows the system to still accept
2883 : * incoming negotiations even if target initiated
2884 : * negotiation is not performed.
2885 : */
2886 0 : if (role == ROLE_TARGET)
2887 0 : transinfo = &tinfo->user;
2888 : else
2889 0 : transinfo = &tinfo->goal;
2890 0 : *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2891 0 : if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2892 0 : maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2893 0 : *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2894 0 : }
2895 0 : if (transinfo->period == 0) {
2896 0 : *period = 0;
2897 0 : *ppr_options = 0;
2898 0 : } else {
2899 0 : *period = MAX(*period, transinfo->period);
2900 0 : ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2901 : }
2902 0 : }
2903 :
2904 : /*
2905 : * Look up the valid period to SCSIRATE conversion in our table.
2906 : * Return the period and offset that should be sent to the target
2907 : * if this was the beginning of an SDTR.
2908 : */
2909 : void
2910 0 : ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2911 : u_int *ppr_options, u_int maxsync)
2912 : {
2913 0 : if (*period < maxsync)
2914 0 : *period = maxsync;
2915 :
2916 0 : if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2917 0 : && *period > AHD_SYNCRATE_MIN_DT)
2918 0 : *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2919 :
2920 0 : if (*period > AHD_SYNCRATE_MIN)
2921 0 : *period = 0;
2922 :
2923 : /* Honor PPR option conformance rules. */
2924 0 : if (*period > AHD_SYNCRATE_PACED)
2925 0 : *ppr_options &= ~MSG_EXT_PPR_RTI;
2926 :
2927 0 : if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2928 0 : *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2929 :
2930 0 : if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2931 0 : *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2932 :
2933 : /* Skip all PACED only entries if IU is not available */
2934 0 : if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2935 0 : && *period < AHD_SYNCRATE_DT)
2936 0 : *period = AHD_SYNCRATE_DT;
2937 :
2938 : /* Skip all DT only entries if DT is not available */
2939 0 : if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2940 0 : && *period < AHD_SYNCRATE_ULTRA2)
2941 0 : *period = AHD_SYNCRATE_ULTRA2;
2942 0 : }
2943 :
2944 : /*
2945 : * Truncate the given synchronous offset to a value the
2946 : * current adapter type and syncrate are capable of.
2947 : */
2948 : void
2949 0 : ahd_validate_offset(struct ahd_softc *ahd,
2950 : struct ahd_initiator_tinfo *tinfo,
2951 : u_int period, u_int *offset, int wide,
2952 : role_t role)
2953 : {
2954 : u_int maxoffset;
2955 :
2956 : /* Limit offset to what we can do */
2957 0 : if (period == 0)
2958 0 : maxoffset = 0;
2959 0 : else if (period <= AHD_SYNCRATE_PACED) {
2960 0 : if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2961 0 : maxoffset = MAX_OFFSET_PACED_BUG;
2962 : else
2963 : maxoffset = MAX_OFFSET_PACED;
2964 : } else
2965 : maxoffset = MAX_OFFSET_NON_PACED;
2966 0 : *offset = MIN(*offset, maxoffset);
2967 0 : if (tinfo != NULL) {
2968 0 : if (role == ROLE_TARGET)
2969 0 : *offset = MIN(*offset, tinfo->user.offset);
2970 : else
2971 0 : *offset = MIN(*offset, tinfo->goal.offset);
2972 : }
2973 0 : }
2974 :
2975 : /*
2976 : * Truncate the given transfer width parameter to a value the
2977 : * current adapter type is capable of.
2978 : */
2979 : void
2980 0 : ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
2981 : u_int *bus_width, role_t role)
2982 : {
2983 0 : switch (*bus_width) {
2984 : default:
2985 0 : if (ahd->features & AHD_WIDE) {
2986 : /* Respond Wide */
2987 0 : *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2988 0 : break;
2989 : }
2990 : /* FALLTHROUGH */
2991 : case MSG_EXT_WDTR_BUS_8_BIT:
2992 0 : *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2993 0 : break;
2994 : }
2995 0 : if (tinfo != NULL) {
2996 0 : if (role == ROLE_TARGET)
2997 0 : *bus_width = MIN(tinfo->user.width, *bus_width);
2998 : else
2999 0 : *bus_width = MIN(tinfo->goal.width, *bus_width);
3000 : }
3001 0 : }
3002 :
3003 : /*
3004 : * Update the bitmask of targets for which the controller should
3005 : * negotiate with at the next convenient oportunity. This currently
3006 : * means the next time we send the initial identify messages for
3007 : * a new transaction.
3008 : */
3009 : int
3010 0 : ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3011 : struct ahd_tmode_tstate *tstate,
3012 : struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
3013 : {
3014 : u_int auto_negotiate_orig;
3015 :
3016 0 : auto_negotiate_orig = tstate->auto_negotiate;
3017 0 : if (neg_type == AHD_NEG_ALWAYS) {
3018 : /*
3019 : * Force our "current" settings to be
3020 : * unknown so that unless a bus reset
3021 : * occurs the need to renegotiate is
3022 : * recorded persistently.
3023 : */
3024 0 : if ((ahd->features & AHD_WIDE) != 0)
3025 0 : tinfo->curr.width = AHD_WIDTH_UNKNOWN;
3026 0 : tinfo->curr.period = AHD_PERIOD_UNKNOWN;
3027 0 : tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
3028 0 : }
3029 0 : if (tinfo->curr.period != tinfo->goal.period
3030 0 : || tinfo->curr.width != tinfo->goal.width
3031 0 : || tinfo->curr.offset != tinfo->goal.offset
3032 0 : || tinfo->curr.ppr_options != tinfo->goal.ppr_options
3033 0 : || (neg_type == AHD_NEG_IF_NON_ASYNC
3034 0 : && (tinfo->goal.offset != 0
3035 0 : || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
3036 0 : || tinfo->goal.ppr_options != 0)))
3037 0 : tstate->auto_negotiate |= devinfo->target_mask;
3038 : else
3039 0 : tstate->auto_negotiate &= ~devinfo->target_mask;
3040 :
3041 0 : return (auto_negotiate_orig != tstate->auto_negotiate);
3042 : }
3043 :
3044 : /*
3045 : * Update the user/goal/curr tables of synchronous negotiation
3046 : * parameters as well as, in the case of a current or active update,
3047 : * any data structures on the host controller. In the case of an
3048 : * active update, the specified target is currently talking to us on
3049 : * the bus, so the transfer parameter update must take effect
3050 : * immediately.
3051 : */
3052 : void
3053 0 : ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3054 : u_int period, u_int offset, u_int ppr_options,
3055 : u_int type, int paused)
3056 : {
3057 : struct ahd_initiator_tinfo *tinfo;
3058 0 : struct ahd_tmode_tstate *tstate;
3059 : u_int old_period;
3060 : u_int old_offset;
3061 : u_int old_ppr;
3062 : int active;
3063 : int update_needed;
3064 :
3065 0 : active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3066 : update_needed = 0;
3067 :
3068 0 : if (period == 0 || offset == 0) {
3069 : period = 0;
3070 : offset = 0;
3071 0 : }
3072 :
3073 0 : tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3074 0 : devinfo->target, &tstate);
3075 :
3076 0 : if ((type & AHD_TRANS_USER) != 0) {
3077 0 : tinfo->user.period = period;
3078 0 : tinfo->user.offset = offset;
3079 0 : tinfo->user.ppr_options = ppr_options;
3080 0 : }
3081 :
3082 0 : if ((type & AHD_TRANS_GOAL) != 0) {
3083 0 : tinfo->goal.period = period;
3084 0 : tinfo->goal.offset = offset;
3085 0 : tinfo->goal.ppr_options = ppr_options;
3086 0 : }
3087 :
3088 0 : old_period = tinfo->curr.period;
3089 0 : old_offset = tinfo->curr.offset;
3090 0 : old_ppr = tinfo->curr.ppr_options;
3091 :
3092 0 : if ((type & AHD_TRANS_CUR) != 0
3093 0 : && (old_period != period
3094 0 : || old_offset != offset
3095 0 : || old_ppr != ppr_options)) {
3096 :
3097 : update_needed++;
3098 :
3099 0 : tinfo->curr.period = period;
3100 0 : tinfo->curr.offset = offset;
3101 0 : tinfo->curr.ppr_options = ppr_options;
3102 : #if 0
3103 : ahd_send_async(ahd, devinfo->channel, devinfo->target,
3104 : CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3105 : #endif
3106 : if (1 /*bootverbose*/) {
3107 0 : if (offset != 0) {
3108 : int options;
3109 :
3110 0 : printf("%s: target %d synchronous with "
3111 : "period = 0x%x, offset = 0x%x",
3112 0 : ahd_name(ahd), devinfo->target,
3113 : period, offset);
3114 : options = 0;
3115 0 : if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
3116 0 : printf("(RDSTRM");
3117 : options++;
3118 0 : }
3119 0 : if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
3120 0 : printf("%s", options ? "|DT" : "(DT");
3121 0 : options++;
3122 0 : }
3123 0 : if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3124 0 : printf("%s", options ? "|IU" : "(IU");
3125 0 : options++;
3126 0 : }
3127 0 : if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3128 0 : printf("%s", options ? "|RTI" : "(RTI");
3129 0 : options++;
3130 0 : }
3131 0 : if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3132 0 : printf("%s", options ? "|QAS" : "(QAS");
3133 0 : options++;
3134 0 : }
3135 0 : if (options != 0)
3136 0 : printf(")\n");
3137 : else
3138 0 : printf("\n");
3139 0 : } else {
3140 0 : printf("%s: target %d using "
3141 : "asynchronous transfers%s\n",
3142 0 : ahd_name(ahd), devinfo->target,
3143 0 : (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3144 : ? "(QAS)" : "");
3145 : }
3146 : }
3147 : }
3148 : /*
3149 : * Always refresh the neg-table to handle the case of the
3150 : * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3151 : * We will always renegotiate in that case if this is a
3152 : * packetized request. Also manage the busfree expected flag
3153 : * from this common routine so that we catch changes due to
3154 : * WDTR or SDTR messages.
3155 : */
3156 0 : if ((type & AHD_TRANS_CUR) != 0) {
3157 0 : if (!paused)
3158 0 : ahd_pause(ahd);
3159 0 : ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3160 0 : if (!paused)
3161 0 : ahd_unpause(ahd);
3162 0 : if (ahd->msg_type != MSG_TYPE_NONE) {
3163 0 : if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3164 0 : != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3165 : #ifdef AHD_DEBUG
3166 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3167 : ahd_print_devinfo(ahd, devinfo);
3168 : printf("Expecting IU Change busfree\n");
3169 : }
3170 : #endif
3171 0 : ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3172 : | MSG_FLAG_IU_REQ_CHANGED;
3173 0 : }
3174 0 : if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3175 : #ifdef AHD_DEBUG
3176 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3177 : printf("PPR with IU_REQ outstanding\n");
3178 : #endif
3179 0 : ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3180 0 : }
3181 : }
3182 : }
3183 :
3184 0 : update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3185 : tinfo, AHD_NEG_TO_GOAL);
3186 :
3187 0 : if (update_needed && active)
3188 0 : ahd_update_pending_scbs(ahd);
3189 0 : }
3190 :
3191 : /*
3192 : * Update the user/goal/curr tables of wide negotiation
3193 : * parameters as well as, in the case of a current or active update,
3194 : * any data structures on the host controller. In the case of an
3195 : * active update, the specified target is currently talking to us on
3196 : * the bus, so the transfer parameter update must take effect
3197 : * immediately.
3198 : */
3199 : void
3200 0 : ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3201 : u_int width, u_int type, int paused)
3202 : {
3203 : struct ahd_initiator_tinfo *tinfo;
3204 0 : struct ahd_tmode_tstate *tstate;
3205 : u_int oldwidth;
3206 : int active;
3207 : int update_needed;
3208 :
3209 0 : active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3210 : update_needed = 0;
3211 0 : tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3212 0 : devinfo->target, &tstate);
3213 :
3214 0 : if ((type & AHD_TRANS_USER) != 0)
3215 0 : tinfo->user.width = width;
3216 :
3217 0 : if ((type & AHD_TRANS_GOAL) != 0)
3218 0 : tinfo->goal.width = width;
3219 :
3220 0 : oldwidth = tinfo->curr.width;
3221 0 : if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
3222 :
3223 : update_needed++;
3224 :
3225 0 : tinfo->curr.width = width;
3226 : #if 0
3227 : ahd_send_async(ahd, devinfo->channel, devinfo->target,
3228 : CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3229 : #endif
3230 : if (bootverbose) {
3231 : printf("%s: target %d using %dbit transfers\n",
3232 : ahd_name(ahd), devinfo->target,
3233 : 8 * (0x01 << width));
3234 : }
3235 0 : }
3236 :
3237 0 : if ((type & AHD_TRANS_CUR) != 0) {
3238 0 : if (!paused)
3239 0 : ahd_pause(ahd);
3240 0 : ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3241 0 : if (!paused)
3242 0 : ahd_unpause(ahd);
3243 : }
3244 :
3245 0 : update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3246 : tinfo, AHD_NEG_TO_GOAL);
3247 0 : if (update_needed && active)
3248 0 : ahd_update_pending_scbs(ahd);
3249 :
3250 0 : }
3251 :
3252 : /*
3253 : * Update the current state of tagged queuing for a given target.
3254 : */
3255 : void
3256 0 : ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3257 : ahd_queue_alg alg)
3258 : {
3259 0 : ahd_platform_set_tags(ahd, devinfo, alg);
3260 : #if 0
3261 : ahd_send_async(ahd, devinfo->channel, devinfo->target,
3262 : devinfo->lun, AC_TRANSFER_NEG, &alg);
3263 : #endif
3264 0 : }
3265 :
3266 : void
3267 0 : ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3268 : struct ahd_transinfo *tinfo)
3269 : {
3270 : ahd_mode_state saved_modes;
3271 : u_int period;
3272 : u_int ppr_opts;
3273 : u_int con_opts;
3274 : u_int offset;
3275 : u_int saved_negoaddr;
3276 : uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
3277 :
3278 0 : saved_modes = ahd_save_modes(ahd);
3279 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3280 :
3281 0 : saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3282 0 : ahd_outb(ahd, NEGOADDR, devinfo->target);
3283 0 : period = tinfo->period;
3284 0 : offset = tinfo->offset;
3285 0 : memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3286 0 : ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3287 : |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3288 : con_opts = 0;
3289 0 : if (period == 0)
3290 0 : period = AHD_SYNCRATE_ASYNC;
3291 0 : if (period == AHD_SYNCRATE_160) {
3292 :
3293 0 : if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3294 : /*
3295 : * When the SPI4 spec was finalized, PACE transfers
3296 : * was not made a configurable option in the PPR
3297 : * message. Instead it is assumed to be enabled for
3298 : * any syncrate faster than 80MHz. Nevertheless,
3299 : * Harpoon2A4 allows this to be configurable.
3300 : *
3301 : * Harpoon2A4 also assumes at most 2 data bytes per
3302 : * negotiated REQ/ACK offset. Paced transfers take
3303 : * 4, so we must adjust our offset.
3304 : */
3305 0 : ppr_opts |= PPROPT_PACE;
3306 0 : offset *= 2;
3307 :
3308 : /*
3309 : * Harpoon2A assumed that there would be a
3310 : * fallback rate between 160MHz and 80MHz,
3311 : * so 7 is used as the period factor rather
3312 : * than 8 for 160MHz.
3313 : */
3314 : period = AHD_SYNCRATE_REVA_160;
3315 0 : }
3316 0 : if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3317 0 : iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3318 : ~AHD_PRECOMP_MASK;
3319 : } else {
3320 : /*
3321 : * Precomp should be disabled for non-paced transfers.
3322 : */
3323 0 : iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3324 :
3325 0 : if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3326 0 : && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
3327 0 : && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
3328 : /*
3329 : * Slow down our CRC interval to be
3330 : * compatible with non-packetized
3331 : * U160 devices that can't handle a
3332 : * CRC at full speed.
3333 : */
3334 : con_opts |= ENSLOWCRC;
3335 0 : }
3336 :
3337 0 : if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3338 : /*
3339 : * On H2A4, revert to a slower slewrate
3340 : * on non-paced transfers.
3341 : */
3342 0 : iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3343 : ~AHD_SLEWRATE_MASK;
3344 0 : }
3345 : }
3346 :
3347 0 : ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3348 0 : ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3349 0 : ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3350 0 : ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3351 :
3352 0 : ahd_outb(ahd, NEGPERIOD, period);
3353 0 : ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3354 0 : ahd_outb(ahd, NEGOFFSET, offset);
3355 :
3356 0 : if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3357 0 : con_opts |= WIDEXFER;
3358 :
3359 : /*
3360 : * During packetized transfers, the target will
3361 : * give us the oportunity to send command packets
3362 : * without us asserting attention.
3363 : */
3364 0 : if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3365 0 : con_opts |= ENAUTOATNO;
3366 0 : ahd_outb(ahd, NEGCONOPTS, con_opts);
3367 0 : ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3368 0 : ahd_restore_modes(ahd, saved_modes);
3369 0 : }
3370 :
3371 : /*
3372 : * When the transfer settings for a connection change, setup for
3373 : * negotiation in pending SCBs to effect the change as quickly as
3374 : * possible. We also cancel any negotiations that are scheduled
3375 : * for inflight SCBs that have not been started yet.
3376 : */
3377 : void
3378 0 : ahd_update_pending_scbs(struct ahd_softc *ahd)
3379 : {
3380 : struct scb *pending_scb;
3381 : int pending_scb_count;
3382 : int paused;
3383 : u_int saved_scbptr;
3384 : ahd_mode_state saved_modes;
3385 :
3386 : /*
3387 : * Traverse the pending SCB list and ensure that all of the
3388 : * SCBs there have the proper settings. We can only safely
3389 : * clear the negotiation required flag (setting requires the
3390 : * execution queue to be modified) and this is only possible
3391 : * if we are not already attempting to select out for this
3392 : * SCB. For this reason, all callers only call this routine
3393 : * if we are changing the negotiation settings for the currently
3394 : * active transaction on the bus.
3395 : */
3396 : pending_scb_count = 0;
3397 0 : TAILQ_FOREACH(pending_scb, &ahd->pending_scbs, next) {
3398 0 : struct ahd_devinfo devinfo;
3399 : struct ahd_initiator_tinfo *tinfo;
3400 0 : struct ahd_tmode_tstate *tstate;
3401 :
3402 0 : ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3403 0 : tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
3404 0 : devinfo.our_scsiid,
3405 0 : devinfo.target, &tstate);
3406 0 : if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3407 0 : && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3408 0 : pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3409 0 : pending_scb->hscb->control &= ~MK_MESSAGE;
3410 0 : }
3411 0 : ahd_sync_scb(ahd, pending_scb,
3412 : BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3413 0 : pending_scb_count++;
3414 0 : }
3415 :
3416 0 : if (pending_scb_count == 0)
3417 0 : return;
3418 :
3419 0 : if (ahd_is_paused(ahd)) {
3420 : paused = 1;
3421 0 : } else {
3422 : paused = 0;
3423 0 : ahd_pause(ahd);
3424 : }
3425 :
3426 : /*
3427 : * Force the sequencer to reinitialize the selection for
3428 : * the command at the head of the execution queue if it
3429 : * has already been setup. The negotiation changes may
3430 : * effect whether we select-out with ATN. It is only
3431 : * safe to clear ENSELO when the bus is not free and no
3432 : * selection is in progres or completed.
3433 : */
3434 0 : saved_modes = ahd_save_modes(ahd);
3435 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3436 0 : if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
3437 0 : && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
3438 0 : ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3439 0 : saved_scbptr = ahd_get_scbptr(ahd);
3440 : /* Ensure that the hscbs down on the card match the new information */
3441 0 : TAILQ_FOREACH(pending_scb, &ahd->pending_scbs, next) {
3442 : u_int scb_tag;
3443 : u_int control;
3444 :
3445 0 : scb_tag = SCB_GET_TAG(pending_scb);
3446 0 : ahd_set_scbptr(ahd, scb_tag);
3447 0 : control = ahd_inb_scbram(ahd, SCB_CONTROL);
3448 0 : control &= ~MK_MESSAGE;
3449 0 : control |= pending_scb->hscb->control & MK_MESSAGE;
3450 0 : ahd_outb(ahd, SCB_CONTROL, control);
3451 : }
3452 0 : ahd_set_scbptr(ahd, saved_scbptr);
3453 0 : ahd_restore_modes(ahd, saved_modes);
3454 :
3455 0 : if (paused == 0)
3456 0 : ahd_unpause(ahd);
3457 0 : }
3458 :
3459 : /**************************** Pathing Information *****************************/
3460 : void
3461 0 : ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3462 : {
3463 : ahd_mode_state saved_modes;
3464 : u_int saved_scsiid;
3465 : role_t role;
3466 : int our_id;
3467 :
3468 0 : saved_modes = ahd_save_modes(ahd);
3469 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3470 :
3471 0 : if (ahd_inb(ahd, SSTAT0) & TARGET)
3472 0 : role = ROLE_TARGET;
3473 : else
3474 : role = ROLE_INITIATOR;
3475 :
3476 0 : if (role == ROLE_TARGET
3477 0 : && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
3478 : /* We were selected, so pull our id from TARGIDIN */
3479 0 : our_id = ahd_inb(ahd, TARGIDIN) & OID;
3480 0 : } else if (role == ROLE_TARGET)
3481 0 : our_id = ahd_inb(ahd, TOWNID);
3482 : else
3483 0 : our_id = ahd_inb(ahd, IOWNID);
3484 :
3485 0 : saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
3486 0 : ahd_compile_devinfo(devinfo,
3487 : our_id,
3488 0 : SCSIID_TARGET(ahd, saved_scsiid),
3489 0 : ahd_inb(ahd, SAVED_LUN),
3490 : SCSIID_CHANNEL(ahd, saved_scsiid),
3491 : role);
3492 0 : ahd_restore_modes(ahd, saved_modes);
3493 0 : }
3494 :
3495 : void
3496 0 : ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3497 : {
3498 0 : printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3499 0 : devinfo->target, devinfo->lun);
3500 0 : }
3501 :
3502 : struct ahd_phase_table_entry*
3503 0 : ahd_lookup_phase_entry(int phase)
3504 : {
3505 : struct ahd_phase_table_entry *entry;
3506 : struct ahd_phase_table_entry *last_entry;
3507 :
3508 : /*
3509 : * num_phases doesn't include the default entry which
3510 : * will be returned if the phase doesn't match.
3511 : */
3512 : last_entry = &ahd_phase_table[num_phases];
3513 0 : for (entry = ahd_phase_table; entry < last_entry; entry++) {
3514 0 : if (phase == entry->phase)
3515 : break;
3516 : }
3517 0 : return (entry);
3518 : }
3519 :
3520 : void
3521 0 : ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
3522 : u_int lun, char channel, role_t role)
3523 : {
3524 0 : devinfo->our_scsiid = our_id;
3525 0 : devinfo->target = target;
3526 0 : devinfo->lun = lun;
3527 0 : devinfo->target_offset = target;
3528 0 : devinfo->channel = channel;
3529 0 : devinfo->role = role;
3530 0 : if (channel == 'B')
3531 0 : devinfo->target_offset += 8;
3532 0 : devinfo->target_mask = (0x01 << devinfo->target_offset);
3533 0 : }
3534 :
3535 : void
3536 0 : ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3537 : struct scb *scb)
3538 : {
3539 : role_t role;
3540 : int our_id;
3541 :
3542 0 : our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
3543 : role = ROLE_INITIATOR;
3544 0 : if ((scb->hscb->control & TARGET_SCB) != 0)
3545 0 : role = ROLE_TARGET;
3546 0 : ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
3547 0 : SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
3548 0 : }
3549 :
3550 :
3551 : /************************ Message Phase Processing ****************************/
3552 : /*
3553 : * When an initiator transaction with the MK_MESSAGE flag either reconnects
3554 : * or enters the initial message out phase, we are interrupted. Fill our
3555 : * outgoing message buffer with the appropriate message and beging handing
3556 : * the message phase(s) manually.
3557 : */
3558 : void
3559 0 : ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3560 : struct scb *scb)
3561 : {
3562 : /*
3563 : * To facilitate adding multiple messages together,
3564 : * each routine should increment the index and len
3565 : * variables instead of setting them explicitly.
3566 : */
3567 0 : ahd->msgout_index = 0;
3568 0 : ahd->msgout_len = 0;
3569 :
3570 0 : if (ahd_currently_packetized(ahd))
3571 0 : ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3572 :
3573 0 : if (ahd->send_msg_perror
3574 0 : && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3575 0 : ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3576 0 : ahd->msgout_len++;
3577 0 : ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3578 : #ifdef AHD_DEBUG
3579 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3580 : printf("Setting up for Parity Error delivery\n");
3581 : #endif
3582 0 : return;
3583 0 : } else if (scb == NULL) {
3584 0 : printf("%s: WARNING. No pending message for "
3585 0 : "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3586 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3587 0 : ahd->msgout_len++;
3588 0 : ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3589 0 : return;
3590 : }
3591 :
3592 0 : if ((scb->flags & SCB_DEVICE_RESET) == 0
3593 0 : && (scb->flags & SCB_PACKETIZED) == 0
3594 0 : && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
3595 : u_int identify_msg;
3596 :
3597 0 : identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
3598 0 : if ((scb->hscb->control & DISCENB) != 0)
3599 0 : identify_msg |= MSG_IDENTIFY_DISCFLAG;
3600 0 : ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
3601 0 : ahd->msgout_len++;
3602 :
3603 0 : if ((scb->hscb->control & TAG_ENB) != 0) {
3604 0 : ahd->msgout_buf[ahd->msgout_index++] =
3605 0 : scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
3606 0 : ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
3607 0 : ahd->msgout_len += 2;
3608 0 : }
3609 0 : }
3610 :
3611 0 : if (scb->flags & SCB_DEVICE_RESET) {
3612 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3613 0 : ahd->msgout_len++;
3614 0 : ahd_print_path(ahd, scb);
3615 0 : printf("Bus Device Reset Message Sent\n");
3616 : /*
3617 : * Clear our selection hardware in advance of
3618 : * the busfree. We may have an entry in the waiting
3619 : * Q for this target, and we don't want to go about
3620 : * selecting while we handle the busfree and blow it
3621 : * away.
3622 : */
3623 0 : ahd_outb(ahd, SCSISEQ0, 0);
3624 0 : } else if ((scb->flags & SCB_ABORT) != 0) {
3625 :
3626 0 : if ((scb->hscb->control & TAG_ENB) != 0) {
3627 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3628 0 : } else {
3629 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3630 : }
3631 0 : ahd->msgout_len++;
3632 0 : ahd_print_path(ahd, scb);
3633 0 : printf("Abort%s Message Sent\n",
3634 0 : (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3635 : /*
3636 : * Clear our selection hardware in advance of
3637 : * the busfree. We may have an entry in the waiting
3638 : * Q for this target, and we don't want to go about
3639 : * selecting while we handle the busfree and blow it
3640 : * away.
3641 : */
3642 0 : ahd_outb(ahd, SCSISEQ0, 0);
3643 0 : } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
3644 0 : ahd_build_transfer_msg(ahd, devinfo);
3645 : /*
3646 : * Clear our selection hardware in advance of potential
3647 : * PPR IU status change busfree. We may have an entry in
3648 : * the waiting Q for this target, and we don't want to go
3649 : * about selecting while we handle the busfree and blow
3650 : * it away.
3651 : */
3652 0 : ahd_outb(ahd, SCSISEQ0, 0);
3653 : } else {
3654 0 : printf("ahd_intr: AWAITING_MSG for an SCB that "
3655 : "does not have a waiting message\n");
3656 0 : printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3657 0 : devinfo->target_mask);
3658 0 : panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3659 0 : "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3660 0 : ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3661 0 : scb->flags);
3662 : }
3663 :
3664 : /*
3665 : * Clear the MK_MESSAGE flag from the SCB so we aren't
3666 : * asked to send this message again.
3667 : */
3668 0 : ahd_outb(ahd, SCB_CONTROL,
3669 : ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
3670 0 : scb->hscb->control &= ~MK_MESSAGE;
3671 0 : ahd->msgout_index = 0;
3672 0 : ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3673 0 : }
3674 :
3675 : /*
3676 : * Build an appropriate transfer negotiation message for the
3677 : * currently active target.
3678 : */
3679 : void
3680 0 : ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3681 : {
3682 : /*
3683 : * We need to initiate transfer negotiations.
3684 : * If our current and goal settings are identical,
3685 : * we want to renegotiate due to a check condition.
3686 : */
3687 : struct ahd_initiator_tinfo *tinfo;
3688 0 : struct ahd_tmode_tstate *tstate;
3689 : int dowide;
3690 : int dosync;
3691 : int doppr;
3692 0 : u_int period;
3693 0 : u_int ppr_options;
3694 0 : u_int offset;
3695 :
3696 0 : tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3697 0 : devinfo->target, &tstate);
3698 : /*
3699 : * Filter our period based on the current connection.
3700 : * If we can't perform DT transfers on this segment (not in LVD
3701 : * mode for instance), then our decision to issue a PPR message
3702 : * may change.
3703 : */
3704 0 : period = tinfo->goal.period;
3705 0 : offset = tinfo->goal.offset;
3706 0 : ppr_options = tinfo->goal.ppr_options;
3707 : /* Target initiated PPR is not allowed in the SCSI spec */
3708 0 : if (devinfo->role == ROLE_TARGET)
3709 : ppr_options = 0;
3710 0 : ahd_devlimited_syncrate(ahd, tinfo, &period,
3711 0 : &ppr_options, devinfo->role);
3712 0 : dowide = tinfo->curr.width != tinfo->goal.width;
3713 0 : dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3714 : /*
3715 : * Only use PPR if we have options that need it, even if the device
3716 : * claims to support it. There might be an expander in the way
3717 : * that doesn't.
3718 : */
3719 0 : doppr = ppr_options != 0;
3720 :
3721 0 : if (!dowide && !dosync && !doppr) {
3722 0 : dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3723 0 : dosync = tinfo->goal.offset != 0;
3724 0 : }
3725 :
3726 0 : if (!dowide && !dosync && !doppr) {
3727 : /*
3728 : * Force async with a WDTR message if we have a wide bus,
3729 : * or just issue an SDTR with a 0 offset.
3730 : */
3731 0 : if ((ahd->features & AHD_WIDE) != 0)
3732 0 : dowide = 1;
3733 : else
3734 : dosync = 1;
3735 :
3736 : if (bootverbose) {
3737 : ahd_print_devinfo(ahd, devinfo);
3738 : printf("Ensuring async\n");
3739 : }
3740 : }
3741 : /* Target initiated PPR is not allowed in the SCSI spec */
3742 0 : if (devinfo->role == ROLE_TARGET)
3743 0 : doppr = 0;
3744 :
3745 : /*
3746 : * Both the PPR message and SDTR message require the
3747 : * goal syncrate to be limited to what the target device
3748 : * is capable of handling (based on whether an LVD->SE
3749 : * expander is on the bus), so combine these two cases.
3750 : * Regardless, guarantee that if we are using WDTR and SDTR
3751 : * messages that WDTR comes first.
3752 : */
3753 0 : if (doppr || (dosync && !dowide)) {
3754 :
3755 0 : offset = tinfo->goal.offset;
3756 0 : ahd_validate_offset(ahd, tinfo, period, &offset,
3757 0 : doppr ? tinfo->goal.width
3758 0 : : tinfo->curr.width,
3759 0 : devinfo->role);
3760 0 : if (doppr) {
3761 0 : ahd_construct_ppr(ahd, devinfo, period, offset,
3762 0 : tinfo->goal.width, ppr_options);
3763 0 : } else {
3764 0 : ahd_construct_sdtr(ahd, devinfo, period, offset);
3765 : }
3766 : } else {
3767 0 : ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3768 : }
3769 0 : }
3770 :
3771 : /*
3772 : * Build a synchronous negotiation message in our message
3773 : * buffer based on the input parameters.
3774 : */
3775 : void
3776 0 : ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3777 : u_int period, u_int offset)
3778 : {
3779 0 : if (offset == 0)
3780 0 : period = AHD_ASYNC_XFER_PERIOD;
3781 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3782 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
3783 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
3784 0 : ahd->msgout_buf[ahd->msgout_index++] = period;
3785 0 : ahd->msgout_buf[ahd->msgout_index++] = offset;
3786 0 : ahd->msgout_len += 5;
3787 : if (bootverbose) {
3788 : printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3789 : ahd_name(ahd), devinfo->channel, devinfo->target,
3790 : devinfo->lun, period, offset);
3791 : }
3792 0 : }
3793 :
3794 : /*
3795 : * Build a wide negotiateion message in our message
3796 : * buffer based on the input parameters.
3797 : */
3798 : void
3799 0 : ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3800 : u_int bus_width)
3801 : {
3802 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3803 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN;
3804 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR;
3805 0 : ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3806 0 : ahd->msgout_len += 4;
3807 : if (bootverbose) {
3808 : printf("(%s:%c:%d:%d): Sending WDTR %x\n",
3809 : ahd_name(ahd), devinfo->channel, devinfo->target,
3810 : devinfo->lun, bus_width);
3811 : }
3812 0 : }
3813 :
3814 : /*
3815 : * Build a parallel protocol request message in our message
3816 : * buffer based on the input parameters.
3817 : */
3818 : void
3819 0 : ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3820 : u_int period, u_int offset, u_int bus_width,
3821 : u_int ppr_options)
3822 : {
3823 : /*
3824 : * Always request precompensation from
3825 : * the other target if we are running
3826 : * at paced syncrates.
3827 : */
3828 0 : if (period <= AHD_SYNCRATE_PACED)
3829 0 : ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3830 0 : if (offset == 0)
3831 0 : period = AHD_ASYNC_XFER_PERIOD;
3832 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3833 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
3834 0 : ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
3835 0 : ahd->msgout_buf[ahd->msgout_index++] = period;
3836 0 : ahd->msgout_buf[ahd->msgout_index++] = 0;
3837 0 : ahd->msgout_buf[ahd->msgout_index++] = offset;
3838 0 : ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3839 0 : ahd->msgout_buf[ahd->msgout_index++] = ppr_options;
3840 0 : ahd->msgout_len += 8;
3841 : if (bootverbose) {
3842 : printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3843 : "offset %x, ppr_options %x\n", ahd_name(ahd),
3844 : devinfo->channel, devinfo->target, devinfo->lun,
3845 : bus_width, period, offset, ppr_options);
3846 : }
3847 0 : }
3848 :
3849 : /*
3850 : * Clear any active message state.
3851 : */
3852 : void
3853 0 : ahd_clear_msg_state(struct ahd_softc *ahd)
3854 : {
3855 : ahd_mode_state saved_modes;
3856 :
3857 0 : saved_modes = ahd_save_modes(ahd);
3858 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3859 0 : ahd->send_msg_perror = 0;
3860 0 : ahd->msg_flags = MSG_FLAG_NONE;
3861 0 : ahd->msgout_len = 0;
3862 0 : ahd->msgin_index = 0;
3863 0 : ahd->msg_type = MSG_TYPE_NONE;
3864 0 : if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
3865 : /*
3866 : * The target didn't care to respond to our
3867 : * message request, so clear ATN.
3868 : */
3869 0 : ahd_outb(ahd, CLRSINT1, CLRATNO);
3870 0 : }
3871 0 : ahd_outb(ahd, MSG_OUT, MSG_NOOP);
3872 0 : ahd_outb(ahd, SEQ_FLAGS2,
3873 : ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3874 0 : ahd_restore_modes(ahd, saved_modes);
3875 0 : }
3876 :
3877 : /*
3878 : * Manual message loop handler.
3879 : */
3880 : void
3881 0 : ahd_handle_message_phase(struct ahd_softc *ahd)
3882 : {
3883 0 : struct ahd_devinfo devinfo;
3884 : u_int bus_phase;
3885 : int end_session;
3886 :
3887 0 : ahd_fetch_devinfo(ahd, &devinfo);
3888 : end_session = FALSE;
3889 0 : bus_phase = ahd_inb(ahd, LASTPHASE);
3890 :
3891 0 : if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
3892 0 : printf("LQIRETRY for LQIPHASE_OUTPKT\n");
3893 0 : ahd_outb(ahd, LQCTL2, LQIRETRY);
3894 0 : }
3895 : reswitch:
3896 0 : switch (ahd->msg_type) {
3897 : case MSG_TYPE_INITIATOR_MSGOUT:
3898 : {
3899 : int lastbyte;
3900 : int phasemis;
3901 : int msgdone;
3902 :
3903 0 : if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3904 0 : panic("HOST_MSG_LOOP interrupt with no active message");
3905 :
3906 : #ifdef AHD_DEBUG
3907 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3908 : ahd_print_devinfo(ahd, &devinfo);
3909 : printf("INITIATOR_MSG_OUT");
3910 : }
3911 : #endif
3912 0 : phasemis = bus_phase != P_MESGOUT;
3913 0 : if (phasemis) {
3914 : #ifdef AHD_DEBUG
3915 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3916 : printf(" PHASEMIS %s\n",
3917 : ahd_lookup_phase_entry(bus_phase)
3918 : ->phasemsg);
3919 : }
3920 : #endif
3921 0 : if (bus_phase == P_MESGIN) {
3922 : /*
3923 : * Change gears and see if
3924 : * this messages is of interest to
3925 : * us or should be passed back to
3926 : * the sequencer.
3927 : */
3928 0 : ahd_outb(ahd, CLRSINT1, CLRATNO);
3929 0 : ahd->send_msg_perror = 0;
3930 0 : ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3931 0 : ahd->msgin_index = 0;
3932 0 : goto reswitch;
3933 : }
3934 : end_session = TRUE;
3935 0 : break;
3936 : }
3937 :
3938 0 : if (ahd->send_msg_perror) {
3939 0 : ahd_outb(ahd, CLRSINT1, CLRATNO);
3940 0 : ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3941 : #ifdef AHD_DEBUG
3942 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3943 : printf(" byte 0x%x\n", ahd->send_msg_perror);
3944 : #endif
3945 : /*
3946 : * If we are notifying the target of a CRC error
3947 : * during packetized operations, the target is
3948 : * within its rights to acknowledge our message
3949 : * with a busfree.
3950 : */
3951 0 : if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
3952 0 : && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
3953 0 : ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
3954 :
3955 0 : ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
3956 0 : ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3957 0 : break;
3958 : }
3959 :
3960 0 : msgdone = ahd->msgout_index == ahd->msgout_len;
3961 0 : if (msgdone) {
3962 : /*
3963 : * The target has requested a retry.
3964 : * Re-assert ATN, reset our message index to
3965 : * 0, and try again.
3966 : */
3967 0 : ahd->msgout_index = 0;
3968 0 : ahd_assert_atn(ahd);
3969 0 : }
3970 :
3971 0 : lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
3972 0 : if (lastbyte) {
3973 : /* Last byte is signified by dropping ATN */
3974 0 : ahd_outb(ahd, CLRSINT1, CLRATNO);
3975 0 : }
3976 :
3977 : /*
3978 : * Clear our interrupt status and present
3979 : * the next byte on the bus.
3980 : */
3981 0 : ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3982 : #ifdef AHD_DEBUG
3983 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3984 : printf(" byte 0x%x\n",
3985 : ahd->msgout_buf[ahd->msgout_index]);
3986 : #endif
3987 0 : ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
3988 0 : ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3989 0 : break;
3990 : }
3991 : case MSG_TYPE_INITIATOR_MSGIN:
3992 : {
3993 : int phasemis;
3994 : int message_done;
3995 :
3996 : #ifdef AHD_DEBUG
3997 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3998 : ahd_print_devinfo(ahd, &devinfo);
3999 : printf("INITIATOR_MSG_IN");
4000 : }
4001 : #endif
4002 0 : phasemis = bus_phase != P_MESGIN;
4003 0 : if (phasemis) {
4004 : #ifdef AHD_DEBUG
4005 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4006 : printf(" PHASEMIS %s\n",
4007 : ahd_lookup_phase_entry(bus_phase)
4008 : ->phasemsg);
4009 : }
4010 : #endif
4011 0 : ahd->msgin_index = 0;
4012 0 : if (bus_phase == P_MESGOUT
4013 0 : && (ahd->send_msg_perror != 0
4014 0 : || (ahd->msgout_len != 0
4015 0 : && ahd->msgout_index == 0))) {
4016 0 : ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
4017 0 : goto reswitch;
4018 : }
4019 : end_session = TRUE;
4020 0 : break;
4021 : }
4022 :
4023 : /* Pull the byte in without acking it */
4024 0 : ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
4025 : #ifdef AHD_DEBUG
4026 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4027 : printf(" byte 0x%x\n",
4028 : ahd->msgin_buf[ahd->msgin_index]);
4029 : #endif
4030 :
4031 0 : message_done = ahd_parse_msg(ahd, &devinfo);
4032 :
4033 0 : if (message_done) {
4034 : /*
4035 : * Clear our incoming message buffer in case there
4036 : * is another message following this one.
4037 : */
4038 0 : ahd->msgin_index = 0;
4039 :
4040 : /*
4041 : * If this message illicited a response,
4042 : * assert ATN so the target takes us to the
4043 : * message out phase.
4044 : */
4045 0 : if (ahd->msgout_len != 0) {
4046 : #ifdef AHD_DEBUG
4047 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4048 : ahd_print_devinfo(ahd, &devinfo);
4049 : printf("Asserting ATN for response\n");
4050 : }
4051 : #endif
4052 0 : ahd_assert_atn(ahd);
4053 0 : }
4054 : } else
4055 0 : ahd->msgin_index++;
4056 :
4057 0 : if (message_done == MSGLOOP_TERMINATED) {
4058 : end_session = TRUE;
4059 0 : } else {
4060 : /* Ack the byte */
4061 0 : ahd_outb(ahd, CLRSINT1, CLRREQINIT);
4062 0 : ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
4063 : }
4064 0 : break;
4065 : }
4066 : case MSG_TYPE_TARGET_MSGIN:
4067 : {
4068 : int msgdone;
4069 : int msgout_request;
4070 :
4071 : /*
4072 : * By default, the message loop will continue.
4073 : */
4074 0 : ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4075 :
4076 0 : if (ahd->msgout_len == 0)
4077 0 : panic("Target MSGIN with no active message");
4078 :
4079 : /*
4080 : * If we interrupted a mesgout session, the initiator
4081 : * will not know this until our first REQ. So, we
4082 : * only honor mesgout requests after we've sent our
4083 : * first byte.
4084 : */
4085 0 : if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
4086 0 : && ahd->msgout_index > 0)
4087 0 : msgout_request = TRUE;
4088 : else
4089 : msgout_request = FALSE;
4090 :
4091 0 : if (msgout_request) {
4092 :
4093 : /*
4094 : * Change gears and see if
4095 : * this messages is of interest to
4096 : * us or should be passed back to
4097 : * the sequencer.
4098 : */
4099 0 : ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
4100 0 : ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
4101 0 : ahd->msgin_index = 0;
4102 : /* Dummy read to REQ for first byte */
4103 0 : ahd_inb(ahd, SCSIDAT);
4104 0 : ahd_outb(ahd, SXFRCTL0,
4105 : ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4106 0 : break;
4107 : }
4108 :
4109 0 : msgdone = ahd->msgout_index == ahd->msgout_len;
4110 0 : if (msgdone) {
4111 0 : ahd_outb(ahd, SXFRCTL0,
4112 : ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4113 : end_session = TRUE;
4114 0 : break;
4115 : }
4116 :
4117 : /*
4118 : * Present the next byte on the bus.
4119 : */
4120 0 : ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4121 0 : ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
4122 0 : break;
4123 : }
4124 : case MSG_TYPE_TARGET_MSGOUT:
4125 : {
4126 : int lastbyte;
4127 : int msgdone;
4128 :
4129 : /*
4130 : * By default, the message loop will continue.
4131 : */
4132 0 : ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4133 :
4134 : /*
4135 : * The initiator signals that this is
4136 : * the last byte by dropping ATN.
4137 : */
4138 0 : lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
4139 :
4140 : /*
4141 : * Read the latched byte, but turn off SPIOEN first
4142 : * so that we don't inadvertently cause a REQ for the
4143 : * next byte.
4144 : */
4145 0 : ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4146 0 : ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
4147 0 : msgdone = ahd_parse_msg(ahd, &devinfo);
4148 0 : if (msgdone == MSGLOOP_TERMINATED) {
4149 : /*
4150 : * The message is *really* done in that it caused
4151 : * us to go to bus free. The sequencer has already
4152 : * been reset at this point, so pull the ejection
4153 : * handle.
4154 : */
4155 0 : return;
4156 : }
4157 :
4158 0 : ahd->msgin_index++;
4159 :
4160 : /*
4161 : * XXX Read spec about initiator dropping ATN too soon
4162 : * and use msgdone to detect it.
4163 : */
4164 0 : if (msgdone == MSGLOOP_MSGCOMPLETE) {
4165 0 : ahd->msgin_index = 0;
4166 :
4167 : /*
4168 : * If this message illicited a response, transition
4169 : * to the Message in phase and send it.
4170 : */
4171 0 : if (ahd->msgout_len != 0) {
4172 0 : ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
4173 0 : ahd_outb(ahd, SXFRCTL0,
4174 : ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4175 0 : ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4176 0 : ahd->msgin_index = 0;
4177 0 : break;
4178 : }
4179 : }
4180 :
4181 0 : if (lastbyte)
4182 0 : end_session = TRUE;
4183 : else {
4184 : /* Ask for the next byte. */
4185 0 : ahd_outb(ahd, SXFRCTL0,
4186 : ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4187 : }
4188 :
4189 0 : break;
4190 : }
4191 : default:
4192 0 : panic("Unknown REQINIT message type");
4193 : }
4194 :
4195 0 : if (end_session) {
4196 0 : if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4197 0 : printf("%s: Returning to Idle Loop\n",
4198 0 : ahd_name(ahd));
4199 0 : ahd_clear_msg_state(ahd);
4200 :
4201 : /*
4202 : * Perform the equivalent of a clear_target_state.
4203 : */
4204 0 : ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4205 0 : ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
4206 0 : ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4207 0 : } else {
4208 0 : ahd_clear_msg_state(ahd);
4209 0 : ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4210 : }
4211 : }
4212 0 : }
4213 :
4214 : /*
4215 : * See if we sent a particular extended message to the target.
4216 : * If "full" is true, return true only if the target saw the full
4217 : * message. If "full" is false, return true if the target saw at
4218 : * least the first byte of the message.
4219 : */
4220 : int
4221 0 : ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
4222 : {
4223 : int found;
4224 : u_int index;
4225 :
4226 : found = FALSE;
4227 : index = 0;
4228 :
4229 0 : while (index < ahd->msgout_len) {
4230 0 : if (ahd->msgout_buf[index] == MSG_EXTENDED) {
4231 : u_int end_index;
4232 :
4233 0 : end_index = index + 1 + ahd->msgout_buf[index + 1];
4234 0 : if (ahd->msgout_buf[index+2] == msgval
4235 0 : && type == AHDMSG_EXT) {
4236 :
4237 0 : if (full) {
4238 0 : if (ahd->msgout_index > end_index)
4239 0 : found = TRUE;
4240 0 : } else if (ahd->msgout_index > index)
4241 0 : found = TRUE;
4242 : }
4243 : index = end_index;
4244 0 : } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4245 0 : && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4246 :
4247 : /* Skip tag type and tag id or residue param*/
4248 0 : index += 2;
4249 0 : } else {
4250 : /* Single byte message */
4251 0 : if (type == AHDMSG_1B
4252 0 : && ahd->msgout_index > index
4253 0 : && (ahd->msgout_buf[index] == msgval
4254 0 : || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4255 0 : && msgval == MSG_IDENTIFYFLAG)))
4256 0 : found = TRUE;
4257 0 : index++;
4258 : }
4259 :
4260 0 : if (found)
4261 : break;
4262 : }
4263 0 : return (found);
4264 : }
4265 :
4266 : /*
4267 : * Wait for a complete incoming message, parse it, and respond accordingly.
4268 : */
4269 : int
4270 0 : ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4271 : {
4272 : struct ahd_initiator_tinfo *tinfo;
4273 0 : struct ahd_tmode_tstate *tstate;
4274 : int reject;
4275 : int done;
4276 : int response;
4277 :
4278 : done = MSGLOOP_IN_PROG;
4279 : response = FALSE;
4280 : reject = FALSE;
4281 0 : tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4282 0 : devinfo->target, &tstate);
4283 :
4284 : /*
4285 : * Parse as much of the message as is available,
4286 : * rejecting it if we don't support it. When
4287 : * the entire message is available and has been
4288 : * handled, return MSGLOOP_MSGCOMPLETE, indicating
4289 : * that we have parsed an entire message.
4290 : *
4291 : * In the case of extended messages, we accept the length
4292 : * byte outright and perform more checking once we know the
4293 : * extended message type.
4294 : */
4295 0 : switch (ahd->msgin_buf[0]) {
4296 : case MSG_DISCONNECT:
4297 : case MSG_SAVEDATAPOINTER:
4298 : case MSG_CMDCOMPLETE:
4299 : case MSG_RESTOREPOINTERS:
4300 : case MSG_IGN_WIDE_RESIDUE:
4301 : /*
4302 : * End our message loop as these are messages
4303 : * the sequencer handles on its own.
4304 : */
4305 : done = MSGLOOP_TERMINATED;
4306 0 : break;
4307 : case MSG_MESSAGE_REJECT:
4308 0 : response = ahd_handle_msg_reject(ahd, devinfo);
4309 : /* FALLTHROUGH */
4310 : case MSG_NOOP:
4311 : done = MSGLOOP_MSGCOMPLETE;
4312 0 : break;
4313 : case MSG_EXTENDED:
4314 : {
4315 : /* Wait for enough of the message to begin validation */
4316 0 : if (ahd->msgin_index < 2)
4317 : break;
4318 0 : switch (ahd->msgin_buf[2]) {
4319 : case MSG_EXT_SDTR:
4320 : {
4321 0 : u_int period;
4322 0 : u_int ppr_options;
4323 0 : u_int offset;
4324 : u_int saved_offset;
4325 :
4326 0 : if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
4327 : reject = TRUE;
4328 0 : break;
4329 : }
4330 :
4331 : /*
4332 : * Wait until we have both args before validating
4333 : * and acting on this message.
4334 : *
4335 : * Add one to MSG_EXT_SDTR_LEN to account for
4336 : * the extended message preamble.
4337 : */
4338 0 : if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
4339 0 : break;
4340 :
4341 0 : period = ahd->msgin_buf[3];
4342 0 : ppr_options = 0;
4343 0 : saved_offset = offset = ahd->msgin_buf[4];
4344 0 : ahd_devlimited_syncrate(ahd, tinfo, &period,
4345 0 : &ppr_options, devinfo->role);
4346 0 : ahd_validate_offset(ahd, tinfo, period, &offset,
4347 0 : tinfo->curr.width, devinfo->role);
4348 : if (bootverbose) {
4349 : printf("(%s:%c:%d:%d): Received "
4350 : "SDTR period %x, offset %x\n\t"
4351 : "Filtered to period %x, offset %x\n",
4352 : ahd_name(ahd), devinfo->channel,
4353 : devinfo->target, devinfo->lun,
4354 : ahd->msgin_buf[3], saved_offset,
4355 : period, offset);
4356 : }
4357 0 : ahd_set_syncrate(ahd, devinfo, period,
4358 0 : offset, ppr_options,
4359 : AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4360 : /*paused*/TRUE);
4361 :
4362 : /*
4363 : * See if we initiated Sync Negotiation
4364 : * and didn't have to fall down to async
4365 : * transfers.
4366 : */
4367 0 : if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
4368 : /* We started it */
4369 0 : if (saved_offset != offset) {
4370 : /* Went too low - force async */
4371 : reject = TRUE;
4372 0 : }
4373 : } else {
4374 : /*
4375 : * Send our own SDTR in reply
4376 : */
4377 : if (bootverbose
4378 : && devinfo->role == ROLE_INITIATOR) {
4379 : printf("(%s:%c:%d:%d): Target "
4380 : "Initiated SDTR\n",
4381 : ahd_name(ahd), devinfo->channel,
4382 : devinfo->target, devinfo->lun);
4383 : }
4384 0 : ahd->msgout_index = 0;
4385 0 : ahd->msgout_len = 0;
4386 0 : ahd_construct_sdtr(ahd, devinfo,
4387 0 : period, offset);
4388 0 : ahd->msgout_index = 0;
4389 : response = TRUE;
4390 : }
4391 : done = MSGLOOP_MSGCOMPLETE;
4392 0 : break;
4393 0 : }
4394 : case MSG_EXT_WDTR:
4395 : {
4396 0 : u_int bus_width;
4397 : u_int saved_width;
4398 : u_int sending_reply;
4399 :
4400 : sending_reply = FALSE;
4401 0 : if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
4402 : reject = TRUE;
4403 0 : break;
4404 : }
4405 :
4406 : /*
4407 : * Wait until we have our arg before validating
4408 : * and acting on this message.
4409 : *
4410 : * Add one to MSG_EXT_WDTR_LEN to account for
4411 : * the extended message preamble.
4412 : */
4413 0 : if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
4414 0 : break;
4415 :
4416 0 : bus_width = ahd->msgin_buf[3];
4417 : saved_width = bus_width;
4418 0 : ahd_validate_width(ahd, tinfo, &bus_width,
4419 0 : devinfo->role);
4420 : if (bootverbose) {
4421 : printf("(%s:%c:%d:%d): Received WDTR "
4422 : "%x filtered to %x\n",
4423 : ahd_name(ahd), devinfo->channel,
4424 : devinfo->target, devinfo->lun,
4425 : saved_width, bus_width);
4426 : }
4427 :
4428 0 : if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
4429 : /*
4430 : * Don't send a WDTR back to the
4431 : * target, since we asked first.
4432 : * If the width went higher than our
4433 : * request, reject it.
4434 : */
4435 0 : if (saved_width > bus_width) {
4436 : reject = TRUE;
4437 0 : printf("(%s:%c:%d:%d): requested %dBit "
4438 : "transfers. Rejecting...\n",
4439 0 : ahd_name(ahd), devinfo->channel,
4440 0 : devinfo->target, devinfo->lun,
4441 0 : 8 * (0x01 << bus_width));
4442 0 : bus_width = 0;
4443 0 : }
4444 : } else {
4445 : /*
4446 : * Send our own WDTR in reply
4447 : */
4448 : if (bootverbose
4449 : && devinfo->role == ROLE_INITIATOR) {
4450 : printf("(%s:%c:%d:%d): Target "
4451 : "Initiated WDTR\n",
4452 : ahd_name(ahd), devinfo->channel,
4453 : devinfo->target, devinfo->lun);
4454 : }
4455 0 : ahd->msgout_index = 0;
4456 0 : ahd->msgout_len = 0;
4457 0 : ahd_construct_wdtr(ahd, devinfo, bus_width);
4458 0 : ahd->msgout_index = 0;
4459 : response = TRUE;
4460 : sending_reply = TRUE;
4461 : }
4462 : /*
4463 : * After a wide message, we are async, but
4464 : * some devices don't seem to honor this portion
4465 : * of the spec. Force a renegotiation of the
4466 : * sync component of our transfer agreement even
4467 : * if our goal is async. By updating our width
4468 : * after forcing the negotiation, we avoid
4469 : * renegotiating for width.
4470 : */
4471 0 : ahd_update_neg_request(ahd, devinfo, tstate,
4472 : tinfo, AHD_NEG_ALWAYS);
4473 0 : ahd_set_width(ahd, devinfo, bus_width,
4474 : AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4475 : /*paused*/TRUE);
4476 0 : if (sending_reply == FALSE && reject == FALSE) {
4477 :
4478 : /*
4479 : * We will always have an SDTR to send.
4480 : */
4481 0 : ahd->msgout_index = 0;
4482 0 : ahd->msgout_len = 0;
4483 0 : ahd_build_transfer_msg(ahd, devinfo);
4484 0 : ahd->msgout_index = 0;
4485 : response = TRUE;
4486 0 : }
4487 : done = MSGLOOP_MSGCOMPLETE;
4488 0 : break;
4489 0 : }
4490 : case MSG_EXT_PPR:
4491 : {
4492 0 : u_int period;
4493 0 : u_int offset;
4494 0 : u_int bus_width;
4495 0 : u_int ppr_options;
4496 : u_int saved_width;
4497 : u_int saved_offset;
4498 : u_int saved_ppr_options;
4499 :
4500 0 : if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
4501 : reject = TRUE;
4502 0 : break;
4503 : }
4504 :
4505 : /*
4506 : * Wait until we have all args before validating
4507 : * and acting on this message.
4508 : *
4509 : * Add one to MSG_EXT_PPR_LEN to account for
4510 : * the extended message preamble.
4511 : */
4512 0 : if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
4513 0 : break;
4514 :
4515 0 : period = ahd->msgin_buf[3];
4516 0 : offset = ahd->msgin_buf[5];
4517 0 : bus_width = ahd->msgin_buf[6];
4518 : saved_width = bus_width;
4519 0 : ppr_options = ahd->msgin_buf[7];
4520 : /*
4521 : * According to the spec, a DT only
4522 : * period factor with no DT option
4523 : * set implies async.
4524 : */
4525 0 : if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
4526 0 : && period <= 9)
4527 0 : offset = 0;
4528 0 : saved_ppr_options = ppr_options;
4529 0 : saved_offset = offset;
4530 :
4531 : /*
4532 : * Transfer options are only available if we
4533 : * are negotiating wide.
4534 : */
4535 0 : if (bus_width == 0)
4536 0 : ppr_options &= MSG_EXT_PPR_QAS_REQ;
4537 :
4538 0 : ahd_validate_width(ahd, tinfo, &bus_width,
4539 0 : devinfo->role);
4540 0 : ahd_devlimited_syncrate(ahd, tinfo, &period,
4541 0 : &ppr_options, devinfo->role);
4542 0 : ahd_validate_offset(ahd, tinfo, period, &offset,
4543 0 : bus_width, devinfo->role);
4544 :
4545 0 : if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
4546 : /*
4547 : * If we are unable to do any of the
4548 : * requested options (we went too low),
4549 : * then we'll have to reject the message.
4550 : */
4551 0 : if (saved_width > bus_width
4552 0 : || saved_offset != offset
4553 0 : || saved_ppr_options != ppr_options) {
4554 : reject = TRUE;
4555 0 : period = 0;
4556 0 : offset = 0;
4557 0 : bus_width = 0;
4558 0 : ppr_options = 0;
4559 0 : }
4560 : } else {
4561 0 : if (devinfo->role != ROLE_TARGET)
4562 0 : printf("(%s:%c:%d:%d): Target "
4563 : "Initiated PPR\n",
4564 : ahd_name(ahd), devinfo->channel,
4565 : devinfo->target, devinfo->lun);
4566 : else
4567 0 : printf("(%s:%c:%d:%d): Initiator "
4568 : "Initiated PPR\n",
4569 : ahd_name(ahd), devinfo->channel,
4570 : devinfo->target, devinfo->lun);
4571 0 : ahd->msgout_index = 0;
4572 0 : ahd->msgout_len = 0;
4573 0 : ahd_construct_ppr(ahd, devinfo, period, offset,
4574 0 : bus_width, ppr_options);
4575 0 : ahd->msgout_index = 0;
4576 : response = TRUE;
4577 : }
4578 : if (bootverbose) {
4579 : printf("(%s:%c:%d:%d): Received PPR width %x, "
4580 : "period %x, offset %x,options %x\n"
4581 : "\tFiltered to width %x, period %x, "
4582 : "offset %x, options %x\n",
4583 : ahd_name(ahd), devinfo->channel,
4584 : devinfo->target, devinfo->lun,
4585 : saved_width, ahd->msgin_buf[3],
4586 : saved_offset, saved_ppr_options,
4587 : bus_width, period, offset, ppr_options);
4588 : }
4589 0 : ahd_set_width(ahd, devinfo, bus_width,
4590 : AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4591 : /*paused*/TRUE);
4592 0 : ahd_set_syncrate(ahd, devinfo, period,
4593 0 : offset, ppr_options,
4594 : AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4595 : /*paused*/TRUE);
4596 :
4597 : done = MSGLOOP_MSGCOMPLETE;
4598 0 : break;
4599 0 : }
4600 : default:
4601 : /* Unknown extended message. Reject it. */
4602 : reject = TRUE;
4603 0 : break;
4604 : }
4605 : break;
4606 : }
4607 : #ifdef AHD_TARGET_MODE
4608 : case MSG_BUS_DEV_RESET:
4609 : ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
4610 : CAM_BDR_SENT,
4611 : "Bus Device Reset Received",
4612 : /*verbose_level*/0);
4613 : ahd_restart(ahd);
4614 : done = MSGLOOP_TERMINATED;
4615 : break;
4616 : case MSG_ABORT_TAG:
4617 : case MSG_ABORT:
4618 : case MSG_CLEAR_QUEUE:
4619 : {
4620 : int tag;
4621 :
4622 : /* Target mode messages */
4623 : if (devinfo->role != ROLE_TARGET) {
4624 : reject = TRUE;
4625 : break;
4626 : }
4627 : tag = SCB_LIST_NULL;
4628 : if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
4629 : tag = ahd_inb(ahd, INITIATOR_TAG);
4630 : ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4631 : devinfo->lun, tag, ROLE_TARGET,
4632 : CAM_REQ_ABORTED);
4633 :
4634 : tstate = ahd->enabled_targets[devinfo->our_scsiid];
4635 : if (tstate != NULL) {
4636 : struct ahd_tmode_lstate* lstate;
4637 :
4638 : lstate = tstate->enabled_luns[devinfo->lun];
4639 : if (lstate != NULL) {
4640 : ahd_queue_lstate_event(ahd, lstate,
4641 : devinfo->our_scsiid,
4642 : ahd->msgin_buf[0],
4643 : /*arg*/tag);
4644 : ahd_send_lstate_events(ahd, lstate);
4645 : }
4646 : }
4647 : ahd_restart(ahd);
4648 : done = MSGLOOP_TERMINATED;
4649 : break;
4650 : }
4651 : #endif
4652 : case MSG_QAS_REQUEST:
4653 : #ifdef AHD_DEBUG
4654 : if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4655 : printf("%s: QAS request. SCSISIGI == 0x%x\n",
4656 : ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4657 : #endif
4658 0 : ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
4659 : /* FALLTHROUGH */
4660 : case MSG_TERM_IO_PROC:
4661 : default:
4662 : reject = TRUE;
4663 0 : break;
4664 : }
4665 :
4666 0 : if (reject) {
4667 : /*
4668 : * Setup to reject the message.
4669 : */
4670 0 : ahd->msgout_index = 0;
4671 0 : ahd->msgout_len = 1;
4672 0 : ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
4673 : done = MSGLOOP_MSGCOMPLETE;
4674 : response = TRUE;
4675 0 : }
4676 :
4677 0 : if (done != MSGLOOP_IN_PROG && !response)
4678 : /* Clear the outgoing message buffer */
4679 0 : ahd->msgout_len = 0;
4680 :
4681 0 : return (done);
4682 0 : }
4683 :
4684 : /*
4685 : * Process a message reject message.
4686 : */
4687 : int
4688 0 : ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4689 : {
4690 : /*
4691 : * What we care about here is if we had an
4692 : * outstanding SDTR or WDTR message for this
4693 : * target. If we did, this is a signal that
4694 : * the target is refusing negotiation.
4695 : */
4696 : struct scb *scb;
4697 : struct ahd_initiator_tinfo *tinfo;
4698 0 : struct ahd_tmode_tstate *tstate;
4699 : u_int scb_index;
4700 : u_int last_msg;
4701 : int response = 0;
4702 :
4703 0 : scb_index = ahd_get_scbptr(ahd);
4704 0 : scb = ahd_lookup_scb(ahd, scb_index);
4705 0 : tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4706 0 : devinfo->our_scsiid,
4707 0 : devinfo->target, &tstate);
4708 : /* Might be necessary */
4709 0 : last_msg = ahd_inb(ahd, LAST_MSG);
4710 :
4711 0 : if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4712 0 : if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4713 0 : && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4714 : /*
4715 : * Target may not like our SPI-4 PPR Options.
4716 : * Attempt to negotiate 80MHz which will turn
4717 : * off these options.
4718 : */
4719 : if (bootverbose) {
4720 : printf("(%s:%c:%d:%d): PPR Rejected. "
4721 : "Trying simple U160 PPR\n",
4722 : ahd_name(ahd), devinfo->channel,
4723 : devinfo->target, devinfo->lun);
4724 : }
4725 0 : tinfo->goal.period = AHD_SYNCRATE_DT;
4726 0 : tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4727 : | MSG_EXT_PPR_QAS_REQ
4728 : | MSG_EXT_PPR_DT_REQ;
4729 0 : } else {
4730 : /*
4731 : * Target does not support the PPR message.
4732 : * Attempt to negotiate SPI-2 style.
4733 : */
4734 : if (bootverbose) {
4735 : printf("(%s:%c:%d:%d): PPR Rejected. "
4736 : "Trying WDTR/SDTR\n",
4737 : ahd_name(ahd), devinfo->channel,
4738 : devinfo->target, devinfo->lun);
4739 : }
4740 0 : tinfo->goal.ppr_options = 0;
4741 0 : tinfo->curr.transport_version = 2;
4742 0 : tinfo->goal.transport_version = 2;
4743 : }
4744 0 : ahd->msgout_index = 0;
4745 0 : ahd->msgout_len = 0;
4746 0 : ahd_build_transfer_msg(ahd, devinfo);
4747 0 : ahd->msgout_index = 0;
4748 : response = 1;
4749 0 : } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4750 :
4751 : /* note 8bit xfers */
4752 0 : printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4753 0 : "8bit transfers\n", ahd_name(ahd),
4754 0 : devinfo->channel, devinfo->target, devinfo->lun);
4755 0 : ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4756 : AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4757 : /*paused*/TRUE);
4758 : /*
4759 : * No need to clear the sync rate. If the target
4760 : * did not accept the command, our syncrate is
4761 : * unaffected. If the target started the negotiation,
4762 : * but rejected our response, we already cleared the
4763 : * sync rate before sending our WDTR.
4764 : */
4765 0 : if (tinfo->goal.offset != tinfo->curr.offset) {
4766 :
4767 : /* Start the sync negotiation */
4768 0 : ahd->msgout_index = 0;
4769 0 : ahd->msgout_len = 0;
4770 0 : ahd_build_transfer_msg(ahd, devinfo);
4771 0 : ahd->msgout_index = 0;
4772 : response = 1;
4773 0 : }
4774 0 : } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4775 : /* note asynch xfers and clear flag */
4776 0 : ahd_set_syncrate(ahd, devinfo, /*period*/0,
4777 : /*offset*/0, /*ppr_options*/0,
4778 : AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4779 : /*paused*/TRUE);
4780 0 : printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4781 : "Using asynchronous transfers\n",
4782 0 : ahd_name(ahd), devinfo->channel,
4783 0 : devinfo->target, devinfo->lun);
4784 0 : } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4785 : int tag_type;
4786 : int mask;
4787 :
4788 : tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4789 :
4790 0 : if (tag_type == MSG_SIMPLE_TASK) {
4791 0 : printf("(%s:%c:%d:%d): refuses tagged commands. "
4792 : "Performing non-tagged I/O\n", ahd_name(ahd),
4793 : devinfo->channel, devinfo->target, devinfo->lun);
4794 0 : ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE);
4795 : mask = ~0x23;
4796 0 : } else {
4797 0 : printf("(%s:%c:%d:%d): refuses %s tagged commands. "
4798 : "Performing simple queue tagged I/O only\n",
4799 : ahd_name(ahd), devinfo->channel, devinfo->target,
4800 : devinfo->lun, tag_type == MSG_ORDERED_TASK
4801 : ? "ordered" : "head of queue");
4802 0 : ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC);
4803 : mask = ~0x03;
4804 : }
4805 :
4806 : /*
4807 : * Resend the identify for this CCB as the target
4808 : * may believe that the selection is invalid otherwise.
4809 : */
4810 0 : ahd_outb(ahd, SCB_CONTROL,
4811 : ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4812 0 : scb->hscb->control &= mask;
4813 : aic_set_transaction_tag(scb, /*enabled*/FALSE,
4814 : /*type*/MSG_SIMPLE_TASK);
4815 0 : ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4816 0 : ahd_assert_atn(ahd);
4817 0 : ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4818 0 : SCB_GET_TAG(scb));
4819 :
4820 : /*
4821 : * Requeue all tagged commands for this target
4822 : * currently in our posession so they can be
4823 : * converted to untagged commands.
4824 : */
4825 0 : ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4826 : SCB_GET_CHANNEL(ahd, scb),
4827 0 : SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4828 : ROLE_INITIATOR, CAM_REQUEUE_REQ,
4829 : SEARCH_COMPLETE);
4830 0 : } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4831 : /*
4832 : * Most likely the device believes that we had
4833 : * previously negotiated packetized.
4834 : */
4835 0 : ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4836 : | MSG_FLAG_IU_REQ_CHANGED;
4837 :
4838 0 : ahd_force_renegotiation(ahd, devinfo);
4839 0 : ahd->msgout_index = 0;
4840 0 : ahd->msgout_len = 0;
4841 0 : ahd_build_transfer_msg(ahd, devinfo);
4842 0 : ahd->msgout_index = 0;
4843 : response = 1;
4844 0 : } else {
4845 : /*
4846 : * Otherwise, we ignore it.
4847 : */
4848 0 : printf("%s:%c:%d: Message reject for %x -- ignored\n",
4849 0 : ahd_name(ahd), devinfo->channel, devinfo->target,
4850 : last_msg);
4851 : }
4852 0 : return (response);
4853 0 : }
4854 :
4855 : /*
4856 : * Process an ingnore wide residue message.
4857 : */
4858 : void
4859 0 : ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4860 : {
4861 : u_int scb_index;
4862 : struct scb *scb;
4863 :
4864 0 : scb_index = ahd_get_scbptr(ahd);
4865 0 : scb = ahd_lookup_scb(ahd, scb_index);
4866 : /*
4867 : * XXX Actually check data direction in the sequencer?
4868 : * Perhaps add datadir to some spare bits in the hscb?
4869 : */
4870 0 : if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4871 0 : || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
4872 : /*
4873 : * Ignore the message if we haven't
4874 : * seen an appropriate data phase yet.
4875 : */
4876 : } else {
4877 : /*
4878 : * If the residual occurred on the last
4879 : * transfer and the transfer request was
4880 : * expected to end on an odd count, do
4881 : * nothing. Otherwise, subtract a byte
4882 : * and update the residual count accordingly.
4883 : */
4884 : uint32_t sgptr;
4885 :
4886 0 : sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4887 0 : if ((sgptr & SG_LIST_NULL) != 0
4888 0 : && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4889 0 : & SCB_XFERLEN_ODD) != 0) {
4890 : /*
4891 : * If the residual occurred on the last
4892 : * transfer and the transfer request was
4893 : * expected to end on an odd count, do
4894 : * nothing.
4895 : */
4896 : } else {
4897 : uint32_t data_cnt;
4898 : uint64_t data_addr;
4899 : uint32_t sglen;
4900 :
4901 : /* Pull in the rest of the sgptr */
4902 0 : sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4903 0 : data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4904 0 : if ((sgptr & SG_LIST_NULL) != 0) {
4905 : /*
4906 : * The residual data count is not updated
4907 : * for the command run to completion case.
4908 : * Explicitly zero the count.
4909 : */
4910 0 : data_cnt &= ~AHD_SG_LEN_MASK;
4911 0 : }
4912 0 : data_addr = ahd_inq(ahd, SHADDR);
4913 0 : data_cnt += 1;
4914 : data_addr -= 1;
4915 0 : sgptr &= SG_PTR_MASK;
4916 0 : if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4917 : struct ahd_dma64_seg *sg;
4918 :
4919 0 : sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4920 :
4921 : /*
4922 : * The residual sg ptr points to the next S/G
4923 : * to load so we must go back one.
4924 : */
4925 0 : sg--;
4926 0 : sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4927 0 : if (sg != scb->sg_list
4928 0 : && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4929 :
4930 0 : sg--;
4931 0 : sglen = aic_le32toh(sg->len);
4932 : /*
4933 : * Preserve High Address and SG_LIST
4934 : * bits while setting the count to 1.
4935 : */
4936 0 : data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4937 0 : data_addr = aic_le64toh(sg->addr)
4938 0 : + (sglen & AHD_SG_LEN_MASK)
4939 : - 1;
4940 :
4941 : /*
4942 : * Increment sg so it points to the
4943 : * "next" sg.
4944 : */
4945 0 : sg++;
4946 0 : sgptr = ahd_sg_virt_to_bus(ahd, scb,
4947 0 : sg);
4948 0 : }
4949 0 : } else {
4950 : struct ahd_dma_seg *sg;
4951 :
4952 0 : sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4953 :
4954 : /*
4955 : * The residual sg ptr points to the next S/G
4956 : * to load so we must go back one.
4957 : */
4958 0 : sg--;
4959 0 : sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4960 0 : if (sg != scb->sg_list
4961 0 : && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4962 :
4963 0 : sg--;
4964 0 : sglen = aic_le32toh(sg->len);
4965 : /*
4966 : * Preserve High Address and SG_LIST
4967 : * bits while setting the count to 1.
4968 : */
4969 0 : data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4970 0 : data_addr = aic_le32toh(sg->addr)
4971 0 : + (sglen & AHD_SG_LEN_MASK)
4972 0 : - 1;
4973 :
4974 : /*
4975 : * Increment sg so it points to the
4976 : * "next" sg.
4977 : */
4978 0 : sg++;
4979 0 : sgptr = ahd_sg_virt_to_bus(ahd, scb,
4980 0 : sg);
4981 0 : }
4982 : }
4983 : /*
4984 : * Toggle the "oddness" of the transfer length
4985 : * to handle this mid-transfer ignore wide
4986 : * residue. This ensures that the oddness is
4987 : * correct for subsequent data transfers.
4988 : */
4989 0 : ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
4990 : ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4991 : ^ SCB_XFERLEN_ODD);
4992 :
4993 0 : ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
4994 0 : ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
4995 : /*
4996 : * The FIFO's pointers will be updated if/when the
4997 : * sequencer re-enters a data phase.
4998 : */
4999 : }
5000 : }
5001 0 : }
5002 :
5003 :
5004 : /*
5005 : * Reinitialize the data pointers for the active transfer
5006 : * based on its current residual.
5007 : */
5008 : void
5009 0 : ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
5010 : {
5011 : struct scb *scb;
5012 : ahd_mode_state saved_modes;
5013 : u_int scb_index;
5014 : u_int wait;
5015 : uint32_t sgptr;
5016 : uint32_t resid;
5017 : uint64_t dataptr;
5018 :
5019 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
5020 : AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
5021 :
5022 0 : scb_index = ahd_get_scbptr(ahd);
5023 0 : scb = ahd_lookup_scb(ahd, scb_index);
5024 :
5025 : /*
5026 : * Release and reacquire the FIFO so we
5027 : * have a clean slate.
5028 : */
5029 0 : ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
5030 : wait = 1000;
5031 0 : while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
5032 0 : aic_delay(100);
5033 0 : if (wait == 0) {
5034 0 : ahd_print_path(ahd, scb);
5035 0 : printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5036 0 : ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
5037 0 : }
5038 0 : saved_modes = ahd_save_modes(ahd);
5039 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5040 0 : ahd_outb(ahd, DFFSTAT,
5041 : ahd_inb(ahd, DFFSTAT)
5042 : | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
5043 :
5044 : /*
5045 : * Determine initial values for data_addr and data_cnt
5046 : * for resuming the data phase.
5047 : */
5048 0 : sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
5049 0 : sgptr &= SG_PTR_MASK;
5050 :
5051 0 : resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
5052 0 : | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
5053 0 : | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
5054 :
5055 0 : if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
5056 : struct ahd_dma64_seg *sg;
5057 :
5058 0 : sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5059 :
5060 : /* The residual sg_ptr always points to the next sg */
5061 0 : sg--;
5062 :
5063 0 : dataptr = aic_le64toh(sg->addr)
5064 0 : + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5065 0 : - resid;
5066 0 : ahd_outl(ahd, HADDR + 4, dataptr >> 32);
5067 0 : } else {
5068 : struct ahd_dma_seg *sg;
5069 :
5070 0 : sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5071 :
5072 : /* The residual sg_ptr always points to the next sg */
5073 0 : sg--;
5074 :
5075 0 : dataptr = aic_le32toh(sg->addr)
5076 0 : + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5077 0 : - resid;
5078 0 : ahd_outb(ahd, HADDR + 4,
5079 : (aic_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
5080 : }
5081 0 : ahd_outl(ahd, HADDR, dataptr);
5082 0 : ahd_outb(ahd, HCNT + 2, resid >> 16);
5083 0 : ahd_outb(ahd, HCNT + 1, resid >> 8);
5084 0 : ahd_outb(ahd, HCNT, resid);
5085 0 : }
5086 :
5087 : /*
5088 : * Handle the effects of issuing a bus device reset message.
5089 : */
5090 : void
5091 0 : ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5092 : u_int lun, cam_status status, char *message,
5093 : int verbose_level)
5094 : {
5095 : #ifdef AHD_TARGET_MODE
5096 : struct ahd_tmode_tstate* tstate;
5097 : #endif
5098 : int found;
5099 :
5100 0 : found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
5101 0 : lun, SCB_LIST_NULL, devinfo->role,
5102 : status);
5103 :
5104 : #ifdef AHD_TARGET_MODE
5105 : /*
5106 : * Send an immediate notify ccb to all target mord peripheral
5107 : * drivers affected by this action.
5108 : */
5109 : tstate = ahd->enabled_targets[devinfo->our_scsiid];
5110 : if (tstate != NULL) {
5111 : u_int cur_lun;
5112 : u_int max_lun;
5113 :
5114 : if (lun != CAM_LUN_WILDCARD) {
5115 : cur_lun = 0;
5116 : max_lun = AHD_NUM_LUNS - 1;
5117 : } else {
5118 : cur_lun = lun;
5119 : max_lun = lun;
5120 : }
5121 : for (cur_lun <= max_lun; cur_lun++) {
5122 : struct ahd_tmode_lstate* lstate;
5123 :
5124 : lstate = tstate->enabled_luns[cur_lun];
5125 : if (lstate == NULL)
5126 : continue;
5127 :
5128 : ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
5129 : MSG_BUS_DEV_RESET, /*arg*/0);
5130 : ahd_send_lstate_events(ahd, lstate);
5131 : }
5132 : }
5133 : #endif
5134 :
5135 : /*
5136 : * Go back to async/narrow transfers and renegotiate.
5137 : */
5138 0 : ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5139 : AHD_TRANS_CUR, /*paused*/TRUE);
5140 0 : ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5141 : /*ppr_options*/0, AHD_TRANS_CUR,
5142 : /*paused*/TRUE);
5143 :
5144 : #if 0
5145 : if (status != CAM_SEL_TIMEOUT)
5146 : ahd_send_async(ahd, devinfo->channel, devinfo->target,
5147 : lun, AC_SENT_BDR, NULL);
5148 : #endif
5149 :
5150 0 : if (message != NULL
5151 0 : && (verbose_level <= bootverbose))
5152 0 : printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5153 0 : message, devinfo->channel, devinfo->target, found);
5154 0 : }
5155 :
5156 : #ifdef AHD_TARGET_MODE
5157 : void
5158 : ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5159 : struct scb *scb)
5160 : {
5161 :
5162 : /*
5163 : * To facilitate adding multiple messages together,
5164 : * each routine should increment the index and len
5165 : * variables instead of setting them explicitly.
5166 : */
5167 : ahd->msgout_index = 0;
5168 : ahd->msgout_len = 0;
5169 :
5170 : if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
5171 : ahd_build_transfer_msg(ahd, devinfo);
5172 : else
5173 : panic("ahd_intr: AWAITING target message with no message");
5174 :
5175 : ahd->msgout_index = 0;
5176 : ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5177 : }
5178 : #endif
5179 : /**************************** Initialization **********************************/
5180 : u_int
5181 0 : ahd_sglist_size(struct ahd_softc *ahd)
5182 : {
5183 : bus_size_t list_size;
5184 :
5185 : list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5186 0 : if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5187 : list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5188 0 : return (list_size);
5189 : }
5190 :
5191 : /*
5192 : * Calculate the optimum S/G List allocation size. S/G elements used
5193 : * for a given transaction must be physically contiguous. Assume the
5194 : * OS will allocate full pages to us, so it doesn't make sense to request
5195 : * less than a page.
5196 : */
5197 : u_int
5198 0 : ahd_sglist_allocsize(struct ahd_softc *ahd)
5199 : {
5200 : bus_size_t sg_list_increment;
5201 : bus_size_t sg_list_size;
5202 : bus_size_t max_list_size;
5203 : bus_size_t best_list_size;
5204 :
5205 : /* Start out with the minimum required for AHD_NSEG. */
5206 0 : sg_list_increment = ahd_sglist_size(ahd);
5207 : sg_list_size = sg_list_increment;
5208 :
5209 : /* Get us as close as possible to a page in size. */
5210 0 : while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
5211 : sg_list_size += sg_list_increment;
5212 :
5213 : /*
5214 : * Try to reduce the amount of wastage by allocating
5215 : * multiple pages.
5216 : */
5217 : best_list_size = sg_list_size;
5218 0 : max_list_size = roundup(sg_list_increment, PAGE_SIZE);
5219 0 : if (max_list_size < 4 * PAGE_SIZE)
5220 : max_list_size = 4 * PAGE_SIZE;
5221 0 : if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
5222 0 : max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
5223 0 : while ((sg_list_size + sg_list_increment) <= max_list_size
5224 0 : && (sg_list_size % PAGE_SIZE) != 0) {
5225 : bus_size_t new_mod;
5226 : bus_size_t best_mod;
5227 :
5228 : sg_list_size += sg_list_increment;
5229 0 : new_mod = sg_list_size % PAGE_SIZE;
5230 0 : best_mod = best_list_size % PAGE_SIZE;
5231 0 : if (new_mod > best_mod || new_mod == 0) {
5232 : best_list_size = sg_list_size;
5233 0 : }
5234 : }
5235 0 : return (best_list_size);
5236 : }
5237 :
5238 : /*
5239 : * Perform initial initialization for a controller structure.
5240 : */
5241 : struct ahd_softc *
5242 0 : ahd_alloc(void *platform_arg, char *name)
5243 : {
5244 0 : struct ahd_softc *ahd = (struct ahd_softc *)platform_arg;
5245 :
5246 0 : ahd->seep_config = malloc(sizeof(*ahd->seep_config),
5247 : M_DEVBUF, M_NOWAIT);
5248 0 : if (ahd->seep_config == NULL)
5249 0 : return (NULL);
5250 :
5251 0 : TAILQ_INIT(&ahd->pending_scbs);
5252 0 : LIST_INIT(&ahd->timedout_scbs);
5253 :
5254 : /* We don't know our unit number until the OSM sets it */
5255 0 : ahd->name = name;
5256 0 : ahd->unit = -1;
5257 0 : ahd->bus_description = NULL;
5258 0 : ahd->channel = 'A';
5259 0 : ahd->chip = AHD_NONE;
5260 0 : ahd->features = AHD_FENONE;
5261 0 : ahd->bugs = AHD_BUGNONE;
5262 0 : ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5263 : | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5264 0 : ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5265 0 : ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5266 0 : ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5267 0 : ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5268 0 : ahd->int_coalescing_stop_threshold =
5269 : AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5270 :
5271 : #ifdef AHD_DEBUG
5272 : if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5273 : printf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5274 : ahd_name(ahd), (u_int)sizeof(struct scb),
5275 : (u_int)sizeof(struct hardware_scb));
5276 : }
5277 : #endif
5278 0 : return (ahd);
5279 0 : }
5280 :
5281 : int
5282 0 : ahd_softc_init(struct ahd_softc *ahd)
5283 : {
5284 :
5285 0 : ahd->unpause = 0;
5286 0 : ahd->pause = PAUSE;
5287 0 : return (0);
5288 : }
5289 :
5290 : void
5291 0 : ahd_softc_insert(struct ahd_softc *ahd)
5292 : {
5293 : struct ahd_softc *list_ahd;
5294 :
5295 : #if AHD_PCI_CONFIG > 0
5296 : /*
5297 : * Second Function PCI devices need to inherit some
5298 : * settings from function 0.
5299 : */
5300 : if ((ahd->features & AHD_MULTI_FUNC) != 0) {
5301 : TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5302 : aic_dev_softc_t list_pci;
5303 : aic_dev_softc_t pci;
5304 :
5305 : list_pci = list_ahd->dev_softc;
5306 : pci = ahd->dev_softc;
5307 : if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
5308 : && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
5309 : struct ahd_softc *master;
5310 : struct ahd_softc *slave;
5311 :
5312 : if (aic_get_pci_function(list_pci) == 0) {
5313 : master = list_ahd;
5314 : slave = ahd;
5315 : } else {
5316 : master = ahd;
5317 : slave = list_ahd;
5318 : }
5319 : slave->flags &= ~AHD_BIOS_ENABLED;
5320 : slave->flags |=
5321 : master->flags & AHD_BIOS_ENABLED;
5322 : break;
5323 : }
5324 : }
5325 : }
5326 : #endif
5327 :
5328 : /*
5329 : * Insertion sort into our list of softcs.
5330 : */
5331 0 : list_ahd = TAILQ_FIRST(&ahd_tailq);
5332 0 : while (list_ahd != NULL
5333 0 : && ahd_softc_comp(ahd, list_ahd) <= 0)
5334 0 : list_ahd = TAILQ_NEXT(list_ahd, links);
5335 0 : if (list_ahd != NULL)
5336 0 : TAILQ_INSERT_BEFORE(list_ahd, ahd, links);
5337 : else
5338 0 : TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links);
5339 0 : ahd->init_level++;
5340 0 : }
5341 :
5342 : /*
5343 : * Verify that the passed in softc pointer is for a
5344 : * controller that is still configured.
5345 : */
5346 : struct ahd_softc *
5347 0 : ahd_find_softc(struct ahd_softc *ahd)
5348 : {
5349 : struct ahd_softc *list_ahd;
5350 :
5351 0 : TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5352 0 : if (list_ahd == ahd)
5353 0 : return (ahd);
5354 : }
5355 0 : return (NULL);
5356 0 : }
5357 :
5358 : void
5359 0 : ahd_set_unit(struct ahd_softc *ahd, int unit)
5360 : {
5361 0 : ahd->unit = unit;
5362 0 : }
5363 :
5364 : void
5365 0 : ahd_set_name(struct ahd_softc *ahd, char *name)
5366 : {
5367 0 : if (ahd->name != NULL)
5368 0 : free(ahd->name, M_DEVBUF, 0);
5369 0 : ahd->name = name;
5370 0 : }
5371 :
5372 : void
5373 0 : ahd_free(struct ahd_softc *ahd)
5374 : {
5375 : int i;
5376 :
5377 0 : switch (ahd->init_level) {
5378 : default:
5379 : case 2:
5380 0 : ahd_shutdown(ahd);
5381 0 : TAILQ_REMOVE(&ahd_tailq, ahd, links);
5382 : /* FALLTHROUGH */
5383 : case 1:
5384 0 : ahd_freedmamem(ahd, &ahd->shared_data_map);
5385 0 : break;
5386 : case 0:
5387 : break;
5388 : }
5389 :
5390 0 : ahd_fini_scbdata(ahd);
5391 0 : for (i = 0; i < AHD_NUM_TARGETS; i++) {
5392 : struct ahd_tmode_tstate *tstate;
5393 :
5394 0 : tstate = ahd->enabled_targets[i];
5395 0 : if (tstate != NULL) {
5396 : #if AHD_TARGET_MODE
5397 : int j;
5398 :
5399 : for (j = 0; j < AHD_NUM_LUNS; j++) {
5400 : struct ahd_tmode_lstate *lstate;
5401 :
5402 : lstate = tstate->enabled_luns[j];
5403 : if (lstate != NULL) {
5404 : xpt_free_path(lstate->path);
5405 : free(lstate, M_DEVBUF, 0);
5406 : }
5407 : }
5408 : #endif
5409 0 : free(tstate, M_DEVBUF, 0);
5410 0 : }
5411 : }
5412 : #if AHD_TARGET_MODE
5413 : if (ahd->black_hole != NULL) {
5414 : xpt_free_path(ahd->black_hole->path);
5415 : free(ahd->black_hole, M_DEVBUF, 0);
5416 : }
5417 : #endif
5418 0 : if (ahd->seep_config != NULL)
5419 0 : free(ahd->seep_config, M_DEVBUF, 0);
5420 0 : if (ahd->saved_stack != NULL)
5421 0 : free(ahd->saved_stack, M_DEVBUF, 0);
5422 : return;
5423 0 : }
5424 :
5425 : void
5426 0 : ahd_shutdown(void *arg)
5427 : {
5428 : struct ahd_softc *ahd;
5429 :
5430 0 : ahd = (struct ahd_softc *)arg;
5431 :
5432 : /*
5433 : * Stop periodic timer callbacks.
5434 : */
5435 0 : aic_timer_stop(&ahd->reset_timer);
5436 0 : aic_timer_stop(&ahd->stat_timer);
5437 :
5438 : /* This will reset most registers to 0, but not all */
5439 0 : ahd_reset(ahd, /*reinit*/FALSE);
5440 0 : }
5441 :
5442 : /*
5443 : * Reset the controller and record some information about it
5444 : * that is only available just after a reset. If "reinit" is
5445 : * non-zero, this reset occured after initial configuration
5446 : * and the caller requests that the chip be fully reinitialized
5447 : * to a runable state. Chip interrupts are *not* enabled after
5448 : * a reinitialization. The caller must enable interrupts via
5449 : * ahd_intr_enable().
5450 : */
5451 : int
5452 0 : ahd_reset(struct ahd_softc *ahd, int reinit)
5453 : {
5454 0 : const pci_chipset_tag_t pc = ahd->dev_softc->pa_pc;
5455 0 : const pcitag_t tag = ahd->dev_softc->pa_tag;
5456 : u_int sxfrctl1;
5457 : int wait;
5458 : pcireg_t cmd;
5459 :
5460 : /*
5461 : * Preserve the value of the SXFRCTL1 register for all channels.
5462 : * It contains settings that affect termination and we don't want
5463 : * to disturb the integrity of the bus.
5464 : */
5465 0 : ahd_pause(ahd);
5466 0 : ahd_update_modes(ahd);
5467 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5468 0 : sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5469 :
5470 0 : cmd = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
5471 :
5472 0 : if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5473 : pcireg_t mod_cmd;
5474 :
5475 : /*
5476 : * A4 Razor #632
5477 : * During the assertion of CHIPRST, the chip
5478 : * does not disable its parity logic prior to
5479 : * the start of the reset. This may cause a
5480 : * parity error to be detected and thus a
5481 : * spurious SERR or PERR assertion. Disble
5482 : * PERR and SERR responses during the CHIPRST.
5483 : */
5484 0 : mod_cmd = cmd & ~(PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE);
5485 0 : pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, mod_cmd);
5486 0 : }
5487 0 : ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5488 :
5489 : /*
5490 : * Ensure that the reset has finished. We delay 1000us
5491 : * prior to reading the register to make sure the chip
5492 : * has sufficiently completed its reset to handle register
5493 : * accesses.
5494 : */
5495 : wait = 1000;
5496 0 : do {
5497 0 : aic_delay(1000);
5498 0 : } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5499 :
5500 0 : if (wait == 0) {
5501 0 : printf("%s: WARNING - Failed chip reset! "
5502 0 : "Trying to initialize anyway.\n", ahd_name(ahd));
5503 0 : }
5504 0 : ahd_outb(ahd, HCNTRL, ahd->pause);
5505 :
5506 0 : if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5507 : /*
5508 : * Clear any latched PCI error status and restore
5509 : * previous SERR and PERR response enables.
5510 : */
5511 0 : pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, cmd |
5512 : (PCI_STATUS_PARITY_ERROR | PCI_STATUS_TARGET_TARGET_ABORT |
5513 : PCI_STATUS_MASTER_TARGET_ABORT | PCI_STATUS_MASTER_ABORT |
5514 : PCI_STATUS_SPECIAL_ERROR));
5515 :
5516 0 : }
5517 :
5518 : /*
5519 : * Mode should be SCSI after a chip reset, but lets
5520 : * set it just to be safe. We touch the MODE_PTR
5521 : * register directly so as to bypass the lazy update
5522 : * code in ahd_set_modes().
5523 : */
5524 0 : ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5525 0 : ahd_outb(ahd, MODE_PTR,
5526 : ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5527 :
5528 : /*
5529 : * Restore SXFRCTL1.
5530 : *
5531 : * We must always initialize STPWEN to 1 before we
5532 : * restore the saved values. STPWEN is initialized
5533 : * to a tri-state condition which can only be cleared
5534 : * by turning it on.
5535 : */
5536 0 : ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5537 0 : ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5538 :
5539 : /* Determine chip configuration */
5540 0 : ahd->features &= ~AHD_WIDE;
5541 0 : if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5542 0 : ahd->features |= AHD_WIDE;
5543 :
5544 : /*
5545 : * If a recovery action has forced a chip reset,
5546 : * re-initialize the chip to our liking.
5547 : */
5548 0 : if (reinit != 0)
5549 0 : ahd_chip_init(ahd);
5550 :
5551 0 : return (0);
5552 : }
5553 :
5554 : /*
5555 : * Determine the number of SCBs available on the controller
5556 : */
5557 : int
5558 0 : ahd_probe_scbs(struct ahd_softc *ahd) {
5559 : int i;
5560 :
5561 0 : AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5562 : ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5563 0 : for (i = 0; i < AHD_SCB_MAX; i++) {
5564 : int j;
5565 :
5566 0 : ahd_set_scbptr(ahd, i);
5567 0 : ahd_outw(ahd, SCB_BASE, i);
5568 0 : for (j = 2; j < 64; j++)
5569 0 : ahd_outb(ahd, SCB_BASE+j, 0);
5570 : /* Start out life as unallocated (needing an abort) */
5571 0 : ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
5572 0 : if (ahd_inw_scbram(ahd, SCB_BASE) != i)
5573 0 : break;
5574 0 : ahd_set_scbptr(ahd, 0);
5575 0 : if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
5576 0 : break;
5577 0 : }
5578 0 : return (i);
5579 : }
5580 :
5581 : void
5582 0 : ahd_initialize_hscbs(struct ahd_softc *ahd)
5583 : {
5584 : int i;
5585 :
5586 0 : for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
5587 0 : ahd_set_scbptr(ahd, i);
5588 :
5589 : /* Clear the control byte. */
5590 0 : ahd_outb(ahd, SCB_CONTROL, 0);
5591 :
5592 : /* Set the next pointer */
5593 0 : ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5594 : }
5595 0 : }
5596 :
5597 : int
5598 0 : ahd_init_scbdata(struct ahd_softc *ahd)
5599 : {
5600 : struct scb_data *scb_data;
5601 : int i;
5602 :
5603 0 : scb_data = &ahd->scb_data;
5604 0 : TAILQ_INIT(&scb_data->free_scbs);
5605 0 : SLIST_INIT(&scb_data->hscb_maps);
5606 0 : SLIST_INIT(&scb_data->sg_maps);
5607 0 : SLIST_INIT(&scb_data->sense_maps);
5608 0 : mtx_init(&ahd->sc_scb_mtx, IPL_BIO);
5609 0 : scsi_iopool_init(&ahd->sc_iopool, ahd, ahd_scb_alloc, ahd_scb_free);
5610 :
5611 : /* Determine the number of hardware SCBs and initialize them */
5612 0 : scb_data->maxhscbs = ahd_probe_scbs(ahd);
5613 0 : if (scb_data->maxhscbs == 0) {
5614 0 : printf("%s: No SCB space found\n", ahd_name(ahd));
5615 0 : return (ENXIO);
5616 : }
5617 :
5618 0 : ahd_initialize_hscbs(ahd);
5619 :
5620 : /*
5621 : * Create our DMA tags. These tags define the kinds of device
5622 : * accessible memory allocations and memory mappings we will
5623 : * need to perform during normal operation.
5624 : *
5625 : * Unless we need to further restrict the allocation, we rely
5626 : * on the restrictions of the parent dmat, hence the common
5627 : * use of MAXADDR and MAXSIZE.
5628 : */
5629 :
5630 : /* Perform initial CCB allocation */
5631 0 : do {
5632 0 : i = scb_data->numscbs;
5633 0 : ahd_alloc_scbs(ahd);
5634 0 : } while ((i != scb_data->numscbs) &&
5635 0 : (scb_data->numscbs < AHD_SCB_MAX_ALLOC));
5636 :
5637 0 : if (scb_data->numscbs != AHD_SCB_MAX_ALLOC) {
5638 0 : printf("%s: ahd_init_scbdata - "
5639 : "Unable to allocate initial scbs\n",
5640 0 : ahd_name(ahd));
5641 : goto error_exit;
5642 : }
5643 :
5644 : /*
5645 : * Note that we were successful
5646 : */
5647 0 : return (0);
5648 :
5649 : error_exit:
5650 :
5651 0 : return (ENOMEM);
5652 0 : }
5653 :
5654 : struct scb *
5655 0 : ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5656 : {
5657 : struct scb *scb;
5658 :
5659 : /*
5660 : * Look on the pending list.
5661 : */
5662 0 : TAILQ_FOREACH(scb, &ahd->pending_scbs, next) {
5663 0 : if (SCB_GET_TAG(scb) == tag)
5664 0 : return (scb);
5665 : }
5666 :
5667 : /*
5668 : * And finally on the generic free list.
5669 : */
5670 0 : TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, next) {
5671 0 : if (SCB_GET_TAG(scb) == tag)
5672 0 : return (scb);
5673 : }
5674 :
5675 0 : return (NULL);
5676 0 : }
5677 :
5678 : void
5679 0 : ahd_fini_scbdata(struct ahd_softc *ahd)
5680 : {
5681 : struct scb_data *scb_data;
5682 :
5683 0 : scb_data = &ahd->scb_data;
5684 0 : if (scb_data == NULL)
5685 0 : return;
5686 :
5687 0 : switch (scb_data->init_level) {
5688 : default:
5689 : case 3:
5690 : {
5691 : struct map_node *sns_map;
5692 :
5693 0 : while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5694 0 : SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5695 0 : ahd_freedmamem(ahd, sns_map);
5696 0 : free(sns_map, M_DEVBUF, 0);
5697 : }
5698 : /* FALLTHROUGH */
5699 0 : }
5700 : case 2:
5701 : {
5702 : struct map_node *sg_map;
5703 :
5704 0 : while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5705 0 : SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5706 0 : ahd_freedmamem(ahd, sg_map);
5707 0 : free(sg_map, M_DEVBUF, 0);
5708 : }
5709 : /* FALLTHROUGH */
5710 0 : }
5711 : case 1:
5712 : {
5713 : struct map_node *hscb_map;
5714 :
5715 0 : while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5716 0 : SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5717 0 : ahd_freedmamem(ahd, hscb_map);
5718 0 : free(hscb_map, M_DEVBUF, 0);
5719 : }
5720 : /* FALLTHROUGH */
5721 0 : }
5722 : case 0:
5723 : break;
5724 : }
5725 0 : }
5726 :
5727 : /*
5728 : * DSP filter Bypass must be enabled until the first selection
5729 : * after a change in bus mode (Razor #491 and #493).
5730 : */
5731 : void
5732 0 : ahd_setup_iocell_workaround(struct ahd_softc *ahd)
5733 : {
5734 : ahd_mode_state saved_modes;
5735 :
5736 0 : saved_modes = ahd_save_modes(ahd);
5737 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5738 0 : ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5739 : | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5740 0 : ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5741 : #ifdef AHD_DEBUG
5742 : if ((ahd_debug & AHD_SHOW_MISC) != 0)
5743 : printf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5744 : #endif
5745 0 : ahd_restore_modes(ahd, saved_modes);
5746 0 : ahd->flags &= ~AHD_HAD_FIRST_SEL;
5747 0 : }
5748 :
5749 : void
5750 0 : ahd_iocell_first_selection(struct ahd_softc *ahd)
5751 : {
5752 : ahd_mode_state saved_modes;
5753 : u_int sblkctl;
5754 :
5755 0 : if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5756 0 : return;
5757 0 : saved_modes = ahd_save_modes(ahd);
5758 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5759 0 : sblkctl = ahd_inb(ahd, SBLKCTL);
5760 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5761 : #ifdef AHD_DEBUG
5762 : if ((ahd_debug & AHD_SHOW_MISC) != 0)
5763 : printf("%s: iocell first selection\n", ahd_name(ahd));
5764 : #endif
5765 0 : if ((sblkctl & ENAB40) != 0) {
5766 0 : ahd_outb(ahd, DSPDATACTL,
5767 : ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5768 : #ifdef AHD_DEBUG
5769 : if ((ahd_debug & AHD_SHOW_MISC) != 0)
5770 : printf("%s: BYPASS now disabled\n", ahd_name(ahd));
5771 : #endif
5772 0 : }
5773 0 : ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5774 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
5775 0 : ahd_restore_modes(ahd, saved_modes);
5776 0 : ahd->flags |= AHD_HAD_FIRST_SEL;
5777 0 : }
5778 :
5779 : /*
5780 : * Get a free scb. If there are none, see if we can allocate a new SCB.
5781 : */
5782 : void *
5783 0 : ahd_scb_alloc(void *xahd)
5784 : {
5785 0 : struct ahd_softc *ahd = xahd;
5786 : struct scb *scb;
5787 :
5788 0 : mtx_enter(&ahd->sc_scb_mtx);
5789 0 : scb = TAILQ_FIRST(&ahd->scb_data.free_scbs);
5790 0 : if (scb) {
5791 0 : TAILQ_REMOVE(&ahd->scb_data.free_scbs, scb, next);
5792 0 : scb->flags |= SCB_ACTIVE;
5793 0 : }
5794 0 : mtx_leave(&ahd->sc_scb_mtx);
5795 :
5796 0 : return (scb);
5797 : }
5798 :
5799 : /*
5800 : * Return an SCB resource to the free list.
5801 : */
5802 : void
5803 0 : ahd_scb_free(void *xahd, void *xscb)
5804 : {
5805 0 : struct ahd_softc *ahd = xahd;
5806 0 : struct scb *scb = xscb;
5807 :
5808 : /* Clean up for the next user */
5809 0 : scb->flags = SCB_FLAG_NONE;
5810 0 : scb->hscb->control = 0;
5811 0 : ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
5812 :
5813 0 : mtx_enter(&ahd->sc_scb_mtx);
5814 0 : TAILQ_INSERT_HEAD(&ahd->scb_data.free_scbs, scb, next);
5815 0 : aic_platform_scb_free(ahd, scb);
5816 0 : mtx_leave(&ahd->sc_scb_mtx);
5817 0 : }
5818 :
5819 : void
5820 0 : ahd_alloc_scbs(struct ahd_softc *ahd)
5821 : {
5822 : struct scb_data *scb_data;
5823 : struct scb *next_scb;
5824 : struct hardware_scb *hscb;
5825 : struct map_node *hscb_map;
5826 : struct map_node *sg_map;
5827 : struct map_node *sense_map;
5828 : uint8_t *segs;
5829 : uint8_t *sense_data;
5830 : bus_addr_t hscb_busaddr;
5831 : bus_addr_t sg_busaddr;
5832 : bus_addr_t sense_busaddr;
5833 : int newcount;
5834 : int i;
5835 :
5836 0 : scb_data = &ahd->scb_data;
5837 0 : if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
5838 : /* Can't allocate any more */
5839 0 : return;
5840 :
5841 0 : KASSERT(scb_data->scbs_left >= 0);
5842 0 : if (scb_data->scbs_left != 0) {
5843 : int offset;
5844 :
5845 0 : offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
5846 0 : hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
5847 0 : hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
5848 0 : hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb));
5849 0 : } else {
5850 0 : hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT);
5851 :
5852 0 : if (hscb_map == NULL)
5853 0 : return;
5854 :
5855 : /* Allocate the next batch of hardware SCBs */
5856 0 : if (ahd_createdmamem(ahd, PAGE_SIZE, hscb_map,
5857 0 : "hardware SCB structures") < 0) {
5858 0 : free(hscb_map, M_DEVBUF, 0);
5859 0 : return;
5860 : }
5861 :
5862 0 : SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
5863 :
5864 0 : hscb = (struct hardware_scb *)hscb_map->vaddr;
5865 0 : hscb_busaddr = hscb_map->busaddr;
5866 0 : scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
5867 : }
5868 :
5869 0 : scb_data->init_level++;
5870 :
5871 0 : if (scb_data->sgs_left != 0) {
5872 : int offset;
5873 :
5874 0 : offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
5875 0 : - scb_data->sgs_left) * ahd_sglist_size(ahd);
5876 0 : sg_map = SLIST_FIRST(&scb_data->sg_maps);
5877 0 : segs = sg_map->vaddr + offset;
5878 0 : sg_busaddr = sg_map->busaddr + offset;
5879 0 : } else {
5880 0 : sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
5881 :
5882 0 : if (sg_map == NULL)
5883 0 : return;
5884 :
5885 : /* Allocate the next batch of S/G lists */
5886 0 : if (ahd_createdmamem(ahd, ahd_sglist_allocsize(ahd), sg_map,
5887 0 : "SG data structures") < 0) {
5888 0 : free(sg_map, M_DEVBUF, 0);
5889 0 : return;
5890 : }
5891 :
5892 0 : SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
5893 :
5894 0 : segs = sg_map->vaddr;
5895 0 : sg_busaddr = sg_map->busaddr;
5896 0 : scb_data->sgs_left =
5897 0 : ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
5898 : #ifdef AHD_DEBUG
5899 : if (ahd_debug & AHD_SHOW_MEMORY)
5900 : printf("%s: ahd_alloc_scbs - Mapped SG data\n", ahd_name(ahd));
5901 : #endif
5902 : }
5903 :
5904 0 : scb_data->init_level++;
5905 :
5906 0 : if (scb_data->sense_left != 0) {
5907 : int offset;
5908 :
5909 0 : offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
5910 0 : sense_map = SLIST_FIRST(&scb_data->sense_maps);
5911 0 : sense_data = sense_map->vaddr + offset;
5912 0 : sense_busaddr = sense_map->busaddr + offset;
5913 0 : } else {
5914 0 : sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT);
5915 :
5916 0 : if (sense_map == NULL)
5917 0 : return;
5918 :
5919 : /* Allocate the next batch of sense buffers */
5920 0 : if (ahd_createdmamem(ahd, PAGE_SIZE, sense_map,
5921 0 : "Sense Data structures") < 0) {
5922 0 : free(sense_map, M_DEVBUF, 0);
5923 0 : return;
5924 : }
5925 :
5926 0 : SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
5927 :
5928 0 : sense_data = sense_map->vaddr;
5929 0 : sense_busaddr = sense_map->busaddr;
5930 0 : scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
5931 : #ifdef AHD_DEBUG
5932 : if (ahd_debug & AHD_SHOW_MEMORY)
5933 : printf("%s: ahd_alloc_scbs - Mapped sense data\n", ahd_name(ahd));
5934 : #endif
5935 : }
5936 :
5937 0 : scb_data->init_level++;
5938 :
5939 0 : newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
5940 0 : newcount = MIN(newcount, scb_data->sgs_left);
5941 0 : newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
5942 0 : scb_data->sense_left -= newcount;
5943 0 : scb_data->scbs_left -= newcount;
5944 0 : scb_data->sgs_left -= newcount;
5945 0 : for (i = 0; i < newcount; i++) {
5946 : int error;
5947 :
5948 0 : next_scb = (struct scb *)malloc(sizeof(*next_scb),
5949 : M_DEVBUF, M_NOWAIT);
5950 0 : if (next_scb == NULL)
5951 0 : break;
5952 :
5953 0 : next_scb->hscb_map = hscb_map;
5954 0 : next_scb->sg_map = sg_map;
5955 0 : next_scb->sense_map = sense_map;
5956 0 : next_scb->sg_list = segs;
5957 0 : next_scb->sense_data = sense_data;
5958 0 : next_scb->sense_busaddr = sense_busaddr;
5959 0 : memset(hscb, 0, sizeof(*hscb));
5960 0 : next_scb->hscb = hscb;
5961 0 : KASSERT((vaddr_t)hscb >= (vaddr_t)hscb_map->vaddr &&
5962 : (vaddr_t)hscb < (vaddr_t)hscb_map->vaddr + PAGE_SIZE);
5963 0 : hscb->hscb_busaddr = aic_htole32(hscb_busaddr);
5964 :
5965 : /*
5966 : * The sequencer always starts with the second entry.
5967 : * The first entry is embedded in the scb.
5968 : */
5969 0 : next_scb->sg_list_busaddr = sg_busaddr;
5970 0 : if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5971 0 : next_scb->sg_list_busaddr
5972 0 : += sizeof(struct ahd_dma64_seg);
5973 : else
5974 0 : next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
5975 0 : next_scb->ahd_softc = ahd;
5976 0 : next_scb->flags = SCB_FLAG_NONE;
5977 :
5978 0 : error = bus_dmamap_create(ahd->parent_dmat,
5979 : AHD_MAXTRANSFER_SIZE, AHD_NSEG, MAXBSIZE, 0,
5980 : BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, &next_scb->dmamap);
5981 :
5982 0 : if (error != 0) {
5983 0 : free(next_scb, M_DEVBUF, 0);
5984 0 : break;
5985 : }
5986 0 : next_scb->hscb->tag = aic_htole16(scb_data->numscbs);
5987 0 : ahd_scb_free(ahd, next_scb);
5988 0 : hscb++;
5989 0 : hscb_busaddr += sizeof(*hscb);
5990 0 : segs += ahd_sglist_size(ahd);
5991 0 : sg_busaddr += ahd_sglist_size(ahd);
5992 0 : sense_data += AHD_SENSE_BUFSIZE;
5993 0 : sense_busaddr += AHD_SENSE_BUFSIZE;
5994 0 : scb_data->numscbs++;
5995 0 : }
5996 0 : }
5997 :
5998 : void
5999 0 : ahd_controller_info(struct ahd_softc *ahd, char *buf, size_t bufsz)
6000 : {
6001 0 : snprintf(buf, bufsz, "%s: %s, U320 %s Channel %c, %s, %d SCBs",
6002 0 : ahd_name(ahd), ahd_chip_names[ahd->chip & AHD_CHIPID_MASK],
6003 0 : ((ahd->features & AHD_WIDE) != 0) ? "Wide" : "Single",
6004 0 : ahd->channel, ahd->bus_description, ahd->scb_data.maxhscbs);
6005 0 : }
6006 :
6007 : static const char *channel_strings[] = {
6008 : "Primary Low",
6009 : "Primary High",
6010 : "Secondary Low",
6011 : "Secondary High"
6012 : };
6013 :
6014 : static const char *termstat_strings[] = {
6015 : "Terminated Correctly",
6016 : "Over Terminated",
6017 : "Under Terminated",
6018 : "Not Configured"
6019 : };
6020 :
6021 : /*
6022 : * Start the board, ready for normal operation
6023 : */
6024 : int
6025 0 : ahd_init(struct ahd_softc *ahd)
6026 : {
6027 : uint8_t *next_vaddr;
6028 : bus_addr_t next_baddr;
6029 : size_t driver_data_size;
6030 : int i;
6031 : int error;
6032 : u_int warn_user;
6033 0 : uint8_t current_sensing;
6034 0 : uint8_t fstat;
6035 :
6036 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6037 :
6038 0 : ahd->stack_size = ahd_probe_stack_size(ahd);
6039 0 : ahd->saved_stack = mallocarray(ahd->stack_size, sizeof(uint16_t),
6040 : M_DEVBUF, M_NOWAIT | M_ZERO);
6041 0 : if (ahd->saved_stack == NULL)
6042 0 : return (ENOMEM);
6043 :
6044 : /*
6045 : * Verify that the compiler hasn't over-aggressively
6046 : * padded important structures.
6047 : */
6048 : if (sizeof(struct hardware_scb) != 64)
6049 : panic("Hardware SCB size is incorrect");
6050 :
6051 : #ifdef AHD_DEBUG
6052 : if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
6053 : ahd->flags |= AHD_SEQUENCER_DEBUG;
6054 : #endif
6055 :
6056 : /*
6057 : * Default to allowing initiator operations.
6058 : */
6059 0 : ahd->flags |= AHD_INITIATORROLE;
6060 :
6061 : /*
6062 : * Only allow target mode features if this unit has them enabled.
6063 : */
6064 0 : if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6065 0 : ahd->features &= ~AHD_TARGETMODE;
6066 :
6067 : /*
6068 : * DMA tag for our command fifos and other data in system memory
6069 : * the card's sequencer must be able to access. For initiator
6070 : * roles, we need to allocate space for the qoutfifo. When providing
6071 : * for the target mode role, we must additionally provide space for
6072 : * the incoming target command fifo.
6073 : */
6074 : driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
6075 : + sizeof(struct hardware_scb);
6076 0 : if ((ahd->features & AHD_TARGETMODE) != 0)
6077 0 : driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6078 0 : if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6079 0 : driver_data_size += PKT_OVERRUN_BUFSIZE;
6080 0 : if (ahd_createdmamem(ahd, driver_data_size, &ahd->shared_data_map,
6081 0 : "shared data") < 0)
6082 0 : return (ENOMEM);
6083 :
6084 0 : ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
6085 :
6086 0 : ahd->init_level++;
6087 :
6088 0 : next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6089 0 : next_baddr = ahd->shared_data_map.busaddr
6090 0 : + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
6091 0 : if ((ahd->features & AHD_TARGETMODE) != 0) {
6092 0 : ahd->targetcmds = (struct target_cmd *)next_vaddr;
6093 0 : next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6094 0 : next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6095 0 : }
6096 :
6097 0 : if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6098 0 : ahd->overrun_buf = next_vaddr;
6099 0 : next_vaddr += PKT_OVERRUN_BUFSIZE;
6100 0 : next_baddr += PKT_OVERRUN_BUFSIZE;
6101 0 : }
6102 :
6103 : /*
6104 : * We need one SCB to serve as the "next SCB". Since the
6105 : * tag identifier in this SCB will never be used, there is
6106 : * no point in using a valid HSCB tag from an SCB pulled from
6107 : * the standard free pool. So, we allocate this "sentinel"
6108 : * specially from the DMA safe memory chunk used for the QOUTFIFO.
6109 : */
6110 0 : ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6111 0 : ahd->next_queued_hscb_map = &ahd->shared_data_map;
6112 0 : ahd->next_queued_hscb->hscb_busaddr = aic_htole32(next_baddr);
6113 :
6114 : /* Allocate SCB data now that buffer_dmat is initialized */
6115 0 : if (ahd_init_scbdata(ahd) != 0)
6116 0 : return (ENOMEM);
6117 :
6118 0 : if ((ahd->flags & AHD_INITIATORROLE) == 0)
6119 0 : ahd->flags &= ~AHD_RESET_BUS_A;
6120 :
6121 : /* Bring up the chip. */
6122 0 : ahd_chip_init(ahd);
6123 :
6124 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6125 :
6126 0 : if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6127 : goto init_done;
6128 :
6129 : /*
6130 : * Verify termination based on current draw and
6131 : * warn user if the bus is over/under terminated.
6132 : */
6133 0 : error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
6134 : CURSENSE_ENB);
6135 0 : if (error != 0) {
6136 0 : printf("%s: current sensing timeout 1\n", ahd_name(ahd));
6137 0 : goto init_done;
6138 : }
6139 0 : for (i = 20, fstat = FLX_FSTAT_BUSY;
6140 0 : (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
6141 0 : error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
6142 0 : if (error != 0) {
6143 0 : printf("%s: current sensing timeout 2\n",
6144 0 : ahd_name(ahd));
6145 0 : goto init_done;
6146 : }
6147 : }
6148 0 : if (i == 0) {
6149 0 : printf("%s: Timeout during current-sensing test\n",
6150 0 : ahd_name(ahd));
6151 0 : goto init_done;
6152 : }
6153 :
6154 : /* Latch Current Sensing status. */
6155 0 : error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing);
6156 0 : if (error != 0) {
6157 0 : printf("%s: current sensing timeout 3\n", ahd_name(ahd));
6158 0 : goto init_done;
6159 : }
6160 :
6161 : /* Disable current sensing. */
6162 0 : ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
6163 :
6164 : #ifdef AHD_DEBUG
6165 : if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
6166 : printf("%s: current_sensing == 0x%x\n",
6167 : ahd_name(ahd), current_sensing);
6168 : }
6169 : #endif
6170 : warn_user = 0;
6171 0 : for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
6172 : u_int term_stat;
6173 :
6174 0 : term_stat = (current_sensing & FLX_CSTAT_MASK);
6175 0 : switch (term_stat) {
6176 : case FLX_CSTAT_OVER:
6177 : case FLX_CSTAT_UNDER:
6178 0 : warn_user++;
6179 : case FLX_CSTAT_INVALID:
6180 : case FLX_CSTAT_OKAY:
6181 0 : if (warn_user == 0 && bootverbose == 0)
6182 : break;
6183 0 : printf("%s: %s Channel %s\n", ahd_name(ahd),
6184 0 : channel_strings[i], termstat_strings[term_stat]);
6185 0 : break;
6186 : }
6187 : }
6188 0 : if (warn_user) {
6189 0 : printf("%s: WARNING. Termination is not configured correctly.\n"
6190 : "%s: WARNING. SCSI bus operations may FAIL.\n",
6191 0 : ahd_name(ahd), ahd_name(ahd));
6192 0 : }
6193 : init_done:
6194 0 : ahd_reset_current_bus(ahd);
6195 0 : ahd_restart(ahd);
6196 0 : aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
6197 0 : ahd_stat_timer, ahd);
6198 0 : return (0);
6199 0 : }
6200 :
6201 : /*
6202 : * (Re)initialize chip state after a chip reset.
6203 : */
6204 : void
6205 0 : ahd_chip_init(struct ahd_softc *ahd)
6206 : {
6207 : uint32_t busaddr;
6208 : u_int sxfrctl1;
6209 : u_int scsiseq_template;
6210 : u_int wait;
6211 : u_int i;
6212 : u_int target;
6213 :
6214 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6215 : /*
6216 : * Take the LED out of diagnostic mode
6217 : */
6218 0 : ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6219 :
6220 : /*
6221 : * Return HS_MAILBOX to its default value.
6222 : */
6223 0 : ahd->hs_mailbox = 0;
6224 0 : ahd_outb(ahd, HS_MAILBOX, 0);
6225 :
6226 : /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6227 0 : ahd_outb(ahd, IOWNID, ahd->our_id);
6228 0 : ahd_outb(ahd, TOWNID, ahd->our_id);
6229 0 : sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6230 0 : sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6231 0 : if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6232 0 : && (ahd->seltime != STIMESEL_MIN)) {
6233 : /*
6234 : * The selection timer duration is twice as long
6235 : * as it should be. Halve it by adding "1" to
6236 : * the user specified setting.
6237 : */
6238 0 : sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
6239 0 : } else {
6240 0 : sxfrctl1 |= ahd->seltime;
6241 : }
6242 :
6243 0 : ahd_outb(ahd, SXFRCTL0, DFON);
6244 0 : ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6245 0 : ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6246 :
6247 : /*
6248 : * Now that termination is set, wait for up
6249 : * to 500ms for our transceivers to settle. If
6250 : * the adapter does not have a cable attached,
6251 : * the transceivers may never settle, so don't
6252 : * complain if we fail here.
6253 : */
6254 0 : for (wait = 10000;
6255 0 : (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6256 0 : wait--)
6257 0 : aic_delay(100);
6258 :
6259 : /* Clear any false bus resets due to the transceivers settling */
6260 0 : ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6261 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
6262 :
6263 : /* Initialize mode specific S/G state. */
6264 0 : for (i = 0; i < 2; i++) {
6265 0 : ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6266 0 : ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
6267 0 : ahd_outb(ahd, SG_STATE, 0);
6268 0 : ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6269 0 : ahd_outb(ahd, SEQIMODE,
6270 : ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6271 : |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6272 : }
6273 :
6274 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6275 0 : ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6276 0 : ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6277 0 : ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6278 0 : ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6279 0 : if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6280 0 : ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6281 0 : } else {
6282 0 : ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6283 : }
6284 0 : ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
6285 0 : if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6286 : /*
6287 : * Do not issue a target abort when a split completion
6288 : * error occurs. Let our PCIX interrupt handler deal
6289 : * with it instead. H2A4 Razor #625
6290 : */
6291 0 : ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6292 :
6293 0 : if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6294 0 : ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6295 :
6296 : /*
6297 : * Tweak IOCELL settings.
6298 : */
6299 0 : if ((ahd->flags & AHD_HP_BOARD) != 0) {
6300 0 : for (i = 0; i < NUMDSPS; i++) {
6301 0 : ahd_outb(ahd, DSPSELECT, i);
6302 0 : ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
6303 : }
6304 : #ifdef AHD_DEBUG
6305 : if ((ahd_debug & AHD_SHOW_MISC) != 0)
6306 : printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6307 : WRTBIASCTL_HP_DEFAULT);
6308 : #endif
6309 : }
6310 0 : ahd_setup_iocell_workaround(ahd);
6311 :
6312 : /*
6313 : * Enable LQI Manager interrupts.
6314 : */
6315 0 : ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6316 : | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6317 : | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6318 0 : ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6319 : /*
6320 : * We choose to have the sequencer catch LQOPHCHGINPKT errors
6321 : * manually for the command phase at the start of a packetized
6322 : * selection case. ENLQOBUSFREE should be made redundant by
6323 : * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6324 : * events fail to assert the BUSFREE interrupt so we must
6325 : * also enable LQOBUSFREE interrupts.
6326 : */
6327 0 : ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
6328 :
6329 : /*
6330 : * Setup sequencer interrupt handlers.
6331 : */
6332 0 : ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6333 0 : ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6334 :
6335 : /*
6336 : * Setup SCB Offset registers.
6337 : */
6338 0 : if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6339 0 : ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6340 : pkt_long_lun));
6341 0 : } else {
6342 0 : ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6343 : }
6344 0 : ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6345 0 : ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
6346 0 : ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6347 0 : ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6348 : shared_data.idata.cdb));
6349 0 : ahd_outb(ahd, QNEXTPTR,
6350 : offsetof(struct hardware_scb, next_hscb_busaddr));
6351 0 : ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6352 0 : ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6353 0 : if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6354 0 : ahd_outb(ahd, LUNLEN,
6355 : sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6356 0 : } else {
6357 0 : ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6358 : }
6359 0 : ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6360 0 : ahd_outb(ahd, MAXCMD, 0xFF);
6361 0 : ahd_outb(ahd, SCBAUTOPTR,
6362 : AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6363 :
6364 : /* We haven't been enabled for target mode yet. */
6365 0 : ahd_outb(ahd, MULTARGID, 0);
6366 0 : ahd_outb(ahd, MULTARGID + 1, 0);
6367 :
6368 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6369 : /* Initialize the negotiation table. */
6370 0 : if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6371 : /*
6372 : * Clear the spare bytes in the neg table to avoid
6373 : * spurious parity errors.
6374 : */
6375 0 : for (target = 0; target < AHD_NUM_TARGETS; target++) {
6376 0 : ahd_outb(ahd, NEGOADDR, target);
6377 0 : ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6378 0 : for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6379 0 : ahd_outb(ahd, ANNEXDAT, 0);
6380 : }
6381 : }
6382 0 : for (target = 0; target < AHD_NUM_TARGETS; target++) {
6383 0 : struct ahd_devinfo devinfo;
6384 : struct ahd_initiator_tinfo *tinfo;
6385 0 : struct ahd_tmode_tstate *tstate;
6386 :
6387 0 : tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6388 : target, &tstate);
6389 0 : ahd_compile_devinfo(&devinfo, ahd->our_id,
6390 : target, CAM_LUN_WILDCARD,
6391 : 'A', ROLE_INITIATOR);
6392 0 : ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6393 0 : }
6394 :
6395 0 : ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6396 0 : ahd_outb(ahd, CLRINT, CLRSCSIINT);
6397 :
6398 : #if NEEDS_MORE_TESTING
6399 : /*
6400 : * Always enable abort on incoming L_Qs if this feature is
6401 : * supported. We use this to catch invalid SCB references.
6402 : */
6403 : if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6404 : ahd_outb(ahd, LQCTL1, ABORTPENDING);
6405 : else
6406 : #endif
6407 0 : ahd_outb(ahd, LQCTL1, 0);
6408 :
6409 : /* All of our queues are empty */
6410 0 : ahd->qoutfifonext = 0;
6411 0 : ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
6412 0 : ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
6413 0 : for (i = 0; i < AHD_QOUT_SIZE; i++)
6414 0 : ahd->qoutfifo[i].valid_tag = 0;
6415 0 : ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6416 :
6417 0 : ahd->qinfifonext = 0;
6418 0 : for (i = 0; i < AHD_QIN_SIZE; i++)
6419 0 : ahd->qinfifo[i] = SCB_LIST_NULL;
6420 :
6421 0 : if ((ahd->features & AHD_TARGETMODE) != 0) {
6422 : /* All target command blocks start out invalid. */
6423 0 : for (i = 0; i < AHD_TMODE_CMDS; i++)
6424 0 : ahd->targetcmds[i].cmd_valid = 0;
6425 0 : ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
6426 0 : ahd->tqinfifonext = 1;
6427 0 : ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
6428 0 : ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
6429 0 : }
6430 :
6431 : /* Initialize Scratch Ram. */
6432 0 : ahd_outb(ahd, SEQ_FLAGS, 0);
6433 0 : ahd_outb(ahd, SEQ_FLAGS2, 0);
6434 :
6435 : /* We don't have any waiting selections */
6436 0 : ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6437 0 : ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6438 0 : ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
6439 0 : ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
6440 0 : for (i = 0; i < AHD_NUM_TARGETS; i++)
6441 0 : ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6442 :
6443 : /*
6444 : * Nobody is waiting to be DMAed into the QOUTFIFO.
6445 : */
6446 0 : ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6447 0 : ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6448 0 : ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6449 0 : ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
6450 0 : ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
6451 :
6452 : /*
6453 : * The Freeze Count is 0.
6454 : */
6455 0 : ahd->qfreeze_cnt = 0;
6456 0 : ahd_outw(ahd, QFREEZE_COUNT, 0);
6457 0 : ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
6458 :
6459 : /*
6460 : * Tell the sequencer where it can find our arrays in memory.
6461 : */
6462 0 : busaddr = ahd->shared_data_map.busaddr;
6463 0 : ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
6464 0 : ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
6465 :
6466 : /*
6467 : * Setup the allowed SCSI Sequences based on operational mode.
6468 : * If we are a target, we'll enable select in operations once
6469 : * we've had a lun enabled.
6470 : */
6471 : scsiseq_template = ENAUTOATNP;
6472 0 : if ((ahd->flags & AHD_INITIATORROLE) != 0)
6473 0 : scsiseq_template |= ENRSELI;
6474 0 : ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
6475 :
6476 : /* There are no busy SCBs yet. */
6477 0 : for (target = 0; target < AHD_NUM_TARGETS; target++) {
6478 : int lun;
6479 :
6480 0 : for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6481 0 : ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6482 : }
6483 :
6484 : /*
6485 : * Initialize the group code to command length table.
6486 : * Vendor Unique codes are set to 0 so we only capture
6487 : * the first byte of the cdb. These can be overridden
6488 : * when target mode is enabled.
6489 : */
6490 0 : ahd_outb(ahd, CMDSIZE_TABLE, 5);
6491 0 : ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6492 0 : ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
6493 0 : ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
6494 0 : ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
6495 0 : ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
6496 0 : ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
6497 0 : ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
6498 :
6499 : /* Tell the sequencer of our initial queue positions */
6500 0 : ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
6501 0 : ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
6502 0 : ahd->qinfifonext = 0;
6503 0 : ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
6504 0 : ahd_set_hescb_qoff(ahd, 0);
6505 0 : ahd_set_snscb_qoff(ahd, 0);
6506 0 : ahd_set_sescb_qoff(ahd, 0);
6507 0 : ahd_set_sdscb_qoff(ahd, 0);
6508 :
6509 : /*
6510 : * Tell the sequencer which SCB will be the next one it receives.
6511 : */
6512 0 : busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6513 0 : ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6514 :
6515 : /*
6516 : * Default to coalescing disabled.
6517 : */
6518 0 : ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6519 0 : ahd_outw(ahd, CMDS_PENDING, 0);
6520 0 : ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6521 0 : ahd->int_coalescing_maxcmds,
6522 0 : ahd->int_coalescing_mincmds);
6523 0 : ahd_enable_coalescing(ahd, FALSE);
6524 :
6525 0 : ahd_loadseq(ahd);
6526 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6527 0 : }
6528 :
6529 : /*
6530 : * Setup default device and controller settings.
6531 : * This should only be called if our probe has
6532 : * determined that no configuration data is available.
6533 : */
6534 : int
6535 0 : ahd_default_config(struct ahd_softc *ahd)
6536 : {
6537 : int targ;
6538 :
6539 0 : ahd->our_id = 7;
6540 :
6541 : /*
6542 : * Allocate a tstate to house information for our
6543 : * initiator presence on the bus as well as the user
6544 : * data for any target mode initiator.
6545 : */
6546 0 : if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6547 0 : printf("%s: unable to allocate ahd_tmode_tstate. "
6548 0 : "Failing attach\n", ahd_name(ahd));
6549 0 : return (ENOMEM);
6550 : }
6551 :
6552 0 : for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6553 0 : struct ahd_devinfo devinfo;
6554 : struct ahd_initiator_tinfo *tinfo;
6555 0 : struct ahd_tmode_tstate *tstate;
6556 : uint16_t target_mask;
6557 :
6558 0 : tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6559 : targ, &tstate);
6560 : /*
6561 : * We support SPC2 and SPI4.
6562 : */
6563 0 : tinfo->user.protocol_version = 4;
6564 0 : tinfo->user.transport_version = 4;
6565 :
6566 0 : target_mask = 0x01 << targ;
6567 0 : ahd->user_discenable |= target_mask;
6568 0 : tstate->discenable |= target_mask;
6569 0 : ahd->user_tagenable |= target_mask;
6570 : #ifdef AHD_FORCE_160
6571 : tinfo->user.period = AHD_SYNCRATE_DT;
6572 : #else
6573 0 : tinfo->user.period = AHD_SYNCRATE_160;
6574 : #endif
6575 0 : tinfo->user.offset = MAX_OFFSET;
6576 0 : tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6577 : | MSG_EXT_PPR_WR_FLOW
6578 : | MSG_EXT_PPR_HOLD_MCS
6579 : | MSG_EXT_PPR_IU_REQ
6580 : | MSG_EXT_PPR_QAS_REQ
6581 : | MSG_EXT_PPR_DT_REQ;
6582 0 : if ((ahd->features & AHD_RTI) != 0)
6583 0 : tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6584 :
6585 0 : tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6586 :
6587 : /*
6588 : * Start out Async/Narrow/Untagged and with
6589 : * conservative protocol support.
6590 : */
6591 0 : tinfo->goal.protocol_version = 2;
6592 0 : tinfo->goal.transport_version = 2;
6593 0 : tinfo->curr.protocol_version = 2;
6594 0 : tinfo->curr.transport_version = 2;
6595 0 : ahd_compile_devinfo(&devinfo, ahd->our_id,
6596 : targ, CAM_LUN_WILDCARD,
6597 : 'A', ROLE_INITIATOR);
6598 0 : tstate->tagenable &= ~target_mask;
6599 0 : ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6600 : AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6601 0 : ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6602 : /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6603 : /*paused*/TRUE);
6604 0 : }
6605 0 : return (0);
6606 0 : }
6607 :
6608 : /*
6609 : * Parse device configuration information.
6610 : */
6611 : int
6612 0 : ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
6613 : {
6614 : int targ;
6615 : int max_targ;
6616 :
6617 0 : max_targ = sc->max_targets & CFMAXTARG;
6618 0 : ahd->our_id = sc->brtime_id & CFSCSIID;
6619 :
6620 : /*
6621 : * Allocate a tstate to house information for our
6622 : * initiator presence on the bus as well as the user
6623 : * data for any target mode initiator.
6624 : */
6625 0 : if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6626 0 : printf("%s: unable to allocate ahd_tmode_tstate. "
6627 0 : "Failing attach\n", ahd_name(ahd));
6628 0 : return (ENOMEM);
6629 : }
6630 :
6631 0 : for (targ = 0; targ < max_targ; targ++) {
6632 0 : struct ahd_devinfo devinfo;
6633 : struct ahd_initiator_tinfo *tinfo;
6634 : struct ahd_transinfo *user_tinfo;
6635 0 : struct ahd_tmode_tstate *tstate;
6636 : uint16_t target_mask;
6637 :
6638 0 : tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6639 : targ, &tstate);
6640 0 : user_tinfo = &tinfo->user;
6641 :
6642 : /*
6643 : * We support SPC2 and SPI4.
6644 : */
6645 0 : tinfo->user.protocol_version = 4;
6646 0 : tinfo->user.transport_version = 4;
6647 :
6648 0 : target_mask = 0x01 << targ;
6649 0 : ahd->user_discenable &= ~target_mask;
6650 0 : tstate->discenable &= ~target_mask;
6651 0 : ahd->user_tagenable &= ~target_mask;
6652 0 : if (sc->device_flags[targ] & CFDISC) {
6653 0 : tstate->discenable |= target_mask;
6654 0 : ahd->user_discenable |= target_mask;
6655 0 : ahd->user_tagenable |= target_mask;
6656 0 : } else {
6657 : /*
6658 : * Cannot be packetized without disconnection.
6659 : */
6660 0 : sc->device_flags[targ] &= ~CFPACKETIZED;
6661 : }
6662 :
6663 0 : user_tinfo->ppr_options = 0;
6664 0 : user_tinfo->period = (sc->device_flags[targ] & CFXFER);
6665 0 : if (user_tinfo->period < CFXFER_ASYNC) {
6666 0 : if (user_tinfo->period <= AHD_PERIOD_10MHz)
6667 0 : user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
6668 0 : user_tinfo->offset = MAX_OFFSET;
6669 0 : } else {
6670 0 : user_tinfo->offset = 0;
6671 0 : user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
6672 : }
6673 : #ifdef AHD_FORCE_160
6674 : if (user_tinfo->period <= AHD_SYNCRATE_160)
6675 : user_tinfo->period = AHD_SYNCRATE_DT;
6676 : #endif
6677 :
6678 0 : if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
6679 0 : user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
6680 : | MSG_EXT_PPR_WR_FLOW
6681 : | MSG_EXT_PPR_HOLD_MCS
6682 : | MSG_EXT_PPR_IU_REQ;
6683 0 : if ((ahd->features & AHD_RTI) != 0)
6684 0 : user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
6685 : }
6686 :
6687 0 : if ((sc->device_flags[targ] & CFQAS) != 0)
6688 0 : user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
6689 :
6690 0 : if ((sc->device_flags[targ] & CFWIDEB) != 0)
6691 0 : user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
6692 : else
6693 0 : user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
6694 : #ifdef AHD_DEBUG
6695 : if ((ahd_debug & AHD_SHOW_MISC) != 0)
6696 : printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
6697 : user_tinfo->period, user_tinfo->offset,
6698 : user_tinfo->ppr_options);
6699 : #endif
6700 : /*
6701 : * Start out Async/Narrow/Untagged and with
6702 : * conservative protocol support.
6703 : */
6704 0 : tstate->tagenable &= ~target_mask;
6705 0 : tinfo->goal.protocol_version = 2;
6706 0 : tinfo->goal.transport_version = 2;
6707 0 : tinfo->curr.protocol_version = 2;
6708 0 : tinfo->curr.transport_version = 2;
6709 0 : ahd_compile_devinfo(&devinfo, ahd->our_id,
6710 : targ, CAM_LUN_WILDCARD,
6711 : 'A', ROLE_INITIATOR);
6712 0 : ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6713 : AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6714 0 : ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6715 : /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6716 : /*paused*/TRUE);
6717 0 : }
6718 :
6719 0 : ahd->flags &= ~AHD_SPCHK_ENB_A;
6720 0 : if (sc->bios_control & CFSPARITY)
6721 0 : ahd->flags |= AHD_SPCHK_ENB_A;
6722 :
6723 0 : ahd->flags &= ~AHD_RESET_BUS_A;
6724 0 : if (sc->bios_control & CFRESETB)
6725 0 : ahd->flags |= AHD_RESET_BUS_A;
6726 :
6727 0 : ahd->flags &= ~AHD_EXTENDED_TRANS_A;
6728 0 : if (sc->bios_control & CFEXTEND)
6729 0 : ahd->flags |= AHD_EXTENDED_TRANS_A;
6730 :
6731 0 : ahd->flags &= ~AHD_BIOS_ENABLED;
6732 0 : if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
6733 0 : ahd->flags |= AHD_BIOS_ENABLED;
6734 :
6735 0 : ahd->flags &= ~AHD_STPWLEVEL_A;
6736 0 : if ((sc->adapter_control & CFSTPWLEVEL) != 0)
6737 0 : ahd->flags |= AHD_STPWLEVEL_A;
6738 :
6739 0 : return (0);
6740 0 : }
6741 :
6742 : /*
6743 : * Parse device configuration information.
6744 : */
6745 : int
6746 0 : ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
6747 : {
6748 : int error;
6749 :
6750 0 : error = ahd_verify_vpd_cksum(vpd);
6751 0 : if (error == 0)
6752 0 : return (EINVAL);
6753 0 : if ((vpd->bios_flags & VPDBOOTHOST) != 0)
6754 0 : ahd->flags |= AHD_BOOT_CHANNEL;
6755 0 : return (0);
6756 0 : }
6757 :
6758 : void
6759 0 : ahd_intr_enable(struct ahd_softc *ahd, int enable)
6760 : {
6761 : u_int hcntrl;
6762 :
6763 0 : hcntrl = ahd_inb(ahd, HCNTRL);
6764 0 : hcntrl &= ~INTEN;
6765 0 : ahd->pause &= ~INTEN;
6766 0 : ahd->unpause &= ~INTEN;
6767 0 : if (enable) {
6768 0 : hcntrl |= INTEN;
6769 0 : ahd->pause |= INTEN;
6770 0 : ahd->unpause |= INTEN;
6771 0 : }
6772 0 : ahd_outb(ahd, HCNTRL, hcntrl);
6773 0 : }
6774 :
6775 : void
6776 0 : ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
6777 : u_int mincmds)
6778 : {
6779 0 : if (timer > AHD_TIMER_MAX_US)
6780 0 : timer = AHD_TIMER_MAX_US;
6781 0 : ahd->int_coalescing_timer = timer;
6782 :
6783 0 : if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
6784 0 : maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
6785 0 : if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
6786 0 : mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
6787 0 : ahd->int_coalescing_maxcmds = maxcmds;
6788 0 : ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
6789 0 : ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
6790 0 : ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
6791 0 : }
6792 :
6793 : void
6794 0 : ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
6795 : {
6796 :
6797 0 : ahd->hs_mailbox &= ~ENINT_COALESCE;
6798 0 : if (enable)
6799 0 : ahd->hs_mailbox |= ENINT_COALESCE;
6800 0 : ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
6801 0 : ahd_flush_device_writes(ahd);
6802 0 : ahd_run_qoutfifo(ahd);
6803 0 : }
6804 :
6805 : /*
6806 : * Ensure that the card is paused in a location
6807 : * outside of all critical sections and that all
6808 : * pending work is completed prior to returning.
6809 : * This routine should only be called from outside
6810 : * an interrupt context.
6811 : */
6812 : void
6813 0 : ahd_pause_and_flushwork(struct ahd_softc *ahd)
6814 : {
6815 : u_int intstat;
6816 : u_int maxloops;
6817 :
6818 : maxloops = 1000;
6819 0 : ahd->flags |= AHD_ALL_INTERRUPTS;
6820 0 : ahd_pause(ahd);
6821 : /*
6822 : * Freeze the outgoing selections. We do this only
6823 : * until we are safely paused without further selections
6824 : * pending.
6825 : */
6826 0 : ahd->qfreeze_cnt--;
6827 0 : ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
6828 0 : ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
6829 0 : do {
6830 :
6831 0 : ahd_unpause(ahd);
6832 : /*
6833 : * Give the sequencer some time to service
6834 : * any active selections.
6835 : */
6836 0 : aic_delay(500);
6837 :
6838 0 : ahd_intr(ahd);
6839 0 : ahd_pause(ahd);
6840 0 : intstat = ahd_inb(ahd, INTSTAT);
6841 0 : if ((intstat & INT_PEND) == 0) {
6842 0 : ahd_clear_critical_section(ahd);
6843 0 : intstat = ahd_inb(ahd, INTSTAT);
6844 0 : }
6845 0 : } while (--maxloops
6846 0 : && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
6847 0 : && ((intstat & INT_PEND) != 0
6848 0 : || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
6849 0 : || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
6850 :
6851 0 : if (maxloops == 0) {
6852 0 : printf("Infinite interrupt loop, INTSTAT = %x",
6853 0 : ahd_inb(ahd, INTSTAT));
6854 0 : }
6855 0 : ahd->qfreeze_cnt++;
6856 0 : ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
6857 :
6858 0 : ahd_flush_qoutfifo(ahd);
6859 :
6860 0 : ahd->flags &= ~AHD_ALL_INTERRUPTS;
6861 0 : }
6862 :
6863 : int
6864 0 : ahd_suspend(struct ahd_softc *ahd)
6865 : {
6866 :
6867 0 : ahd_pause_and_flushwork(ahd);
6868 :
6869 0 : if (!TAILQ_EMPTY(&ahd->pending_scbs)) {
6870 0 : ahd_unpause(ahd);
6871 0 : return (EBUSY);
6872 : }
6873 0 : ahd_shutdown(ahd);
6874 0 : return (0);
6875 0 : }
6876 :
6877 : int
6878 0 : ahd_resume(struct ahd_softc *ahd)
6879 : {
6880 :
6881 0 : ahd_reset(ahd, /*reinit*/TRUE);
6882 0 : ahd_intr_enable(ahd, TRUE);
6883 0 : ahd_restart(ahd);
6884 0 : return (0);
6885 : }
6886 :
6887 : /************************** Busy Target Table *********************************/
6888 : /*
6889 : * Set SCBPTR to the SCB that contains the busy
6890 : * table entry for TCL. Return the offset into
6891 : * the SCB that contains the entry for TCL.
6892 : * saved_scbid is dereferenced and set to the
6893 : * scbid that should be restored once manipualtion
6894 : * of the TCL entry is complete.
6895 : */
6896 : u_int ahd_index_busy_tcl(struct ahd_softc *, u_int *, u_int);
6897 : u_int
6898 0 : ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
6899 : {
6900 : /*
6901 : * Index to the SCB that contains the busy entry.
6902 : */
6903 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6904 0 : *saved_scbid = ahd_get_scbptr(ahd);
6905 0 : ahd_set_scbptr(ahd, TCL_LUN(tcl)
6906 0 : | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
6907 :
6908 : /*
6909 : * And now calculate the SCB offset to the entry.
6910 : * Each entry is 2 bytes wide, hence the
6911 : * multiplication by 2.
6912 : */
6913 0 : return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
6914 : }
6915 :
6916 : /*
6917 : * Return the untagged transaction id for a given target/channel lun.
6918 : */
6919 : u_int
6920 0 : ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
6921 : {
6922 : u_int scbid;
6923 : u_int scb_offset;
6924 0 : u_int saved_scbptr;
6925 :
6926 0 : scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
6927 0 : scbid = ahd_inw_scbram(ahd, scb_offset);
6928 0 : ahd_set_scbptr(ahd, saved_scbptr);
6929 0 : return (scbid);
6930 0 : }
6931 :
6932 : void
6933 0 : ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
6934 : {
6935 : u_int scb_offset;
6936 0 : u_int saved_scbptr;
6937 :
6938 0 : scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
6939 0 : ahd_outw(ahd, scb_offset, scbid);
6940 0 : ahd_set_scbptr(ahd, saved_scbptr);
6941 0 : }
6942 :
6943 : /************************** SCB and SCB queue management **********************/
6944 : int
6945 0 : ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
6946 : char channel, int lun, u_int tag, role_t role)
6947 : {
6948 0 : int targ = SCB_GET_TARGET(ahd, scb);
6949 : char chan = SCB_GET_CHANNEL(ahd, scb);
6950 0 : int slun = SCB_GET_LUN(scb);
6951 : int match;
6952 :
6953 0 : match = ((chan == channel) || (channel == ALL_CHANNELS));
6954 0 : if (match != 0)
6955 0 : match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
6956 0 : if (match != 0)
6957 0 : match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
6958 0 : if (match != 0) {
6959 : #if AHD_TARGET_MODE
6960 : int group;
6961 :
6962 : group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
6963 : if (role == ROLE_INITIATOR) {
6964 : match = (group != XPT_FC_GROUP_TMODE)
6965 : && ((tag == SCB_GET_TAG(scb))
6966 : || (tag == SCB_LIST_NULL));
6967 : } else if (role == ROLE_TARGET) {
6968 : match = (group == XPT_FC_GROUP_TMODE)
6969 : && ((tag == scb->io_ctx->csio.tag_id)
6970 : || (tag == SCB_LIST_NULL));
6971 : }
6972 : #else /* !AHD_TARGET_MODE */
6973 0 : match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
6974 : #endif /* AHD_TARGET_MODE */
6975 0 : }
6976 :
6977 0 : return match;
6978 : }
6979 :
6980 : void
6981 0 : ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
6982 : {
6983 : int target;
6984 : char channel;
6985 : int lun;
6986 :
6987 0 : target = SCB_GET_TARGET(ahd, scb);
6988 0 : lun = SCB_GET_LUN(scb);
6989 : channel = SCB_GET_CHANNEL(ahd, scb);
6990 :
6991 0 : ahd_search_qinfifo(ahd, target, channel, lun,
6992 : /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
6993 : CAM_REQUEUE_REQ, SEARCH_COMPLETE);
6994 0 : }
6995 :
6996 : void
6997 0 : ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
6998 : {
6999 : struct scb *prev_scb;
7000 : ahd_mode_state saved_modes;
7001 :
7002 0 : saved_modes = ahd_save_modes(ahd);
7003 0 : ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7004 : prev_scb = NULL;
7005 0 : if (ahd_qinfifo_count(ahd) != 0) {
7006 : u_int prev_tag;
7007 : u_int prev_pos;
7008 :
7009 0 : prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7010 0 : prev_tag = ahd->qinfifo[prev_pos];
7011 0 : prev_scb = ahd_lookup_scb(ahd, prev_tag);
7012 0 : }
7013 0 : ahd_qinfifo_requeue(ahd, prev_scb, scb);
7014 0 : ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7015 0 : ahd_restore_modes(ahd, saved_modes);
7016 0 : }
7017 :
7018 : void
7019 0 : ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7020 : struct scb *scb)
7021 : {
7022 0 : if (prev_scb == NULL) {
7023 : uint32_t busaddr;
7024 :
7025 0 : busaddr = aic_le32toh(scb->hscb->hscb_busaddr);
7026 0 : ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7027 0 : } else {
7028 0 : prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7029 0 : ahd_sync_scb(ahd, prev_scb,
7030 : BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7031 : }
7032 0 : ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7033 0 : ahd->qinfifonext++;
7034 0 : scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
7035 0 : ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7036 0 : }
7037 :
7038 : int
7039 0 : ahd_qinfifo_count(struct ahd_softc *ahd)
7040 : {
7041 : u_int qinpos;
7042 : u_int wrap_qinpos;
7043 : u_int wrap_qinfifonext;
7044 :
7045 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7046 0 : qinpos = ahd_get_snscb_qoff(ahd);
7047 0 : wrap_qinpos = AHD_QIN_WRAP(qinpos);
7048 0 : wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7049 0 : if (wrap_qinfifonext >= wrap_qinpos)
7050 0 : return (wrap_qinfifonext - wrap_qinpos);
7051 : else
7052 0 : return (wrap_qinfifonext
7053 0 : + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7054 0 : }
7055 :
7056 : void
7057 0 : ahd_reset_cmds_pending(struct ahd_softc *ahd)
7058 : {
7059 : struct scb *scb;
7060 : ahd_mode_state saved_modes;
7061 : u_int pending_cmds;
7062 :
7063 0 : saved_modes = ahd_save_modes(ahd);
7064 0 : ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7065 :
7066 : /*
7067 : * Don't count any commands as outstanding that the
7068 : * sequencer has already marked for completion.
7069 : */
7070 0 : ahd_flush_qoutfifo(ahd);
7071 :
7072 : pending_cmds = 0;
7073 0 : TAILQ_FOREACH(scb, &ahd->pending_scbs, next) {
7074 0 : pending_cmds++;
7075 : }
7076 0 : ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7077 0 : ahd_restore_modes(ahd, saved_modes);
7078 0 : ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7079 0 : }
7080 :
7081 : void
7082 0 : ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
7083 : {
7084 : cam_status ostat;
7085 : cam_status cstat;
7086 :
7087 0 : ostat = aic_get_transaction_status(scb);
7088 0 : if (ostat == CAM_REQ_INPROG)
7089 0 : aic_set_transaction_status(scb, status);
7090 0 : cstat = aic_get_transaction_status(scb);
7091 : if (cstat != CAM_REQ_CMP)
7092 : aic_freeze_scb(scb);
7093 0 : ahd_done(ahd, scb);
7094 0 : }
7095 :
7096 : int
7097 0 : ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7098 : int lun, u_int tag, role_t role, uint32_t status,
7099 : ahd_search_action action)
7100 : {
7101 : struct scb *scb;
7102 : struct scb *mk_msg_scb;
7103 : struct scb *prev_scb;
7104 : ahd_mode_state saved_modes;
7105 : u_int qinstart;
7106 : u_int qinpos;
7107 : u_int qintail;
7108 : u_int tid_next;
7109 : u_int tid_prev;
7110 : u_int scbid;
7111 : u_int seq_flags2;
7112 : u_int savedscbptr;
7113 : uint32_t busaddr;
7114 : int found;
7115 : int targets;
7116 :
7117 : /* Must be in CCHAN mode */
7118 0 : saved_modes = ahd_save_modes(ahd);
7119 0 : ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7120 :
7121 : /*
7122 : * Halt any pending SCB DMA. The sequencer will reinitiate
7123 : * this dma if the qinfifo is not empty once we unpause.
7124 : */
7125 0 : if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
7126 0 : == (CCARREN|CCSCBEN|CCSCBDIR)) {
7127 0 : ahd_outb(ahd, CCSCBCTL,
7128 : ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
7129 0 : while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
7130 : ;
7131 : }
7132 : /* Determine sequencer's position in the qinfifo. */
7133 0 : qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7134 0 : qinstart = ahd_get_snscb_qoff(ahd);
7135 0 : qinpos = AHD_QIN_WRAP(qinstart);
7136 : found = 0;
7137 : prev_scb = NULL;
7138 :
7139 0 : if (action == SEARCH_PRINT) {
7140 0 : printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7141 0 : qinstart, ahd->qinfifonext);
7142 0 : }
7143 :
7144 : /*
7145 : * Start with an empty queue. Entries that are not chosen
7146 : * for removal will be re-added to the queue as we go.
7147 : */
7148 0 : ahd->qinfifonext = qinstart;
7149 0 : busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7150 0 : ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7151 :
7152 0 : while (qinpos != qintail) {
7153 0 : scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7154 0 : if (scb == NULL) {
7155 0 : printf("qinpos = %d, SCB index = %d\n",
7156 0 : qinpos, ahd->qinfifo[qinpos]);
7157 0 : panic("Loop 1");
7158 : }
7159 :
7160 0 : if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7161 : /*
7162 : * We found an scb that needs to be acted on.
7163 : */
7164 0 : found++;
7165 0 : switch (action) {
7166 : case SEARCH_COMPLETE:
7167 0 : if ((scb->flags & SCB_ACTIVE) == 0)
7168 0 : printf("Inactive SCB in qinfifo\n");
7169 0 : ahd_done_with_status(ahd, scb, status);
7170 : /* FALLTHROUGH */
7171 : case SEARCH_REMOVE:
7172 : break;
7173 : case SEARCH_PRINT:
7174 0 : printf(" 0x%x", ahd->qinfifo[qinpos]);
7175 : /* FALLTHROUGH */
7176 : case SEARCH_COUNT:
7177 0 : ahd_qinfifo_requeue(ahd, prev_scb, scb);
7178 : prev_scb = scb;
7179 0 : break;
7180 : }
7181 : } else {
7182 0 : ahd_qinfifo_requeue(ahd, prev_scb, scb);
7183 : prev_scb = scb;
7184 : }
7185 0 : qinpos = AHD_QIN_WRAP(qinpos+1);
7186 : }
7187 :
7188 0 : ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7189 :
7190 0 : if (action == SEARCH_PRINT)
7191 0 : printf("\nWAITING_TID_QUEUES:\n");
7192 :
7193 : /*
7194 : * Search waiting for selection lists. We traverse the
7195 : * list of "their ids" waiting for selection and, if
7196 : * appropriate, traverse the SCBs of each "their id"
7197 : * looking for matches.
7198 : */
7199 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7200 0 : seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
7201 0 : if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
7202 0 : scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
7203 0 : mk_msg_scb = ahd_lookup_scb(ahd, scbid);
7204 0 : } else
7205 : mk_msg_scb = NULL;
7206 0 : savedscbptr = ahd_get_scbptr(ahd);
7207 0 : tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7208 : tid_prev = SCB_LIST_NULL;
7209 : targets = 0;
7210 0 : for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7211 0 : u_int tid_head;
7212 0 : u_int tid_tail;
7213 :
7214 0 : targets++;
7215 0 : if (targets > AHD_NUM_TARGETS)
7216 0 : panic("TID LIST LOOP");
7217 :
7218 0 : if (scbid >= ahd->scb_data.numscbs) {
7219 0 : printf("%s: Waiting TID List inconsistency. "
7220 : "SCB index == 0x%x, yet numscbs == 0x%x.",
7221 0 : ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7222 0 : ahd_dump_card_state(ahd);
7223 0 : panic("for safety");
7224 : }
7225 0 : scb = ahd_lookup_scb(ahd, scbid);
7226 0 : if (scb == NULL) {
7227 0 : printf("%s: SCB = 0x%x Not Active!\n",
7228 0 : ahd_name(ahd), scbid);
7229 0 : panic("Waiting TID List traversal");
7230 : }
7231 0 : ahd_set_scbptr(ahd, scbid);
7232 0 : tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
7233 0 : if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7234 0 : SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
7235 : tid_prev = scbid;
7236 0 : continue;
7237 : }
7238 :
7239 : /*
7240 : * We found a list of scbs that needs to be searched.
7241 : */
7242 0 : if (action == SEARCH_PRINT)
7243 0 : printf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7244 0 : tid_head = scbid;
7245 0 : found += ahd_search_scb_list(ahd, target, channel,
7246 : lun, tag, role, status,
7247 : action, &tid_head, &tid_tail,
7248 0 : SCB_GET_TARGET(ahd, scb));
7249 : /*
7250 : * Check any MK_MESSAGE SCB that is still waiting to
7251 : * enter this target's waiting for selection queue.
7252 : */
7253 0 : if (mk_msg_scb != NULL
7254 0 : && ahd_match_scb(ahd, mk_msg_scb, target, channel,
7255 : lun, tag, role)) {
7256 :
7257 : /*
7258 : * We found an scb that needs to be acted on.
7259 : */
7260 0 : found++;
7261 0 : switch (action) {
7262 : case SEARCH_COMPLETE:
7263 0 : if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
7264 0 : printf("Inactive SCB pending MK_MSG\n");
7265 0 : ahd_done_with_status(ahd, mk_msg_scb, status);
7266 : /* FALLTHROUGH */
7267 : case SEARCH_REMOVE:
7268 : {
7269 : u_int tail_offset;
7270 :
7271 0 : printf("Removing MK_MSG scb\n");
7272 :
7273 : /*
7274 : * Reset our tail to the tail of the
7275 : * main per-target list.
7276 : */
7277 : tail_offset = WAITING_SCB_TAILS
7278 0 : + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
7279 0 : ahd_outw(ahd, tail_offset, tid_tail);
7280 :
7281 0 : seq_flags2 &= ~PENDING_MK_MESSAGE;
7282 0 : ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7283 0 : ahd_outw(ahd, CMDS_PENDING,
7284 0 : ahd_inw(ahd, CMDS_PENDING)-1);
7285 : mk_msg_scb = NULL;
7286 : break;
7287 : }
7288 : case SEARCH_PRINT:
7289 0 : printf(" 0x%x", SCB_GET_TAG(scb));
7290 : /* FALLTHROUGH */
7291 : case SEARCH_COUNT:
7292 : break;
7293 : }
7294 : }
7295 :
7296 0 : if (mk_msg_scb != NULL
7297 0 : && SCBID_IS_NULL(tid_head)
7298 0 : && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7299 : SCB_LIST_NULL, ROLE_UNKNOWN)) {
7300 :
7301 : /*
7302 : * When removing the last SCB for a target
7303 : * queue with a pending MK_MESSAGE scb, we
7304 : * must queue the MK_MESSAGE scb.
7305 : */
7306 0 : printf("Queueing mk_msg_scb\n");
7307 0 : tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
7308 0 : seq_flags2 &= ~PENDING_MK_MESSAGE;
7309 0 : ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7310 : mk_msg_scb = NULL;
7311 0 : }
7312 0 : if (tid_head != scbid)
7313 0 : ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7314 0 : if (!SCBID_IS_NULL(tid_head))
7315 0 : tid_prev = tid_head;
7316 0 : if (action == SEARCH_PRINT)
7317 0 : printf(")\n");
7318 0 : }
7319 :
7320 : /* Restore saved state. */
7321 0 : ahd_set_scbptr(ahd, savedscbptr);
7322 0 : ahd_restore_modes(ahd, saved_modes);
7323 0 : return (found);
7324 : }
7325 :
7326 : int
7327 0 : ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7328 : int lun, u_int tag, role_t role, uint32_t status,
7329 : ahd_search_action action, u_int *list_head,
7330 : u_int *list_tail, u_int tid)
7331 : {
7332 : struct scb *scb;
7333 : u_int scbid;
7334 : u_int next;
7335 : u_int prev;
7336 : int found;
7337 :
7338 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7339 : found = 0;
7340 : prev = SCB_LIST_NULL;
7341 0 : next = *list_head;
7342 0 : *list_tail = SCB_LIST_NULL;
7343 0 : for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7344 0 : if (scbid >= ahd->scb_data.numscbs) {
7345 0 : printf("%s:SCB List inconsistency. "
7346 : "SCB == 0x%x, yet numscbs == 0x%x.",
7347 0 : ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7348 0 : ahd_dump_card_state(ahd);
7349 0 : panic("for safety");
7350 : }
7351 0 : scb = ahd_lookup_scb(ahd, scbid);
7352 0 : if (scb == NULL) {
7353 0 : printf("%s: SCB = %d Not Active!\n",
7354 0 : ahd_name(ahd), scbid);
7355 0 : panic("Waiting List traversal");
7356 : }
7357 0 : ahd_set_scbptr(ahd, scbid);
7358 0 : *list_tail = scbid;
7359 0 : next = ahd_inw_scbram(ahd, SCB_NEXT);
7360 0 : if (ahd_match_scb(ahd, scb, target, channel,
7361 0 : lun, SCB_LIST_NULL, role) == 0) {
7362 : prev = scbid;
7363 0 : continue;
7364 : }
7365 0 : found++;
7366 0 : switch (action) {
7367 : case SEARCH_COMPLETE:
7368 0 : if ((scb->flags & SCB_ACTIVE) == 0)
7369 0 : printf("Inactive SCB in Waiting List\n");
7370 0 : ahd_done_with_status(ahd, scb, status);
7371 : /* FALLTHROUGH */
7372 : case SEARCH_REMOVE:
7373 0 : ahd_rem_wscb(ahd, scbid, prev, next, tid);
7374 0 : *list_tail = prev;
7375 0 : if (SCBID_IS_NULL(prev))
7376 0 : *list_head = next;
7377 : break;
7378 : case SEARCH_PRINT:
7379 0 : printf("0x%x ", scbid);
7380 : case SEARCH_COUNT:
7381 : prev = scbid;
7382 0 : break;
7383 : }
7384 0 : if (found > AHD_SCB_MAX)
7385 0 : panic("SCB LIST LOOP");
7386 : }
7387 0 : if (action == SEARCH_COMPLETE
7388 0 : || action == SEARCH_REMOVE)
7389 0 : ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7390 0 : return (found);
7391 : }
7392 :
7393 : void
7394 0 : ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7395 : u_int tid_cur, u_int tid_next)
7396 : {
7397 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7398 :
7399 0 : if (SCBID_IS_NULL(tid_cur)) {
7400 :
7401 : /* Bypass current TID list */
7402 0 : if (SCBID_IS_NULL(tid_prev)) {
7403 0 : ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7404 0 : } else {
7405 0 : ahd_set_scbptr(ahd, tid_prev);
7406 0 : ahd_outw(ahd, SCB_NEXT2, tid_next);
7407 : }
7408 0 : if (SCBID_IS_NULL(tid_next))
7409 0 : ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
7410 : } else {
7411 :
7412 : /* Stitch through tid_cur */
7413 0 : if (SCBID_IS_NULL(tid_prev)) {
7414 0 : ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
7415 0 : } else {
7416 0 : ahd_set_scbptr(ahd, tid_prev);
7417 0 : ahd_outw(ahd, SCB_NEXT2, tid_cur);
7418 : }
7419 0 : ahd_set_scbptr(ahd, tid_cur);
7420 0 : ahd_outw(ahd, SCB_NEXT2, tid_next);
7421 :
7422 0 : if (SCBID_IS_NULL(tid_next))
7423 0 : ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
7424 : }
7425 0 : }
7426 :
7427 : /*
7428 : * Manipulate the waiting for selection list and return the
7429 : * scb that follows the one that we remove.
7430 : */
7431 : u_int
7432 0 : ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7433 : u_int prev, u_int next, u_int tid)
7434 : {
7435 : u_int tail_offset;
7436 :
7437 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7438 0 : if (!SCBID_IS_NULL(prev)) {
7439 0 : ahd_set_scbptr(ahd, prev);
7440 0 : ahd_outw(ahd, SCB_NEXT, next);
7441 0 : }
7442 :
7443 : /*
7444 : * SCBs that have MK_MESSAGE set in them may
7445 : * cause the tail pointer to be updated without
7446 : * setting the next pointer of the previous tail.
7447 : * Only clear the tail if the removed SCB was
7448 : * the tail.
7449 : */
7450 0 : tail_offset = WAITING_SCB_TAILS + (2 * tid);
7451 0 : if (SCBID_IS_NULL(next)
7452 0 : && ahd_inw(ahd, tail_offset) == scbid)
7453 0 : ahd_outw(ahd, tail_offset, prev);
7454 :
7455 0 : ahd_add_scb_to_free_list(ahd, scbid);
7456 0 : return (next);
7457 : }
7458 :
7459 : /*
7460 : * Add the SCB as selected by SCBPTR onto the on chip list of
7461 : * free hardware SCBs. This list is empty/unused if we are not
7462 : * performing SCB paging.
7463 : */
7464 : void
7465 0 : ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
7466 : {
7467 : /* XXX Need some other mechanism to designate "free". */
7468 : /*
7469 : * Invalidate the tag so that our abort
7470 : * routines don't think it's active.
7471 : ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7472 : */
7473 0 : }
7474 :
7475 : /******************************** Error Handling ******************************/
7476 : /*
7477 : * Abort all SCBs that match the given description (target/channel/lun/tag),
7478 : * setting their status to the passed in status if the status has not already
7479 : * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7480 : * is paused before it is called.
7481 : */
7482 : int
7483 0 : ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7484 : int lun, u_int tag, role_t role, uint32_t status)
7485 : {
7486 : struct scb *scbp;
7487 : struct scb *scbp_next;
7488 : u_int i, j;
7489 : u_int maxtarget;
7490 : u_int minlun;
7491 : u_int maxlun;
7492 : int found;
7493 : ahd_mode_state saved_modes;
7494 :
7495 : /* restore this when we're done */
7496 0 : saved_modes = ahd_save_modes(ahd);
7497 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7498 :
7499 0 : found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7500 : role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7501 :
7502 : /*
7503 : * Clean out the busy target table for any untagged commands.
7504 : */
7505 : i = 0;
7506 : maxtarget = 16;
7507 0 : if (target != CAM_TARGET_WILDCARD) {
7508 : i = target;
7509 0 : if (channel == 'B')
7510 0 : i += 8;
7511 0 : maxtarget = i + 1;
7512 0 : }
7513 :
7514 0 : if (lun == CAM_LUN_WILDCARD) {
7515 : minlun = 0;
7516 : maxlun = AHD_NUM_LUNS_NONPKT;
7517 0 : } else if (lun >= AHD_NUM_LUNS_NONPKT) {
7518 : minlun = maxlun = 0;
7519 0 : } else {
7520 : minlun = lun;
7521 0 : maxlun = lun + 1;
7522 : }
7523 :
7524 0 : if (role != ROLE_TARGET) {
7525 0 : for (;i < maxtarget; i++) {
7526 0 : for (j = minlun;j < maxlun; j++) {
7527 : u_int scbid;
7528 : u_int tcl;
7529 :
7530 0 : tcl = BUILD_TCL_RAW(i, 'A', j);
7531 0 : scbid = ahd_find_busy_tcl(ahd, tcl);
7532 0 : scbp = ahd_lookup_scb(ahd, scbid);
7533 0 : if (scbp == NULL
7534 0 : || ahd_match_scb(ahd, scbp, target, channel,
7535 0 : lun, tag, role) == 0)
7536 0 : continue;
7537 0 : ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7538 0 : }
7539 : }
7540 : }
7541 :
7542 : /*
7543 : * Don't abort commands that have already completed,
7544 : * but haven't quite made it up to the host yet.
7545 : */
7546 0 : ahd_flush_qoutfifo(ahd);
7547 :
7548 : /*
7549 : * Go through the pending CCB list and look for
7550 : * commands for this target that are still active.
7551 : * These are other tagged commands that were
7552 : * disconnected when the reset occurred.
7553 : */
7554 0 : scbp_next = TAILQ_FIRST(&ahd->pending_scbs);
7555 0 : while (scbp_next != NULL) {
7556 : scbp = scbp_next;
7557 0 : scbp_next = TAILQ_NEXT(scbp, next);
7558 0 : if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7559 : cam_status ostat;
7560 :
7561 0 : ostat = aic_get_transaction_status(scbp);
7562 0 : if (ostat == CAM_REQ_INPROG)
7563 0 : aic_set_transaction_status(scbp, status);
7564 0 : if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
7565 : aic_freeze_scb(scbp);
7566 0 : if ((scbp->flags & SCB_ACTIVE) == 0)
7567 0 : printf("Inactive SCB on pending list\n");
7568 0 : ahd_done(ahd, scbp);
7569 0 : found++;
7570 0 : }
7571 : }
7572 0 : ahd_restore_modes(ahd, saved_modes);
7573 0 : ahd->flags |= AHD_UPDATE_PEND_CMDS;
7574 0 : return found;
7575 : }
7576 :
7577 : void
7578 0 : ahd_reset_current_bus(struct ahd_softc *ahd)
7579 : {
7580 : uint8_t scsiseq;
7581 :
7582 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7583 0 : ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7584 0 : scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
7585 0 : ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7586 0 : ahd_flush_device_writes(ahd);
7587 0 : aic_delay(AHD_BUSRESET_DELAY);
7588 : /* Turn off the bus reset */
7589 0 : ahd_outb(ahd, SCSISEQ0, scsiseq);
7590 0 : ahd_flush_device_writes(ahd);
7591 0 : aic_delay(AHD_BUSRESET_DELAY);
7592 0 : if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7593 : /*
7594 : * 2A Razor #474
7595 : * Certain chip state is not cleared for
7596 : * SCSI bus resets that we initiate, so
7597 : * we must reset the chip.
7598 : */
7599 0 : ahd_reset(ahd, /*reinit*/TRUE);
7600 0 : ahd_intr_enable(ahd, /*enable*/TRUE);
7601 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7602 0 : }
7603 :
7604 0 : ahd_clear_intstat(ahd);
7605 0 : }
7606 :
7607 : int
7608 0 : ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7609 : {
7610 : u_int initiator;
7611 : u_int target;
7612 : u_int max_scsiid;
7613 : int found;
7614 : u_int fifo;
7615 : u_int next_fifo;
7616 :
7617 0 : ahd->pending_device = NULL;
7618 :
7619 0 : ahd_pause(ahd);
7620 :
7621 : /* Make sure the sequencer is in a safe location. */
7622 0 : ahd_clear_critical_section(ahd);
7623 :
7624 : #if AHD_TARGET_MODE
7625 : if ((ahd->flags & AHD_TARGETROLE) != 0) {
7626 : ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7627 : }
7628 : #endif
7629 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7630 :
7631 : /*
7632 : * Disable selections so no automatic hardware
7633 : * functions will modify chip state.
7634 : */
7635 0 : ahd_outb(ahd, SCSISEQ0, 0);
7636 0 : ahd_outb(ahd, SCSISEQ1, 0);
7637 :
7638 : /*
7639 : * Safely shut down our DMA engines. Always start with
7640 : * the FIFO that is not currently active (if any are
7641 : * actively connected).
7642 : */
7643 0 : next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7644 0 : if (next_fifo > CURRFIFO_1)
7645 : /* If disconneced, arbitrarily start with FIFO1. */
7646 0 : next_fifo = fifo = 0;
7647 0 : do {
7648 0 : next_fifo ^= CURRFIFO_1;
7649 0 : ahd_set_modes(ahd, next_fifo, next_fifo);
7650 0 : ahd_outb(ahd, DFCNTRL,
7651 : ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7652 0 : while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7653 0 : aic_delay(10);
7654 : /*
7655 : * Set CURRFIFO to the now inactive channel.
7656 : */
7657 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7658 0 : ahd_outb(ahd, DFFSTAT, next_fifo);
7659 0 : } while (next_fifo != fifo);
7660 :
7661 : /*
7662 : * Reset the bus if we are initiating this reset
7663 : */
7664 0 : ahd_clear_msg_state(ahd);
7665 0 : ahd_outb(ahd, SIMODE1,
7666 : ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
7667 :
7668 0 : if (initiate_reset)
7669 0 : ahd_reset_current_bus(ahd);
7670 :
7671 0 : ahd_clear_intstat(ahd);
7672 :
7673 : /*
7674 : * Clean up all the state information for the
7675 : * pending transactions on this bus.
7676 : */
7677 0 : found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
7678 : CAM_LUN_WILDCARD, SCB_LIST_NULL,
7679 : ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
7680 :
7681 : /*
7682 : * Cleanup anything left in the FIFOs.
7683 : */
7684 0 : ahd_clear_fifo(ahd, 0);
7685 0 : ahd_clear_fifo(ahd, 1);
7686 :
7687 : /*
7688 : * Revert to async/narrow transfers until we renegotiate.
7689 : */
7690 0 : max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7691 0 : for (target = 0; target <= max_scsiid; target++) {
7692 :
7693 0 : if (ahd->enabled_targets[target] == NULL)
7694 : continue;
7695 0 : for (initiator = 0; initiator <= max_scsiid; initiator++) {
7696 0 : struct ahd_devinfo devinfo;
7697 :
7698 0 : ahd_compile_devinfo(&devinfo, target, initiator,
7699 : CAM_LUN_WILDCARD,
7700 : 'A', ROLE_UNKNOWN);
7701 0 : ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7702 : AHD_TRANS_CUR, /*paused*/TRUE);
7703 0 : ahd_set_syncrate(ahd, &devinfo, /*period*/0,
7704 : /*offset*/0, /*ppr_options*/0,
7705 : AHD_TRANS_CUR, /*paused*/TRUE);
7706 0 : }
7707 : }
7708 :
7709 : #ifdef AHD_TARGET_MODE
7710 : max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7711 :
7712 : /*
7713 : * Send an immediate notify ccb to all target more peripheral
7714 : * drivers affected by this action.
7715 : */
7716 : for (target = 0; target <= max_scsiid; target++) {
7717 : struct ahd_tmode_tstate* tstate;
7718 : u_int lun;
7719 :
7720 : tstate = ahd->enabled_targets[target];
7721 : if (tstate == NULL)
7722 : continue;
7723 : for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
7724 : struct ahd_tmode_lstate* lstate;
7725 :
7726 : lstate = tstate->enabled_luns[lun];
7727 : if (lstate == NULL)
7728 : continue;
7729 :
7730 : ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
7731 : EVENT_TYPE_BUS_RESET, /*arg*/0);
7732 : ahd_send_lstate_events(ahd, lstate);
7733 : }
7734 : }
7735 : #endif
7736 : #if 0
7737 : /* Notify the XPT that a bus reset occurred */
7738 : ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
7739 : CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
7740 : #endif
7741 0 : ahd_restart(ahd);
7742 : /*
7743 : * Freeze the SIMQ until our poller can determine that
7744 : * the bus reset has really gone away. We set the initial
7745 : * timer to 0 to have the check performed as soon as possible
7746 : * from the timer context.
7747 : */
7748 0 : if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
7749 0 : ahd->flags |= AHD_RESET_POLL_ACTIVE;
7750 : aic_freeze_simq(ahd);
7751 0 : aic_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
7752 0 : }
7753 0 : return (found);
7754 : }
7755 :
7756 :
7757 : #define AHD_RESET_POLL_MS 1
7758 : void
7759 0 : ahd_reset_poll(void *arg)
7760 : {
7761 : struct ahd_softc *ahd;
7762 : u_int scsiseq1;
7763 : int l;
7764 : int s;
7765 :
7766 0 : ahd_list_lock(&l);
7767 0 : ahd = ahd_find_softc((struct ahd_softc *)arg);
7768 0 : if (ahd == NULL) {
7769 0 : printf("ahd_reset_poll: Instance %p no longer exists\n", arg);
7770 0 : ahd_list_unlock(&l);
7771 0 : return;
7772 : }
7773 0 : ahd_lock(ahd, &s);
7774 0 : ahd_pause(ahd);
7775 0 : ahd_update_modes(ahd);
7776 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7777 0 : ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
7778 0 : if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
7779 0 : aic_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_MS,
7780 0 : ahd_reset_poll, ahd);
7781 0 : ahd_unpause(ahd);
7782 0 : ahd_unlock(ahd, &s);
7783 0 : ahd_list_unlock(&l);
7784 0 : return;
7785 : }
7786 :
7787 : /* Reset is now low. Complete chip reinitialization. */
7788 0 : ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
7789 0 : scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
7790 0 : ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
7791 0 : ahd_unpause(ahd);
7792 0 : ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
7793 0 : ahd_unlock(ahd, &s);
7794 : aic_release_simq(ahd);
7795 0 : ahd_list_unlock(&l);
7796 0 : }
7797 :
7798 : /**************************** Statistics Processing ***************************/
7799 : void
7800 0 : ahd_stat_timer(void *arg)
7801 : {
7802 : struct ahd_softc *ahd;
7803 : int l;
7804 : int s;
7805 : int enint_coal;
7806 :
7807 0 : ahd_list_lock(&l);
7808 0 : ahd = ahd_find_softc((struct ahd_softc *)arg);
7809 0 : if (ahd == NULL) {
7810 0 : printf("ahd_stat_timer: Instance %p no longer exists\n", arg);
7811 0 : ahd_list_unlock(&l);
7812 0 : return;
7813 : }
7814 0 : ahd_lock(ahd, &s);
7815 :
7816 0 : enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
7817 0 : if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
7818 0 : enint_coal |= ENINT_COALESCE;
7819 0 : else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
7820 0 : enint_coal &= ~ENINT_COALESCE;
7821 :
7822 0 : if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
7823 0 : ahd_enable_coalescing(ahd, enint_coal);
7824 : #ifdef AHD_DEBUG
7825 : if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
7826 : printf("%s: Interrupt coalescing "
7827 : "now %sabled. Cmds %d\n",
7828 : ahd_name(ahd),
7829 : (enint_coal & ENINT_COALESCE) ? "en" : "dis",
7830 : ahd->cmdcmplt_total);
7831 : #endif
7832 0 : }
7833 :
7834 0 : ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
7835 0 : ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
7836 0 : ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
7837 0 : aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
7838 0 : ahd_stat_timer, ahd);
7839 0 : ahd_unlock(ahd, &s);
7840 0 : ahd_list_unlock(&l);
7841 0 : }
7842 :
7843 : /****************************** Status Processing *****************************/
7844 : void
7845 0 : ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
7846 : {
7847 0 : if (scb->hscb->shared_data.istatus.scsi_status != 0) {
7848 0 : ahd_handle_scsi_status(ahd, scb);
7849 0 : } else {
7850 0 : ahd_calc_residual(ahd, scb);
7851 0 : ahd_done(ahd, scb);
7852 : }
7853 0 : }
7854 :
7855 : void
7856 0 : ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
7857 : {
7858 : struct hardware_scb *hscb;
7859 : int paused;
7860 :
7861 : /*
7862 : * The sequencer freezes its select-out queue
7863 : * anytime a SCSI status error occurs. We must
7864 : * handle the error and increment our qfreeze count
7865 : * to allow the sequencer to continue. We don't
7866 : * bother clearing critical sections here since all
7867 : * operations are on data structures that the sequencer
7868 : * is not touching once the queue is frozen.
7869 : */
7870 0 : hscb = scb->hscb;
7871 :
7872 0 : if (ahd_is_paused(ahd)) {
7873 : paused = 1;
7874 0 : } else {
7875 : paused = 0;
7876 0 : ahd_pause(ahd);
7877 : }
7878 :
7879 : /* Freeze the queue until the client sees the error. */
7880 0 : ahd_freeze_devq(ahd, scb);
7881 : aic_freeze_scb(scb);
7882 0 : ahd->qfreeze_cnt++;
7883 0 : ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7884 :
7885 0 : if (paused == 0)
7886 0 : ahd_unpause(ahd);
7887 :
7888 : /* Don't want to clobber the original sense code */
7889 0 : if ((scb->flags & SCB_SENSE) != 0) {
7890 : /*
7891 : * Clear the SCB_SENSE Flag and perform
7892 : * a normal command completion.
7893 : */
7894 0 : scb->flags &= ~SCB_SENSE;
7895 0 : aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
7896 0 : ahd_done(ahd, scb);
7897 0 : return;
7898 : }
7899 0 : aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
7900 0 : aic_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
7901 0 : switch (hscb->shared_data.istatus.scsi_status) {
7902 : case STATUS_PKT_SENSE:
7903 : {
7904 : struct scsi_status_iu_header *siu;
7905 :
7906 0 : ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
7907 0 : siu = (struct scsi_status_iu_header *)scb->sense_data;
7908 0 : aic_set_scsi_status(scb, siu->status);
7909 : #ifdef AHD_DEBUG
7910 : if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
7911 : ahd_print_path(ahd, scb);
7912 : printf("SCB 0x%x Received PKT Status of 0x%x\n",
7913 : SCB_GET_TAG(scb), siu->status);
7914 : printf("\tflags = 0x%x, sense len = 0x%x, "
7915 : "pktfail = 0x%x\n",
7916 : siu->flags, scsi_4btoul(siu->sense_length),
7917 : scsi_4btoul(siu->pkt_failures_length));
7918 : }
7919 : #endif
7920 0 : if ((siu->flags & SIU_RSPVALID) != 0) {
7921 0 : ahd_print_path(ahd, scb);
7922 0 : if (scsi_4btoul(siu->pkt_failures_length) < 4) {
7923 0 : printf("Unable to parse pkt_failures\n");
7924 0 : } else {
7925 :
7926 0 : switch (SIU_PKTFAIL_CODE(siu)) {
7927 : case SIU_PFC_NONE:
7928 0 : printf("No packet failure found\n");
7929 0 : break;
7930 : case SIU_PFC_CIU_FIELDS_INVALID:
7931 0 : printf("Invalid Command IU Field\n");
7932 0 : break;
7933 : case SIU_PFC_TMF_NOT_SUPPORTED:
7934 0 : printf("TMF not supportd\n");
7935 0 : break;
7936 : case SIU_PFC_TMF_FAILED:
7937 0 : printf("TMF failed\n");
7938 0 : break;
7939 : case SIU_PFC_INVALID_TYPE_CODE:
7940 0 : printf("Invalid L_Q Type code\n");
7941 0 : break;
7942 : case SIU_PFC_ILLEGAL_REQUEST:
7943 0 : printf("Illegal request\n");
7944 : default:
7945 : break;
7946 : }
7947 : }
7948 0 : if (siu->status == SCSI_STATUS_OK)
7949 0 : aic_set_transaction_status(scb,
7950 : CAM_REQ_CMP_ERR);
7951 : }
7952 0 : if ((siu->flags & SIU_SNSVALID) != 0) {
7953 0 : scb->flags |= SCB_PKT_SENSE;
7954 : #ifdef AHD_DEBUG
7955 : if ((ahd_debug & AHD_SHOW_SENSE) != 0)
7956 : printf("Sense data available\n");
7957 : #endif
7958 0 : }
7959 0 : ahd_done(ahd, scb);
7960 : break;
7961 : }
7962 : case SCSI_STATUS_CMD_TERMINATED:
7963 : case SCSI_STATUS_CHECK_COND:
7964 : {
7965 0 : struct ahd_devinfo devinfo;
7966 : struct ahd_dma_seg *sg;
7967 : struct scsi_sense *sc;
7968 : struct ahd_initiator_tinfo *targ_info;
7969 0 : struct ahd_tmode_tstate *tstate;
7970 : struct ahd_transinfo *tinfo;
7971 : #ifdef AHD_DEBUG
7972 : if (ahd_debug & AHD_SHOW_SENSE) {
7973 : ahd_print_path(ahd, scb);
7974 : printf("SCB %d: requests Check Status\n",
7975 : SCB_GET_TAG(scb));
7976 : }
7977 : #endif
7978 :
7979 : if (aic_perform_autosense(scb) == 0)
7980 : break;
7981 :
7982 0 : ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
7983 0 : SCB_GET_TARGET(ahd, scb),
7984 0 : SCB_GET_LUN(scb),
7985 : SCB_GET_CHANNEL(ahd, scb),
7986 : ROLE_INITIATOR);
7987 0 : targ_info = ahd_fetch_transinfo(ahd,
7988 0 : devinfo.channel,
7989 0 : devinfo.our_scsiid,
7990 0 : devinfo.target,
7991 : &tstate);
7992 0 : tinfo = &targ_info->curr;
7993 0 : sg = scb->sg_list;
7994 0 : sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
7995 : /*
7996 : * Save off the residual if there is one.
7997 : */
7998 0 : ahd_update_residual(ahd, scb);
7999 : #ifdef AHD_DEBUG
8000 : if (ahd_debug & AHD_SHOW_SENSE) {
8001 : ahd_print_path(ahd, scb);
8002 : printf("Sending Sense\n");
8003 : }
8004 : #endif
8005 0 : scb->sg_count = 0;
8006 0 : sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8007 : aic_get_sense_bufsize(ahd, scb),
8008 : /*last*/TRUE);
8009 0 : sc->opcode = REQUEST_SENSE;
8010 0 : sc->byte2 = 0;
8011 0 : if (tinfo->protocol_version <= SCSI_REV_2
8012 0 : && SCB_GET_LUN(scb) < 8)
8013 0 : sc->byte2 = SCB_GET_LUN(scb) << 5;
8014 0 : sc->unused[0] = 0;
8015 0 : sc->unused[1] = 0;
8016 0 : sc->length = aic_get_sense_bufsize(ahd, scb);
8017 0 : sc->control = 0;
8018 :
8019 : /*
8020 : * We can't allow the target to disconnect.
8021 : * This will be an untagged transaction and
8022 : * having the target disconnect will make this
8023 : * transaction indestinguishable from outstanding
8024 : * tagged transactions.
8025 : */
8026 0 : hscb->control = 0;
8027 :
8028 : /*
8029 : * This request sense could be because the
8030 : * the device lost power or in some other
8031 : * way has lost our transfer negotiations.
8032 : * Renegotiate if appropriate. Unit attention
8033 : * errors will be reported before any data
8034 : * phases occur.
8035 : */
8036 0 : if (aic_get_residual(scb) == aic_get_transfer_length(scb)) {
8037 0 : ahd_update_neg_request(ahd, &devinfo,
8038 0 : tstate, targ_info,
8039 : AHD_NEG_IF_NON_ASYNC);
8040 0 : }
8041 0 : if (tstate->auto_negotiate & devinfo.target_mask) {
8042 0 : hscb->control |= MK_MESSAGE;
8043 0 : scb->flags &=
8044 : ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8045 0 : scb->flags |= SCB_AUTO_NEGOTIATE;
8046 0 : }
8047 0 : hscb->cdb_len = sizeof(*sc);
8048 0 : ahd_setup_data_scb(ahd, scb);
8049 0 : scb->flags |= SCB_SENSE;
8050 0 : ahd_queue_scb(ahd, scb);
8051 : /*
8052 : * Ensure we have enough time to actually
8053 : * retrieve the sense, but only schedule
8054 : * the timer if we are not in recovery or
8055 : * this is a recovery SCB that is allowed
8056 : * to have an active timer.
8057 : */
8058 0 : aic_scb_timer_reset(scb, 5 * 1000);
8059 : break;
8060 0 : }
8061 : case SCSI_STATUS_OK:
8062 0 : printf("%s: Interrupted for staus of 0???\n",
8063 0 : ahd_name(ahd));
8064 : /* FALLTHROUGH */
8065 : default:
8066 0 : ahd_done(ahd, scb);
8067 0 : break;
8068 : }
8069 0 : }
8070 :
8071 : /*
8072 : * Calculate the residual for a just completed SCB.
8073 : */
8074 : void
8075 0 : ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
8076 : {
8077 : struct hardware_scb *hscb;
8078 : struct initiator_status *spkt;
8079 : uint32_t sgptr;
8080 : uint32_t resid_sgptr;
8081 : uint32_t resid;
8082 :
8083 : /*
8084 : * 5 cases.
8085 : * 1) No residual.
8086 : * SG_STATUS_VALID clear in sgptr.
8087 : * 2) Transferless command
8088 : * 3) Never performed any transfers.
8089 : * sgptr has SG_FULL_RESID set.
8090 : * 4) No residual but target did not
8091 : * save data pointers after the
8092 : * last transfer, so sgptr was
8093 : * never updated.
8094 : * 5) We have a partial residual.
8095 : * Use residual_sgptr to determine
8096 : * where we are.
8097 : */
8098 :
8099 0 : hscb = scb->hscb;
8100 0 : sgptr = aic_le32toh(hscb->sgptr);
8101 0 : if ((sgptr & SG_STATUS_VALID) == 0)
8102 : /* Case 1 */
8103 0 : return;
8104 0 : sgptr &= ~SG_STATUS_VALID;
8105 :
8106 0 : if ((sgptr & SG_LIST_NULL) != 0)
8107 : /* Case 2 */
8108 0 : return;
8109 :
8110 : /*
8111 : * Residual fields are the same in both
8112 : * target and initiator status packets,
8113 : * so we can always use the initiator fields
8114 : * regardless of the role for this SCB.
8115 : */
8116 0 : spkt = &hscb->shared_data.istatus;
8117 0 : resid_sgptr = aic_le32toh(spkt->residual_sgptr);
8118 0 : if ((sgptr & SG_FULL_RESID) != 0) {
8119 : /* Case 3 */
8120 0 : resid = aic_get_transfer_length(scb);
8121 0 : } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8122 : /* Case 4 */
8123 0 : return;
8124 0 : } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8125 0 : ahd_print_path(ahd, scb);
8126 0 : printf("data overrun detected Tag == 0x%x.\n",
8127 0 : SCB_GET_TAG(scb));
8128 0 : ahd_freeze_devq(ahd, scb);
8129 0 : aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8130 : aic_freeze_scb(scb);
8131 0 : return;
8132 0 : } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8133 0 : panic("Bogus resid sgptr value 0x%x", resid_sgptr);
8134 : /* NOTREACHED */
8135 : } else {
8136 : struct ahd_dma_seg *sg;
8137 :
8138 : /*
8139 : * Remainder of the SG where the transfer
8140 : * stopped.
8141 : */
8142 0 : resid = aic_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8143 0 : sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8144 :
8145 : /* The residual sg_ptr always points to the next sg */
8146 0 : sg--;
8147 :
8148 : /*
8149 : * Add up the contents of all residual
8150 : * SG segments that are after the SG where
8151 : * the transfer stopped.
8152 : */
8153 0 : while ((aic_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8154 0 : sg++;
8155 0 : resid += aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
8156 : }
8157 : }
8158 : if ((scb->flags & SCB_SENSE) == 0)
8159 : aic_set_residual(scb, resid);
8160 : else
8161 : aic_set_sense_residual(scb, resid);
8162 :
8163 : #ifdef AHD_DEBUG
8164 : if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8165 : ahd_print_path(ahd, scb);
8166 : printf("Handled %sResidual of %d bytes\n",
8167 : (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
8168 : }
8169 : #endif
8170 0 : }
8171 :
8172 : /******************************* Target Mode **********************************/
8173 : #ifdef AHD_TARGET_MODE
8174 : /*
8175 : * Add a target mode event to this lun's queue
8176 : */
8177 : void
8178 : ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
8179 : u_int initiator_id, u_int event_type, u_int event_arg)
8180 : {
8181 : struct ahd_tmode_event *event;
8182 : int pending;
8183 :
8184 : xpt_freeze_devq(lstate->path, /*count*/1);
8185 : if (lstate->event_w_idx >= lstate->event_r_idx)
8186 : pending = lstate->event_w_idx - lstate->event_r_idx;
8187 : else
8188 : pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
8189 : - (lstate->event_r_idx - lstate->event_w_idx);
8190 :
8191 : if (event_type == EVENT_TYPE_BUS_RESET
8192 : || event_type == MSG_BUS_DEV_RESET) {
8193 : /*
8194 : * Any earlier events are irrelevant, so reset our buffer.
8195 : * This has the effect of allowing us to deal with reset
8196 : * floods (an external device holding down the reset line)
8197 : * without losing the event that is really interesting.
8198 : */
8199 : lstate->event_r_idx = 0;
8200 : lstate->event_w_idx = 0;
8201 : xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
8202 : }
8203 :
8204 : if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
8205 : xpt_print_path(lstate->path);
8206 : printf("immediate event %x:%x lost\n",
8207 : lstate->event_buffer[lstate->event_r_idx].event_type,
8208 : lstate->event_buffer[lstate->event_r_idx].event_arg);
8209 : lstate->event_r_idx++;
8210 : if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8211 : lstate->event_r_idx = 0;
8212 : xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
8213 : }
8214 :
8215 : event = &lstate->event_buffer[lstate->event_w_idx];
8216 : event->initiator_id = initiator_id;
8217 : event->event_type = event_type;
8218 : event->event_arg = event_arg;
8219 : lstate->event_w_idx++;
8220 : if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8221 : lstate->event_w_idx = 0;
8222 : }
8223 :
8224 : /*
8225 : * Send any target mode events queued up waiting
8226 : * for immediate notify resources.
8227 : */
8228 : void
8229 : ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
8230 : {
8231 : struct ccb_hdr *ccbh;
8232 : struct ccb_immed_notify *inot;
8233 :
8234 : while (lstate->event_r_idx != lstate->event_w_idx
8235 : && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
8236 : struct ahd_tmode_event *event;
8237 :
8238 : event = &lstate->event_buffer[lstate->event_r_idx];
8239 : SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
8240 : inot = (struct ccb_immed_notify *)ccbh;
8241 : switch (event->event_type) {
8242 : case EVENT_TYPE_BUS_RESET:
8243 : ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
8244 : break;
8245 : default:
8246 : ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
8247 : inot->message_args[0] = event->event_type;
8248 : inot->message_args[1] = event->event_arg;
8249 : break;
8250 : }
8251 : inot->initiator_id = event->initiator_id;
8252 : inot->sense_len = 0;
8253 : xpt_done((union ccb *)inot);
8254 : lstate->event_r_idx++;
8255 : if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8256 : lstate->event_r_idx = 0;
8257 : }
8258 : }
8259 : #endif
8260 :
8261 : /******************** Sequencer Program Patching/Download *********************/
8262 :
8263 : #ifdef AHD_DUMP_SEQ
8264 : void
8265 : ahd_dumpseq(struct ahd_softc* ahd)
8266 : {
8267 : int i;
8268 : int max_prog;
8269 :
8270 : max_prog = 2048;
8271 :
8272 : ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8273 : ahd_outw(ahd, PRGMCNT, 0);
8274 : for (i = 0; i < max_prog; i++) {
8275 : uint8_t ins_bytes[4];
8276 :
8277 : ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8278 : printf("0x%08x\n", ins_bytes[0] << 24
8279 : | ins_bytes[1] << 16
8280 : | ins_bytes[2] << 8
8281 : | ins_bytes[3]);
8282 : }
8283 : }
8284 : #endif
8285 :
8286 : void
8287 0 : ahd_loadseq(struct ahd_softc *ahd)
8288 : {
8289 0 : struct cs cs_table[NUM_CRITICAL_SECTIONS];
8290 0 : u_int begin_set[NUM_CRITICAL_SECTIONS];
8291 0 : u_int end_set[NUM_CRITICAL_SECTIONS];
8292 0 : const struct patch *cur_patch;
8293 : u_int cs_count;
8294 : u_int cur_cs;
8295 : u_int i;
8296 : int downloaded;
8297 0 : u_int skip_addr;
8298 : u_int sg_prefetch_cnt;
8299 : u_int sg_prefetch_cnt_limit;
8300 : u_int sg_prefetch_align;
8301 : u_int sg_size;
8302 : u_int cacheline_mask;
8303 0 : uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8304 :
8305 : if (bootverbose)
8306 : printf("%s: Downloading Sequencer Program...",
8307 : ahd_name(ahd));
8308 :
8309 : #if DOWNLOAD_CONST_COUNT != 8
8310 : #error "Download Const Mismatch"
8311 : #endif
8312 : /*
8313 : * Start out with 0 critical sections
8314 : * that apply to this firmware load.
8315 : */
8316 : cs_count = 0;
8317 : cur_cs = 0;
8318 0 : memset(begin_set, 0, sizeof(begin_set));
8319 0 : memset(end_set, 0, sizeof(end_set));
8320 :
8321 : /*
8322 : * Setup downloadable constant table.
8323 : *
8324 : * The computation for the S/G prefetch variables is
8325 : * a bit complicated. We would like to always fetch
8326 : * in terms of cachelined sized increments. However,
8327 : * if the cacheline is not an even multiple of the
8328 : * SG element size or is larger than our SG RAM, using
8329 : * just the cache size might leave us with only a portion
8330 : * of an SG element at the tail of a prefetch. If the
8331 : * cacheline is larger than our S/G prefetch buffer less
8332 : * the size of an SG element, we may round down to a cacheline
8333 : * that doesn't contain any or all of the S/G of interest
8334 : * within the bounds of our S/G ram. Provide variables to
8335 : * the sequencer that will allow it to handle these edge
8336 : * cases.
8337 : */
8338 : /* Start by aligning to the nearest cacheline. */
8339 0 : sg_prefetch_align = ahd->pci_cachesize;
8340 0 : if (sg_prefetch_align == 0)
8341 : sg_prefetch_align = 8;
8342 : /* Round down to the nearest power of 2. */
8343 0 : while (powerof2(sg_prefetch_align) == 0)
8344 0 : sg_prefetch_align--;
8345 :
8346 : cacheline_mask = sg_prefetch_align - 1;
8347 :
8348 : /*
8349 : * If the cacheline boundary is greater than half our prefetch RAM
8350 : * we risk not being able to fetch even a single complete S/G
8351 : * segment if we align to that boundary.
8352 : */
8353 0 : if (sg_prefetch_align > CCSGADDR_MAX/2)
8354 0 : sg_prefetch_align = CCSGADDR_MAX/2;
8355 : /* Start by fetching a single cacheline. */
8356 : sg_prefetch_cnt = sg_prefetch_align;
8357 : /*
8358 : * Increment the prefetch count by cachelines until
8359 : * at least one S/G element will fit.
8360 : */
8361 : sg_size = sizeof(struct ahd_dma_seg);
8362 0 : if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
8363 : sg_size = sizeof(struct ahd_dma64_seg);
8364 0 : while (sg_prefetch_cnt < sg_size)
8365 0 : sg_prefetch_cnt += sg_prefetch_align;
8366 : /*
8367 : * If the cacheline is not an even multiple of
8368 : * the S/G size, we may only get a partial S/G when
8369 : * we align. Add a cacheline if this is the case.
8370 : */
8371 0 : if ((sg_prefetch_align % sg_size) != 0
8372 0 : && (sg_prefetch_cnt < CCSGADDR_MAX))
8373 0 : sg_prefetch_cnt += sg_prefetch_align;
8374 : /*
8375 : * Lastly, compute a value that the sequencer can use
8376 : * to determine if the remainder of the CCSGRAM buffer
8377 : * has a full S/G element in it.
8378 : */
8379 0 : sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8380 0 : download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8381 0 : download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8382 0 : download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8383 0 : download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8384 0 : download_consts[SG_SIZEOF] = sg_size;
8385 0 : download_consts[PKT_OVERRUN_BUFOFFSET] =
8386 0 : (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8387 0 : download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8388 0 : download_consts[CACHELINE_MASK] = cacheline_mask;
8389 0 : cur_patch = patches;
8390 : downloaded = 0;
8391 0 : skip_addr = 0;
8392 0 : ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8393 0 : ahd_outw(ahd, PRGMCNT, 0);
8394 :
8395 0 : for (i = 0; i < sizeof(seqprog)/4; i++) {
8396 0 : if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8397 : /*
8398 : * Don't download this instruction as it
8399 : * is in a patch that was removed.
8400 : */
8401 : continue;
8402 : }
8403 : /*
8404 : * Move through the CS table until we find a CS
8405 : * that might apply to this instruction.
8406 : */
8407 0 : for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) {
8408 0 : if (critical_sections[cur_cs].end <= i) {
8409 0 : if (begin_set[cs_count] == TRUE
8410 0 : && end_set[cs_count] == FALSE) {
8411 0 : cs_table[cs_count].end = downloaded;
8412 0 : end_set[cs_count] = TRUE;
8413 0 : cs_count++;
8414 0 : }
8415 : continue;
8416 : }
8417 0 : if (critical_sections[cur_cs].begin <= i
8418 0 : && begin_set[cs_count] == FALSE) {
8419 0 : cs_table[cs_count].begin = downloaded;
8420 0 : begin_set[cs_count] = TRUE;
8421 0 : }
8422 : break;
8423 : }
8424 0 : ahd_download_instr(ahd, i, download_consts);
8425 0 : downloaded++;
8426 0 : }
8427 :
8428 0 : ahd->num_critical_sections = cs_count;
8429 0 : if (cs_count != 0) {
8430 0 : ahd->critical_sections = mallocarray(cs_count,
8431 : sizeof(struct cs), M_DEVBUF, M_NOWAIT);
8432 0 : if (ahd->critical_sections == NULL)
8433 0 : panic("ahd_loadseq: Could not malloc");
8434 0 : cs_count *= sizeof(struct cs);
8435 :
8436 0 : memcpy(ahd->critical_sections, cs_table, cs_count);
8437 0 : }
8438 0 : ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8439 :
8440 : if (bootverbose) {
8441 : printf(" %d instructions downloaded\n", downloaded);
8442 : printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8443 : ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8444 : }
8445 0 : }
8446 :
8447 : int
8448 0 : ahd_check_patch(struct ahd_softc *ahd, const struct patch **start_patch,
8449 : u_int start_instr, u_int *skip_addr)
8450 : {
8451 : const struct patch *cur_patch;
8452 : const struct patch *last_patch;
8453 : u_int num_patches;
8454 :
8455 : num_patches = sizeof(patches)/sizeof(struct patch);
8456 : last_patch = &patches[num_patches];
8457 0 : cur_patch = *start_patch;
8458 :
8459 0 : while (cur_patch < last_patch && start_instr == cur_patch->begin) {
8460 :
8461 0 : if (cur_patch->patch_func(ahd) == 0) {
8462 :
8463 : /* Start rejecting code */
8464 0 : *skip_addr = start_instr + cur_patch->skip_instr;
8465 0 : cur_patch += cur_patch->skip_patch;
8466 0 : } else {
8467 : /* Accepted this patch. Advance to the next
8468 : * one and wait for our intruction pointer to
8469 : * hit this point.
8470 : */
8471 0 : cur_patch++;
8472 : }
8473 : }
8474 :
8475 0 : *start_patch = cur_patch;
8476 0 : if (start_instr < *skip_addr)
8477 : /* Still skipping */
8478 0 : return (0);
8479 :
8480 0 : return (1);
8481 0 : }
8482 :
8483 : u_int
8484 0 : ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8485 : {
8486 0 : const struct patch *cur_patch;
8487 : int address_offset;
8488 0 : u_int skip_addr;
8489 : u_int i;
8490 :
8491 : address_offset = 0;
8492 0 : cur_patch = patches;
8493 0 : skip_addr = 0;
8494 :
8495 0 : for (i = 0; i < address;) {
8496 :
8497 0 : ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
8498 :
8499 0 : if (skip_addr > i) {
8500 : int end_addr;
8501 :
8502 0 : end_addr = MIN(address, skip_addr);
8503 0 : address_offset += end_addr - i;
8504 : i = skip_addr;
8505 0 : } else {
8506 0 : i++;
8507 : }
8508 : }
8509 0 : return (address - address_offset);
8510 0 : }
8511 :
8512 : void
8513 0 : ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
8514 : {
8515 0 : union ins_formats instr;
8516 : struct ins_format1 *fmt1_ins;
8517 : struct ins_format3 *fmt3_ins;
8518 : u_int opcode;
8519 :
8520 : /*
8521 : * The firmware is always compiled into a little endian format.
8522 : */
8523 0 : instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8524 :
8525 0 : fmt1_ins = &instr.format1;
8526 : fmt3_ins = NULL;
8527 :
8528 : /* Pull the opcode */
8529 0 : opcode = instr.format1.opcode;
8530 0 : switch (opcode) {
8531 : case AIC_OP_JMP:
8532 : case AIC_OP_JC:
8533 : case AIC_OP_JNC:
8534 : case AIC_OP_CALL:
8535 : case AIC_OP_JNE:
8536 : case AIC_OP_JNZ:
8537 : case AIC_OP_JE:
8538 : case AIC_OP_JZ:
8539 : {
8540 0 : fmt3_ins = &instr.format3;
8541 0 : fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
8542 : /* FALLTHROUGH */
8543 0 : }
8544 : case AIC_OP_OR:
8545 : case AIC_OP_AND:
8546 : case AIC_OP_XOR:
8547 : case AIC_OP_ADD:
8548 : case AIC_OP_ADC:
8549 : case AIC_OP_BMOV:
8550 0 : if (fmt1_ins->parity != 0) {
8551 0 : fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
8552 0 : }
8553 0 : fmt1_ins->parity = 0;
8554 : /* FALLTHROUGH */
8555 : case AIC_OP_ROL:
8556 : {
8557 : int i, count;
8558 :
8559 : /* Calculate odd parity for the instruction */
8560 0 : for (i = 0, count = 0; i < 31; i++) {
8561 : uint32_t mask;
8562 :
8563 0 : mask = 0x01 << i;
8564 0 : if ((instr.integer & mask) != 0)
8565 0 : count++;
8566 : }
8567 0 : if ((count & 0x01) == 0)
8568 0 : instr.format1.parity = 1;
8569 :
8570 : /* The sequencer is a little endian cpu */
8571 0 : instr.integer = aic_htole32(instr.integer);
8572 0 : ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8573 : break;
8574 : }
8575 : default:
8576 0 : panic("Unknown opcode encountered in seq program");
8577 : break;
8578 : }
8579 0 : }
8580 :
8581 : int
8582 0 : ahd_probe_stack_size(struct ahd_softc *ahd)
8583 : {
8584 : int last_probe;
8585 :
8586 : last_probe = 0;
8587 0 : while (1) {
8588 : int i;
8589 :
8590 : /*
8591 : * We avoid using 0 as a pattern to avoid
8592 : * confusion if the stack implementation
8593 : * "back-fills" with zeros when "poping'
8594 : * entries.
8595 : */
8596 0 : for (i = 1; i <= last_probe+1; i++) {
8597 0 : ahd_outb(ahd, STACK, i & 0xFF);
8598 0 : ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8599 : }
8600 :
8601 : /* Verify */
8602 0 : for (i = last_probe+1; i > 0; i--) {
8603 : u_int stack_entry;
8604 :
8605 0 : stack_entry = ahd_inb(ahd, STACK)
8606 0 : |(ahd_inb(ahd, STACK) << 8);
8607 0 : if (stack_entry != i)
8608 0 : goto sized;
8609 0 : }
8610 : last_probe++;
8611 0 : }
8612 : sized:
8613 0 : return (last_probe);
8614 0 : }
8615 :
8616 : void
8617 0 : ahd_dump_all_cards_state(void)
8618 : {
8619 : struct ahd_softc *list_ahd;
8620 :
8621 0 : TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
8622 0 : ahd_dump_card_state(list_ahd);
8623 : }
8624 0 : }
8625 :
8626 : int
8627 0 : ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8628 : const char *name, u_int address, u_int value,
8629 : u_int *cur_column, u_int wrap_point)
8630 : {
8631 : u_int printed_mask;
8632 : int entry, printed;
8633 :
8634 0 : if (cur_column != NULL && *cur_column >= wrap_point) {
8635 0 : printf("\n");
8636 0 : *cur_column = 0;
8637 0 : }
8638 0 : printed = printf("%s[0x%x]", name, value);
8639 0 : if (table == NULL) {
8640 0 : printed += printf(" ");
8641 0 : if (cur_column != NULL)
8642 0 : *cur_column += printed;
8643 0 : return (printed);
8644 : }
8645 :
8646 : printed_mask = 0;
8647 0 : while (printed_mask != 0xFF) {
8648 0 : for (entry = 0; entry < num_entries; entry++) {
8649 0 : if (((value & table[entry].mask) != table[entry].value)
8650 0 : || ((printed_mask & table[entry].mask) ==
8651 : table[entry].mask))
8652 : continue;
8653 :
8654 0 : printed += printf("%s%s",
8655 0 : printed_mask == 0 ? ":(" : "|",
8656 0 : table[entry].name);
8657 0 : printed_mask |= table[entry].mask;
8658 :
8659 0 : break;
8660 : }
8661 0 : if (entry >= num_entries)
8662 : break;
8663 : }
8664 :
8665 0 : printed += printf("%s", printed_mask == 0 ? " " : ") ");
8666 0 : if (cur_column != NULL)
8667 0 : *cur_column += printed;
8668 :
8669 0 : return (printed);
8670 0 : }
8671 :
8672 : void
8673 0 : ahd_dump_card_state(struct ahd_softc *ahd)
8674 : {
8675 : struct scb *scb;
8676 : ahd_mode_state saved_modes;
8677 : u_int dffstat;
8678 : int paused;
8679 : u_int scb_index;
8680 : u_int saved_scb_index;
8681 0 : u_int cur_col;
8682 : int i;
8683 :
8684 0 : if (ahd_is_paused(ahd)) {
8685 : paused = 1;
8686 0 : } else {
8687 : paused = 0;
8688 0 : ahd_pause(ahd);
8689 : }
8690 0 : saved_modes = ahd_save_modes(ahd);
8691 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8692 0 : printf("================== Dump Card State Begins =================\n"
8693 : "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8694 0 : ahd_name(ahd),
8695 0 : ahd_inw(ahd, CURADDR),
8696 0 : ahd_build_mode_state(ahd, ahd->saved_src_mode,
8697 0 : ahd->saved_dst_mode));
8698 0 : if (paused)
8699 0 : printf("Card was paused\n");
8700 :
8701 0 : if (ahd_check_cmdcmpltqueues(ahd))
8702 0 : printf("Completions are pending\n");
8703 :
8704 : /*
8705 : * Mode independent registers.
8706 : */
8707 0 : cur_col = 0;
8708 0 : ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
8709 0 : ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
8710 0 : ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
8711 0 : ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
8712 0 : ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
8713 0 : ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
8714 0 : ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
8715 0 : ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
8716 0 : ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
8717 0 : ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
8718 0 : ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
8719 0 : ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
8720 0 : ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
8721 0 : ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
8722 0 : ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
8723 0 : ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
8724 0 : ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
8725 0 : ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
8726 0 : ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
8727 0 : ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
8728 : &cur_col, 50);
8729 0 : ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
8730 0 : ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
8731 : &cur_col, 50);
8732 0 : ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
8733 0 : ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
8734 0 : ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
8735 0 : ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
8736 0 : ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
8737 0 : ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
8738 0 : ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
8739 0 : ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
8740 0 : ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
8741 0 : ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
8742 0 : ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
8743 0 : ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
8744 0 : printf("\n");
8745 0 : printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
8746 : "CURRSCB 0x%x NEXTSCB 0x%x\n",
8747 0 : ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
8748 0 : ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
8749 0 : ahd_inw(ahd, NEXTSCB));
8750 0 : cur_col = 0;
8751 : /* QINFIFO */
8752 0 : ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
8753 : CAM_LUN_WILDCARD, SCB_LIST_NULL,
8754 : ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
8755 0 : saved_scb_index = ahd_get_scbptr(ahd);
8756 0 : printf("Pending list:");
8757 : i = 0;
8758 0 : TAILQ_FOREACH(scb, &ahd->pending_scbs, next) {
8759 0 : if (i++ > AHD_SCB_MAX)
8760 : break;
8761 0 : cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
8762 0 : ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
8763 0 : ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
8764 0 : ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
8765 : &cur_col, 60);
8766 0 : ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
8767 : &cur_col, 60);
8768 : }
8769 0 : printf("\nTotal %d\n", i);
8770 :
8771 0 : printf("Kernel Free SCB list: ");
8772 : i = 0;
8773 0 : TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, next) {
8774 0 : printf("%d ", SCB_GET_TAG(scb));
8775 : }
8776 0 : printf("\n");
8777 :
8778 0 : printf("Sequencer Complete DMA-inprog list: ");
8779 0 : scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
8780 : i = 0;
8781 0 : while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8782 0 : ahd_set_scbptr(ahd, scb_index);
8783 0 : printf("%d ", scb_index);
8784 0 : scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
8785 : }
8786 0 : printf("\n");
8787 :
8788 0 : printf("Sequencer Complete list: ");
8789 0 : scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
8790 : i = 0;
8791 0 : while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8792 0 : ahd_set_scbptr(ahd, scb_index);
8793 0 : printf("%d ", scb_index);
8794 0 : scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
8795 : }
8796 0 : printf("\n");
8797 :
8798 :
8799 0 : printf("Sequencer DMA-Up and Complete list: ");
8800 0 : scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
8801 : i = 0;
8802 0 : while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8803 0 : ahd_set_scbptr(ahd, scb_index);
8804 0 : printf("%d ", scb_index);
8805 0 : scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
8806 : }
8807 0 : printf("\n");
8808 0 : printf("Sequencer On QFreeze and Complete list: ");
8809 0 : scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
8810 : i = 0;
8811 0 : while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8812 0 : ahd_set_scbptr(ahd, scb_index);
8813 0 : printf("%d ", scb_index);
8814 0 : scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
8815 : }
8816 0 : printf("\n");
8817 0 : ahd_set_scbptr(ahd, saved_scb_index);
8818 0 : dffstat = ahd_inb(ahd, DFFSTAT);
8819 0 : for (i = 0; i < 2; i++) {
8820 : #ifdef AHD_DEBUG
8821 : struct scb *fifo_scb;
8822 : #endif
8823 : u_int fifo_scbptr;
8824 :
8825 0 : ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
8826 0 : fifo_scbptr = ahd_get_scbptr(ahd);
8827 0 : printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
8828 0 : ahd_name(ahd), i,
8829 0 : (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
8830 0 : ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
8831 0 : cur_col = 0;
8832 0 : ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
8833 0 : ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
8834 0 : ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
8835 0 : ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
8836 0 : ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
8837 : &cur_col, 50);
8838 0 : ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
8839 0 : ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
8840 0 : ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
8841 0 : ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
8842 0 : if (cur_col > 50) {
8843 0 : printf("\n");
8844 0 : cur_col = 0;
8845 0 : }
8846 0 : cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
8847 0 : ahd_inl(ahd, SHADDR+4),
8848 0 : ahd_inl(ahd, SHADDR),
8849 0 : (ahd_inb(ahd, SHCNT)
8850 0 : | (ahd_inb(ahd, SHCNT + 1) << 8)
8851 0 : | (ahd_inb(ahd, SHCNT + 2) << 16)));
8852 0 : if (cur_col > 50) {
8853 0 : printf("\n");
8854 0 : cur_col = 0;
8855 0 : }
8856 0 : cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ",
8857 0 : ahd_inl(ahd, HADDR+4),
8858 0 : ahd_inl(ahd, HADDR),
8859 0 : (ahd_inb(ahd, HCNT)
8860 0 : | (ahd_inb(ahd, HCNT + 1) << 8)
8861 0 : | (ahd_inb(ahd, HCNT + 2) << 16)));
8862 0 : ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
8863 : #ifdef AHD_DEBUG
8864 : if ((ahd_debug & AHD_SHOW_SG) != 0) {
8865 : fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
8866 : if (fifo_scb != NULL)
8867 : ahd_dump_sglist(fifo_scb);
8868 : }
8869 : #endif
8870 : }
8871 0 : printf("\nLQIN: ");
8872 0 : for (i = 0; i < 20; i++)
8873 0 : printf("0x%x ", ahd_inb(ahd, LQIN + i));
8874 0 : printf("\n");
8875 0 : ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
8876 0 : printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
8877 0 : ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
8878 0 : ahd_inb(ahd, OPTIONMODE));
8879 0 : printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
8880 0 : ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
8881 0 : ahd_inb(ahd, MAXCMDCNT));
8882 0 : printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
8883 0 : ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
8884 0 : ahd_inb(ahd, SAVED_LUN));
8885 0 : ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
8886 0 : printf("\n");
8887 0 : ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
8888 0 : cur_col = 0;
8889 0 : ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
8890 0 : printf("\n");
8891 0 : ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
8892 0 : printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
8893 0 : ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
8894 0 : ahd_inw(ahd, DINDEX));
8895 0 : printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
8896 0 : ahd_name(ahd), ahd_get_scbptr(ahd),
8897 0 : ahd_inw_scbram(ahd, SCB_NEXT),
8898 0 : ahd_inw_scbram(ahd, SCB_NEXT2));
8899 0 : printf("CDB %x %x %x %x %x %x\n",
8900 0 : ahd_inb_scbram(ahd, SCB_CDB_STORE),
8901 0 : ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
8902 0 : ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
8903 0 : ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
8904 0 : ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
8905 0 : ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
8906 0 : printf("STACK:");
8907 0 : for (i = 0; i < ahd->stack_size; i++) {
8908 0 : ahd->saved_stack[i] =
8909 0 : ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
8910 0 : printf(" 0x%x", ahd->saved_stack[i]);
8911 : }
8912 0 : for (i = ahd->stack_size-1; i >= 0; i--) {
8913 0 : ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
8914 0 : ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
8915 : }
8916 0 : printf("\n================= Dump Card State Ends ==================\n");
8917 0 : ahd_platform_dump_card_state(ahd);
8918 0 : ahd_restore_modes(ahd, saved_modes);
8919 0 : if (paused == 0)
8920 0 : ahd_unpause(ahd);
8921 0 : }
8922 :
8923 : void
8924 0 : ahd_dump_scbs(struct ahd_softc *ahd)
8925 : {
8926 : ahd_mode_state saved_modes;
8927 : u_int saved_scb_index;
8928 : int i;
8929 :
8930 0 : saved_modes = ahd_save_modes(ahd);
8931 0 : ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8932 0 : saved_scb_index = ahd_get_scbptr(ahd);
8933 0 : for (i = 0; i < AHD_SCB_MAX; i++) {
8934 0 : ahd_set_scbptr(ahd, i);
8935 0 : printf("%3d", i);
8936 0 : printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
8937 0 : ahd_inb_scbram(ahd, SCB_CONTROL),
8938 0 : ahd_inb_scbram(ahd, SCB_SCSIID),
8939 0 : ahd_inw_scbram(ahd, SCB_NEXT),
8940 0 : ahd_inw_scbram(ahd, SCB_NEXT2),
8941 0 : ahd_inl_scbram(ahd, SCB_SGPTR),
8942 0 : ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
8943 : }
8944 0 : printf("\n");
8945 0 : ahd_set_scbptr(ahd, saved_scb_index);
8946 0 : ahd_restore_modes(ahd, saved_modes);
8947 0 : }
8948 :
8949 :
8950 : /*************************** Timeout Handling *********************************/
8951 : void
8952 0 : ahd_timeout(void *arg)
8953 : {
8954 : struct scb *scb, *list_scb;
8955 : struct ahd_softc *ahd;
8956 : char channel;
8957 : long s;
8958 : int found;
8959 : #ifdef AHD_DEBUG
8960 : int was_paused;
8961 : #endif
8962 :
8963 0 : scb = (struct scb *)arg;
8964 0 : ahd = scb->ahd_softc;
8965 :
8966 0 : ahd_lock(ahd, &s);
8967 :
8968 : #ifdef AHD_DEBUG
8969 : was_paused = ahd_is_paused(ahd);
8970 : printf("%s: SCB %d timed out - Card was %spaused\n", ahd_name(ahd),
8971 : SCB_GET_TAG(scb), was_paused ? "" : "not ");
8972 : ahd_dump_card_state(ahd);
8973 : #endif
8974 :
8975 0 : ahd_pause(ahd);
8976 :
8977 0 : if (scb->flags & SCB_ACTIVE) {
8978 0 : aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
8979 : /*
8980 : * Go through all of our pending SCBs and remove any scheduled
8981 : * timeouts for them. They're about to be aborted so no need
8982 : * for them to timeout.
8983 : */
8984 0 : TAILQ_FOREACH(list_scb, &ahd->pending_scbs, next) {
8985 0 : if (list_scb->xs)
8986 0 : timeout_del(&list_scb->xs->stimeout);
8987 : }
8988 : channel = SCB_GET_CHANNEL(ahd, scb);
8989 0 : found = ahd_reset_channel(ahd, channel, /*Initiate Reset*/TRUE);
8990 : #ifdef AHD_DEBUG
8991 : printf("%s: Issued Channel %c Bus Reset. %d SCBs aborted\n",
8992 : ahd_name(ahd), channel, found);
8993 : #endif
8994 0 : }
8995 :
8996 0 : ahd_unpause(ahd);
8997 0 : ahd_unlock(ahd, &s);
8998 0 : }
8999 :
9000 : /**************************** Flexport Logic **********************************/
9001 : /*
9002 : * Read count 16bit words from 16bit word address start_addr from the
9003 : * SEEPROM attached to the controller, into buf, using the controller's
9004 : * SEEPROM reading state machine. Optionally treat the data as a byte
9005 : * stream in terms of byte order.
9006 : */
9007 : int
9008 0 : ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9009 : u_int start_addr, u_int count, int bytestream)
9010 : {
9011 : u_int cur_addr;
9012 : u_int end_addr;
9013 : int error;
9014 :
9015 : /*
9016 : * If we never make it through the loop even once,
9017 : * we were passed invalid arguments.
9018 : */
9019 : error = EINVAL;
9020 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9021 0 : end_addr = start_addr + count;
9022 0 : for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9023 :
9024 0 : ahd_outb(ahd, SEEADR, cur_addr);
9025 0 : ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9026 :
9027 0 : error = ahd_wait_seeprom(ahd);
9028 0 : if (error) {
9029 0 : printf("%s: ahd_wait_seeprom timed out\n", ahd_name(ahd));
9030 0 : break;
9031 : }
9032 0 : if (bytestream != 0) {
9033 : uint8_t *bytestream_ptr;
9034 :
9035 0 : bytestream_ptr = (uint8_t *)buf;
9036 0 : *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9037 0 : *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9038 0 : } else {
9039 : /*
9040 : * ahd_inw() already handles machine byte order.
9041 : */
9042 0 : *buf = ahd_inw(ahd, SEEDAT);
9043 : }
9044 0 : buf++;
9045 : }
9046 0 : return (error);
9047 : }
9048 :
9049 : /*
9050 : * Write count 16bit words from buf, into SEEPROM attache to the
9051 : * controller starting at 16bit word address start_addr, using the
9052 : * controller's SEEPROM writing state machine.
9053 : */
9054 : int
9055 0 : ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9056 : u_int start_addr, u_int count)
9057 : {
9058 : u_int cur_addr;
9059 : u_int end_addr;
9060 : int error;
9061 : int retval;
9062 :
9063 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9064 :
9065 : /* Place the chip into write-enable mode */
9066 0 : ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
9067 0 : ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
9068 0 : error = ahd_wait_seeprom(ahd);
9069 0 : if (error)
9070 0 : return (error);
9071 :
9072 : /*
9073 : * Write the data. If we don't get throught the loop at
9074 : * least once, the arguments were invalid.
9075 : */
9076 : retval = EINVAL;
9077 0 : end_addr = start_addr + count;
9078 0 : for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9079 0 : ahd_outw(ahd, SEEDAT, *buf++);
9080 0 : ahd_outb(ahd, SEEADR, cur_addr);
9081 0 : ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
9082 :
9083 0 : retval = ahd_wait_seeprom(ahd);
9084 0 : if (retval)
9085 : break;
9086 : }
9087 :
9088 : /*
9089 : * Disable writes.
9090 : */
9091 0 : ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
9092 0 : ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
9093 0 : error = ahd_wait_seeprom(ahd);
9094 0 : if (error)
9095 0 : return (error);
9096 0 : return (retval);
9097 0 : }
9098 :
9099 : /*
9100 : * Wait ~100us for the serial eeprom to satisfy our request.
9101 : */
9102 : int
9103 0 : ahd_wait_seeprom(struct ahd_softc *ahd)
9104 : {
9105 : int cnt;
9106 :
9107 : cnt = 5000;
9108 0 : while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9109 0 : aic_delay(5);
9110 :
9111 0 : if (cnt == 0)
9112 0 : return (ETIMEDOUT);
9113 0 : return (0);
9114 0 : }
9115 :
9116 : /*
9117 : * Validate the two checksums in the per_channel
9118 : * vital product data struct.
9119 : */
9120 : int
9121 0 : ahd_verify_vpd_cksum(struct vpd_config *vpd)
9122 : {
9123 : int i;
9124 : int maxaddr;
9125 : uint32_t checksum;
9126 : uint8_t *vpdarray;
9127 :
9128 0 : vpdarray = (uint8_t *)vpd;
9129 : maxaddr = offsetof(struct vpd_config, vpd_checksum);
9130 : checksum = 0;
9131 0 : for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9132 0 : checksum = checksum + vpdarray[i];
9133 0 : if (checksum == 0
9134 0 : || (-checksum & 0xFF) != vpd->vpd_checksum)
9135 0 : return (0);
9136 :
9137 : checksum = 0;
9138 : maxaddr = offsetof(struct vpd_config, checksum);
9139 0 : for (i = offsetof(struct vpd_config, default_target_flags);
9140 0 : i < maxaddr; i++)
9141 0 : checksum = checksum + vpdarray[i];
9142 0 : if (checksum == 0
9143 0 : || (-checksum & 0xFF) != vpd->checksum)
9144 0 : return (0);
9145 0 : return (1);
9146 0 : }
9147 :
9148 : int
9149 0 : ahd_verify_cksum(struct seeprom_config *sc)
9150 : {
9151 : int i;
9152 : int maxaddr;
9153 : uint32_t checksum;
9154 : uint16_t *scarray;
9155 :
9156 : maxaddr = (sizeof(*sc)/2) - 1;
9157 : checksum = 0;
9158 0 : scarray = (uint16_t *)sc;
9159 :
9160 0 : for (i = 0; i < maxaddr; i++)
9161 0 : checksum = checksum + scarray[i];
9162 0 : if (checksum == 0
9163 0 : || (checksum & 0xFFFF) != sc->checksum) {
9164 0 : return (0);
9165 : } else {
9166 0 : return (1);
9167 : }
9168 0 : }
9169 :
9170 : int
9171 0 : ahd_acquire_seeprom(struct ahd_softc *ahd)
9172 : {
9173 : /*
9174 : * We should be able to determine the SEEPROM type
9175 : * from the flexport logic, but unfortunately not
9176 : * all implementations have this logic and there is
9177 : * no programatic method for determining if the logic
9178 : * is present.
9179 : */
9180 0 : return (1);
9181 : #if 0
9182 : uint8_t seetype;
9183 : int error;
9184 :
9185 : error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9186 : if (error != 0
9187 : || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9188 : return (0);
9189 : return (1);
9190 : #endif
9191 : }
9192 :
9193 : void
9194 0 : ahd_release_seeprom(struct ahd_softc *ahd)
9195 : {
9196 : /* Currently a no-op */
9197 0 : }
9198 :
9199 : int
9200 0 : ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
9201 : {
9202 : int error;
9203 :
9204 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9205 0 : if (addr > 7)
9206 0 : panic("ahd_write_flexport: address out of range");
9207 0 : ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9208 0 : error = ahd_wait_flexport(ahd);
9209 0 : if (error != 0)
9210 0 : return (error);
9211 0 : ahd_outb(ahd, BRDDAT, value);
9212 0 : ahd_flush_device_writes(ahd);
9213 0 : ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
9214 0 : ahd_flush_device_writes(ahd);
9215 0 : ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9216 0 : ahd_flush_device_writes(ahd);
9217 0 : ahd_outb(ahd, BRDCTL, 0);
9218 0 : ahd_flush_device_writes(ahd);
9219 0 : return (0);
9220 0 : }
9221 :
9222 : int
9223 0 : ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
9224 : {
9225 : int error;
9226 :
9227 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9228 0 : if (addr > 7)
9229 0 : panic("ahd_read_flexport: address out of range");
9230 0 : ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
9231 0 : error = ahd_wait_flexport(ahd);
9232 0 : if (error != 0)
9233 0 : return (error);
9234 0 : *value = ahd_inb(ahd, BRDDAT);
9235 0 : ahd_outb(ahd, BRDCTL, 0);
9236 0 : ahd_flush_device_writes(ahd);
9237 0 : return (0);
9238 0 : }
9239 :
9240 : /*
9241 : * Wait at most 2 seconds for flexport arbitration to succeed.
9242 : */
9243 : int
9244 0 : ahd_wait_flexport(struct ahd_softc *ahd)
9245 : {
9246 : int cnt;
9247 :
9248 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9249 : cnt = 1000000 * 2 / 5;
9250 0 : while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9251 0 : aic_delay(5);
9252 :
9253 0 : if (cnt == 0)
9254 0 : return (ETIMEDOUT);
9255 0 : return (0);
9256 0 : }
9257 :
9258 : /************************* Target Mode ****************************************/
9259 : #ifdef AHD_TARGET_MODE
9260 : cam_status
9261 : ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
9262 : struct ahd_tmode_tstate **tstate,
9263 : struct ahd_tmode_lstate **lstate,
9264 : int notfound_failure)
9265 : {
9266 :
9267 : if ((ahd->features & AHD_TARGETMODE) == 0)
9268 : return (CAM_REQ_INVALID);
9269 :
9270 : /*
9271 : * Handle the 'black hole' device that sucks up
9272 : * requests to unattached luns on enabled targets.
9273 : */
9274 : if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
9275 : && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
9276 : *tstate = NULL;
9277 : *lstate = ahd->black_hole;
9278 : } else {
9279 : u_int max_id;
9280 :
9281 : max_id = (ahd->features & AHD_WIDE) ? 15 : 7;
9282 : if (ccb->ccb_h.target_id > max_id)
9283 : return (CAM_TID_INVALID);
9284 :
9285 : if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
9286 : return (CAM_LUN_INVALID);
9287 :
9288 : *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
9289 : *lstate = NULL;
9290 : if (*tstate != NULL)
9291 : *lstate =
9292 : (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
9293 : }
9294 :
9295 : if (notfound_failure != 0 && *lstate == NULL)
9296 : return (CAM_PATH_INVALID);
9297 :
9298 : return (CAM_REQ_CMP);
9299 : }
9300 :
9301 : void
9302 : ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
9303 : {
9304 : #if NOT_YET
9305 : struct ahd_tmode_tstate *tstate;
9306 : struct ahd_tmode_lstate *lstate;
9307 : struct ccb_en_lun *cel;
9308 : cam_status status;
9309 : u_int target;
9310 : u_int lun;
9311 : u_int target_mask;
9312 : int s;
9313 : char channel;
9314 :
9315 : status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
9316 : /*notfound_failure*/FALSE);
9317 :
9318 : if (status != CAM_REQ_CMP) {
9319 : ccb->ccb_h.status = status;
9320 : return;
9321 : }
9322 :
9323 : if ((ahd->features & AHD_MULTIROLE) != 0) {
9324 : u_int our_id;
9325 :
9326 : our_id = ahd->our_id;
9327 : if (ccb->ccb_h.target_id != our_id) {
9328 : if ((ahd->features & AHD_MULTI_TID) != 0
9329 : && (ahd->flags & AHD_INITIATORROLE) != 0) {
9330 : /*
9331 : * Only allow additional targets if
9332 : * the initiator role is disabled.
9333 : * The hardware cannot handle a re-select-in
9334 : * on the initiator id during a re-select-out
9335 : * on a different target id.
9336 : */
9337 : status = CAM_TID_INVALID;
9338 : } else if ((ahd->flags & AHD_INITIATORROLE) != 0
9339 : || ahd->enabled_luns > 0) {
9340 : /*
9341 : * Only allow our target id to change
9342 : * if the initiator role is not configured
9343 : * and there are no enabled luns which
9344 : * are attached to the currently registered
9345 : * scsi id.
9346 : */
9347 : status = CAM_TID_INVALID;
9348 : }
9349 : }
9350 : }
9351 :
9352 : if (status != CAM_REQ_CMP) {
9353 : ccb->ccb_h.status = status;
9354 : return;
9355 : }
9356 :
9357 : /*
9358 : * We now have an id that is valid.
9359 : * If we aren't in target mode, switch modes.
9360 : */
9361 : if ((ahd->flags & AHD_TARGETROLE) == 0
9362 : && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9363 : int s;
9364 :
9365 : printf("Configuring Target Mode\n");
9366 : ahd_lock(ahd, &s);
9367 : if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9368 : ccb->ccb_h.status = CAM_BUSY;
9369 : ahd_unlock(ahd, &s);
9370 : return;
9371 : }
9372 : ahd->flags |= AHD_TARGETROLE;
9373 : if ((ahd->features & AHD_MULTIROLE) == 0)
9374 : ahd->flags &= ~AHD_INITIATORROLE;
9375 : ahd_pause(ahd);
9376 : ahd_loadseq(ahd);
9377 : ahd_restart(ahd);
9378 : ahd_unlock(ahd, &s);
9379 : }
9380 : cel = &ccb->cel;
9381 : target = ccb->ccb_h.target_id;
9382 : lun = ccb->ccb_h.target_lun;
9383 : channel = SCSI_CHANNEL(ahd, sim);
9384 : target_mask = 0x01 << target;
9385 : if (channel == 'B')
9386 : target_mask <<= 8;
9387 :
9388 : if (cel->enable != 0) {
9389 : u_int scsiseq1;
9390 :
9391 : /* Are we already enabled?? */
9392 : if (lstate != NULL) {
9393 : xpt_print_path(ccb->ccb_h.path);
9394 : printf("Lun already enabled\n");
9395 : ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9396 : return;
9397 : }
9398 :
9399 : if (cel->grp6_len != 0
9400 : || cel->grp7_len != 0) {
9401 : /*
9402 : * Don't (yet?) support vendor
9403 : * specific commands.
9404 : */
9405 : ccb->ccb_h.status = CAM_REQ_INVALID;
9406 : printf("Non-zero Group Codes\n");
9407 : return;
9408 : }
9409 :
9410 : /*
9411 : * Seems to be okay.
9412 : * Setup our data structures.
9413 : */
9414 : if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
9415 : tstate = ahd_alloc_tstate(ahd, target, channel);
9416 : if (tstate == NULL) {
9417 : xpt_print_path(ccb->ccb_h.path);
9418 : printf("Couldn't allocate tstate\n");
9419 : ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9420 : return;
9421 : }
9422 : }
9423 : lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT | M_ZERO);
9424 : if (lstate == NULL) {
9425 : xpt_print_path(ccb->ccb_h.path);
9426 : printf("Couldn't allocate lstate\n");
9427 : ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9428 : return;
9429 : }
9430 : status = xpt_create_path(&lstate->path, /*periph*/NULL,
9431 : xpt_path_path_id(ccb->ccb_h.path),
9432 : xpt_path_target_id(ccb->ccb_h.path),
9433 : xpt_path_lun_id(ccb->ccb_h.path));
9434 : if (status != CAM_REQ_CMP) {
9435 : free(lstate, M_DEVBUF, 0);
9436 : xpt_print_path(ccb->ccb_h.path);
9437 : printf("Couldn't allocate path\n");
9438 : ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9439 : return;
9440 : }
9441 : SLIST_INIT(&lstate->accept_tios);
9442 : SLIST_INIT(&lstate->immed_notifies);
9443 : ahd_lock(ahd, &s);
9444 : ahd_pause(ahd);
9445 : if (target != CAM_TARGET_WILDCARD) {
9446 : tstate->enabled_luns[lun] = lstate;
9447 : ahd->enabled_luns++;
9448 :
9449 : if ((ahd->features & AHD_MULTI_TID) != 0) {
9450 : u_int targid_mask;
9451 :
9452 : targid_mask = ahd_inw(ahd, TARGID);
9453 : targid_mask |= target_mask;
9454 : ahd_outw(ahd, TARGID, targid_mask);
9455 : ahd_update_scsiid(ahd, targid_mask);
9456 : } else {
9457 : u_int our_id;
9458 : char channel;
9459 :
9460 : channel = SCSI_CHANNEL(ahd, sim);
9461 : our_id = SCSI_SCSI_ID(ahd, sim);
9462 :
9463 : /*
9464 : * This can only happen if selections
9465 : * are not enabled
9466 : */
9467 : if (target != our_id) {
9468 : u_int sblkctl;
9469 : char cur_channel;
9470 : int swap;
9471 :
9472 : sblkctl = ahd_inb(ahd, SBLKCTL);
9473 : cur_channel = (sblkctl & SELBUSB)
9474 : ? 'B' : 'A';
9475 : if ((ahd->features & AHD_TWIN) == 0)
9476 : cur_channel = 'A';
9477 : swap = cur_channel != channel;
9478 : ahd->our_id = target;
9479 :
9480 : if (swap)
9481 : ahd_outb(ahd, SBLKCTL,
9482 : sblkctl ^ SELBUSB);
9483 :
9484 : ahd_outb(ahd, SCSIID, target);
9485 :
9486 : if (swap)
9487 : ahd_outb(ahd, SBLKCTL, sblkctl);
9488 : }
9489 : }
9490 : } else
9491 : ahd->black_hole = lstate;
9492 : /* Allow select-in operations */
9493 : if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
9494 : scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
9495 : scsiseq1 |= ENSELI;
9496 : ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
9497 : scsiseq1 = ahd_inb(ahd, SCSISEQ1);
9498 : scsiseq1 |= ENSELI;
9499 : ahd_outb(ahd, SCSISEQ1, scsiseq1);
9500 : }
9501 : ahd_unpause(ahd);
9502 : ahd_unlock(ahd, &s);
9503 : ccb->ccb_h.status = CAM_REQ_CMP;
9504 : xpt_print_path(ccb->ccb_h.path);
9505 : printf("Lun now enabled for target mode\n");
9506 : } else {
9507 : struct scb *scb;
9508 : int i, empty;
9509 :
9510 : if (lstate == NULL) {
9511 : ccb->ccb_h.status = CAM_LUN_INVALID;
9512 : return;
9513 : }
9514 :
9515 : ahd_lock(ahd, &s);
9516 :
9517 : ccb->ccb_h.status = CAM_REQ_CMP;
9518 : TAILQ_FOREACH(scb, &ahd->pending_scbs, next) {
9519 : struct ccb_hdr *ccbh;
9520 :
9521 : ccbh = &scb->io_ctx->ccb_h;
9522 : if (ccbh->func_code == XPT_CONT_TARGET_IO
9523 : && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
9524 : printf("CTIO pending\n");
9525 : ccb->ccb_h.status = CAM_REQ_INVALID;
9526 : ahd_unlock(ahd, &s);
9527 : return;
9528 : }
9529 : }
9530 :
9531 : if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
9532 : printf("ATIOs pending\n");
9533 : ccb->ccb_h.status = CAM_REQ_INVALID;
9534 : }
9535 :
9536 : if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
9537 : printf("INOTs pending\n");
9538 : ccb->ccb_h.status = CAM_REQ_INVALID;
9539 : }
9540 :
9541 : if (ccb->ccb_h.status != CAM_REQ_CMP) {
9542 : ahd_unlock(ahd, &s);
9543 : return;
9544 : }
9545 :
9546 : xpt_print_path(ccb->ccb_h.path);
9547 : printf("Target mode disabled\n");
9548 : xpt_free_path(lstate->path);
9549 : free(lstate, M_DEVBUF, 0);
9550 :
9551 : ahd_pause(ahd);
9552 : /* Can we clean up the target too? */
9553 : if (target != CAM_TARGET_WILDCARD) {
9554 : tstate->enabled_luns[lun] = NULL;
9555 : ahd->enabled_luns--;
9556 : for (empty = 1, i = 0; i < 8; i++)
9557 : if (tstate->enabled_luns[i] != NULL) {
9558 : empty = 0;
9559 : break;
9560 : }
9561 :
9562 : if (empty) {
9563 : ahd_free_tstate(ahd, target, channel,
9564 : /*force*/FALSE);
9565 : if (ahd->features & AHD_MULTI_TID) {
9566 : u_int targid_mask;
9567 :
9568 : targid_mask = ahd_inw(ahd, TARGID);
9569 : targid_mask &= ~target_mask;
9570 : ahd_outw(ahd, TARGID, targid_mask);
9571 : ahd_update_scsiid(ahd, targid_mask);
9572 : }
9573 : }
9574 : } else {
9575 :
9576 : ahd->black_hole = NULL;
9577 :
9578 : /*
9579 : * We can't allow selections without
9580 : * our black hole device.
9581 : */
9582 : empty = TRUE;
9583 : }
9584 : if (ahd->enabled_luns == 0) {
9585 : /* Disallow select-in */
9586 : u_int scsiseq1;
9587 :
9588 : scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
9589 : scsiseq1 &= ~ENSELI;
9590 : ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
9591 : scsiseq1 = ahd_inb(ahd, SCSISEQ1);
9592 : scsiseq1 &= ~ENSELI;
9593 : ahd_outb(ahd, SCSISEQ1, scsiseq1);
9594 :
9595 : if ((ahd->features & AHD_MULTIROLE) == 0) {
9596 : printf("Configuring Initiator Mode\n");
9597 : ahd->flags &= ~AHD_TARGETROLE;
9598 : ahd->flags |= AHD_INITIATORROLE;
9599 : ahd_pause(ahd);
9600 : ahd_loadseq(ahd);
9601 : ahd_restart(ahd);
9602 : /*
9603 : * Unpaused. The extra unpause
9604 : * that follows is harmless.
9605 : */
9606 : }
9607 : }
9608 : ahd_unpause(ahd);
9609 : ahd_unlock(ahd, &s);
9610 : }
9611 : #endif
9612 : }
9613 :
9614 : void
9615 : ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
9616 : {
9617 : #if NOT_YET
9618 : u_int scsiid_mask;
9619 : u_int scsiid;
9620 :
9621 : if ((ahd->features & AHD_MULTI_TID) == 0)
9622 : panic("ahd_update_scsiid called on non-multitid unit");
9623 :
9624 : /*
9625 : * Since we will rely on the TARGID mask
9626 : * for selection enables, ensure that OID
9627 : * in SCSIID is not set to some other ID
9628 : * that we don't want to allow selections on.
9629 : */
9630 : if ((ahd->features & AHD_ULTRA2) != 0)
9631 : scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
9632 : else
9633 : scsiid = ahd_inb(ahd, SCSIID);
9634 : scsiid_mask = 0x1 << (scsiid & OID);
9635 : if ((targid_mask & scsiid_mask) == 0) {
9636 : u_int our_id;
9637 :
9638 : /* ffs counts from 1 */
9639 : our_id = ffs(targid_mask);
9640 : if (our_id == 0)
9641 : our_id = ahd->our_id;
9642 : else
9643 : our_id--;
9644 : scsiid &= TID;
9645 : scsiid |= our_id;
9646 : }
9647 : if ((ahd->features & AHD_ULTRA2) != 0)
9648 : ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
9649 : else
9650 : ahd_outb(ahd, SCSIID, scsiid);
9651 : #endif
9652 : }
9653 :
9654 : void
9655 : ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
9656 : {
9657 : struct target_cmd *cmd;
9658 :
9659 : ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
9660 : while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
9661 :
9662 : /*
9663 : * Only advance through the queue if we
9664 : * have the resources to process the command.
9665 : */
9666 : if (ahd_handle_target_cmd(ahd, cmd) != 0)
9667 : break;
9668 :
9669 : cmd->cmd_valid = 0;
9670 : ahd_dmamap_sync(ahd, ahd->parent_dmat /*shared_data_dmat*/,
9671 : ahd->shared_data_dmamap,
9672 : ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
9673 : sizeof(struct target_cmd),
9674 : BUS_DMASYNC_PREREAD);
9675 : ahd->tqinfifonext++;
9676 :
9677 : /*
9678 : * Lazily update our position in the target mode incoming
9679 : * command queue as seen by the sequencer.
9680 : */
9681 : if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
9682 : u_int hs_mailbox;
9683 :
9684 : hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
9685 : hs_mailbox &= ~HOST_TQINPOS;
9686 : hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
9687 : ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
9688 : }
9689 : }
9690 : }
9691 :
9692 : int
9693 : ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
9694 : {
9695 : struct ahd_tmode_tstate *tstate;
9696 : struct ahd_tmode_lstate *lstate;
9697 : struct ccb_accept_tio *atio;
9698 : uint8_t *byte;
9699 : int initiator;
9700 : int target;
9701 : int lun;
9702 :
9703 : initiator = SCSIID_TARGET(ahd, cmd->scsiid);
9704 : target = SCSIID_OUR_ID(cmd->scsiid);
9705 : lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
9706 :
9707 : byte = cmd->bytes;
9708 : tstate = ahd->enabled_targets[target];
9709 : lstate = NULL;
9710 : if (tstate != NULL)
9711 : lstate = tstate->enabled_luns[lun];
9712 :
9713 : /*
9714 : * Commands for disabled luns go to the black hole driver.
9715 : */
9716 : if (lstate == NULL)
9717 : lstate = ahd->black_hole;
9718 :
9719 : atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
9720 : if (atio == NULL) {
9721 : ahd->flags |= AHD_TQINFIFO_BLOCKED;
9722 : /*
9723 : * Wait for more ATIOs from the peripheral driver for this lun.
9724 : */
9725 : return (1);
9726 : } else
9727 : ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
9728 : #ifdef AHD_DEBUG
9729 : if ((ahd_debug & AHD_SHOW_TQIN) != 0)
9730 : printf("Incoming command from %d for %d:%d%s\n",
9731 : initiator, target, lun,
9732 : lstate == ahd->black_hole ? "(Black Holed)" : "");
9733 : #endif
9734 : SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
9735 :
9736 : if (lstate == ahd->black_hole) {
9737 : /* Fill in the wildcards */
9738 : atio->ccb_h.target_id = target;
9739 : atio->ccb_h.target_lun = lun;
9740 : }
9741 :
9742 : /*
9743 : * Package it up and send it off to
9744 : * whomever has this lun enabled.
9745 : */
9746 : atio->sense_len = 0;
9747 : atio->init_id = initiator;
9748 : if (byte[0] != 0xFF) {
9749 : /* Tag was included */
9750 : atio->tag_action = *byte++;
9751 : atio->tag_id = *byte++;
9752 : atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
9753 : } else {
9754 : atio->ccb_h.flags = 0;
9755 : }
9756 : byte++;
9757 :
9758 : /* Okay. Now determine the cdb size based on the command code */
9759 : switch (*byte >> CMD_GROUP_CODE_SHIFT) {
9760 : case 0:
9761 : atio->cdb_len = 6;
9762 : break;
9763 : case 1:
9764 : case 2:
9765 : atio->cdb_len = 10;
9766 : break;
9767 : case 4:
9768 : atio->cdb_len = 16;
9769 : break;
9770 : case 5:
9771 : atio->cdb_len = 12;
9772 : break;
9773 : case 3:
9774 : default:
9775 : /* Only copy the opcode. */
9776 : atio->cdb_len = 1;
9777 : printf("Reserved or VU command code type encountered\n");
9778 : break;
9779 : }
9780 :
9781 : memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
9782 :
9783 : atio->ccb_h.status |= CAM_CDB_RECVD;
9784 :
9785 : if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
9786 : /*
9787 : * We weren't allowed to disconnect.
9788 : * We're hanging on the bus until a
9789 : * continue target I/O comes in response
9790 : * to this accept tio.
9791 : */
9792 : #ifdef AHD_DEBUG
9793 : if ((ahd_debug & AHD_SHOW_TQIN) != 0)
9794 : printf("Received Immediate Command %d:%d:%d - %p\n",
9795 : initiator, target, lun, ahd->pending_device);
9796 : #endif
9797 : ahd->pending_device = lstate;
9798 : ahd_freeze_ccb((union ccb *)atio);
9799 : atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
9800 : }
9801 : xpt_done((union ccb*)atio);
9802 : return (0);
9803 : }
9804 :
9805 : #endif
9806 :
9807 : int
9808 0 : ahd_createdmamem(struct ahd_softc *ahd, size_t size, struct map_node *map,
9809 : const char *what)
9810 : {
9811 0 : bus_dma_tag_t tag = ahd->parent_dmat;
9812 0 : int nseg, error;
9813 :
9814 0 : bzero(map, sizeof(*map));
9815 :
9816 0 : if ((error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT,
9817 0 : &map->dmamap)) != 0) {
9818 0 : printf("%s: failed to create DMA map for %s, error = %d\n",
9819 0 : ahd_name(ahd), what, error);
9820 0 : return (error);
9821 : }
9822 :
9823 0 : if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0, &map->dmaseg,
9824 0 : 1, &nseg, BUS_DMA_NOWAIT)) != 0) {
9825 0 : printf("%s: failed to allocate DMA mem for %s, error = %d\n",
9826 0 : ahd_name(ahd), what, error);
9827 0 : goto destroy;
9828 : }
9829 :
9830 0 : if ((error = bus_dmamem_map(tag, &map->dmaseg, nseg, size,
9831 0 : (caddr_t *)&map->vaddr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
9832 0 : printf("%s: failed to map DMA mem for %s, error = %d\n",
9833 0 : ahd_name(ahd), what, error);
9834 0 : goto free;
9835 : }
9836 :
9837 0 : if ((error = bus_dmamap_load(tag, map->dmamap, map->vaddr, size, NULL,
9838 0 : BUS_DMA_NOWAIT)) != 0) {
9839 0 : printf("%s: failed to load DMA map for %s, error = %d\n",
9840 0 : ahd_name(ahd), what, error);
9841 : goto unmap;
9842 : }
9843 :
9844 0 : map->size = size;
9845 0 : map->busaddr = map->dmamap->dm_segs[0].ds_addr;
9846 0 : return (0);
9847 :
9848 : unmap:
9849 0 : bus_dmamem_unmap(tag, map->vaddr, size);
9850 : free:
9851 0 : bus_dmamem_free(tag, &map->dmaseg, 1);
9852 : destroy:
9853 0 : bus_dmamap_destroy(tag, map->dmamap);
9854 :
9855 0 : bzero(map, sizeof(*map));
9856 0 : return (error);
9857 0 : }
9858 :
9859 : void
9860 0 : ahd_freedmamem(struct ahd_softc* ahd, struct map_node *map)
9861 : {
9862 0 : bus_dma_tag_t tag = ahd->parent_dmat;
9863 :
9864 0 : bus_dmamap_unload(tag, map->dmamap);
9865 0 : bus_dmamem_unmap(tag, map->vaddr, map->size);
9866 0 : bus_dmamem_free(tag, &map->dmaseg, 1);
9867 0 : bus_dmamap_destroy(tag, map->dmamap);
9868 0 : }
9869 :
9870 : char *
9871 0 : ahd_name(struct ahd_softc *ahd)
9872 : {
9873 0 : return (ahd->name);
9874 : }
9875 :
9876 : void
9877 0 : ahd_known_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
9878 : {
9879 0 : ahd->src_mode = src;
9880 0 : ahd->dst_mode = dst;
9881 0 : ahd->saved_src_mode = src;
9882 0 : ahd->saved_dst_mode = dst;
9883 0 : }
9884 :
9885 : ahd_mode_state
9886 0 : ahd_build_mode_state(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
9887 : {
9888 0 : return ((src << SRC_MODE_SHIFT) | (dst << DST_MODE_SHIFT));
9889 : }
9890 :
9891 : void
9892 0 : ahd_extract_mode_state(struct ahd_softc *ahd, ahd_mode_state state,
9893 : ahd_mode *src, ahd_mode *dst)
9894 : {
9895 0 : *src = (state & SRC_MODE) >> SRC_MODE_SHIFT;
9896 0 : *dst = (state & DST_MODE) >> DST_MODE_SHIFT;
9897 0 : }
9898 :
9899 : void
9900 0 : ahd_set_modes(struct ahd_softc *ahd, ahd_mode src, ahd_mode dst)
9901 : {
9902 0 : if (ahd->src_mode == src && ahd->dst_mode == dst)
9903 : return;
9904 : #ifdef AHD_DEBUG
9905 : if (ahd->src_mode == AHD_MODE_UNKNOWN
9906 : || ahd->dst_mode == AHD_MODE_UNKNOWN)
9907 : panic("Setting mode prior to saving it.");
9908 : if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
9909 : printf("%s: Setting mode 0x%x\n", ahd_name(ahd),
9910 : ahd_build_mode_state(ahd, src, dst));
9911 : #endif
9912 0 : ahd_outb(ahd, MODE_PTR, ahd_build_mode_state(ahd, src, dst));
9913 0 : ahd->src_mode = src;
9914 0 : ahd->dst_mode = dst;
9915 0 : }
9916 :
9917 : void
9918 0 : ahd_update_modes(struct ahd_softc *ahd)
9919 : {
9920 : ahd_mode_state mode_ptr;
9921 0 : ahd_mode src;
9922 0 : ahd_mode dst;
9923 :
9924 0 : mode_ptr = ahd_inb(ahd, MODE_PTR);
9925 : #ifdef AHD_DEBUG
9926 : if ((ahd_debug & AHD_SHOW_MODEPTR) != 0)
9927 : printf("Reading mode 0x%x\n", mode_ptr);
9928 : #endif
9929 0 : ahd_extract_mode_state(ahd, mode_ptr, &src, &dst);
9930 0 : ahd_known_modes(ahd, src, dst);
9931 0 : }
9932 :
9933 : void
9934 0 : ahd_assert_modes(struct ahd_softc *ahd, ahd_mode srcmode,
9935 : ahd_mode dstmode, const char *file, int line)
9936 : {
9937 : #ifdef AHD_DEBUG
9938 : if ((srcmode & AHD_MK_MSK(ahd->src_mode)) == 0
9939 : || (dstmode & AHD_MK_MSK(ahd->dst_mode)) == 0) {
9940 : panic("%s:%s:%d: Mode assertion failed.",
9941 : ahd_name(ahd), file, line);
9942 : }
9943 : #endif
9944 0 : }
9945 :
9946 : ahd_mode_state
9947 0 : ahd_save_modes(struct ahd_softc *ahd)
9948 : {
9949 0 : if (ahd->src_mode == AHD_MODE_UNKNOWN
9950 0 : || ahd->dst_mode == AHD_MODE_UNKNOWN)
9951 0 : ahd_update_modes(ahd);
9952 :
9953 0 : return (ahd_build_mode_state(ahd, ahd->src_mode, ahd->dst_mode));
9954 : }
9955 :
9956 : void
9957 0 : ahd_restore_modes(struct ahd_softc *ahd, ahd_mode_state state)
9958 : {
9959 0 : ahd_mode src;
9960 0 : ahd_mode dst;
9961 :
9962 0 : ahd_extract_mode_state(ahd, state, &src, &dst);
9963 0 : ahd_set_modes(ahd, src, dst);
9964 0 : }
9965 :
9966 : /*
9967 : * Determine whether the sequencer has halted code execution.
9968 : * Returns non-zero status if the sequencer is stopped.
9969 : */
9970 : int
9971 0 : ahd_is_paused(struct ahd_softc *ahd)
9972 : {
9973 0 : return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0);
9974 : }
9975 :
9976 : /*
9977 : * Request that the sequencer stop and wait, indefinitely, for it
9978 : * to stop. The sequencer will only acknowledge that it is paused
9979 : * once it has reached an instruction boundary and PAUSEDIS is
9980 : * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
9981 : * for critical sections.
9982 : */
9983 : void
9984 0 : ahd_pause(struct ahd_softc *ahd)
9985 : {
9986 0 : ahd_outb(ahd, HCNTRL, ahd->pause);
9987 :
9988 : /*
9989 : * Since the sequencer can disable pausing in a critical section, we
9990 : * must loop until it actually stops.
9991 : */
9992 0 : while (ahd_is_paused(ahd) == 0)
9993 : ;
9994 0 : }
9995 :
9996 : /*
9997 : * Allow the sequencer to continue program execution.
9998 : * We check here to ensure that no additional interrupt
9999 : * sources that would cause the sequencer to halt have been
10000 : * asserted. If, for example, a SCSI bus reset is detected
10001 : * while we are fielding a different, pausing, interrupt type,
10002 : * we don't want to release the sequencer before going back
10003 : * into our interrupt handler and dealing with this new
10004 : * condition.
10005 : */
10006 : void
10007 0 : ahd_unpause(struct ahd_softc *ahd)
10008 : {
10009 : /*
10010 : * Automatically restore our modes to those saved
10011 : * prior to the first change of the mode.
10012 : */
10013 0 : if (ahd->saved_src_mode != AHD_MODE_UNKNOWN
10014 0 : && ahd->saved_dst_mode != AHD_MODE_UNKNOWN) {
10015 0 : if ((ahd->flags & AHD_UPDATE_PEND_CMDS) != 0)
10016 0 : ahd_reset_cmds_pending(ahd);
10017 0 : ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
10018 0 : }
10019 :
10020 0 : if ((ahd_inb(ahd, INTSTAT) & ~CMDCMPLT) == 0)
10021 0 : ahd_outb(ahd, HCNTRL, ahd->unpause);
10022 :
10023 0 : ahd_known_modes(ahd, AHD_MODE_UNKNOWN, AHD_MODE_UNKNOWN);
10024 0 : }
10025 :
10026 : void *
10027 0 : ahd_sg_setup(struct ahd_softc *ahd, struct scb *scb,
10028 : void *sgptr, bus_addr_t addr, bus_size_t len, int last)
10029 : {
10030 0 : scb->sg_count++;
10031 0 : if (sizeof(bus_addr_t) > 4
10032 0 : && (ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
10033 : struct ahd_dma64_seg *sg;
10034 :
10035 0 : sg = (struct ahd_dma64_seg *)sgptr;
10036 0 : sg->addr = aic_htole64(addr);
10037 0 : sg->len = aic_htole32(len | (last ? AHD_DMA_LAST_SEG : 0));
10038 0 : return (sg + 1);
10039 : } else {
10040 : struct ahd_dma_seg *sg;
10041 :
10042 0 : sg = (struct ahd_dma_seg *)sgptr;
10043 0 : sg->addr = aic_htole32(addr & 0xFFFFFFFF);
10044 0 : sg->len = aic_htole32(len | ((addr >> 8) & 0x7F000000)
10045 : | (last ? AHD_DMA_LAST_SEG : 0));
10046 0 : return (sg + 1);
10047 : }
10048 0 : }
10049 :
10050 : void
10051 0 : ahd_setup_scb_common(struct ahd_softc *ahd, struct scb *scb)
10052 : {
10053 : /* XXX Handle target mode SCBs. */
10054 0 : scb->crc_retry_count = 0;
10055 0 : if ((scb->flags & SCB_PACKETIZED) != 0) {
10056 : /* XXX what about ACA?? It is type 4, but TAG_TYPE == 0x3. */
10057 0 : scb->hscb->task_attribute = scb->hscb->control & SCB_TAG_TYPE;
10058 0 : } else {
10059 0 : if (aic_get_transfer_length(scb) & 0x01)
10060 0 : scb->hscb->task_attribute = SCB_XFERLEN_ODD;
10061 : else
10062 0 : scb->hscb->task_attribute = 0;
10063 : }
10064 :
10065 0 : if (scb->hscb->cdb_len <= MAX_CDB_LEN_WITH_SENSE_ADDR
10066 0 : || (scb->hscb->cdb_len & SCB_CDB_LEN_PTR) != 0)
10067 0 : scb->hscb->shared_data.idata.cdb_plus_saddr.sense_addr =
10068 0 : aic_htole32(scb->sense_busaddr);
10069 0 : }
10070 :
10071 : void
10072 0 : ahd_setup_data_scb(struct ahd_softc *ahd, struct scb *scb)
10073 : {
10074 : /*
10075 : * Copy the first SG into the "current" data pointer area.
10076 : */
10077 0 : if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
10078 : struct ahd_dma64_seg *sg;
10079 :
10080 0 : sg = (struct ahd_dma64_seg *)scb->sg_list;
10081 0 : scb->hscb->dataptr = sg->addr;
10082 0 : scb->hscb->datacnt = sg->len;
10083 0 : } else {
10084 : struct ahd_dma_seg *sg;
10085 : uint32_t *dataptr_words;
10086 :
10087 0 : sg = (struct ahd_dma_seg *)scb->sg_list;
10088 0 : dataptr_words = (uint32_t*)&scb->hscb->dataptr;
10089 0 : dataptr_words[0] = sg->addr;
10090 0 : dataptr_words[1] = 0;
10091 0 : if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
10092 : uint64_t high_addr;
10093 :
10094 0 : high_addr = aic_le32toh(sg->len) & 0x7F000000;
10095 0 : scb->hscb->dataptr |= aic_htole64(high_addr << 8);
10096 0 : }
10097 0 : scb->hscb->datacnt = sg->len;
10098 : }
10099 : /*
10100 : * Note where to find the SG entries in bus space.
10101 : * We also set the full residual flag which the
10102 : * sequencer will clear as soon as a data transfer
10103 : * occurs.
10104 : */
10105 0 : scb->hscb->sgptr = aic_htole32(scb->sg_list_busaddr|SG_FULL_RESID);
10106 0 : }
10107 :
10108 : void
10109 0 : ahd_setup_noxfer_scb(struct ahd_softc *ahd, struct scb *scb)
10110 : {
10111 0 : scb->hscb->sgptr = aic_htole32(SG_LIST_NULL);
10112 0 : scb->hscb->dataptr = 0;
10113 0 : scb->hscb->datacnt = 0;
10114 0 : }
10115 :
10116 : size_t
10117 0 : ahd_sg_size(struct ahd_softc *ahd)
10118 : {
10119 0 : if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
10120 0 : return (sizeof(struct ahd_dma64_seg));
10121 0 : return (sizeof(struct ahd_dma_seg));
10122 0 : }
10123 :
10124 : void *
10125 0 : ahd_sg_bus_to_virt(struct ahd_softc *ahd, struct scb *scb, uint32_t sg_busaddr)
10126 : {
10127 : bus_addr_t sg_offset;
10128 :
10129 : /* sg_list_phys points to entry 1, not 0 */
10130 0 : sg_offset = sg_busaddr - (scb->sg_list_busaddr - ahd_sg_size(ahd));
10131 0 : return ((uint8_t *)scb->sg_list + sg_offset);
10132 : }
10133 :
10134 : uint32_t
10135 0 : ahd_sg_virt_to_bus(struct ahd_softc *ahd, struct scb *scb, void *sg)
10136 : {
10137 : bus_addr_t sg_offset;
10138 :
10139 : /* sg_list_phys points to entry 1, not 0 */
10140 0 : sg_offset = ((uint8_t *)sg - (uint8_t *)scb->sg_list)
10141 0 : - ahd_sg_size(ahd);
10142 :
10143 0 : return (scb->sg_list_busaddr + sg_offset);
10144 : }
10145 :
10146 : void
10147 0 : ahd_sync_scb(struct ahd_softc *ahd, struct scb *scb, int op)
10148 : {
10149 0 : ahd_dmamap_sync(ahd, ahd->parent_dmat, scb->hscb_map->dmamap,
10150 : /*offset*/(uint8_t*)scb->hscb - scb->hscb_map->vaddr,
10151 : /*len*/sizeof(*scb->hscb), op);
10152 0 : }
10153 :
10154 : void
10155 0 : ahd_sync_sglist(struct ahd_softc *ahd, struct scb *scb, int op)
10156 : {
10157 0 : if (scb->sg_count == 0)
10158 : return;
10159 :
10160 0 : ahd_dmamap_sync(ahd, ahd->parent_dmat,
10161 : scb->sense_map->dmamap,
10162 : /*offset*/scb->sg_list_busaddr - ahd_sg_size(ahd),
10163 : /*len*/ahd_sg_size(ahd) * scb->sg_count, op);
10164 0 : }
10165 :
10166 : void
10167 0 : ahd_sync_sense(struct ahd_softc *ahd, struct scb *scb, int op)
10168 : {
10169 0 : ahd_dmamap_sync(ahd, ahd->parent_dmat,
10170 : scb->sense_map->dmamap,
10171 : /*offset*/scb->sense_busaddr,
10172 : /*len*/AHD_SENSE_BUFSIZE, op);
10173 0 : }
10174 :
10175 : uint32_t
10176 0 : ahd_targetcmd_offset(struct ahd_softc *ahd, u_int index)
10177 : {
10178 0 : return (((uint8_t *)&ahd->targetcmds[index])
10179 0 : - (uint8_t *)ahd->qoutfifo);
10180 : }
10181 :
10182 : void
10183 0 : ahd_complete_scb(struct ahd_softc *ahd, struct scb *scb)
10184 : {
10185 : uint32_t sgptr;
10186 :
10187 0 : sgptr = aic_le32toh(scb->hscb->sgptr);
10188 0 : if ((sgptr & SG_STATUS_VALID) != 0)
10189 0 : ahd_handle_scb_status(ahd, scb);
10190 : else
10191 0 : ahd_done(ahd, scb);
10192 0 : }
10193 :
10194 : /*
10195 : * Determine whether the sequencer reported a residual
10196 : * for this SCB/transaction.
10197 : */
10198 : void
10199 0 : ahd_update_residual(struct ahd_softc *ahd, struct scb *scb)
10200 : {
10201 : uint32_t sgptr;
10202 :
10203 0 : sgptr = aic_le32toh(scb->hscb->sgptr);
10204 0 : if ((sgptr & SG_STATUS_VALID) != 0)
10205 0 : ahd_calc_residual(ahd, scb);
10206 0 : }
10207 :
10208 : /*
10209 : * Return pointers to the transfer negotiation information
10210 : * for the specified our_id/remote_id pair.
10211 : */
10212 : struct ahd_initiator_tinfo *
10213 0 : ahd_fetch_transinfo(struct ahd_softc *ahd, char channel, u_int our_id,
10214 : u_int remote_id, struct ahd_tmode_tstate **tstate)
10215 : {
10216 : /*
10217 : * Transfer data structures are stored from the perspective
10218 : * of the target role. Since the parameters for a connection
10219 : * in the initiator role to a given target are the same as
10220 : * when the roles are reversed, we pretend we are the target.
10221 : */
10222 0 : if (channel == 'B')
10223 0 : our_id += 8;
10224 0 : *tstate = ahd->enabled_targets[our_id];
10225 0 : return (&(*tstate)->transinfo[remote_id]);
10226 : }
10227 :
10228 : #define AHD_COPY_COL_IDX(dst, src) \
10229 : do { \
10230 : dst->hscb->scsiid = src->hscb->scsiid; \
10231 : dst->hscb->lun = src->hscb->lun; \
10232 : } while (0)
10233 :
10234 : uint16_t
10235 0 : ahd_inw(struct ahd_softc *ahd, u_int port)
10236 : {
10237 : /*
10238 : * Read high byte first as some registers increment
10239 : * or have other side effects when the low byte is
10240 : * read.
10241 : */
10242 0 : return ((ahd_inb(ahd, port+1) << 8) | ahd_inb(ahd, port));
10243 : }
10244 :
10245 : void
10246 0 : ahd_outw(struct ahd_softc *ahd, u_int port, u_int value)
10247 : {
10248 : /*
10249 : * Write low byte first to accommodate registers
10250 : * such as PRGMCNT where the order maters.
10251 : */
10252 0 : ahd_outb(ahd, port, value & 0xFF);
10253 0 : ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
10254 0 : }
10255 :
10256 : uint32_t
10257 0 : ahd_inl(struct ahd_softc *ahd, u_int port)
10258 : {
10259 0 : return ((ahd_inb(ahd, port))
10260 0 : | (ahd_inb(ahd, port+1) << 8)
10261 0 : | (ahd_inb(ahd, port+2) << 16)
10262 0 : | (ahd_inb(ahd, port+3) << 24));
10263 : }
10264 :
10265 : void
10266 0 : ahd_outl(struct ahd_softc *ahd, u_int port, uint32_t value)
10267 : {
10268 0 : ahd_outb(ahd, port, (value) & 0xFF);
10269 0 : ahd_outb(ahd, port+1, ((value) >> 8) & 0xFF);
10270 0 : ahd_outb(ahd, port+2, ((value) >> 16) & 0xFF);
10271 0 : ahd_outb(ahd, port+3, ((value) >> 24) & 0xFF);
10272 0 : }
10273 :
10274 : uint64_t
10275 0 : ahd_inq(struct ahd_softc *ahd, u_int port)
10276 : {
10277 0 : return ((ahd_inb(ahd, port))
10278 0 : | (ahd_inb(ahd, port+1) << 8)
10279 0 : | (ahd_inb(ahd, port+2) << 16)
10280 0 : | (ahd_inb(ahd, port+3) << 24)
10281 0 : | (((uint64_t)ahd_inb(ahd, port+4)) << 32)
10282 0 : | (((uint64_t)ahd_inb(ahd, port+5)) << 40)
10283 0 : | (((uint64_t)ahd_inb(ahd, port+6)) << 48)
10284 0 : | (((uint64_t)ahd_inb(ahd, port+7)) << 56));
10285 : }
10286 :
10287 : void
10288 0 : ahd_outq(struct ahd_softc *ahd, u_int port, uint64_t value)
10289 : {
10290 0 : ahd_outb(ahd, port, value & 0xFF);
10291 0 : ahd_outb(ahd, port+1, (value >> 8) & 0xFF);
10292 0 : ahd_outb(ahd, port+2, (value >> 16) & 0xFF);
10293 0 : ahd_outb(ahd, port+3, (value >> 24) & 0xFF);
10294 0 : ahd_outb(ahd, port+4, (value >> 32) & 0xFF);
10295 0 : ahd_outb(ahd, port+5, (value >> 40) & 0xFF);
10296 0 : ahd_outb(ahd, port+6, (value >> 48) & 0xFF);
10297 0 : ahd_outb(ahd, port+7, (value >> 56) & 0xFF);
10298 0 : }
10299 :
10300 : u_int
10301 0 : ahd_get_scbptr(struct ahd_softc *ahd)
10302 : {
10303 0 : AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
10304 : ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
10305 0 : return (ahd_inb(ahd, SCBPTR) | (ahd_inb(ahd, SCBPTR + 1) << 8));
10306 : }
10307 :
10308 : void
10309 0 : ahd_set_scbptr(struct ahd_softc *ahd, u_int scbptr)
10310 : {
10311 0 : AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
10312 : ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
10313 0 : ahd_outb(ahd, SCBPTR, scbptr & 0xFF);
10314 0 : ahd_outb(ahd, SCBPTR+1, (scbptr >> 8) & 0xFF);
10315 0 : }
10316 :
10317 : u_int
10318 0 : ahd_get_hnscb_qoff(struct ahd_softc *ahd)
10319 : {
10320 0 : return (ahd_inw_atomic(ahd, HNSCB_QOFF));
10321 : }
10322 :
10323 : void
10324 0 : ahd_set_hnscb_qoff(struct ahd_softc *ahd, u_int value)
10325 : {
10326 0 : ahd_outw_atomic(ahd, HNSCB_QOFF, value);
10327 0 : }
10328 :
10329 : u_int
10330 0 : ahd_get_hescb_qoff(struct ahd_softc *ahd)
10331 : {
10332 0 : return (ahd_inb(ahd, HESCB_QOFF));
10333 : }
10334 :
10335 : void
10336 0 : ahd_set_hescb_qoff(struct ahd_softc *ahd, u_int value)
10337 : {
10338 0 : ahd_outb(ahd, HESCB_QOFF, value);
10339 0 : }
10340 :
10341 : u_int
10342 0 : ahd_get_snscb_qoff(struct ahd_softc *ahd)
10343 : {
10344 : u_int oldvalue;
10345 :
10346 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
10347 0 : oldvalue = ahd_inw(ahd, SNSCB_QOFF);
10348 0 : ahd_outw(ahd, SNSCB_QOFF, oldvalue);
10349 0 : return (oldvalue);
10350 : }
10351 :
10352 : void
10353 0 : ahd_set_snscb_qoff(struct ahd_softc *ahd, u_int value)
10354 : {
10355 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
10356 0 : ahd_outw(ahd, SNSCB_QOFF, value);
10357 0 : }
10358 :
10359 : u_int
10360 0 : ahd_get_sescb_qoff(struct ahd_softc *ahd)
10361 : {
10362 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
10363 0 : return (ahd_inb(ahd, SESCB_QOFF));
10364 : }
10365 :
10366 : void
10367 0 : ahd_set_sescb_qoff(struct ahd_softc *ahd, u_int value)
10368 : {
10369 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
10370 0 : ahd_outb(ahd, SESCB_QOFF, value);
10371 0 : }
10372 :
10373 : u_int
10374 0 : ahd_get_sdscb_qoff(struct ahd_softc *ahd)
10375 : {
10376 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
10377 0 : return (ahd_inb(ahd, SDSCB_QOFF) | (ahd_inb(ahd, SDSCB_QOFF + 1) << 8));
10378 : }
10379 :
10380 : void
10381 0 : ahd_set_sdscb_qoff(struct ahd_softc *ahd, u_int value)
10382 : {
10383 0 : AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
10384 0 : ahd_outb(ahd, SDSCB_QOFF, value & 0xFF);
10385 0 : ahd_outb(ahd, SDSCB_QOFF+1, (value >> 8) & 0xFF);
10386 0 : }
10387 :
10388 : u_int
10389 0 : ahd_inb_scbram(struct ahd_softc *ahd, u_int offset)
10390 : {
10391 : u_int value;
10392 :
10393 : /*
10394 : * Workaround PCI-X Rev A. hardware bug.
10395 : * After a host read of SCB memory, the chip
10396 : * may become confused into thinking prefetch
10397 : * was required. This starts the discard timer
10398 : * running and can cause an unexpected discard
10399 : * timer interrupt. The work around is to read
10400 : * a normal register prior to the exhaustion of
10401 : * the discard timer. The mode pointer register
10402 : * has no side effects and so serves well for
10403 : * this purpose.
10404 : *
10405 : * Razor #528
10406 : */
10407 0 : value = ahd_inb(ahd, offset);
10408 0 : if ((ahd->bugs & AHD_PCIX_SCBRAM_RD_BUG) != 0)
10409 0 : ahd_inb(ahd, MODE_PTR);
10410 0 : return (value);
10411 : }
10412 :
10413 : u_int
10414 0 : ahd_inw_scbram(struct ahd_softc *ahd, u_int offset)
10415 : {
10416 0 : return (ahd_inb_scbram(ahd, offset)
10417 0 : | (ahd_inb_scbram(ahd, offset+1) << 8));
10418 : }
10419 :
10420 : uint32_t
10421 0 : ahd_inl_scbram(struct ahd_softc *ahd, u_int offset)
10422 : {
10423 0 : return (ahd_inw_scbram(ahd, offset)
10424 0 : | (ahd_inw_scbram(ahd, offset+2) << 16));
10425 : }
10426 :
10427 : uint64_t
10428 0 : ahd_inq_scbram(struct ahd_softc *ahd, u_int offset)
10429 : {
10430 0 : return (ahd_inl_scbram(ahd, offset)
10431 0 : | ((uint64_t)ahd_inl_scbram(ahd, offset+4)) << 32);
10432 : }
10433 :
10434 : struct scb *
10435 0 : ahd_lookup_scb(struct ahd_softc *ahd, u_int tag)
10436 : {
10437 : struct scb* scb;
10438 :
10439 0 : if (tag >= AHD_SCB_MAX)
10440 0 : return (NULL);
10441 0 : scb = ahd->scb_data.scbindex[tag];
10442 0 : if (scb != NULL)
10443 0 : ahd_sync_scb(ahd, scb,
10444 : BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
10445 0 : return (scb);
10446 0 : }
10447 :
10448 : void
10449 0 : ahd_swap_with_next_hscb(struct ahd_softc *ahd, struct scb *scb)
10450 : {
10451 : struct hardware_scb *q_hscb;
10452 : struct map_node *q_hscb_map;
10453 : uint32_t saved_hscb_busaddr;
10454 :
10455 : /*
10456 : * Our queuing method is a bit tricky. The card
10457 : * knows in advance which HSCB (by address) to download,
10458 : * and we can't disappoint it. To achieve this, the next
10459 : * HSCB to download is saved off in ahd->next_queued_hscb.
10460 : * When we are called to queue "an arbitrary scb",
10461 : * we copy the contents of the incoming HSCB to the one
10462 : * the sequencer knows about, swap HSCB pointers and
10463 : * finally assign the SCB to the tag indexed location
10464 : * in the scb_array. This makes sure that we can still
10465 : * locate the correct SCB by SCB_TAG.
10466 : */
10467 0 : q_hscb = ahd->next_queued_hscb;
10468 0 : q_hscb_map = ahd->next_queued_hscb_map;
10469 0 : saved_hscb_busaddr = q_hscb->hscb_busaddr;
10470 0 : memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
10471 0 : q_hscb->hscb_busaddr = saved_hscb_busaddr;
10472 0 : q_hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
10473 :
10474 : /* Now swap HSCB pointers. */
10475 0 : ahd->next_queued_hscb = scb->hscb;
10476 0 : ahd->next_queued_hscb_map = scb->hscb_map;
10477 0 : scb->hscb = q_hscb;
10478 0 : scb->hscb_map = q_hscb_map;
10479 :
10480 : /* Now define the mapping from tag to SCB in the scbindex */
10481 0 : ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = scb;
10482 0 : }
10483 :
10484 : /*
10485 : * Tell the sequencer about a new transaction to execute.
10486 : */
10487 : void
10488 0 : ahd_queue_scb(struct ahd_softc *ahd, struct scb *scb)
10489 : {
10490 0 : ahd_swap_with_next_hscb(ahd, scb);
10491 :
10492 0 : if (SCBID_IS_NULL(SCB_GET_TAG(scb)))
10493 0 : panic("Attempt to queue invalid SCB tag %x",
10494 : SCB_GET_TAG(scb));
10495 :
10496 : /*
10497 : * Keep a history of SCBs we've downloaded in the qinfifo.
10498 : */
10499 0 : ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
10500 0 : ahd->qinfifonext++;
10501 :
10502 0 : if (scb->sg_count != 0)
10503 0 : ahd_setup_data_scb(ahd, scb);
10504 : else
10505 0 : ahd_setup_noxfer_scb(ahd, scb);
10506 0 : ahd_setup_scb_common(ahd, scb);
10507 :
10508 : /*
10509 : * Make sure our data is consistent from the
10510 : * perspective of the adapter.
10511 : */
10512 0 : ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
10513 :
10514 : #ifdef AHD_DEBUG
10515 : if ((ahd_debug & AHD_SHOW_QUEUE) != 0) {
10516 : uint64_t host_dataptr;
10517 :
10518 : host_dataptr = aic_le64toh(scb->hscb->dataptr);
10519 : printf("%s: Queueing SCB %d:0x%x bus addr 0x%x - 0x%x%x/0x%x\n",
10520 : ahd_name(ahd),
10521 : SCB_GET_TAG(scb), scb->hscb->scsiid,
10522 : aic_le32toh(scb->hscb->hscb_busaddr),
10523 : (u_int)((host_dataptr >> 32) & 0xFFFFFFFF),
10524 : (u_int)(host_dataptr & 0xFFFFFFFF),
10525 : aic_le32toh(scb->hscb->datacnt));
10526 : }
10527 : #endif
10528 : /* Tell the adapter about the newly queued SCB */
10529 0 : ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
10530 0 : }
10531 :
10532 : uint8_t *
10533 0 : ahd_get_sense_buf(struct ahd_softc *ahd, struct scb *scb)
10534 : {
10535 0 : return (scb->sense_data);
10536 : }
10537 :
10538 : uint32_t
10539 0 : ahd_get_sense_bufaddr(struct ahd_softc *ahd, struct scb *scb)
10540 : {
10541 0 : return (scb->sense_busaddr);
10542 : }
10543 :
10544 : void
10545 0 : ahd_sync_qoutfifo(struct ahd_softc *ahd, int op)
10546 : {
10547 0 : ahd_dmamap_sync(ahd, ahd->parent_dmat, ahd->shared_data_map.dmamap,
10548 : /*offset*/0,
10549 : /*len*/AHD_SCB_MAX * sizeof(struct ahd_completion), op);
10550 0 : }
10551 :
10552 : void
10553 0 : ahd_sync_tqinfifo(struct ahd_softc *ahd, int op)
10554 : {
10555 : #ifdef AHD_TARGET_MODE
10556 : if ((ahd->flags & AHD_TARGETROLE) != 0) {
10557 : ahd_dmamap_sync(ahd, ahd->parent_dmat,
10558 : ahd->shared_data_map.dmamap,
10559 : ahd_targetcmd_offset(ahd, 0),
10560 : sizeof(struct target_cmd) * AHD_TMODE_CMDS,
10561 : op);
10562 : }
10563 : #endif
10564 0 : }
10565 :
10566 : /*
10567 : * See if the firmware has posted any completed commands
10568 : * into our in-core command complete fifos.
10569 : */
10570 : #define AHD_RUN_QOUTFIFO 0x1
10571 : #define AHD_RUN_TQINFIFO 0x2
10572 : u_int
10573 0 : ahd_check_cmdcmpltqueues(struct ahd_softc *ahd)
10574 : {
10575 : u_int retval;
10576 :
10577 : retval = 0;
10578 0 : ahd_dmamap_sync(ahd, ahd->parent_dmat, ahd->shared_data_map.dmamap,
10579 : /*offset*/ahd->qoutfifonext * sizeof(*ahd->qoutfifo),
10580 : /*len*/sizeof(*ahd->qoutfifo), BUS_DMASYNC_POSTREAD);
10581 0 : if (ahd->qoutfifo[ahd->qoutfifonext].valid_tag
10582 0 : == ahd->qoutfifonext_valid_tag)
10583 0 : retval |= AHD_RUN_QOUTFIFO;
10584 : #ifdef AHD_TARGET_MODE
10585 : if ((ahd->flags & AHD_TARGETROLE) != 0
10586 : && (ahd->flags & AHD_TQINFIFO_BLOCKED) == 0) {
10587 : ahd_dmamap_sync(ahd, ahd->parent_dmat
10588 : ahd->shared_data_map.dmamap,
10589 : ahd_targetcmd_offset(ahd, ahd->tqinfifofnext),
10590 : /*len*/sizeof(struct target_cmd),
10591 : BUS_DMASYNC_POSTREAD);
10592 : if (ahd->targetcmds[ahd->tqinfifonext].cmd_valid != 0)
10593 : retval |= AHD_RUN_TQINFIFO;
10594 : }
10595 : #endif
10596 0 : return (retval);
10597 : }
10598 :
10599 : /*
10600 : * Catch an interrupt from the adapter
10601 : */
10602 : int
10603 0 : ahd_intr(struct ahd_softc *ahd)
10604 : {
10605 : u_int intstat;
10606 :
10607 0 : if ((ahd->pause & INTEN) == 0) {
10608 : /*
10609 : * Our interrupt is not enabled on the chip
10610 : * and may be disabled for re-entrancy reasons,
10611 : * so just return. This is likely just a shared
10612 : * interrupt.
10613 : */
10614 0 : return (0);
10615 : }
10616 :
10617 : /*
10618 : * Instead of directly reading the interrupt status register,
10619 : * infer the cause of the interrupt by checking our in-core
10620 : * completion queues. This avoids a costly PCI bus read in
10621 : * most cases.
10622 : */
10623 0 : if ((ahd->flags & AHD_ALL_INTERRUPTS) == 0
10624 0 : && (ahd_check_cmdcmpltqueues(ahd) != 0))
10625 0 : intstat = CMDCMPLT;
10626 : else
10627 0 : intstat = ahd_inb(ahd, INTSTAT);
10628 :
10629 0 : if ((intstat & INT_PEND) == 0)
10630 0 : return (0);
10631 :
10632 0 : if (intstat & CMDCMPLT) {
10633 0 : ahd_outb(ahd, CLRINT, CLRCMDINT);
10634 :
10635 : /*
10636 : * Ensure that the chip sees that we've cleared
10637 : * this interrupt before we walk the output fifo.
10638 : * Otherwise, we may, due to posted bus writes,
10639 : * clear the interrupt after we finish the scan,
10640 : * and after the sequencer has added new entries
10641 : * and asserted the interrupt again.
10642 : */
10643 0 : if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
10644 0 : if (ahd_is_paused(ahd)) {
10645 : /*
10646 : * Potentially lost SEQINT.
10647 : * If SEQINTCODE is non-zero,
10648 : * simulate the SEQINT.
10649 : */
10650 0 : if (ahd_inb(ahd, SEQINTCODE) != NO_SEQINT)
10651 0 : intstat |= SEQINT;
10652 : }
10653 : } else {
10654 0 : ahd_flush_device_writes(ahd);
10655 : }
10656 0 : ahd_run_qoutfifo(ahd);
10657 0 : ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]++;
10658 0 : ahd->cmdcmplt_total++;
10659 : #ifdef AHD_TARGET_MODE
10660 : if ((ahd->flags & AHD_TARGETROLE) != 0)
10661 : ahd_run_tqinfifo(ahd, /*paused*/FALSE);
10662 : #endif
10663 0 : }
10664 :
10665 : /*
10666 : * Handle statuses that may invalidate our cached
10667 : * copy of INTSTAT separately.
10668 : */
10669 0 : if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) {
10670 : /* Hot eject. Do nothing */
10671 0 : } else if (intstat & HWERRINT) {
10672 0 : ahd_handle_hwerrint(ahd);
10673 0 : } else if ((intstat & (PCIINT|SPLTINT)) != 0) {
10674 0 : ahd->bus_intr(ahd);
10675 0 : } else {
10676 :
10677 0 : if ((intstat & SEQINT) != 0)
10678 0 : ahd_handle_seqint(ahd, intstat);
10679 :
10680 0 : if ((intstat & SCSIINT) != 0)
10681 0 : ahd_handle_scsiint(ahd, intstat);
10682 : }
10683 0 : return (1);
10684 0 : }
10685 :
10686 : void
10687 0 : ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
10688 : {
10689 0 : ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
10690 0 : }
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