Line data Source code
1 : /* $OpenBSD: aic7xxx.c,v 1.93 2017/12/12 12:33:36 krw Exp $ */
2 : /* $NetBSD: aic7xxx.c,v 1.108 2003/11/02 11:07:44 wiz Exp $ */
3 :
4 : /*
5 : * Core routines and tables shareable across OS platforms.
6 : *
7 : * Copyright (c) 1994-2002 Justin T. Gibbs.
8 : * Copyright (c) 2000-2002 Adaptec Inc.
9 : * All rights reserved.
10 : *
11 : * Redistribution and use in source and binary forms, with or without
12 : * modification, are permitted provided that the following conditions
13 : * are met:
14 : * 1. Redistributions of source code must retain the above copyright
15 : * notice, this list of conditions, and the following disclaimer,
16 : * without modification.
17 : * 2. Redistributions in binary form must reproduce at minimum a disclaimer
18 : * substantially similar to the "NO WARRANTY" disclaimer below
19 : * ("Disclaimer") and any redistribution must be conditioned upon
20 : * including a substantially similar Disclaimer requirement for further
21 : * binary redistribution.
22 : * 3. Neither the names of the above-listed copyright holders nor the names
23 : * of any contributors may be used to endorse or promote products derived
24 : * from this software without specific prior written permission.
25 : *
26 : * Alternatively, this software may be distributed under the terms of the
27 : * GNU General Public License ("GPL") version 2 as published by the Free
28 : * Software Foundation.
29 : *
30 : * NO WARRANTY
31 : * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 : * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 : * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
34 : * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 : * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 : * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 : * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 : * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
39 : * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
40 : * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 : * POSSIBILITY OF SUCH DAMAGES.
42 : *
43 : * $Id: aic7xxx.c,v 1.93 2017/12/12 12:33:36 krw Exp $
44 : */
45 : /*
46 : * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
47 : */
48 :
49 : #include <dev/ic/aic7xxx_openbsd.h>
50 : #ifdef SMALL_KERNEL
51 : #define IO_EXPAND
52 : #endif
53 : #include <dev/ic/aic7xxx_inline.h>
54 : #include <dev/microcode/aic7xxx/aicasm_insformat.h>
55 :
56 : /****************************** Softc Data ************************************/
57 : struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq);
58 :
59 : /***************************** Lookup Tables **********************************/
60 : char *ahc_chip_names[] =
61 : {
62 : "NONE",
63 : "aic7770",
64 : "aic7850",
65 : "aic7855",
66 : "aic7859",
67 : "aic7860",
68 : "aic7870",
69 : "aic7880",
70 : "aic7895",
71 : "aic7895C",
72 : "aic7890/91",
73 : "aic7896/97",
74 : "aic7892",
75 : "aic7899"
76 : };
77 :
78 : /*
79 : * Hardware error codes.
80 : */
81 : struct ahc_hard_error_entry {
82 : uint8_t errno;
83 : char *errmesg;
84 : };
85 :
86 : #if !defined(SMALL_KERNEL)
87 : static struct ahc_hard_error_entry ahc_hard_errors[] = {
88 : { ILLHADDR, "Illegal Host Access" },
89 : { ILLSADDR, "Illegal Sequencer Address referrenced" },
90 : { ILLOPCODE, "Illegal Opcode in sequencer program" },
91 : { SQPARERR, "Sequencer Parity Error" },
92 : { DPARERR, "Data-path Parity Error" },
93 : { MPARERR, "Scratch or SCB Memory Parity Error" },
94 : { PCIERRSTAT, "PCI Error detected" },
95 : { CIOPARERR, "CIOBUS Parity Error" },
96 : };
97 : static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
98 : #endif /* !defined(SMALL_KERNEL) */
99 :
100 : static struct ahc_phase_table_entry ahc_phase_table[] =
101 : {
102 : { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
103 : { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
104 : { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
105 : { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
106 : { P_COMMAND, MSG_NOOP, "in Command phase" },
107 : { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
108 : { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
109 : { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
110 : { P_BUSFREE, MSG_NOOP, "while idle" },
111 : { 0, MSG_NOOP, "in unknown phase" }
112 : };
113 :
114 : /*
115 : * In most cases we only wish to itterate over real phases, so
116 : * exclude the last element from the count.
117 : */
118 : static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
119 :
120 : /*
121 : * Valid SCSIRATE values. (p. 3-17)
122 : * Provides a mapping of transfer periods in ns to the proper value to
123 : * stick in the scsixfer reg.
124 : */
125 : static struct ahc_syncrate ahc_syncrates[] =
126 : {
127 : /* ultra2 fast/ultra period rate */
128 : { 0x42, 0x000, 9, "80.0" },
129 : { 0x03, 0x000, 10, "40.0" },
130 : { 0x04, 0x000, 11, "33.0" },
131 : { 0x05, 0x100, 12, "20.0" },
132 : { 0x06, 0x110, 15, "16.0" },
133 : { 0x07, 0x120, 18, "13.4" },
134 : { 0x08, 0x000, 25, "10.0" },
135 : { 0x19, 0x010, 31, "8.0" },
136 : { 0x1a, 0x020, 37, "6.67" },
137 : { 0x1b, 0x030, 43, "5.7" },
138 : { 0x1c, 0x040, 50, "5.0" },
139 : { 0x00, 0x050, 56, "4.4" },
140 : { 0x00, 0x060, 62, "4.0" },
141 : { 0x00, 0x070, 68, "3.6" },
142 : { 0x00, 0x000, 0, NULL }
143 : };
144 :
145 : /* Our Sequencer Program */
146 : #include <dev/microcode/aic7xxx/aic7xxx_seq.h>
147 :
148 : /**************************** Function Declarations ***************************/
149 : static void ahc_force_renegotiation(struct ahc_softc *ahc,
150 : struct ahc_devinfo *devinfo);
151 : static struct ahc_tmode_tstate*
152 : ahc_alloc_tstate(struct ahc_softc *ahc,
153 : u_int scsi_id, char channel);
154 : #ifdef AHC_TARGET_MODE
155 : static void ahc_free_tstate(struct ahc_softc *ahc,
156 : u_int scsi_id, char channel, int force);
157 : #endif
158 : static struct ahc_syncrate*
159 : ahc_devlimited_syncrate(struct ahc_softc *ahc,
160 : struct ahc_initiator_tinfo *,
161 : u_int *period,
162 : u_int *ppr_options,
163 : role_t role);
164 : static void ahc_update_pending_scbs(struct ahc_softc *ahc);
165 : static void ahc_fetch_devinfo(struct ahc_softc *ahc,
166 : struct ahc_devinfo *devinfo);
167 : static void ahc_assert_atn(struct ahc_softc *ahc);
168 : static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
169 : struct ahc_devinfo *devinfo,
170 : struct scb *scb);
171 : static void ahc_build_transfer_msg(struct ahc_softc *ahc,
172 : struct ahc_devinfo *devinfo);
173 : static void ahc_construct_sdtr(struct ahc_softc *ahc,
174 : struct ahc_devinfo *devinfo,
175 : u_int period, u_int offset);
176 : static void ahc_construct_wdtr(struct ahc_softc *ahc,
177 : struct ahc_devinfo *devinfo,
178 : u_int bus_width);
179 : static void ahc_construct_ppr(struct ahc_softc *ahc,
180 : struct ahc_devinfo *devinfo,
181 : u_int period, u_int offset,
182 : u_int bus_width, u_int ppr_options);
183 : static void ahc_clear_msg_state(struct ahc_softc *ahc);
184 : static void ahc_handle_proto_violation(struct ahc_softc *ahc);
185 : static void ahc_handle_message_phase(struct ahc_softc *ahc);
186 : typedef enum {
187 : AHCMSG_1B,
188 : AHCMSG_2B,
189 : AHCMSG_EXT
190 : } ahc_msgtype;
191 : static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
192 : u_int msgval, int full);
193 : static int ahc_parse_msg(struct ahc_softc *ahc,
194 : struct ahc_devinfo *devinfo);
195 : static int ahc_handle_msg_reject(struct ahc_softc *ahc,
196 : struct ahc_devinfo *devinfo);
197 : static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
198 : struct ahc_devinfo *devinfo);
199 : static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
200 : static void ahc_handle_devreset(struct ahc_softc *ahc,
201 : struct ahc_devinfo *devinfo,
202 : cam_status status, char *message,
203 : int verbose_level);
204 : #ifdef AHC_TARGET_MODE
205 : static void ahc_setup_target_msgin(struct ahc_softc *ahc,
206 : struct ahc_devinfo *devinfo,
207 : struct scb *scb);
208 : #endif
209 :
210 : //static bus_dmamap_callback_t ahc_dmamap_cb;
211 : static void ahc_build_free_scb_list(struct ahc_softc *ahc);
212 : static int ahc_init_scbdata(struct ahc_softc *ahc);
213 : static void ahc_fini_scbdata(struct ahc_softc *ahc);
214 : static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
215 : struct scb *prev_scb,
216 : struct scb *scb);
217 : static int ahc_qinfifo_count(struct ahc_softc *ahc);
218 : static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
219 : u_int prev, u_int scbptr);
220 : static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
221 : static u_int ahc_rem_wscb(struct ahc_softc *ahc,
222 : u_int scbpos, u_int prev);
223 : static void ahc_reset_current_bus(struct ahc_softc *ahc);
224 : #ifdef AHC_DUMP_SEQ
225 : static void ahc_dumpseq(struct ahc_softc *ahc);
226 : #endif
227 : static int ahc_loadseq(struct ahc_softc *ahc);
228 : static int ahc_check_patch(struct ahc_softc *ahc,
229 : const struct patch **start_patch,
230 : u_int start_instr, u_int *skip_addr);
231 : static void ahc_download_instr(struct ahc_softc *ahc,
232 : u_int instrptr, uint8_t *dconsts);
233 : #ifdef AHC_TARGET_MODE
234 : static void ahc_queue_lstate_event(struct ahc_softc *ahc,
235 : struct ahc_tmode_lstate *lstate,
236 : u_int initiator_id,
237 : u_int event_type,
238 : u_int event_arg);
239 : static void ahc_update_scsiid(struct ahc_softc *ahc,
240 : u_int targid_mask);
241 : static int ahc_handle_target_cmd(struct ahc_softc *ahc,
242 : struct target_cmd *cmd);
243 : #endif
244 :
245 : /************************** Added for porting to NetBSD ***********************/
246 : static int ahc_createdmamem(bus_dma_tag_t tag,
247 : int size,
248 : int flags,
249 : bus_dmamap_t *mapp,
250 : caddr_t *vaddr,
251 : bus_addr_t *baddr,
252 : bus_dma_segment_t *seg,
253 : int *nseg,
254 : const char *myname, const char *what);
255 : static void ahc_freedmamem(bus_dma_tag_t tag,
256 : int size,
257 : bus_dmamap_t map,
258 : caddr_t vaddr,
259 : bus_dma_segment_t *seg,
260 : int nseg);
261 :
262 : /************************* Sequencer Execution Control ************************/
263 : /*
264 : * Restart the sequencer program from address zero
265 : */
266 : void
267 0 : ahc_restart(struct ahc_softc *ahc)
268 : {
269 :
270 0 : ahc_pause(ahc);
271 :
272 : /* No more pending messages. */
273 0 : ahc_clear_msg_state(ahc);
274 :
275 0 : ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
276 0 : ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
277 0 : ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
278 0 : ahc_outb(ahc, LASTPHASE, P_BUSFREE);
279 0 : ahc_outb(ahc, SAVED_SCSIID, 0xFF);
280 0 : ahc_outb(ahc, SAVED_LUN, 0xFF);
281 :
282 : /*
283 : * Ensure that the sequencer's idea of TQINPOS
284 : * matches our own. The sequencer increments TQINPOS
285 : * only after it sees a DMA complete and a reset could
286 : * occur before the increment leaving the kernel to believe
287 : * the command arrived but the sequencer to not.
288 : */
289 0 : ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
290 :
291 : /* Always allow reselection */
292 0 : ahc_outb(ahc, SCSISEQ,
293 : ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
294 0 : if ((ahc->features & AHC_CMD_CHAN) != 0) {
295 : /* Ensure that no DMA operations are in progress */
296 0 : ahc_outb(ahc, CCSCBCNT, 0);
297 0 : ahc_outb(ahc, CCSGCTL, 0);
298 0 : ahc_outb(ahc, CCSCBCTL, 0);
299 0 : }
300 : /*
301 : * If we were in the process of DMA'ing SCB data into
302 : * an SCB, replace that SCB on the free list. This prevents
303 : * an SCB leak.
304 : */
305 0 : if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
306 0 : ahc_add_curscb_to_free_list(ahc);
307 0 : ahc_outb(ahc, SEQ_FLAGS2,
308 : ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
309 0 : }
310 :
311 : /*
312 : * Clear any pending sequencer interrupt. It is no
313 : * longer relevant since we're resetting the Program
314 : * Counter.
315 : */
316 0 : ahc_outb(ahc, CLRINT, CLRSEQINT);
317 :
318 0 : ahc_outb(ahc, MWI_RESIDUAL, 0);
319 0 : ahc_outb(ahc, SEQCTL, ahc->seqctl);
320 0 : ahc_outb(ahc, SEQADDR0, 0);
321 0 : ahc_outb(ahc, SEQADDR1, 0);
322 :
323 0 : ahc_unpause(ahc);
324 0 : }
325 :
326 : /************************* Input/Output Queues ********************************/
327 : void
328 0 : ahc_run_qoutfifo(struct ahc_softc *ahc)
329 : {
330 : struct scb *scb;
331 : u_int scb_index;
332 :
333 0 : ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
334 0 : while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
335 :
336 : scb_index = ahc->qoutfifo[ahc->qoutfifonext];
337 : #ifdef __sgi__
338 : if ((ahc->qoutfifonext & 0x1f) == 0x1f) {
339 : u_int modnext;
340 : u_int32_t *nextp;
341 :
342 : /*
343 : * Clear 32 bytes of QOUTFIFO at a time
344 : * so that we don't clobber an incoming
345 : * byte DMA to the array on architectures
346 : * non coherent caches.
347 : */
348 : modnext = ahc->qoutfifonext & ~0x1f;
349 : nextp = (uint32_t *)(&ahc->qoutfifo[modnext]);
350 : *nextp++ = 0xFFFFFFFFUL;
351 : *nextp++ = 0xFFFFFFFFUL;
352 : *nextp++ = 0xFFFFFFFFUL;
353 : *nextp++ = 0xFFFFFFFFUL;
354 : *nextp++ = 0xFFFFFFFFUL;
355 : *nextp++ = 0xFFFFFFFFUL;
356 : *nextp++ = 0xFFFFFFFFUL;
357 : *nextp++ = 0xFFFFFFFFUL;
358 : ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
359 : ahc->shared_data_dmamap,
360 : /*offset*/modnext, /*len*/32,
361 : BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
362 : }
363 : #else
364 0 : if ((ahc->qoutfifonext & 0x03) == 0x03) {
365 : u_int modnext;
366 :
367 : /*
368 : * Clear 32bits of QOUTFIFO at a time
369 : * so that we don't clobber an incoming
370 : * byte DMA to the array on architectures
371 : * that only support 32bit load and store
372 : * operations.
373 : */
374 0 : modnext = ahc->qoutfifonext & ~0x3;
375 0 : *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
376 0 : ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
377 : ahc->shared_data_dmamap,
378 : /*offset*/modnext, /*len*/4,
379 : BUS_DMASYNC_PREREAD);
380 0 : }
381 : #endif
382 0 : ahc->qoutfifonext++;
383 :
384 0 : scb = ahc_lookup_scb(ahc, scb_index);
385 0 : if (scb == NULL) {
386 0 : printf("%s: WARNING no command for scb %d "
387 : "(cmdcmplt)\nQOUTPOS = %d\n",
388 0 : ahc_name(ahc), scb_index,
389 0 : (ahc->qoutfifonext - 1) & 0xFF);
390 0 : continue;
391 : }
392 :
393 : /*
394 : * Save off the residual
395 : * if there is one.
396 : */
397 0 : ahc_update_residual(ahc, scb);
398 0 : ahc_done(ahc, scb);
399 : }
400 0 : }
401 :
402 : void
403 0 : ahc_run_untagged_queues(struct ahc_softc *ahc)
404 : {
405 : int i;
406 :
407 0 : for (i = 0; i < 16; i++)
408 0 : ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
409 0 : }
410 :
411 : void
412 0 : ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
413 : {
414 : struct scb *scb;
415 :
416 0 : if (ahc->untagged_queue_lock != 0)
417 0 : return;
418 :
419 0 : if ((scb = TAILQ_FIRST(queue)) != NULL
420 0 : && (scb->flags & SCB_ACTIVE) == 0) {
421 0 : scb->flags |= SCB_ACTIVE;
422 0 : ahc_queue_scb(ahc, scb);
423 0 : }
424 0 : }
425 :
426 : /************************* Interrupt Handling *********************************/
427 : void
428 0 : ahc_handle_brkadrint(struct ahc_softc *ahc)
429 : {
430 : /*
431 : * We upset the sequencer :-(
432 : * Lookup the error message
433 : */
434 : #ifndef SMALL_KERNEL
435 : int i;
436 : int error;
437 :
438 0 : error = ahc_inb(ahc, ERROR);
439 0 : for (i = 0; error != 1 && i < num_errors; i++)
440 0 : error >>= 1;
441 0 : if (i >= num_errors)
442 0 : panic("invalid error code");
443 0 : printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
444 0 : ahc_name(ahc), ahc_hard_errors[i].errmesg,
445 0 : ahc_inb(ahc, SEQADDR0) |
446 0 : (ahc_inb(ahc, SEQADDR1) << 8));
447 :
448 0 : ahc_dump_card_state(ahc);
449 : #endif
450 :
451 : /* Tell everyone that this HBA is no longer available */
452 0 : ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
453 : CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
454 : CAM_NO_HBA);
455 :
456 : /* Disable all interrupt sources by resetting the controller */
457 0 : ahc_shutdown(ahc);
458 0 : }
459 :
460 : void
461 0 : ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
462 : {
463 : struct scb *scb;
464 0 : struct ahc_devinfo devinfo;
465 : u_int scb_index;
466 :
467 0 : ahc_fetch_devinfo(ahc, &devinfo);
468 :
469 : /*
470 : * Clear the upper byte that holds SEQINT status
471 : * codes and clear the SEQINT bit. We will unpause
472 : * the sequencer, if appropriate, after servicing
473 : * the request.
474 : */
475 0 : ahc_outb(ahc, CLRINT, CLRSEQINT);
476 0 : switch (intstat & SEQINT_MASK) {
477 : case BAD_STATUS:
478 : {
479 : struct hardware_scb *hscb;
480 :
481 : /*
482 : * Set the default return value to 0 (don't
483 : * send sense). The sense code will change
484 : * this if needed.
485 : */
486 0 : ahc_outb(ahc, RETURN_1, 0);
487 :
488 : /*
489 : * The sequencer will notify us when a command
490 : * has an error that would be of interest to
491 : * the kernel. This allows us to leave the sequencer
492 : * running in the common case of command completes
493 : * without error. The sequencer will already have
494 : * DMA'd the SCB back up to us, so we can reference
495 : * the in kernel copy directly.
496 : */
497 0 : scb_index = ahc_inb(ahc, SCB_TAG);
498 0 : scb = ahc_lookup_scb(ahc, scb_index);
499 0 : if (scb == NULL) {
500 0 : ahc_print_devinfo(ahc, &devinfo);
501 0 : printf("ahc_intr - referenced scb "
502 : "not valid during seqint 0x%x scb(%d)\n",
503 : intstat, scb_index);
504 0 : ahc_dump_card_state(ahc);
505 0 : panic("for safety");
506 : goto unpause;
507 : }
508 :
509 0 : hscb = scb->hscb;
510 :
511 : /* Don't want to clobber the original sense code */
512 0 : if ((scb->flags & SCB_SENSE) != 0) {
513 : /*
514 : * Clear the SCB_SENSE Flag and have
515 : * the sequencer do a normal command
516 : * complete.
517 : */
518 0 : scb->flags &= ~SCB_SENSE;
519 0 : ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
520 0 : break;
521 : }
522 0 : ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
523 : /* Freeze the queue until the client sees the error. */
524 0 : ahc_freeze_devq(ahc, scb);
525 0 : ahc_freeze_scb(scb);
526 0 : ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
527 0 : switch (hscb->shared_data.status.scsi_status) {
528 : case SCSI_STATUS_OK:
529 0 : printf("%s: Interrupted for status of 0 (?)\n",
530 0 : ahc_name(ahc));
531 0 : break;
532 : case SCSI_STATUS_CMD_TERMINATED:
533 : case SCSI_STATUS_CHECK_COND:
534 : {
535 : struct ahc_dma_seg *sg;
536 : struct scsi_sense *sc;
537 : struct ahc_initiator_tinfo *targ_info;
538 0 : struct ahc_tmode_tstate *tstate;
539 : struct ahc_transinfo *tinfo;
540 : #ifdef AHC_DEBUG
541 : if (ahc_debug & AHC_SHOW_SENSE) {
542 : ahc_print_path(ahc, scb);
543 : printf("SCB %d: requests Check Status\n",
544 : scb->hscb->tag);
545 : }
546 : #endif
547 :
548 0 : if (ahc_perform_autosense(scb) == 0)
549 0 : break;
550 :
551 0 : targ_info = ahc_fetch_transinfo(ahc,
552 0 : devinfo.channel,
553 0 : devinfo.our_scsiid,
554 0 : devinfo.target,
555 : &tstate);
556 0 : tinfo = &targ_info->curr;
557 0 : sg = scb->sg_list;
558 0 : sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
559 : /*
560 : * Save off the residual if there is one.
561 : */
562 0 : ahc_update_residual(ahc, scb);
563 : #ifdef AHC_DEBUG
564 : if (ahc_debug & AHC_SHOW_SENSE) {
565 : ahc_print_path(ahc, scb);
566 : printf("Sending Sense\n");
567 : }
568 : #endif
569 0 : sg->addr = ahc_get_sense_bufaddr(ahc, scb);
570 0 : sg->len = ahc_get_sense_bufsize(ahc, scb);
571 0 : sg->len |= AHC_DMA_LAST_SEG;
572 :
573 : /* Fixup byte order */
574 0 : sg->addr = aic_htole32(sg->addr);
575 0 : sg->len = aic_htole32(sg->len);
576 :
577 0 : sc->opcode = REQUEST_SENSE;
578 0 : sc->byte2 = 0;
579 0 : if (tinfo->protocol_version <= SCSI_REV_2
580 0 : && SCB_GET_LUN(scb) < 8)
581 0 : sc->byte2 = SCB_GET_LUN(scb) << 5;
582 0 : sc->unused[0] = 0;
583 0 : sc->unused[1] = 0;
584 0 : sc->length = sg->len;
585 0 : sc->control = 0;
586 :
587 : /*
588 : * We can't allow the target to disconnect.
589 : * This will be an untagged transaction and
590 : * having the target disconnect will make this
591 : * transaction indistinguishable from outstanding
592 : * tagged transactions.
593 : */
594 0 : hscb->control = 0;
595 :
596 : /*
597 : * This request sense could be because the
598 : * the device lost power or in some other
599 : * way has lost our transfer negotiations.
600 : * Renegotiate if appropriate. Unit attention
601 : * errors will be reported before any data
602 : * phases occur.
603 : */
604 0 : if (ahc_get_residual(scb)
605 0 : == ahc_get_transfer_length(scb)) {
606 0 : ahc_update_neg_request(ahc, &devinfo,
607 0 : tstate, targ_info,
608 : AHC_NEG_IF_NON_ASYNC);
609 0 : }
610 0 : if (tstate->auto_negotiate & devinfo.target_mask) {
611 0 : hscb->control |= MK_MESSAGE;
612 0 : scb->flags &= ~SCB_NEGOTIATE;
613 0 : scb->flags |= SCB_AUTO_NEGOTIATE;
614 0 : }
615 0 : hscb->cdb_len = sizeof(*sc);
616 0 : hscb->dataptr = sg->addr;
617 0 : hscb->datacnt = sg->len;
618 0 : hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
619 0 : hscb->sgptr = aic_htole32(hscb->sgptr);
620 : #ifdef __OpenBSD__
621 0 : bus_dmamap_sync(ahc->parent_dmat,
622 : ahc->scb_data->sense_dmamap,
623 : (scb - ahc->scb_data->scbarray) *
624 : sizeof(struct scsi_sense_data),
625 : sizeof(struct scsi_sense_data),
626 : BUS_DMASYNC_PREREAD);
627 0 : bus_dmamap_sync(ahc->parent_dmat,
628 : scb->sg_map->sg_dmamap,
629 : 0, scb->sg_map->sg_dmamap->dm_mapsize,
630 : BUS_DMASYNC_PREWRITE);
631 0 : bus_dmamap_sync(ahc->parent_dmat,
632 : ahc->scb_data->hscb_dmamap,
633 : 0, ahc->scb_data->hscb_dmamap->dm_mapsize,
634 : BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
635 : #endif
636 0 : scb->sg_count = 1;
637 0 : scb->flags |= SCB_SENSE;
638 0 : ahc_qinfifo_requeue_tail(ahc, scb);
639 0 : ahc_outb(ahc, RETURN_1, SEND_SENSE);
640 : /*
641 : * Ensure we have enough time to actually
642 : * retrieve the sense.
643 : */
644 0 : ahc_scb_timer_reset(scb, 5 * 1000000);
645 0 : break;
646 0 : }
647 : default:
648 : break;
649 : }
650 0 : break;
651 : }
652 : case NO_MATCH:
653 : {
654 : /* Ensure we don't leave the selection hardware on */
655 0 : ahc_outb(ahc, SCSISEQ,
656 : ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
657 :
658 0 : printf("%s:%c:%d: no active SCB for reconnecting "
659 : "target - issuing BUS DEVICE RESET\n",
660 0 : ahc_name(ahc), devinfo.channel, devinfo.target);
661 0 : printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
662 : "ARG_1 == 0x%x ACCUM = 0x%x\n",
663 0 : ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
664 0 : ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
665 0 : printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
666 : "SINDEX == 0x%x\n",
667 0 : ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
668 0 : ahc_index_busy_tcl(ahc,
669 0 : BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
670 : ahc_inb(ahc, SAVED_LUN))),
671 0 : ahc_inb(ahc, SINDEX));
672 0 : printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
673 : "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
674 0 : ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
675 0 : ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
676 0 : ahc_inb(ahc, SCB_CONTROL));
677 0 : printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
678 0 : ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
679 0 : printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
680 0 : printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
681 0 : ahc_dump_card_state(ahc);
682 0 : ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
683 0 : ahc->msgout_len = 1;
684 0 : ahc->msgout_index = 0;
685 0 : ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
686 0 : ahc_outb(ahc, MSG_OUT, HOST_MSG);
687 0 : ahc_assert_atn(ahc);
688 0 : break;
689 : }
690 : case SEND_REJECT:
691 : {
692 0 : u_int rejbyte = ahc_inb(ahc, ACCUM);
693 0 : printf("%s:%c:%d: Warning - unknown message received from "
694 : "target (0x%x). Rejecting\n",
695 0 : ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
696 : break;
697 : }
698 : case PROTO_VIOLATION:
699 : {
700 0 : ahc_handle_proto_violation(ahc);
701 0 : break;
702 : }
703 : case IGN_WIDE_RES:
704 0 : ahc_handle_ign_wide_residue(ahc, &devinfo);
705 0 : break;
706 : case PDATA_REINIT:
707 0 : ahc_reinitialize_dataptrs(ahc);
708 0 : break;
709 : case BAD_PHASE:
710 : {
711 : u_int lastphase;
712 :
713 0 : lastphase = ahc_inb(ahc, LASTPHASE);
714 0 : printf("%s:%c:%d: unknown scsi bus phase %x, "
715 : "lastphase = 0x%x. Attempting to continue\n",
716 0 : ahc_name(ahc), devinfo.channel, devinfo.target,
717 0 : lastphase, ahc_inb(ahc, SCSISIGI));
718 : break;
719 : }
720 : case MISSED_BUSFREE:
721 : {
722 : u_int lastphase;
723 :
724 0 : lastphase = ahc_inb(ahc, LASTPHASE);
725 0 : printf("%s:%c:%d: Missed busfree. "
726 : "Lastphase = 0x%x, Curphase = 0x%x\n",
727 0 : ahc_name(ahc), devinfo.channel, devinfo.target,
728 0 : lastphase, ahc_inb(ahc, SCSISIGI));
729 0 : ahc_restart(ahc);
730 : return;
731 : }
732 : case HOST_MSG_LOOP:
733 : {
734 : /*
735 : * The sequencer has encountered a message phase
736 : * that requires host assistance for completion.
737 : * While handling the message phase(s), we will be
738 : * notified by the sequencer after each byte is
739 : * transferred so we can track bus phase changes.
740 : *
741 : * If this is the first time we've seen a HOST_MSG_LOOP
742 : * interrupt, initialize the state of the host message
743 : * loop.
744 : */
745 0 : if (ahc->msg_type == MSG_TYPE_NONE) {
746 : u_int bus_phase;
747 :
748 0 : bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
749 0 : if (bus_phase != P_MESGIN
750 0 : && bus_phase != P_MESGOUT) {
751 0 : printf("ahc_intr: HOST_MSG_LOOP bad "
752 : "phase 0x%x\n",
753 : bus_phase);
754 : /*
755 : * Probably transitioned to bus free before
756 : * we got here. Just punt the message.
757 : */
758 0 : ahc_clear_intstat(ahc);
759 0 : ahc_restart(ahc);
760 0 : return;
761 : }
762 :
763 0 : scb_index = ahc_inb(ahc, SCB_TAG);
764 0 : scb = ahc_lookup_scb(ahc, scb_index);
765 0 : if (devinfo.role == ROLE_INITIATOR) {
766 0 : if (scb == NULL)
767 0 : panic("HOST_MSG_LOOP with "
768 : "invalid SCB %x\n", scb_index);
769 :
770 0 : if (bus_phase == P_MESGOUT)
771 0 : ahc_setup_initiator_msgout(ahc,
772 : &devinfo,
773 : scb);
774 : else {
775 0 : ahc->msg_type =
776 : MSG_TYPE_INITIATOR_MSGIN;
777 0 : ahc->msgin_index = 0;
778 : }
779 : }
780 : #ifdef AHC_TARGET_MODE
781 : else {
782 : if (bus_phase == P_MESGOUT) {
783 : ahc->msg_type =
784 : MSG_TYPE_TARGET_MSGOUT;
785 : ahc->msgin_index = 0;
786 : }
787 : else
788 : ahc_setup_target_msgin(ahc,
789 : &devinfo,
790 : scb);
791 : }
792 : #endif
793 0 : }
794 :
795 0 : ahc_handle_message_phase(ahc);
796 0 : break;
797 : }
798 : case PERR_DETECTED:
799 : {
800 : /*
801 : * If we've cleared the parity error interrupt
802 : * but the sequencer still believes that SCSIPERR
803 : * is true, it must be that the parity error is
804 : * for the currently presented byte on the bus,
805 : * and we are not in a phase (data-in) where we will
806 : * eventually ack this byte. Ack the byte and
807 : * throw it away in the hope that the target will
808 : * take us to message out to deliver the appropriate
809 : * error message.
810 : */
811 0 : if ((intstat & SCSIINT) == 0
812 0 : && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
813 :
814 0 : if ((ahc->features & AHC_DT) == 0) {
815 : u_int curphase;
816 :
817 : /*
818 : * The hardware will only let you ack bytes
819 : * if the expected phase in SCSISIGO matches
820 : * the current phase. Make sure this is
821 : * currently the case.
822 : */
823 0 : curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
824 0 : ahc_outb(ahc, LASTPHASE, curphase);
825 0 : ahc_outb(ahc, SCSISIGO, curphase);
826 0 : }
827 0 : if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
828 : int wait;
829 :
830 : /*
831 : * In a data phase. Faster to bitbucket
832 : * the data than to individually ack each
833 : * byte. This is also the only strategy
834 : * that will work with AUTOACK enabled.
835 : */
836 0 : ahc_outb(ahc, SXFRCTL1,
837 : ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
838 : wait = 5000;
839 0 : while (--wait != 0) {
840 0 : if ((ahc_inb(ahc, SCSISIGI)
841 0 : & (CDI|MSGI)) != 0)
842 : break;
843 0 : aic_delay(100);
844 : }
845 0 : ahc_outb(ahc, SXFRCTL1,
846 : ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
847 0 : if (wait == 0) {
848 0 : ahc_print_devinfo(ahc, &devinfo);
849 0 : printf("Unable to clear parity error. "
850 : "Resetting bus.\n");
851 0 : scb_index = ahc_inb(ahc, SCB_TAG);
852 0 : scb = ahc_lookup_scb(ahc, scb_index);
853 0 : if (scb != NULL)
854 0 : ahc_set_transaction_status(scb,
855 : CAM_UNCOR_PARITY);
856 0 : ahc_reset_channel(ahc, devinfo.channel,
857 : /*init reset*/TRUE);
858 0 : }
859 0 : } else {
860 0 : ahc_inb(ahc, SCSIDATL);
861 : }
862 : }
863 : break;
864 : }
865 : case DATA_OVERRUN:
866 : {
867 : /*
868 : * When the sequencer detects an overrun, it
869 : * places the controller in "BITBUCKET" mode
870 : * and allows the target to complete its transfer.
871 : * Unfortunately, none of the counters get updated
872 : * when the controller is in this mode, so we have
873 : * no way of knowing how large the overrun was.
874 : */
875 0 : u_int scbindex = ahc_inb(ahc, SCB_TAG);
876 0 : u_int lastphase = ahc_inb(ahc, LASTPHASE);
877 : u_int i;
878 :
879 0 : scb = ahc_lookup_scb(ahc, scbindex);
880 0 : for (i = 0; i < num_phases; i++) {
881 0 : if (lastphase == ahc_phase_table[i].phase)
882 : break;
883 : }
884 : #ifdef AHC_DEBUG
885 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
886 : ahc_print_path(ahc, scb);
887 : printf("data overrun detected %s."
888 : " Tag == 0x%x.\n",
889 : ahc_phase_table[i].phasemsg,
890 : scb->hscb->tag);
891 : ahc_print_path(ahc, scb);
892 : printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
893 : ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
894 : ahc_get_transfer_length(scb), scb->sg_count);
895 : if (scb->sg_count > 0) {
896 : for (i = 0; i < scb->sg_count; i++) {
897 :
898 : printf("sg[%d] - Addr 0x%x%x : Length %d\n",
899 : i,
900 : (aic_le32toh(scb->sg_list[i].len) >> 24
901 : & SG_HIGH_ADDR_BITS),
902 : aic_le32toh(scb->sg_list[i].addr),
903 : aic_le32toh(scb->sg_list[i].len)
904 : & AHC_SG_LEN_MASK);
905 : }
906 : }
907 : }
908 : #endif
909 : /*
910 : * Set this and it will take effect when the
911 : * target does a command complete.
912 : */
913 0 : ahc_freeze_devq(ahc, scb);
914 0 : if ((scb->flags & SCB_SENSE) == 0) {
915 0 : ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
916 0 : } else {
917 0 : scb->flags &= ~SCB_SENSE;
918 0 : ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
919 : }
920 0 : ahc_freeze_scb(scb);
921 :
922 0 : if ((ahc->features & AHC_ULTRA2) != 0) {
923 : /*
924 : * Clear the channel in case we return
925 : * to data phase later.
926 : */
927 0 : ahc_outb(ahc, SXFRCTL0,
928 : ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
929 0 : ahc_outb(ahc, SXFRCTL0,
930 : ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
931 0 : }
932 0 : if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
933 : u_int dscommand1;
934 :
935 : /* Ensure HHADDR is 0 for future DMA operations. */
936 0 : dscommand1 = ahc_inb(ahc, DSCOMMAND1);
937 0 : ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
938 0 : ahc_outb(ahc, HADDR, 0);
939 0 : ahc_outb(ahc, DSCOMMAND1, dscommand1);
940 0 : }
941 : break;
942 : }
943 : case MKMSG_FAILED:
944 : {
945 : u_int scbindex;
946 :
947 0 : printf("%s:%c:%d:%d: Attempt to issue message failed\n",
948 0 : ahc_name(ahc), devinfo.channel, devinfo.target,
949 0 : devinfo.lun);
950 0 : scbindex = ahc_inb(ahc, SCB_TAG);
951 0 : scb = ahc_lookup_scb(ahc, scbindex);
952 0 : if (scb != NULL)
953 : /*
954 : * Ensure that we didn't put a second instance of this
955 : * SCB into the QINFIFO.
956 : */
957 0 : ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
958 0 : SCB_GET_CHANNEL(ahc, scb),
959 0 : SCB_GET_LUN(scb), scb->hscb->tag,
960 : ROLE_INITIATOR, /*status*/0,
961 : SEARCH_REMOVE);
962 : break;
963 : }
964 : case NO_FREE_SCB:
965 : {
966 0 : printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
967 0 : ahc_dump_card_state(ahc);
968 0 : panic("for safety");
969 : break;
970 : }
971 : case SCB_MISMATCH:
972 : {
973 : u_int scbptr;
974 :
975 0 : scbptr = ahc_inb(ahc, SCBPTR);
976 0 : printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
977 0 : scbptr, ahc_inb(ahc, ARG_1),
978 0 : ahc->scb_data->hscbs[scbptr].tag);
979 0 : ahc_dump_card_state(ahc);
980 0 : panic("for safety");
981 : break;
982 : }
983 : case OUT_OF_RANGE:
984 : {
985 : #ifndef SMALL_KERNEL
986 0 : printf("%s: BTT calculation out of range\n", ahc_name(ahc));
987 0 : printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
988 : "ARG_1 == 0x%x ACCUM = 0x%x\n",
989 0 : ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
990 0 : ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
991 0 : printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
992 : "SINDEX == 0x%x\n, A == 0x%x\n",
993 0 : ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
994 0 : ahc_index_busy_tcl(ahc,
995 0 : BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
996 : ahc_inb(ahc, SAVED_LUN))),
997 0 : ahc_inb(ahc, SINDEX),
998 0 : ahc_inb(ahc, ACCUM));
999 0 : printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1000 : "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1001 0 : ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1002 0 : ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1003 0 : ahc_inb(ahc, SCB_CONTROL));
1004 0 : printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1005 0 : ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
1006 : #endif
1007 0 : ahc_dump_card_state(ahc);
1008 0 : panic("for safety");
1009 : break;
1010 : }
1011 : default:
1012 0 : printf("ahc_intr: seqint, "
1013 : "intstat == 0x%x, scsisigi = 0x%x\n",
1014 0 : intstat, ahc_inb(ahc, SCSISIGI));
1015 0 : break;
1016 : }
1017 : unpause:
1018 : /*
1019 : * The sequencer is paused immediately on
1020 : * a SEQINT, so we should restart it when
1021 : * we're done.
1022 : */
1023 0 : ahc_unpause(ahc);
1024 0 : }
1025 :
1026 : void
1027 0 : ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
1028 : {
1029 : u_int scb_index;
1030 : u_int status0;
1031 : u_int status;
1032 : struct scb *scb;
1033 : char cur_channel;
1034 : char intr_channel;
1035 :
1036 0 : if ((ahc->features & AHC_TWIN) != 0
1037 0 : && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
1038 0 : cur_channel = 'B';
1039 : else
1040 : cur_channel = 'A';
1041 : intr_channel = cur_channel;
1042 :
1043 0 : if ((ahc->features & AHC_ULTRA2) != 0)
1044 0 : status0 = ahc_inb(ahc, SSTAT0) & IOERR;
1045 : else
1046 : status0 = 0;
1047 0 : status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1048 0 : if (status == 0 && status0 == 0) {
1049 0 : if ((ahc->features & AHC_TWIN) != 0) {
1050 : /* Try the other channel */
1051 0 : ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1052 0 : status = ahc_inb(ahc, SSTAT1)
1053 0 : & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1054 0 : intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1055 0 : }
1056 0 : if (status == 0) {
1057 0 : printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1058 0 : ahc_outb(ahc, CLRINT, CLRSCSIINT);
1059 0 : ahc_unpause(ahc);
1060 0 : return;
1061 : }
1062 : }
1063 :
1064 : /* Make sure the sequencer is in a safe location. */
1065 0 : ahc_clear_critical_section(ahc);
1066 :
1067 0 : scb_index = ahc_inb(ahc, SCB_TAG);
1068 0 : scb = ahc_lookup_scb(ahc, scb_index);
1069 0 : if (scb != NULL
1070 0 : && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1071 0 : scb = NULL;
1072 :
1073 0 : if ((ahc->features & AHC_ULTRA2) != 0
1074 0 : && (status0 & IOERR) != 0) {
1075 : int now_lvd;
1076 :
1077 0 : now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1078 0 : printf("%s: Transceiver State Has Changed to %s mode\n",
1079 0 : ahc_name(ahc), now_lvd ? "LVD" : "SE");
1080 0 : ahc_outb(ahc, CLRSINT0, CLRIOERR);
1081 : /*
1082 : * When transitioning to SE mode, the reset line
1083 : * glitches, triggering an arbitration bug in some
1084 : * Ultra2 controllers. This bug is cleared when we
1085 : * assert the reset line. Since a reset glitch has
1086 : * already occurred with this transition and a
1087 : * transceiver state change is handled just like
1088 : * a bus reset anyway, asserting the reset line
1089 : * ourselves is safe.
1090 : */
1091 0 : ahc_reset_channel(ahc, intr_channel,
1092 0 : /*Initiate Reset*/now_lvd == 0);
1093 0 : } else if ((status & SCSIRSTI) != 0) {
1094 0 : printf("%s: Someone reset channel %c\n",
1095 0 : ahc_name(ahc), intr_channel);
1096 0 : if (intr_channel != cur_channel)
1097 0 : ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1098 0 : ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1099 0 : } else if ((status & SCSIPERR) != 0) {
1100 : /*
1101 : * Determine the bus phase and queue an appropriate message.
1102 : * SCSIPERR is latched true as soon as a parity error
1103 : * occurs. If the sequencer acked the transfer that
1104 : * caused the parity error and the currently presented
1105 : * transfer on the bus has correct parity, SCSIPERR will
1106 : * be cleared by CLRSCSIPERR. Use this to determine if
1107 : * we should look at the last phase the sequencer recorded,
1108 : * or the current phase presented on the bus.
1109 : */
1110 0 : struct ahc_devinfo devinfo;
1111 : u_int mesg_out;
1112 : u_int curphase;
1113 : u_int errorphase;
1114 : u_int lastphase;
1115 : u_int scsirate;
1116 : u_int i;
1117 : u_int sstat2;
1118 : int silent;
1119 :
1120 0 : lastphase = ahc_inb(ahc, LASTPHASE);
1121 0 : curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1122 0 : sstat2 = ahc_inb(ahc, SSTAT2);
1123 0 : ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1124 : /*
1125 : * For all phases save DATA, the sequencer won't
1126 : * automatically ack a byte that has a parity error
1127 : * in it. So the only way that the current phase
1128 : * could be 'data-in' is if the parity error is for
1129 : * an already acked byte in the data phase. During
1130 : * synchronous data-in transfers, we may actually
1131 : * ack bytes before latching the current phase in
1132 : * LASTPHASE, leading to the discrepancy between
1133 : * curphase and lastphase.
1134 : */
1135 0 : if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1136 0 : || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1137 0 : errorphase = curphase;
1138 : else
1139 : errorphase = lastphase;
1140 :
1141 0 : for (i = 0; i < num_phases; i++) {
1142 0 : if (errorphase == ahc_phase_table[i].phase)
1143 : break;
1144 : }
1145 0 : mesg_out = ahc_phase_table[i].mesg_out;
1146 : silent = FALSE;
1147 0 : if (scb != NULL) {
1148 0 : if (SCB_IS_SILENT(scb))
1149 0 : silent = TRUE;
1150 : else
1151 0 : ahc_print_path(ahc, scb);
1152 0 : scb->flags |= SCB_TRANSMISSION_ERROR;
1153 0 : } else
1154 0 : printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1155 0 : SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1156 0 : scsirate = ahc_inb(ahc, SCSIRATE);
1157 0 : if (silent == FALSE) {
1158 0 : printf("parity error detected %s. "
1159 : "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1160 0 : ahc_phase_table[i].phasemsg,
1161 0 : ahc_inw(ahc, SEQADDR0),
1162 : scsirate);
1163 0 : if ((ahc->features & AHC_DT) != 0) {
1164 0 : if ((sstat2 & CRCVALERR) != 0)
1165 0 : printf("\tCRC Value Mismatch\n");
1166 0 : if ((sstat2 & CRCENDERR) != 0)
1167 0 : printf("\tNo terminal CRC packet "
1168 : "received\n");
1169 0 : if ((sstat2 & CRCREQERR) != 0)
1170 0 : printf("\tIllegal CRC packet "
1171 : "request\n");
1172 0 : if ((sstat2 & DUAL_EDGE_ERR) != 0)
1173 0 : printf("\tUnexpected %sDT Data Phase\n",
1174 0 : (scsirate & SINGLE_EDGE)
1175 : ? "" : "non-");
1176 : }
1177 : }
1178 :
1179 0 : if ((ahc->features & AHC_DT) != 0
1180 0 : && (sstat2 & DUAL_EDGE_ERR) != 0) {
1181 : /*
1182 : * This error applies regardless of
1183 : * data direction, so ignore the value
1184 : * in the phase table.
1185 : */
1186 : mesg_out = MSG_INITIATOR_DET_ERR;
1187 0 : }
1188 :
1189 : /*
1190 : * We've set the hardware to assert ATN if we
1191 : * get a parity error on "in" phases, so all we
1192 : * need to do is stuff the message buffer with
1193 : * the appropriate message. "In" phases have set
1194 : * mesg_out to something other than MSG_NOP.
1195 : */
1196 0 : if (mesg_out != MSG_NOOP) {
1197 0 : if (ahc->msg_type != MSG_TYPE_NONE)
1198 0 : ahc->send_msg_perror = TRUE;
1199 : else
1200 0 : ahc_outb(ahc, MSG_OUT, mesg_out);
1201 : }
1202 : /*
1203 : * Force a renegotiation with this target just in
1204 : * case we are out of sync for some external reason
1205 : * unknown (or unreported) by the target.
1206 : */
1207 0 : ahc_fetch_devinfo(ahc, &devinfo);
1208 0 : ahc_force_renegotiation(ahc, &devinfo);
1209 :
1210 0 : ahc_outb(ahc, CLRINT, CLRSCSIINT);
1211 0 : ahc_unpause(ahc);
1212 0 : } else if ((status & SELTO) != 0) {
1213 : u_int scbptr;
1214 :
1215 : /* Stop the selection */
1216 0 : ahc_outb(ahc, SCSISEQ, 0);
1217 :
1218 : /* No more pending messages */
1219 0 : ahc_clear_msg_state(ahc);
1220 :
1221 : /* Clear interrupt state */
1222 0 : ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1223 0 : ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1224 :
1225 : /*
1226 : * Although the driver does not care about the
1227 : * 'Selection in Progress' status bit, the busy
1228 : * LED does. SELINGO is only cleared by a successful
1229 : * selection, so we must manually clear it to insure
1230 : * the LED turns off just incase no future successful
1231 : * selections occur (e.g. no devices on the bus).
1232 : */
1233 0 : ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1234 :
1235 0 : scbptr = ahc_inb(ahc, WAITING_SCBH);
1236 0 : ahc_outb(ahc, SCBPTR, scbptr);
1237 0 : scb_index = ahc_inb(ahc, SCB_TAG);
1238 :
1239 0 : scb = ahc_lookup_scb(ahc, scb_index);
1240 0 : if (scb == NULL) {
1241 0 : printf("%s: ahc_intr - referenced scb not "
1242 : "valid during SELTO scb(%d, %d)\n",
1243 0 : ahc_name(ahc), scbptr, scb_index);
1244 0 : ahc_dump_card_state(ahc);
1245 0 : } else {
1246 0 : struct ahc_devinfo devinfo;
1247 : #ifdef AHC_DEBUG
1248 : if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1249 : ahc_print_path(ahc, scb);
1250 : printf("Saw Selection Timeout for SCB 0x%x\n",
1251 : scb_index);
1252 : }
1253 : #endif
1254 0 : ahc_scb_devinfo(ahc, &devinfo, scb);
1255 0 : ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1256 0 : ahc_freeze_devq(ahc, scb);
1257 :
1258 : /*
1259 : * Cancel any pending transactions on the device
1260 : * now that it seems to be missing. This will
1261 : * also revert us to async/narrow transfers until
1262 : * we can renegotiate with the device.
1263 : */
1264 0 : ahc_handle_devreset(ahc, &devinfo,
1265 : CAM_SEL_TIMEOUT,
1266 : "Selection Timeout",
1267 : /*verbose_level*/1);
1268 0 : }
1269 0 : ahc_outb(ahc, CLRINT, CLRSCSIINT);
1270 0 : ahc_restart(ahc);
1271 0 : } else if ((status & BUSFREE) != 0
1272 0 : && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1273 0 : struct ahc_devinfo devinfo;
1274 : u_int lastphase;
1275 : u_int saved_scsiid;
1276 : u_int saved_lun;
1277 : u_int target;
1278 : u_int initiator_role_id;
1279 : char channel;
1280 : int printerror;
1281 :
1282 : /*
1283 : * Clear our selection hardware as soon as possible.
1284 : * We may have an entry in the waiting Q for this target,
1285 : * that is affected by this busfree and we don't want to
1286 : * go about selecting the target while we handle the event.
1287 : */
1288 0 : ahc_outb(ahc, SCSISEQ,
1289 : ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1290 :
1291 : /*
1292 : * Disable busfree interrupts and clear the busfree
1293 : * interrupt status. We do this here so that several
1294 : * bus transactions occur prior to clearing the SCSIINT
1295 : * latch. It can take a bit for the clearing to take effect.
1296 : */
1297 0 : ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1298 0 : ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1299 :
1300 : /*
1301 : * Look at what phase we were last in.
1302 : * If its message out, chances are pretty good
1303 : * that the busfree was in response to one of
1304 : * our abort requests.
1305 : */
1306 0 : lastphase = ahc_inb(ahc, LASTPHASE);
1307 0 : saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1308 0 : saved_lun = ahc_inb(ahc, SAVED_LUN);
1309 0 : target = SCSIID_TARGET(ahc, saved_scsiid);
1310 0 : initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1311 0 : channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1312 0 : ahc_compile_devinfo(&devinfo, initiator_role_id,
1313 : target, saved_lun, channel, ROLE_INITIATOR);
1314 : printerror = 1;
1315 :
1316 0 : if (lastphase == P_MESGOUT) {
1317 : u_int tag;
1318 :
1319 : tag = SCB_LIST_NULL;
1320 0 : if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1321 0 : || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1322 0 : if (ahc->msgout_buf[ahc->msgout_index - 1]
1323 0 : == MSG_ABORT_TAG)
1324 0 : tag = scb->hscb->tag;
1325 0 : ahc_print_path(ahc, scb);
1326 0 : printf("SCB %d - Abort%s Completed.\n",
1327 0 : scb->hscb->tag, tag == SCB_LIST_NULL ?
1328 : "" : " Tag");
1329 0 : ahc_abort_scbs(ahc, target, channel,
1330 : saved_lun, tag,
1331 : ROLE_INITIATOR,
1332 : CAM_REQ_ABORTED);
1333 : printerror = 0;
1334 0 : } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1335 : MSG_BUS_DEV_RESET, TRUE)) {
1336 : #ifdef __FreeBSD__
1337 : /*
1338 : * Don't mark the user's request for this BDR
1339 : * as completing with CAM_BDR_SENT. CAM3
1340 : * specifies CAM_REQ_CMP.
1341 : */
1342 : if (scb != NULL
1343 : && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1344 : && ahc_match_scb(ahc, scb, target, channel,
1345 : CAM_LUN_WILDCARD,
1346 : SCB_LIST_NULL,
1347 : ROLE_INITIATOR)) {
1348 : ahc_set_transaction_status(scb, CAM_REQ_CMP);
1349 : }
1350 : #endif
1351 0 : ahc_compile_devinfo(&devinfo,
1352 : initiator_role_id,
1353 : target,
1354 : CAM_LUN_WILDCARD,
1355 : channel,
1356 : ROLE_INITIATOR);
1357 0 : ahc_handle_devreset(ahc, &devinfo,
1358 : CAM_BDR_SENT,
1359 : "Bus Device Reset",
1360 : /*verbose_level*/0);
1361 : printerror = 0;
1362 0 : } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1363 : MSG_EXT_PPR, FALSE)) {
1364 : struct ahc_initiator_tinfo *tinfo;
1365 0 : struct ahc_tmode_tstate *tstate;
1366 :
1367 : /*
1368 : * PPR Rejected. Try non-ppr negotiation
1369 : * and retry command.
1370 : */
1371 0 : tinfo = ahc_fetch_transinfo(ahc,
1372 0 : devinfo.channel,
1373 0 : devinfo.our_scsiid,
1374 0 : devinfo.target,
1375 : &tstate);
1376 0 : tinfo->curr.transport_version = 2;
1377 0 : tinfo->goal.transport_version = 2;
1378 0 : tinfo->goal.ppr_options = 0;
1379 0 : ahc_qinfifo_requeue_tail(ahc, scb);
1380 : printerror = 0;
1381 0 : } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1382 : MSG_EXT_WDTR, FALSE)) {
1383 : /*
1384 : * Negotiation Rejected. Go-narrow and
1385 : * retry command.
1386 : */
1387 0 : ahc_set_width(ahc, &devinfo,
1388 : MSG_EXT_WDTR_BUS_8_BIT,
1389 : AHC_TRANS_CUR|AHC_TRANS_GOAL,
1390 : /*paused*/TRUE);
1391 0 : ahc_qinfifo_requeue_tail(ahc, scb);
1392 : printerror = 0;
1393 0 : } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1394 : MSG_EXT_SDTR, FALSE)) {
1395 : /*
1396 : * Negotiation Rejected. Go-async and
1397 : * retry command.
1398 : */
1399 0 : ahc_set_syncrate(ahc, &devinfo,
1400 : /*syncrate*/NULL,
1401 : /*period*/0, /*offset*/0,
1402 : /*ppr_options*/0,
1403 : AHC_TRANS_CUR|AHC_TRANS_GOAL,
1404 : /*paused*/TRUE);
1405 0 : ahc_qinfifo_requeue_tail(ahc, scb);
1406 : printerror = 0;
1407 0 : }
1408 0 : }
1409 0 : if (printerror != 0) {
1410 : u_int i;
1411 :
1412 0 : if (scb != NULL) {
1413 : u_int tag;
1414 :
1415 0 : if ((scb->hscb->control & TAG_ENB) != 0)
1416 0 : tag = scb->hscb->tag;
1417 : else
1418 : tag = SCB_LIST_NULL;
1419 0 : ahc_print_path(ahc, scb);
1420 0 : ahc_abort_scbs(ahc, target, channel,
1421 0 : SCB_GET_LUN(scb), tag,
1422 : ROLE_INITIATOR,
1423 : CAM_UNEXP_BUSFREE);
1424 0 : } else {
1425 : /*
1426 : * We had not fully identified this connection,
1427 : * so we cannot abort anything.
1428 : */
1429 0 : printf("%s: ", ahc_name(ahc));
1430 : }
1431 0 : for (i = 0; i < num_phases; i++) {
1432 0 : if (lastphase == ahc_phase_table[i].phase)
1433 : break;
1434 : }
1435 0 : if (lastphase != P_BUSFREE) {
1436 : /*
1437 : * Renegotiate with this device at the
1438 : * next oportunity just in case this busfree
1439 : * is due to a negotiation mismatch with the
1440 : * device.
1441 : */
1442 0 : ahc_force_renegotiation(ahc, &devinfo);
1443 0 : }
1444 0 : printf("Unexpected busfree %s\n"
1445 : "SEQADDR == 0x%x\n",
1446 0 : ahc_phase_table[i].phasemsg,
1447 0 : ahc_inb(ahc, SEQADDR0)
1448 0 : | (ahc_inb(ahc, SEQADDR1) << 8));
1449 0 : }
1450 0 : ahc_outb(ahc, CLRINT, CLRSCSIINT);
1451 0 : ahc_restart(ahc);
1452 0 : } else {
1453 0 : printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1454 0 : ahc_name(ahc), status);
1455 0 : ahc_outb(ahc, CLRINT, CLRSCSIINT);
1456 : }
1457 0 : }
1458 :
1459 : /*
1460 : * Force renegotiation to occur the next time we initiate
1461 : * a command to the current device.
1462 : */
1463 : void
1464 0 : ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1465 : {
1466 : struct ahc_initiator_tinfo *targ_info;
1467 0 : struct ahc_tmode_tstate *tstate;
1468 :
1469 0 : targ_info = ahc_fetch_transinfo(ahc,
1470 0 : devinfo->channel,
1471 0 : devinfo->our_scsiid,
1472 0 : devinfo->target,
1473 : &tstate);
1474 0 : ahc_update_neg_request(ahc, devinfo, tstate,
1475 : targ_info, AHC_NEG_IF_NON_ASYNC);
1476 0 : }
1477 :
1478 : #define AHC_MAX_STEPS 2000
1479 : void
1480 0 : ahc_clear_critical_section(struct ahc_softc *ahc)
1481 : {
1482 : int stepping;
1483 : int steps;
1484 : u_int simode0;
1485 : u_int simode1;
1486 :
1487 0 : if (ahc->num_critical_sections == 0)
1488 0 : return;
1489 :
1490 : stepping = FALSE;
1491 : steps = 0;
1492 : simode0 = 0;
1493 : simode1 = 0;
1494 0 : for (;;) {
1495 : struct cs *cs;
1496 : u_int seqaddr;
1497 : u_int i;
1498 :
1499 0 : seqaddr = ahc_inb(ahc, SEQADDR0)
1500 0 : | (ahc_inb(ahc, SEQADDR1) << 8);
1501 :
1502 : /*
1503 : * Seqaddr represents the next instruction to execute,
1504 : * so we are really executing the instruction just
1505 : * before it.
1506 : */
1507 0 : cs = ahc->critical_sections;
1508 0 : for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1509 :
1510 0 : if (cs->begin < seqaddr && cs->end >= seqaddr)
1511 : break;
1512 : }
1513 :
1514 0 : if (i == ahc->num_critical_sections)
1515 0 : break;
1516 :
1517 0 : if (steps > AHC_MAX_STEPS) {
1518 0 : printf("%s: Infinite loop in critical section\n",
1519 0 : ahc_name(ahc));
1520 0 : ahc_dump_card_state(ahc);
1521 0 : panic("critical section loop");
1522 : }
1523 :
1524 0 : steps++;
1525 0 : if (stepping == FALSE) {
1526 :
1527 : /*
1528 : * Disable all interrupt sources so that the
1529 : * sequencer will not be stuck by a pausing
1530 : * interrupt condition while we attempt to
1531 : * leave a critical section.
1532 : */
1533 0 : simode0 = ahc_inb(ahc, SIMODE0);
1534 0 : ahc_outb(ahc, SIMODE0, 0);
1535 0 : simode1 = ahc_inb(ahc, SIMODE1);
1536 0 : if ((ahc->features & AHC_DT) != 0)
1537 : /*
1538 : * On DT class controllers, we
1539 : * use the enhanced busfree logic.
1540 : * Unfortunately we cannot re-enable
1541 : * busfree detection within the
1542 : * current connection, so we must
1543 : * leave it on while single stepping.
1544 : */
1545 0 : ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1546 : else
1547 0 : ahc_outb(ahc, SIMODE1, 0);
1548 0 : ahc_outb(ahc, CLRINT, CLRSCSIINT);
1549 0 : ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1550 : stepping = TRUE;
1551 0 : }
1552 0 : if ((ahc->features & AHC_DT) != 0) {
1553 0 : ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1554 0 : ahc_outb(ahc, CLRINT, CLRSCSIINT);
1555 0 : }
1556 0 : ahc_outb(ahc, HCNTRL, ahc->unpause);
1557 0 : while (!ahc_is_paused(ahc))
1558 0 : aic_delay(200);
1559 0 : }
1560 0 : if (stepping) {
1561 0 : ahc_outb(ahc, SIMODE0, simode0);
1562 0 : ahc_outb(ahc, SIMODE1, simode1);
1563 0 : ahc_outb(ahc, SEQCTL, ahc->seqctl);
1564 0 : }
1565 0 : }
1566 :
1567 : /*
1568 : * Clear any pending interrupt status.
1569 : */
1570 : void
1571 0 : ahc_clear_intstat(struct ahc_softc *ahc)
1572 : {
1573 : /* Clear any interrupt conditions this may have caused */
1574 0 : ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1575 : |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1576 : CLRREQINIT);
1577 0 : ahc_flush_device_writes(ahc);
1578 0 : ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1579 0 : ahc_flush_device_writes(ahc);
1580 0 : ahc_outb(ahc, CLRINT, CLRSCSIINT);
1581 0 : ahc_flush_device_writes(ahc);
1582 0 : }
1583 :
1584 : /**************************** Debugging Routines ******************************/
1585 : #ifdef AHC_DEBUG
1586 : uint32_t ahc_debug = 0; /* AHC_SHOW_MISC|AHC_SHOW_SENSE|AHC_DEBUG_OPTS;*/
1587 :
1588 : void
1589 : ahc_print_scb(struct scb *scb)
1590 : {
1591 : int i;
1592 :
1593 : struct hardware_scb *hscb = scb->hscb;
1594 :
1595 : printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1596 : (void *)scb,
1597 : hscb->control,
1598 : hscb->scsiid,
1599 : hscb->lun,
1600 : hscb->cdb_len);
1601 : printf("Shared Data: ");
1602 : for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1603 : printf("%#02x", hscb->shared_data.cdb[i]);
1604 : printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1605 : aic_le32toh(hscb->dataptr),
1606 : aic_le32toh(hscb->datacnt),
1607 : aic_le32toh(hscb->sgptr),
1608 : hscb->tag);
1609 : if (scb->sg_count > 0) {
1610 : for (i = 0; i < scb->sg_count; i++) {
1611 : printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1612 : i,
1613 : (aic_le32toh(scb->sg_list[i].len) >> 24
1614 : & SG_HIGH_ADDR_BITS),
1615 : aic_le32toh(scb->sg_list[i].addr),
1616 : aic_le32toh(scb->sg_list[i].len));
1617 : }
1618 : }
1619 : }
1620 : #endif
1621 :
1622 : /************************* Transfer Negotiation *******************************/
1623 : /*
1624 : * Allocate per target mode instance (ID we respond to as a target)
1625 : * transfer negotiation data structures.
1626 : */
1627 : static struct ahc_tmode_tstate *
1628 0 : ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1629 : {
1630 : struct ahc_tmode_tstate *master_tstate;
1631 : struct ahc_tmode_tstate *tstate;
1632 : int i;
1633 :
1634 0 : master_tstate = ahc->enabled_targets[ahc->our_id];
1635 0 : if (channel == 'B') {
1636 0 : scsi_id += 8;
1637 0 : master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1638 0 : }
1639 0 : if (ahc->enabled_targets[scsi_id] != NULL
1640 0 : && ahc->enabled_targets[scsi_id] != master_tstate)
1641 0 : panic("%s: ahc_alloc_tstate - Target already allocated",
1642 0 : ahc_name(ahc));
1643 0 : tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT | M_ZERO);
1644 0 : if (tstate == NULL)
1645 0 : return (NULL);
1646 :
1647 : /*
1648 : * If we have allocated a master tstate, copy user settings from
1649 : * the master tstate (taken from SRAM or the EEPROM) for this
1650 : * channel, but reset our current and goal settings to async/narrow
1651 : * until an initiator talks to us.
1652 : */
1653 0 : if (master_tstate != NULL) {
1654 0 : memcpy(tstate, master_tstate, sizeof(*tstate));
1655 0 : memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1656 0 : tstate->ultraenb = 0;
1657 0 : for (i = 0; i < AHC_NUM_TARGETS; i++) {
1658 0 : memset(&tstate->transinfo[i].curr, 0,
1659 : sizeof(tstate->transinfo[i].curr));
1660 0 : memset(&tstate->transinfo[i].goal, 0,
1661 : sizeof(tstate->transinfo[i].goal));
1662 : }
1663 : }
1664 0 : ahc->enabled_targets[scsi_id] = tstate;
1665 0 : return (tstate);
1666 0 : }
1667 :
1668 : #ifdef AHC_TARGET_MODE
1669 : /*
1670 : * Free per target mode instance (ID we respond to as a target)
1671 : * transfer negotiation data structures.
1672 : */
1673 : static void
1674 : ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1675 : {
1676 : struct ahc_tmode_tstate *tstate;
1677 :
1678 : /*
1679 : * Don't clean up our "master" tstate.
1680 : * It has our default user settings.
1681 : */
1682 : if (((channel == 'B' && scsi_id == ahc->our_id_b)
1683 : || (channel == 'A' && scsi_id == ahc->our_id))
1684 : && force == FALSE)
1685 : return;
1686 :
1687 : if (channel == 'B')
1688 : scsi_id += 8;
1689 : tstate = ahc->enabled_targets[scsi_id];
1690 : if (tstate != NULL)
1691 : free(tstate, M_DEVBUF, 0);
1692 : ahc->enabled_targets[scsi_id] = NULL;
1693 : }
1694 : #endif
1695 :
1696 : /*
1697 : * Called when we have an active connection to a target on the bus,
1698 : * this function finds the nearest syncrate to the input period limited
1699 : * by the capabilities of the bus connectivity of and sync settings for
1700 : * the target.
1701 : */
1702 : struct ahc_syncrate *
1703 0 : ahc_devlimited_syncrate(struct ahc_softc *ahc,
1704 : struct ahc_initiator_tinfo *tinfo,
1705 : u_int *period, u_int *ppr_options, role_t role)
1706 : {
1707 : struct ahc_transinfo *transinfo;
1708 : u_int maxsync;
1709 :
1710 0 : if ((ahc->features & AHC_ULTRA2) != 0) {
1711 0 : if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1712 0 : && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1713 : maxsync = AHC_SYNCRATE_DT;
1714 0 : } else {
1715 : maxsync = AHC_SYNCRATE_ULTRA;
1716 : /* Can't do DT on an SE bus */
1717 0 : *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1718 : }
1719 0 : } else if ((ahc->features & AHC_ULTRA) != 0) {
1720 : maxsync = AHC_SYNCRATE_ULTRA;
1721 0 : } else {
1722 : maxsync = AHC_SYNCRATE_FAST;
1723 : }
1724 : /*
1725 : * Never allow a value higher than our current goal
1726 : * period otherwise we may allow a target initiated
1727 : * negotiation to go above the limit as set by the
1728 : * user. In the case of an initiator initiated
1729 : * sync negotiation, we limit based on the user
1730 : * setting. This allows the system to still accept
1731 : * incoming negotiations even if target initiated
1732 : * negotiation is not performed.
1733 : */
1734 0 : if (role == ROLE_TARGET)
1735 0 : transinfo = &tinfo->user;
1736 : else
1737 0 : transinfo = &tinfo->goal;
1738 0 : *ppr_options &= transinfo->ppr_options;
1739 0 : if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1740 0 : maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1741 0 : *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1742 0 : }
1743 0 : if (transinfo->period == 0) {
1744 0 : *period = 0;
1745 0 : *ppr_options = 0;
1746 0 : return (NULL);
1747 : }
1748 0 : *period = MAX(*period, transinfo->period);
1749 0 : return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1750 0 : }
1751 :
1752 : /*
1753 : * Look up the valid period to SCSIRATE conversion in our table.
1754 : * Return the period and offset that should be sent to the target
1755 : * if this was the beginning of an SDTR.
1756 : */
1757 : struct ahc_syncrate *
1758 0 : ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1759 : u_int *ppr_options, u_int maxsync)
1760 : {
1761 : struct ahc_syncrate *syncrate;
1762 :
1763 0 : if ((ahc->features & AHC_DT) == 0)
1764 0 : *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1765 :
1766 : /* Skip all DT only entries if DT is not available */
1767 0 : if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1768 0 : && maxsync < AHC_SYNCRATE_ULTRA2)
1769 0 : maxsync = AHC_SYNCRATE_ULTRA2;
1770 :
1771 0 : for (syncrate = &ahc_syncrates[maxsync];
1772 0 : syncrate->rate != NULL;
1773 0 : syncrate++) {
1774 :
1775 : /*
1776 : * The Ultra2 table doesn't go as low
1777 : * as for the Fast/Ultra cards.
1778 : */
1779 0 : if ((ahc->features & AHC_ULTRA2) != 0
1780 0 : && (syncrate->sxfr_u2 == 0))
1781 : break;
1782 :
1783 0 : if (*period <= syncrate->period) {
1784 : /*
1785 : * When responding to a target that requests
1786 : * sync, the requested rate may fall between
1787 : * two rates that we can output, but still be
1788 : * a rate that we can receive. Because of this,
1789 : * we want to respond to the target with
1790 : * the same rate that it sent to us even
1791 : * if the period we use to send data to it
1792 : * is lower. Only lower the response period
1793 : * if we must.
1794 : */
1795 0 : if (syncrate == &ahc_syncrates[maxsync])
1796 0 : *period = syncrate->period;
1797 :
1798 : /*
1799 : * At some speeds, we only support
1800 : * ST transfers.
1801 : */
1802 0 : if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1803 0 : *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1804 : break;
1805 : }
1806 : }
1807 :
1808 0 : if ((*period == 0)
1809 0 : || (syncrate->rate == NULL)
1810 0 : || ((ahc->features & AHC_ULTRA2) != 0
1811 0 : && (syncrate->sxfr_u2 == 0))) {
1812 : /* Use asynchronous transfers. */
1813 0 : *period = 0;
1814 : syncrate = NULL;
1815 0 : *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1816 0 : }
1817 0 : return (syncrate);
1818 : }
1819 :
1820 : /*
1821 : * Convert from an entry in our syncrate table to the SCSI equivalent
1822 : * sync "period" factor.
1823 : */
1824 : u_int
1825 0 : ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1826 : {
1827 : struct ahc_syncrate *syncrate;
1828 :
1829 0 : if ((ahc->features & AHC_ULTRA2) != 0)
1830 0 : scsirate &= SXFR_ULTRA2;
1831 : else
1832 0 : scsirate &= SXFR;
1833 :
1834 0 : syncrate = &ahc_syncrates[maxsync];
1835 0 : while (syncrate->rate != NULL) {
1836 :
1837 0 : if ((ahc->features & AHC_ULTRA2) != 0) {
1838 0 : if (syncrate->sxfr_u2 == 0)
1839 : break;
1840 0 : else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1841 0 : return (syncrate->period);
1842 0 : } else if (scsirate == (syncrate->sxfr & SXFR)) {
1843 0 : return (syncrate->period);
1844 : }
1845 0 : syncrate++;
1846 : }
1847 0 : return (0); /* async */
1848 0 : }
1849 :
1850 : /*
1851 : * Truncate the given synchronous offset to a value the
1852 : * current adapter type and syncrate are capable of.
1853 : */
1854 : void
1855 0 : ahc_validate_offset(struct ahc_softc *ahc,
1856 : struct ahc_initiator_tinfo *tinfo,
1857 : struct ahc_syncrate *syncrate,
1858 : u_int *offset, int wide, role_t role)
1859 : {
1860 : u_int maxoffset;
1861 :
1862 : /* Limit offset to what we can do */
1863 0 : if (syncrate == NULL) {
1864 : maxoffset = 0;
1865 0 : } else if ((ahc->features & AHC_ULTRA2) != 0) {
1866 : maxoffset = MAX_OFFSET_ULTRA2;
1867 0 : } else {
1868 0 : if (wide)
1869 0 : maxoffset = MAX_OFFSET_16BIT;
1870 : else
1871 : maxoffset = MAX_OFFSET_8BIT;
1872 : }
1873 0 : *offset = MIN(*offset, maxoffset);
1874 0 : if (tinfo != NULL) {
1875 0 : if (role == ROLE_TARGET)
1876 0 : *offset = MIN(*offset, tinfo->user.offset);
1877 : else
1878 0 : *offset = MIN(*offset, tinfo->goal.offset);
1879 : }
1880 0 : }
1881 :
1882 : /*
1883 : * Truncate the given transfer width parameter to a value the
1884 : * current adapter type is capable of.
1885 : */
1886 : void
1887 0 : ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1888 : u_int *bus_width, role_t role)
1889 : {
1890 0 : switch (*bus_width) {
1891 : default:
1892 0 : if (ahc->features & AHC_WIDE) {
1893 : /* Respond Wide */
1894 0 : *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1895 0 : break;
1896 : }
1897 : /* FALLTHROUGH */
1898 : case MSG_EXT_WDTR_BUS_8_BIT:
1899 0 : *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1900 0 : break;
1901 : }
1902 0 : if (tinfo != NULL) {
1903 0 : if (role == ROLE_TARGET)
1904 0 : *bus_width = MIN(tinfo->user.width, *bus_width);
1905 : else
1906 0 : *bus_width = MIN(tinfo->goal.width, *bus_width);
1907 : }
1908 0 : }
1909 :
1910 : /*
1911 : * Update the bitmask of targets for which the controller should
1912 : * negotiate with at the next convenient opportunity. This currently
1913 : * means the next time we send the initial identify messages for
1914 : * a new transaction.
1915 : */
1916 : int
1917 0 : ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1918 : struct ahc_tmode_tstate *tstate,
1919 : struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1920 : {
1921 : u_int auto_negotiate_orig;
1922 :
1923 0 : auto_negotiate_orig = tstate->auto_negotiate;
1924 0 : if (neg_type == AHC_NEG_ALWAYS) {
1925 : /*
1926 : * Force our "current" settings to be
1927 : * unknown so that unless a bus reset
1928 : * occurs the need to renegotiate is
1929 : * recorded persistently.
1930 : */
1931 0 : if ((ahc->features & AHC_WIDE) != 0)
1932 0 : tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1933 0 : tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1934 0 : tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1935 0 : }
1936 0 : if (tinfo->curr.period != tinfo->goal.period
1937 0 : || tinfo->curr.width != tinfo->goal.width
1938 0 : || tinfo->curr.offset != tinfo->goal.offset
1939 0 : || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1940 0 : || (neg_type == AHC_NEG_IF_NON_ASYNC
1941 0 : && (tinfo->goal.offset != 0
1942 0 : || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1943 0 : || tinfo->goal.ppr_options != 0)))
1944 0 : tstate->auto_negotiate |= devinfo->target_mask;
1945 : else
1946 0 : tstate->auto_negotiate &= ~devinfo->target_mask;
1947 :
1948 0 : return (auto_negotiate_orig != tstate->auto_negotiate);
1949 : }
1950 :
1951 : /*
1952 : * Update the user/goal/curr tables of synchronous negotiation
1953 : * parameters as well as, in the case of a current or active update,
1954 : * any data structures on the host controller. In the case of an
1955 : * active update, the specified target is currently talking to us on
1956 : * the bus, so the transfer parameter update must take effect
1957 : * immediately.
1958 : */
1959 : void
1960 0 : ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1961 : struct ahc_syncrate *syncrate, u_int period,
1962 : u_int offset, u_int ppr_options, u_int type, int paused)
1963 : {
1964 : struct ahc_initiator_tinfo *tinfo;
1965 0 : struct ahc_tmode_tstate *tstate;
1966 : u_int old_period;
1967 : u_int old_offset;
1968 : u_int old_ppr;
1969 : int active;
1970 : int update_needed;
1971 :
1972 0 : active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1973 : update_needed = 0;
1974 :
1975 0 : if (syncrate == NULL) {
1976 : period = 0;
1977 : offset = 0;
1978 0 : }
1979 :
1980 0 : tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1981 0 : devinfo->target, &tstate);
1982 :
1983 0 : if ((type & AHC_TRANS_USER) != 0) {
1984 0 : tinfo->user.period = period;
1985 0 : tinfo->user.offset = offset;
1986 0 : tinfo->user.ppr_options = ppr_options;
1987 0 : }
1988 :
1989 0 : if ((type & AHC_TRANS_GOAL) != 0) {
1990 0 : tinfo->goal.period = period;
1991 0 : tinfo->goal.offset = offset;
1992 0 : tinfo->goal.ppr_options = ppr_options;
1993 0 : }
1994 :
1995 0 : old_period = tinfo->curr.period;
1996 0 : old_offset = tinfo->curr.offset;
1997 0 : old_ppr = tinfo->curr.ppr_options;
1998 :
1999 0 : if ((type & AHC_TRANS_CUR) != 0
2000 0 : && (old_period != period
2001 0 : || old_offset != offset
2002 0 : || old_ppr != ppr_options)) {
2003 : u_int scsirate;
2004 :
2005 : update_needed++;
2006 0 : scsirate = tinfo->scsirate;
2007 0 : if ((ahc->features & AHC_ULTRA2) != 0) {
2008 :
2009 0 : scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
2010 0 : if (syncrate != NULL) {
2011 0 : scsirate |= syncrate->sxfr_u2;
2012 0 : if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
2013 0 : scsirate |= ENABLE_CRC;
2014 : else
2015 0 : scsirate |= SINGLE_EDGE;
2016 : }
2017 : } else {
2018 :
2019 0 : scsirate &= ~(SXFR|SOFS);
2020 : /*
2021 : * Ensure Ultra mode is set properly for
2022 : * this target.
2023 : */
2024 0 : tstate->ultraenb &= ~devinfo->target_mask;
2025 0 : if (syncrate != NULL) {
2026 0 : if (syncrate->sxfr & ULTRA_SXFR) {
2027 0 : tstate->ultraenb |=
2028 0 : devinfo->target_mask;
2029 0 : }
2030 0 : scsirate |= syncrate->sxfr & SXFR;
2031 0 : scsirate |= offset & SOFS;
2032 0 : }
2033 0 : if (active) {
2034 : u_int sxfrctl0;
2035 :
2036 0 : sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
2037 0 : sxfrctl0 &= ~FAST20;
2038 0 : if (tstate->ultraenb & devinfo->target_mask)
2039 0 : sxfrctl0 |= FAST20;
2040 0 : ahc_outb(ahc, SXFRCTL0, sxfrctl0);
2041 0 : }
2042 : }
2043 0 : if (active) {
2044 0 : ahc_outb(ahc, SCSIRATE, scsirate);
2045 0 : if ((ahc->features & AHC_ULTRA2) != 0)
2046 0 : ahc_outb(ahc, SCSIOFFSET, offset);
2047 : }
2048 :
2049 0 : tinfo->scsirate = scsirate;
2050 0 : tinfo->curr.period = period;
2051 0 : tinfo->curr.offset = offset;
2052 0 : tinfo->curr.ppr_options = ppr_options;
2053 :
2054 0 : ahc_send_async(ahc, devinfo->channel, devinfo->target,
2055 : CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2056 : if (1 /*bootverbose*/) {
2057 0 : if (offset != 0) {
2058 0 : printf("%s: target %d synchronous at %sMHz%s, "
2059 : "offset = 0x%x\n", ahc_name(ahc),
2060 0 : devinfo->target, syncrate->rate,
2061 0 : (ppr_options & MSG_EXT_PPR_DT_REQ)
2062 : ? " DT" : "", offset);
2063 0 : } else {
2064 0 : printf("%s: target %d using "
2065 : "asynchronous transfers\n",
2066 : ahc_name(ahc), devinfo->target);
2067 : }
2068 : }
2069 0 : }
2070 :
2071 0 : update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2072 : tinfo, AHC_NEG_TO_GOAL);
2073 :
2074 0 : if (update_needed)
2075 0 : ahc_update_pending_scbs(ahc);
2076 0 : }
2077 :
2078 : /*
2079 : * Update the user/goal/curr tables of wide negotiation
2080 : * parameters as well as, in the case of a current or active update,
2081 : * any data structures on the host controller. In the case of an
2082 : * active update, the specified target is currently talking to us on
2083 : * the bus, so the transfer parameter update must take effect
2084 : * immediately.
2085 : */
2086 : void
2087 0 : ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2088 : u_int width, u_int type, int paused)
2089 : {
2090 : struct ahc_initiator_tinfo *tinfo;
2091 0 : struct ahc_tmode_tstate *tstate;
2092 : u_int oldwidth;
2093 : int active;
2094 : int update_needed;
2095 :
2096 0 : active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2097 : update_needed = 0;
2098 0 : tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2099 0 : devinfo->target, &tstate);
2100 :
2101 0 : if ((type & AHC_TRANS_USER) != 0)
2102 0 : tinfo->user.width = width;
2103 :
2104 0 : if ((type & AHC_TRANS_GOAL) != 0)
2105 0 : tinfo->goal.width = width;
2106 :
2107 0 : oldwidth = tinfo->curr.width;
2108 0 : if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2109 : u_int scsirate;
2110 :
2111 : update_needed++;
2112 0 : scsirate = tinfo->scsirate;
2113 0 : scsirate &= ~WIDEXFER;
2114 0 : if (width == MSG_EXT_WDTR_BUS_16_BIT)
2115 0 : scsirate |= WIDEXFER;
2116 :
2117 0 : tinfo->scsirate = scsirate;
2118 :
2119 0 : if (active)
2120 0 : ahc_outb(ahc, SCSIRATE, scsirate);
2121 :
2122 0 : tinfo->curr.width = width;
2123 :
2124 0 : ahc_send_async(ahc, devinfo->channel, devinfo->target,
2125 : CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2126 : if (1 /*bootverbose*/) {
2127 0 : printf("%s: target %d using %dbit transfers\n",
2128 0 : ahc_name(ahc), devinfo->target,
2129 0 : 8 * (0x01 << width));
2130 : }
2131 0 : }
2132 :
2133 0 : update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2134 : tinfo, AHC_NEG_TO_GOAL);
2135 0 : if (update_needed)
2136 0 : ahc_update_pending_scbs(ahc);
2137 0 : }
2138 :
2139 : /*
2140 : * Update the current state of tagged queuing for a given target.
2141 : */
2142 : void
2143 0 : ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2144 : ahc_queue_alg alg)
2145 : {
2146 0 : ahc_platform_set_tags(ahc, devinfo, alg);
2147 0 : ahc_send_async(ahc, devinfo->channel, devinfo->target,
2148 0 : devinfo->lun, AC_TRANSFER_NEG, &alg);
2149 0 : }
2150 :
2151 : /*
2152 : * When the transfer settings for a connection change, update any
2153 : * in-transit SCBs to contain the new data so the hardware will
2154 : * be set correctly during future (re)selections.
2155 : */
2156 : static void
2157 0 : ahc_update_pending_scbs(struct ahc_softc *ahc)
2158 : {
2159 : struct scb *pending_scb;
2160 : int pending_scb_count;
2161 : int i;
2162 : int paused;
2163 : u_int saved_scbptr;
2164 :
2165 : /*
2166 : * Traverse the pending SCB list and ensure that all of the
2167 : * SCBs there have the proper settings.
2168 : */
2169 : pending_scb_count = 0;
2170 0 : LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2171 0 : struct ahc_devinfo devinfo;
2172 : struct hardware_scb *pending_hscb;
2173 : struct ahc_initiator_tinfo *tinfo;
2174 0 : struct ahc_tmode_tstate *tstate;
2175 :
2176 0 : ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2177 0 : tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2178 0 : devinfo.our_scsiid,
2179 0 : devinfo.target, &tstate);
2180 0 : pending_hscb = pending_scb->hscb;
2181 0 : pending_hscb->control &= ~ULTRAENB;
2182 0 : if ((tstate->ultraenb & devinfo.target_mask) != 0)
2183 0 : pending_hscb->control |= ULTRAENB;
2184 0 : pending_hscb->scsirate = tinfo->scsirate;
2185 0 : pending_hscb->scsioffset = tinfo->curr.offset;
2186 0 : if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2187 0 : && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2188 0 : pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2189 0 : pending_hscb->control &= ~MK_MESSAGE;
2190 0 : }
2191 0 : ahc_sync_scb(ahc, pending_scb,
2192 : BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2193 0 : pending_scb_count++;
2194 0 : }
2195 :
2196 0 : if (pending_scb_count == 0)
2197 0 : return;
2198 :
2199 0 : if (ahc_is_paused(ahc)) {
2200 : paused = 1;
2201 0 : } else {
2202 : paused = 0;
2203 0 : ahc_pause(ahc);
2204 : }
2205 :
2206 0 : saved_scbptr = ahc_inb(ahc, SCBPTR);
2207 : /* Ensure that the hscbs down on the card match the new information */
2208 0 : for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2209 : struct hardware_scb *pending_hscb;
2210 : u_int control;
2211 : u_int scb_tag;
2212 :
2213 0 : ahc_outb(ahc, SCBPTR, i);
2214 0 : scb_tag = ahc_inb(ahc, SCB_TAG);
2215 0 : pending_scb = ahc_lookup_scb(ahc, scb_tag);
2216 0 : if (pending_scb == NULL)
2217 0 : continue;
2218 :
2219 0 : pending_hscb = pending_scb->hscb;
2220 0 : control = ahc_inb(ahc, SCB_CONTROL);
2221 0 : control &= ~(ULTRAENB|MK_MESSAGE);
2222 0 : control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2223 0 : ahc_outb(ahc, SCB_CONTROL, control);
2224 0 : ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2225 0 : ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2226 0 : }
2227 0 : ahc_outb(ahc, SCBPTR, saved_scbptr);
2228 :
2229 0 : if (paused == 0)
2230 0 : ahc_unpause(ahc);
2231 0 : }
2232 :
2233 : /**************************** Pathing Information *****************************/
2234 : static void
2235 0 : ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2236 : {
2237 : u_int saved_scsiid;
2238 : role_t role;
2239 : int our_id;
2240 :
2241 0 : if (ahc_inb(ahc, SSTAT0) & TARGET)
2242 0 : role = ROLE_TARGET;
2243 : else
2244 : role = ROLE_INITIATOR;
2245 :
2246 0 : if (role == ROLE_TARGET
2247 0 : && (ahc->features & AHC_MULTI_TID) != 0
2248 0 : && (ahc_inb(ahc, SEQ_FLAGS)
2249 0 : & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2250 : /* We were selected, so pull our id from TARGIDIN */
2251 0 : our_id = ahc_inb(ahc, TARGIDIN) & OID;
2252 0 : } else if ((ahc->features & AHC_ULTRA2) != 0)
2253 0 : our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2254 : else
2255 0 : our_id = ahc_inb(ahc, SCSIID) & OID;
2256 :
2257 0 : saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2258 0 : ahc_compile_devinfo(devinfo,
2259 : our_id,
2260 0 : SCSIID_TARGET(ahc, saved_scsiid),
2261 0 : ahc_inb(ahc, SAVED_LUN),
2262 0 : SCSIID_CHANNEL(ahc, saved_scsiid),
2263 : role);
2264 0 : }
2265 :
2266 : struct ahc_phase_table_entry*
2267 0 : ahc_lookup_phase_entry(int phase)
2268 : {
2269 : struct ahc_phase_table_entry *entry;
2270 : struct ahc_phase_table_entry *last_entry;
2271 :
2272 : /*
2273 : * num_phases doesn't include the default entry which
2274 : * will be returned if the phase doesn't match.
2275 : */
2276 : last_entry = &ahc_phase_table[num_phases];
2277 0 : for (entry = ahc_phase_table; entry < last_entry; entry++) {
2278 0 : if (phase == entry->phase)
2279 : break;
2280 : }
2281 0 : return (entry);
2282 : }
2283 :
2284 : void
2285 0 : ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2286 : u_int lun, char channel, role_t role)
2287 : {
2288 0 : devinfo->our_scsiid = our_id;
2289 0 : devinfo->target = target;
2290 0 : devinfo->lun = lun;
2291 0 : devinfo->target_offset = target;
2292 0 : devinfo->channel = channel;
2293 0 : devinfo->role = role;
2294 0 : if (channel == 'B')
2295 0 : devinfo->target_offset += 8;
2296 0 : devinfo->target_mask = (0x01 << devinfo->target_offset);
2297 0 : }
2298 :
2299 : void
2300 0 : ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2301 : {
2302 0 : printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2303 0 : devinfo->target, devinfo->lun);
2304 0 : }
2305 :
2306 : void
2307 0 : ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2308 : struct scb *scb)
2309 : {
2310 : role_t role;
2311 : int our_id;
2312 :
2313 0 : our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2314 : role = ROLE_INITIATOR;
2315 0 : if ((scb->flags & SCB_TARGET_SCB) != 0)
2316 : role = ROLE_TARGET;
2317 0 : ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2318 0 : SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2319 0 : }
2320 :
2321 :
2322 : /************************ Message Phase Processing ****************************/
2323 : static void
2324 0 : ahc_assert_atn(struct ahc_softc *ahc)
2325 : {
2326 : u_int scsisigo;
2327 :
2328 : scsisigo = ATNO;
2329 0 : if ((ahc->features & AHC_DT) == 0)
2330 0 : scsisigo |= ahc_inb(ahc, SCSISIGI);
2331 0 : ahc_outb(ahc, SCSISIGO, scsisigo);
2332 0 : }
2333 :
2334 : /*
2335 : * When an initiator transaction with the MK_MESSAGE flag either reconnects
2336 : * or enters the initial message out phase, we are interrupted. Fill our
2337 : * outgoing message buffer with the appropriate message and begin handing
2338 : * the message phase(s) manually.
2339 : */
2340 : static void
2341 0 : ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2342 : struct scb *scb)
2343 : {
2344 : /*
2345 : * To facilitate adding multiple messages together,
2346 : * each routine should increment the index and len
2347 : * variables instead of setting them explicitly.
2348 : */
2349 0 : ahc->msgout_index = 0;
2350 0 : ahc->msgout_len = 0;
2351 :
2352 0 : if ((scb->flags & SCB_DEVICE_RESET) == 0
2353 0 : && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2354 : u_int identify_msg;
2355 :
2356 0 : identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2357 0 : if ((scb->hscb->control & DISCENB) != 0)
2358 0 : identify_msg |= MSG_IDENTIFY_DISCFLAG;
2359 0 : ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2360 0 : ahc->msgout_len++;
2361 :
2362 0 : if ((scb->hscb->control & TAG_ENB) != 0) {
2363 0 : ahc->msgout_buf[ahc->msgout_index++] =
2364 0 : scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2365 0 : ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2366 0 : ahc->msgout_len += 2;
2367 0 : }
2368 0 : }
2369 :
2370 0 : if (scb->flags & SCB_DEVICE_RESET) {
2371 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2372 0 : ahc->msgout_len++;
2373 0 : ahc_print_path(ahc, scb);
2374 0 : printf("Bus Device Reset Message Sent\n");
2375 : /*
2376 : * Clear our selection hardware in advance of
2377 : * the busfree. We may have an entry in the waiting
2378 : * Q for this target, and we don't want to go about
2379 : * selecting while we handle the busfree and blow it
2380 : * away.
2381 : */
2382 0 : ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2383 0 : } else if ((scb->flags & SCB_ABORT) != 0) {
2384 0 : if ((scb->hscb->control & TAG_ENB) != 0)
2385 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2386 : else
2387 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2388 0 : ahc->msgout_len++;
2389 0 : ahc_print_path(ahc, scb);
2390 0 : printf("Abort%s Message Sent\n",
2391 0 : (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2392 : /*
2393 : * Clear our selection hardware in advance of
2394 : * the busfree. We may have an entry in the waiting
2395 : * Q for this target, and we don't want to go about
2396 : * selecting while we handle the busfree and blow it
2397 : * away.
2398 : */
2399 0 : ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2400 0 : } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2401 0 : ahc_build_transfer_msg(ahc, devinfo);
2402 : } else {
2403 0 : printf("ahc_intr: AWAITING_MSG for an SCB that "
2404 : "does not have a waiting message\n");
2405 0 : printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2406 0 : devinfo->target_mask);
2407 0 : panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2408 0 : "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2409 0 : ahc_inb(ahc, MSG_OUT), scb->flags);
2410 : }
2411 :
2412 : /*
2413 : * Clear the MK_MESSAGE flag from the SCB so we aren't
2414 : * asked to send this message again.
2415 : */
2416 0 : ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2417 0 : scb->hscb->control &= ~MK_MESSAGE;
2418 0 : ahc->msgout_index = 0;
2419 0 : ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2420 0 : }
2421 :
2422 : /*
2423 : * Build an appropriate transfer negotiation message for the
2424 : * currently active target.
2425 : */
2426 : static void
2427 0 : ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2428 : {
2429 : /*
2430 : * We need to initiate transfer negotiations.
2431 : * If our current and goal settings are identical,
2432 : * we want to renegotiate due to a check condition.
2433 : */
2434 : struct ahc_initiator_tinfo *tinfo;
2435 0 : struct ahc_tmode_tstate *tstate;
2436 : struct ahc_syncrate *rate;
2437 : int dowide;
2438 : int dosync;
2439 : int doppr;
2440 0 : u_int period;
2441 0 : u_int ppr_options;
2442 0 : u_int offset;
2443 :
2444 0 : tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2445 0 : devinfo->target, &tstate);
2446 : /*
2447 : * Filter our period based on the current connection.
2448 : * If we can't perform DT transfers on this segment (not in LVD
2449 : * mode for instance), then our decision to issue a PPR message
2450 : * may change.
2451 : */
2452 0 : period = tinfo->goal.period;
2453 0 : offset = tinfo->goal.offset;
2454 0 : ppr_options = tinfo->goal.ppr_options;
2455 : /* Target initiated PPR is not allowed in the SCSI spec */
2456 0 : if (devinfo->role == ROLE_TARGET)
2457 : ppr_options = 0;
2458 0 : rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2459 0 : &ppr_options, devinfo->role);
2460 0 : dowide = tinfo->curr.width != tinfo->goal.width;
2461 0 : dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2462 : /*
2463 : * Only use PPR if we have options that need it, even if the device
2464 : * claims to support it. There might be an expander in the way
2465 : * that doesn't.
2466 : */
2467 0 : doppr = ppr_options != 0;
2468 :
2469 0 : if (!dowide && !dosync && !doppr) {
2470 0 : dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2471 0 : dosync = tinfo->goal.offset != 0;
2472 0 : }
2473 :
2474 0 : if (!dowide && !dosync && !doppr) {
2475 : /*
2476 : * Force async with a WDTR message if we have a wide bus,
2477 : * or just issue an SDTR with a 0 offset.
2478 : */
2479 0 : if ((ahc->features & AHC_WIDE) != 0)
2480 0 : dowide = 1;
2481 : else
2482 : dosync = 1;
2483 :
2484 : if (bootverbose) {
2485 : ahc_print_devinfo(ahc, devinfo);
2486 : printf("Ensuring async\n");
2487 : }
2488 : }
2489 :
2490 : /* Target initiated PPR is not allowed in the SCSI spec */
2491 0 : if (devinfo->role == ROLE_TARGET)
2492 0 : doppr = 0;
2493 :
2494 : /*
2495 : * Both the PPR message and SDTR message require the
2496 : * goal syncrate to be limited to what the target device
2497 : * is capable of handling (based on whether an LVD->SE
2498 : * expander is on the bus), so combine these two cases.
2499 : * Regardless, guarantee that if we are using WDTR and SDTR
2500 : * messages that WDTR comes first.
2501 : */
2502 0 : if (doppr || (dosync && !dowide)) {
2503 :
2504 0 : offset = tinfo->goal.offset;
2505 0 : ahc_validate_offset(ahc, tinfo, rate, &offset,
2506 0 : doppr ? tinfo->goal.width
2507 0 : : tinfo->curr.width,
2508 0 : devinfo->role);
2509 0 : if (doppr) {
2510 0 : ahc_construct_ppr(ahc, devinfo, period, offset,
2511 0 : tinfo->goal.width, ppr_options);
2512 0 : } else {
2513 0 : ahc_construct_sdtr(ahc, devinfo, period, offset);
2514 : }
2515 : } else {
2516 0 : ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2517 : }
2518 0 : }
2519 :
2520 : /*
2521 : * Build a synchronous negotiation message in our message
2522 : * buffer based on the input parameters.
2523 : */
2524 : static void
2525 0 : ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2526 : u_int period, u_int offset)
2527 : {
2528 0 : if (offset == 0)
2529 0 : period = AHC_ASYNC_XFER_PERIOD;
2530 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2531 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2532 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2533 0 : ahc->msgout_buf[ahc->msgout_index++] = period;
2534 0 : ahc->msgout_buf[ahc->msgout_index++] = offset;
2535 0 : ahc->msgout_len += 5;
2536 : if (bootverbose) {
2537 : printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2538 : ahc_name(ahc), devinfo->channel, devinfo->target,
2539 : devinfo->lun, period, offset);
2540 : }
2541 0 : }
2542 :
2543 : /*
2544 : * Build a wide negotiation message in our message
2545 : * buffer based on the input parameters.
2546 : */
2547 : static void
2548 0 : ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2549 : u_int bus_width)
2550 : {
2551 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2552 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2553 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2554 0 : ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2555 0 : ahc->msgout_len += 4;
2556 : if (bootverbose) {
2557 : printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2558 : ahc_name(ahc), devinfo->channel, devinfo->target,
2559 : devinfo->lun, bus_width);
2560 : }
2561 0 : }
2562 :
2563 : /*
2564 : * Build a parallel protocol request message in our message
2565 : * buffer based on the input parameters.
2566 : */
2567 : static void
2568 0 : ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2569 : u_int period, u_int offset, u_int bus_width,
2570 : u_int ppr_options)
2571 : {
2572 0 : if (offset == 0)
2573 0 : period = AHC_ASYNC_XFER_PERIOD;
2574 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2575 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2576 0 : ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2577 0 : ahc->msgout_buf[ahc->msgout_index++] = period;
2578 0 : ahc->msgout_buf[ahc->msgout_index++] = 0;
2579 0 : ahc->msgout_buf[ahc->msgout_index++] = offset;
2580 0 : ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2581 0 : ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2582 0 : ahc->msgout_len += 8;
2583 : if (bootverbose) {
2584 : printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2585 : "offset %x, ppr_options %x\n", ahc_name(ahc),
2586 : devinfo->channel, devinfo->target, devinfo->lun,
2587 : bus_width, period, offset, ppr_options);
2588 : }
2589 0 : }
2590 :
2591 : /*
2592 : * Clear any active message state.
2593 : */
2594 : static void
2595 0 : ahc_clear_msg_state(struct ahc_softc *ahc)
2596 : {
2597 0 : ahc->msgout_len = 0;
2598 0 : ahc->msgin_index = 0;
2599 0 : ahc->msg_type = MSG_TYPE_NONE;
2600 0 : if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2601 : /*
2602 : * The target didn't care to respond to our
2603 : * message request, so clear ATN.
2604 : */
2605 0 : ahc_outb(ahc, CLRSINT1, CLRATNO);
2606 0 : }
2607 0 : ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2608 0 : ahc_outb(ahc, SEQ_FLAGS2,
2609 : ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2610 0 : }
2611 :
2612 : static void
2613 0 : ahc_handle_proto_violation(struct ahc_softc *ahc)
2614 : {
2615 0 : struct ahc_devinfo devinfo;
2616 : struct scb *scb;
2617 : u_int scbid;
2618 : u_int seq_flags;
2619 : u_int curphase;
2620 : u_int lastphase;
2621 : int found;
2622 :
2623 0 : ahc_fetch_devinfo(ahc, &devinfo);
2624 0 : scbid = ahc_inb(ahc, SCB_TAG);
2625 0 : scb = ahc_lookup_scb(ahc, scbid);
2626 0 : seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2627 0 : curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2628 0 : lastphase = ahc_inb(ahc, LASTPHASE);
2629 0 : if ((seq_flags & NOT_IDENTIFIED) != 0) {
2630 :
2631 : /*
2632 : * The reconnecting target either did not send an
2633 : * identify message, or did, but we didn't find an SCB
2634 : * to match.
2635 : */
2636 0 : ahc_print_devinfo(ahc, &devinfo);
2637 0 : printf("Target did not send an IDENTIFY message. "
2638 : "LASTPHASE = 0x%x.\n", lastphase);
2639 : scb = NULL;
2640 0 : } else if (scb == NULL) {
2641 : /*
2642 : * We don't seem to have an SCB active for this
2643 : * transaction. Print an error and reset the bus.
2644 : */
2645 0 : ahc_print_devinfo(ahc, &devinfo);
2646 0 : printf("No SCB found during protocol violation\n");
2647 0 : goto proto_violation_reset;
2648 : } else {
2649 0 : ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2650 0 : if ((seq_flags & NO_CDB_SENT) != 0) {
2651 0 : ahc_print_path(ahc, scb);
2652 0 : printf("No or incomplete CDB sent to device.\n");
2653 0 : } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2654 : /*
2655 : * The target never bothered to provide status to
2656 : * us prior to completing the command. Since we don't
2657 : * know the disposition of this command, we must attempt
2658 : * to abort it. Assert ATN and prepare to send an abort
2659 : * message.
2660 : */
2661 : ahc_print_path(ahc, scb);
2662 0 : printf("Completed command without status.\n");
2663 0 : } else {
2664 : ahc_print_path(ahc, scb);
2665 0 : printf("Unknown protocol violation.\n");
2666 0 : ahc_dump_card_state(ahc);
2667 : }
2668 : }
2669 0 : if ((lastphase & ~P_DATAIN_DT) == 0
2670 0 : || lastphase == P_COMMAND) {
2671 : proto_violation_reset:
2672 : /*
2673 : * Target either went directly to data/command
2674 : * phase or didn't respond to our ATN.
2675 : * The only safe thing to do is to blow
2676 : * it away with a bus reset.
2677 : */
2678 0 : found = ahc_reset_channel(ahc, 'A', TRUE);
2679 0 : printf("%s: Issued Channel %c Bus Reset. "
2680 0 : "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2681 0 : } else {
2682 : /*
2683 : * Leave the selection hardware off in case
2684 : * this abort attempt will affect yet to
2685 : * be sent commands.
2686 : */
2687 0 : ahc_outb(ahc, SCSISEQ,
2688 : ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2689 0 : ahc_assert_atn(ahc);
2690 0 : ahc_outb(ahc, MSG_OUT, HOST_MSG);
2691 0 : if (scb == NULL) {
2692 0 : ahc_print_devinfo(ahc, &devinfo);
2693 0 : ahc->msgout_buf[0] = MSG_ABORT_TASK;
2694 0 : ahc->msgout_len = 1;
2695 0 : ahc->msgout_index = 0;
2696 0 : ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2697 0 : } else {
2698 0 : ahc_print_path(ahc, scb);
2699 0 : scb->flags |= SCB_ABORT;
2700 : }
2701 0 : printf("Protocol violation %s. Attempting to abort.\n",
2702 0 : ahc_lookup_phase_entry(curphase)->phasemsg);
2703 : }
2704 0 : }
2705 :
2706 : /*
2707 : * Manual message loop handler.
2708 : */
2709 : static void
2710 0 : ahc_handle_message_phase(struct ahc_softc *ahc)
2711 : {
2712 0 : struct ahc_devinfo devinfo;
2713 : u_int bus_phase;
2714 : int end_session;
2715 :
2716 0 : ahc_fetch_devinfo(ahc, &devinfo);
2717 : end_session = FALSE;
2718 0 : bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2719 :
2720 : reswitch:
2721 0 : switch (ahc->msg_type) {
2722 : case MSG_TYPE_INITIATOR_MSGOUT:
2723 : {
2724 : int lastbyte;
2725 : int phasemis;
2726 : int msgdone;
2727 :
2728 0 : if (ahc->msgout_len == 0)
2729 0 : panic("HOST_MSG_LOOP interrupt with no active message");
2730 :
2731 : #ifdef AHC_DEBUG
2732 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2733 : ahc_print_devinfo(ahc, &devinfo);
2734 : printf("INITIATOR_MSG_OUT");
2735 : }
2736 : #endif
2737 0 : phasemis = bus_phase != P_MESGOUT;
2738 0 : if (phasemis) {
2739 : #ifdef AHC_DEBUG
2740 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2741 : printf(" PHASEMIS %s\n",
2742 : ahc_lookup_phase_entry(bus_phase)
2743 : ->phasemsg);
2744 : }
2745 : #endif
2746 0 : if (bus_phase == P_MESGIN) {
2747 : /*
2748 : * Change gears and see if
2749 : * this messages is of interest to
2750 : * us or should be passed back to
2751 : * the sequencer.
2752 : */
2753 0 : ahc_outb(ahc, CLRSINT1, CLRATNO);
2754 0 : ahc->send_msg_perror = FALSE;
2755 0 : ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2756 0 : ahc->msgin_index = 0;
2757 0 : goto reswitch;
2758 : }
2759 : end_session = TRUE;
2760 0 : break;
2761 : }
2762 :
2763 0 : if (ahc->send_msg_perror) {
2764 0 : ahc_outb(ahc, CLRSINT1, CLRATNO);
2765 0 : ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2766 : #ifdef AHC_DEBUG
2767 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2768 : printf(" byte 0x%x\n", ahc->send_msg_perror);
2769 : #endif
2770 0 : ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2771 0 : break;
2772 : }
2773 :
2774 0 : msgdone = ahc->msgout_index == ahc->msgout_len;
2775 0 : if (msgdone) {
2776 : /*
2777 : * The target has requested a retry.
2778 : * Re-assert ATN, reset our message index to
2779 : * 0, and try again.
2780 : */
2781 0 : ahc->msgout_index = 0;
2782 0 : ahc_assert_atn(ahc);
2783 0 : }
2784 :
2785 0 : lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2786 0 : if (lastbyte) {
2787 : /* Last byte is signified by dropping ATN */
2788 0 : ahc_outb(ahc, CLRSINT1, CLRATNO);
2789 0 : }
2790 :
2791 : /*
2792 : * Clear our interrupt status and present
2793 : * the next byte on the bus.
2794 : */
2795 0 : ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2796 : #ifdef AHC_DEBUG
2797 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2798 : printf(" byte 0x%x\n",
2799 : ahc->msgout_buf[ahc->msgout_index]);
2800 : #endif
2801 0 : ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2802 0 : break;
2803 : }
2804 : case MSG_TYPE_INITIATOR_MSGIN:
2805 : {
2806 : int phasemis;
2807 : int message_done;
2808 :
2809 : #ifdef AHC_DEBUG
2810 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2811 : ahc_print_devinfo(ahc, &devinfo);
2812 : printf("INITIATOR_MSG_IN");
2813 : }
2814 : #endif
2815 0 : phasemis = bus_phase != P_MESGIN;
2816 0 : if (phasemis) {
2817 : #ifdef AHC_DEBUG
2818 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2819 : printf(" PHASEMIS %s\n",
2820 : ahc_lookup_phase_entry(bus_phase)
2821 : ->phasemsg);
2822 : }
2823 : #endif
2824 0 : ahc->msgin_index = 0;
2825 0 : if (bus_phase == P_MESGOUT
2826 0 : && (ahc->send_msg_perror == TRUE
2827 0 : || (ahc->msgout_len != 0
2828 0 : && ahc->msgout_index == 0))) {
2829 0 : ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2830 0 : goto reswitch;
2831 : }
2832 : end_session = TRUE;
2833 0 : break;
2834 : }
2835 :
2836 : /* Pull the byte in without acking it */
2837 0 : ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2838 : #ifdef AHC_DEBUG
2839 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2840 : printf(" byte 0x%x\n",
2841 : ahc->msgin_buf[ahc->msgin_index]);
2842 : #endif
2843 :
2844 0 : message_done = ahc_parse_msg(ahc, &devinfo);
2845 :
2846 0 : if (message_done) {
2847 : /*
2848 : * Clear our incoming message buffer in case there
2849 : * is another message following this one.
2850 : */
2851 0 : ahc->msgin_index = 0;
2852 :
2853 : /*
2854 : * If this message illicited a response,
2855 : * assert ATN so the target takes us to the
2856 : * message out phase.
2857 : */
2858 0 : if (ahc->msgout_len != 0) {
2859 : #ifdef AHC_DEBUG
2860 : if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2861 : ahc_print_devinfo(ahc, &devinfo);
2862 : printf("Asserting ATN for response\n");
2863 : }
2864 : #endif
2865 0 : ahc_assert_atn(ahc);
2866 0 : }
2867 : } else
2868 0 : ahc->msgin_index++;
2869 :
2870 0 : if (message_done == MSGLOOP_TERMINATED) {
2871 : end_session = TRUE;
2872 0 : } else {
2873 : /* Ack the byte */
2874 0 : ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2875 0 : ahc_inb(ahc, SCSIDATL);
2876 : }
2877 0 : break;
2878 : }
2879 : case MSG_TYPE_TARGET_MSGIN:
2880 : {
2881 : int msgdone;
2882 : int msgout_request;
2883 :
2884 0 : if (ahc->msgout_len == 0)
2885 0 : panic("Target MSGIN with no active message");
2886 :
2887 : /*
2888 : * If we interrupted a mesgout session, the initiator
2889 : * will not know this until our first REQ. So, we
2890 : * only honor mesgout requests after we've sent our
2891 : * first byte.
2892 : */
2893 0 : if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2894 0 : && ahc->msgout_index > 0)
2895 0 : msgout_request = TRUE;
2896 : else
2897 : msgout_request = FALSE;
2898 :
2899 0 : if (msgout_request) {
2900 :
2901 : /*
2902 : * Change gears and see if
2903 : * this messages is of interest to
2904 : * us or should be passed back to
2905 : * the sequencer.
2906 : */
2907 0 : ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2908 0 : ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2909 0 : ahc->msgin_index = 0;
2910 : /* Dummy read to REQ for first byte */
2911 0 : ahc_inb(ahc, SCSIDATL);
2912 0 : ahc_outb(ahc, SXFRCTL0,
2913 : ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2914 0 : break;
2915 : }
2916 :
2917 0 : msgdone = ahc->msgout_index == ahc->msgout_len;
2918 0 : if (msgdone) {
2919 0 : ahc_outb(ahc, SXFRCTL0,
2920 : ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2921 : end_session = TRUE;
2922 0 : break;
2923 : }
2924 :
2925 : /*
2926 : * Present the next byte on the bus.
2927 : */
2928 0 : ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2929 0 : ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2930 0 : break;
2931 : }
2932 : case MSG_TYPE_TARGET_MSGOUT:
2933 : {
2934 : int lastbyte;
2935 : int msgdone;
2936 :
2937 : /*
2938 : * The initiator signals that this is
2939 : * the last byte by dropping ATN.
2940 : */
2941 0 : lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2942 :
2943 : /*
2944 : * Read the latched byte, but turn off SPIOEN first
2945 : * so that we don't inadvertently cause a REQ for the
2946 : * next byte.
2947 : */
2948 0 : ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2949 0 : ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2950 0 : msgdone = ahc_parse_msg(ahc, &devinfo);
2951 0 : if (msgdone == MSGLOOP_TERMINATED) {
2952 : /*
2953 : * The message is *really* done in that it caused
2954 : * us to go to bus free. The sequencer has already
2955 : * been reset at this point, so pull the ejection
2956 : * handle.
2957 : */
2958 0 : return;
2959 : }
2960 :
2961 0 : ahc->msgin_index++;
2962 :
2963 : /*
2964 : * XXX Read spec about initiator dropping ATN too soon
2965 : * and use msgdone to detect it.
2966 : */
2967 0 : if (msgdone == MSGLOOP_MSGCOMPLETE) {
2968 0 : ahc->msgin_index = 0;
2969 :
2970 : /*
2971 : * If this message illicited a response, transition
2972 : * to the Message in phase and send it.
2973 : */
2974 0 : if (ahc->msgout_len != 0) {
2975 0 : ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2976 0 : ahc_outb(ahc, SXFRCTL0,
2977 : ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2978 0 : ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2979 0 : ahc->msgin_index = 0;
2980 0 : break;
2981 : }
2982 : }
2983 :
2984 0 : if (lastbyte)
2985 0 : end_session = TRUE;
2986 : else {
2987 : /* Ask for the next byte. */
2988 0 : ahc_outb(ahc, SXFRCTL0,
2989 : ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2990 : }
2991 :
2992 0 : break;
2993 : }
2994 : default:
2995 0 : panic("Unknown REQINIT message type");
2996 : }
2997 :
2998 0 : if (end_session) {
2999 0 : ahc_clear_msg_state(ahc);
3000 0 : ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3001 0 : } else
3002 0 : ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3003 0 : }
3004 :
3005 : /*
3006 : * See if we sent a particular extended message to the target.
3007 : * If "full" is true, return true only if the target saw the full
3008 : * message. If "full" is false, return true if the target saw at
3009 : * least the first byte of the message.
3010 : */
3011 : static int
3012 0 : ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3013 : {
3014 : int found;
3015 : u_int index;
3016 :
3017 : found = FALSE;
3018 : index = 0;
3019 :
3020 0 : while (index < ahc->msgout_len) {
3021 0 : if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3022 : u_int end_index;
3023 :
3024 0 : end_index = index + 1 + ahc->msgout_buf[index + 1];
3025 0 : if (ahc->msgout_buf[index+2] == msgval
3026 0 : && type == AHCMSG_EXT) {
3027 :
3028 0 : if (full) {
3029 0 : if (ahc->msgout_index > end_index)
3030 0 : found = TRUE;
3031 0 : } else if (ahc->msgout_index > index)
3032 0 : found = TRUE;
3033 : }
3034 : index = end_index;
3035 0 : } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3036 0 : && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3037 :
3038 : /* Skip tag type and tag id or residue param*/
3039 0 : index += 2;
3040 0 : } else {
3041 : /* Single byte message */
3042 0 : if (type == AHCMSG_1B
3043 0 : && ahc->msgout_buf[index] == msgval
3044 0 : && ahc->msgout_index > index)
3045 0 : found = TRUE;
3046 0 : index++;
3047 : }
3048 :
3049 0 : if (found)
3050 : break;
3051 : }
3052 0 : return (found);
3053 : }
3054 :
3055 : /*
3056 : * Wait for a complete incoming message, parse it, and respond accordingly.
3057 : */
3058 : static int
3059 0 : ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3060 : {
3061 : struct ahc_initiator_tinfo *tinfo;
3062 0 : struct ahc_tmode_tstate *tstate;
3063 : int reject;
3064 : int done;
3065 : int response;
3066 : u_int targ_scsirate;
3067 :
3068 : done = MSGLOOP_IN_PROG;
3069 : response = FALSE;
3070 : reject = FALSE;
3071 0 : tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3072 0 : devinfo->target, &tstate);
3073 0 : targ_scsirate = tinfo->scsirate;
3074 :
3075 : /*
3076 : * Parse as much of the message as is available,
3077 : * rejecting it if we don't support it. When
3078 : * the entire message is available and has been
3079 : * handled, return MSGLOOP_MSGCOMPLETE, indicating
3080 : * that we have parsed an entire message.
3081 : *
3082 : * In the case of extended messages, we accept the length
3083 : * byte outright and perform more checking once we know the
3084 : * extended message type.
3085 : */
3086 0 : switch (ahc->msgin_buf[0]) {
3087 : case MSG_DISCONNECT:
3088 : case MSG_SAVEDATAPOINTER:
3089 : case MSG_CMDCOMPLETE:
3090 : case MSG_RESTOREPOINTERS:
3091 : case MSG_IGN_WIDE_RESIDUE:
3092 : /*
3093 : * End our message loop as these are messages
3094 : * the sequencer handles on its own.
3095 : */
3096 : done = MSGLOOP_TERMINATED;
3097 0 : break;
3098 : case MSG_MESSAGE_REJECT:
3099 0 : response = ahc_handle_msg_reject(ahc, devinfo);
3100 : /* FALLTHROUGH */
3101 : case MSG_NOOP:
3102 : done = MSGLOOP_MSGCOMPLETE;
3103 0 : break;
3104 : case MSG_EXTENDED:
3105 : {
3106 : /* Wait for enough of the message to begin validation */
3107 0 : if (ahc->msgin_index < 2)
3108 : break;
3109 0 : switch (ahc->msgin_buf[2]) {
3110 : case MSG_EXT_SDTR:
3111 : {
3112 : struct ahc_syncrate *syncrate;
3113 0 : u_int period;
3114 0 : u_int ppr_options;
3115 0 : u_int offset;
3116 : u_int saved_offset;
3117 :
3118 0 : if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3119 : reject = TRUE;
3120 0 : break;
3121 : }
3122 :
3123 : /*
3124 : * Wait until we have both args before validating
3125 : * and acting on this message.
3126 : *
3127 : * Add one to MSG_EXT_SDTR_LEN to account for
3128 : * the extended message preamble.
3129 : */
3130 0 : if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3131 0 : break;
3132 :
3133 0 : period = ahc->msgin_buf[3];
3134 0 : ppr_options = 0;
3135 0 : saved_offset = offset = ahc->msgin_buf[4];
3136 0 : syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3137 : &ppr_options,
3138 0 : devinfo->role);
3139 0 : ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3140 0 : targ_scsirate & WIDEXFER,
3141 0 : devinfo->role);
3142 : if (bootverbose) {
3143 : printf("(%s:%c:%d:%d): Received "
3144 : "SDTR period %x, offset %x\n\t"
3145 : "Filtered to period %x, offset %x\n",
3146 : ahc_name(ahc), devinfo->channel,
3147 : devinfo->target, devinfo->lun,
3148 : ahc->msgin_buf[3], saved_offset,
3149 : period, offset);
3150 : }
3151 0 : ahc_set_syncrate(ahc, devinfo,
3152 0 : syncrate, period,
3153 0 : offset, ppr_options,
3154 : AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3155 : /*paused*/TRUE);
3156 :
3157 : /*
3158 : * See if we initiated Sync Negotiation
3159 : * and didn't have to fall down to async
3160 : * transfers.
3161 : */
3162 0 : if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3163 : /* We started it */
3164 0 : if (saved_offset != offset) {
3165 : /* Went too low - force async */
3166 : reject = TRUE;
3167 0 : }
3168 : } else {
3169 : /*
3170 : * Send our own SDTR in reply
3171 : */
3172 : if (bootverbose
3173 : && devinfo->role == ROLE_INITIATOR) {
3174 : printf("(%s:%c:%d:%d): Target "
3175 : "Initiated SDTR\n",
3176 : ahc_name(ahc), devinfo->channel,
3177 : devinfo->target, devinfo->lun);
3178 : }
3179 0 : ahc->msgout_index = 0;
3180 0 : ahc->msgout_len = 0;
3181 0 : ahc_construct_sdtr(ahc, devinfo,
3182 0 : period, offset);
3183 0 : ahc->msgout_index = 0;
3184 : response = TRUE;
3185 : }
3186 : done = MSGLOOP_MSGCOMPLETE;
3187 0 : break;
3188 0 : }
3189 : case MSG_EXT_WDTR:
3190 : {
3191 0 : u_int bus_width;
3192 : u_int saved_width;
3193 : u_int sending_reply;
3194 :
3195 : sending_reply = FALSE;
3196 0 : if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3197 : reject = TRUE;
3198 0 : break;
3199 : }
3200 :
3201 : /*
3202 : * Wait until we have our arg before validating
3203 : * and acting on this message.
3204 : *
3205 : * Add one to MSG_EXT_WDTR_LEN to account for
3206 : * the extended message preamble.
3207 : */
3208 0 : if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3209 0 : break;
3210 :
3211 0 : bus_width = ahc->msgin_buf[3];
3212 : saved_width = bus_width;
3213 0 : ahc_validate_width(ahc, tinfo, &bus_width,
3214 0 : devinfo->role);
3215 : if (bootverbose) {
3216 : printf("(%s:%c:%d:%d): Received WDTR "
3217 : "%x filtered to %x\n",
3218 : ahc_name(ahc), devinfo->channel,
3219 : devinfo->target, devinfo->lun,
3220 : saved_width, bus_width);
3221 : }
3222 :
3223 0 : if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3224 : /*
3225 : * Don't send a WDTR back to the
3226 : * target, since we asked first.
3227 : * If the width went higher than our
3228 : * request, reject it.
3229 : */
3230 0 : if (saved_width > bus_width) {
3231 : reject = TRUE;
3232 0 : printf("(%s:%c:%d:%d): requested %dBit "
3233 : "transfers. Rejecting...\n",
3234 0 : ahc_name(ahc), devinfo->channel,
3235 0 : devinfo->target, devinfo->lun,
3236 0 : 8 * (0x01 << bus_width));
3237 0 : bus_width = 0;
3238 0 : }
3239 : } else {
3240 : /*
3241 : * Send our own WDTR in reply
3242 : */
3243 : if (bootverbose
3244 : && devinfo->role == ROLE_INITIATOR) {
3245 : printf("(%s:%c:%d:%d): Target "
3246 : "Initiated WDTR\n",
3247 : ahc_name(ahc), devinfo->channel,
3248 : devinfo->target, devinfo->lun);
3249 : }
3250 0 : ahc->msgout_index = 0;
3251 0 : ahc->msgout_len = 0;
3252 0 : ahc_construct_wdtr(ahc, devinfo, bus_width);
3253 0 : ahc->msgout_index = 0;
3254 : response = TRUE;
3255 : sending_reply = TRUE;
3256 : }
3257 : /*
3258 : * After a wide message, we are async, but
3259 : * some devices don't seem to honor this portion
3260 : * of the spec. Force a renegotiation of the
3261 : * sync component of our transfer agreement even
3262 : * if our goal is async. By updating our width
3263 : * after forcing the negotiation, we avoid
3264 : * renegotiating for width.
3265 : */
3266 0 : ahc_update_neg_request(ahc, devinfo, tstate,
3267 : tinfo, AHC_NEG_ALWAYS);
3268 0 : ahc_set_width(ahc, devinfo, bus_width,
3269 : AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3270 : /*paused*/TRUE);
3271 0 : if (sending_reply == FALSE && reject == FALSE) {
3272 :
3273 : /*
3274 : * We will always have an SDTR to send.
3275 : */
3276 0 : ahc->msgout_index = 0;
3277 0 : ahc->msgout_len = 0;
3278 0 : ahc_build_transfer_msg(ahc, devinfo);
3279 0 : ahc->msgout_index = 0;
3280 : response = TRUE;
3281 0 : }
3282 : done = MSGLOOP_MSGCOMPLETE;
3283 0 : break;
3284 0 : }
3285 : case MSG_EXT_PPR:
3286 : {
3287 : struct ahc_syncrate *syncrate;
3288 0 : u_int period;
3289 0 : u_int offset;
3290 0 : u_int bus_width;
3291 0 : u_int ppr_options;
3292 : u_int saved_width;
3293 : u_int saved_offset;
3294 : u_int saved_ppr_options;
3295 :
3296 0 : if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3297 : reject = TRUE;
3298 0 : break;
3299 : }
3300 :
3301 : /*
3302 : * Wait until we have all args before validating
3303 : * and acting on this message.
3304 : *
3305 : * Add one to MSG_EXT_PPR_LEN to account for
3306 : * the extended message preamble.
3307 : */
3308 0 : if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3309 0 : break;
3310 :
3311 0 : period = ahc->msgin_buf[3];
3312 0 : offset = ahc->msgin_buf[5];
3313 0 : bus_width = ahc->msgin_buf[6];
3314 : saved_width = bus_width;
3315 0 : ppr_options = ahc->msgin_buf[7];
3316 : /*
3317 : * According to the spec, a DT only
3318 : * period factor with no DT option
3319 : * set implies async.
3320 : */
3321 0 : if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3322 0 : && period == 9)
3323 0 : offset = 0;
3324 0 : saved_ppr_options = ppr_options;
3325 0 : saved_offset = offset;
3326 :
3327 : /*
3328 : * Mask out any options we don't support
3329 : * on any controller. Transfer options are
3330 : * only available if we are negotiating wide.
3331 : */
3332 0 : ppr_options &= MSG_EXT_PPR_DT_REQ;
3333 0 : if (bus_width == 0)
3334 : ppr_options = 0;
3335 :
3336 0 : ahc_validate_width(ahc, tinfo, &bus_width,
3337 0 : devinfo->role);
3338 0 : syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3339 : &ppr_options,
3340 0 : devinfo->role);
3341 0 : ahc_validate_offset(ahc, tinfo, syncrate,
3342 0 : &offset, bus_width,
3343 0 : devinfo->role);
3344 :
3345 0 : if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3346 : /*
3347 : * If we are unable to do any of the
3348 : * requested options (we went too low),
3349 : * then we'll have to reject the message.
3350 : */
3351 0 : if (saved_width > bus_width
3352 0 : || saved_offset != offset
3353 0 : || saved_ppr_options != ppr_options) {
3354 : reject = TRUE;
3355 0 : period = 0;
3356 0 : offset = 0;
3357 0 : bus_width = 0;
3358 0 : ppr_options = 0;
3359 : syncrate = NULL;
3360 0 : }
3361 : } else {
3362 0 : if (devinfo->role != ROLE_TARGET)
3363 0 : printf("(%s:%c:%d:%d): Target "
3364 : "Initiated PPR\n",
3365 : ahc_name(ahc), devinfo->channel,
3366 : devinfo->target, devinfo->lun);
3367 : else
3368 0 : printf("(%s:%c:%d:%d): Initiator "
3369 : "Initiated PPR\n",
3370 : ahc_name(ahc), devinfo->channel,
3371 : devinfo->target, devinfo->lun);
3372 0 : ahc->msgout_index = 0;
3373 0 : ahc->msgout_len = 0;
3374 0 : ahc_construct_ppr(ahc, devinfo, period, offset,
3375 0 : bus_width, ppr_options);
3376 0 : ahc->msgout_index = 0;
3377 : response = TRUE;
3378 : }
3379 : if (bootverbose) {
3380 : printf("(%s:%c:%d:%d): Received PPR width %x, "
3381 : "period %x, offset %x,options %x\n"
3382 : "\tFiltered to width %x, period %x, "
3383 : "offset %x, options %x\n",
3384 : ahc_name(ahc), devinfo->channel,
3385 : devinfo->target, devinfo->lun,
3386 : saved_width, ahc->msgin_buf[3],
3387 : saved_offset, saved_ppr_options,
3388 : bus_width, period, offset, ppr_options);
3389 : }
3390 0 : ahc_set_width(ahc, devinfo, bus_width,
3391 : AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3392 : /*paused*/TRUE);
3393 0 : ahc_set_syncrate(ahc, devinfo,
3394 0 : syncrate, period,
3395 0 : offset, ppr_options,
3396 : AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3397 : /*paused*/TRUE);
3398 : done = MSGLOOP_MSGCOMPLETE;
3399 0 : break;
3400 0 : }
3401 : default:
3402 : /* Unknown extended message. Reject it. */
3403 : reject = TRUE;
3404 0 : break;
3405 : }
3406 : break;
3407 : }
3408 : #ifdef AHC_TARGET_MODE
3409 : case MSG_BUS_DEV_RESET:
3410 : ahc_handle_devreset(ahc, devinfo,
3411 : CAM_BDR_SENT,
3412 : "Bus Device Reset Received",
3413 : /*verbose_level*/0);
3414 : ahc_restart(ahc);
3415 : done = MSGLOOP_TERMINATED;
3416 : break;
3417 : case MSG_ABORT_TAG:
3418 : case MSG_ABORT:
3419 : case MSG_CLEAR_QUEUE:
3420 : {
3421 : int tag;
3422 :
3423 : /* Target mode messages */
3424 : if (devinfo->role != ROLE_TARGET) {
3425 : reject = TRUE;
3426 : break;
3427 : }
3428 : tag = SCB_LIST_NULL;
3429 : if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3430 : tag = ahc_inb(ahc, INITIATOR_TAG);
3431 : ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3432 : devinfo->lun, tag, ROLE_TARGET,
3433 : CAM_REQ_ABORTED);
3434 :
3435 : tstate = ahc->enabled_targets[devinfo->our_scsiid];
3436 : if (tstate != NULL) {
3437 : struct ahc_tmode_lstate* lstate;
3438 :
3439 : lstate = tstate->enabled_luns[devinfo->lun];
3440 : if (lstate != NULL) {
3441 : ahc_queue_lstate_event(ahc, lstate,
3442 : devinfo->our_scsiid,
3443 : ahc->msgin_buf[0],
3444 : /*arg*/tag);
3445 : ahc_send_lstate_events(ahc, lstate);
3446 : }
3447 : }
3448 : ahc_restart(ahc);
3449 : done = MSGLOOP_TERMINATED;
3450 : break;
3451 : }
3452 : #endif
3453 : case MSG_TERM_IO_PROC:
3454 : default:
3455 : reject = TRUE;
3456 0 : break;
3457 : }
3458 :
3459 0 : if (reject) {
3460 : /*
3461 : * Setup to reject the message.
3462 : */
3463 0 : ahc->msgout_index = 0;
3464 0 : ahc->msgout_len = 1;
3465 0 : ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3466 : done = MSGLOOP_MSGCOMPLETE;
3467 : response = TRUE;
3468 0 : }
3469 :
3470 0 : if (done != MSGLOOP_IN_PROG && !response)
3471 : /* Clear the outgoing message buffer */
3472 0 : ahc->msgout_len = 0;
3473 :
3474 0 : return (done);
3475 0 : }
3476 :
3477 : /*
3478 : * Process a message reject message.
3479 : */
3480 : static int
3481 0 : ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3482 : {
3483 : /*
3484 : * What we care about here is if we had an
3485 : * outstanding SDTR or WDTR message for this
3486 : * target. If we did, this is a signal that
3487 : * the target is refusing negotiation.
3488 : */
3489 : struct scb *scb;
3490 : struct ahc_initiator_tinfo *tinfo;
3491 0 : struct ahc_tmode_tstate *tstate;
3492 : u_int scb_index;
3493 : u_int last_msg;
3494 : int response = 0;
3495 :
3496 0 : scb_index = ahc_inb(ahc, SCB_TAG);
3497 0 : scb = ahc_lookup_scb(ahc, scb_index);
3498 0 : tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3499 0 : devinfo->our_scsiid,
3500 0 : devinfo->target, &tstate);
3501 : /* Might be necessary */
3502 0 : last_msg = ahc_inb(ahc, LAST_MSG);
3503 :
3504 0 : if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3505 : /*
3506 : * Target does not support the PPR message.
3507 : * Attempt to negotiate SPI-2 style.
3508 : */
3509 : if (bootverbose) {
3510 : printf("(%s:%c:%d:%d): PPR Rejected. "
3511 : "Trying WDTR/SDTR\n",
3512 : ahc_name(ahc), devinfo->channel,
3513 : devinfo->target, devinfo->lun);
3514 : }
3515 0 : tinfo->goal.ppr_options = 0;
3516 0 : tinfo->curr.transport_version = 2;
3517 0 : tinfo->goal.transport_version = 2;
3518 0 : ahc->msgout_index = 0;
3519 0 : ahc->msgout_len = 0;
3520 0 : ahc_build_transfer_msg(ahc, devinfo);
3521 0 : ahc->msgout_index = 0;
3522 : response = 1;
3523 0 : } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3524 :
3525 : /* note 8bit xfers */
3526 0 : printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3527 0 : "8bit transfers\n", ahc_name(ahc),
3528 0 : devinfo->channel, devinfo->target, devinfo->lun);
3529 0 : ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3530 : AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3531 : /*paused*/TRUE);
3532 : /*
3533 : * No need to clear the sync rate. If the target
3534 : * did not accept the command, our syncrate is
3535 : * unaffected. If the target started the negotiation,
3536 : * but rejected our response, we already cleared the
3537 : * sync rate before sending our WDTR.
3538 : */
3539 0 : if (tinfo->goal.offset != tinfo->curr.offset) {
3540 :
3541 : /* Start the sync negotiation */
3542 0 : ahc->msgout_index = 0;
3543 0 : ahc->msgout_len = 0;
3544 0 : ahc_build_transfer_msg(ahc, devinfo);
3545 0 : ahc->msgout_index = 0;
3546 : response = 1;
3547 0 : }
3548 0 : } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3549 : /* note asynch xfers and clear flag */
3550 0 : ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3551 : /*offset*/0, /*ppr_options*/0,
3552 : AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3553 : /*paused*/TRUE);
3554 0 : printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3555 : "Using asynchronous transfers\n",
3556 0 : ahc_name(ahc), devinfo->channel,
3557 0 : devinfo->target, devinfo->lun);
3558 0 : } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3559 : int tag_type;
3560 : int mask;
3561 :
3562 : tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3563 :
3564 0 : if (tag_type == MSG_SIMPLE_TASK) {
3565 0 : printf("(%s:%c:%d:%d): refuses tagged commands. "
3566 : "Performing non-tagged I/O\n", ahc_name(ahc),
3567 : devinfo->channel, devinfo->target, devinfo->lun);
3568 0 : ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3569 : mask = ~0x23;
3570 0 : } else {
3571 0 : printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3572 : "Performing simple queue tagged I/O only\n",
3573 : ahc_name(ahc), devinfo->channel, devinfo->target,
3574 : devinfo->lun, tag_type == MSG_ORDERED_TASK
3575 : ? "ordered" : "head of queue");
3576 0 : ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3577 : mask = ~0x03;
3578 : }
3579 :
3580 : /*
3581 : * Resend the identify for this CCB as the target
3582 : * may believe that the selection is invalid otherwise.
3583 : */
3584 0 : ahc_outb(ahc, SCB_CONTROL,
3585 : ahc_inb(ahc, SCB_CONTROL) & mask);
3586 0 : scb->hscb->control &= mask;
3587 0 : ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3588 : /*type*/MSG_SIMPLE_TASK);
3589 0 : ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3590 0 : ahc_assert_atn(ahc);
3591 :
3592 : /*
3593 : * This transaction is now at the head of
3594 : * the untagged queue for this target.
3595 : */
3596 0 : if ((ahc->flags & AHC_SCB_BTT) == 0) {
3597 : struct scb_tailq *untagged_q;
3598 :
3599 : untagged_q =
3600 0 : &(ahc->untagged_queues[devinfo->target_offset]);
3601 0 : TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3602 0 : scb->flags |= SCB_UNTAGGEDQ;
3603 0 : }
3604 0 : ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3605 0 : scb->hscb->tag);
3606 :
3607 : /*
3608 : * Requeue all tagged commands for this target
3609 : * currently in our possession so they can be
3610 : * converted to untagged commands.
3611 : */
3612 0 : ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3613 0 : SCB_GET_CHANNEL(ahc, scb),
3614 0 : SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3615 : ROLE_INITIATOR, CAM_REQUEUE_REQ,
3616 : SEARCH_COMPLETE);
3617 0 : } else {
3618 : /*
3619 : * Otherwise, we ignore it.
3620 : */
3621 0 : printf("%s:%c:%d: Message reject for %x -- ignored\n",
3622 0 : ahc_name(ahc), devinfo->channel, devinfo->target,
3623 : last_msg);
3624 : }
3625 0 : return (response);
3626 0 : }
3627 :
3628 : /*
3629 : * Process an ingnore wide residue message.
3630 : */
3631 : static void
3632 0 : ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3633 : {
3634 : u_int scb_index;
3635 : struct scb *scb;
3636 :
3637 0 : scb_index = ahc_inb(ahc, SCB_TAG);
3638 0 : scb = ahc_lookup_scb(ahc, scb_index);
3639 : /*
3640 : * XXX Actually check data direction in the sequencer?
3641 : * Perhaps add datadir to some spare bits in the hscb?
3642 : */
3643 0 : if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3644 0 : || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3645 : /*
3646 : * Ignore the message if we haven't
3647 : * seen an appropriate data phase yet.
3648 : */
3649 : } else {
3650 : /*
3651 : * If the residual occurred on the last
3652 : * transfer and the transfer request was
3653 : * expected to end on an odd count, do
3654 : * nothing. Otherwise, subtract a byte
3655 : * and update the residual count accordingly.
3656 : */
3657 : uint32_t sgptr;
3658 :
3659 0 : sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3660 0 : if ((sgptr & SG_LIST_NULL) != 0
3661 0 : && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3662 : /*
3663 : * If the residual occurred on the last
3664 : * transfer and the transfer request was
3665 : * expected to end on an odd count, do
3666 : * nothing.
3667 : */
3668 : } else {
3669 : struct ahc_dma_seg *sg;
3670 : uint32_t data_cnt;
3671 : uint32_t data_addr;
3672 : uint32_t sglen;
3673 :
3674 : /* Pull in all of the sgptr */
3675 0 : sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3676 0 : data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3677 :
3678 0 : if ((sgptr & SG_LIST_NULL) != 0) {
3679 : /*
3680 : * The residual data count is not updated
3681 : * for the command run to completion case.
3682 : * Explicitly zero the count.
3683 : */
3684 0 : data_cnt &= ~AHC_SG_LEN_MASK;
3685 0 : }
3686 :
3687 0 : data_addr = ahc_inl(ahc, SHADDR);
3688 :
3689 0 : data_cnt += 1;
3690 : data_addr -= 1;
3691 0 : sgptr &= SG_PTR_MASK;
3692 :
3693 0 : sg = ahc_sg_bus_to_virt(scb, sgptr);
3694 :
3695 : /*
3696 : * The residual sg ptr points to the next S/G
3697 : * to load so we must go back one.
3698 : */
3699 0 : sg--;
3700 0 : sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
3701 0 : if (sg != scb->sg_list
3702 0 : && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3703 :
3704 0 : sg--;
3705 0 : sglen = aic_le32toh(sg->len);
3706 : /*
3707 : * Preserve High Address and SG_LIST bits
3708 : * while setting the count to 1.
3709 : */
3710 0 : data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3711 0 : data_addr = aic_le32toh(sg->addr)
3712 0 : + (sglen & AHC_SG_LEN_MASK) - 1;
3713 :
3714 : /*
3715 : * Increment sg so it points to the
3716 : * "next" sg.
3717 : */
3718 0 : sg++;
3719 0 : sgptr = ahc_sg_virt_to_bus(scb, sg);
3720 0 : }
3721 0 : ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3722 0 : ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3723 : /*
3724 : * Toggle the "oddness" of the transfer length
3725 : * to handle this mid-transfer ignore wide
3726 : * residue. This ensures that the oddness is
3727 : * correct for subsequent data transfers.
3728 : */
3729 0 : ahc_outb(ahc, SCB_LUN,
3730 : ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3731 : }
3732 : }
3733 0 : }
3734 :
3735 :
3736 : /*
3737 : * Reinitialize the data pointers for the active transfer
3738 : * based on its current residual.
3739 : */
3740 : static void
3741 0 : ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3742 : {
3743 : struct scb *scb;
3744 : struct ahc_dma_seg *sg;
3745 : u_int scb_index;
3746 : uint32_t sgptr;
3747 : uint32_t resid;
3748 : uint32_t dataptr;
3749 :
3750 0 : scb_index = ahc_inb(ahc, SCB_TAG);
3751 0 : scb = ahc_lookup_scb(ahc, scb_index);
3752 0 : sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3753 0 : | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3754 0 : | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3755 0 : | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3756 :
3757 0 : sgptr &= SG_PTR_MASK;
3758 0 : sg = ahc_sg_bus_to_virt(scb, sgptr);
3759 :
3760 : /* The residual sg_ptr always points to the next sg */
3761 0 : sg--;
3762 :
3763 0 : resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3764 0 : | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3765 0 : | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3766 :
3767 0 : dataptr = aic_le32toh(sg->addr)
3768 0 : + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK)
3769 0 : - resid;
3770 0 : if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3771 : u_int dscommand1;
3772 :
3773 0 : dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3774 0 : ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3775 0 : ahc_outb(ahc, HADDR,
3776 : (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3777 0 : ahc_outb(ahc, DSCOMMAND1, dscommand1);
3778 0 : }
3779 0 : ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3780 0 : ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3781 0 : ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3782 0 : ahc_outb(ahc, HADDR, dataptr);
3783 0 : ahc_outb(ahc, HCNT + 2, resid >> 16);
3784 0 : ahc_outb(ahc, HCNT + 1, resid >> 8);
3785 0 : ahc_outb(ahc, HCNT, resid);
3786 0 : if ((ahc->features & AHC_ULTRA2) == 0) {
3787 0 : ahc_outb(ahc, STCNT + 2, resid >> 16);
3788 0 : ahc_outb(ahc, STCNT + 1, resid >> 8);
3789 0 : ahc_outb(ahc, STCNT, resid);
3790 0 : }
3791 0 : }
3792 :
3793 : /*
3794 : * Handle the effects of issuing a bus device reset message.
3795 : */
3796 : static void
3797 0 : ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3798 : cam_status status, char *message, int verbose_level)
3799 : {
3800 : #ifdef AHC_TARGET_MODE
3801 : struct ahc_tmode_tstate* tstate;
3802 : u_int lun;
3803 : #endif
3804 : int found;
3805 :
3806 0 : found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3807 0 : CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3808 : status);
3809 :
3810 : #ifdef AHC_TARGET_MODE
3811 : /*
3812 : * Send an immediate notify ccb to all target mord peripheral
3813 : * drivers affected by this action.
3814 : */
3815 : tstate = ahc->enabled_targets[devinfo->our_scsiid];
3816 : if (tstate != NULL) {
3817 : for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3818 : struct ahc_tmode_lstate* lstate;
3819 :
3820 : lstate = tstate->enabled_luns[lun];
3821 : if (lstate == NULL)
3822 : continue;
3823 :
3824 : ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3825 : MSG_BUS_DEV_RESET, /*arg*/0);
3826 : ahc_send_lstate_events(ahc, lstate);
3827 : }
3828 : }
3829 : #endif
3830 :
3831 : /*
3832 : * Go back to async/narrow transfers and renegotiate.
3833 : */
3834 0 : ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3835 : AHC_TRANS_CUR, /*paused*/TRUE);
3836 0 : ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3837 : /*period*/0, /*offset*/0, /*ppr_options*/0,
3838 : AHC_TRANS_CUR, /*paused*/TRUE);
3839 :
3840 0 : if (status != CAM_SEL_TIMEOUT)
3841 0 : ahc_send_async(ahc, devinfo->channel, devinfo->target,
3842 : CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3843 :
3844 0 : if (message != NULL
3845 0 : && (verbose_level <= bootverbose))
3846 0 : printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3847 0 : message, devinfo->channel, devinfo->target, found);
3848 0 : }
3849 :
3850 : #ifdef AHC_TARGET_MODE
3851 : static void
3852 : ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3853 : struct scb *scb)
3854 : {
3855 :
3856 : /*
3857 : * To facilitate adding multiple messages together,
3858 : * each routine should increment the index and len
3859 : * variables instead of setting them explicitly.
3860 : */
3861 : ahc->msgout_index = 0;
3862 : ahc->msgout_len = 0;
3863 :
3864 : if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3865 : ahc_build_transfer_msg(ahc, devinfo);
3866 : else
3867 : panic("ahc_intr: AWAITING target message with no message");
3868 :
3869 : ahc->msgout_index = 0;
3870 : ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3871 : }
3872 : #endif
3873 :
3874 : int
3875 0 : ahc_softc_init(struct ahc_softc *ahc)
3876 : {
3877 :
3878 : /* The IRQMS bit is only valid on VL and EISA chips */
3879 0 : if ((ahc->chip & AHC_PCI) == 0)
3880 0 : ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3881 : else
3882 0 : ahc->unpause = 0;
3883 0 : ahc->pause = ahc->unpause | PAUSE;
3884 : /* XXX The shared scb data stuff should be deprecated */
3885 0 : if (ahc->scb_data == NULL) {
3886 0 : ahc->scb_data = malloc(sizeof(*ahc->scb_data), M_DEVBUF,
3887 : M_NOWAIT | M_ZERO);
3888 0 : if (ahc->scb_data == NULL)
3889 0 : return (ENOMEM);
3890 : }
3891 :
3892 0 : return (0);
3893 0 : }
3894 :
3895 : void
3896 0 : ahc_softc_insert(struct ahc_softc *ahc)
3897 : {
3898 : struct ahc_softc *list_ahc;
3899 :
3900 : #if AHC_PCI_CONFIG > 0
3901 : /*
3902 : * Second Function PCI devices need to inherit some
3903 : * settings from function 0.
3904 : */
3905 0 : if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI
3906 0 : && (ahc->features & AHC_MULTI_FUNC) != 0) {
3907 0 : TAILQ_FOREACH(list_ahc, &ahc_tailq, links) {
3908 : ahc_dev_softc_t list_pci;
3909 : ahc_dev_softc_t pci;
3910 :
3911 0 : list_pci = list_ahc->dev_softc;
3912 0 : pci = ahc->dev_softc;
3913 0 : if (ahc_get_pci_slot(list_pci) == ahc_get_pci_slot(pci)
3914 0 : && ahc_get_pci_bus(list_pci) == ahc_get_pci_bus(pci)) {
3915 : struct ahc_softc *master;
3916 : struct ahc_softc *slave;
3917 :
3918 0 : if (ahc_get_pci_function(list_pci) == 0) {
3919 : master = list_ahc;
3920 : slave = ahc;
3921 0 : } else {
3922 : master = ahc;
3923 : slave = list_ahc;
3924 : }
3925 0 : slave->flags &= ~AHC_BIOS_ENABLED;
3926 0 : slave->flags |=
3927 0 : master->flags & AHC_BIOS_ENABLED;
3928 0 : slave->flags &= ~AHC_PRIMARY_CHANNEL;
3929 0 : slave->flags |=
3930 0 : master->flags & AHC_PRIMARY_CHANNEL;
3931 : break;
3932 : }
3933 0 : }
3934 : }
3935 : #endif
3936 :
3937 : /*
3938 : * Insertion sort into our list of softcs.
3939 : */
3940 0 : list_ahc = TAILQ_FIRST(&ahc_tailq);
3941 0 : while (list_ahc != NULL
3942 0 : && ahc_softc_comp(ahc, list_ahc) <= 0)
3943 0 : list_ahc = TAILQ_NEXT(list_ahc, links);
3944 0 : if (list_ahc != NULL)
3945 0 : TAILQ_INSERT_BEFORE(list_ahc, ahc, links);
3946 : else
3947 0 : TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links);
3948 0 : ahc->init_level++;
3949 0 : }
3950 :
3951 : void
3952 0 : ahc_set_unit(struct ahc_softc *ahc, int unit)
3953 : {
3954 0 : ahc->unit = unit;
3955 0 : }
3956 :
3957 : void
3958 0 : ahc_set_name(struct ahc_softc *ahc, char *name)
3959 : {
3960 0 : if (ahc->name != NULL)
3961 0 : free(ahc->name, M_DEVBUF, 0);
3962 0 : ahc->name = name;
3963 0 : }
3964 :
3965 : void
3966 0 : ahc_free(struct ahc_softc *ahc)
3967 : {
3968 : int i;
3969 :
3970 0 : switch (ahc->init_level) {
3971 : default:
3972 : case 2:
3973 0 : ahc_shutdown(ahc);
3974 : /* FALLTHROUGH */
3975 : case 1:
3976 0 : bus_dmamap_unload(ahc->parent_dmat, ahc->shared_data_dmamap);
3977 0 : bus_dmamap_destroy(ahc->parent_dmat, ahc->shared_data_dmamap);
3978 0 : bus_dmamem_unmap(ahc->parent_dmat, (caddr_t)ahc->qoutfifo, ahc->shared_data_size);
3979 0 : bus_dmamem_free(ahc->parent_dmat, &ahc->shared_data_seg, ahc->shared_data_nseg);
3980 0 : break;
3981 : case 0:
3982 : break;
3983 : }
3984 :
3985 0 : ahc_fini_scbdata(ahc);
3986 0 : for (i = 0; i < AHC_NUM_TARGETS; i++) {
3987 : struct ahc_tmode_tstate *tstate;
3988 :
3989 0 : tstate = ahc->enabled_targets[i];
3990 0 : if (tstate != NULL) {
3991 : #ifdef AHC_TARGET_MODE
3992 : int j;
3993 :
3994 : for (j = 0; j < AHC_NUM_LUNS; j++) {
3995 : struct ahc_tmode_lstate *lstate;
3996 :
3997 : lstate = tstate->enabled_luns[j];
3998 : if (lstate != NULL) {
3999 : /*xpt_free_path(lstate->path);*/
4000 : free(lstate, M_DEVBUF, 0);
4001 : }
4002 : }
4003 : #endif
4004 0 : free(tstate, M_DEVBUF, 0);
4005 0 : }
4006 : }
4007 : #ifdef AHC_TARGET_MODE
4008 : if (ahc->black_hole != NULL) {
4009 : /*xpt_free_path(ahc->black_hole->path);*/
4010 : free(ahc->black_hole, M_DEVBUF, 0);
4011 : }
4012 : #endif
4013 0 : if (ahc->seep_config != NULL)
4014 0 : free(ahc->seep_config, M_DEVBUF, 0);
4015 : return;
4016 0 : }
4017 :
4018 : void
4019 0 : ahc_shutdown(void *arg)
4020 : {
4021 : struct ahc_softc *ahc;
4022 : int i;
4023 :
4024 0 : ahc = (struct ahc_softc *)arg;
4025 :
4026 : /* This will reset most registers to 0, but not all */
4027 0 : ahc_reset(ahc, /*reinit*/FALSE);
4028 0 : ahc_outb(ahc, SCSISEQ, 0);
4029 0 : ahc_outb(ahc, SXFRCTL0, 0);
4030 0 : ahc_outb(ahc, DSPCISTATUS, 0);
4031 :
4032 0 : for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4033 0 : ahc_outb(ahc, i, 0);
4034 0 : }
4035 :
4036 : /*
4037 : * Reset the controller and record some information about it
4038 : * that is only available just after a reset. If "reinit" is
4039 : * non-zero, this reset occured after initial configuration
4040 : * and the caller requests that the chip be fully reinitialized
4041 : * to a runable state. Chip interrupts are *not* enabled after
4042 : * a reinitialization. The caller must enable interrupts via
4043 : * ahc_intr_enable().
4044 : */
4045 : int
4046 0 : ahc_reset(struct ahc_softc *ahc, int reinit)
4047 : {
4048 : u_int sblkctl;
4049 : u_int sxfrctl1_a, sxfrctl1_b;
4050 : int error;
4051 : int wait;
4052 :
4053 : /*
4054 : * Preserve the value of the SXFRCTL1 register for all channels.
4055 : * It contains settings that affect termination and we don't want
4056 : * to disturb the integrity of the bus.
4057 : */
4058 0 : ahc_pause(ahc);
4059 : sxfrctl1_b = 0;
4060 0 : if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4061 : /*
4062 : * Save channel B's settings in case this chip
4063 : * is setup for TWIN channel operation.
4064 : */
4065 0 : sblkctl = ahc_inb(ahc, SBLKCTL);
4066 0 : ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4067 0 : sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4068 0 : ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4069 0 : }
4070 0 : sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4071 :
4072 0 : ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4073 :
4074 : /*
4075 : * Ensure that the reset has finished. We delay 1000us
4076 : * prior to reading the register to make sure the chip
4077 : * has sufficiently completed its reset to handle register
4078 : * accesses.
4079 : */
4080 : wait = 1000;
4081 0 : do {
4082 0 : aic_delay(1000);
4083 0 : } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4084 :
4085 0 : if (wait == 0) {
4086 0 : printf("%s: WARNING - Failed chip reset! "
4087 0 : "Trying to initialize anyway.\n", ahc_name(ahc));
4088 0 : }
4089 0 : ahc_outb(ahc, HCNTRL, ahc->pause);
4090 :
4091 : /* Determine channel configuration */
4092 0 : sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4093 : /* No Twin Channel PCI cards */
4094 0 : if ((ahc->chip & AHC_PCI) != 0)
4095 0 : sblkctl &= ~SELBUSB;
4096 0 : switch (sblkctl) {
4097 : case 0:
4098 : /* Single Narrow Channel */
4099 : break;
4100 : case SELWIDE:
4101 : /* Wide Channel */
4102 0 : ahc->features |= AHC_WIDE;
4103 0 : break;
4104 : case SELBUSB:
4105 : /* Twin Channel */
4106 0 : ahc->features |= AHC_TWIN;
4107 0 : break;
4108 : default:
4109 0 : printf(" Unsupported adapter type (0x%x). Ignoring\n", sblkctl);
4110 0 : return(-1);
4111 : }
4112 :
4113 : /*
4114 : * Reload sxfrctl1.
4115 : *
4116 : * We must always initialize STPWEN to 1 before we
4117 : * restore the saved values. STPWEN is initialized
4118 : * to a tri-state condition which can only be cleared
4119 : * by turning it on.
4120 : */
4121 0 : if ((ahc->features & AHC_TWIN) != 0) {
4122 0 : sblkctl = ahc_inb(ahc, SBLKCTL);
4123 0 : ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4124 0 : ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4125 0 : ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4126 0 : }
4127 0 : ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4128 :
4129 : error = 0;
4130 0 : if (reinit != 0)
4131 : /*
4132 : * If a recovery action has forced a chip reset,
4133 : * re-initialize the chip to our liking.
4134 : */
4135 0 : error = ahc->bus_chip_init(ahc);
4136 : #ifdef AHC_DUMP_SEQ
4137 : else
4138 : ahc_dumpseq(ahc);
4139 : #endif
4140 :
4141 0 : return (error);
4142 0 : }
4143 :
4144 : /*
4145 : * Determine the number of SCBs available on the controller
4146 : */
4147 : int
4148 0 : ahc_probe_scbs(struct ahc_softc *ahc) {
4149 : int i;
4150 :
4151 0 : for (i = 0; i < AHC_SCB_MAX; i++) {
4152 :
4153 0 : ahc_outb(ahc, SCBPTR, i);
4154 0 : ahc_outb(ahc, SCB_BASE, i);
4155 0 : if (ahc_inb(ahc, SCB_BASE) != i)
4156 : break;
4157 0 : ahc_outb(ahc, SCBPTR, 0);
4158 0 : if (ahc_inb(ahc, SCB_BASE) != 0)
4159 : break;
4160 : }
4161 0 : return (i);
4162 : }
4163 :
4164 : #if 0
4165 : static void
4166 : ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4167 : {
4168 : bus_addr_t *baddr;
4169 :
4170 : baddr = (bus_addr_t *)arg;
4171 : *baddr = segs->ds_addr;
4172 : }
4173 : #endif
4174 :
4175 : static void
4176 0 : ahc_build_free_scb_list(struct ahc_softc *ahc)
4177 : {
4178 : int scbsize;
4179 : int i;
4180 :
4181 : scbsize = 32;
4182 0 : if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4183 : scbsize = 64;
4184 :
4185 0 : for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4186 : int j;
4187 :
4188 0 : ahc_outb(ahc, SCBPTR, i);
4189 :
4190 : /*
4191 : * Touch all SCB bytes to avoid parity errors
4192 : * should one of our debugging routines read
4193 : * an otherwise uninitiatlized byte.
4194 : */
4195 0 : for (j = 0; j < scbsize; j++)
4196 0 : ahc_outb(ahc, SCB_BASE+j, 0xFF);
4197 :
4198 : /* Clear the control byte. */
4199 0 : ahc_outb(ahc, SCB_CONTROL, 0);
4200 :
4201 : /* Set the next pointer */
4202 0 : if ((ahc->flags & AHC_PAGESCBS) != 0)
4203 0 : ahc_outb(ahc, SCB_NEXT, i+1);
4204 : else
4205 0 : ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4206 :
4207 : /* Make the tag number, SCSIID, and lun invalid */
4208 0 : ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4209 0 : ahc_outb(ahc, SCB_SCSIID, 0xFF);
4210 0 : ahc_outb(ahc, SCB_LUN, 0xFF);
4211 : }
4212 :
4213 0 : if ((ahc->flags & AHC_PAGESCBS) != 0) {
4214 : /* SCB 0 heads the free list. */
4215 0 : ahc_outb(ahc, FREE_SCBH, 0);
4216 0 : } else {
4217 : /* No free list. */
4218 0 : ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4219 : }
4220 :
4221 : /* Make sure that the last SCB terminates the free list */
4222 0 : ahc_outb(ahc, SCBPTR, i-1);
4223 0 : ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4224 0 : }
4225 :
4226 : static int
4227 0 : ahc_init_scbdata(struct ahc_softc *ahc)
4228 : {
4229 : struct scb_data *scb_data;
4230 : int i;
4231 :
4232 0 : scb_data = ahc->scb_data;
4233 0 : SLIST_INIT(&scb_data->free_scbs);
4234 0 : SLIST_INIT(&scb_data->sg_maps);
4235 :
4236 0 : mtx_init(&ahc->sc_scb_mtx, IPL_BIO);
4237 0 : scsi_iopool_init(&ahc->sc_iopool, ahc, ahc_scb_alloc, ahc_scb_free);
4238 :
4239 : /* Allocate SCB resources */
4240 0 : scb_data->scbarray = mallocarray(AHC_SCB_MAX_ALLOC, sizeof(struct scb),
4241 : M_DEVBUF, M_NOWAIT | M_ZERO);
4242 0 : if (scb_data->scbarray == NULL)
4243 0 : return (ENOMEM);
4244 :
4245 : /* Determine the number of hardware SCBs and initialize them */
4246 :
4247 0 : scb_data->maxhscbs = ahc_probe_scbs(ahc);
4248 0 : if (ahc->scb_data->maxhscbs == 0) {
4249 0 : printf("%s: No SCB space found\n", ahc_name(ahc));
4250 0 : return (ENXIO);
4251 : }
4252 :
4253 : /*
4254 : * Create our DMA tags. These tags define the kinds of device
4255 : * accessible memory allocations and memory mappings we will
4256 : * need to perform during normal operation.
4257 : *
4258 : * Unless we need to further restrict the allocation, we rely
4259 : * on the restrictions of the parent dmat, hence the common
4260 : * use of MAXADDR and MAXSIZE.
4261 : */
4262 :
4263 0 : if (ahc_createdmamem(ahc->parent_dmat,
4264 0 : AHC_SCB_MAX * sizeof(struct hardware_scb), ahc->sc_dmaflags,
4265 0 : &scb_data->hscb_dmamap,
4266 0 : (caddr_t *)&scb_data->hscbs, &scb_data->hscb_busaddr,
4267 0 : &scb_data->hscb_seg, &scb_data->hscb_nseg, ahc_name(ahc),
4268 0 : "hardware SCB structures") < 0)
4269 : goto error_exit;
4270 :
4271 0 : scb_data->init_level++;
4272 :
4273 0 : if (ahc_createdmamem(ahc->parent_dmat,
4274 0 : AHC_SCB_MAX * sizeof(struct scsi_sense_data), ahc->sc_dmaflags,
4275 0 : &scb_data->sense_dmamap, (caddr_t *)&scb_data->sense,
4276 0 : &scb_data->sense_busaddr, &scb_data->sense_seg,
4277 0 : &scb_data->sense_nseg, ahc_name(ahc), "sense buffers") < 0)
4278 : goto error_exit;
4279 :
4280 0 : scb_data->init_level++;
4281 :
4282 : /* Perform initial CCB allocation */
4283 0 : memset(scb_data->hscbs, 0,
4284 : AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4285 0 : do {
4286 0 : i = scb_data->numscbs;
4287 0 : ahc_alloc_scbs(ahc);
4288 0 : } while ((i != scb_data->numscbs) &&
4289 0 : (scb_data->numscbs < AHC_SCB_MAX_ALLOC));
4290 :
4291 0 : if (scb_data->numscbs != AHC_SCB_MAX_ALLOC) {
4292 0 : printf("%s: ahc_init_scbdata - "
4293 : "Unable to allocate initial scbs\n",
4294 0 : ahc_name(ahc));
4295 0 : goto error_exit;
4296 : }
4297 :
4298 : /*
4299 : * Reserve the next queued SCB.
4300 : */
4301 0 : ahc->next_queued_scb = scsi_io_get(&ahc->sc_iopool,
4302 : SCSI_POLL | SCSI_NOSLEEP);
4303 0 : if (ahc->next_queued_scb != NULL)
4304 : /* Note that we were successful */
4305 0 : return (0);
4306 :
4307 : error_exit:
4308 :
4309 0 : return (ENOMEM);
4310 0 : }
4311 :
4312 : static void
4313 0 : ahc_fini_scbdata(struct ahc_softc *ahc)
4314 : {
4315 : struct scb_data *scb_data;
4316 :
4317 0 : scb_data = ahc->scb_data;
4318 0 : if (scb_data == NULL)
4319 0 : return;
4320 :
4321 0 : switch (scb_data->init_level) {
4322 : default:
4323 : case 5:
4324 : {
4325 : struct sg_map_node *sg_map;
4326 :
4327 0 : while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4328 0 : SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4329 0 : ahc_freedmamem(ahc->parent_dmat, PAGE_SIZE,
4330 0 : sg_map->sg_dmamap, (caddr_t)sg_map->sg_vaddr,
4331 0 : &sg_map->sg_dmasegs, sg_map->sg_nseg);
4332 0 : free(sg_map, M_DEVBUF, 0);
4333 : }
4334 0 : }
4335 : /*FALLTHROUGH*/
4336 : case 4:
4337 0 : ahc_freedmamem(ahc->parent_dmat,
4338 : AHC_SCB_MAX * sizeof(struct scsipi_sense_data),
4339 0 : scb_data->sense_dmamap, (caddr_t)scb_data->sense,
4340 0 : &scb_data->sense_seg, scb_data->sense_nseg);
4341 : /*FALLTHROUGH*/
4342 : case 3:
4343 0 : ahc_freedmamem(ahc->parent_dmat,
4344 : AHC_SCB_MAX * sizeof(struct hardware_scb),
4345 0 : scb_data->hscb_dmamap, (caddr_t)scb_data->hscbs,
4346 0 : &scb_data->hscb_seg, scb_data->hscb_nseg);
4347 : /*FALLTHROUGH*/
4348 : case 2:
4349 : case 1:
4350 : case 0:
4351 : break;
4352 : }
4353 0 : if (scb_data->scbarray != NULL)
4354 0 : free(scb_data->scbarray, M_DEVBUF, 0);
4355 0 : }
4356 :
4357 : void
4358 0 : ahc_alloc_scbs(struct ahc_softc *ahc)
4359 : {
4360 : struct scb_data *scb_data;
4361 : struct scb *next_scb;
4362 : struct sg_map_node *sg_map;
4363 : bus_addr_t physaddr;
4364 : struct ahc_dma_seg *segs;
4365 : int newcount;
4366 : int i;
4367 :
4368 0 : scb_data = ahc->scb_data;
4369 0 : if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4370 : /* Can't allocate any more */
4371 0 : return;
4372 :
4373 0 : next_scb = &scb_data->scbarray[scb_data->numscbs];
4374 :
4375 0 : sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4376 :
4377 0 : if (sg_map == NULL)
4378 0 : return;
4379 :
4380 : /* Allocate S/G space for the next batch of SCBS */
4381 0 : if (ahc_createdmamem(ahc->parent_dmat, PAGE_SIZE, ahc->sc_dmaflags,
4382 0 : &sg_map->sg_dmamap,
4383 0 : (caddr_t *)&sg_map->sg_vaddr, &sg_map->sg_physaddr,
4384 0 : &sg_map->sg_dmasegs, &sg_map->sg_nseg, ahc_name(ahc),
4385 0 : "SG space") < 0) {
4386 0 : free(sg_map, M_DEVBUF, 0);
4387 0 : return;
4388 : }
4389 :
4390 0 : SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4391 :
4392 0 : segs = sg_map->sg_vaddr;
4393 0 : physaddr = sg_map->sg_physaddr;
4394 :
4395 : newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4396 0 : newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4397 0 : for (i = 0; i < newcount; i++) {
4398 : int error;
4399 :
4400 0 : next_scb->sg_map = sg_map;
4401 0 : next_scb->sg_list = segs;
4402 : /*
4403 : * The sequencer always starts with the second entry.
4404 : * The first entry is embedded in the scb.
4405 : */
4406 0 : next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4407 0 : next_scb->ahc_softc = ahc;
4408 0 : next_scb->flags = SCB_FLAG_NONE;
4409 :
4410 0 : error = bus_dmamap_create(ahc->parent_dmat,
4411 : AHC_MAXTRANSFER_SIZE, AHC_NSEG, MAXPHYS, 0,
4412 : BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW|ahc->sc_dmaflags,
4413 : &next_scb->dmamap);
4414 0 : if (error != 0)
4415 0 : break;
4416 :
4417 0 : next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4418 0 : next_scb->hscb->tag = ahc->scb_data->numscbs;
4419 0 : mtx_enter(&ahc->sc_scb_mtx);
4420 0 : SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4421 : next_scb, links.sle);
4422 0 : mtx_leave(&ahc->sc_scb_mtx);
4423 0 : segs += AHC_NSEG;
4424 0 : physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4425 0 : next_scb++;
4426 0 : ahc->scb_data->numscbs++;
4427 0 : }
4428 0 : }
4429 :
4430 : #ifndef DEBUG
4431 : void
4432 0 : ahc_controller_info(struct ahc_softc *ahc, char *buf, size_t buf_len)
4433 : {
4434 : int len = 0;
4435 :
4436 0 : snprintf(buf + len, buf_len - len, "%s: ",
4437 0 : ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4438 0 : len = strlen(buf);
4439 0 : if ((ahc->features & AHC_TWIN) != 0)
4440 0 : snprintf(buf + len, buf_len - len,
4441 : "Twin Channel, primary %c, ",
4442 0 : (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4443 : else {
4444 : const char *speed;
4445 : const char *type;
4446 :
4447 : speed = "";
4448 0 : if ((ahc->features & AHC_ULTRA) != 0) {
4449 : speed = "Ultra ";
4450 0 : } else if ((ahc->features & AHC_DT) != 0) {
4451 : speed = "Ultra160 ";
4452 0 : } else if ((ahc->features & AHC_ULTRA2) != 0) {
4453 : speed = "Ultra2 ";
4454 0 : }
4455 0 : if ((ahc->features & AHC_WIDE) != 0) {
4456 : type = "Wide";
4457 0 : } else {
4458 : type = "Single";
4459 : }
4460 0 : snprintf(buf + len, buf_len - len,
4461 : "%s%s Channel %c, ",
4462 0 : speed, type, ahc->channel);
4463 : }
4464 0 : len = strlen(buf);
4465 :
4466 0 : if ((ahc->flags & AHC_PAGESCBS) != 0)
4467 0 : snprintf(buf + len, buf_len - len, "%d/%d SCBs",
4468 : ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4469 : else
4470 0 : snprintf(buf + len, buf_len - len, "%d SCBs",
4471 : ahc->scb_data->maxhscbs);
4472 0 : }
4473 : #endif /* !DEBUG */
4474 :
4475 : int
4476 0 : ahc_chip_init(struct ahc_softc *ahc)
4477 : {
4478 : int term;
4479 : int error;
4480 : u_int i;
4481 : u_int scsi_conf;
4482 : u_int scsiseq_template;
4483 : uint32_t physaddr;
4484 :
4485 0 : ahc_outb(ahc, SEQ_FLAGS, 0);
4486 0 : ahc_outb(ahc, SEQ_FLAGS2, 0);
4487 :
4488 : /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4489 0 : if (ahc->features & AHC_TWIN) {
4490 :
4491 : /*
4492 : * Setup Channel B first.
4493 : */
4494 0 : ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4495 0 : term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4496 0 : ahc_outb(ahc, SCSIID, ahc->our_id_b);
4497 0 : scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4498 0 : ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4499 : |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4500 0 : if ((ahc->features & AHC_ULTRA2) != 0)
4501 0 : ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4502 0 : ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4503 0 : ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4504 :
4505 : /* Select Channel A */
4506 0 : ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4507 0 : }
4508 0 : term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4509 0 : if ((ahc->features & AHC_ULTRA2) != 0)
4510 0 : ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4511 : else
4512 0 : ahc_outb(ahc, SCSIID, ahc->our_id);
4513 0 : scsi_conf = ahc_inb(ahc, SCSICONF);
4514 0 : ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4515 : |term|ahc->seltime
4516 : |ENSTIMER|ACTNEGEN);
4517 0 : if ((ahc->features & AHC_ULTRA2) != 0)
4518 0 : ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4519 0 : ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4520 0 : ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4521 :
4522 : /* There are no untagged SCBs active yet. */
4523 0 : for (i = 0; i < 16; i++) {
4524 0 : ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4525 0 : if ((ahc->flags & AHC_SCB_BTT) != 0) {
4526 : int lun;
4527 :
4528 : /*
4529 : * The SCB based BTT allows an entry per
4530 : * target and lun pair.
4531 : */
4532 0 : for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4533 0 : ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4534 0 : }
4535 : }
4536 :
4537 : /* All of our queues are empty */
4538 0 : for (i = 0; i < 256; i++)
4539 0 : ahc->qoutfifo[i] = SCB_LIST_NULL;
4540 : #ifdef __sgi__
4541 : ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
4542 : #else
4543 0 : ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4544 : #endif
4545 0 : for (i = 0; i < 256; i++)
4546 0 : ahc->qinfifo[i] = SCB_LIST_NULL;
4547 :
4548 0 : if ((ahc->features & AHC_MULTI_TID) != 0) {
4549 0 : ahc_outb(ahc, TARGID, 0);
4550 0 : ahc_outb(ahc, TARGID + 1, 0);
4551 0 : }
4552 :
4553 : /*
4554 : * Tell the sequencer where it can find our arrays in memory.
4555 : */
4556 0 : physaddr = ahc->scb_data->hscb_busaddr;
4557 0 : ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4558 0 : ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4559 0 : ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4560 0 : ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4561 :
4562 0 : physaddr = ahc->shared_data_busaddr;
4563 0 : ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4564 0 : ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4565 0 : ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4566 0 : ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4567 :
4568 : /*
4569 : * Initialize the group code to command length table.
4570 : * This overrides the values in TARG_SCSIRATE, so only
4571 : * setup the table after we have processed that information.
4572 : */
4573 0 : ahc_outb(ahc, CMDSIZE_TABLE, 5);
4574 0 : ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4575 0 : ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4576 0 : ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4577 0 : ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4578 0 : ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4579 0 : ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4580 0 : ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4581 :
4582 0 : if ((ahc->features & AHC_HS_MAILBOX) != 0)
4583 0 : ahc_outb(ahc, HS_MAILBOX, 0);
4584 :
4585 : /* Tell the sequencer of our initial queue positions */
4586 0 : if ((ahc->features & AHC_TARGETMODE) != 0) {
4587 0 : ahc->tqinfifonext = 1;
4588 0 : ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4589 0 : ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4590 0 : }
4591 0 : ahc->qinfifonext = 0;
4592 0 : ahc->qoutfifonext = 0;
4593 0 : if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4594 0 : ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4595 0 : ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4596 0 : ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4597 0 : ahc_outb(ahc, SDSCB_QOFF, 0);
4598 0 : } else {
4599 0 : ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4600 0 : ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4601 0 : ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4602 : }
4603 :
4604 : /* We don't have any waiting selections */
4605 0 : ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4606 :
4607 : /* Our disconnection list is empty too */
4608 0 : ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4609 :
4610 : /* Message out buffer starts empty */
4611 0 : ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4612 :
4613 : /*
4614 : * Setup the allowed SCSI Sequences based on operational mode.
4615 : * If we are a target, we'll enable select in operations once
4616 : * we've had a lun enabled.
4617 : */
4618 : scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4619 0 : if ((ahc->flags & AHC_INITIATORROLE) != 0)
4620 0 : scsiseq_template |= ENRSELI;
4621 0 : ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4622 :
4623 : /* Initialize our list of free SCBs. */
4624 0 : ahc_build_free_scb_list(ahc);
4625 :
4626 : /*
4627 : * Tell the sequencer which SCB will be the next one it receives.
4628 : */
4629 0 : ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4630 :
4631 : /*
4632 : * Load the Sequencer program and Enable the adapter
4633 : * in "fast" mode.
4634 : */
4635 : if (bootverbose)
4636 : printf("%s: Downloading Sequencer Program...",
4637 : ahc_name(ahc));
4638 :
4639 0 : error = ahc_loadseq(ahc);
4640 0 : if (error != 0)
4641 0 : return (error);
4642 :
4643 0 : if ((ahc->features & AHC_ULTRA2) != 0) {
4644 : int wait;
4645 :
4646 : /*
4647 : * Wait for up to 500ms for our transceivers
4648 : * to settle. If the adapter does not have
4649 : * a cable attached, the transceivers may
4650 : * never settle, so don't complain if we
4651 : * fail here.
4652 : */
4653 0 : for (wait = 5000;
4654 0 : (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4655 0 : wait--)
4656 0 : aic_delay(100);
4657 0 : }
4658 0 : ahc_restart(ahc);
4659 0 : return (0);
4660 0 : }
4661 :
4662 : /*
4663 : * Start the board, ready for normal operation
4664 : */
4665 : int
4666 0 : ahc_init(struct ahc_softc *ahc)
4667 : {
4668 : int max_targ;
4669 : u_int i;
4670 : u_int scsi_conf;
4671 : u_int ultraenb;
4672 : u_int discenable;
4673 : u_int tagenable;
4674 : size_t driver_data_size;
4675 :
4676 : #ifdef AHC_DEBUG
4677 : if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4678 : ahc->flags |= AHC_SEQUENCER_DEBUG;
4679 : #endif
4680 :
4681 : #ifdef AHC_PRINT_SRAM
4682 : printf("Scratch Ram:");
4683 : for (i = 0x20; i < 0x5f; i++) {
4684 : if (((i % 8) == 0) && (i != 0)) {
4685 : printf ("\n ");
4686 : }
4687 : printf (" 0x%x", ahc_inb(ahc, i));
4688 : }
4689 : if ((ahc->features & AHC_MORE_SRAM) != 0) {
4690 : for (i = 0x70; i < 0x7f; i++) {
4691 : if (((i % 8) == 0) && (i != 0)) {
4692 : printf ("\n ");
4693 : }
4694 : printf (" 0x%x", ahc_inb(ahc, i));
4695 : }
4696 : }
4697 : printf ("\n");
4698 : /*
4699 : * Reading uninitialized scratch ram may
4700 : * generate parity errors.
4701 : */
4702 : ahc_outb(ahc, CLRINT, CLRPARERR);
4703 : ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4704 : #endif
4705 : max_targ = 15;
4706 :
4707 : /*
4708 : * Assume we have a board at this stage and it has been reset.
4709 : */
4710 0 : if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4711 0 : ahc->our_id = ahc->our_id_b = 7;
4712 :
4713 : /*
4714 : * Default to allowing initiator operations.
4715 : */
4716 0 : ahc->flags |= AHC_INITIATORROLE;
4717 :
4718 : /*
4719 : * Only allow target mode features if this unit has them enabled.
4720 : */
4721 : //if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4722 0 : ahc->features &= ~AHC_TARGETMODE;
4723 :
4724 : /*
4725 : * DMA tag for our command fifos and other data in system memory
4726 : * the card's sequencer must be able to access. For initiator
4727 : * roles, we need to allocate space for the qinfifo and qoutfifo.
4728 : * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4729 : * When providing for the target mode role, we must additionally
4730 : * provide space for the incoming target command fifo and an extra
4731 : * byte to deal with a DMA bug in some chip versions.
4732 : */
4733 : driver_data_size = 2 * 256 * sizeof(uint8_t);
4734 0 : if ((ahc->features & AHC_TARGETMODE) != 0)
4735 0 : driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4736 : + /*DMA WideOdd Bug Buffer*/1;
4737 :
4738 0 : ahc->init_level++;
4739 :
4740 0 : if (ahc_createdmamem(ahc->parent_dmat, driver_data_size,
4741 0 : ahc->sc_dmaflags,
4742 0 : &ahc->shared_data_dmamap, (caddr_t *)&ahc->qoutfifo,
4743 0 : &ahc->shared_data_busaddr, &ahc->shared_data_seg,
4744 0 : &ahc->shared_data_nseg, ahc_name(ahc), "shared data") < 0)
4745 0 : return (ENOMEM);
4746 :
4747 0 : ahc->init_level++;
4748 :
4749 0 : if ((ahc->features & AHC_TARGETMODE) != 0) {
4750 0 : ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4751 0 : ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4752 0 : ahc->dma_bug_buf = ahc->shared_data_busaddr
4753 0 : + driver_data_size - 1;
4754 : /* All target command blocks start out invalid. */
4755 0 : for (i = 0; i < AHC_TMODE_CMDS; i++)
4756 0 : ahc->targetcmds[i].cmd_valid = 0;
4757 : #ifdef __sgi__
4758 : ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
4759 : #else
4760 0 : ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4761 : #endif
4762 0 : ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4763 0 : }
4764 0 : ahc->qinfifo = &ahc->qoutfifo[256];
4765 :
4766 0 : ahc->init_level++;
4767 :
4768 : /* Allocate SCB data now that buffer_dmat is initialized */
4769 0 : if (ahc->scb_data->maxhscbs == 0)
4770 0 : if (ahc_init_scbdata(ahc) != 0)
4771 0 : return (ENOMEM);
4772 :
4773 : /*
4774 : * Allocate a tstate to house information for our
4775 : * initiator presence on the bus as well as the user
4776 : * data for any target mode initiator.
4777 : */
4778 0 : if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4779 0 : printf("%s: unable to allocate ahc_tmode_tstate. "
4780 0 : "Failing attach\n", ahc_name(ahc));
4781 0 : return (ENOMEM);
4782 : }
4783 :
4784 0 : if ((ahc->features & AHC_TWIN) != 0) {
4785 0 : if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4786 0 : printf("%s: unable to allocate ahc_tmode_tstate. "
4787 0 : "Failing attach\n", ahc_name(ahc));
4788 0 : return (ENOMEM);
4789 : }
4790 : }
4791 :
4792 0 : ahc_outb(ahc, SEQ_FLAGS, 0);
4793 0 : ahc_outb(ahc, SEQ_FLAGS2, 0);
4794 :
4795 0 : if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4796 0 : ahc->flags |= AHC_PAGESCBS;
4797 0 : } else {
4798 0 : ahc->flags &= ~AHC_PAGESCBS;
4799 : }
4800 :
4801 : #ifdef AHC_DEBUG
4802 : if (ahc_debug & AHC_SHOW_MISC) {
4803 : printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4804 : "ahc_dma %u bytes\n",
4805 : ahc_name(ahc),
4806 : (u_int)sizeof(struct hardware_scb),
4807 : (u_int)sizeof(struct scb),
4808 : (u_int)sizeof(struct ahc_dma_seg));
4809 : }
4810 : #endif /* AHC_DEBUG */
4811 :
4812 : /*
4813 : * Look at the information that board initialization or
4814 : * the board bios has left us.
4815 : */
4816 0 : if (ahc->features & AHC_TWIN) {
4817 0 : scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4818 0 : if ((scsi_conf & RESET_SCSI) != 0
4819 0 : && (ahc->flags & AHC_INITIATORROLE) != 0)
4820 0 : ahc->flags |= AHC_RESET_BUS_B;
4821 : }
4822 :
4823 0 : scsi_conf = ahc_inb(ahc, SCSICONF);
4824 0 : if ((scsi_conf & RESET_SCSI) != 0
4825 0 : && (ahc->flags & AHC_INITIATORROLE) != 0)
4826 0 : ahc->flags |= AHC_RESET_BUS_A;
4827 :
4828 : ultraenb = 0;
4829 : tagenable = ALL_TARGETS_MASK;
4830 :
4831 : /* Grab the disconnection disable table and invert it for our needs */
4832 0 : if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
4833 0 : printf("%s: Host Adapter Bios disabled. Using default SCSI "
4834 0 : "device parameters\n", ahc_name(ahc));
4835 0 : ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4836 : AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4837 : discenable = ALL_TARGETS_MASK;
4838 0 : if ((ahc->features & AHC_ULTRA) != 0)
4839 0 : ultraenb = ALL_TARGETS_MASK;
4840 : } else {
4841 0 : discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4842 0 : | ahc_inb(ahc, DISC_DSB));
4843 0 : if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4844 0 : ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4845 0 : | ahc_inb(ahc, ULTRA_ENB);
4846 : }
4847 :
4848 0 : if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4849 0 : max_targ = 7;
4850 :
4851 0 : for (i = 0; i <= max_targ; i++) {
4852 : struct ahc_initiator_tinfo *tinfo;
4853 0 : struct ahc_tmode_tstate *tstate;
4854 : u_int our_id;
4855 : u_int target_id;
4856 : char channel;
4857 :
4858 : channel = 'A';
4859 0 : our_id = ahc->our_id;
4860 : target_id = i;
4861 0 : if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4862 : channel = 'B';
4863 0 : our_id = ahc->our_id_b;
4864 0 : target_id = i % 8;
4865 0 : }
4866 0 : tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4867 : target_id, &tstate);
4868 : /* Default to async narrow across the board */
4869 0 : memset(tinfo, 0, sizeof(*tinfo));
4870 0 : if (ahc->flags & AHC_USEDEFAULTS) {
4871 0 : if ((ahc->features & AHC_WIDE) != 0)
4872 0 : tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4873 :
4874 : /*
4875 : * These will be truncated when we determine the
4876 : * connection type we have with the target.
4877 : */
4878 0 : tinfo->user.period = ahc_syncrates->period;
4879 0 : tinfo->user.offset = MAX_OFFSET;
4880 0 : } else {
4881 : u_int scsirate;
4882 : uint16_t mask;
4883 :
4884 : /* Take the settings leftover in scratch RAM. */
4885 0 : scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
4886 0 : mask = (0x01 << i);
4887 0 : if ((ahc->features & AHC_ULTRA2) != 0) {
4888 : u_int offset;
4889 : u_int maxsync;
4890 :
4891 0 : if ((scsirate & SOFS) == 0x0F) {
4892 : /*
4893 : * Haven't negotiated yet,
4894 : * so the format is different.
4895 : */
4896 0 : scsirate = (scsirate & SXFR) >> 4
4897 0 : | (ultraenb & mask)
4898 : ? 0x08 : 0x0
4899 0 : | (scsirate & WIDEXFER);
4900 : offset = MAX_OFFSET_ULTRA2;
4901 0 : } else
4902 0 : offset = ahc_inb(ahc, TARG_OFFSET + i);
4903 0 : if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
4904 : /* Set to the lowest sync rate, 5MHz */
4905 0 : scsirate |= 0x1c;
4906 : maxsync = AHC_SYNCRATE_ULTRA2;
4907 0 : if ((ahc->features & AHC_DT) != 0)
4908 : maxsync = AHC_SYNCRATE_DT;
4909 0 : tinfo->user.period =
4910 0 : ahc_find_period(ahc, scsirate, maxsync);
4911 0 : if (offset == 0)
4912 0 : tinfo->user.period = 0;
4913 : else
4914 0 : tinfo->user.offset = MAX_OFFSET;
4915 0 : if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
4916 0 : && (ahc->features & AHC_DT) != 0)
4917 0 : tinfo->user.ppr_options =
4918 : MSG_EXT_PPR_DT_REQ;
4919 0 : } else if ((scsirate & SOFS) != 0) {
4920 0 : if ((scsirate & SXFR) == 0x40
4921 0 : && (ultraenb & mask) != 0) {
4922 : /* Treat 10MHz as a non-ultra speed */
4923 0 : scsirate &= ~SXFR;
4924 0 : ultraenb &= ~mask;
4925 0 : }
4926 0 : tinfo->user.period =
4927 0 : ahc_find_period(ahc, scsirate,
4928 0 : (ultraenb & mask)
4929 : ? AHC_SYNCRATE_ULTRA
4930 : : AHC_SYNCRATE_FAST);
4931 0 : if (tinfo->user.period != 0)
4932 0 : tinfo->user.offset = MAX_OFFSET;
4933 : }
4934 0 : if (tinfo->user.period == 0)
4935 0 : tinfo->user.offset = 0;
4936 0 : if ((scsirate & WIDEXFER) != 0
4937 0 : && (ahc->features & AHC_WIDE) != 0)
4938 0 : tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4939 0 : tinfo->user.protocol_version = 4;
4940 0 : if ((ahc->features & AHC_DT) != 0)
4941 0 : tinfo->user.transport_version = 3;
4942 : else
4943 0 : tinfo->user.transport_version = 2;
4944 0 : tinfo->goal.protocol_version = 2;
4945 0 : tinfo->goal.transport_version = 2;
4946 0 : tinfo->curr.protocol_version = 2;
4947 0 : tinfo->curr.transport_version = 2;
4948 : }
4949 0 : tstate->ultraenb = 0;
4950 0 : tstate->discenable = discenable;
4951 0 : }
4952 0 : ahc->user_discenable = discenable;
4953 0 : ahc->user_tagenable = tagenable;
4954 :
4955 0 : return (ahc->bus_chip_init(ahc));
4956 0 : }
4957 :
4958 : void
4959 0 : ahc_intr_enable(struct ahc_softc *ahc, int enable)
4960 : {
4961 : u_int hcntrl;
4962 :
4963 0 : hcntrl = ahc_inb(ahc, HCNTRL);
4964 0 : hcntrl &= ~INTEN;
4965 0 : ahc->pause &= ~INTEN;
4966 0 : ahc->unpause &= ~INTEN;
4967 0 : if (enable) {
4968 0 : hcntrl |= INTEN;
4969 0 : ahc->pause |= INTEN;
4970 0 : ahc->unpause |= INTEN;
4971 0 : }
4972 0 : ahc_outb(ahc, HCNTRL, hcntrl);
4973 0 : }
4974 :
4975 : /************************** Busy Target Table *********************************/
4976 : /*
4977 : * Return the untagged transaction id for a given target/channel lun.
4978 : * Optionally, clear the entry.
4979 : */
4980 : u_int
4981 0 : ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
4982 : {
4983 : u_int scbid;
4984 : u_int target_offset;
4985 :
4986 0 : if ((ahc->flags & AHC_SCB_BTT) != 0) {
4987 : u_int saved_scbptr;
4988 :
4989 0 : saved_scbptr = ahc_inb(ahc, SCBPTR);
4990 0 : ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
4991 0 : scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
4992 0 : ahc_outb(ahc, SCBPTR, saved_scbptr);
4993 0 : } else {
4994 0 : target_offset = TCL_TARGET_OFFSET(tcl);
4995 0 : scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
4996 : }
4997 :
4998 0 : return (scbid);
4999 : }
5000 :
5001 : void
5002 0 : ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5003 : {
5004 : u_int target_offset;
5005 :
5006 0 : if ((ahc->flags & AHC_SCB_BTT) != 0) {
5007 : u_int saved_scbptr;
5008 :
5009 0 : saved_scbptr = ahc_inb(ahc, SCBPTR);
5010 0 : ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5011 0 : ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5012 0 : ahc_outb(ahc, SCBPTR, saved_scbptr);
5013 0 : } else {
5014 0 : target_offset = TCL_TARGET_OFFSET(tcl);
5015 0 : ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5016 : }
5017 0 : }
5018 :
5019 : void
5020 0 : ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5021 : {
5022 : u_int target_offset;
5023 :
5024 0 : if ((ahc->flags & AHC_SCB_BTT) != 0) {
5025 : u_int saved_scbptr;
5026 :
5027 0 : saved_scbptr = ahc_inb(ahc, SCBPTR);
5028 0 : ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5029 0 : ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5030 0 : ahc_outb(ahc, SCBPTR, saved_scbptr);
5031 0 : } else {
5032 0 : target_offset = TCL_TARGET_OFFSET(tcl);
5033 0 : ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5034 : }
5035 0 : }
5036 :
5037 : /************************** SCB and SCB queue management **********************/
5038 : int
5039 0 : ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5040 : char channel, int lun, u_int tag, role_t role)
5041 : {
5042 : char chan;
5043 : int targ, slun, match;
5044 :
5045 0 : if (scb == NULL)
5046 0 : return 0;
5047 :
5048 0 : targ = SCB_GET_TARGET(ahc, scb);
5049 0 : chan = SCB_GET_CHANNEL(ahc, scb);
5050 0 : slun = SCB_GET_LUN(scb);
5051 :
5052 0 : match = ((chan == channel) || (channel == ALL_CHANNELS));
5053 0 : if (match != 0)
5054 0 : match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5055 0 : if (match != 0)
5056 0 : match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5057 0 : if (match != 0) {
5058 : #ifdef AHC_TARGET_MODE
5059 : int group;
5060 :
5061 : group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5062 : if (role == ROLE_INITIATOR) {
5063 : match = (group != XPT_FC_GROUP_TMODE)
5064 : && ((tag == scb->hscb->tag)
5065 : || (tag == SCB_LIST_NULL));
5066 : } else if (role == ROLE_TARGET) {
5067 : match = (group == XPT_FC_GROUP_TMODE)
5068 : && ((tag == scb->io_ctx->csio.tag_id)
5069 : || (tag == SCB_LIST_NULL));
5070 : }
5071 : #else /* !AHC_TARGET_MODE */
5072 0 : match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5073 : #endif /* AHC_TARGET_MODE */
5074 0 : }
5075 :
5076 0 : return match;
5077 0 : }
5078 :
5079 : void
5080 0 : ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5081 : {
5082 : int target;
5083 : char channel;
5084 : int lun;
5085 :
5086 0 : target = SCB_GET_TARGET(ahc, scb);
5087 0 : lun = SCB_GET_LUN(scb);
5088 0 : channel = SCB_GET_CHANNEL(ahc, scb);
5089 :
5090 0 : ahc_search_qinfifo(ahc, target, channel, lun,
5091 : /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5092 : CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5093 0 : }
5094 :
5095 : void
5096 0 : ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5097 : {
5098 : struct scb *prev_scb;
5099 :
5100 : prev_scb = NULL;
5101 0 : if (ahc_qinfifo_count(ahc) != 0) {
5102 : u_int prev_tag;
5103 : uint8_t prev_pos;
5104 :
5105 0 : prev_pos = ahc->qinfifonext - 1;
5106 0 : prev_tag = ahc->qinfifo[prev_pos];
5107 0 : prev_scb = ahc_lookup_scb(ahc, prev_tag);
5108 0 : }
5109 0 : ahc_qinfifo_requeue(ahc, prev_scb, scb);
5110 0 : if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5111 0 : ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5112 0 : } else {
5113 0 : ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5114 : }
5115 0 : }
5116 :
5117 : static void
5118 0 : ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5119 : struct scb *scb)
5120 : {
5121 0 : if (prev_scb == NULL) {
5122 0 : ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5123 0 : } else {
5124 0 : prev_scb->hscb->next = scb->hscb->tag;
5125 0 : ahc_sync_scb(ahc, prev_scb,
5126 : BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5127 : }
5128 0 : ahc->qinfifo[ahc->qinfifonext] = scb->hscb->tag;
5129 0 : ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap,
5130 : /*offset*/ahc->qinfifonext+256, /*len*/1,
5131 : BUS_DMASYNC_PREWRITE);
5132 0 : ahc->qinfifonext++;
5133 0 : scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5134 0 : ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5135 0 : }
5136 :
5137 : static int
5138 0 : ahc_qinfifo_count(struct ahc_softc *ahc)
5139 : {
5140 : uint8_t qinpos;
5141 : uint8_t diff;
5142 :
5143 0 : if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5144 0 : qinpos = ahc_inb(ahc, SNSCB_QOFF);
5145 0 : ahc_outb(ahc, SNSCB_QOFF, qinpos);
5146 0 : } else
5147 0 : qinpos = ahc_inb(ahc, QINPOS);
5148 0 : diff = ahc->qinfifonext - qinpos;
5149 0 : return (diff);
5150 : }
5151 :
5152 : int
5153 0 : ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5154 : int lun, u_int tag, role_t role, uint32_t status,
5155 : ahc_search_action action)
5156 : {
5157 : struct scb *scb;
5158 : struct scb *prev_scb;
5159 : uint8_t qinstart;
5160 : uint8_t qinpos;
5161 : uint8_t qintail;
5162 : uint8_t next;
5163 : uint8_t prev;
5164 : uint8_t curscbptr;
5165 : int found;
5166 : int have_qregs;
5167 :
5168 0 : qintail = ahc->qinfifonext;
5169 0 : have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5170 0 : if (have_qregs) {
5171 0 : qinstart = ahc_inb(ahc, SNSCB_QOFF);
5172 0 : ahc_outb(ahc, SNSCB_QOFF, qinstart);
5173 0 : } else
5174 0 : qinstart = ahc_inb(ahc, QINPOS);
5175 : qinpos = qinstart;
5176 : found = 0;
5177 : prev_scb = NULL;
5178 :
5179 0 : if (action == SEARCH_COMPLETE) {
5180 : /*
5181 : * Don't attempt to run any queued untagged transactions
5182 : * until we are done with the abort process.
5183 : */
5184 0 : ahc_freeze_untagged_queues(ahc);
5185 0 : }
5186 :
5187 : /*
5188 : * Start with an empty queue. Entries that are not chosen
5189 : * for removal will be re-added to the queue as we go.
5190 : */
5191 0 : ahc->qinfifonext = qinpos;
5192 0 : ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5193 :
5194 0 : while (qinpos != qintail) {
5195 0 : scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5196 0 : if (scb == NULL) {
5197 0 : printf("qinpos = %d, SCB index = %d\n",
5198 0 : qinpos, ahc->qinfifo[qinpos]);
5199 0 : panic("Loop 1");
5200 : }
5201 :
5202 0 : if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5203 : /*
5204 : * We found an scb that needs to be acted on.
5205 : */
5206 0 : found++;
5207 0 : switch (action) {
5208 : case SEARCH_COMPLETE:
5209 : {
5210 : cam_status ostat;
5211 : cam_status cstat;
5212 :
5213 0 : ostat = ahc_get_transaction_status(scb);
5214 0 : if (ostat == CAM_REQ_INPROG)
5215 0 : ahc_set_transaction_status(scb, status);
5216 0 : cstat = ahc_get_transaction_status(scb);
5217 0 : if (cstat != CAM_REQ_CMP)
5218 0 : ahc_freeze_scb(scb);
5219 0 : if ((scb->flags & SCB_ACTIVE) == 0)
5220 0 : printf("Inactive SCB in qinfifo\n");
5221 0 : ahc_done(ahc, scb);
5222 :
5223 : /* FALLTHROUGH */
5224 0 : }
5225 : case SEARCH_REMOVE:
5226 : break;
5227 : case SEARCH_COUNT:
5228 0 : ahc_qinfifo_requeue(ahc, prev_scb, scb);
5229 : prev_scb = scb;
5230 0 : break;
5231 : }
5232 : } else {
5233 0 : ahc_qinfifo_requeue(ahc, prev_scb, scb);
5234 : prev_scb = scb;
5235 : }
5236 0 : qinpos++;
5237 : }
5238 :
5239 0 : if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5240 0 : ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5241 0 : } else {
5242 0 : ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5243 : }
5244 :
5245 0 : if (action != SEARCH_COUNT
5246 0 : && (found != 0)
5247 0 : && (qinstart != ahc->qinfifonext)) {
5248 : /*
5249 : * The sequencer may be in the process of DMA'ing
5250 : * down the SCB at the beginning of the queue.
5251 : * This could be problematic if either the first,
5252 : * or the second SCB is removed from the queue
5253 : * (the first SCB includes a pointer to the "next"
5254 : * SCB to DMA). If we have removed any entries, swap
5255 : * the first element in the queue with the next HSCB
5256 : * so the sequencer will notice that NEXT_QUEUED_SCB
5257 : * has changed during its DMA attempt and will retry
5258 : * the DMA.
5259 : */
5260 0 : scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5261 :
5262 0 : if (scb == NULL) {
5263 0 : printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5264 0 : found, qinstart, ahc->qinfifonext);
5265 0 : panic("First/Second Qinfifo fixup");
5266 : }
5267 : /*
5268 : * ahc_swap_with_next_hscb forces our next pointer to
5269 : * point to the reserved SCB for future commands. Save
5270 : * and restore our original next pointer to maintain
5271 : * queue integrity.
5272 : */
5273 0 : next = scb->hscb->next;
5274 0 : ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5275 0 : ahc_swap_with_next_hscb(ahc, scb);
5276 0 : scb->hscb->next = next;
5277 0 : ahc->qinfifo[qinstart] = scb->hscb->tag;
5278 :
5279 : /* Tell the card about the new head of the qinfifo. */
5280 0 : ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5281 :
5282 : /* Fixup the tail "next" pointer. */
5283 0 : qintail = ahc->qinfifonext - 1;
5284 0 : scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5285 0 : scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5286 0 : }
5287 :
5288 : /*
5289 : * Search waiting for selection list.
5290 : */
5291 0 : curscbptr = ahc_inb(ahc, SCBPTR);
5292 0 : next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5293 : prev = SCB_LIST_NULL;
5294 :
5295 0 : while (next != SCB_LIST_NULL) {
5296 : uint8_t scb_index;
5297 :
5298 0 : ahc_outb(ahc, SCBPTR, next);
5299 0 : scb_index = ahc_inb(ahc, SCB_TAG);
5300 0 : if (scb_index >= ahc->scb_data->numscbs) {
5301 0 : printf("Waiting List inconsistency. "
5302 : "SCB index == %d, yet numscbs == %d.",
5303 : scb_index, ahc->scb_data->numscbs);
5304 0 : ahc_dump_card_state(ahc);
5305 0 : panic("for safety");
5306 : }
5307 0 : scb = ahc_lookup_scb(ahc, scb_index);
5308 0 : if (scb == NULL) {
5309 0 : printf("scb_index = %d, next = %d\n",
5310 : scb_index, next);
5311 0 : panic("Waiting List traversal");
5312 : }
5313 0 : if (ahc_match_scb(ahc, scb, target, channel,
5314 : lun, SCB_LIST_NULL, role)) {
5315 : /*
5316 : * We found an scb that needs to be acted on.
5317 : */
5318 0 : found++;
5319 0 : switch (action) {
5320 : case SEARCH_COMPLETE:
5321 : {
5322 : cam_status ostat;
5323 : cam_status cstat;
5324 :
5325 0 : ostat = ahc_get_transaction_status(scb);
5326 0 : if (ostat == CAM_REQ_INPROG)
5327 0 : ahc_set_transaction_status(scb, status);
5328 0 : cstat = ahc_get_transaction_status(scb);
5329 0 : if (cstat != CAM_REQ_CMP)
5330 0 : ahc_freeze_scb(scb);
5331 0 : if ((scb->flags & SCB_ACTIVE) == 0)
5332 0 : printf("Inactive SCB in Wait List\n");
5333 0 : ahc_done(ahc, scb);
5334 : /* FALLTHROUGH */
5335 0 : }
5336 : case SEARCH_REMOVE:
5337 0 : next = ahc_rem_wscb(ahc, next, prev);
5338 0 : break;
5339 : case SEARCH_COUNT:
5340 : prev = next;
5341 0 : next = ahc_inb(ahc, SCB_NEXT);
5342 0 : break;
5343 : }
5344 : } else {
5345 :
5346 : prev = next;
5347 0 : next = ahc_inb(ahc, SCB_NEXT);
5348 : }
5349 : }
5350 0 : ahc_outb(ahc, SCBPTR, curscbptr);
5351 :
5352 0 : found += ahc_search_untagged_queues(ahc, /*scsi_xfer*/NULL, target,
5353 : channel, lun, status, action);
5354 :
5355 0 : if (action == SEARCH_COMPLETE)
5356 0 : ahc_release_untagged_queues(ahc);
5357 0 : return (found);
5358 : }
5359 :
5360 : int
5361 0 : ahc_search_untagged_queues(struct ahc_softc *ahc, struct scsi_xfer *xs,
5362 : int target, char channel, int lun, uint32_t status,
5363 : ahc_search_action action)
5364 : {
5365 : struct scb *scb;
5366 : int maxtarget;
5367 : int found;
5368 : int i;
5369 :
5370 0 : if (action == SEARCH_COMPLETE) {
5371 : /*
5372 : * Don't attempt to run any queued untagged transactions
5373 : * until we are done with the abort process.
5374 : */
5375 0 : ahc_freeze_untagged_queues(ahc);
5376 0 : }
5377 :
5378 : found = 0;
5379 : i = 0;
5380 0 : if ((ahc->flags & AHC_SCB_BTT) == 0) {
5381 :
5382 : maxtarget = 16;
5383 0 : if (target != CAM_TARGET_WILDCARD) {
5384 :
5385 : i = target;
5386 0 : if (channel == 'B')
5387 0 : i += 8;
5388 0 : maxtarget = i + 1;
5389 0 : }
5390 : } else {
5391 : maxtarget = 0;
5392 : }
5393 :
5394 0 : for (; i < maxtarget; i++) {
5395 : struct scb_tailq *untagged_q;
5396 : struct scb *next_scb;
5397 :
5398 0 : untagged_q = &(ahc->untagged_queues[i]);
5399 0 : next_scb = TAILQ_FIRST(untagged_q);
5400 0 : while (next_scb != NULL) {
5401 :
5402 : scb = next_scb;
5403 0 : next_scb = TAILQ_NEXT(scb, links.tqe);
5404 :
5405 : /*
5406 : * The head of the list may be the currently
5407 : * active untagged command for a device.
5408 : * We're only searching for commands that
5409 : * have not been started. A transaction
5410 : * marked active but still in the qinfifo
5411 : * is removed by the qinfifo scanning code
5412 : * above.
5413 : */
5414 0 : if ((scb->flags & SCB_ACTIVE) != 0)
5415 0 : continue;
5416 :
5417 0 : if (ahc_match_scb(ahc, scb, target, channel, lun,
5418 0 : SCB_LIST_NULL, ROLE_INITIATOR) == 0
5419 0 : || (xs != NULL && xs != scb->xs))
5420 0 : continue;
5421 :
5422 : /*
5423 : * We found an scb that needs to be acted on.
5424 : */
5425 0 : found++;
5426 0 : switch (action) {
5427 : case SEARCH_COMPLETE:
5428 : {
5429 : cam_status ostat;
5430 : cam_status cstat;
5431 :
5432 0 : ostat = ahc_get_transaction_status(scb);
5433 0 : if (ostat == CAM_REQ_INPROG)
5434 0 : ahc_set_transaction_status(scb, status);
5435 0 : cstat = ahc_get_transaction_status(scb);
5436 0 : if (cstat != CAM_REQ_CMP)
5437 0 : ahc_freeze_scb(scb);
5438 0 : ahc_done(ahc, scb);
5439 : break;
5440 : }
5441 : case SEARCH_REMOVE:
5442 0 : scb->flags &= ~SCB_UNTAGGEDQ;
5443 0 : TAILQ_REMOVE(untagged_q, scb, links.tqe);
5444 0 : break;
5445 : case SEARCH_COUNT:
5446 : break;
5447 : }
5448 : }
5449 : }
5450 :
5451 0 : if (action == SEARCH_COMPLETE)
5452 0 : ahc_release_untagged_queues(ahc);
5453 0 : return (found);
5454 : }
5455 :
5456 : int
5457 0 : ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5458 : int lun, u_int tag, int stop_on_first, int remove,
5459 : int save_state)
5460 : {
5461 : struct scb *scbp;
5462 : u_int next;
5463 : u_int prev;
5464 : u_int count;
5465 : u_int active_scb;
5466 :
5467 : count = 0;
5468 0 : next = ahc_inb(ahc, DISCONNECTED_SCBH);
5469 : prev = SCB_LIST_NULL;
5470 :
5471 0 : if (save_state) {
5472 : /* restore this when we're done */
5473 0 : active_scb = ahc_inb(ahc, SCBPTR);
5474 0 : } else
5475 : /* Silence compiler */
5476 : active_scb = SCB_LIST_NULL;
5477 :
5478 0 : while (next != SCB_LIST_NULL) {
5479 : u_int scb_index;
5480 :
5481 0 : ahc_outb(ahc, SCBPTR, next);
5482 0 : scb_index = ahc_inb(ahc, SCB_TAG);
5483 0 : if (scb_index >= ahc->scb_data->numscbs) {
5484 0 : printf("Disconnected List inconsistency. "
5485 : "SCB index == %d, yet numscbs == %d.",
5486 : scb_index, ahc->scb_data->numscbs);
5487 0 : ahc_dump_card_state(ahc);
5488 0 : panic("for safety");
5489 : }
5490 :
5491 0 : if (next == prev) {
5492 0 : panic("Disconnected List Loop. "
5493 : "cur SCBPTR == %x, prev SCBPTR == %x.",
5494 : next, prev);
5495 : }
5496 0 : scbp = ahc_lookup_scb(ahc, scb_index);
5497 0 : if (ahc_match_scb(ahc, scbp, target, channel, lun,
5498 : tag, ROLE_INITIATOR)) {
5499 0 : count++;
5500 0 : if (remove) {
5501 : next =
5502 0 : ahc_rem_scb_from_disc_list(ahc, prev, next);
5503 0 : } else {
5504 : prev = next;
5505 0 : next = ahc_inb(ahc, SCB_NEXT);
5506 : }
5507 0 : if (stop_on_first)
5508 0 : break;
5509 : } else {
5510 : prev = next;
5511 0 : next = ahc_inb(ahc, SCB_NEXT);
5512 : }
5513 0 : }
5514 0 : if (save_state)
5515 0 : ahc_outb(ahc, SCBPTR, active_scb);
5516 0 : return (count);
5517 : }
5518 :
5519 : /*
5520 : * Remove an SCB from the on chip list of disconnected transactions.
5521 : * This is empty/unused if we are not performing SCB paging.
5522 : */
5523 : static u_int
5524 0 : ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5525 : {
5526 : u_int next;
5527 :
5528 0 : ahc_outb(ahc, SCBPTR, scbptr);
5529 0 : next = ahc_inb(ahc, SCB_NEXT);
5530 :
5531 0 : ahc_outb(ahc, SCB_CONTROL, 0);
5532 :
5533 0 : ahc_add_curscb_to_free_list(ahc);
5534 :
5535 0 : if (prev != SCB_LIST_NULL) {
5536 0 : ahc_outb(ahc, SCBPTR, prev);
5537 0 : ahc_outb(ahc, SCB_NEXT, next);
5538 0 : } else
5539 0 : ahc_outb(ahc, DISCONNECTED_SCBH, next);
5540 :
5541 0 : return (next);
5542 : }
5543 :
5544 : /*
5545 : * Add the SCB as selected by SCBPTR onto the on chip list of
5546 : * free hardware SCBs. This list is empty/unused if we are not
5547 : * performing SCB paging.
5548 : */
5549 : static void
5550 0 : ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5551 : {
5552 : /*
5553 : * Invalidate the tag so that our abort
5554 : * routines don't think it's active.
5555 : */
5556 0 : ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5557 :
5558 0 : if ((ahc->flags & AHC_PAGESCBS) != 0) {
5559 0 : ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5560 0 : ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5561 0 : }
5562 0 : }
5563 :
5564 : /*
5565 : * Manipulate the waiting for selection list and return the
5566 : * scb that follows the one that we remove.
5567 : */
5568 : static u_int
5569 0 : ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5570 : {
5571 : u_int curscb, next;
5572 :
5573 : /*
5574 : * Select the SCB we want to abort and
5575 : * pull the next pointer out of it.
5576 : */
5577 0 : curscb = ahc_inb(ahc, SCBPTR);
5578 0 : ahc_outb(ahc, SCBPTR, scbpos);
5579 0 : next = ahc_inb(ahc, SCB_NEXT);
5580 :
5581 : /* Clear the necessary fields */
5582 0 : ahc_outb(ahc, SCB_CONTROL, 0);
5583 :
5584 0 : ahc_add_curscb_to_free_list(ahc);
5585 :
5586 : /* update the waiting list */
5587 0 : if (prev == SCB_LIST_NULL) {
5588 : /* First in the list */
5589 0 : ahc_outb(ahc, WAITING_SCBH, next);
5590 :
5591 : /*
5592 : * Ensure we aren't attempting to perform
5593 : * selection for this entry.
5594 : */
5595 0 : ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5596 0 : } else {
5597 : /*
5598 : * Select the scb that pointed to us
5599 : * and update its next pointer.
5600 : */
5601 0 : ahc_outb(ahc, SCBPTR, prev);
5602 0 : ahc_outb(ahc, SCB_NEXT, next);
5603 : }
5604 :
5605 : /*
5606 : * Point us back at the original scb position.
5607 : */
5608 0 : ahc_outb(ahc, SCBPTR, curscb);
5609 0 : return next;
5610 : }
5611 :
5612 : /******************************** Error Handling ******************************/
5613 : /*
5614 : * Abort all SCBs that match the given description (target/channel/lun/tag),
5615 : * setting their status to the passed in status if the status has not already
5616 : * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5617 : * is paused before it is called.
5618 : */
5619 : int
5620 0 : ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5621 : int lun, u_int tag, role_t role, uint32_t status)
5622 : {
5623 : struct scb *scbp;
5624 : struct scb *scbp_next;
5625 : u_int active_scb;
5626 : int i, j;
5627 : int maxtarget;
5628 : int minlun;
5629 : int maxlun;
5630 :
5631 : int found;
5632 :
5633 : /*
5634 : * Don't attempt to run any queued untagged transactions
5635 : * until we are done with the abort process.
5636 : */
5637 0 : ahc_freeze_untagged_queues(ahc);
5638 :
5639 : /* restore this when we're done */
5640 0 : active_scb = ahc_inb(ahc, SCBPTR);
5641 :
5642 0 : found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5643 : role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5644 :
5645 : /*
5646 : * Clean out the busy target table for any untagged commands.
5647 : */
5648 : i = 0;
5649 : maxtarget = 16;
5650 0 : if (target != CAM_TARGET_WILDCARD) {
5651 : i = target;
5652 0 : if (channel == 'B')
5653 0 : i += 8;
5654 0 : maxtarget = i + 1;
5655 0 : }
5656 :
5657 0 : if (lun == CAM_LUN_WILDCARD) {
5658 :
5659 : /*
5660 : * Unless we are using an SCB based
5661 : * busy targets table, there is only
5662 : * one table entry for all luns of
5663 : * a target.
5664 : */
5665 : minlun = 0;
5666 : maxlun = 1;
5667 0 : if ((ahc->flags & AHC_SCB_BTT) != 0)
5668 : maxlun = AHC_NUM_LUNS;
5669 0 : } else {
5670 : minlun = lun;
5671 0 : maxlun = lun + 1;
5672 : }
5673 :
5674 0 : if (role != ROLE_TARGET) {
5675 0 : for (;i < maxtarget; i++) {
5676 0 : for (j = minlun;j < maxlun; j++) {
5677 : u_int scbid;
5678 : u_int tcl;
5679 :
5680 0 : tcl = BUILD_TCL(i << 4, j);
5681 0 : scbid = ahc_index_busy_tcl(ahc, tcl);
5682 0 : scbp = ahc_lookup_scb(ahc, scbid);
5683 0 : if (scbp == NULL
5684 0 : || ahc_match_scb(ahc, scbp, target, channel,
5685 0 : lun, tag, role) == 0)
5686 0 : continue;
5687 0 : ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5688 0 : }
5689 : }
5690 :
5691 : /*
5692 : * Go through the disconnected list and remove any entries we
5693 : * have queued for completion, 0'ing their control byte too.
5694 : * We save the active SCB and restore it ourselves, so there
5695 : * is no reason for this search to restore it too.
5696 : */
5697 0 : ahc_search_disc_list(ahc, target, channel, lun, tag,
5698 : /*stop_on_first*/FALSE, /*remove*/TRUE,
5699 : /*save_state*/FALSE);
5700 0 : }
5701 :
5702 : /*
5703 : * Go through the hardware SCB array looking for commands that
5704 : * were active but not on any list. In some cases, these remnants
5705 : * might not still have mappings in the scbindex array (e.g. unexpected
5706 : * bus free with the same scb queued for an abort). Don't hold this
5707 : * against them.
5708 : */
5709 0 : for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5710 : u_int scbid;
5711 :
5712 0 : ahc_outb(ahc, SCBPTR, i);
5713 0 : scbid = ahc_inb(ahc, SCB_TAG);
5714 0 : scbp = ahc_lookup_scb(ahc, scbid);
5715 0 : if ((scbp == NULL && scbid != SCB_LIST_NULL)
5716 0 : || (scbp != NULL
5717 0 : && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5718 0 : ahc_add_curscb_to_free_list(ahc);
5719 : }
5720 :
5721 : /*
5722 : * Go through the pending CCB list and look for
5723 : * commands for this target that are still active.
5724 : * These are other tagged commands that were
5725 : * disconnected when the reset occurred.
5726 : */
5727 0 : scbp_next = LIST_FIRST(&ahc->pending_scbs);
5728 0 : while (scbp_next != NULL) {
5729 : scbp = scbp_next;
5730 0 : scbp_next = LIST_NEXT(scbp, pending_links);
5731 0 : if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5732 : cam_status ostat;
5733 :
5734 0 : ostat = ahc_get_transaction_status(scbp);
5735 0 : if (ostat == CAM_REQ_INPROG)
5736 0 : ahc_set_transaction_status(scbp, status);
5737 0 : if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5738 0 : ahc_freeze_scb(scbp);
5739 0 : if ((scbp->flags & SCB_ACTIVE) == 0)
5740 0 : printf("Inactive SCB on pending list\n");
5741 0 : ahc_done(ahc, scbp);
5742 0 : found++;
5743 0 : }
5744 : }
5745 0 : ahc_outb(ahc, SCBPTR, active_scb);
5746 0 : ahc_release_untagged_queues(ahc);
5747 0 : return found;
5748 : }
5749 :
5750 : static void
5751 0 : ahc_reset_current_bus(struct ahc_softc *ahc)
5752 : {
5753 : uint8_t scsiseq;
5754 :
5755 0 : ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5756 0 : scsiseq = ahc_inb(ahc, SCSISEQ);
5757 0 : ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5758 0 : ahc_flush_device_writes(ahc);
5759 0 : aic_delay(AHC_BUSRESET_DELAY);
5760 : /* Turn off the bus reset */
5761 0 : ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5762 :
5763 0 : ahc_clear_intstat(ahc);
5764 :
5765 : /* Re-enable reset interrupts */
5766 0 : ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5767 0 : }
5768 :
5769 : int
5770 0 : ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5771 : {
5772 0 : struct ahc_devinfo devinfo;
5773 : u_int initiator, target, max_scsiid;
5774 : u_int sblkctl;
5775 : u_int scsiseq;
5776 : u_int simode1;
5777 : int found;
5778 : int restart_needed;
5779 : char cur_channel;
5780 :
5781 0 : ahc->pending_device = NULL;
5782 :
5783 0 : ahc_compile_devinfo(&devinfo,
5784 : CAM_TARGET_WILDCARD,
5785 : CAM_TARGET_WILDCARD,
5786 : CAM_LUN_WILDCARD,
5787 : channel, ROLE_UNKNOWN);
5788 0 : ahc_pause(ahc);
5789 :
5790 : /* Make sure the sequencer is in a safe location. */
5791 0 : ahc_clear_critical_section(ahc);
5792 :
5793 : /*
5794 : * Run our command complete fifos to ensure that we perform
5795 : * completion processing on any commands that 'completed'
5796 : * before the reset occurred.
5797 : */
5798 0 : ahc_run_qoutfifo(ahc);
5799 : #ifdef AHC_TARGET_MODE
5800 : /*
5801 : * XXX - In Twin mode, the tqinfifo may have commands
5802 : * for an unaffected channel in it. However, if
5803 : * we have run out of ATIO resources to drain that
5804 : * queue, we may not get them all out here. Further,
5805 : * the blocked transactions for the reset channel
5806 : * should just be killed off, irrespecitve of whether
5807 : * we are blocked on ATIO resources. Write a routine
5808 : * to compact the tqinfifo appropriately.
5809 : */
5810 : if ((ahc->flags & AHC_TARGETROLE) != 0) {
5811 : ahc_run_tqinfifo(ahc, /*paused*/TRUE);
5812 : }
5813 : #endif
5814 :
5815 : /*
5816 : * Reset the bus if we are initiating this reset
5817 : */
5818 0 : sblkctl = ahc_inb(ahc, SBLKCTL);
5819 : cur_channel = 'A';
5820 0 : if ((ahc->features & AHC_TWIN) != 0
5821 0 : && ((sblkctl & SELBUSB) != 0))
5822 0 : cur_channel = 'B';
5823 0 : scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
5824 0 : if (cur_channel != channel) {
5825 : /* Case 1: Command for another bus is active
5826 : * Stealthily reset the other bus without
5827 : * upsetting the current bus.
5828 : */
5829 0 : ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5830 0 : simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5831 : #ifdef AHC_TARGET_MODE
5832 : /*
5833 : * Bus resets clear ENSELI, so we cannot
5834 : * defer re-enabling bus reset interrupts
5835 : * if we are in target mode.
5836 : */
5837 : if ((ahc->flags & AHC_TARGETROLE) != 0)
5838 : simode1 |= ENSCSIRST;
5839 : #endif
5840 0 : ahc_outb(ahc, SIMODE1, simode1);
5841 0 : if (initiate_reset)
5842 0 : ahc_reset_current_bus(ahc);
5843 0 : ahc_clear_intstat(ahc);
5844 0 : ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5845 0 : ahc_outb(ahc, SBLKCTL, sblkctl);
5846 : restart_needed = FALSE;
5847 0 : } else {
5848 : /* Case 2: A command from this bus is active or we're idle */
5849 0 : simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5850 : #ifdef AHC_TARGET_MODE
5851 : /*
5852 : * Bus resets clear ENSELI, so we cannot
5853 : * defer re-enabling bus reset interrupts
5854 : * if we are in target mode.
5855 : */
5856 : if ((ahc->flags & AHC_TARGETROLE) != 0)
5857 : simode1 |= ENSCSIRST;
5858 : #endif
5859 0 : ahc_outb(ahc, SIMODE1, simode1);
5860 0 : if (initiate_reset)
5861 0 : ahc_reset_current_bus(ahc);
5862 0 : ahc_clear_intstat(ahc);
5863 0 : ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5864 : restart_needed = TRUE;
5865 : }
5866 :
5867 : /*
5868 : * Clean up all the state information for the
5869 : * pending transactions on this bus.
5870 : */
5871 0 : found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
5872 : CAM_LUN_WILDCARD, SCB_LIST_NULL,
5873 : ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
5874 :
5875 0 : max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
5876 :
5877 : #ifdef AHC_TARGET_MODE
5878 : /*
5879 : * Send an immediate notify ccb to all target more peripheral
5880 : * drivers affected by this action.
5881 : */
5882 : for (target = 0; target <= max_scsiid; target++) {
5883 : struct ahc_tmode_tstate* tstate;
5884 : u_int lun;
5885 :
5886 : tstate = ahc->enabled_targets[target];
5887 : if (tstate == NULL)
5888 : continue;
5889 : for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
5890 : struct ahc_tmode_lstate* lstate;
5891 :
5892 : lstate = tstate->enabled_luns[lun];
5893 : if (lstate == NULL)
5894 : continue;
5895 :
5896 : ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
5897 : EVENT_TYPE_BUS_RESET, /*arg*/0);
5898 : ahc_send_lstate_events(ahc, lstate);
5899 : }
5900 : }
5901 : #endif
5902 : /* Notify the XPT that a bus reset occurred */
5903 0 : ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
5904 : CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
5905 :
5906 : /*
5907 : * Revert to async/narrow transfers until we renegotiate.
5908 : */
5909 0 : for (target = 0; target <= max_scsiid; target++) {
5910 :
5911 0 : if (ahc->enabled_targets[target] == NULL)
5912 : continue;
5913 0 : for (initiator = 0; initiator <= max_scsiid; initiator++) {
5914 0 : ahc_compile_devinfo(&devinfo, target, initiator,
5915 : CAM_LUN_WILDCARD,
5916 : channel, ROLE_UNKNOWN);
5917 0 : ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5918 : AHC_TRANS_CUR, /*paused*/TRUE);
5919 0 : ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
5920 : /*period*/0, /*offset*/0,
5921 : /*ppr_options*/0, AHC_TRANS_CUR,
5922 : /*paused*/TRUE);
5923 : }
5924 : }
5925 :
5926 0 : if (restart_needed)
5927 0 : ahc_restart(ahc);
5928 : else
5929 0 : ahc_unpause(ahc);
5930 0 : return found;
5931 0 : }
5932 :
5933 :
5934 : /***************************** Residual Processing ****************************/
5935 : /*
5936 : * Calculate the residual for a just completed SCB.
5937 : */
5938 : void
5939 0 : ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
5940 : {
5941 : struct hardware_scb *hscb;
5942 : struct status_pkt *spkt;
5943 : uint32_t sgptr;
5944 : uint32_t resid_sgptr;
5945 : uint32_t resid;
5946 :
5947 : /*
5948 : * 5 cases.
5949 : * 1) No residual.
5950 : * SG_RESID_VALID clear in sgptr.
5951 : * 2) Transferless command
5952 : * 3) Never performed any transfers.
5953 : * sgptr has SG_FULL_RESID set.
5954 : * 4) No residual but target did not
5955 : * save data pointers after the
5956 : * last transfer, so sgptr was
5957 : * never updated.
5958 : * 5) We have a partial residual.
5959 : * Use residual_sgptr to determine
5960 : * where we are.
5961 : */
5962 :
5963 0 : hscb = scb->hscb;
5964 0 : sgptr = aic_le32toh(hscb->sgptr);
5965 0 : if ((sgptr & SG_RESID_VALID) == 0)
5966 : /* Case 1 */
5967 0 : return;
5968 0 : sgptr &= ~SG_RESID_VALID;
5969 :
5970 0 : if ((sgptr & SG_LIST_NULL) != 0)
5971 : /* Case 2 */
5972 0 : return;
5973 :
5974 0 : spkt = &hscb->shared_data.status;
5975 0 : resid_sgptr = aic_le32toh(spkt->residual_sg_ptr);
5976 0 : if ((sgptr & SG_FULL_RESID) != 0) {
5977 : /* Case 3 */
5978 0 : resid = ahc_get_transfer_length(scb);
5979 0 : } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
5980 : /* Case 4 */
5981 0 : return;
5982 0 : } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
5983 0 : panic("Bogus resid sgptr value 0x%x", resid_sgptr);
5984 : } else {
5985 : struct ahc_dma_seg *sg;
5986 :
5987 : /*
5988 : * Remainder of the SG where the transfer
5989 : * stopped.
5990 : */
5991 0 : resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
5992 0 : sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
5993 :
5994 : /* The residual sg_ptr always points to the next sg */
5995 0 : sg--;
5996 :
5997 : /*
5998 : * Add up the contents of all residual
5999 : * SG segments that are after the SG where
6000 : * the transfer stopped.
6001 : */
6002 0 : while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6003 0 : sg++;
6004 0 : resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK;
6005 : }
6006 : }
6007 0 : if ((scb->flags & SCB_SENSE) == 0)
6008 0 : ahc_set_residual(scb, resid);
6009 : else
6010 0 : ahc_set_sense_residual(scb, resid);
6011 :
6012 : #ifdef AHC_DEBUG
6013 : if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6014 : ahc_print_path(ahc, scb);
6015 : printf("Handled %sResidual of %d bytes\n",
6016 : (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6017 : }
6018 : #endif
6019 0 : }
6020 :
6021 : /******************************* Target Mode **********************************/
6022 : #ifdef AHC_TARGET_MODE
6023 : /*
6024 : * Add a target mode event to this lun's queue
6025 : */
6026 : static void
6027 : ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6028 : u_int initiator_id, u_int event_type, u_int event_arg)
6029 : {
6030 : struct ahc_tmode_event *event;
6031 : int pending;
6032 :
6033 : xpt_freeze_devq(lstate->path, /*count*/1);
6034 : if (lstate->event_w_idx >= lstate->event_r_idx)
6035 : pending = lstate->event_w_idx - lstate->event_r_idx;
6036 : else
6037 : pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6038 : - (lstate->event_r_idx - lstate->event_w_idx);
6039 :
6040 : if (event_type == EVENT_TYPE_BUS_RESET
6041 : || event_type == MSG_BUS_DEV_RESET) {
6042 : /*
6043 : * Any earlier events are irrelevant, so reset our buffer.
6044 : * This has the effect of allowing us to deal with reset
6045 : * floods (an external device holding down the reset line)
6046 : * without losing the event that is really interesting.
6047 : */
6048 : lstate->event_r_idx = 0;
6049 : lstate->event_w_idx = 0;
6050 : xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6051 : }
6052 :
6053 : if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6054 : xpt_print_path(lstate->path);
6055 : printf("immediate event %x:%x lost\n",
6056 : lstate->event_buffer[lstate->event_r_idx].event_type,
6057 : lstate->event_buffer[lstate->event_r_idx].event_arg);
6058 : lstate->event_r_idx++;
6059 : if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6060 : lstate->event_r_idx = 0;
6061 : xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6062 : }
6063 :
6064 : event = &lstate->event_buffer[lstate->event_w_idx];
6065 : event->initiator_id = initiator_id;
6066 : event->event_type = event_type;
6067 : event->event_arg = event_arg;
6068 : lstate->event_w_idx++;
6069 : if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6070 : lstate->event_w_idx = 0;
6071 : }
6072 :
6073 : /*
6074 : * Send any target mode events queued up waiting
6075 : * for immediate notify resources.
6076 : */
6077 : void
6078 : ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6079 : {
6080 : struct ccb_hdr *ccbh;
6081 : struct ccb_immed_notify *inot;
6082 :
6083 : while (lstate->event_r_idx != lstate->event_w_idx
6084 : && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6085 : struct ahc_tmode_event *event;
6086 :
6087 : event = &lstate->event_buffer[lstate->event_r_idx];
6088 : SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6089 : inot = (struct ccb_immed_notify *)ccbh;
6090 : switch (event->event_type) {
6091 : case EVENT_TYPE_BUS_RESET:
6092 : ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6093 : break;
6094 : default:
6095 : ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6096 : inot->message_args[0] = event->event_type;
6097 : inot->message_args[1] = event->event_arg;
6098 : break;
6099 : }
6100 : inot->initiator_id = event->initiator_id;
6101 : inot->sense_len = 0;
6102 : xpt_done((union ccb *)inot);
6103 : lstate->event_r_idx++;
6104 : if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6105 : lstate->event_r_idx = 0;
6106 : }
6107 : }
6108 : #endif
6109 :
6110 : /******************** Sequencer Program Patching/Download *********************/
6111 :
6112 : #ifdef AHC_DUMP_SEQ
6113 : void
6114 : ahc_dumpseq(struct ahc_softc* ahc)
6115 : {
6116 : int i;
6117 :
6118 : ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6119 : ahc_outb(ahc, SEQADDR0, 0);
6120 : ahc_outb(ahc, SEQADDR1, 0);
6121 : for (i = 0; i < ahc->instruction_ram_size; i++) {
6122 : uint8_t ins_bytes[4];
6123 :
6124 : ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6125 : printf("0x%08x\n", ins_bytes[0] << 24
6126 : | ins_bytes[1] << 16
6127 : | ins_bytes[2] << 8
6128 : | ins_bytes[3]);
6129 : }
6130 : }
6131 : #endif
6132 :
6133 : static int
6134 0 : ahc_loadseq(struct ahc_softc *ahc)
6135 : {
6136 0 : struct cs cs_table[NUM_CRITICAL_SECTIONS];
6137 0 : u_int begin_set[NUM_CRITICAL_SECTIONS];
6138 0 : u_int end_set[NUM_CRITICAL_SECTIONS];
6139 0 : const struct patch *cur_patch;
6140 : u_int cs_count;
6141 : u_int cur_cs;
6142 : u_int i;
6143 0 : u_int skip_addr;
6144 : u_int sg_prefetch_cnt;
6145 : int downloaded;
6146 0 : uint8_t download_consts[7];
6147 :
6148 : /*
6149 : * Start out with 0 critical sections
6150 : * that apply to this firmware load.
6151 : */
6152 : cs_count = 0;
6153 : cur_cs = 0;
6154 0 : memset(begin_set, 0, sizeof(begin_set));
6155 0 : memset(end_set, 0, sizeof(end_set));
6156 :
6157 : /* Setup downloadable constant table */
6158 0 : download_consts[QOUTFIFO_OFFSET] = 0;
6159 0 : if (ahc->targetcmds != NULL)
6160 0 : download_consts[QOUTFIFO_OFFSET] += 32;
6161 0 : download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6162 0 : download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6163 0 : download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6164 0 : sg_prefetch_cnt = ahc->pci_cachesize;
6165 0 : if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6166 : sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6167 0 : download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6168 0 : download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6169 0 : download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6170 :
6171 0 : cur_patch = patches;
6172 : downloaded = 0;
6173 0 : skip_addr = 0;
6174 0 : ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6175 0 : ahc_outb(ahc, SEQADDR0, 0);
6176 0 : ahc_outb(ahc, SEQADDR1, 0);
6177 :
6178 0 : for (i = 0; i < sizeof(seqprog)/4; i++) {
6179 0 : if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6180 : /*
6181 : * Don't download this instruction as it
6182 : * is in a patch that was removed.
6183 : */
6184 : continue;
6185 : }
6186 :
6187 0 : if (downloaded == ahc->instruction_ram_size) {
6188 : /*
6189 : * We're about to exceed the instruction
6190 : * storage capacity for this chip. Fail
6191 : * the load.
6192 : */
6193 0 : printf("\n%s: Program too large for instruction memory "
6194 0 : "size of %d!\n", ahc_name(ahc),
6195 0 : ahc->instruction_ram_size);
6196 0 : return (ENOMEM);
6197 : }
6198 :
6199 : /*
6200 : * Move through the CS table until we find a CS
6201 : * that might apply to this instruction.
6202 : */
6203 0 : for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) {
6204 0 : if (critical_sections[cur_cs].end <= i) {
6205 0 : if (begin_set[cs_count] == TRUE
6206 0 : && end_set[cs_count] == FALSE) {
6207 0 : cs_table[cs_count].end = downloaded;
6208 0 : end_set[cs_count] = TRUE;
6209 0 : cs_count++;
6210 0 : }
6211 : continue;
6212 : }
6213 0 : if (critical_sections[cur_cs].begin <= i
6214 0 : && begin_set[cs_count] == FALSE) {
6215 0 : cs_table[cs_count].begin = downloaded;
6216 0 : begin_set[cs_count] = TRUE;
6217 0 : }
6218 : break;
6219 : }
6220 0 : ahc_download_instr(ahc, i, download_consts);
6221 0 : downloaded++;
6222 0 : }
6223 :
6224 0 : ahc->num_critical_sections = cs_count;
6225 0 : if (cs_count != 0) {
6226 0 : ahc->critical_sections = mallocarray(cs_count,
6227 : sizeof(struct cs), M_DEVBUF, M_NOWAIT);
6228 0 : if (ahc->critical_sections == NULL)
6229 0 : panic("ahc_loadseq: Could not malloc");
6230 0 : cs_count *= sizeof(struct cs);
6231 :
6232 0 : memcpy(ahc->critical_sections, cs_table, cs_count);
6233 0 : }
6234 0 : ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6235 :
6236 : if (bootverbose) {
6237 : printf(" %d instructions downloaded\n", downloaded);
6238 : printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6239 : ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6240 : }
6241 0 : return (0);
6242 0 : }
6243 :
6244 : static int
6245 0 : ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch,
6246 : u_int start_instr, u_int *skip_addr)
6247 : {
6248 : const struct patch *cur_patch;
6249 : const struct patch *last_patch;
6250 : u_int num_patches;
6251 :
6252 : num_patches = sizeof(patches)/sizeof(struct patch);
6253 : last_patch = &patches[num_patches];
6254 0 : cur_patch = *start_patch;
6255 :
6256 0 : while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6257 :
6258 0 : if (cur_patch->patch_func(ahc) == 0) {
6259 :
6260 : /* Start rejecting code */
6261 0 : *skip_addr = start_instr + cur_patch->skip_instr;
6262 0 : cur_patch += cur_patch->skip_patch;
6263 0 : } else {
6264 : /* Accepted this patch. Advance to the next
6265 : * one and wait for our intruction pointer to
6266 : * hit this point.
6267 : */
6268 0 : cur_patch++;
6269 : }
6270 : }
6271 :
6272 0 : *start_patch = cur_patch;
6273 0 : if (start_instr < *skip_addr)
6274 : /* Still skipping */
6275 0 : return (0);
6276 :
6277 0 : return (1);
6278 0 : }
6279 :
6280 : static void
6281 0 : ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6282 : {
6283 0 : union ins_formats instr;
6284 : struct ins_format1 *fmt1_ins;
6285 : struct ins_format3 *fmt3_ins;
6286 : u_int opcode;
6287 :
6288 : /*
6289 : * The firmware is always compiled into a little endian format.
6290 : */
6291 0 : instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6292 :
6293 0 : fmt1_ins = &instr.format1;
6294 : fmt3_ins = NULL;
6295 :
6296 : /* Pull the opcode */
6297 0 : opcode = instr.format1.opcode;
6298 0 : switch (opcode) {
6299 : case AIC_OP_JMP:
6300 : case AIC_OP_JC:
6301 : case AIC_OP_JNC:
6302 : case AIC_OP_CALL:
6303 : case AIC_OP_JNE:
6304 : case AIC_OP_JNZ:
6305 : case AIC_OP_JE:
6306 : case AIC_OP_JZ:
6307 : {
6308 0 : const struct patch *cur_patch;
6309 : int address_offset;
6310 : u_int address;
6311 0 : u_int skip_addr;
6312 : u_int i;
6313 :
6314 0 : fmt3_ins = &instr.format3;
6315 : address_offset = 0;
6316 0 : address = fmt3_ins->address;
6317 0 : cur_patch = patches;
6318 0 : skip_addr = 0;
6319 :
6320 0 : for (i = 0; i < address;) {
6321 :
6322 0 : ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6323 :
6324 0 : if (skip_addr > i) {
6325 : int end_addr;
6326 :
6327 0 : end_addr = MIN(address, skip_addr);
6328 0 : address_offset += end_addr - i;
6329 : i = skip_addr;
6330 0 : } else {
6331 0 : i++;
6332 : }
6333 : }
6334 0 : address -= address_offset;
6335 0 : fmt3_ins->address = address;
6336 : /* FALLTHROUGH */
6337 0 : }
6338 : case AIC_OP_OR:
6339 : case AIC_OP_AND:
6340 : case AIC_OP_XOR:
6341 : case AIC_OP_ADD:
6342 : case AIC_OP_ADC:
6343 : case AIC_OP_BMOV:
6344 0 : if (fmt1_ins->parity != 0) {
6345 0 : fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6346 0 : }
6347 0 : fmt1_ins->parity = 0;
6348 0 : if ((ahc->features & AHC_CMD_CHAN) == 0
6349 0 : && opcode == AIC_OP_BMOV) {
6350 : /*
6351 : * Block move was added at the same time
6352 : * as the command channel. Verify that
6353 : * this is only a move of a single element
6354 : * and convert the BMOV to a MOV
6355 : * (AND with an immediate of FF).
6356 : */
6357 0 : if (fmt1_ins->immediate != 1)
6358 0 : panic("%s: BMOV not supported",
6359 0 : ahc_name(ahc));
6360 0 : fmt1_ins->opcode = AIC_OP_AND;
6361 0 : fmt1_ins->immediate = 0xff;
6362 0 : }
6363 : /* FALLTHROUGH */
6364 : case AIC_OP_ROL:
6365 0 : if ((ahc->features & AHC_ULTRA2) != 0) {
6366 : int i, count;
6367 :
6368 : /* Calculate odd parity for the instruction */
6369 0 : for (i = 0, count = 0; i < 31; i++) {
6370 : uint32_t mask;
6371 :
6372 0 : mask = 0x01 << i;
6373 0 : if ((instr.integer & mask) != 0)
6374 0 : count++;
6375 : }
6376 0 : if ((count & 0x01) == 0)
6377 0 : instr.format1.parity = 1;
6378 0 : } else {
6379 : /* Compress the instruction for older sequencers */
6380 0 : if (fmt3_ins != NULL) {
6381 0 : instr.integer =
6382 0 : fmt3_ins->immediate
6383 0 : | (fmt3_ins->source << 8)
6384 0 : | (fmt3_ins->address << 16)
6385 0 : | (fmt3_ins->opcode << 25);
6386 0 : } else {
6387 0 : instr.integer =
6388 0 : fmt1_ins->immediate
6389 0 : | (fmt1_ins->source << 8)
6390 0 : | (fmt1_ins->destination << 16)
6391 0 : | (fmt1_ins->ret << 24)
6392 0 : | (fmt1_ins->opcode << 25);
6393 : }
6394 : }
6395 : /* The sequencer is a little endian cpu */
6396 0 : instr.integer = aic_htole32(instr.integer);
6397 0 : ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6398 : break;
6399 : default:
6400 0 : panic("Unknown opcode encountered in seq program");
6401 : break;
6402 : }
6403 0 : }
6404 :
6405 : #ifndef SMALL_KERNEL
6406 : int
6407 0 : ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6408 : const char *name, u_int address, u_int value,
6409 : u_int *cur_column, u_int wrap_point)
6410 : {
6411 : u_int printed_mask;
6412 : int entry, printed;
6413 :
6414 0 : if (cur_column != NULL && *cur_column >= wrap_point) {
6415 0 : printf("\n");
6416 0 : *cur_column = 0;
6417 0 : }
6418 0 : printed = printf("%s[0x%x]", name, value);
6419 0 : if (table == NULL) {
6420 0 : printed += printf(" ");
6421 0 : if (cur_column != NULL)
6422 0 : *cur_column += printed;
6423 0 : return (printed);
6424 : }
6425 :
6426 : printed_mask = 0;
6427 0 : while (printed_mask != 0xFF) {
6428 0 : for (entry = 0; entry < num_entries; entry++) {
6429 0 : if (((value & table[entry].mask) != table[entry].value)
6430 0 : || ((printed_mask & table[entry].mask) ==
6431 : table[entry].mask))
6432 : continue;
6433 :
6434 0 : printed += printf("%s%s",
6435 0 : printed_mask == 0 ? ":(" : "|",
6436 0 : table[entry].name);
6437 0 : printed_mask |= table[entry].mask;
6438 :
6439 0 : break;
6440 : }
6441 0 : if (entry >= num_entries)
6442 : break;
6443 : }
6444 :
6445 0 : printed += printf("%s", printed_mask == 0 ? " " : ") ");
6446 0 : if (cur_column != NULL)
6447 0 : *cur_column += printed;
6448 :
6449 0 : return (printed);
6450 0 : }
6451 : #endif
6452 :
6453 : void
6454 0 : ahc_dump_card_state(struct ahc_softc *ahc)
6455 : {
6456 : #ifndef SMALL_KERNEL
6457 : struct scb *scb;
6458 : struct scb_tailq *untagged_q;
6459 0 : u_int cur_col;
6460 : int paused;
6461 : int target;
6462 : int maxtarget;
6463 : int i;
6464 : uint8_t last_phase;
6465 : uint8_t qinpos;
6466 : uint8_t qintail;
6467 : uint8_t qoutpos;
6468 : uint8_t scb_index;
6469 : uint8_t saved_scbptr;
6470 :
6471 0 : if (ahc_is_paused(ahc)) {
6472 : paused = 1;
6473 0 : } else {
6474 : paused = 0;
6475 0 : ahc_pause(ahc);
6476 : }
6477 :
6478 0 : saved_scbptr = ahc_inb(ahc, SCBPTR);
6479 0 : last_phase = ahc_inb(ahc, LASTPHASE);
6480 0 : printf("================== Dump Card State Begins =================\n"
6481 : "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6482 0 : ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6483 0 : ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6484 0 : if (paused)
6485 0 : printf("Card was paused\n");
6486 0 : printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6487 0 : ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6488 0 : ahc_inb(ahc, ARG_2));
6489 0 : printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6490 0 : ahc_inb(ahc, SCBPTR));
6491 0 : cur_col = 0;
6492 0 : if ((ahc->features & AHC_DT) != 0)
6493 0 : ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6494 0 : ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6495 0 : ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6496 0 : ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6497 0 : ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6498 0 : ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6499 0 : ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6500 0 : ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6501 0 : ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6502 0 : ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6503 0 : ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6504 0 : ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6505 0 : ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6506 0 : ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6507 0 : ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6508 0 : ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6509 0 : ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6510 0 : ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6511 0 : ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6512 0 : if (cur_col != 0)
6513 0 : printf("\n");
6514 0 : printf("STACK:");
6515 0 : for (i = 0; i < STACK_SIZE; i++)
6516 0 : printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6517 0 : printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6518 0 : printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6519 0 : printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6520 : /* QINFIFO */
6521 0 : printf("QINFIFO entries: ");
6522 0 : if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6523 0 : qinpos = ahc_inb(ahc, SNSCB_QOFF);
6524 0 : ahc_outb(ahc, SNSCB_QOFF, qinpos);
6525 0 : } else
6526 0 : qinpos = ahc_inb(ahc, QINPOS);
6527 0 : qintail = ahc->qinfifonext;
6528 0 : while (qinpos != qintail) {
6529 0 : printf("%d ", ahc->qinfifo[qinpos]);
6530 0 : qinpos++;
6531 : }
6532 0 : printf("\n");
6533 :
6534 0 : printf("Waiting Queue entries: ");
6535 0 : scb_index = ahc_inb(ahc, WAITING_SCBH);
6536 : i = 0;
6537 0 : while (scb_index != SCB_LIST_NULL && i++ < 256) {
6538 0 : ahc_outb(ahc, SCBPTR, scb_index);
6539 0 : printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6540 0 : scb_index = ahc_inb(ahc, SCB_NEXT);
6541 : }
6542 0 : printf("\n");
6543 :
6544 0 : printf("Disconnected Queue entries: ");
6545 0 : scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6546 : i = 0;
6547 0 : while (scb_index != SCB_LIST_NULL && i++ < 256) {
6548 0 : ahc_outb(ahc, SCBPTR, scb_index);
6549 0 : printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6550 0 : scb_index = ahc_inb(ahc, SCB_NEXT);
6551 : }
6552 0 : printf("\n");
6553 :
6554 0 : ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6555 0 : printf("QOUTFIFO entries: ");
6556 0 : qoutpos = ahc->qoutfifonext;
6557 : i = 0;
6558 0 : while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6559 0 : printf("%d ", ahc->qoutfifo[qoutpos]);
6560 0 : qoutpos++;
6561 : }
6562 0 : printf("\n");
6563 :
6564 0 : printf("Sequencer Free SCB List: ");
6565 0 : scb_index = ahc_inb(ahc, FREE_SCBH);
6566 : i = 0;
6567 0 : while (scb_index != SCB_LIST_NULL && i++ < 256) {
6568 0 : ahc_outb(ahc, SCBPTR, scb_index);
6569 0 : printf("%d ", scb_index);
6570 0 : scb_index = ahc_inb(ahc, SCB_NEXT);
6571 : }
6572 0 : printf("\n");
6573 :
6574 0 : printf("Sequencer SCB Info: ");
6575 0 : for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6576 0 : ahc_outb(ahc, SCBPTR, i);
6577 0 : /*cur_col =*/ printf("\n%3d ", i);
6578 :
6579 0 : ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6580 0 : ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6581 0 : ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6582 0 : ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6583 : }
6584 0 : printf("\n");
6585 :
6586 0 : printf("Pending list: ");
6587 : i = 0;
6588 0 : LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6589 0 : if (i++ > 256)
6590 : break;
6591 0 : /*cur_col =*/ printf("\n%3d ", scb->hscb->tag);
6592 0 : ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6593 0 : ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6594 0 : ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6595 0 : if ((ahc->flags & AHC_PAGESCBS) == 0) {
6596 0 : ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6597 0 : printf("(");
6598 0 : ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6599 : &cur_col, 60);
6600 0 : ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6601 0 : printf(")");
6602 0 : }
6603 : }
6604 0 : printf("\n");
6605 :
6606 0 : printf("Kernel Free SCB list: ");
6607 : i = 0;
6608 0 : mtx_enter(&ahc->sc_scb_mtx);
6609 0 : SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6610 0 : if (i++ > 256)
6611 : break;
6612 0 : printf("%d ", scb->hscb->tag);
6613 : }
6614 0 : printf("\n");
6615 0 : mtx_leave(&ahc->sc_scb_mtx);
6616 :
6617 0 : maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6618 0 : for (target = 0; target <= maxtarget; target++) {
6619 0 : untagged_q = &ahc->untagged_queues[target];
6620 0 : if (TAILQ_FIRST(untagged_q) == NULL)
6621 : continue;
6622 0 : printf("Untagged Q(%d): ", target);
6623 : i = 0;
6624 0 : TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6625 0 : if (i++ > 256)
6626 : break;
6627 0 : printf("%d ", scb->hscb->tag);
6628 : }
6629 0 : printf("\n");
6630 0 : }
6631 :
6632 0 : ahc_platform_dump_card_state(ahc);
6633 0 : printf("\n================= Dump Card State Ends ==================\n");
6634 0 : ahc_outb(ahc, SCBPTR, saved_scbptr);
6635 0 : if (paused == 0)
6636 0 : ahc_unpause(ahc);
6637 : #endif
6638 0 : }
6639 :
6640 : /************************* Target Mode ****************************************/
6641 : #ifdef AHC_TARGET_MODE
6642 : cam_status
6643 : ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
6644 : struct ahc_tmode_tstate **tstate,
6645 : struct ahc_tmode_lstate **lstate,
6646 : int notfound_failure)
6647 : {
6648 :
6649 : if ((ahc->features & AHC_TARGETMODE) == 0)
6650 : return (CAM_REQ_INVALID);
6651 :
6652 : /*
6653 : * Handle the 'black hole' device that sucks up
6654 : * requests to unattached luns on enabled targets.
6655 : */
6656 : if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
6657 : && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
6658 : *tstate = NULL;
6659 : *lstate = ahc->black_hole;
6660 : } else {
6661 : u_int max_id;
6662 :
6663 : max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
6664 : if (ccb->ccb_h.target_id > max_id)
6665 : return (CAM_TID_INVALID);
6666 :
6667 : if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
6668 : return (CAM_LUN_INVALID);
6669 :
6670 : *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
6671 : *lstate = NULL;
6672 : if (*tstate != NULL)
6673 : *lstate =
6674 : (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
6675 : }
6676 :
6677 : if (notfound_failure != 0 && *lstate == NULL)
6678 : return (CAM_PATH_INVALID);
6679 :
6680 : return (CAM_REQ_CMP);
6681 : }
6682 :
6683 : void
6684 : ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
6685 : {
6686 : struct ahc_tmode_tstate *tstate;
6687 : struct ahc_tmode_lstate *lstate;
6688 : struct ccb_en_lun *cel;
6689 : cam_status status;
6690 : u_long s;
6691 : u_int target;
6692 : u_int lun;
6693 : u_int target_mask;
6694 : u_int our_id;
6695 : int error;
6696 : char channel;
6697 :
6698 : status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
6699 : /*notfound_failure*/FALSE);
6700 :
6701 : if (status != CAM_REQ_CMP) {
6702 : ccb->ccb_h.status = status;
6703 : return;
6704 : }
6705 :
6706 : if (cam_sim_bus(sim) == 0)
6707 : our_id = ahc->our_id;
6708 : else
6709 : our_id = ahc->our_id_b;
6710 :
6711 : if (ccb->ccb_h.target_id != our_id) {
6712 : /*
6713 : * our_id represents our initiator ID, or
6714 : * the ID of the first target to have an
6715 : * enabled lun in target mode. There are
6716 : * two cases that may preclude enabling a
6717 : * target id other than our_id.
6718 : *
6719 : * o our_id is for an active initiator role.
6720 : * Since the hardware does not support
6721 : * reselections to the initiator role at
6722 : * anything other than our_id, and our_id
6723 : * is used by the hardware to indicate the
6724 : * ID to use for both select-out and
6725 : * reselect-out operations, the only target
6726 : * ID we can support in this mode is our_id.
6727 : *
6728 : * o The MULTARGID feature is not available and
6729 : * a previous target mode ID has been enabled.
6730 : */
6731 : if ((ahc->features & AHC_MULTIROLE) != 0) {
6732 :
6733 : if ((ahc->features & AHC_MULTI_TID) != 0
6734 : && (ahc->flags & AHC_INITIATORROLE) != 0) {
6735 : /*
6736 : * Only allow additional targets if
6737 : * the initiator role is disabled.
6738 : * The hardware cannot handle a re-select-in
6739 : * on the initiator id during a re-select-out
6740 : * on a different target id.
6741 : */
6742 : status = CAM_TID_INVALID;
6743 : } else if ((ahc->flags & AHC_INITIATORROLE) != 0
6744 : || ahc->enabled_luns > 0) {
6745 : /*
6746 : * Only allow our target id to change
6747 : * if the initiator role is not configured
6748 : * and there are no enabled luns which
6749 : * are attached to the currently registered
6750 : * scsi id.
6751 : */
6752 : status = CAM_TID_INVALID;
6753 : }
6754 : } else if ((ahc->features & AHC_MULTI_TID) == 0
6755 : && ahc->enabled_luns > 0) {
6756 :
6757 : status = CAM_TID_INVALID;
6758 : }
6759 : }
6760 :
6761 : if (status != CAM_REQ_CMP) {
6762 : ccb->ccb_h.status = status;
6763 : return;
6764 : }
6765 :
6766 : /*
6767 : * We now have an id that is valid.
6768 : * If we aren't in target mode, switch modes.
6769 : */
6770 : if ((ahc->flags & AHC_TARGETROLE) == 0
6771 : && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
6772 : u_long s;
6773 : ahc_flag saved_flags;
6774 :
6775 : printf("Configuring Target Mode\n");
6776 : s = splbio();
6777 : if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6778 : ccb->ccb_h.status = CAM_BUSY;
6779 : splx(s);
6780 : return;
6781 : }
6782 : saved_flags = ahc->flags;
6783 : ahc->flags |= AHC_TARGETROLE;
6784 : if ((ahc->features & AHC_MULTIROLE) == 0)
6785 : ahc->flags &= ~AHC_INITIATORROLE;
6786 : ahc_pause(ahc);
6787 : error = ahc_loadseq(ahc);
6788 : if (error != 0) {
6789 : /*
6790 : * Restore original configuration and notify
6791 : * the caller that we cannot support target mode.
6792 : * Since the adapter started out in this
6793 : * configuration, the firmware load will succeed,
6794 : * so there is no point in checking ahc_loadseq's
6795 : * return value.
6796 : */
6797 : ahc->flags = saved_flags;
6798 : (void)ahc_loadseq(ahc);
6799 : ahc_restart(ahc);
6800 : splx(s);
6801 : ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
6802 : return;
6803 : }
6804 : ahc_restart(ahc);
6805 : splx(s);
6806 : }
6807 : cel = &ccb->cel;
6808 : target = ccb->ccb_h.target_id;
6809 : lun = ccb->ccb_h.target_lun;
6810 : channel = SIM_CHANNEL(ahc, sim);
6811 : target_mask = 0x01 << target;
6812 : if (channel == 'B')
6813 : target_mask <<= 8;
6814 :
6815 : if (cel->enable != 0) {
6816 : u_int scsiseq;
6817 :
6818 : /* Are we already enabled?? */
6819 : if (lstate != NULL) {
6820 : xpt_print_path(ccb->ccb_h.path);
6821 : printf("Lun already enabled\n");
6822 : ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
6823 : return;
6824 : }
6825 :
6826 : if (cel->grp6_len != 0
6827 : || cel->grp7_len != 0) {
6828 : /*
6829 : * Don't (yet?) support vendor
6830 : * specific commands.
6831 : */
6832 : ccb->ccb_h.status = CAM_REQ_INVALID;
6833 : printf("Non-zero Group Codes\n");
6834 : return;
6835 : }
6836 :
6837 : /*
6838 : * Seems to be okay.
6839 : * Setup our data structures.
6840 : */
6841 : if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
6842 : tstate = ahc_alloc_tstate(ahc, target, channel);
6843 : if (tstate == NULL) {
6844 : xpt_print_path(ccb->ccb_h.path);
6845 : printf("Couldn't allocate tstate\n");
6846 : ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6847 : return;
6848 : }
6849 : }
6850 : lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT | M_ZERO);
6851 : if (lstate == NULL) {
6852 : xpt_print_path(ccb->ccb_h.path);
6853 : printf("Couldn't allocate lstate\n");
6854 : ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6855 : return;
6856 : }
6857 : status = xpt_create_path(&lstate->path, /*periph*/NULL,
6858 : xpt_path_path_id(ccb->ccb_h.path),
6859 : xpt_path_target_id(ccb->ccb_h.path),
6860 : xpt_path_lun_id(ccb->ccb_h.path));
6861 : if (status != CAM_REQ_CMP) {
6862 : free(lstate, M_DEVBUF, 0);
6863 : xpt_print_path(ccb->ccb_h.path);
6864 : printf("Couldn't allocate path\n");
6865 : ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6866 : return;
6867 : }
6868 : SLIST_INIT(&lstate->accept_tios);
6869 : SLIST_INIT(&lstate->immed_notifies);
6870 : s = splbio();
6871 : ahc_pause(ahc);
6872 : if (target != CAM_TARGET_WILDCARD) {
6873 : tstate->enabled_luns[lun] = lstate;
6874 : ahc->enabled_luns++;
6875 :
6876 : if ((ahc->features & AHC_MULTI_TID) != 0) {
6877 : u_int targid_mask;
6878 :
6879 : targid_mask = ahc_inb(ahc, TARGID)
6880 : | (ahc_inb(ahc, TARGID + 1) << 8);
6881 :
6882 : targid_mask |= target_mask;
6883 : ahc_outb(ahc, TARGID, targid_mask);
6884 : ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
6885 :
6886 : ahc_update_scsiid(ahc, targid_mask);
6887 : } else {
6888 : u_int our_id;
6889 : char channel;
6890 :
6891 : channel = SIM_CHANNEL(ahc, sim);
6892 : our_id = SIM_SCSI_ID(ahc, sim);
6893 :
6894 : /*
6895 : * This can only happen if selections
6896 : * are not enabled
6897 : */
6898 : if (target != our_id) {
6899 : u_int sblkctl;
6900 : char cur_channel;
6901 : int swap;
6902 :
6903 : sblkctl = ahc_inb(ahc, SBLKCTL);
6904 : cur_channel = (sblkctl & SELBUSB)
6905 : ? 'B' : 'A';
6906 : if ((ahc->features & AHC_TWIN) == 0)
6907 : cur_channel = 'A';
6908 : swap = cur_channel != channel;
6909 : if (channel == 'A')
6910 : ahc->our_id = target;
6911 : else
6912 : ahc->our_id_b = target;
6913 :
6914 : if (swap)
6915 : ahc_outb(ahc, SBLKCTL,
6916 : sblkctl ^ SELBUSB);
6917 :
6918 : ahc_outb(ahc, SCSIID, target);
6919 :
6920 : if (swap)
6921 : ahc_outb(ahc, SBLKCTL, sblkctl);
6922 : }
6923 : }
6924 : } else
6925 : ahc->black_hole = lstate;
6926 : /* Allow select-in operations */
6927 : if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
6928 : scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6929 : scsiseq |= ENSELI;
6930 : ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
6931 : scsiseq = ahc_inb(ahc, SCSISEQ);
6932 : scsiseq |= ENSELI;
6933 : ahc_outb(ahc, SCSISEQ, scsiseq);
6934 : }
6935 : ahc_unpause(ahc);
6936 : splx(s);
6937 : ccb->ccb_h.status = CAM_REQ_CMP;
6938 : xpt_print_path(ccb->ccb_h.path);
6939 : printf("Lun now enabled for target mode\n");
6940 : } else {
6941 : struct scb *scb;
6942 : int i, empty;
6943 :
6944 : if (lstate == NULL) {
6945 : ccb->ccb_h.status = CAM_LUN_INVALID;
6946 : return;
6947 : }
6948 :
6949 : s = splbio();
6950 :
6951 : ccb->ccb_h.status = CAM_REQ_CMP;
6952 : LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6953 : struct ccb_hdr *ccbh;
6954 :
6955 : ccbh = &scb->io_ctx->ccb_h;
6956 : if (ccbh->func_code == XPT_CONT_TARGET_IO
6957 : && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
6958 : printf("CTIO pending\n");
6959 : ccb->ccb_h.status = CAM_REQ_INVALID;
6960 : splx(s);
6961 : return;
6962 : }
6963 : }
6964 :
6965 : if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
6966 : printf("ATIOs pending\n");
6967 : ccb->ccb_h.status = CAM_REQ_INVALID;
6968 : }
6969 :
6970 : if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
6971 : printf("INOTs pending\n");
6972 : ccb->ccb_h.status = CAM_REQ_INVALID;
6973 : }
6974 :
6975 : if (ccb->ccb_h.status != CAM_REQ_CMP) {
6976 : splx(s);
6977 : return;
6978 : }
6979 :
6980 : xpt_print_path(ccb->ccb_h.path);
6981 : printf("Target mode disabled\n");
6982 : xpt_free_path(lstate->path);
6983 : free(lstate, M_DEVBUF, 0);
6984 :
6985 : ahc_pause(ahc);
6986 : /* Can we clean up the target too? */
6987 : if (target != CAM_TARGET_WILDCARD) {
6988 : tstate->enabled_luns[lun] = NULL;
6989 : ahc->enabled_luns--;
6990 : for (empty = 1, i = 0; i < 8; i++)
6991 : if (tstate->enabled_luns[i] != NULL) {
6992 : empty = 0;
6993 : break;
6994 : }
6995 :
6996 : if (empty) {
6997 : ahc_free_tstate(ahc, target, channel,
6998 : /*force*/FALSE);
6999 : if (ahc->features & AHC_MULTI_TID) {
7000 : u_int targid_mask;
7001 :
7002 : targid_mask = ahc_inb(ahc, TARGID)
7003 : | (ahc_inb(ahc, TARGID + 1)
7004 : << 8);
7005 :
7006 : targid_mask &= ~target_mask;
7007 : ahc_outb(ahc, TARGID, targid_mask);
7008 : ahc_outb(ahc, TARGID+1,
7009 : (targid_mask >> 8));
7010 : ahc_update_scsiid(ahc, targid_mask);
7011 : }
7012 : }
7013 : } else {
7014 :
7015 : ahc->black_hole = NULL;
7016 :
7017 : /*
7018 : * We can't allow selections without
7019 : * our black hole device.
7020 : */
7021 : empty = TRUE;
7022 : }
7023 : if (ahc->enabled_luns == 0) {
7024 : /* Disallow select-in */
7025 : u_int scsiseq;
7026 :
7027 : scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7028 : scsiseq &= ~ENSELI;
7029 : ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7030 : scsiseq = ahc_inb(ahc, SCSISEQ);
7031 : scsiseq &= ~ENSELI;
7032 : ahc_outb(ahc, SCSISEQ, scsiseq);
7033 :
7034 : if ((ahc->features & AHC_MULTIROLE) == 0) {
7035 : printf("Configuring Initiator Mode\n");
7036 : ahc->flags &= ~AHC_TARGETROLE;
7037 : ahc->flags |= AHC_INITIATORROLE;
7038 : /*
7039 : * Returning to a configuration that
7040 : * fit previously will always succeed.
7041 : */
7042 : (void)ahc_loadseq(ahc);
7043 : ahc_restart(ahc);
7044 : /*
7045 : * Unpaused. The extra unpause
7046 : * that follows is harmless.
7047 : */
7048 : }
7049 : }
7050 : ahc_unpause(ahc);
7051 : splx(s);
7052 : }
7053 : }
7054 :
7055 : static void
7056 : ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7057 : {
7058 : u_int scsiid_mask;
7059 : u_int scsiid;
7060 :
7061 : if ((ahc->features & AHC_MULTI_TID) == 0)
7062 : panic("ahc_update_scsiid called on non-multitid unit");
7063 :
7064 : /*
7065 : * Since we will rely on the TARGID mask
7066 : * for selection enables, ensure that OID
7067 : * in SCSIID is not set to some other ID
7068 : * that we don't want to allow selections on.
7069 : */
7070 : if ((ahc->features & AHC_ULTRA2) != 0)
7071 : scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7072 : else
7073 : scsiid = ahc_inb(ahc, SCSIID);
7074 : scsiid_mask = 0x1 << (scsiid & OID);
7075 : if ((targid_mask & scsiid_mask) == 0) {
7076 : u_int our_id;
7077 :
7078 : /* ffs counts from 1 */
7079 : our_id = ffs(targid_mask);
7080 : if (our_id == 0)
7081 : our_id = ahc->our_id;
7082 : else
7083 : our_id--;
7084 : scsiid &= TID;
7085 : scsiid |= our_id;
7086 : }
7087 : if ((ahc->features & AHC_ULTRA2) != 0)
7088 : ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7089 : else
7090 : ahc_outb(ahc, SCSIID, scsiid);
7091 : }
7092 :
7093 : #ifdef AHC_TARGET_MODE
7094 : void
7095 : ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7096 : {
7097 : struct target_cmd *cmd;
7098 :
7099 : /*
7100 : * If the card supports auto-access pause,
7101 : * we can access the card directly regardless
7102 : * of whether it is paused or not.
7103 : */
7104 : if ((ahc->features & AHC_AUTOPAUSE) != 0)
7105 : paused = TRUE;
7106 :
7107 : ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7108 : while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7109 :
7110 : /*
7111 : * Only advance through the queue if we
7112 : * have the resources to process the command.
7113 : */
7114 : if (ahc_handle_target_cmd(ahc, cmd) != 0)
7115 : break;
7116 :
7117 : cmd->cmd_valid = 0;
7118 : ahc_dmamap_sync(ahc, ahc->parent_dmat/*shared_data_dmat*/,
7119 : ahc->shared_data_dmamap,
7120 : ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7121 : sizeof(struct target_cmd),
7122 : #ifdef __sgi__
7123 : BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
7124 : #else
7125 : BUS_DMASYNC_PREREAD);
7126 : #endif
7127 : ahc->tqinfifonext++;
7128 :
7129 : /*
7130 : * Lazily update our position in the target mode incoming
7131 : * command queue as seen by the sequencer.
7132 : */
7133 : if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7134 : if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7135 : u_int hs_mailbox;
7136 :
7137 : hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7138 : hs_mailbox &= ~HOST_TQINPOS;
7139 : hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7140 : ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7141 : } else {
7142 : if (!paused)
7143 : ahc_pause(ahc);
7144 : ahc_outb(ahc, KERNEL_TQINPOS,
7145 : ahc->tqinfifonext & HOST_TQINPOS);
7146 : if (!paused)
7147 : ahc_unpause(ahc);
7148 : }
7149 : }
7150 : }
7151 : }
7152 : #endif
7153 :
7154 : static int
7155 : ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7156 : {
7157 : struct ahc_tmode_tstate *tstate;
7158 : struct ahc_tmode_lstate *lstate;
7159 : struct ccb_accept_tio *atio;
7160 : uint8_t *byte;
7161 : int initiator;
7162 : int target;
7163 : int lun;
7164 :
7165 : initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7166 : target = SCSIID_OUR_ID(cmd->scsiid);
7167 : lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7168 :
7169 : byte = cmd->bytes;
7170 : tstate = ahc->enabled_targets[target];
7171 : lstate = NULL;
7172 : if (tstate != NULL)
7173 : lstate = tstate->enabled_luns[lun];
7174 :
7175 : /*
7176 : * Commands for disabled luns go to the black hole driver.
7177 : */
7178 : if (lstate == NULL)
7179 : lstate = ahc->black_hole;
7180 :
7181 : atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7182 : if (atio == NULL) {
7183 : ahc->flags |= AHC_TQINFIFO_BLOCKED;
7184 : /*
7185 : * Wait for more ATIOs from the peripheral driver for this lun.
7186 : */
7187 : if (bootverbose)
7188 : printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7189 : return (1);
7190 : } else
7191 : ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7192 : #if 0
7193 : printf("Incoming command from %d for %d:%d%s\n",
7194 : initiator, target, lun,
7195 : lstate == ahc->black_hole ? "(Black Holed)" : "");
7196 : #endif
7197 : SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7198 :
7199 : if (lstate == ahc->black_hole) {
7200 : /* Fill in the wildcards */
7201 : atio->ccb_h.target_id = target;
7202 : atio->ccb_h.target_lun = lun;
7203 : }
7204 :
7205 : /*
7206 : * Package it up and send it off to
7207 : * whomever has this lun enabled.
7208 : */
7209 : atio->sense_len = 0;
7210 : atio->init_id = initiator;
7211 : if (byte[0] != 0xFF) {
7212 : /* Tag was included */
7213 : atio->tag_action = *byte++;
7214 : atio->tag_id = *byte++;
7215 : atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7216 : } else {
7217 : atio->ccb_h.flags = 0;
7218 : }
7219 : byte++;
7220 :
7221 : /* Okay. Now determine the cdb size based on the command code */
7222 : switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7223 : case 0:
7224 : atio->cdb_len = 6;
7225 : break;
7226 : case 1:
7227 : case 2:
7228 : atio->cdb_len = 10;
7229 : break;
7230 : case 4:
7231 : atio->cdb_len = 16;
7232 : break;
7233 : case 5:
7234 : atio->cdb_len = 12;
7235 : break;
7236 : case 3:
7237 : default:
7238 : /* Only copy the opcode. */
7239 : atio->cdb_len = 1;
7240 : printf("Reserved or VU command code type encountered\n");
7241 : break;
7242 : }
7243 :
7244 : memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7245 :
7246 : atio->ccb_h.status |= CAM_CDB_RECVD;
7247 :
7248 : if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7249 : /*
7250 : * We weren't allowed to disconnect.
7251 : * We're hanging on the bus until a
7252 : * continue target I/O comes in response
7253 : * to this accept tio.
7254 : */
7255 : #if 0
7256 : printf("Received Immediate Command %d:%d:%d - %p\n",
7257 : initiator, target, lun, ahc->pending_device);
7258 : #endif
7259 : ahc->pending_device = lstate;
7260 : ahc_freeze_ccb((union ccb *)atio);
7261 : atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7262 : }
7263 : xpt_done((union ccb*)atio);
7264 : return (0);
7265 : }
7266 : #endif
7267 :
7268 : static int
7269 0 : ahc_createdmamem(bus_dma_tag_t tag, int size, int flags, bus_dmamap_t *mapp,
7270 : caddr_t *vaddr, bus_addr_t *baddr, bus_dma_segment_t *seg, int *nseg,
7271 : const char *myname, const char *what)
7272 : {
7273 : int error;
7274 :
7275 0 : if ((error = bus_dmamap_create(tag, size, 1, size, 0,
7276 0 : BUS_DMA_NOWAIT | flags, mapp)) != 0) {
7277 0 : printf("%s: failed to create DMA map for %s, error = %d\n",
7278 : myname, what, error);
7279 0 : return (error);
7280 : }
7281 :
7282 0 : if ((error = bus_dmamem_alloc(tag, size, PAGE_SIZE, 0,
7283 0 : seg, 1, nseg, BUS_DMA_NOWAIT)) != 0) {
7284 0 : printf("%s: failed to allocate DMA mem for %s, error = %d\n",
7285 : myname, what, error);
7286 0 : goto destroy;
7287 : }
7288 :
7289 0 : if ((error = bus_dmamem_map(tag, seg, *nseg, size, vaddr,
7290 0 : BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
7291 0 : printf("%s: failed to map DMA mem for %s, error = %d\n",
7292 : myname, what, error);
7293 0 : goto free;
7294 : }
7295 :
7296 0 : if ((error = bus_dmamap_load(tag, *mapp, *vaddr, size, NULL,
7297 0 : BUS_DMA_NOWAIT)) != 0) {
7298 0 : printf("%s: failed to load DMA map for %s, error = %d\n",
7299 : myname, what, error);
7300 : goto unmap;
7301 : }
7302 :
7303 0 : *baddr = (*mapp)->dm_segs[0].ds_addr;
7304 0 : return (0);
7305 :
7306 : unmap:
7307 0 : bus_dmamem_unmap(tag, *vaddr, size);
7308 : free:
7309 0 : bus_dmamem_free(tag, seg, *nseg);
7310 : destroy:
7311 0 : bus_dmamap_destroy(tag, *mapp);
7312 :
7313 0 : *vaddr = 0;
7314 0 : bzero(seg, sizeof(*seg));
7315 0 : return (error);
7316 0 : }
7317 :
7318 : static void
7319 0 : ahc_freedmamem(bus_dma_tag_t tag, int size, bus_dmamap_t map, caddr_t vaddr,
7320 : bus_dma_segment_t *seg, int nseg)
7321 : {
7322 :
7323 0 : bus_dmamap_unload(tag, map);
7324 0 : bus_dmamem_unmap(tag, vaddr, size);
7325 0 : bus_dmamem_free(tag, seg, nseg);
7326 0 : bus_dmamap_destroy(tag, map);
7327 0 : }
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