Line data Source code
1 : /* $OpenBSD: ar5211.c,v 1.50 2018/01/31 11:27:03 stsp Exp $ */
2 :
3 : /*
4 : * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 : *
6 : * Permission to use, copy, modify, and distribute this software for any
7 : * purpose with or without fee is hereby granted, provided that the above
8 : * copyright notice and this permission notice appear in all copies.
9 : *
10 : * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 : * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 : * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 : * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 : * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 : * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 : * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 : */
18 :
19 : /*
20 : * HAL interface for the Atheros AR5001 Wireless LAN chipset
21 : * (AR5211 + AR5111).
22 : */
23 :
24 : #include <dev/ic/ar5xxx.h>
25 : #include <dev/ic/ar5211reg.h>
26 : #include <dev/ic/ar5211var.h>
27 :
28 : HAL_BOOL ar5k_ar5211_nic_reset(struct ath_hal *, u_int32_t);
29 : HAL_BOOL ar5k_ar5211_nic_wakeup(struct ath_hal *, u_int16_t);
30 : u_int16_t ar5k_ar5211_radio_revision(struct ath_hal *, HAL_CHIP);
31 : void ar5k_ar5211_fill(struct ath_hal *);
32 : HAL_BOOL ar5k_ar5211_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int,
33 : u_int);
34 :
35 : /*
36 : * Initial register setting for the AR5211
37 : */
38 : static const struct ar5k_ini ar5211_ini[] =
39 : AR5K_AR5211_INI;
40 : static const struct ar5k_ar5211_ini_mode ar5211_mode[] =
41 : AR5K_AR5211_INI_MODE;
42 : static const struct ar5k_ar5211_ini_rf ar5211_rf[] =
43 : AR5K_AR5211_INI_RF;
44 :
45 : AR5K_HAL_FUNCTIONS(extern, ar5k_ar5211,);
46 :
47 : void
48 0 : ar5k_ar5211_fill(struct ath_hal *hal)
49 : {
50 0 : hal->ah_magic = AR5K_AR5211_MAGIC;
51 :
52 : /*
53 : * Init/Exit functions
54 : */
55 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_rate_table);
56 0 : AR5K_HAL_FUNCTION(hal, ar5211, detach);
57 :
58 : /*
59 : * Reset functions
60 : */
61 0 : AR5K_HAL_FUNCTION(hal, ar5211, reset);
62 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_opmode);
63 0 : AR5K_HAL_FUNCTION(hal, ar5211, calibrate);
64 :
65 : /*
66 : * TX functions
67 : */
68 0 : AR5K_HAL_FUNCTION(hal, ar5211, update_tx_triglevel);
69 0 : AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queue);
70 0 : AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_queueprops);
71 0 : AR5K_HAL_FUNCTION(hal, ar5211, release_tx_queue);
72 0 : AR5K_HAL_FUNCTION(hal, ar5211, reset_tx_queue);
73 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_tx_buf);
74 0 : AR5K_HAL_FUNCTION(hal, ar5211, put_tx_buf);
75 0 : AR5K_HAL_FUNCTION(hal, ar5211, tx_start);
76 0 : AR5K_HAL_FUNCTION(hal, ar5211, stop_tx_dma);
77 0 : AR5K_HAL_FUNCTION(hal, ar5211, setup_tx_desc);
78 0 : AR5K_HAL_FUNCTION(hal, ar5211, setup_xtx_desc);
79 0 : AR5K_HAL_FUNCTION(hal, ar5211, fill_tx_desc);
80 0 : AR5K_HAL_FUNCTION(hal, ar5211, proc_tx_desc);
81 0 : AR5K_HAL_FUNCTION(hal, ar5211, has_veol);
82 :
83 : /*
84 : * RX functions
85 : */
86 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_rx_buf);
87 0 : AR5K_HAL_FUNCTION(hal, ar5211, put_rx_buf);
88 0 : AR5K_HAL_FUNCTION(hal, ar5211, start_rx);
89 0 : AR5K_HAL_FUNCTION(hal, ar5211, stop_rx_dma);
90 0 : AR5K_HAL_FUNCTION(hal, ar5211, start_rx_pcu);
91 0 : AR5K_HAL_FUNCTION(hal, ar5211, stop_pcu_recv);
92 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filter);
93 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_mcast_filterindex);
94 0 : AR5K_HAL_FUNCTION(hal, ar5211, clear_mcast_filter_idx);
95 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_rx_filter);
96 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_rx_filter);
97 0 : AR5K_HAL_FUNCTION(hal, ar5211, setup_rx_desc);
98 0 : AR5K_HAL_FUNCTION(hal, ar5211, proc_rx_desc);
99 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_rx_signal);
100 :
101 : /*
102 : * Misc functions
103 : */
104 0 : AR5K_HAL_FUNCTION(hal, ar5211, dump_state);
105 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_diag_state);
106 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_lladdr);
107 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_lladdr);
108 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_regdomain);
109 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_ledstate);
110 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_associd);
111 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_input);
112 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_output);
113 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_gpio);
114 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_gpio);
115 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_gpio_intr);
116 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_tsf32);
117 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_tsf64);
118 0 : AR5K_HAL_FUNCTION(hal, ar5211, reset_tsf);
119 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_regdomain);
120 0 : AR5K_HAL_FUNCTION(hal, ar5211, detect_card_present);
121 0 : AR5K_HAL_FUNCTION(hal, ar5211, update_mib_counters);
122 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_rf_gain);
123 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_slot_time);
124 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_slot_time);
125 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_ack_timeout);
126 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_ack_timeout);
127 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_cts_timeout);
128 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_cts_timeout);
129 :
130 : /*
131 : * Key table (WEP) functions
132 : */
133 0 : AR5K_HAL_FUNCTION(hal, ar5211, is_cipher_supported);
134 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_keycache_size);
135 0 : AR5K_HAL_FUNCTION(hal, ar5211, reset_key);
136 0 : AR5K_HAL_FUNCTION(hal, ar5211, is_key_valid);
137 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_key);
138 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_key_lladdr);
139 0 : AR5K_HAL_FUNCTION(hal, ar5211, softcrypto);
140 :
141 : /*
142 : * Power management functions
143 : */
144 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_power);
145 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_power_mode);
146 0 : AR5K_HAL_FUNCTION(hal, ar5211, query_pspoll_support);
147 0 : AR5K_HAL_FUNCTION(hal, ar5211, init_pspoll);
148 0 : AR5K_HAL_FUNCTION(hal, ar5211, enable_pspoll);
149 0 : AR5K_HAL_FUNCTION(hal, ar5211, disable_pspoll);
150 :
151 : /*
152 : * Beacon functions
153 : */
154 0 : AR5K_HAL_FUNCTION(hal, ar5211, init_beacon);
155 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_beacon_timers);
156 0 : AR5K_HAL_FUNCTION(hal, ar5211, reset_beacon);
157 0 : AR5K_HAL_FUNCTION(hal, ar5211, wait_for_beacon);
158 :
159 : /*
160 : * Interrupt functions
161 : */
162 0 : AR5K_HAL_FUNCTION(hal, ar5211, is_intr_pending);
163 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_isr);
164 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_intr);
165 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_intr);
166 :
167 : /*
168 : * Chipset functions (ar5k-specific, non-HAL)
169 : */
170 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_capabilities);
171 0 : AR5K_HAL_FUNCTION(hal, ar5211, radar_alert);
172 :
173 : /*
174 : * EEPROM access
175 : */
176 0 : AR5K_HAL_FUNCTION(hal, ar5211, eeprom_is_busy);
177 0 : AR5K_HAL_FUNCTION(hal, ar5211, eeprom_read);
178 0 : AR5K_HAL_FUNCTION(hal, ar5211, eeprom_write);
179 :
180 : /*
181 : * Unused functions or functions not implemented
182 : */
183 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_tx_queueprops);
184 0 : AR5K_HAL_FUNCTION(hal, ar5211, num_tx_pending);
185 0 : AR5K_HAL_FUNCTION(hal, ar5211, phy_disable);
186 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_txpower_limit);
187 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_def_antenna);
188 0 : AR5K_HAL_FUNCTION(hal, ar5211, get_def_antenna);
189 0 : AR5K_HAL_FUNCTION(hal, ar5211, set_bssid_mask);
190 : #ifdef notyet
191 : AR5K_HAL_FUNCTION(hal, ar5211, set_capability);
192 : AR5K_HAL_FUNCTION(hal, ar5211, proc_mib_event);
193 : AR5K_HAL_FUNCTION(hal, ar5211, get_tx_inter_queue);
194 : #endif
195 0 : }
196 :
197 : struct ath_hal *
198 0 : ar5k_ar5211_attach(u_int16_t device, void *sc, bus_space_tag_t st,
199 : bus_space_handle_t sh, int *status)
200 : {
201 0 : struct ath_hal *hal = (struct ath_hal*) sc;
202 0 : u_int8_t mac[IEEE80211_ADDR_LEN];
203 : u_int32_t srev;
204 :
205 0 : ar5k_ar5211_fill(hal);
206 :
207 : /* Bring device out of sleep and reset its units */
208 0 : if (ar5k_ar5211_nic_wakeup(hal, AR5K_INIT_MODE) != AH_TRUE)
209 0 : return (NULL);
210 :
211 : /* Get MAC, PHY and RADIO revisions */
212 0 : srev = AR5K_REG_READ(AR5K_AR5211_SREV);
213 0 : hal->ah_mac_srev = srev;
214 0 : hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_AR5211_SREV_VER);
215 0 : hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_AR5211_SREV_REV);
216 0 : hal->ah_phy_revision = AR5K_REG_READ(AR5K_AR5211_PHY_CHIP_ID) &
217 : 0x00ffffffff;
218 0 : hal->ah_radio_5ghz_revision =
219 0 : ar5k_ar5211_radio_revision(hal, HAL_CHIP_5GHZ);
220 0 : hal->ah_radio_2ghz_revision = 0;
221 :
222 : /* Identify the chipset (this has to be done in an early step) */
223 0 : hal->ah_version = AR5K_AR5211;
224 0 : hal->ah_radio = AR5K_AR5111;
225 0 : hal->ah_phy = AR5K_AR5211_PHY(0);
226 :
227 0 : bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN);
228 0 : ar5k_ar5211_set_associd(hal, mac, 0, 0);
229 0 : ar5k_ar5211_get_lladdr(hal, mac);
230 0 : ar5k_ar5211_set_opmode(hal);
231 :
232 0 : return (hal);
233 0 : }
234 :
235 : HAL_BOOL
236 0 : ar5k_ar5211_nic_reset(struct ath_hal *hal, u_int32_t val)
237 : {
238 : HAL_BOOL ret = AH_FALSE;
239 0 : u_int32_t mask = val ? val : ~0;
240 :
241 : /* Read-and-clear */
242 0 : AR5K_REG_READ(AR5K_AR5211_RXDP);
243 :
244 : /*
245 : * Reset the device and wait until success
246 : */
247 0 : AR5K_REG_WRITE(AR5K_AR5211_RC, val);
248 :
249 : /* Wait at least 128 PCI clocks */
250 0 : AR5K_DELAY(15);
251 :
252 0 : val &=
253 : AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB;
254 :
255 0 : mask &=
256 : AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB;
257 :
258 0 : ret = ar5k_register_timeout(hal, AR5K_AR5211_RC, mask, val, AH_FALSE);
259 :
260 : /*
261 : * Reset configuration register
262 : */
263 0 : if ((val & AR5K_AR5211_RC_PCU) == 0)
264 0 : AR5K_REG_WRITE(AR5K_AR5211_CFG, AR5K_AR5211_INIT_CFG);
265 :
266 0 : return (ret);
267 : }
268 :
269 : HAL_BOOL
270 0 : ar5k_ar5211_nic_wakeup(struct ath_hal *hal, u_int16_t flags)
271 : {
272 : u_int32_t turbo, mode, clock;
273 :
274 : turbo = 0;
275 : mode = 0;
276 : clock = 0;
277 :
278 : /*
279 : * Get channel mode flags
280 : */
281 :
282 0 : if (flags & IEEE80211_CHAN_2GHZ) {
283 : mode |= AR5K_AR5211_PHY_MODE_FREQ_2GHZ;
284 : clock |= AR5K_AR5211_PHY_PLL_44MHZ;
285 0 : } else if (flags & IEEE80211_CHAN_5GHZ) {
286 : mode |= AR5K_AR5211_PHY_MODE_FREQ_5GHZ;
287 : clock |= AR5K_AR5211_PHY_PLL_40MHZ;
288 : } else {
289 0 : AR5K_PRINT("invalid radio frequency mode\n");
290 0 : return (AH_FALSE);
291 : }
292 :
293 0 : if ((flags & IEEE80211_CHAN_CCK) ||
294 0 : (flags & IEEE80211_CHAN_DYN)) {
295 : /* Dynamic OFDM/CCK is not supported by the AR5211 */
296 0 : mode |= AR5K_AR5211_PHY_MODE_MOD_CCK;
297 0 : } else if (flags & IEEE80211_CHAN_OFDM) {
298 : mode |= AR5K_AR5211_PHY_MODE_MOD_OFDM;
299 : } else {
300 0 : AR5K_PRINT("invalid radio frequency mode\n");
301 0 : return (AH_FALSE);
302 : }
303 :
304 : /*
305 : * Reset and wakeup the device
306 : */
307 :
308 : /* ...reset chipset and PCI device */
309 0 : if (ar5k_ar5211_nic_reset(hal,
310 0 : AR5K_AR5211_RC_CHIP | AR5K_AR5211_RC_PCI) == AH_FALSE) {
311 0 : AR5K_PRINT("failed to reset the AR5211 + PCI chipset\n");
312 0 : return (AH_FALSE);
313 : }
314 :
315 : /* ...wakeup */
316 0 : if (ar5k_ar5211_set_power(hal,
317 0 : HAL_PM_AWAKE, AH_TRUE, 0) == AH_FALSE) {
318 0 : AR5K_PRINT("failed to resume the AR5211 (again)\n");
319 0 : return (AH_FALSE);
320 : }
321 :
322 : /* ...final warm reset */
323 0 : if (ar5k_ar5211_nic_reset(hal, 0) == AH_FALSE) {
324 0 : AR5K_PRINT("failed to warm reset the AR5211\n");
325 0 : return (AH_FALSE);
326 : }
327 :
328 : /* ...set the PHY operating mode */
329 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_PLL, clock);
330 0 : AR5K_DELAY(300);
331 :
332 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_MODE, mode);
333 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_TURBO, turbo);
334 :
335 0 : return (AH_TRUE);
336 0 : }
337 :
338 : u_int16_t
339 0 : ar5k_ar5211_radio_revision(struct ath_hal *hal, HAL_CHIP chip)
340 : {
341 : int i;
342 : u_int32_t srev;
343 : u_int16_t ret;
344 :
345 : /*
346 : * Set the radio chip access register
347 : */
348 0 : switch (chip) {
349 : case HAL_CHIP_2GHZ:
350 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_2GHZ);
351 0 : break;
352 : case HAL_CHIP_5GHZ:
353 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ);
354 0 : break;
355 : default:
356 0 : return (0);
357 : }
358 :
359 0 : AR5K_DELAY(2000);
360 :
361 : /* ...wait until PHY is ready and read the selected radio revision */
362 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY(0x34), 0x00001c16);
363 :
364 0 : for (i = 0; i < 8; i++)
365 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY(0x20), 0x00010000);
366 0 : srev = (AR5K_REG_READ(AR5K_AR5211_PHY(0x100)) >> 24) & 0xff;
367 :
368 0 : ret = ar5k_bitswap(((srev & 0xf0) >> 4) | ((srev & 0x0f) << 4), 8);
369 :
370 : /* Reset to the 5GHz mode */
371 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ);
372 :
373 0 : return (ret);
374 0 : }
375 :
376 : const HAL_RATE_TABLE *
377 0 : ar5k_ar5211_get_rate_table(struct ath_hal *hal, u_int mode)
378 : {
379 0 : switch (mode) {
380 : case HAL_MODE_11A:
381 0 : return (&hal->ah_rt_11a);
382 : case HAL_MODE_11B:
383 0 : return (&hal->ah_rt_11b);
384 : case HAL_MODE_11G:
385 : case HAL_MODE_PUREG:
386 0 : return (&hal->ah_rt_11g);
387 : default:
388 0 : return (NULL);
389 : }
390 :
391 : return (NULL);
392 0 : }
393 :
394 : void
395 0 : ar5k_ar5211_detach(struct ath_hal *hal)
396 : {
397 : /*
398 : * Free HAL structure, assume interrupts are down
399 : */
400 0 : free(hal, M_DEVBUF, 0);
401 0 : }
402 :
403 : HAL_BOOL
404 0 : ar5k_ar5211_phy_disable(struct ath_hal *hal)
405 : {
406 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_DISABLE);
407 0 : return (AH_TRUE);
408 : }
409 :
410 : HAL_BOOL
411 0 : ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
412 : HAL_BOOL change_channel, HAL_STATUS *status)
413 : {
414 0 : struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
415 0 : u_int8_t mac[IEEE80211_ADDR_LEN];
416 : u_int32_t data, s_seq, s_ant, s_led[3];
417 : u_int i, mode, freq, ee_mode, ant[2];
418 :
419 : /* Not used, keep for HAL compatibility */
420 0 : *status = HAL_OK;
421 :
422 : /*
423 : * Save some registers before a reset
424 : */
425 0 : if (change_channel == AH_TRUE) {
426 0 : s_seq = AR5K_REG_READ(AR5K_AR5211_DCU_SEQNUM(0));
427 0 : s_ant = AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA);
428 0 : } else {
429 : s_seq = 0;
430 : s_ant = 1;
431 : }
432 :
433 0 : s_led[0] = AR5K_REG_READ(AR5K_AR5211_PCICFG) &
434 : AR5K_AR5211_PCICFG_LEDSTATE;
435 0 : s_led[1] = AR5K_REG_READ(AR5K_AR5211_GPIOCR);
436 0 : s_led[2] = AR5K_REG_READ(AR5K_AR5211_GPIODO);
437 :
438 0 : if (ar5k_ar5211_nic_wakeup(hal, channel->c_channel_flags) == AH_FALSE)
439 0 : return (AH_FALSE);
440 :
441 : /*
442 : * Initialize operating mode
443 : */
444 0 : hal->ah_op_mode = op_mode;
445 :
446 0 : if ((channel->c_channel_flags & CHANNEL_A) == CHANNEL_A) {
447 : mode = AR5K_INI_VAL_11A;
448 : freq = AR5K_INI_RFGAIN_5GHZ;
449 : ee_mode = AR5K_EEPROM_MODE_11A;
450 0 : } else if ((channel->c_channel_flags & CHANNEL_B) == CHANNEL_B) {
451 0 : if (hal->ah_capabilities.cap_mode & HAL_MODE_11B) {
452 : mode = AR5K_INI_VAL_11B;
453 : ee_mode = AR5K_EEPROM_MODE_11B;
454 0 : } else {
455 : mode = AR5K_INI_VAL_11G;
456 : ee_mode = AR5K_EEPROM_MODE_11G;
457 : }
458 : freq = AR5K_INI_RFGAIN_2GHZ;
459 0 : } else if ((channel->c_channel_flags & (CHANNEL_G | CHANNEL_PUREG)) ==
460 : (CHANNEL_G | CHANNEL_PUREG)) {
461 : mode = AR5K_INI_VAL_11G;
462 : freq = AR5K_INI_RFGAIN_2GHZ;
463 : ee_mode = AR5K_EEPROM_MODE_11G;
464 : } else {
465 0 : AR5K_PRINTF("invalid channel: %d\n", channel->c_channel);
466 0 : return (AH_FALSE);
467 : }
468 :
469 : /* PHY access enable */
470 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY(0), AR5K_AR5211_PHY_SHIFT_5GHZ);
471 :
472 : /*
473 : * Write initial RF registers
474 : */
475 0 : if (ar5k_ar5211_rfregs(hal, channel, freq, ee_mode) == AH_FALSE)
476 0 : return (AH_FALSE);
477 :
478 : /*
479 : * Write initial mode settings
480 : */
481 0 : for (i = 0; i < nitems(ar5211_mode); i++) {
482 0 : AR5K_REG_WAIT(i);
483 0 : AR5K_REG_WRITE((u_int32_t)ar5211_mode[i].mode_register,
484 : ar5211_mode[i].mode_value[mode]);
485 : }
486 :
487 : /*
488 : * Write initial register settings
489 : */
490 0 : for (i = 0; i < nitems(ar5211_ini); i++) {
491 0 : if (change_channel == AH_TRUE &&
492 0 : ar5211_ini[i].ini_register >= AR5K_AR5211_PCU_MIN &&
493 0 : ar5211_ini[i].ini_register <= AR5K_AR5211_PCU_MAX)
494 : continue;
495 :
496 0 : AR5K_REG_WAIT(i);
497 0 : AR5K_REG_WRITE((u_int32_t)ar5211_ini[i].ini_register,
498 : ar5211_ini[i].ini_value);
499 0 : }
500 :
501 : /*
502 : * Write initial RF gain settings
503 : */
504 0 : if (ar5k_rfgain(hal, freq) == AH_FALSE)
505 0 : return (AH_FALSE);
506 :
507 0 : AR5K_DELAY(1000);
508 :
509 : /*
510 : * Configure additional registers
511 : */
512 :
513 0 : if (hal->ah_radio == AR5K_AR5111) {
514 0 : if (channel->c_channel_flags & IEEE80211_CHAN_B)
515 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_TXCFG,
516 : AR5K_AR5211_TXCFG_B_MODE);
517 : else
518 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_TXCFG,
519 : AR5K_AR5211_TXCFG_B_MODE);
520 : }
521 :
522 : /* Set antenna mode */
523 0 : AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x44),
524 : hal->ah_antenna[ee_mode][0], 0xfffffc06);
525 :
526 0 : if (freq == AR5K_INI_RFGAIN_2GHZ)
527 0 : ant[0] = ant[1] = HAL_ANT_FIXED_B;
528 : else
529 : ant[0] = ant[1] = HAL_ANT_FIXED_A;
530 :
531 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0,
532 : hal->ah_antenna[ee_mode][ant[0]]);
533 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1,
534 : hal->ah_antenna[ee_mode][ant[1]]);
535 :
536 : /* Commit values from EEPROM */
537 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_FC,
538 : AR5K_AR5211_PHY_FC_TX_CLIP, ee->ee_tx_clip);
539 :
540 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY(0x5a),
541 : AR5K_AR5211_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]));
542 :
543 0 : AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x11),
544 : (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, 0xffffc07f);
545 0 : AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x12),
546 : (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, 0xfffc0fff);
547 0 : AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x14),
548 : (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
549 : ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), 0xffff0000);
550 :
551 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY(0x0d),
552 : (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
553 : (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
554 : (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
555 : (ee->ee_tx_frm2xpa_enable[ee_mode]));
556 :
557 0 : AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x0a),
558 : ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
559 0 : AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x19),
560 : (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
561 0 : AR5K_REG_MASKED_BITS(AR5K_AR5211_PHY(0x49), 4, 0xffffff01);
562 :
563 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ,
564 : AR5K_AR5211_PHY_IQ_CORR_ENABLE |
565 : (ee->ee_i_cal[ee_mode] << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S) |
566 : ee->ee_q_cal[ee_mode]);
567 :
568 : /*
569 : * Restore saved values
570 : */
571 0 : AR5K_REG_WRITE(AR5K_AR5211_DCU_SEQNUM(0), s_seq);
572 0 : AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, s_ant);
573 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, s_led[0]);
574 0 : AR5K_REG_WRITE(AR5K_AR5211_GPIOCR, s_led[1]);
575 0 : AR5K_REG_WRITE(AR5K_AR5211_GPIODO, s_led[2]);
576 :
577 : /*
578 : * Misc
579 : */
580 0 : bcopy(etherbroadcastaddr, mac, IEEE80211_ADDR_LEN);
581 0 : ar5k_ar5211_set_associd(hal, mac, 0, 0);
582 0 : ar5k_ar5211_set_opmode(hal);
583 0 : AR5K_REG_WRITE(AR5K_AR5211_PISR, 0xffffffff);
584 0 : AR5K_REG_WRITE(AR5K_AR5211_RSSI_THR, AR5K_TUNE_RSSI_THRES);
585 :
586 : /*
587 : * Set Rx/Tx DMA Configuration
588 : */
589 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG, AR5K_AR5211_TXCFG_SDMAMR,
590 : AR5K_AR5211_DMASIZE_512B | AR5K_AR5211_TXCFG_DMASIZE);
591 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_RXCFG, AR5K_AR5211_RXCFG_SDMAMW,
592 : AR5K_AR5211_DMASIZE_512B);
593 :
594 : /*
595 : * Set channel and calibrate the PHY
596 : */
597 0 : if (ar5k_channel(hal, channel) == AH_FALSE)
598 0 : return (AH_FALSE);
599 :
600 : /*
601 : * Enable the PHY and wait until completion
602 : */
603 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_ACTIVE, AR5K_AR5211_PHY_ENABLE);
604 :
605 0 : data = AR5K_REG_READ(AR5K_AR5211_PHY_RX_DELAY) &
606 : AR5K_AR5211_PHY_RX_DELAY_M;
607 0 : data = (channel->c_channel_flags & IEEE80211_CHAN_CCK) ?
608 0 : ((data << 2) / 22) : (data / 10);
609 :
610 0 : AR5K_DELAY(100 + data);
611 :
612 : /*
613 : * Start calibration
614 : */
615 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL,
616 : AR5K_AR5211_PHY_AGCCTL_NF |
617 : AR5K_AR5211_PHY_AGCCTL_CAL);
618 :
619 0 : if (channel->c_channel_flags & IEEE80211_CHAN_B) {
620 0 : hal->ah_calibration = AH_FALSE;
621 0 : } else {
622 0 : hal->ah_calibration = AH_TRUE;
623 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_PHY_IQ,
624 : AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX, 15);
625 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ,
626 : AR5K_AR5211_PHY_IQ_RUN);
627 : }
628 :
629 : /*
630 : * Reset queues and start beacon timers at the end of the reset routine
631 : */
632 0 : for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
633 0 : AR5K_REG_WRITE_Q(AR5K_AR5211_DCU_QCUMASK(i), i);
634 0 : if (ar5k_ar5211_reset_tx_queue(hal, i) == AH_FALSE) {
635 0 : AR5K_PRINTF("failed to reset TX queue #%d\n", i);
636 0 : return (AH_FALSE);
637 : }
638 : }
639 :
640 : /* Pre-enable interrupts */
641 0 : ar5k_ar5211_set_intr(hal, HAL_INT_RX | HAL_INT_TX | HAL_INT_FATAL);
642 :
643 : /*
644 : * Set RF kill flags if supported by the device (read from the EEPROM)
645 : */
646 0 : if (AR5K_EEPROM_HDR_RFKILL(hal->ah_capabilities.cap_eeprom.ee_header)) {
647 0 : ar5k_ar5211_set_gpio_input(hal, 0);
648 0 : if ((hal->ah_gpio[0] = ar5k_ar5211_get_gpio(hal, 0)) == 0)
649 0 : ar5k_ar5211_set_gpio_intr(hal, 0, 1);
650 : else
651 0 : ar5k_ar5211_set_gpio_intr(hal, 0, 0);
652 : }
653 :
654 : /*
655 : * Disable beacons and reset the register
656 : */
657 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_BEACON,
658 : AR5K_AR5211_BEACON_ENABLE | AR5K_AR5211_BEACON_RESET_TSF);
659 :
660 0 : return (AH_TRUE);
661 0 : }
662 :
663 : void
664 0 : ar5k_ar5211_set_def_antenna(struct ath_hal *hal, u_int ant)
665 : {
666 0 : AR5K_REG_WRITE(AR5K_AR5211_DEFAULT_ANTENNA, ant);
667 0 : }
668 :
669 : u_int
670 0 : ar5k_ar5211_get_def_antenna(struct ath_hal *hal)
671 : {
672 0 : return AR5K_REG_READ(AR5K_AR5211_DEFAULT_ANTENNA);
673 : }
674 :
675 : void
676 0 : ar5k_ar5211_set_opmode(struct ath_hal *hal)
677 : {
678 : u_int32_t pcu_reg, low_id, high_id;
679 :
680 : pcu_reg = 0;
681 :
682 0 : switch (hal->ah_op_mode) {
683 : #ifndef IEEE80211_STA_ONLY
684 : case IEEE80211_M_IBSS:
685 : pcu_reg |= AR5K_AR5211_STA_ID1_ADHOC |
686 : AR5K_AR5211_STA_ID1_DESC_ANTENNA;
687 0 : break;
688 :
689 : case IEEE80211_M_HOSTAP:
690 : pcu_reg |= AR5K_AR5211_STA_ID1_AP |
691 : AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA;
692 0 : break;
693 : #endif
694 :
695 : case IEEE80211_M_STA:
696 : case IEEE80211_M_MONITOR:
697 : pcu_reg |= AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA;
698 0 : break;
699 :
700 : default:
701 0 : return;
702 : }
703 :
704 : /*
705 : * Set PCU registers
706 : */
707 0 : low_id = AR5K_LOW_ID(hal->ah_sta_id);
708 0 : high_id = AR5K_HIGH_ID(hal->ah_sta_id);
709 0 : AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id);
710 0 : AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, pcu_reg | high_id);
711 :
712 0 : return;
713 0 : }
714 :
715 : HAL_BOOL
716 0 : ar5k_ar5211_calibrate(struct ath_hal *hal, HAL_CHANNEL *channel)
717 : {
718 : u_int32_t i_pwr, q_pwr;
719 : int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd;
720 :
721 0 : if (hal->ah_calibration == AH_FALSE ||
722 0 : AR5K_REG_READ(AR5K_AR5211_PHY_IQ) & AR5K_AR5211_PHY_IQ_RUN)
723 : goto done;
724 :
725 0 : hal->ah_calibration = AH_FALSE;
726 :
727 0 : iq_corr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_CORR);
728 0 : i_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_I);
729 0 : q_pwr = AR5K_REG_READ(AR5K_AR5211_PHY_IQRES_CAL_PWR_Q);
730 0 : i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
731 0 : q_coffd = q_pwr >> 6;
732 :
733 0 : if (i_coffd == 0 || q_coffd == 0)
734 : goto done;
735 :
736 0 : i_coff = ((-iq_corr) / i_coffd) & 0x3f;
737 0 : q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f;
738 :
739 : /* Commit new IQ value */
740 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_IQ,
741 : AR5K_AR5211_PHY_IQ_CORR_ENABLE |
742 : ((u_int32_t)q_coff) |
743 : ((u_int32_t)i_coff << AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S));
744 :
745 : done:
746 : /* Start noise floor calibration */
747 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PHY_AGCCTL,
748 : AR5K_AR5211_PHY_AGCCTL_NF);
749 :
750 0 : return (AH_TRUE);
751 : }
752 :
753 : /*
754 : * Transmit functions
755 : */
756 :
757 : HAL_BOOL
758 0 : ar5k_ar5211_update_tx_triglevel(struct ath_hal *hal, HAL_BOOL increase)
759 : {
760 : u_int32_t trigger_level, imr;
761 : HAL_BOOL status = AH_FALSE;
762 :
763 : /*
764 : * Disable interrupts by setting the mask
765 : */
766 0 : imr = ar5k_ar5211_set_intr(hal, hal->ah_imr & ~HAL_INT_GLOBAL);
767 :
768 0 : trigger_level = AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TXCFG),
769 : AR5K_AR5211_TXCFG_TXFULL);
770 :
771 0 : if (increase == AH_FALSE) {
772 0 : if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
773 : goto done;
774 : } else
775 0 : trigger_level +=
776 0 : ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
777 :
778 : /*
779 : * Update trigger level on success
780 : */
781 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_TXCFG,
782 : AR5K_AR5211_TXCFG_TXFULL, trigger_level);
783 0 : status = AH_TRUE;
784 :
785 : done:
786 : /*
787 : * Restore interrupt mask
788 : */
789 0 : ar5k_ar5211_set_intr(hal, imr);
790 :
791 0 : return (status);
792 : }
793 :
794 : int
795 0 : ar5k_ar5211_setup_tx_queue(struct ath_hal *hal, HAL_TX_QUEUE queue_type,
796 : const HAL_TXQ_INFO *queue_info)
797 : {
798 : u_int queue;
799 :
800 : /*
801 : * Get queue by type
802 : */
803 0 : if (queue_type == HAL_TX_QUEUE_DATA) {
804 0 : for (queue = HAL_TX_QUEUE_ID_DATA_MIN;
805 0 : hal->ah_txq[queue].tqi_type != HAL_TX_QUEUE_INACTIVE;
806 0 : queue++)
807 0 : if (queue > HAL_TX_QUEUE_ID_DATA_MAX)
808 0 : return (-1);
809 0 : } else if (queue_type == HAL_TX_QUEUE_PSPOLL) {
810 : queue = HAL_TX_QUEUE_ID_PSPOLL;
811 0 : } else if (queue_type == HAL_TX_QUEUE_BEACON) {
812 : queue = HAL_TX_QUEUE_ID_BEACON;
813 0 : } else if (queue_type == HAL_TX_QUEUE_CAB) {
814 : queue = HAL_TX_QUEUE_ID_CAB;
815 : } else
816 0 : return (-1);
817 :
818 : /*
819 : * Setup internal queue structure
820 : */
821 0 : bzero(&hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
822 0 : hal->ah_txq[queue].tqi_type = queue_type;
823 :
824 0 : if (queue_info != NULL) {
825 0 : if (ar5k_ar5211_setup_tx_queueprops(hal, queue, queue_info)
826 0 : != AH_TRUE)
827 0 : return (-1);
828 : }
829 :
830 0 : AR5K_Q_ENABLE_BITS(hal->ah_txq_interrupts, queue);
831 :
832 0 : return (queue);
833 0 : }
834 :
835 : HAL_BOOL
836 0 : ar5k_ar5211_setup_tx_queueprops(struct ath_hal *hal, int queue,
837 : const HAL_TXQ_INFO *queue_info)
838 : {
839 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
840 :
841 0 : if (hal->ah_txq[queue].tqi_type == HAL_TX_QUEUE_INACTIVE)
842 0 : return (AH_FALSE);
843 :
844 0 : bcopy(queue_info, &hal->ah_txq[queue], sizeof(HAL_TXQ_INFO));
845 :
846 0 : if (queue_info->tqi_type == HAL_TX_QUEUE_DATA &&
847 0 : (queue_info->tqi_subtype >= HAL_WME_AC_VI) &&
848 0 : (queue_info->tqi_subtype <= HAL_WME_UPSD))
849 0 : hal->ah_txq[queue].tqi_flags |=
850 : AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
851 :
852 0 : return (AH_TRUE);
853 0 : }
854 :
855 : HAL_BOOL
856 0 : ar5k_ar5211_get_tx_queueprops(struct ath_hal *hal, int queue,
857 : HAL_TXQ_INFO *queue_info)
858 : {
859 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
860 0 : bcopy(&hal->ah_txq[queue], queue_info, sizeof(HAL_TXQ_INFO));
861 0 : return (AH_TRUE);
862 0 : }
863 :
864 : HAL_BOOL
865 0 : ar5k_ar5211_release_tx_queue(struct ath_hal *hal, u_int queue)
866 : {
867 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
868 :
869 : /* This queue will be skipped in further operations */
870 0 : hal->ah_txq[queue].tqi_type = HAL_TX_QUEUE_INACTIVE;
871 0 : AR5K_Q_DISABLE_BITS(hal->ah_txq_interrupts, queue);
872 :
873 0 : return (AH_FALSE);
874 0 : }
875 :
876 : HAL_BOOL
877 0 : ar5k_ar5211_reset_tx_queue(struct ath_hal *hal, u_int queue)
878 : {
879 : u_int32_t cw_min, cw_max, retry_lg, retry_sh;
880 0 : struct ieee80211_channel *channel = (struct ieee80211_channel*)
881 0 : &hal->ah_current_channel;
882 : HAL_TXQ_INFO *tq;
883 :
884 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
885 :
886 0 : tq = &hal->ah_txq[queue];
887 :
888 0 : if (tq->tqi_type == HAL_TX_QUEUE_INACTIVE)
889 0 : return (AH_TRUE);
890 :
891 : /*
892 : * Set registers by channel mode
893 : */
894 0 : if (IEEE80211_IS_CHAN_B(channel)) {
895 0 : hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;
896 0 : cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B;
897 0 : hal->ah_aifs = AR5K_TUNE_AIFS_11B;
898 0 : } else {
899 0 : hal->ah_cw_min = AR5K_TUNE_CWMIN;
900 0 : cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX;
901 0 : hal->ah_aifs = AR5K_TUNE_AIFS;
902 : }
903 :
904 : /*
905 : * Set retry limits
906 : */
907 0 : if (hal->ah_software_retry == AH_TRUE) {
908 : /* XXX Need to test this */
909 0 : retry_lg = hal->ah_limit_tx_retries;
910 : retry_sh = retry_lg =
911 0 : retry_lg > AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY ?
912 : AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY : retry_lg;
913 0 : } else {
914 : retry_lg = AR5K_INIT_LG_RETRY;
915 : retry_sh = AR5K_INIT_SH_RETRY;
916 : }
917 :
918 0 : AR5K_REG_WRITE(AR5K_AR5211_DCU_RETRY_LMT(queue),
919 : AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
920 : AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY) |
921 : AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
922 : AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY) |
923 : AR5K_REG_SM(retry_lg, AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY) |
924 : AR5K_REG_SM(retry_sh, AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY));
925 :
926 : /*
927 : * Set initial content window (cw_min/cw_max)
928 : */
929 : cw_min = 1;
930 0 : while (cw_min < hal->ah_cw_min)
931 0 : cw_min = (cw_min << 1) | 1;
932 :
933 0 : cw_min = tq->tqi_cw_min < 0 ?
934 0 : (cw_min >> (-tq->tqi_cw_min)) :
935 0 : ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
936 0 : cw_max = tq->tqi_cw_max < 0 ?
937 0 : (cw_max >> (-tq->tqi_cw_max)) :
938 0 : ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
939 :
940 0 : AR5K_REG_WRITE(AR5K_AR5211_DCU_LCL_IFS(queue),
941 : AR5K_REG_SM(cw_min, AR5K_AR5211_DCU_LCL_IFS_CW_MIN) |
942 : AR5K_REG_SM(cw_max, AR5K_AR5211_DCU_LCL_IFS_CW_MAX) |
943 : AR5K_REG_SM(hal->ah_aifs + tq->tqi_aifs,
944 : AR5K_AR5211_DCU_LCL_IFS_AIFS));
945 :
946 : /*
947 : * Set misc registers
948 : */
949 0 : AR5K_REG_WRITE(AR5K_AR5211_QCU_MISC(queue),
950 : AR5K_AR5211_QCU_MISC_DCU_EARLY);
951 :
952 0 : if (tq->tqi_cbr_period) {
953 0 : AR5K_REG_WRITE(AR5K_AR5211_QCU_CBRCFG(queue),
954 : AR5K_REG_SM(tq->tqi_cbr_period,
955 : AR5K_AR5211_QCU_CBRCFG_INTVAL) |
956 : AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
957 : AR5K_AR5211_QCU_CBRCFG_ORN_THRES));
958 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue),
959 : AR5K_AR5211_QCU_MISC_FRSHED_CBR);
960 0 : if (tq->tqi_cbr_overflow_limit)
961 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue),
962 : AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE);
963 : }
964 :
965 0 : if (tq->tqi_ready_time) {
966 0 : AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue),
967 : AR5K_REG_SM(tq->tqi_ready_time,
968 : AR5K_AR5211_QCU_RDYTIMECFG_INTVAL) |
969 : AR5K_AR5211_QCU_RDYTIMECFG_ENABLE);
970 0 : }
971 :
972 0 : if (tq->tqi_burst_time) {
973 0 : AR5K_REG_WRITE(AR5K_AR5211_DCU_CHAN_TIME(queue),
974 : AR5K_REG_SM(tq->tqi_burst_time,
975 : AR5K_AR5211_DCU_CHAN_TIME_DUR) |
976 : AR5K_AR5211_DCU_CHAN_TIME_ENABLE);
977 :
978 0 : if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) {
979 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue),
980 : AR5K_AR5211_QCU_MISC_TXE);
981 0 : }
982 : }
983 :
984 0 : if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) {
985 0 : AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue),
986 : AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS);
987 0 : }
988 :
989 0 : if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
990 0 : AR5K_REG_WRITE(AR5K_AR5211_DCU_MISC(queue),
991 : AR5K_AR5211_DCU_MISC_BACKOFF_FRAG);
992 0 : }
993 :
994 : /*
995 : * Set registers by queue type
996 : */
997 0 : switch (tq->tqi_type) {
998 : case HAL_TX_QUEUE_BEACON:
999 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue),
1000 : AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT |
1001 : AR5K_AR5211_QCU_MISC_CBREXP_BCN |
1002 : AR5K_AR5211_QCU_MISC_BCN_ENABLE);
1003 :
1004 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue),
1005 : (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
1006 : AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL) |
1007 : AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS |
1008 : AR5K_AR5211_DCU_MISC_BCN_ENABLE);
1009 :
1010 0 : AR5K_REG_WRITE(AR5K_AR5211_QCU_RDYTIMECFG(queue),
1011 : ((AR5K_TUNE_BEACON_INTERVAL -
1012 : (AR5K_TUNE_SW_BEACON_RESP - AR5K_TUNE_DMA_BEACON_RESP) -
1013 : AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
1014 : AR5K_AR5211_QCU_RDYTIMECFG_ENABLE);
1015 0 : break;
1016 :
1017 : case HAL_TX_QUEUE_CAB:
1018 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue),
1019 : AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT |
1020 : AR5K_AR5211_QCU_MISC_CBREXP |
1021 : AR5K_AR5211_QCU_MISC_CBREXP_BCN);
1022 :
1023 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_DCU_MISC(queue),
1024 : (AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
1025 : AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL));
1026 0 : break;
1027 :
1028 : case HAL_TX_QUEUE_PSPOLL:
1029 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_QCU_MISC(queue),
1030 : AR5K_AR5211_QCU_MISC_CBREXP);
1031 0 : break;
1032 :
1033 : case HAL_TX_QUEUE_DATA:
1034 : default:
1035 : break;
1036 : }
1037 :
1038 : /*
1039 : * Enable tx queue in the secondary interrupt mask registers
1040 : */
1041 0 : AR5K_REG_WRITE(AR5K_AR5211_SIMR0,
1042 : AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXOK) |
1043 : AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR0_QCU_TXDESC));
1044 0 : AR5K_REG_WRITE(AR5K_AR5211_SIMR1,
1045 : AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR1_QCU_TXERR));
1046 0 : AR5K_REG_WRITE(AR5K_AR5211_SIMR2,
1047 : AR5K_REG_SM(hal->ah_txq_interrupts, AR5K_AR5211_SIMR2_QCU_TXURN));
1048 :
1049 0 : return (AH_TRUE);
1050 0 : }
1051 :
1052 : u_int32_t
1053 0 : ar5k_ar5211_get_tx_buf(struct ath_hal *hal, u_int queue)
1054 : {
1055 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
1056 :
1057 : /*
1058 : * Get the transmit queue descriptor pointer from the selected queue
1059 : */
1060 0 : return (AR5K_REG_READ(AR5K_AR5211_QCU_TXDP(queue)));
1061 0 : }
1062 :
1063 : HAL_BOOL
1064 0 : ar5k_ar5211_put_tx_buf(struct ath_hal *hal, u_int queue, u_int32_t phys_addr)
1065 : {
1066 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
1067 :
1068 : /*
1069 : * Set the transmit queue descriptor pointer for the selected queue
1070 : * (this won't work if the queue is still active)
1071 : */
1072 0 : if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, queue))
1073 0 : return (AH_FALSE);
1074 :
1075 0 : AR5K_REG_WRITE(AR5K_AR5211_QCU_TXDP(queue), phys_addr);
1076 :
1077 0 : return (AH_TRUE);
1078 0 : }
1079 :
1080 : u_int32_t
1081 0 : ar5k_ar5211_num_tx_pending(struct ath_hal *hal, u_int queue)
1082 : {
1083 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
1084 0 : return (AR5K_AR5211_QCU_STS(queue) & AR5K_AR5211_QCU_STS_FRMPENDCNT);
1085 0 : }
1086 :
1087 : HAL_BOOL
1088 0 : ar5k_ar5211_tx_start(struct ath_hal *hal, u_int queue)
1089 : {
1090 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
1091 :
1092 : /* Return if queue is disabled */
1093 0 : if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXD, queue))
1094 0 : return (AH_FALSE);
1095 :
1096 : /* Start queue */
1097 0 : AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXE, queue);
1098 :
1099 0 : return (AH_TRUE);
1100 0 : }
1101 :
1102 : HAL_BOOL
1103 0 : ar5k_ar5211_stop_tx_dma(struct ath_hal *hal, u_int queue)
1104 : {
1105 : int i = 100, pending;
1106 :
1107 0 : AR5K_ASSERT_ENTRY(queue, hal->ah_capabilities.cap_queues.q_tx_num);
1108 :
1109 : /*
1110 : * Schedule TX disable and wait until queue is empty
1111 : */
1112 0 : AR5K_REG_WRITE_Q(AR5K_AR5211_QCU_TXD, queue);
1113 :
1114 0 : do {
1115 0 : pending = AR5K_REG_READ(AR5K_AR5211_QCU_STS(queue)) &
1116 : AR5K_AR5211_QCU_STS_FRMPENDCNT;
1117 0 : delay(100);
1118 0 : } while (--i && pending);
1119 :
1120 : /* Clear register */
1121 0 : AR5K_REG_WRITE(AR5K_AR5211_QCU_TXD, 0);
1122 :
1123 0 : return (AH_TRUE);
1124 0 : }
1125 :
1126 : HAL_BOOL
1127 0 : ar5k_ar5211_setup_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
1128 : u_int packet_length, u_int header_length, HAL_PKT_TYPE type, u_int tx_power,
1129 : u_int tx_rate0, u_int tx_tries0, u_int key_index, u_int antenna_mode,
1130 : u_int flags, u_int rtscts_rate, u_int rtscts_duration)
1131 : {
1132 : struct ar5k_ar5211_tx_desc *tx_desc;
1133 :
1134 0 : tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0;
1135 :
1136 : /*
1137 : * Validate input
1138 : */
1139 0 : if (tx_tries0 == 0)
1140 0 : return (AH_FALSE);
1141 :
1142 0 : if ((tx_desc->tx_control_0 = (packet_length &
1143 0 : AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN)) != packet_length)
1144 0 : return (AH_FALSE);
1145 :
1146 0 : tx_desc->tx_control_0 |=
1147 0 : AR5K_REG_SM(tx_rate0, AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE) |
1148 0 : AR5K_REG_SM(antenna_mode, AR5K_AR5211_DESC_TX_CTL0_ANT_MODE_XMIT);
1149 0 : tx_desc->tx_control_1 =
1150 0 : AR5K_REG_SM(type, AR5K_AR5211_DESC_TX_CTL1_FRAME_TYPE);
1151 :
1152 : #define _TX_FLAGS(_c, _flag) \
1153 : if (flags & HAL_TXDESC_##_flag) \
1154 : tx_desc->tx_control_##_c |= \
1155 : AR5K_AR5211_DESC_TX_CTL##_c##_##_flag
1156 :
1157 0 : _TX_FLAGS(0, CLRDMASK);
1158 0 : _TX_FLAGS(0, VEOL);
1159 0 : _TX_FLAGS(0, INTREQ);
1160 0 : _TX_FLAGS(0, RTSENA);
1161 0 : _TX_FLAGS(1, NOACK);
1162 :
1163 : #undef _TX_FLAGS
1164 :
1165 : /*
1166 : * WEP crap
1167 : */
1168 0 : if (key_index != HAL_TXKEYIX_INVALID) {
1169 0 : tx_desc->tx_control_0 |=
1170 : AR5K_AR5211_DESC_TX_CTL0_ENCRYPT_KEY_VALID;
1171 0 : tx_desc->tx_control_1 |=
1172 0 : AR5K_REG_SM(key_index,
1173 : AR5K_AR5211_DESC_TX_CTL1_ENCRYPT_KEY_INDEX);
1174 0 : }
1175 :
1176 0 : return (AH_TRUE);
1177 0 : }
1178 :
1179 : HAL_BOOL
1180 0 : ar5k_ar5211_fill_tx_desc(struct ath_hal *hal, struct ath_desc *desc,
1181 : u_int segment_length, HAL_BOOL first_segment, HAL_BOOL last_segment)
1182 : {
1183 : struct ar5k_ar5211_tx_desc *tx_desc;
1184 :
1185 0 : tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0;
1186 :
1187 : /* Clear status descriptor */
1188 0 : bzero(desc->ds_hw, sizeof(desc->ds_hw));
1189 :
1190 : /* Validate segment length and initialize the descriptor */
1191 0 : if (segment_length & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN)
1192 0 : return (AH_FALSE);
1193 0 : tx_desc->tx_control_1 =
1194 : #if 0
1195 : (tx_desc->tx_control_1 & ~AR5K_AR5211_DESC_TX_CTL1_BUF_LEN) |
1196 : #endif
1197 : segment_length;
1198 :
1199 0 : if (first_segment != AH_TRUE)
1200 0 : tx_desc->tx_control_0 &= ~AR5K_AR5211_DESC_TX_CTL0_FRAME_LEN;
1201 :
1202 0 : if (last_segment != AH_TRUE)
1203 0 : tx_desc->tx_control_1 |= AR5K_AR5211_DESC_TX_CTL1_MORE;
1204 :
1205 0 : return (AH_TRUE);
1206 0 : }
1207 :
1208 : HAL_BOOL
1209 0 : ar5k_ar5211_setup_xtx_desc(struct ath_hal *hal, struct ath_desc *desc,
1210 : u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
1211 : u_int tx_rate3, u_int tx_tries3)
1212 : {
1213 0 : return (AH_FALSE);
1214 : }
1215 :
1216 : HAL_STATUS
1217 0 : ar5k_ar5211_proc_tx_desc(struct ath_hal *hal, struct ath_desc *desc)
1218 : {
1219 : struct ar5k_ar5211_tx_status *tx_status;
1220 : struct ar5k_ar5211_tx_desc *tx_desc;
1221 :
1222 0 : tx_desc = (struct ar5k_ar5211_tx_desc*)&desc->ds_ctl0;
1223 0 : tx_status = (struct ar5k_ar5211_tx_status*)&desc->ds_hw[0];
1224 :
1225 : /* No frame has been send or error */
1226 0 : if ((tx_status->tx_status_1 & AR5K_AR5211_DESC_TX_STATUS1_DONE) == 0)
1227 0 : return (HAL_EINPROGRESS);
1228 :
1229 : /*
1230 : * Get descriptor status
1231 : */
1232 0 : desc->ds_us.tx.ts_tstamp =
1233 0 : AR5K_REG_MS(tx_status->tx_status_0,
1234 : AR5K_AR5211_DESC_TX_STATUS0_SEND_TIMESTAMP);
1235 0 : desc->ds_us.tx.ts_shortretry =
1236 0 : AR5K_REG_MS(tx_status->tx_status_0,
1237 : AR5K_AR5211_DESC_TX_STATUS0_RTS_FAIL_COUNT);
1238 0 : desc->ds_us.tx.ts_longretry =
1239 0 : AR5K_REG_MS(tx_status->tx_status_0,
1240 : AR5K_AR5211_DESC_TX_STATUS0_DATA_FAIL_COUNT);
1241 0 : desc->ds_us.tx.ts_seqnum =
1242 0 : AR5K_REG_MS(tx_status->tx_status_1,
1243 : AR5K_AR5211_DESC_TX_STATUS1_SEQ_NUM);
1244 0 : desc->ds_us.tx.ts_rssi =
1245 0 : AR5K_REG_MS(tx_status->tx_status_1,
1246 : AR5K_AR5211_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
1247 0 : desc->ds_us.tx.ts_antenna = 1;
1248 0 : desc->ds_us.tx.ts_status = 0;
1249 0 : desc->ds_us.tx.ts_rate =
1250 0 : AR5K_REG_MS(tx_desc->tx_control_0,
1251 : AR5K_AR5211_DESC_TX_CTL0_XMIT_RATE);
1252 :
1253 0 : if ((tx_status->tx_status_0 &
1254 0 : AR5K_AR5211_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0) {
1255 0 : if (tx_status->tx_status_0 &
1256 : AR5K_AR5211_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
1257 0 : desc->ds_us.tx.ts_status |= HAL_TXERR_XRETRY;
1258 :
1259 0 : if (tx_status->tx_status_0 &
1260 : AR5K_AR5211_DESC_TX_STATUS0_FIFO_UNDERRUN)
1261 0 : desc->ds_us.tx.ts_status |= HAL_TXERR_FIFO;
1262 :
1263 0 : if (tx_status->tx_status_0 &
1264 : AR5K_AR5211_DESC_TX_STATUS0_FILTERED)
1265 0 : desc->ds_us.tx.ts_status |= HAL_TXERR_FILT;
1266 : }
1267 :
1268 0 : return (HAL_OK);
1269 0 : }
1270 :
1271 : HAL_BOOL
1272 0 : ar5k_ar5211_has_veol(struct ath_hal *hal)
1273 : {
1274 0 : return (AH_TRUE);
1275 : }
1276 :
1277 : /*
1278 : * Receive functions
1279 : */
1280 :
1281 : u_int32_t
1282 0 : ar5k_ar5211_get_rx_buf(struct ath_hal *hal)
1283 : {
1284 0 : return (AR5K_REG_READ(AR5K_AR5211_RXDP));
1285 : }
1286 :
1287 : void
1288 0 : ar5k_ar5211_put_rx_buf(struct ath_hal *hal, u_int32_t phys_addr)
1289 : {
1290 0 : AR5K_REG_WRITE(AR5K_AR5211_RXDP, phys_addr);
1291 0 : }
1292 :
1293 : void
1294 0 : ar5k_ar5211_start_rx(struct ath_hal *hal)
1295 : {
1296 0 : AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXE);
1297 0 : }
1298 :
1299 : HAL_BOOL
1300 0 : ar5k_ar5211_stop_rx_dma(struct ath_hal *hal)
1301 : {
1302 : int i;
1303 :
1304 0 : AR5K_REG_WRITE(AR5K_AR5211_CR, AR5K_AR5211_CR_RXD);
1305 :
1306 : /*
1307 : * It may take some time to disable the DMA receive unit
1308 : */
1309 0 : for (i = 2000;
1310 0 : i > 0 && (AR5K_REG_READ(AR5K_AR5211_CR) & AR5K_AR5211_CR_RXE) != 0;
1311 0 : i--)
1312 0 : AR5K_DELAY(10);
1313 :
1314 0 : return (i > 0 ? AH_TRUE : AH_FALSE);
1315 : }
1316 :
1317 : void
1318 0 : ar5k_ar5211_start_rx_pcu(struct ath_hal *hal)
1319 : {
1320 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX);
1321 0 : }
1322 :
1323 : void
1324 0 : ar5k_ar5211_stop_pcu_recv(struct ath_hal *hal)
1325 : {
1326 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, AR5K_AR5211_DIAG_SW_DIS_RX);
1327 0 : }
1328 :
1329 : void
1330 0 : ar5k_ar5211_set_mcast_filter(struct ath_hal *hal, u_int32_t filter0,
1331 : u_int32_t filter1)
1332 : {
1333 : /* Set the multicat filter */
1334 0 : AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL0, filter0);
1335 0 : AR5K_REG_WRITE(AR5K_AR5211_MCAST_FIL1, filter1);
1336 0 : }
1337 :
1338 : HAL_BOOL
1339 0 : ar5k_ar5211_set_mcast_filterindex(struct ath_hal *hal, u_int32_t index)
1340 : {
1341 0 : if (index >= 64) {
1342 0 : return (AH_FALSE);
1343 0 : } else if (index >= 32) {
1344 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL1,
1345 : (1 << (index - 32)));
1346 0 : } else {
1347 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_MCAST_FIL0,
1348 : (1 << index));
1349 : }
1350 :
1351 0 : return (AH_TRUE);
1352 0 : }
1353 :
1354 : HAL_BOOL
1355 0 : ar5k_ar5211_clear_mcast_filter_idx(struct ath_hal *hal, u_int32_t index)
1356 : {
1357 :
1358 0 : if (index >= 64) {
1359 0 : return (AH_FALSE);
1360 0 : } else if (index >= 32) {
1361 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL1,
1362 : (1 << (index - 32)));
1363 0 : } else {
1364 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_MCAST_FIL0,
1365 : (1 << index));
1366 : }
1367 :
1368 0 : return (AH_TRUE);
1369 0 : }
1370 :
1371 : u_int32_t
1372 0 : ar5k_ar5211_get_rx_filter(struct ath_hal *hal)
1373 : {
1374 0 : return (AR5K_REG_READ(AR5K_AR5211_RX_FILTER));
1375 : }
1376 :
1377 : void
1378 0 : ar5k_ar5211_set_rx_filter(struct ath_hal *hal, u_int32_t filter)
1379 : {
1380 0 : AR5K_REG_WRITE(AR5K_AR5211_RX_FILTER, filter);
1381 0 : }
1382 :
1383 : HAL_BOOL
1384 0 : ar5k_ar5211_setup_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
1385 : u_int32_t size, u_int flags)
1386 : {
1387 : struct ar5k_ar5211_rx_desc *rx_desc;
1388 :
1389 0 : rx_desc = (struct ar5k_ar5211_rx_desc*)&desc->ds_ctl0;
1390 :
1391 0 : if ((rx_desc->rx_control_1 = (size &
1392 0 : AR5K_AR5211_DESC_RX_CTL1_BUF_LEN)) != size)
1393 0 : return (AH_FALSE);
1394 :
1395 0 : if (flags & HAL_RXDESC_INTREQ)
1396 0 : rx_desc->rx_control_1 |= AR5K_AR5211_DESC_RX_CTL1_INTREQ;
1397 :
1398 0 : return (AH_TRUE);
1399 0 : }
1400 :
1401 : HAL_STATUS
1402 0 : ar5k_ar5211_proc_rx_desc(struct ath_hal *hal, struct ath_desc *desc,
1403 : u_int32_t phys_addr, struct ath_desc *next)
1404 : {
1405 : struct ar5k_ar5211_rx_status *rx_status;
1406 :
1407 0 : rx_status = (struct ar5k_ar5211_rx_status*)&desc->ds_hw[0];
1408 :
1409 : /* No frame received / not ready */
1410 0 : if ((rx_status->rx_status_1 & AR5K_AR5211_DESC_RX_STATUS1_DONE) == 0)
1411 0 : return (HAL_EINPROGRESS);
1412 :
1413 : /*
1414 : * Frame receive status
1415 : */
1416 0 : desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
1417 : AR5K_AR5211_DESC_RX_STATUS0_DATA_LEN;
1418 0 : desc->ds_us.rx.rs_rssi =
1419 0 : AR5K_REG_MS(rx_status->rx_status_0,
1420 : AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_SIGNAL);
1421 0 : desc->ds_us.rx.rs_rate =
1422 0 : AR5K_REG_MS(rx_status->rx_status_0,
1423 : AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_RATE);
1424 0 : desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
1425 : AR5K_AR5211_DESC_RX_STATUS0_RECEIVE_ANTENNA;
1426 0 : desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
1427 : AR5K_AR5211_DESC_RX_STATUS0_MORE;
1428 0 : desc->ds_us.rx.rs_tstamp =
1429 0 : AR5K_REG_MS(rx_status->rx_status_1,
1430 : AR5K_AR5211_DESC_RX_STATUS1_RECEIVE_TIMESTAMP);
1431 0 : desc->ds_us.rx.rs_status = 0;
1432 :
1433 : /*
1434 : * Key table status
1435 : */
1436 0 : if (rx_status->rx_status_1 &
1437 : AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX_VALID) {
1438 0 : desc->ds_us.rx.rs_keyix =
1439 0 : AR5K_REG_MS(rx_status->rx_status_1,
1440 : AR5K_AR5211_DESC_RX_STATUS1_KEY_INDEX);
1441 0 : } else {
1442 0 : desc->ds_us.rx.rs_keyix = HAL_RXKEYIX_INVALID;
1443 : }
1444 :
1445 : /*
1446 : * Receive/descriptor errors
1447 : */
1448 0 : if ((rx_status->rx_status_1 &
1449 0 : AR5K_AR5211_DESC_RX_STATUS1_FRAME_RECEIVE_OK) == 0) {
1450 0 : if (rx_status->rx_status_1 &
1451 : AR5K_AR5211_DESC_RX_STATUS1_CRC_ERROR)
1452 0 : desc->ds_us.rx.rs_status |= HAL_RXERR_CRC;
1453 :
1454 0 : if (rx_status->rx_status_1 &
1455 : AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR) {
1456 0 : desc->ds_us.rx.rs_status |= HAL_RXERR_PHY;
1457 0 : desc->ds_us.rx.rs_phyerr =
1458 0 : AR5K_REG_MS(rx_status->rx_status_1,
1459 : AR5K_AR5211_DESC_RX_STATUS1_PHY_ERROR);
1460 0 : }
1461 :
1462 0 : if (rx_status->rx_status_1 &
1463 : AR5K_AR5211_DESC_RX_STATUS1_DECRYPT_CRC_ERROR)
1464 0 : desc->ds_us.rx.rs_status |= HAL_RXERR_DECRYPT;
1465 : }
1466 :
1467 0 : return (HAL_OK);
1468 0 : }
1469 :
1470 : void
1471 0 : ar5k_ar5211_set_rx_signal(struct ath_hal *hal)
1472 : {
1473 : /* Signal state monitoring is not yet supported */
1474 0 : }
1475 :
1476 : /*
1477 : * Misc functions
1478 : */
1479 :
1480 : void
1481 0 : ar5k_ar5211_dump_state(struct ath_hal *hal)
1482 : {
1483 : #ifdef AR5K_DEBUG
1484 : #define AR5K_PRINT_REGISTER(_x) \
1485 : printf("(%s: %08x) ", #_x, AR5K_REG_READ(AR5K_AR5211_##_x));
1486 :
1487 : printf("MAC registers:\n");
1488 : AR5K_PRINT_REGISTER(CR);
1489 : AR5K_PRINT_REGISTER(CFG);
1490 : AR5K_PRINT_REGISTER(IER);
1491 : AR5K_PRINT_REGISTER(RTSD0);
1492 : AR5K_PRINT_REGISTER(TXCFG);
1493 : AR5K_PRINT_REGISTER(RXCFG);
1494 : AR5K_PRINT_REGISTER(RXJLA);
1495 : AR5K_PRINT_REGISTER(MIBC);
1496 : AR5K_PRINT_REGISTER(TOPS);
1497 : AR5K_PRINT_REGISTER(RXNOFRM);
1498 : AR5K_PRINT_REGISTER(RPGTO);
1499 : AR5K_PRINT_REGISTER(RFCNT);
1500 : AR5K_PRINT_REGISTER(MISC);
1501 : AR5K_PRINT_REGISTER(PISR);
1502 : AR5K_PRINT_REGISTER(SISR0);
1503 : AR5K_PRINT_REGISTER(SISR1);
1504 : AR5K_PRINT_REGISTER(SISR3);
1505 : AR5K_PRINT_REGISTER(SISR4);
1506 : AR5K_PRINT_REGISTER(QCU_TXE);
1507 : AR5K_PRINT_REGISTER(QCU_TXD);
1508 : AR5K_PRINT_REGISTER(DCU_GBL_IFS_SIFS);
1509 : AR5K_PRINT_REGISTER(DCU_GBL_IFS_SLOT);
1510 : AR5K_PRINT_REGISTER(DCU_FP);
1511 : AR5K_PRINT_REGISTER(DCU_TXP);
1512 : AR5K_PRINT_REGISTER(DCU_TX_FILTER);
1513 : AR5K_PRINT_REGISTER(RC);
1514 : AR5K_PRINT_REGISTER(SCR);
1515 : AR5K_PRINT_REGISTER(INTPEND);
1516 : AR5K_PRINT_REGISTER(PCICFG);
1517 : AR5K_PRINT_REGISTER(GPIOCR);
1518 : AR5K_PRINT_REGISTER(GPIODO);
1519 : AR5K_PRINT_REGISTER(SREV);
1520 : AR5K_PRINT_REGISTER(EEPROM_BASE);
1521 : AR5K_PRINT_REGISTER(EEPROM_DATA);
1522 : AR5K_PRINT_REGISTER(EEPROM_CMD);
1523 : AR5K_PRINT_REGISTER(EEPROM_CFG);
1524 : AR5K_PRINT_REGISTER(PCU_MIN);
1525 : AR5K_PRINT_REGISTER(STA_ID0);
1526 : AR5K_PRINT_REGISTER(STA_ID1);
1527 : AR5K_PRINT_REGISTER(BSS_ID0);
1528 : AR5K_PRINT_REGISTER(SLOT_TIME);
1529 : AR5K_PRINT_REGISTER(TIME_OUT);
1530 : AR5K_PRINT_REGISTER(RSSI_THR);
1531 : AR5K_PRINT_REGISTER(BEACON);
1532 : AR5K_PRINT_REGISTER(CFP_PERIOD);
1533 : AR5K_PRINT_REGISTER(TIMER0);
1534 : AR5K_PRINT_REGISTER(TIMER2);
1535 : AR5K_PRINT_REGISTER(TIMER3);
1536 : AR5K_PRINT_REGISTER(CFP_DUR);
1537 : AR5K_PRINT_REGISTER(MCAST_FIL0);
1538 : AR5K_PRINT_REGISTER(MCAST_FIL1);
1539 : AR5K_PRINT_REGISTER(DIAG_SW);
1540 : AR5K_PRINT_REGISTER(TSF_U32);
1541 : AR5K_PRINT_REGISTER(ADDAC_TEST);
1542 : AR5K_PRINT_REGISTER(DEFAULT_ANTENNA);
1543 : AR5K_PRINT_REGISTER(LAST_TSTP);
1544 : AR5K_PRINT_REGISTER(NAV);
1545 : AR5K_PRINT_REGISTER(RTS_OK);
1546 : AR5K_PRINT_REGISTER(ACK_FAIL);
1547 : AR5K_PRINT_REGISTER(FCS_FAIL);
1548 : AR5K_PRINT_REGISTER(BEACON_CNT);
1549 : AR5K_PRINT_REGISTER(KEYTABLE_0);
1550 : printf("\n");
1551 :
1552 : printf("PHY registers:\n");
1553 : AR5K_PRINT_REGISTER(PHY_TURBO);
1554 : AR5K_PRINT_REGISTER(PHY_AGC);
1555 : AR5K_PRINT_REGISTER(PHY_CHIP_ID);
1556 : AR5K_PRINT_REGISTER(PHY_AGCCTL);
1557 : AR5K_PRINT_REGISTER(PHY_NF);
1558 : AR5K_PRINT_REGISTER(PHY_RX_DELAY);
1559 : AR5K_PRINT_REGISTER(PHY_IQ);
1560 : AR5K_PRINT_REGISTER(PHY_PAPD_PROBE);
1561 : AR5K_PRINT_REGISTER(PHY_FC);
1562 : AR5K_PRINT_REGISTER(PHY_RADAR);
1563 : AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_0);
1564 : AR5K_PRINT_REGISTER(PHY_ANT_SWITCH_TABLE_1);
1565 : printf("\n");
1566 : #endif
1567 0 : }
1568 :
1569 : HAL_BOOL
1570 0 : ar5k_ar5211_get_diag_state(struct ath_hal *hal, int id, void **device,
1571 : u_int *size)
1572 : {
1573 : /*
1574 : * We'll ignore this right now. This seems to be some kind of an obscure
1575 : * debugging interface for the binary-only HAL.
1576 : */
1577 0 : return (AH_FALSE);
1578 : }
1579 :
1580 : void
1581 0 : ar5k_ar5211_get_lladdr(struct ath_hal *hal, u_int8_t *mac)
1582 : {
1583 0 : bcopy(hal->ah_sta_id, mac, IEEE80211_ADDR_LEN);
1584 0 : }
1585 :
1586 : HAL_BOOL
1587 0 : ar5k_ar5211_set_lladdr(struct ath_hal *hal, const u_int8_t *mac)
1588 : {
1589 : u_int32_t low_id, high_id;
1590 :
1591 : /* Set new station ID */
1592 0 : bcopy(mac, hal->ah_sta_id, IEEE80211_ADDR_LEN);
1593 :
1594 0 : low_id = AR5K_LOW_ID(mac);
1595 0 : high_id = 0x0000ffff & AR5K_HIGH_ID(mac);
1596 :
1597 0 : AR5K_REG_WRITE(AR5K_AR5211_STA_ID0, low_id);
1598 0 : AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, high_id);
1599 :
1600 0 : return (AH_TRUE);
1601 : }
1602 :
1603 : HAL_BOOL
1604 0 : ar5k_ar5211_set_regdomain(struct ath_hal *hal, u_int16_t regdomain,
1605 : HAL_STATUS *status)
1606 : {
1607 0 : ieee80211_regdomain_t ieee_regdomain;
1608 :
1609 0 : ieee_regdomain = ar5k_regdomain_to_ieee(regdomain);
1610 :
1611 0 : if (ar5k_eeprom_regulation_domain(hal, AH_TRUE,
1612 0 : &ieee_regdomain) == AH_TRUE) {
1613 0 : *status = HAL_OK;
1614 0 : return (AH_TRUE);
1615 : }
1616 :
1617 0 : *status = EIO;
1618 :
1619 0 : return (AH_FALSE);
1620 0 : }
1621 :
1622 : void
1623 0 : ar5k_ar5211_set_ledstate(struct ath_hal *hal, HAL_LED_STATE state)
1624 : {
1625 : u_int32_t led;
1626 :
1627 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_PCICFG,
1628 : AR5K_AR5211_PCICFG_LEDMODE | AR5K_AR5211_PCICFG_LED);
1629 :
1630 : /*
1631 : * Some blinking values, define at your wish
1632 : */
1633 0 : switch (state) {
1634 : case IEEE80211_S_SCAN:
1635 : case IEEE80211_S_AUTH:
1636 : led = AR5K_AR5211_PCICFG_LEDMODE_PROP |
1637 : AR5K_AR5211_PCICFG_LED_PEND;
1638 0 : break;
1639 :
1640 : case IEEE80211_S_INIT:
1641 : led = AR5K_AR5211_PCICFG_LEDMODE_PROP |
1642 : AR5K_AR5211_PCICFG_LED_NONE;
1643 0 : break;
1644 :
1645 : case IEEE80211_S_ASSOC:
1646 : case IEEE80211_S_RUN:
1647 : led = AR5K_AR5211_PCICFG_LEDMODE_PROP |
1648 : AR5K_AR5211_PCICFG_LED_ASSOC;
1649 0 : break;
1650 :
1651 : default:
1652 : led = AR5K_AR5211_PCICFG_LEDMODE_PROM |
1653 : AR5K_AR5211_PCICFG_LED_NONE;
1654 0 : break;
1655 : }
1656 :
1657 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PCICFG, led);
1658 0 : }
1659 :
1660 : void
1661 0 : ar5k_ar5211_set_associd(struct ath_hal *hal, const u_int8_t *bssid,
1662 : u_int16_t assoc_id, u_int16_t tim_offset)
1663 : {
1664 : u_int32_t low_id, high_id;
1665 :
1666 : /*
1667 : * Set BSSID which triggers the "SME Join" operation
1668 : */
1669 0 : low_id = AR5K_LOW_ID(bssid);
1670 0 : high_id = AR5K_HIGH_ID(bssid);
1671 0 : AR5K_REG_WRITE(AR5K_AR5211_BSS_ID0, low_id);
1672 0 : AR5K_REG_WRITE(AR5K_AR5211_BSS_ID1, high_id |
1673 : ((assoc_id & 0x3fff) << AR5K_AR5211_BSS_ID1_AID_S));
1674 0 : bcopy(bssid, hal->ah_bssid, IEEE80211_ADDR_LEN);
1675 :
1676 0 : if (assoc_id == 0) {
1677 0 : ar5k_ar5211_disable_pspoll(hal);
1678 0 : return;
1679 : }
1680 :
1681 0 : AR5K_REG_WRITE(AR5K_AR5211_BEACON,
1682 : (AR5K_REG_READ(AR5K_AR5211_BEACON) &
1683 : ~AR5K_AR5211_BEACON_TIM) |
1684 : (((tim_offset ? tim_offset + 4 : 0) <<
1685 : AR5K_AR5211_BEACON_TIM_S) &
1686 : AR5K_AR5211_BEACON_TIM));
1687 :
1688 0 : ar5k_ar5211_enable_pspoll(hal, NULL, 0);
1689 0 : }
1690 :
1691 : HAL_BOOL
1692 0 : ar5k_ar5211_set_bssid_mask(struct ath_hal *hal, const u_int8_t* mask)
1693 : {
1694 : /* Not supported in 5211 */
1695 0 : return (AH_FALSE);
1696 : }
1697 :
1698 : HAL_BOOL
1699 0 : ar5k_ar5211_set_gpio_output(struct ath_hal *hal, u_int32_t gpio)
1700 : {
1701 0 : if (gpio > AR5K_AR5211_NUM_GPIO)
1702 0 : return (AH_FALSE);
1703 :
1704 0 : AR5K_REG_WRITE(AR5K_AR5211_GPIOCR,
1705 : (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio))
1706 : | AR5K_AR5211_GPIOCR_ALL(gpio));
1707 :
1708 0 : return (AH_TRUE);
1709 0 : }
1710 :
1711 : HAL_BOOL
1712 0 : ar5k_ar5211_set_gpio_input(struct ath_hal *hal, u_int32_t gpio)
1713 : {
1714 0 : if (gpio > AR5K_AR5211_NUM_GPIO)
1715 0 : return (AH_FALSE);
1716 :
1717 0 : AR5K_REG_WRITE(AR5K_AR5211_GPIOCR,
1718 : (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &~ AR5K_AR5211_GPIOCR_ALL(gpio))
1719 : | AR5K_AR5211_GPIOCR_NONE(gpio));
1720 :
1721 0 : return (AH_TRUE);
1722 0 : }
1723 :
1724 : u_int32_t
1725 0 : ar5k_ar5211_get_gpio(struct ath_hal *hal, u_int32_t gpio)
1726 : {
1727 0 : if (gpio > AR5K_AR5211_NUM_GPIO)
1728 0 : return (0xffffffff);
1729 :
1730 : /* GPIO input magic */
1731 0 : return (((AR5K_REG_READ(AR5K_AR5211_GPIODI) &
1732 0 : AR5K_AR5211_GPIODI_M) >> gpio) & 0x1);
1733 0 : }
1734 :
1735 : HAL_BOOL
1736 0 : ar5k_ar5211_set_gpio(struct ath_hal *hal, u_int32_t gpio, u_int32_t val)
1737 : {
1738 : u_int32_t data;
1739 :
1740 0 : if (gpio > AR5K_AR5211_NUM_GPIO)
1741 0 : return (0xffffffff);
1742 :
1743 : /* GPIO output magic */
1744 0 : data = AR5K_REG_READ(AR5K_AR5211_GPIODO);
1745 :
1746 0 : data &= ~(1 << gpio);
1747 0 : data |= (val&1) << gpio;
1748 :
1749 0 : AR5K_REG_WRITE(AR5K_AR5211_GPIODO, data);
1750 :
1751 0 : return (AH_TRUE);
1752 0 : }
1753 :
1754 : void
1755 0 : ar5k_ar5211_set_gpio_intr(struct ath_hal *hal, u_int gpio,
1756 : u_int32_t interrupt_level)
1757 : {
1758 : u_int32_t data;
1759 :
1760 0 : if (gpio > AR5K_AR5211_NUM_GPIO)
1761 0 : return;
1762 :
1763 : /*
1764 : * Set the GPIO interrupt
1765 : */
1766 0 : data = (AR5K_REG_READ(AR5K_AR5211_GPIOCR) &
1767 0 : ~(AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_SELH |
1768 0 : AR5K_AR5211_GPIOCR_INT_ENA | AR5K_AR5211_GPIOCR_ALL(gpio))) |
1769 0 : (AR5K_AR5211_GPIOCR_INT_SEL(gpio) | AR5K_AR5211_GPIOCR_INT_ENA);
1770 :
1771 0 : AR5K_REG_WRITE(AR5K_AR5211_GPIOCR,
1772 : interrupt_level ? data : (data | AR5K_AR5211_GPIOCR_INT_SELH));
1773 :
1774 0 : hal->ah_imr |= AR5K_AR5211_PIMR_GPIO;
1775 :
1776 : /* Enable GPIO interrupts */
1777 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR, AR5K_AR5211_PIMR_GPIO);
1778 0 : }
1779 :
1780 : u_int32_t
1781 0 : ar5k_ar5211_get_tsf32(struct ath_hal *hal)
1782 : {
1783 0 : return (AR5K_REG_READ(AR5K_AR5211_TSF_L32));
1784 : }
1785 :
1786 : u_int64_t
1787 0 : ar5k_ar5211_get_tsf64(struct ath_hal *hal)
1788 : {
1789 0 : u_int64_t tsf = AR5K_REG_READ(AR5K_AR5211_TSF_U32);
1790 :
1791 0 : return (AR5K_REG_READ(AR5K_AR5211_TSF_L32) | (tsf << 32));
1792 : }
1793 :
1794 : void
1795 0 : ar5k_ar5211_reset_tsf(struct ath_hal *hal)
1796 : {
1797 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_BEACON,
1798 : AR5K_AR5211_BEACON_RESET_TSF);
1799 0 : }
1800 :
1801 : u_int16_t
1802 0 : ar5k_ar5211_get_regdomain(struct ath_hal *hal)
1803 : {
1804 0 : return (ar5k_get_regdomain(hal));
1805 : }
1806 :
1807 : HAL_BOOL
1808 0 : ar5k_ar5211_detect_card_present(struct ath_hal *hal)
1809 : {
1810 0 : u_int16_t magic;
1811 :
1812 : /*
1813 : * Checking the EEPROM's magic value could be an indication
1814 : * if the card is still present. I didn't find another suitable
1815 : * way to do this.
1816 : */
1817 0 : if (ar5k_ar5211_eeprom_read(hal, AR5K_EEPROM_MAGIC, &magic) != 0)
1818 0 : return (AH_FALSE);
1819 :
1820 0 : return (magic == AR5K_EEPROM_MAGIC_VALUE ? AH_TRUE : AH_FALSE);
1821 0 : }
1822 :
1823 : void
1824 0 : ar5k_ar5211_update_mib_counters(struct ath_hal *hal, HAL_MIB_STATS *statistics)
1825 : {
1826 0 : statistics->ackrcv_bad += AR5K_REG_READ(AR5K_AR5211_ACK_FAIL);
1827 0 : statistics->rts_bad += AR5K_REG_READ(AR5K_AR5211_RTS_FAIL);
1828 0 : statistics->rts_good += AR5K_REG_READ(AR5K_AR5211_RTS_OK);
1829 0 : statistics->fcs_bad += AR5K_REG_READ(AR5K_AR5211_FCS_FAIL);
1830 0 : statistics->beacons += AR5K_REG_READ(AR5K_AR5211_BEACON_CNT);
1831 0 : }
1832 :
1833 : HAL_RFGAIN
1834 0 : ar5k_ar5211_get_rf_gain(struct ath_hal *hal)
1835 : {
1836 0 : return (HAL_RFGAIN_INACTIVE);
1837 : }
1838 :
1839 : HAL_BOOL
1840 0 : ar5k_ar5211_set_slot_time(struct ath_hal *hal, u_int slot_time)
1841 : {
1842 0 : if (slot_time < HAL_SLOT_TIME_9 || slot_time > HAL_SLOT_TIME_MAX)
1843 0 : return (AH_FALSE);
1844 :
1845 0 : AR5K_REG_WRITE(AR5K_AR5211_DCU_GBL_IFS_SLOT, slot_time);
1846 :
1847 0 : return (AH_TRUE);
1848 0 : }
1849 :
1850 : u_int
1851 0 : ar5k_ar5211_get_slot_time(struct ath_hal *hal)
1852 : {
1853 0 : return (AR5K_REG_READ(AR5K_AR5211_DCU_GBL_IFS_SLOT) & 0xffff);
1854 : }
1855 :
1856 : HAL_BOOL
1857 0 : ar5k_ar5211_set_ack_timeout(struct ath_hal *hal, u_int timeout)
1858 : {
1859 0 : if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_ACK))
1860 0 : <= timeout)
1861 0 : return (AH_FALSE);
1862 :
1863 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_ACK,
1864 : ar5k_htoclock(timeout));
1865 :
1866 0 : return (AH_TRUE);
1867 0 : }
1868 :
1869 : u_int
1870 0 : ar5k_ar5211_get_ack_timeout(struct ath_hal *hal)
1871 : {
1872 0 : return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT),
1873 : AR5K_AR5211_TIME_OUT_ACK)));
1874 : }
1875 :
1876 : HAL_BOOL
1877 0 : ar5k_ar5211_set_cts_timeout(struct ath_hal *hal, u_int timeout)
1878 : {
1879 0 : if (ar5k_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_AR5211_TIME_OUT_CTS))
1880 0 : <= timeout)
1881 0 : return (AH_FALSE);
1882 :
1883 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_TIME_OUT, AR5K_AR5211_TIME_OUT_CTS,
1884 : ar5k_htoclock(timeout));
1885 :
1886 0 : return (AH_TRUE);
1887 0 : }
1888 :
1889 : u_int
1890 0 : ar5k_ar5211_get_cts_timeout(struct ath_hal *hal)
1891 : {
1892 0 : return (ar5k_clocktoh(AR5K_REG_MS(AR5K_REG_READ(AR5K_AR5211_TIME_OUT),
1893 : AR5K_AR5211_TIME_OUT_CTS)));
1894 : }
1895 :
1896 : /*
1897 : * Key table (WEP) functions
1898 : */
1899 :
1900 : HAL_BOOL
1901 0 : ar5k_ar5211_is_cipher_supported(struct ath_hal *hal, HAL_CIPHER cipher)
1902 : {
1903 : /*
1904 : * The AR5211 only supports WEP
1905 : */
1906 0 : if (cipher == HAL_CIPHER_WEP)
1907 0 : return (AH_TRUE);
1908 :
1909 0 : return (AH_FALSE);
1910 0 : }
1911 :
1912 : u_int32_t
1913 0 : ar5k_ar5211_get_keycache_size(struct ath_hal *hal)
1914 : {
1915 0 : return (AR5K_AR5211_KEYCACHE_SIZE);
1916 : }
1917 :
1918 : HAL_BOOL
1919 0 : ar5k_ar5211_reset_key(struct ath_hal *hal, u_int16_t entry)
1920 : {
1921 : int i;
1922 :
1923 0 : AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE);
1924 :
1925 0 : for (i = 0; i < AR5K_AR5211_KEYCACHE_SIZE; i++)
1926 0 : AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), 0);
1927 :
1928 : /* Set NULL encryption */
1929 0 : AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_TYPE(entry),
1930 : AR5K_AR5211_KEYTABLE_TYPE_NULL);
1931 :
1932 0 : return (AH_FALSE);
1933 0 : }
1934 :
1935 : HAL_BOOL
1936 0 : ar5k_ar5211_is_key_valid(struct ath_hal *hal, u_int16_t entry)
1937 : {
1938 0 : AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE);
1939 :
1940 : /*
1941 : * Check the validation flag at the end of the entry
1942 : */
1943 0 : if (AR5K_REG_READ(AR5K_AR5211_KEYTABLE_MAC1(entry)) &
1944 : AR5K_AR5211_KEYTABLE_VALID)
1945 0 : return (AH_TRUE);
1946 :
1947 0 : return (AH_FALSE);
1948 0 : }
1949 :
1950 : HAL_BOOL
1951 0 : ar5k_ar5211_set_key(struct ath_hal *hal, u_int16_t entry,
1952 : const HAL_KEYVAL *keyval, const u_int8_t *mac, int xor_notused)
1953 : {
1954 : int i;
1955 0 : u_int32_t key_v[AR5K_AR5211_KEYCACHE_SIZE - 2];
1956 :
1957 0 : AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE);
1958 :
1959 0 : bzero(&key_v, sizeof(key_v));
1960 :
1961 0 : switch (keyval->wk_len) {
1962 : case AR5K_KEYVAL_LENGTH_40:
1963 0 : bcopy(keyval->wk_key, &key_v[0], 4);
1964 0 : bcopy(keyval->wk_key + 4, &key_v[1], 1);
1965 0 : key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_40;
1966 0 : break;
1967 :
1968 : case AR5K_KEYVAL_LENGTH_104:
1969 0 : bcopy(keyval->wk_key, &key_v[0], 4);
1970 0 : bcopy(keyval->wk_key + 4, &key_v[1], 2);
1971 0 : bcopy(keyval->wk_key + 6, &key_v[2], 4);
1972 0 : bcopy(keyval->wk_key + 10, &key_v[3], 2);
1973 0 : bcopy(keyval->wk_key + 12, &key_v[4], 1);
1974 0 : key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_104;
1975 0 : break;
1976 :
1977 : case AR5K_KEYVAL_LENGTH_128:
1978 0 : bcopy(keyval->wk_key, &key_v[0], 4);
1979 0 : bcopy(keyval->wk_key + 4, &key_v[1], 2);
1980 0 : bcopy(keyval->wk_key + 6, &key_v[2], 4);
1981 0 : bcopy(keyval->wk_key + 10, &key_v[3], 2);
1982 0 : bcopy(keyval->wk_key + 12, &key_v[4], 4);
1983 0 : key_v[5] = AR5K_AR5211_KEYTABLE_TYPE_128;
1984 0 : break;
1985 :
1986 : default:
1987 : /* Unsupported key length (not WEP40/104/128) */
1988 0 : return (AH_FALSE);
1989 : }
1990 :
1991 0 : for (i = 0; i < nitems(key_v); i++)
1992 0 : AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_OFF(entry, i), key_v[i]);
1993 :
1994 0 : return (ar5k_ar5211_set_key_lladdr(hal, entry, mac));
1995 0 : }
1996 :
1997 : HAL_BOOL
1998 0 : ar5k_ar5211_set_key_lladdr(struct ath_hal *hal, u_int16_t entry,
1999 : const u_int8_t *mac)
2000 : {
2001 : u_int32_t low_id, high_id;
2002 : const u_int8_t *mac_v;
2003 :
2004 : /*
2005 : * Invalid entry (key table overflow)
2006 : */
2007 0 : AR5K_ASSERT_ENTRY(entry, AR5K_AR5211_KEYTABLE_SIZE);
2008 :
2009 : /* MAC may be NULL if it's a broadcast key */
2010 0 : mac_v = mac == NULL ? etherbroadcastaddr : mac;
2011 :
2012 0 : low_id = AR5K_LOW_ID(mac_v);
2013 0 : high_id = AR5K_HIGH_ID(mac_v) | AR5K_AR5211_KEYTABLE_VALID;
2014 :
2015 0 : AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC0(entry), low_id);
2016 0 : AR5K_REG_WRITE(AR5K_AR5211_KEYTABLE_MAC1(entry), high_id);
2017 :
2018 0 : return (AH_TRUE);
2019 0 : }
2020 :
2021 : HAL_BOOL
2022 0 : ar5k_ar5211_softcrypto(struct ath_hal *hal, HAL_BOOL enable)
2023 : {
2024 : u_int32_t bits;
2025 : int i;
2026 :
2027 : bits = AR5K_AR5211_DIAG_SW_DIS_ENC | AR5K_AR5211_DIAG_SW_DIS_DEC;
2028 0 : if (enable == AH_TRUE) {
2029 : /* Disable the hardware crypto engine */
2030 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_DIAG_SW, bits);
2031 0 : } else {
2032 : /* Enable the hardware crypto engine */
2033 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_DIAG_SW, bits);
2034 : }
2035 :
2036 : /* Reset the key cache */
2037 0 : for (i = 0; i < AR5K_AR5211_KEYTABLE_SIZE; i++)
2038 0 : ar5k_ar5211_reset_key(hal, i);
2039 :
2040 0 : return (AH_TRUE);
2041 : }
2042 :
2043 : /*
2044 : * Power management functions
2045 : */
2046 :
2047 : HAL_BOOL
2048 0 : ar5k_ar5211_set_power(struct ath_hal *hal, HAL_POWER_MODE mode,
2049 : HAL_BOOL set_chip, u_int16_t sleep_duration)
2050 : {
2051 : u_int32_t staid;
2052 : int i;
2053 :
2054 0 : staid = AR5K_REG_READ(AR5K_AR5211_STA_ID1);
2055 :
2056 0 : switch (mode) {
2057 : case HAL_PM_AUTO:
2058 0 : staid &= ~AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA;
2059 : /* FALLTHROUGH */
2060 : case HAL_PM_NETWORK_SLEEP:
2061 0 : if (set_chip == AH_TRUE) {
2062 0 : AR5K_REG_WRITE(AR5K_AR5211_SCR,
2063 : AR5K_AR5211_SCR_SLE | sleep_duration);
2064 0 : }
2065 0 : staid |= AR5K_AR5211_STA_ID1_PWR_SV;
2066 0 : break;
2067 :
2068 : case HAL_PM_FULL_SLEEP:
2069 0 : if (set_chip == AH_TRUE) {
2070 0 : AR5K_REG_WRITE(AR5K_AR5211_SCR,
2071 : AR5K_AR5211_SCR_SLE_SLP);
2072 0 : }
2073 0 : staid |= AR5K_AR5211_STA_ID1_PWR_SV;
2074 0 : break;
2075 :
2076 : case HAL_PM_AWAKE:
2077 0 : if (set_chip == AH_FALSE)
2078 : goto commit;
2079 :
2080 0 : AR5K_REG_WRITE(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLE_WAKE);
2081 :
2082 0 : for (i = 5000; i > 0; i--) {
2083 : /* Check if the AR5211 did wake up */
2084 0 : if ((AR5K_REG_READ(AR5K_AR5211_PCICFG) &
2085 0 : AR5K_AR5211_PCICFG_SPWR_DN) == 0)
2086 : break;
2087 :
2088 : /* Wait a bit and retry */
2089 0 : AR5K_DELAY(200);
2090 0 : AR5K_REG_WRITE(AR5K_AR5211_SCR,
2091 : AR5K_AR5211_SCR_SLE_WAKE);
2092 : }
2093 :
2094 : /* Fail if the AR5211 didn't wake up */
2095 0 : if (i <= 0)
2096 0 : return (AH_FALSE);
2097 :
2098 0 : staid &= ~AR5K_AR5211_STA_ID1_PWR_SV;
2099 0 : break;
2100 :
2101 : default:
2102 0 : return (AH_FALSE);
2103 : }
2104 :
2105 : commit:
2106 0 : hal->ah_power_mode = mode;
2107 :
2108 0 : AR5K_REG_WRITE(AR5K_AR5211_STA_ID1, staid);
2109 :
2110 0 : return (AH_TRUE);
2111 0 : }
2112 :
2113 : HAL_POWER_MODE
2114 0 : ar5k_ar5211_get_power_mode(struct ath_hal *hal)
2115 : {
2116 0 : return (hal->ah_power_mode);
2117 : }
2118 :
2119 : HAL_BOOL
2120 0 : ar5k_ar5211_query_pspoll_support(struct ath_hal *hal)
2121 : {
2122 : /* nope */
2123 0 : return (AH_FALSE);
2124 : }
2125 :
2126 : HAL_BOOL
2127 0 : ar5k_ar5211_init_pspoll(struct ath_hal *hal)
2128 : {
2129 : /*
2130 : * Not used on the AR5211
2131 : */
2132 0 : return (AH_FALSE);
2133 : }
2134 :
2135 : HAL_BOOL
2136 0 : ar5k_ar5211_enable_pspoll(struct ath_hal *hal, u_int8_t *bssid,
2137 : u_int16_t assoc_id)
2138 : {
2139 0 : return (AH_FALSE);
2140 : }
2141 :
2142 : HAL_BOOL
2143 0 : ar5k_ar5211_disable_pspoll(struct ath_hal *hal)
2144 : {
2145 0 : return (AH_FALSE);
2146 : }
2147 :
2148 : /*
2149 : * Beacon functions
2150 : */
2151 :
2152 : void
2153 0 : ar5k_ar5211_init_beacon(struct ath_hal *hal, u_int32_t next_beacon,
2154 : u_int32_t interval)
2155 : {
2156 : u_int32_t timer1, timer2, timer3;
2157 :
2158 : /*
2159 : * Set the additional timers by mode
2160 : */
2161 0 : switch (hal->ah_op_mode) {
2162 : case HAL_M_STA:
2163 : timer1 = 0x0000ffff;
2164 : timer2 = 0x0007ffff;
2165 0 : break;
2166 :
2167 : default:
2168 0 : timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) <<
2169 : 0x00000003;
2170 0 : timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) <<
2171 : 0x00000003;
2172 0 : }
2173 :
2174 0 : timer3 = next_beacon +
2175 0 : (hal->ah_atim_window ? hal->ah_atim_window : 1);
2176 :
2177 : /*
2178 : * Enable all timers and set the beacon register
2179 : * (next beacon, DMA beacon, software beacon, ATIM window time)
2180 : */
2181 0 : AR5K_REG_WRITE(AR5K_AR5211_TIMER0, next_beacon);
2182 0 : AR5K_REG_WRITE(AR5K_AR5211_TIMER1, timer1);
2183 0 : AR5K_REG_WRITE(AR5K_AR5211_TIMER2, timer2);
2184 0 : AR5K_REG_WRITE(AR5K_AR5211_TIMER3, timer3);
2185 :
2186 0 : AR5K_REG_WRITE(AR5K_AR5211_BEACON, interval &
2187 : (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_RESET_TSF |
2188 : AR5K_AR5211_BEACON_ENABLE));
2189 0 : }
2190 :
2191 : void
2192 0 : ar5k_ar5211_set_beacon_timers(struct ath_hal *hal,
2193 : const HAL_BEACON_STATE *state, u_int32_t tsf, u_int32_t dtim_count,
2194 : u_int32_t cfp_count)
2195 : {
2196 : u_int32_t cfp_period, next_cfp;
2197 :
2198 : /* Return on an invalid beacon state */
2199 0 : if (state->bs_interval < 1)
2200 0 : return;
2201 :
2202 : /*
2203 : * PCF support?
2204 : */
2205 0 : if (state->bs_cfp_period > 0) {
2206 : /* Enable CFP mode and set the CFP and timer registers */
2207 0 : cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2208 : state->bs_interval;
2209 0 : next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2210 : state->bs_interval;
2211 :
2212 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1,
2213 : AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA |
2214 : AR5K_AR5211_STA_ID1_PCF);
2215 0 : AR5K_REG_WRITE(AR5K_AR5211_CFP_PERIOD, cfp_period);
2216 0 : AR5K_REG_WRITE(AR5K_AR5211_CFP_DUR, state->bs_cfp_max_duration);
2217 0 : AR5K_REG_WRITE(AR5K_AR5211_TIMER2,
2218 : (tsf + (next_cfp == 0 ? cfp_period : next_cfp)) << 3);
2219 0 : } else {
2220 : /* Disable PCF mode */
2221 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1,
2222 : AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA |
2223 : AR5K_AR5211_STA_ID1_PCF);
2224 : }
2225 :
2226 : /*
2227 : * Enable the beacon timer register
2228 : */
2229 0 : AR5K_REG_WRITE(AR5K_AR5211_TIMER0, state->bs_next_beacon);
2230 :
2231 : /*
2232 : * Start the beacon timers
2233 : */
2234 0 : AR5K_REG_WRITE(AR5K_AR5211_BEACON,
2235 : (AR5K_REG_READ(AR5K_AR5211_BEACON) &~
2236 : (AR5K_AR5211_BEACON_PERIOD | AR5K_AR5211_BEACON_TIM)) |
2237 : AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2238 : AR5K_AR5211_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2239 : AR5K_AR5211_BEACON_PERIOD));
2240 :
2241 : /*
2242 : * Write new beacon miss threshold, if it appears to be valid
2243 : */
2244 0 : if ((AR5K_AR5211_RSSI_THR_BMISS >> AR5K_AR5211_RSSI_THR_BMISS_S) <
2245 0 : state->bs_bmiss_threshold)
2246 0 : return;
2247 :
2248 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_RSSI_THR_M,
2249 : AR5K_AR5211_RSSI_THR_BMISS, state->bs_bmiss_threshold);
2250 0 : AR5K_REG_WRITE_BITS(AR5K_AR5211_SCR, AR5K_AR5211_SCR_SLDUR,
2251 : (state->bs_sleepduration - 3) << 3);
2252 0 : }
2253 :
2254 : void
2255 0 : ar5k_ar5211_reset_beacon(struct ath_hal *hal)
2256 : {
2257 : /*
2258 : * Disable beacon timer
2259 : */
2260 0 : AR5K_REG_WRITE(AR5K_AR5211_TIMER0, 0);
2261 :
2262 : /*
2263 : * Disable some beacon register values
2264 : */
2265 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_STA_ID1,
2266 : AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA | AR5K_AR5211_STA_ID1_PCF);
2267 0 : AR5K_REG_WRITE(AR5K_AR5211_BEACON, AR5K_AR5211_BEACON_PERIOD);
2268 0 : }
2269 :
2270 : HAL_BOOL
2271 0 : ar5k_ar5211_wait_for_beacon(struct ath_hal *hal, bus_addr_t phys_addr)
2272 : {
2273 : HAL_BOOL ret;
2274 :
2275 : /*
2276 : * Wait for beaconn queue to be done
2277 : */
2278 0 : ret = ar5k_register_timeout(hal,
2279 : AR5K_AR5211_QCU_STS(HAL_TX_QUEUE_ID_BEACON),
2280 : AR5K_AR5211_QCU_STS_FRMPENDCNT, 0, AH_FALSE);
2281 :
2282 0 : if (AR5K_REG_READ_Q(AR5K_AR5211_QCU_TXE, HAL_TX_QUEUE_ID_BEACON))
2283 0 : return (AH_FALSE);
2284 :
2285 0 : return (ret);
2286 0 : }
2287 :
2288 : /*
2289 : * Interrupt handling
2290 : */
2291 :
2292 : HAL_BOOL
2293 0 : ar5k_ar5211_is_intr_pending(struct ath_hal *hal)
2294 : {
2295 0 : return (AR5K_REG_READ(AR5K_AR5211_INTPEND) == 0 ? AH_FALSE : AH_TRUE);
2296 : }
2297 :
2298 : HAL_BOOL
2299 0 : ar5k_ar5211_get_isr(struct ath_hal *hal, u_int32_t *interrupt_mask)
2300 : {
2301 : u_int32_t data;
2302 :
2303 : /*
2304 : * Read interrupt status from the Read-And-Clear shadow register
2305 : */
2306 0 : data = AR5K_REG_READ(AR5K_AR5211_RAC_PISR);
2307 :
2308 : /*
2309 : * Get abstract interrupt mask (HAL-compatible)
2310 : */
2311 0 : *interrupt_mask = (data & HAL_INT_COMMON) & hal->ah_imr;
2312 :
2313 0 : if (data == HAL_INT_NOCARD)
2314 0 : return (AH_FALSE);
2315 :
2316 0 : if (data & (AR5K_AR5211_PISR_RXOK | AR5K_AR5211_PISR_RXERR))
2317 0 : *interrupt_mask |= HAL_INT_RX;
2318 :
2319 0 : if (data & (AR5K_AR5211_PISR_TXOK | AR5K_AR5211_PISR_TXERR))
2320 0 : *interrupt_mask |= HAL_INT_TX;
2321 :
2322 0 : if (data & (AR5K_AR5211_PISR_HIUERR))
2323 0 : *interrupt_mask |= HAL_INT_FATAL;
2324 :
2325 : /*
2326 : * Special interrupt handling (not caught by the driver)
2327 : */
2328 0 : if (((*interrupt_mask) & AR5K_AR5211_PISR_RXPHY) &&
2329 0 : hal->ah_radar.r_enabled == AH_TRUE)
2330 0 : ar5k_radar_alert(hal);
2331 :
2332 0 : return (AH_TRUE);
2333 0 : }
2334 :
2335 : u_int32_t
2336 0 : ar5k_ar5211_get_intr(struct ath_hal *hal)
2337 : {
2338 : /* Return the interrupt mask stored previously */
2339 0 : return (hal->ah_imr);
2340 : }
2341 :
2342 : HAL_INT
2343 0 : ar5k_ar5211_set_intr(struct ath_hal *hal, HAL_INT new_mask)
2344 : {
2345 : HAL_INT old_mask, int_mask;
2346 :
2347 : /*
2348 : * Disable card interrupts to prevent any race conditions
2349 : * (they will be re-enabled afterwards).
2350 : */
2351 0 : AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE);
2352 :
2353 0 : old_mask = hal->ah_imr;
2354 :
2355 : /*
2356 : * Add additional, chipset-dependent interrupt mask flags
2357 : * and write them to the IMR (interrupt mask register).
2358 : */
2359 0 : int_mask = new_mask & HAL_INT_COMMON;
2360 :
2361 0 : if (new_mask & HAL_INT_RX)
2362 0 : int_mask |=
2363 : AR5K_AR5211_PIMR_RXOK |
2364 : AR5K_AR5211_PIMR_RXERR |
2365 : AR5K_AR5211_PIMR_RXORN |
2366 : AR5K_AR5211_PIMR_RXDESC;
2367 :
2368 0 : if (new_mask & HAL_INT_TX)
2369 0 : int_mask |=
2370 : AR5K_AR5211_PIMR_TXOK |
2371 : AR5K_AR5211_PIMR_TXERR |
2372 : AR5K_AR5211_PIMR_TXDESC |
2373 : AR5K_AR5211_PIMR_TXURN;
2374 :
2375 0 : if (new_mask & HAL_INT_FATAL) {
2376 0 : int_mask |= AR5K_AR5211_PIMR_HIUERR;
2377 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_SIMR2,
2378 : AR5K_AR5211_SIMR2_MCABT |
2379 : AR5K_AR5211_SIMR2_SSERR |
2380 : AR5K_AR5211_SIMR2_DPERR);
2381 0 : }
2382 :
2383 0 : AR5K_REG_WRITE(AR5K_AR5211_PIMR, int_mask);
2384 :
2385 : /* Store new interrupt mask */
2386 0 : hal->ah_imr = new_mask;
2387 :
2388 : /* ..re-enable interrupts */
2389 0 : AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE);
2390 :
2391 0 : return (old_mask);
2392 : }
2393 :
2394 : /*
2395 : * Misc internal functions
2396 : */
2397 :
2398 : HAL_BOOL
2399 0 : ar5k_ar5211_get_capabilities(struct ath_hal *hal)
2400 : {
2401 : u_int16_t ee_header;
2402 : u_int a, b, g;
2403 :
2404 : /* Capabilities stored in the EEPROM */
2405 0 : ee_header = hal->ah_capabilities.cap_eeprom.ee_header;
2406 :
2407 0 : a = AR5K_EEPROM_HDR_11A(ee_header);
2408 0 : b = AR5K_EEPROM_HDR_11B(ee_header);
2409 0 : g = AR5K_EEPROM_HDR_11G(ee_header);
2410 :
2411 : /*
2412 : * If the EEPROM is not reporting any mode, we try 11b.
2413 : * This might fix a few broken devices with invalid EEPROM.
2414 : */
2415 0 : if (!a && !b && !g)
2416 0 : b = 1;
2417 :
2418 : /*
2419 : * XXX The AR5211 tranceiver supports frequencies from 4920 to 6100GHz
2420 : * XXX and from 2312 to 2732GHz. There are problems with the current
2421 : * XXX ieee80211 implementation because the IEEE channel mapping
2422 : * XXX does not support negative channel numbers (2312MHz is channel
2423 : * XXX -19). Of course, this doesn't matter because these channels
2424 : * XXX are out of range but some regulation domains like MKK (Japan)
2425 : * XXX will support frequencies somewhere around 4.8GHz.
2426 : */
2427 :
2428 : /*
2429 : * Set radio capabilities
2430 : */
2431 :
2432 0 : if (a) {
2433 0 : hal->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2434 0 : hal->ah_capabilities.cap_range.range_5ghz_max = 6100;
2435 :
2436 : /* Set supported modes */
2437 0 : hal->ah_capabilities.cap_mode = HAL_MODE_11A | HAL_MODE_TURBO;
2438 0 : }
2439 :
2440 : /* This chip will support 802.11b if the 2GHz radio is connected */
2441 0 : if (b || g) {
2442 0 : hal->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2443 0 : hal->ah_capabilities.cap_range.range_2ghz_max = 2732;
2444 :
2445 0 : if (b)
2446 0 : hal->ah_capabilities.cap_mode |= HAL_MODE_11B;
2447 : #if 0
2448 : if (g)
2449 : hal->ah_capabilities.cap_mode |= HAL_MODE_11G;
2450 : #endif
2451 : }
2452 :
2453 : /* GPIO */
2454 0 : hal->ah_gpio_npins = AR5K_AR5211_NUM_GPIO;
2455 :
2456 : /* Set number of supported TX queues */
2457 0 : hal->ah_capabilities.cap_queues.q_tx_num = AR5K_AR5211_TX_NUM_QUEUES;
2458 :
2459 0 : return (AH_TRUE);
2460 : }
2461 :
2462 : void
2463 0 : ar5k_ar5211_radar_alert(struct ath_hal *hal, HAL_BOOL enable)
2464 : {
2465 : /*
2466 : * Enable radar detection
2467 : */
2468 0 : AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_DISABLE);
2469 :
2470 0 : if (enable == AH_TRUE) {
2471 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR,
2472 : AR5K_AR5211_PHY_RADAR_ENABLE);
2473 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_PIMR,
2474 : AR5K_AR5211_PIMR_RXPHY);
2475 0 : } else {
2476 0 : AR5K_REG_WRITE(AR5K_AR5211_PHY_RADAR,
2477 : AR5K_AR5211_PHY_RADAR_DISABLE);
2478 0 : AR5K_REG_DISABLE_BITS(AR5K_AR5211_PIMR,
2479 : AR5K_AR5211_PIMR_RXPHY);
2480 : }
2481 :
2482 0 : AR5K_REG_WRITE(AR5K_AR5211_IER, AR5K_AR5211_IER_ENABLE);
2483 0 : }
2484 :
2485 : /*
2486 : * EEPROM access functions
2487 : */
2488 :
2489 : HAL_BOOL
2490 0 : ar5k_ar5211_eeprom_is_busy(struct ath_hal *hal)
2491 : {
2492 0 : return (AR5K_REG_READ(AR5K_AR5211_CFG) & AR5K_AR5211_CFG_EEBS ?
2493 : AH_TRUE : AH_FALSE);
2494 : }
2495 :
2496 : int
2497 0 : ar5k_ar5211_eeprom_read(struct ath_hal *hal, u_int32_t offset, u_int16_t *data)
2498 : {
2499 : u_int32_t status, i;
2500 :
2501 : /*
2502 : * Initialize EEPROM access
2503 : */
2504 0 : AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset);
2505 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD,
2506 : AR5K_AR5211_EEPROM_CMD_READ);
2507 :
2508 0 : for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
2509 0 : status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS);
2510 0 : if (status & AR5K_AR5211_EEPROM_STAT_RDDONE) {
2511 0 : if (status & AR5K_AR5211_EEPROM_STAT_RDERR)
2512 0 : return (EIO);
2513 0 : *data = (u_int16_t)
2514 0 : (AR5K_REG_READ(AR5K_AR5211_EEPROM_DATA) & 0xffff);
2515 0 : return (0);
2516 : }
2517 0 : AR5K_DELAY(15);
2518 : }
2519 :
2520 0 : return (ETIMEDOUT);
2521 0 : }
2522 :
2523 : int
2524 0 : ar5k_ar5211_eeprom_write(struct ath_hal *hal, u_int32_t offset, u_int16_t data)
2525 : {
2526 : u_int32_t status, timeout;
2527 :
2528 : /* Enable eeprom access */
2529 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD,
2530 : AR5K_AR5211_EEPROM_CMD_RESET);
2531 0 : AR5K_REG_ENABLE_BITS(AR5K_AR5211_EEPROM_CMD,
2532 : AR5K_AR5211_EEPROM_CMD_WRITE);
2533 :
2534 : /*
2535 : * Prime write pump
2536 : */
2537 0 : AR5K_REG_WRITE(AR5K_AR5211_EEPROM_BASE, (u_int8_t)offset - 1);
2538 :
2539 0 : for (timeout = 10000; timeout > 0; timeout--) {
2540 0 : AR5K_DELAY(1);
2541 0 : status = AR5K_REG_READ(AR5K_AR5211_EEPROM_STATUS);
2542 0 : if (status & AR5K_AR5211_EEPROM_STAT_WRDONE) {
2543 0 : if (status & AR5K_AR5211_EEPROM_STAT_WRERR)
2544 0 : return (EIO);
2545 0 : return (0);
2546 : }
2547 : }
2548 :
2549 0 : return (ETIMEDOUT);
2550 0 : }
2551 :
2552 : /*
2553 : * RF register settings
2554 : */
2555 :
2556 : HAL_BOOL
2557 0 : ar5k_ar5211_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int freq,
2558 : u_int ee_mode)
2559 : {
2560 0 : struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
2561 0 : struct ar5k_ar5211_ini_rf rf[nitems(ar5211_rf)];
2562 : u_int32_t ob, db, xpds, xpdp, x_gain;
2563 : u_int i;
2564 : int obdb;
2565 :
2566 0 : bcopy(ar5211_rf, rf, sizeof(rf));
2567 : obdb = 0;
2568 :
2569 0 : if (freq == AR5K_INI_RFGAIN_2GHZ &&
2570 0 : hal->ah_ee_version >= AR5K_EEPROM_VERSION_3_1) {
2571 0 : ob = ar5k_bitswap(ee->ee_ob[ee_mode][0], 3);
2572 0 : db = ar5k_bitswap(ee->ee_db[ee_mode][0], 3);
2573 0 : rf[25].rf_value[freq] =
2574 0 : ((ob << 6) & 0xc0) | (rf[25].rf_value[freq] & ~0xc0);
2575 0 : rf[26].rf_value[freq] =
2576 0 : (((ob >> 2) & 0x1) | ((db << 1) & 0xe)) |
2577 0 : (rf[26].rf_value[freq] & ~0xf);
2578 0 : }
2579 :
2580 0 : if (freq == AR5K_INI_RFGAIN_5GHZ) {
2581 : /* For 11a and Turbo */
2582 0 : obdb = channel->c_channel >= 5725 ? 3 :
2583 0 : (channel->c_channel >= 5500 ? 2 :
2584 0 : (channel->c_channel >= 5260 ? 1 :
2585 0 : (channel->c_channel > 4000 ? 0 : -1)));
2586 0 : }
2587 :
2588 : /* bogus channel: bad beacon? */
2589 0 : if (obdb < 0)
2590 0 : return (AH_FALSE);
2591 :
2592 0 : ob = ee->ee_ob[ee_mode][obdb];
2593 0 : db = ee->ee_db[ee_mode][obdb];
2594 0 : x_gain = ee->ee_x_gain[ee_mode];
2595 0 : xpds = ee->ee_xpd[ee_mode];
2596 0 : xpdp = !xpds;
2597 :
2598 0 : rf[11].rf_value[freq] = (rf[11].rf_value[freq] & ~0xc0) |
2599 0 : (((ar5k_bitswap(x_gain, 4) << 7) | (xpdp << 6)) & 0xc0);
2600 0 : rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x7) |
2601 0 : ((ar5k_bitswap(x_gain, 4) >> 1) & 0x7);
2602 0 : rf[12].rf_value[freq] = (rf[12].rf_value[freq] & ~0x80) |
2603 0 : ((ar5k_bitswap(ob, 3) << 7) & 0x80);
2604 0 : rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x3) |
2605 0 : ((ar5k_bitswap(ob, 3) >> 1) & 0x3);
2606 0 : rf[13].rf_value[freq] = (rf[13].rf_value[freq] & ~0x1c) |
2607 0 : ((ar5k_bitswap(db, 3) << 2) & 0x1c);
2608 0 : rf[17].rf_value[freq] = (rf[17].rf_value[freq] & ~0x8) |
2609 0 : ((xpds << 3) & 0x8);
2610 :
2611 0 : for (i = 0; i < nitems(rf); i++) {
2612 0 : AR5K_REG_WAIT(i);
2613 0 : AR5K_REG_WRITE((u_int32_t)rf[i].rf_register,
2614 : rf[i].rf_value[freq]);
2615 : }
2616 :
2617 0 : hal->ah_rf_gain = HAL_RFGAIN_INACTIVE;
2618 :
2619 0 : return (AH_TRUE);
2620 0 : }
2621 :
2622 : HAL_BOOL
2623 0 : ar5k_ar5211_set_txpower_limit(struct ath_hal *hal, u_int power)
2624 : {
2625 : /* Not implemented */
2626 0 : return (AH_FALSE);
2627 : }
|
