Line data Source code
1 : /* $OpenBSD: athn.c,v 1.99 2018/04/26 12:50:07 pirofti Exp $ */
2 :
3 : /*-
4 : * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
5 : * Copyright (c) 2008-2010 Atheros Communications Inc.
6 : *
7 : * Permission to use, copy, modify, and/or distribute this software for any
8 : * purpose with or without fee is hereby granted, provided that the above
9 : * copyright notice and this permission notice appear in all copies.
10 : *
11 : * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 : * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 : * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 : * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 : * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 : * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 : * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 : */
19 :
20 : /*
21 : * Driver for Atheros 802.11a/g/n chipsets.
22 : */
23 :
24 : #include "athn_usb.h"
25 : #include "bpfilter.h"
26 :
27 : #include <sys/param.h>
28 : #include <sys/sockio.h>
29 : #include <sys/mbuf.h>
30 : #include <sys/kernel.h>
31 : #include <sys/socket.h>
32 : #include <sys/systm.h>
33 : #include <sys/malloc.h>
34 : #include <sys/queue.h>
35 : #include <sys/timeout.h>
36 : #include <sys/conf.h>
37 : #include <sys/device.h>
38 : #include <sys/stdint.h> /* uintptr_t */
39 : #include <sys/endian.h>
40 :
41 : #include <machine/bus.h>
42 : #include <machine/intr.h>
43 :
44 : #if NBPFILTER > 0
45 : #include <net/bpf.h>
46 : #endif
47 : #include <net/if.h>
48 : #include <net/if_dl.h>
49 : #include <net/if_media.h>
50 :
51 : #include <netinet/in.h>
52 : #include <netinet/if_ether.h>
53 :
54 : #include <net80211/ieee80211_var.h>
55 : #include <net80211/ieee80211_amrr.h>
56 : #include <net80211/ieee80211_mira.h>
57 : #include <net80211/ieee80211_radiotap.h>
58 :
59 : #include <dev/ic/athnreg.h>
60 : #include <dev/ic/athnvar.h>
61 :
62 : #ifdef ATHN_DEBUG
63 : int athn_debug = 0;
64 : #endif
65 :
66 : void athn_radiotap_attach(struct athn_softc *);
67 : void athn_get_chanlist(struct athn_softc *);
68 : const char * athn_get_mac_name(struct athn_softc *);
69 : const char * athn_get_rf_name(struct athn_softc *);
70 : void athn_led_init(struct athn_softc *);
71 : void athn_set_led(struct athn_softc *, int);
72 : void athn_btcoex_init(struct athn_softc *);
73 : void athn_btcoex_enable(struct athn_softc *);
74 : void athn_btcoex_disable(struct athn_softc *);
75 : void athn_set_rxfilter(struct athn_softc *, uint32_t);
76 : void athn_get_chipid(struct athn_softc *);
77 : int athn_reset_power_on(struct athn_softc *);
78 : int athn_reset(struct athn_softc *, int);
79 : void athn_init_pll(struct athn_softc *,
80 : const struct ieee80211_channel *);
81 : int athn_set_power_awake(struct athn_softc *);
82 : void athn_set_power_sleep(struct athn_softc *);
83 : void athn_write_serdes(struct athn_softc *,
84 : const struct athn_serdes *);
85 : void athn_config_pcie(struct athn_softc *);
86 : void athn_config_nonpcie(struct athn_softc *);
87 : int athn_set_chan(struct athn_softc *, struct ieee80211_channel *,
88 : struct ieee80211_channel *);
89 : int athn_switch_chan(struct athn_softc *,
90 : struct ieee80211_channel *, struct ieee80211_channel *);
91 : void athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);
92 : void athn_reset_key(struct athn_softc *, int);
93 : int athn_set_key(struct ieee80211com *, struct ieee80211_node *,
94 : struct ieee80211_key *);
95 : void athn_delete_key(struct ieee80211com *, struct ieee80211_node *,
96 : struct ieee80211_key *);
97 : void athn_iter_calib(void *, struct ieee80211_node *);
98 : void athn_calib_to(void *);
99 : int athn_init_calib(struct athn_softc *,
100 : struct ieee80211_channel *, struct ieee80211_channel *);
101 : uint8_t athn_chan2fbin(struct ieee80211_channel *);
102 : int athn_interpolate(int, int, int, int, int);
103 : void athn_get_pier_ival(uint8_t, const uint8_t *, int, int *,
104 : int *);
105 : void athn_init_dma(struct athn_softc *);
106 : void athn_rx_start(struct athn_softc *);
107 : void athn_inc_tx_trigger_level(struct athn_softc *);
108 : int athn_stop_rx_dma(struct athn_softc *);
109 : int athn_rx_abort(struct athn_softc *);
110 : void athn_tx_reclaim(struct athn_softc *, int);
111 : int athn_tx_pending(struct athn_softc *, int);
112 : void athn_stop_tx_dma(struct athn_softc *, int);
113 : int athn_txtime(struct athn_softc *, int, int, u_int);
114 : void athn_set_sta_timers(struct athn_softc *);
115 : void athn_set_hostap_timers(struct athn_softc *);
116 : void athn_set_opmode(struct athn_softc *);
117 : void athn_set_bss(struct athn_softc *, struct ieee80211_node *);
118 : void athn_enable_interrupts(struct athn_softc *);
119 : void athn_disable_interrupts(struct athn_softc *);
120 : void athn_init_qos(struct athn_softc *);
121 : int athn_hw_reset(struct athn_softc *, struct ieee80211_channel *,
122 : struct ieee80211_channel *, int);
123 : struct ieee80211_node *athn_node_alloc(struct ieee80211com *);
124 : void athn_newassoc(struct ieee80211com *, struct ieee80211_node *,
125 : int);
126 : void athn_node_leave(struct ieee80211com *, struct ieee80211_node *);
127 : int athn_media_change(struct ifnet *);
128 : void athn_next_scan(void *);
129 : void athn_iter_mira_delete(void *, struct ieee80211_node *);
130 : void athn_delete_mira_nodes(struct athn_softc *);
131 : int athn_newstate(struct ieee80211com *, enum ieee80211_state,
132 : int);
133 : void athn_updateedca(struct ieee80211com *);
134 : int athn_clock_rate(struct athn_softc *);
135 : void athn_updateslot(struct ieee80211com *);
136 : void athn_start(struct ifnet *);
137 : void athn_watchdog(struct ifnet *);
138 : void athn_set_multi(struct athn_softc *);
139 : int athn_ioctl(struct ifnet *, u_long, caddr_t);
140 : int athn_init(struct ifnet *);
141 : void athn_stop(struct ifnet *, int);
142 : void athn_init_tx_queues(struct athn_softc *);
143 : int32_t athn_ani_get_rssi(struct athn_softc *);
144 : void athn_ani_ofdm_err_trigger(struct athn_softc *);
145 : void athn_ani_cck_err_trigger(struct athn_softc *);
146 : void athn_ani_lower_immunity(struct athn_softc *);
147 : void athn_ani_restart(struct athn_softc *);
148 : void athn_ani_monitor(struct athn_softc *);
149 :
150 : /* Extern functions. */
151 : int ar5416_attach(struct athn_softc *);
152 : int ar9280_attach(struct athn_softc *);
153 : int ar9285_attach(struct athn_softc *);
154 : int ar9287_attach(struct athn_softc *);
155 : int ar9380_attach(struct athn_softc *);
156 : int ar5416_init_calib(struct athn_softc *,
157 : struct ieee80211_channel *, struct ieee80211_channel *);
158 : int ar9285_init_calib(struct athn_softc *,
159 : struct ieee80211_channel *, struct ieee80211_channel *);
160 : int ar9003_init_calib(struct athn_softc *);
161 : void ar9285_pa_calib(struct athn_softc *);
162 : void ar9271_pa_calib(struct athn_softc *);
163 : void ar9287_1_3_enable_async_fifo(struct athn_softc *);
164 : void ar9287_1_3_setup_async_fifo(struct athn_softc *);
165 : void ar9003_reset_txsring(struct athn_softc *);
166 :
167 : struct cfdriver athn_cd = {
168 : NULL, "athn", DV_IFNET
169 : };
170 :
171 : int
172 0 : athn_attach(struct athn_softc *sc)
173 : {
174 0 : struct ieee80211com *ic = &sc->sc_ic;
175 0 : struct ifnet *ifp = &ic->ic_if;
176 : int error;
177 :
178 : /* Read hardware revision. */
179 0 : athn_get_chipid(sc);
180 :
181 0 : if ((error = athn_reset_power_on(sc)) != 0) {
182 0 : printf("%s: could not reset chip\n", sc->sc_dev.dv_xname);
183 0 : return (error);
184 : }
185 :
186 0 : if ((error = athn_set_power_awake(sc)) != 0) {
187 0 : printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname);
188 0 : return (error);
189 : }
190 :
191 0 : if (AR_SREV_5416(sc) || AR_SREV_9160(sc))
192 0 : error = ar5416_attach(sc);
193 0 : else if (AR_SREV_9280(sc))
194 0 : error = ar9280_attach(sc);
195 0 : else if (AR_SREV_9285(sc))
196 0 : error = ar9285_attach(sc);
197 : #if NATHN_USB > 0
198 0 : else if (AR_SREV_9271(sc))
199 0 : error = ar9285_attach(sc);
200 : #endif
201 0 : else if (AR_SREV_9287(sc))
202 0 : error = ar9287_attach(sc);
203 0 : else if (AR_SREV_9380(sc) || AR_SREV_9485(sc))
204 0 : error = ar9380_attach(sc);
205 : else
206 : error = ENOTSUP;
207 0 : if (error != 0) {
208 0 : printf("%s: could not attach chip\n", sc->sc_dev.dv_xname);
209 0 : return (error);
210 : }
211 :
212 : /* We can put the chip in sleep state now. */
213 0 : athn_set_power_sleep(sc);
214 :
215 0 : if (!(sc->flags & ATHN_FLAG_USB)) {
216 0 : error = sc->ops.dma_alloc(sc);
217 0 : if (error != 0) {
218 0 : printf("%s: could not allocate DMA resources\n",
219 0 : sc->sc_dev.dv_xname);
220 0 : return (error);
221 : }
222 : /* Steal one Tx buffer for beacons. */
223 0 : sc->bcnbuf = SIMPLEQ_FIRST(&sc->txbufs);
224 0 : SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list);
225 : }
226 :
227 0 : if (sc->flags & ATHN_FLAG_RFSILENT) {
228 : DPRINTF(("found RF switch connected to GPIO pin %d\n",
229 : sc->rfsilent_pin));
230 : }
231 : DPRINTF(("%d key cache entries\n", sc->kc_entries));
232 : /*
233 : * In HostAP mode, the number of STAs that we can handle is
234 : * limited by the number of entries in the HW key cache.
235 : * TKIP keys consume 2 entries in the cache.
236 : */
237 0 : ic->ic_max_nnodes = (sc->kc_entries / 2) - IEEE80211_WEP_NKID;
238 0 : if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE)
239 0 : ic->ic_max_nnodes = IEEE80211_CACHE_SIZE;
240 :
241 : DPRINTF(("using %s loop power control\n",
242 : (sc->flags & ATHN_FLAG_OLPC) ? "open" : "closed"));
243 :
244 : DPRINTF(("txchainmask=0x%x rxchainmask=0x%x\n",
245 : sc->txchainmask, sc->rxchainmask));
246 : /* Count the number of bits set (in lowest 3 bits). */
247 0 : sc->ntxchains =
248 0 : ((sc->txchainmask >> 2) & 1) +
249 0 : ((sc->txchainmask >> 1) & 1) +
250 0 : ((sc->txchainmask >> 0) & 1);
251 0 : sc->nrxchains =
252 0 : ((sc->rxchainmask >> 2) & 1) +
253 0 : ((sc->rxchainmask >> 1) & 1) +
254 0 : ((sc->rxchainmask >> 0) & 1);
255 :
256 0 : if (AR_SINGLE_CHIP(sc)) {
257 0 : printf("%s: %s rev %d (%dT%dR), ROM rev %d, address %s\n",
258 : sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev,
259 0 : sc->ntxchains, sc->nrxchains, sc->eep_rev,
260 0 : ether_sprintf(ic->ic_myaddr));
261 0 : } else {
262 0 : printf("%s: MAC %s rev %d, RF %s (%dT%dR), ROM rev %d, "
263 : "address %s\n",
264 : sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev,
265 0 : athn_get_rf_name(sc), sc->ntxchains, sc->nrxchains,
266 0 : sc->eep_rev, ether_sprintf(ic->ic_myaddr));
267 : }
268 :
269 0 : timeout_set(&sc->scan_to, athn_next_scan, sc);
270 0 : timeout_set(&sc->calib_to, athn_calib_to, sc);
271 :
272 0 : sc->amrr.amrr_min_success_threshold = 1;
273 0 : sc->amrr.amrr_max_success_threshold = 15;
274 :
275 0 : ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
276 0 : ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
277 0 : ic->ic_state = IEEE80211_S_INIT;
278 :
279 : /* Set device capabilities. */
280 0 : ic->ic_caps =
281 : IEEE80211_C_WEP | /* WEP. */
282 : IEEE80211_C_RSN | /* WPA/RSN. */
283 : #ifndef IEEE80211_STA_ONLY
284 : IEEE80211_C_HOSTAP | /* Host AP mode supported. */
285 : IEEE80211_C_APPMGT | /* Host AP power saving supported. */
286 : #endif
287 : IEEE80211_C_MONITOR | /* Monitor mode supported. */
288 : IEEE80211_C_SHSLOT | /* Short slot time supported. */
289 : IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */
290 : IEEE80211_C_PMGT; /* Power saving supported. */
291 :
292 0 : if (sc->flags & ATHN_FLAG_11N) {
293 : int i, ntxstreams, nrxstreams;
294 :
295 : /* Set HT capabilities. */
296 0 : ic->ic_htcaps = (IEEE80211_HTCAP_SMPS_DIS <<
297 : IEEE80211_HTCAP_SMPS_SHIFT);
298 : #ifdef notyet
299 : ic->ic_htcaps |= IEEE80211_HTCAP_CBW20_40 |
300 : IEEE80211_HTCAP_SGI40 |
301 : IEEE80211_HTCAP_DSSSCCK40;
302 : #endif
303 0 : ic->ic_htxcaps = 0;
304 : #ifdef notyet
305 : if (AR_SREV_9271(sc) || AR_SREV_9287_10_OR_LATER(sc))
306 : ic->ic_htcaps |= IEEE80211_HTCAP_SGI20;
307 : if (AR_SREV_9380_10_OR_LATER(sc))
308 : ic->ic_htcaps |= IEEE80211_HTCAP_LDPC;
309 : if (AR_SREV_9280_10_OR_LATER(sc)) {
310 : ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
311 : ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT;
312 : }
313 : #endif
314 0 : ntxstreams = sc->ntxchains;
315 0 : nrxstreams = sc->nrxchains;
316 0 : if (!AR_SREV_9380_10_OR_LATER(sc)) {
317 0 : ntxstreams = MIN(ntxstreams, 2);
318 0 : nrxstreams = MIN(nrxstreams, 2);
319 0 : }
320 : /* Set supported HT rates. */
321 0 : for (i = 0; i < nrxstreams; i++)
322 0 : ic->ic_sup_mcs[i] = 0xff;
323 0 : ic->ic_tx_mcs_set |= IEEE80211_TX_MCS_SET_DEFINED;
324 0 : if (ntxstreams != nrxstreams) {
325 0 : ic->ic_tx_mcs_set |= IEEE80211_TX_RX_MCS_NOT_EQUAL;
326 0 : ic->ic_tx_mcs_set |= (ntxstreams - 1) << 2;
327 0 : }
328 0 : }
329 :
330 : /* Set supported rates. */
331 0 : if (sc->flags & ATHN_FLAG_11G) {
332 0 : ic->ic_sup_rates[IEEE80211_MODE_11B] =
333 0 : ieee80211_std_rateset_11b;
334 0 : ic->ic_sup_rates[IEEE80211_MODE_11G] =
335 0 : ieee80211_std_rateset_11g;
336 0 : }
337 0 : if (sc->flags & ATHN_FLAG_11A) {
338 0 : ic->ic_sup_rates[IEEE80211_MODE_11A] =
339 0 : ieee80211_std_rateset_11a;
340 0 : }
341 :
342 : /* Get the list of authorized/supported channels. */
343 0 : athn_get_chanlist(sc);
344 :
345 : /* IBSS channel undefined for now. */
346 0 : ic->ic_ibss_chan = &ic->ic_channels[0];
347 :
348 0 : ifp->if_softc = sc;
349 0 : ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
350 0 : ifp->if_ioctl = athn_ioctl;
351 0 : ifp->if_start = athn_start;
352 0 : ifp->if_watchdog = athn_watchdog;
353 0 : memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
354 :
355 0 : if_attach(ifp);
356 0 : ieee80211_ifattach(ifp);
357 0 : ic->ic_node_alloc = athn_node_alloc;
358 : #ifndef IEEE80211_STA_ONLY
359 0 : ic->ic_node_leave = athn_node_leave;
360 : #endif
361 0 : ic->ic_newassoc = athn_newassoc;
362 0 : ic->ic_updateslot = athn_updateslot;
363 0 : ic->ic_updateedca = athn_updateedca;
364 : #ifdef notyet
365 : ic->ic_set_key = athn_set_key;
366 : ic->ic_delete_key = athn_delete_key;
367 : #endif
368 :
369 : /* Override 802.11 state transition machine. */
370 0 : sc->sc_newstate = ic->ic_newstate;
371 0 : ic->ic_newstate = athn_newstate;
372 0 : ieee80211_media_init(ifp, athn_media_change, ieee80211_media_status);
373 :
374 : #if NBPFILTER > 0
375 0 : athn_radiotap_attach(sc);
376 : #endif
377 :
378 0 : return (0);
379 0 : }
380 :
381 : void
382 0 : athn_detach(struct athn_softc *sc)
383 : {
384 0 : struct ifnet *ifp = &sc->sc_ic.ic_if;
385 : struct ieee80211com *ic = &sc->sc_ic;
386 : int qid;
387 :
388 0 : timeout_del(&sc->scan_to);
389 0 : timeout_del(&sc->calib_to);
390 0 : if (ic->ic_flags & IEEE80211_F_HTON)
391 0 : athn_delete_mira_nodes(sc);
392 :
393 0 : if (!(sc->flags & ATHN_FLAG_USB)) {
394 0 : for (qid = 0; qid < ATHN_QID_COUNT; qid++)
395 0 : athn_tx_reclaim(sc, qid);
396 :
397 : /* Free Tx/Rx DMA resources. */
398 0 : sc->ops.dma_free(sc);
399 0 : }
400 : /* Free ROM copy. */
401 0 : if (sc->eep != NULL)
402 0 : free(sc->eep, M_DEVBUF, 0);
403 :
404 0 : ieee80211_ifdetach(ifp);
405 0 : if_detach(ifp);
406 0 : }
407 :
408 : #if NBPFILTER > 0
409 : /*
410 : * Attach the interface to 802.11 radiotap.
411 : */
412 : void
413 0 : athn_radiotap_attach(struct athn_softc *sc)
414 : {
415 0 : bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO,
416 : sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN);
417 :
418 0 : sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
419 0 : sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
420 0 : sc->sc_rxtap.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT);
421 :
422 0 : sc->sc_txtap_len = sizeof(sc->sc_txtapu);
423 0 : sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
424 0 : sc->sc_txtap.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT);
425 0 : }
426 : #endif
427 :
428 : void
429 0 : athn_get_chanlist(struct athn_softc *sc)
430 : {
431 0 : struct ieee80211com *ic = &sc->sc_ic;
432 : uint8_t chan;
433 : int i;
434 :
435 0 : if (sc->flags & ATHN_FLAG_11G) {
436 0 : for (i = 1; i <= 14; i++) {
437 0 : chan = i;
438 0 : ic->ic_channels[chan].ic_freq =
439 0 : ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ);
440 0 : ic->ic_channels[chan].ic_flags =
441 : IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
442 : IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
443 0 : if (sc->flags & ATHN_FLAG_11N)
444 0 : ic->ic_channels[chan].ic_flags |=
445 : IEEE80211_CHAN_HT;
446 : }
447 : }
448 0 : if (sc->flags & ATHN_FLAG_11A) {
449 0 : for (i = 0; i < nitems(athn_5ghz_chans); i++) {
450 0 : chan = athn_5ghz_chans[i];
451 0 : ic->ic_channels[chan].ic_freq =
452 0 : ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ);
453 0 : ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A;
454 0 : if (sc->flags & ATHN_FLAG_11N)
455 0 : ic->ic_channels[chan].ic_flags |=
456 : IEEE80211_CHAN_HT;
457 : }
458 : }
459 0 : }
460 :
461 : void
462 0 : athn_rx_start(struct athn_softc *sc)
463 : {
464 0 : struct ieee80211com *ic = &sc->sc_ic;
465 : uint32_t rfilt;
466 :
467 : /* Setup Rx DMA descriptors. */
468 0 : sc->ops.rx_enable(sc);
469 :
470 : /* Set Rx filter. */
471 : rfilt = AR_RX_FILTER_UCAST | AR_RX_FILTER_BCAST | AR_RX_FILTER_MCAST;
472 : /* Want Compressed Block Ack Requests. */
473 : rfilt |= AR_RX_FILTER_COMPR_BAR;
474 : rfilt |= AR_RX_FILTER_BEACON;
475 0 : if (ic->ic_opmode != IEEE80211_M_STA) {
476 : rfilt |= AR_RX_FILTER_PROBEREQ;
477 0 : if (ic->ic_opmode == IEEE80211_M_MONITOR)
478 0 : rfilt |= AR_RX_FILTER_PROM;
479 : #ifndef IEEE80211_STA_ONLY
480 0 : if (AR_SREV_9280_10_OR_LATER(sc) &&
481 0 : ic->ic_opmode == IEEE80211_M_HOSTAP)
482 0 : rfilt |= AR_RX_FILTER_PSPOLL;
483 : #endif
484 : }
485 0 : athn_set_rxfilter(sc, rfilt);
486 :
487 : /* Set BSSID mask. */
488 0 : AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
489 0 : AR_WRITE(sc, AR_BSSMSKU, 0xffff);
490 :
491 0 : athn_set_opmode(sc);
492 :
493 : /* Set multicast filter. */
494 0 : AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff);
495 0 : AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff);
496 :
497 0 : AR_WRITE(sc, AR_FILT_OFDM, 0);
498 0 : AR_WRITE(sc, AR_FILT_CCK, 0);
499 0 : AR_WRITE(sc, AR_MIBC, 0);
500 0 : AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
501 0 : AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
502 :
503 : /* XXX ANI. */
504 0 : AR_WRITE(sc, AR_PHY_ERR_1, 0);
505 0 : AR_WRITE(sc, AR_PHY_ERR_2, 0);
506 :
507 : /* Disable HW crypto for now. */
508 0 : AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS);
509 :
510 : /* Start PCU Rx. */
511 0 : AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
512 0 : AR_WRITE_BARRIER(sc);
513 0 : }
514 :
515 : void
516 0 : athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt)
517 : {
518 0 : AR_WRITE(sc, AR_RX_FILTER, rfilt);
519 :
520 : #ifdef notyet
521 : reg = AR_READ(sc, AR_PHY_ERR);
522 : reg &= (AR_PHY_ERR_RADAR | AR_PHY_ERR_OFDM_TIMING |
523 : AR_PHY_ERR_CCK_TIMING);
524 : AR_WRITE(sc, AR_PHY_ERR, reg);
525 : if (reg != 0)
526 : AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
527 : else
528 : AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
529 : #else
530 0 : AR_WRITE(sc, AR_PHY_ERR, 0);
531 0 : AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA);
532 : #endif
533 0 : AR_WRITE_BARRIER(sc);
534 0 : }
535 :
536 : int
537 0 : athn_intr(void *xsc)
538 : {
539 0 : struct athn_softc *sc = xsc;
540 0 : struct ifnet *ifp = &sc->sc_ic.ic_if;
541 :
542 0 : if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) !=
543 : (IFF_UP | IFF_RUNNING))
544 0 : return (0);
545 :
546 0 : return (sc->ops.intr(sc));
547 0 : }
548 :
549 : void
550 0 : athn_get_chipid(struct athn_softc *sc)
551 : {
552 : uint32_t reg;
553 :
554 0 : reg = AR_READ(sc, AR_SREV);
555 0 : if (MS(reg, AR_SREV_ID) == 0xff) {
556 0 : sc->mac_ver = MS(reg, AR_SREV_VERSION2);
557 0 : sc->mac_rev = MS(reg, AR_SREV_REVISION2);
558 0 : if (!(reg & AR_SREV_TYPE2_HOST_MODE))
559 0 : sc->flags |= ATHN_FLAG_PCIE;
560 : } else {
561 0 : sc->mac_ver = MS(reg, AR_SREV_VERSION);
562 0 : sc->mac_rev = MS(reg, AR_SREV_REVISION);
563 0 : if (sc->mac_ver == AR_SREV_VERSION_5416_PCIE)
564 0 : sc->flags |= ATHN_FLAG_PCIE;
565 : }
566 0 : }
567 :
568 : const char *
569 0 : athn_get_mac_name(struct athn_softc *sc)
570 : {
571 0 : switch (sc->mac_ver) {
572 : case AR_SREV_VERSION_5416_PCI:
573 0 : return ("AR5416");
574 : case AR_SREV_VERSION_5416_PCIE:
575 0 : return ("AR5418");
576 : case AR_SREV_VERSION_9160:
577 0 : return ("AR9160");
578 : case AR_SREV_VERSION_9280:
579 0 : return ("AR9280");
580 : case AR_SREV_VERSION_9285:
581 0 : return ("AR9285");
582 : case AR_SREV_VERSION_9271:
583 0 : return ("AR9271");
584 : case AR_SREV_VERSION_9287:
585 0 : return ("AR9287");
586 : case AR_SREV_VERSION_9380:
587 0 : return ("AR9380");
588 : case AR_SREV_VERSION_9485:
589 0 : return ("AR9485");
590 : }
591 0 : return ("unknown");
592 0 : }
593 :
594 : /*
595 : * Return RF chip name (not for single-chip solutions).
596 : */
597 : const char *
598 0 : athn_get_rf_name(struct athn_softc *sc)
599 : {
600 0 : KASSERT(!AR_SINGLE_CHIP(sc));
601 :
602 0 : switch (sc->rf_rev) {
603 : case AR_RAD5133_SREV_MAJOR: /* Dual-band 3T3R. */
604 0 : return ("AR5133");
605 : case AR_RAD2133_SREV_MAJOR: /* Single-band 3T3R. */
606 0 : return ("AR2133");
607 : case AR_RAD5122_SREV_MAJOR: /* Dual-band 2T2R. */
608 0 : return ("AR5122");
609 : case AR_RAD2122_SREV_MAJOR: /* Single-band 2T2R. */
610 0 : return ("AR2122");
611 : }
612 0 : return ("unknown");
613 0 : }
614 :
615 : int
616 0 : athn_reset_power_on(struct athn_softc *sc)
617 : {
618 : int ntries;
619 :
620 : /* Set force wake. */
621 0 : AR_WRITE(sc, AR_RTC_FORCE_WAKE,
622 : AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
623 :
624 0 : if (!AR_SREV_9380_10_OR_LATER(sc)) {
625 : /* Make sure no DMA is active by doing an AHB reset. */
626 0 : AR_WRITE(sc, AR_RC, AR_RC_AHB);
627 0 : }
628 : /* RTC reset and clear. */
629 0 : AR_WRITE(sc, AR_RTC_RESET, 0);
630 0 : AR_WRITE_BARRIER(sc);
631 0 : DELAY(2);
632 0 : if (!AR_SREV_9380_10_OR_LATER(sc))
633 0 : AR_WRITE(sc, AR_RC, 0);
634 0 : AR_WRITE(sc, AR_RTC_RESET, 1);
635 :
636 : /* Poll until RTC is ON. */
637 0 : for (ntries = 0; ntries < 1000; ntries++) {
638 0 : if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
639 : AR_RTC_STATUS_ON)
640 : break;
641 0 : DELAY(10);
642 : }
643 0 : if (ntries == 1000) {
644 : DPRINTF(("RTC not waking up\n"));
645 0 : return (ETIMEDOUT);
646 : }
647 0 : return (athn_reset(sc, 0));
648 0 : }
649 :
650 : int
651 0 : athn_reset(struct athn_softc *sc, int cold)
652 : {
653 : int ntries;
654 :
655 : /* Set force wake. */
656 0 : AR_WRITE(sc, AR_RTC_FORCE_WAKE,
657 : AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
658 :
659 0 : if (AR_READ(sc, AR_INTR_SYNC_CAUSE) &
660 : (AR_INTR_SYNC_LOCAL_TIMEOUT | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
661 0 : AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
662 0 : AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
663 : (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0));
664 0 : } else if (!AR_SREV_9380_10_OR_LATER(sc))
665 0 : AR_WRITE(sc, AR_RC, AR_RC_AHB);
666 :
667 0 : AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |
668 : (cold ? AR_RTC_RC_MAC_COLD : 0));
669 0 : AR_WRITE_BARRIER(sc);
670 0 : DELAY(50);
671 0 : AR_WRITE(sc, AR_RTC_RC, 0);
672 0 : for (ntries = 0; ntries < 1000; ntries++) {
673 0 : if (!(AR_READ(sc, AR_RTC_RC) &
674 : (AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD)))
675 : break;
676 0 : DELAY(10);
677 : }
678 0 : if (ntries == 1000) {
679 : DPRINTF(("RTC stuck in MAC reset\n"));
680 0 : return (ETIMEDOUT);
681 : }
682 0 : AR_WRITE(sc, AR_RC, 0);
683 0 : AR_WRITE_BARRIER(sc);
684 0 : return (0);
685 0 : }
686 :
687 : int
688 0 : athn_set_power_awake(struct athn_softc *sc)
689 : {
690 : int ntries, error;
691 :
692 : /* Do a Power-On-Reset if shutdown. */
693 0 : if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
694 : AR_RTC_STATUS_SHUTDOWN) {
695 0 : if ((error = athn_reset_power_on(sc)) != 0)
696 0 : return (error);
697 0 : if (!AR_SREV_9380_10_OR_LATER(sc))
698 0 : athn_init_pll(sc, NULL);
699 : }
700 0 : AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
701 0 : AR_WRITE_BARRIER(sc);
702 0 : DELAY(50); /* Give chip the chance to awake. */
703 :
704 : /* Poll until RTC is ON. */
705 0 : for (ntries = 0; ntries < 4000; ntries++) {
706 0 : if ((AR_READ(sc, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
707 : AR_RTC_STATUS_ON)
708 : break;
709 0 : DELAY(50);
710 0 : AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
711 : }
712 0 : if (ntries == 4000) {
713 : DPRINTF(("RTC not waking up\n"));
714 0 : return (ETIMEDOUT);
715 : }
716 :
717 0 : AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
718 0 : AR_WRITE_BARRIER(sc);
719 0 : return (0);
720 0 : }
721 :
722 : void
723 0 : athn_set_power_sleep(struct athn_softc *sc)
724 : {
725 0 : AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
726 : /* Allow the MAC to go to sleep. */
727 0 : AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
728 0 : if (!AR_SREV_9380_10_OR_LATER(sc))
729 0 : AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
730 : /*
731 : * NB: Clearing RTC_RESET_EN when setting the chip to sleep mode
732 : * results in high power consumption on AR5416 chipsets.
733 : */
734 0 : if (!AR_SREV_5416(sc) && !AR_SREV_9271(sc))
735 0 : AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN);
736 0 : AR_WRITE_BARRIER(sc);
737 0 : }
738 :
739 : void
740 0 : athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c)
741 : {
742 : uint32_t pll;
743 :
744 0 : if (AR_SREV_9380_10_OR_LATER(sc)) {
745 0 : if (AR_SREV_9485(sc))
746 0 : AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666);
747 : pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5);
748 : pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
749 0 : } else if (AR_SREV_9280_10_OR_LATER(sc)) {
750 : pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
751 0 : if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c)) {
752 0 : if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK)
753 0 : pll = 0x142c;
754 0 : else if (AR_SREV_9280_20(sc))
755 0 : pll = 0x2850;
756 : else
757 : pll |= SM(AR_RTC_9160_PLL_DIV, 0x28);
758 : } else
759 : pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c);
760 0 : } else if (AR_SREV_9160_10_OR_LATER(sc)) {
761 : pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05);
762 0 : if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c))
763 0 : pll |= SM(AR_RTC_9160_PLL_DIV, 0x50);
764 : else
765 : pll |= SM(AR_RTC_9160_PLL_DIV, 0x58);
766 : } else {
767 : pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
768 0 : if (c != NULL && IEEE80211_IS_CHAN_5GHZ(c))
769 0 : pll |= SM(AR_RTC_PLL_DIV, 0x0a);
770 : else
771 : pll |= SM(AR_RTC_PLL_DIV, 0x0b);
772 : }
773 : DPRINTFN(5, ("AR_RTC_PLL_CONTROL=0x%08x\n", pll));
774 0 : AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll);
775 0 : if (AR_SREV_9271(sc)) {
776 : /* Switch core clock to 117MHz. */
777 0 : AR_WRITE_BARRIER(sc);
778 0 : DELAY(500);
779 0 : AR_WRITE(sc, 0x50050, 0x304);
780 0 : }
781 0 : AR_WRITE_BARRIER(sc);
782 0 : DELAY(100);
783 0 : AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
784 0 : AR_WRITE_BARRIER(sc);
785 0 : }
786 :
787 : void
788 0 : athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes)
789 : {
790 : int i;
791 :
792 : /* Write sequence to Serializer/Deserializer. */
793 0 : for (i = 0; i < serdes->nvals; i++)
794 0 : AR_WRITE(sc, serdes->regs[i], serdes->vals[i]);
795 0 : AR_WRITE_BARRIER(sc);
796 0 : }
797 :
798 : void
799 0 : athn_config_pcie(struct athn_softc *sc)
800 : {
801 : /* Disable PLL when in L0s as well as receiver clock when in L1. */
802 0 : athn_write_serdes(sc, sc->serdes);
803 :
804 0 : DELAY(1000);
805 : /* Allow forcing of PCIe core into L1 state. */
806 0 : AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
807 :
808 : #ifndef ATHN_PCIE_WAEN
809 0 : AR_WRITE(sc, AR_WA, sc->workaround);
810 : #else
811 : AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN);
812 : #endif
813 0 : AR_WRITE_BARRIER(sc);
814 0 : }
815 :
816 : /*
817 : * Serializer/Deserializer programming for non-PCIe devices.
818 : */
819 : static const uint32_t ar_nonpcie_serdes_regs[] = {
820 : AR_PCIE_SERDES,
821 : AR_PCIE_SERDES,
822 : AR_PCIE_SERDES,
823 : AR_PCIE_SERDES,
824 : AR_PCIE_SERDES,
825 : AR_PCIE_SERDES,
826 : AR_PCIE_SERDES,
827 : AR_PCIE_SERDES,
828 : AR_PCIE_SERDES,
829 : AR_PCIE_SERDES2,
830 : };
831 :
832 : static const uint32_t ar_nonpcie_serdes_vals[] = {
833 : 0x9248fc00,
834 : 0x24924924,
835 : 0x28000029,
836 : 0x57160824,
837 : 0x25980579,
838 : 0x00000000,
839 : 0x1aaabe40,
840 : 0xbe105554,
841 : 0x000e1007,
842 : 0x00000000
843 : };
844 :
845 : static const struct athn_serdes ar_nonpcie_serdes = {
846 : nitems(ar_nonpcie_serdes_vals),
847 : ar_nonpcie_serdes_regs,
848 : ar_nonpcie_serdes_vals
849 : };
850 :
851 : void
852 0 : athn_config_nonpcie(struct athn_softc *sc)
853 : {
854 0 : athn_write_serdes(sc, &ar_nonpcie_serdes);
855 0 : }
856 :
857 : int
858 0 : athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c,
859 : struct ieee80211_channel *extc)
860 : {
861 0 : struct athn_ops *ops = &sc->ops;
862 : int error, qid;
863 :
864 : /* Check that Tx is stopped, otherwise RF Bus grant will not work. */
865 0 : for (qid = 0; qid < ATHN_QID_COUNT; qid++)
866 0 : if (athn_tx_pending(sc, qid))
867 0 : return (EBUSY);
868 :
869 : /* Request RF Bus grant. */
870 0 : if ((error = ops->rf_bus_request(sc)) != 0)
871 0 : return (error);
872 :
873 0 : ops->set_phy(sc, c, extc);
874 :
875 : /* Change the synthesizer. */
876 0 : if ((error = ops->set_synth(sc, c, extc)) != 0)
877 0 : return (error);
878 :
879 0 : sc->curchan = c;
880 0 : sc->curchanext = extc;
881 :
882 : /* Set transmit power values for new channel. */
883 0 : ops->set_txpower(sc, c, extc);
884 :
885 : /* Release the RF Bus grant. */
886 0 : ops->rf_bus_release(sc);
887 :
888 : /* Write delta slope coeffs for modes where OFDM may be used. */
889 0 : if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B)
890 0 : ops->set_delta_slope(sc, c, extc);
891 :
892 0 : ops->spur_mitigate(sc, c, extc);
893 : /* XXX Load noisefloor values and start calibration. */
894 :
895 0 : return (0);
896 0 : }
897 :
898 : int
899 0 : athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c,
900 : struct ieee80211_channel *extc)
901 : {
902 : int error, qid;
903 :
904 : /* Disable interrupts. */
905 0 : athn_disable_interrupts(sc);
906 :
907 : /* Stop all Tx queues. */
908 0 : for (qid = 0; qid < ATHN_QID_COUNT; qid++)
909 0 : athn_stop_tx_dma(sc, qid);
910 0 : for (qid = 0; qid < ATHN_QID_COUNT; qid++)
911 0 : athn_tx_reclaim(sc, qid);
912 :
913 : /* Stop Rx. */
914 0 : AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
915 0 : AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
916 0 : AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
917 0 : AR_WRITE(sc, AR_FILT_OFDM, 0);
918 0 : AR_WRITE(sc, AR_FILT_CCK, 0);
919 0 : athn_set_rxfilter(sc, 0);
920 0 : error = athn_stop_rx_dma(sc);
921 : if (error != 0)
922 : goto reset;
923 :
924 : #ifdef notyet
925 : /* AR9280 needs a full reset. */
926 : if (AR_SREV_9280(sc))
927 : #endif
928 : goto reset;
929 :
930 : /* If band or bandwidth changes, we need to do a full reset. */
931 : if (c->ic_flags != sc->curchan->ic_flags ||
932 : ((extc != NULL) ^ (sc->curchanext != NULL))) {
933 : DPRINTFN(2, ("channel band switch\n"));
934 : goto reset;
935 : }
936 : error = athn_set_power_awake(sc);
937 : if (error != 0)
938 : goto reset;
939 :
940 : error = athn_set_chan(sc, c, extc);
941 : if (error != 0) {
942 : reset: /* Error found, try a full reset. */
943 : DPRINTFN(3, ("needs a full reset\n"));
944 0 : error = athn_hw_reset(sc, c, extc, 0);
945 0 : if (error != 0) /* Hopeless case. */
946 0 : return (error);
947 : }
948 0 : athn_rx_start(sc);
949 :
950 : /* Re-enable interrupts. */
951 0 : athn_enable_interrupts(sc);
952 0 : return (0);
953 0 : }
954 :
955 : void
956 0 : athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa)
957 : {
958 : #define COEFF_SCALE_SHIFT 24
959 : uint32_t exp, man;
960 :
961 : /* exponent = 14 - floor(log2(coeff)) */
962 0 : for (exp = 31; exp > 0; exp--)
963 0 : if (coeff & (1 << exp))
964 : break;
965 0 : exp = 14 - (exp - COEFF_SCALE_SHIFT);
966 :
967 : /* mantissa = floor(coeff * 2^exponent + 0.5) */
968 0 : man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1));
969 :
970 0 : *mantissa = man >> (COEFF_SCALE_SHIFT - exp);
971 0 : *exponent = exp - 16;
972 : #undef COEFF_SCALE_SHIFT
973 0 : }
974 :
975 : void
976 0 : athn_reset_key(struct athn_softc *sc, int entry)
977 : {
978 : /*
979 : * NB: Key cache registers access special memory area that requires
980 : * two 32-bit writes to actually update the values in the internal
981 : * memory. Consequently, writes must be grouped by pair.
982 : */
983 0 : AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0);
984 0 : AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0);
985 :
986 0 : AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0);
987 0 : AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0);
988 :
989 0 : AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0);
990 0 : AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
991 :
992 0 : AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0);
993 0 : AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0);
994 :
995 0 : AR_WRITE_BARRIER(sc);
996 0 : }
997 :
998 : int
999 0 : athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1000 : struct ieee80211_key *k)
1001 : {
1002 0 : struct athn_softc *sc = ic->ic_softc;
1003 : const uint8_t *txmic, *rxmic, *key, *addr;
1004 : uintptr_t entry, micentry;
1005 : uint32_t type, lo, hi;
1006 :
1007 0 : switch (k->k_cipher) {
1008 : case IEEE80211_CIPHER_WEP40:
1009 : type = AR_KEYTABLE_TYPE_40;
1010 0 : break;
1011 : case IEEE80211_CIPHER_WEP104:
1012 : type = AR_KEYTABLE_TYPE_104;
1013 0 : break;
1014 : case IEEE80211_CIPHER_TKIP:
1015 : type = AR_KEYTABLE_TYPE_TKIP;
1016 0 : break;
1017 : case IEEE80211_CIPHER_CCMP:
1018 : type = AR_KEYTABLE_TYPE_CCM;
1019 0 : break;
1020 : default:
1021 : /* Fallback to software crypto for other ciphers. */
1022 0 : return (ieee80211_set_key(ic, ni, k));
1023 : }
1024 :
1025 0 : if (!(k->k_flags & IEEE80211_KEY_GROUP))
1026 0 : entry = IEEE80211_WEP_NKID + IEEE80211_AID(ni->ni_associd);
1027 : else
1028 0 : entry = k->k_id;
1029 0 : k->k_priv = (void *)entry;
1030 :
1031 : /* NB: See note about key cache registers access above. */
1032 0 : key = k->k_key;
1033 0 : if (type == AR_KEYTABLE_TYPE_TKIP) {
1034 : #ifndef IEEE80211_STA_ONLY
1035 0 : if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1036 : txmic = &key[16];
1037 0 : rxmic = &key[24];
1038 0 : } else
1039 : #endif
1040 : {
1041 : rxmic = &key[16];
1042 0 : txmic = &key[24];
1043 : }
1044 : /* Tx+Rx MIC key is at entry + 64. */
1045 0 : micentry = entry + 64;
1046 0 : AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0]));
1047 0 : AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2]));
1048 :
1049 0 : AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4]));
1050 0 : AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0]));
1051 :
1052 0 : AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4]));
1053 0 : AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR);
1054 0 : }
1055 0 : AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0]));
1056 0 : AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4]));
1057 :
1058 0 : AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6]));
1059 0 : AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10]));
1060 :
1061 0 : AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12]));
1062 0 : AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type);
1063 :
1064 0 : if (!(k->k_flags & IEEE80211_KEY_GROUP)) {
1065 0 : addr = ni->ni_macaddr;
1066 0 : lo = LE_READ_4(&addr[0]);
1067 0 : hi = LE_READ_2(&addr[4]);
1068 0 : lo = lo >> 1 | hi << 31;
1069 0 : hi = hi >> 1;
1070 0 : } else
1071 : lo = hi = 0;
1072 0 : AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo);
1073 0 : AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID);
1074 0 : AR_WRITE_BARRIER(sc);
1075 0 : return (0);
1076 0 : }
1077 :
1078 : void
1079 0 : athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1080 : struct ieee80211_key *k)
1081 : {
1082 0 : struct athn_softc *sc = ic->ic_softc;
1083 : uintptr_t entry;
1084 :
1085 0 : switch (k->k_cipher) {
1086 : case IEEE80211_CIPHER_WEP40:
1087 : case IEEE80211_CIPHER_WEP104:
1088 : case IEEE80211_CIPHER_CCMP:
1089 0 : entry = (uintptr_t)k->k_priv;
1090 0 : athn_reset_key(sc, entry);
1091 0 : break;
1092 : case IEEE80211_CIPHER_TKIP:
1093 0 : entry = (uintptr_t)k->k_priv;
1094 0 : athn_reset_key(sc, entry);
1095 0 : athn_reset_key(sc, entry + 64);
1096 0 : break;
1097 : default:
1098 : /* Fallback to software crypto for other ciphers. */
1099 0 : ieee80211_delete_key(ic, ni, k);
1100 0 : }
1101 0 : }
1102 :
1103 : void
1104 0 : athn_led_init(struct athn_softc *sc)
1105 : {
1106 0 : struct athn_ops *ops = &sc->ops;
1107 :
1108 0 : ops->gpio_config_output(sc, sc->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1109 : /* LED off, active low. */
1110 0 : athn_set_led(sc, 0);
1111 0 : }
1112 :
1113 : void
1114 0 : athn_set_led(struct athn_softc *sc, int on)
1115 : {
1116 0 : struct athn_ops *ops = &sc->ops;
1117 :
1118 0 : sc->led_state = on;
1119 0 : ops->gpio_write(sc, sc->led_pin, !sc->led_state);
1120 0 : }
1121 :
1122 : #ifdef ATHN_BT_COEXISTENCE
1123 : void
1124 : athn_btcoex_init(struct athn_softc *sc)
1125 : {
1126 : struct athn_ops *ops = &sc->ops;
1127 : uint32_t reg;
1128 :
1129 : if (sc->flags & ATHN_FLAG_BTCOEX2WIRE) {
1130 : /* Connect bt_active to baseband. */
1131 : AR_CLRBITS(sc, sc->gpio_input_en_off,
1132 : AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
1133 : AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF);
1134 : AR_SETBITS(sc, sc->gpio_input_en_off,
1135 : AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
1136 :
1137 : reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
1138 : reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
1139 : AR_GPIO_BTACTIVE_PIN);
1140 : AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
1141 : AR_WRITE_BARRIER(sc);
1142 :
1143 : ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
1144 : } else { /* 3-wire. */
1145 : AR_SETBITS(sc, sc->gpio_input_en_off,
1146 : AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
1147 : AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
1148 :
1149 : reg = AR_READ(sc, AR_GPIO_INPUT_MUX1);
1150 : reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,
1151 : AR_GPIO_BTACTIVE_PIN);
1152 : reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,
1153 : AR_GPIO_BTPRIORITY_PIN);
1154 : AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
1155 : AR_WRITE_BARRIER(sc);
1156 :
1157 : ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN);
1158 : ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN);
1159 : }
1160 : }
1161 :
1162 : void
1163 : athn_btcoex_enable(struct athn_softc *sc)
1164 : {
1165 : struct athn_ops *ops = &sc->ops;
1166 : uint32_t reg;
1167 :
1168 : if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) {
1169 : AR_WRITE(sc, AR_BT_COEX_MODE,
1170 : SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) |
1171 : SM(AR_BT_PRIORITY_TIME, 2) |
1172 : SM(AR_BT_FIRST_SLOT_TIME, 5) |
1173 : SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) |
1174 : AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND |
1175 : AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY);
1176 : AR_WRITE(sc, AR_BT_COEX_WEIGHT,
1177 : SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) |
1178 : SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT));
1179 : AR_WRITE(sc, AR_BT_COEX_MODE2,
1180 : SM(AR_BT_BCN_MISS_THRESH, 50) |
1181 : AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT);
1182 :
1183 : AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE);
1184 : AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX);
1185 : AR_WRITE_BARRIER(sc);
1186 :
1187 : ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
1188 : AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
1189 :
1190 : } else { /* 2-wire. */
1191 : ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
1192 : AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
1193 : }
1194 : reg = AR_READ(sc, AR_GPIO_PDPU);
1195 : reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN * 2));
1196 : reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN * 2);
1197 : AR_WRITE(sc, AR_GPIO_PDPU, reg);
1198 : AR_WRITE_BARRIER(sc);
1199 :
1200 : /* Disable PCIe Active State Power Management (ASPM). */
1201 : if (sc->sc_disable_aspm != NULL)
1202 : sc->sc_disable_aspm(sc);
1203 :
1204 : /* XXX Start periodic timer. */
1205 : }
1206 :
1207 : void
1208 : athn_btcoex_disable(struct athn_softc *sc)
1209 : {
1210 : struct athn_ops *ops = &sc->ops;
1211 :
1212 : ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN, 0);
1213 :
1214 : ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN,
1215 : AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1216 :
1217 : if (sc->flags & ATHN_FLAG_BTCOEX3WIRE) {
1218 : AR_WRITE(sc, AR_BT_COEX_MODE,
1219 : SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET);
1220 : AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0);
1221 : AR_WRITE(sc, AR_BT_COEX_MODE2, 0);
1222 : /* XXX Stop periodic timer. */
1223 : }
1224 : AR_WRITE_BARRIER(sc);
1225 : /* XXX Restore ASPM setting? */
1226 : }
1227 : #endif
1228 :
1229 : void
1230 0 : athn_iter_calib(void *arg, struct ieee80211_node *ni)
1231 : {
1232 0 : struct athn_softc *sc = arg;
1233 0 : struct athn_node *an = (struct athn_node *)ni;
1234 :
1235 0 : if ((ni->ni_flags & IEEE80211_NODE_HT) == 0)
1236 0 : ieee80211_amrr_choose(&sc->amrr, ni, &an->amn);
1237 0 : }
1238 :
1239 : void
1240 0 : athn_calib_to(void *arg)
1241 : {
1242 : extern int ticks;
1243 0 : struct athn_softc *sc = arg;
1244 0 : struct athn_ops *ops = &sc->ops;
1245 0 : struct ieee80211com *ic = &sc->sc_ic;
1246 : int s;
1247 :
1248 0 : s = splnet();
1249 :
1250 : /* Do periodic (every 4 minutes) PA calibration. */
1251 0 : if (AR_SREV_9285_11_OR_LATER(sc) &&
1252 0 : !AR_SREV_9380_10_OR_LATER(sc) &&
1253 0 : (ticks - (sc->pa_calib_ticks + 240 * hz)) >= 0) {
1254 0 : sc->pa_calib_ticks = ticks;
1255 0 : if (AR_SREV_9271(sc))
1256 0 : ar9271_pa_calib(sc);
1257 : else
1258 0 : ar9285_pa_calib(sc);
1259 : }
1260 :
1261 : /* Do periodic (every 30 seconds) temperature compensation. */
1262 0 : if ((sc->flags & ATHN_FLAG_OLPC) &&
1263 0 : ticks >= sc->olpc_ticks + 30 * hz) {
1264 0 : sc->olpc_ticks = ticks;
1265 0 : ops->olpc_temp_compensation(sc);
1266 0 : }
1267 :
1268 : #ifdef notyet
1269 : /* XXX ANI. */
1270 : athn_ani_monitor(sc);
1271 :
1272 : ops->next_calib(sc);
1273 : #endif
1274 0 : if (ic->ic_fixed_rate == -1) {
1275 0 : if (ic->ic_opmode == IEEE80211_M_STA)
1276 0 : athn_iter_calib(sc, ic->ic_bss);
1277 : else
1278 0 : ieee80211_iterate_nodes(ic, athn_iter_calib, sc);
1279 : }
1280 0 : timeout_add_msec(&sc->calib_to, 500);
1281 0 : splx(s);
1282 0 : }
1283 :
1284 : int
1285 0 : athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
1286 : struct ieee80211_channel *extc)
1287 : {
1288 0 : struct athn_ops *ops = &sc->ops;
1289 : int error;
1290 :
1291 0 : if (AR_SREV_9380_10_OR_LATER(sc))
1292 0 : error = ar9003_init_calib(sc);
1293 0 : else if (AR_SREV_9285_10_OR_LATER(sc))
1294 0 : error = ar9285_init_calib(sc, c, extc);
1295 : else
1296 0 : error = ar5416_init_calib(sc, c, extc);
1297 0 : if (error != 0)
1298 0 : return (error);
1299 :
1300 0 : if (!AR_SREV_9380_10_OR_LATER(sc)) {
1301 : /* Do PA calibration. */
1302 0 : if (AR_SREV_9285_11_OR_LATER(sc)) {
1303 : extern int ticks;
1304 0 : sc->pa_calib_ticks = ticks;
1305 0 : if (AR_SREV_9271(sc))
1306 0 : ar9271_pa_calib(sc);
1307 : else
1308 0 : ar9285_pa_calib(sc);
1309 : }
1310 : /* Do noisefloor calibration. */
1311 0 : ops->noisefloor_calib(sc);
1312 0 : }
1313 0 : if (AR_SREV_9160_10_OR_LATER(sc)) {
1314 : /* Support IQ calibration. */
1315 0 : sc->sup_calib_mask = ATHN_CAL_IQ;
1316 0 : if (AR_SREV_9380_10_OR_LATER(sc)) {
1317 : /* Support temperature compensation calibration. */
1318 0 : sc->sup_calib_mask |= ATHN_CAL_TEMP;
1319 0 : } else if (IEEE80211_IS_CHAN_5GHZ(c) || extc != NULL) {
1320 : /*
1321 : * ADC gain calibration causes uplink throughput
1322 : * drops in HT40 mode on AR9287.
1323 : */
1324 0 : if (!AR_SREV_9287(sc)) {
1325 : /* Support ADC gain calibration. */
1326 0 : sc->sup_calib_mask |= ATHN_CAL_ADC_GAIN;
1327 0 : }
1328 : /* Support ADC DC offset calibration. */
1329 0 : sc->sup_calib_mask |= ATHN_CAL_ADC_DC;
1330 0 : }
1331 : }
1332 0 : return (0);
1333 0 : }
1334 :
1335 : /*
1336 : * Adaptive noise immunity.
1337 : */
1338 : int32_t
1339 0 : athn_ani_get_rssi(struct athn_softc *sc)
1340 : {
1341 0 : return (0); /* XXX */
1342 : }
1343 :
1344 : void
1345 0 : athn_ani_ofdm_err_trigger(struct athn_softc *sc)
1346 : {
1347 0 : struct athn_ani *ani = &sc->ani;
1348 0 : struct athn_ops *ops = &sc->ops;
1349 : int32_t rssi;
1350 :
1351 : /* First, raise noise immunity level, up to max. */
1352 0 : if (ani->noise_immunity_level < 4) {
1353 0 : ani->noise_immunity_level++;
1354 0 : ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
1355 0 : return;
1356 : }
1357 :
1358 : /* Then, raise our spur immunity level, up to max. */
1359 0 : if (ani->spur_immunity_level < 7) {
1360 0 : ani->spur_immunity_level++;
1361 0 : ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
1362 0 : return;
1363 : }
1364 :
1365 : #ifndef IEEE80211_STA_ONLY
1366 0 : if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
1367 0 : if (ani->firstep_level < 2) {
1368 0 : ani->firstep_level++;
1369 0 : ops->set_firstep_level(sc, ani->firstep_level);
1370 0 : }
1371 0 : return;
1372 : }
1373 : #endif
1374 0 : rssi = athn_ani_get_rssi(sc);
1375 0 : if (rssi > ATHN_ANI_RSSI_THR_HIGH) {
1376 : /*
1377 : * Beacon RSSI is high, turn off OFDM weak signal detection
1378 : * or raise first step level as last resort.
1379 : */
1380 0 : if (ani->ofdm_weak_signal) {
1381 0 : ani->ofdm_weak_signal = 0;
1382 0 : ops->disable_ofdm_weak_signal(sc);
1383 0 : ani->spur_immunity_level = 0;
1384 0 : ops->set_spur_immunity_level(sc, 0);
1385 0 : } else if (ani->firstep_level < 2) {
1386 0 : ani->firstep_level++;
1387 0 : ops->set_firstep_level(sc, ani->firstep_level);
1388 0 : }
1389 0 : } else if (rssi > ATHN_ANI_RSSI_THR_LOW) {
1390 : /*
1391 : * Beacon RSSI is in mid range, we need OFDM weak signal
1392 : * detection but we can raise first step level.
1393 : */
1394 0 : if (!ani->ofdm_weak_signal) {
1395 0 : ani->ofdm_weak_signal = 1;
1396 0 : ops->enable_ofdm_weak_signal(sc);
1397 0 : }
1398 0 : if (ani->firstep_level < 2) {
1399 0 : ani->firstep_level++;
1400 0 : ops->set_firstep_level(sc, ani->firstep_level);
1401 0 : }
1402 0 : } else if (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_bss->ni_chan)) {
1403 : /*
1404 : * Beacon RSSI is low, if in b/g mode, turn off OFDM weak
1405 : * signal detection and zero first step level to maximize
1406 : * CCK sensitivity.
1407 : */
1408 0 : if (ani->ofdm_weak_signal) {
1409 0 : ani->ofdm_weak_signal = 0;
1410 0 : ops->disable_ofdm_weak_signal(sc);
1411 0 : }
1412 0 : if (ani->firstep_level > 0) {
1413 0 : ani->firstep_level = 0;
1414 0 : ops->set_firstep_level(sc, 0);
1415 0 : }
1416 : }
1417 0 : }
1418 :
1419 : void
1420 0 : athn_ani_cck_err_trigger(struct athn_softc *sc)
1421 : {
1422 0 : struct athn_ani *ani = &sc->ani;
1423 0 : struct athn_ops *ops = &sc->ops;
1424 : int32_t rssi;
1425 :
1426 : /* Raise noise immunity level, up to max. */
1427 0 : if (ani->noise_immunity_level < 4) {
1428 0 : ani->noise_immunity_level++;
1429 0 : ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
1430 0 : return;
1431 : }
1432 :
1433 : #ifndef IEEE80211_STA_ONLY
1434 0 : if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
1435 0 : if (ani->firstep_level < 2) {
1436 0 : ani->firstep_level++;
1437 0 : ops->set_firstep_level(sc, ani->firstep_level);
1438 0 : }
1439 0 : return;
1440 : }
1441 : #endif
1442 0 : rssi = athn_ani_get_rssi(sc);
1443 0 : if (rssi > ATHN_ANI_RSSI_THR_LOW) {
1444 : /*
1445 : * Beacon RSSI is in mid or high range, raise first step
1446 : * level.
1447 : */
1448 0 : if (ani->firstep_level < 2) {
1449 0 : ani->firstep_level++;
1450 0 : ops->set_firstep_level(sc, ani->firstep_level);
1451 0 : }
1452 0 : } else if (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_bss->ni_chan)) {
1453 : /*
1454 : * Beacon RSSI is low, zero first step level to maximize
1455 : * CCK sensitivity.
1456 : */
1457 0 : if (ani->firstep_level > 0) {
1458 0 : ani->firstep_level = 0;
1459 0 : ops->set_firstep_level(sc, 0);
1460 0 : }
1461 : }
1462 0 : }
1463 :
1464 : void
1465 0 : athn_ani_lower_immunity(struct athn_softc *sc)
1466 : {
1467 0 : struct athn_ani *ani = &sc->ani;
1468 0 : struct athn_ops *ops = &sc->ops;
1469 : int32_t rssi;
1470 :
1471 : #ifndef IEEE80211_STA_ONLY
1472 0 : if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
1473 0 : if (ani->firstep_level > 0) {
1474 0 : ani->firstep_level--;
1475 0 : ops->set_firstep_level(sc, ani->firstep_level);
1476 0 : }
1477 0 : return;
1478 : }
1479 : #endif
1480 0 : rssi = athn_ani_get_rssi(sc);
1481 0 : if (rssi > ATHN_ANI_RSSI_THR_HIGH) {
1482 : /*
1483 : * Beacon RSSI is high, leave OFDM weak signal detection
1484 : * off or it may oscillate.
1485 : */
1486 0 : } else if (rssi > ATHN_ANI_RSSI_THR_LOW) {
1487 : /*
1488 : * Beacon RSSI is in mid range, turn on OFDM weak signal
1489 : * detection or lower first step level.
1490 : */
1491 0 : if (!ani->ofdm_weak_signal) {
1492 0 : ani->ofdm_weak_signal = 1;
1493 0 : ops->enable_ofdm_weak_signal(sc);
1494 0 : return;
1495 : }
1496 0 : if (ani->firstep_level > 0) {
1497 0 : ani->firstep_level--;
1498 0 : ops->set_firstep_level(sc, ani->firstep_level);
1499 0 : return;
1500 : }
1501 : } else {
1502 : /* Beacon RSSI is low, lower first step level. */
1503 0 : if (ani->firstep_level > 0) {
1504 0 : ani->firstep_level--;
1505 0 : ops->set_firstep_level(sc, ani->firstep_level);
1506 0 : return;
1507 : }
1508 : }
1509 : /*
1510 : * Lower spur immunity level down to zero, or if all else fails,
1511 : * lower noise immunity level down to zero.
1512 : */
1513 0 : if (ani->spur_immunity_level > 0) {
1514 0 : ani->spur_immunity_level--;
1515 0 : ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
1516 0 : } else if (ani->noise_immunity_level > 0) {
1517 0 : ani->noise_immunity_level--;
1518 0 : ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
1519 0 : }
1520 0 : }
1521 :
1522 : void
1523 0 : athn_ani_restart(struct athn_softc *sc)
1524 : {
1525 0 : struct athn_ani *ani = &sc->ani;
1526 :
1527 0 : AR_WRITE(sc, AR_PHY_ERR_1, 0);
1528 0 : AR_WRITE(sc, AR_PHY_ERR_2, 0);
1529 0 : AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1530 0 : AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1531 0 : AR_WRITE_BARRIER(sc);
1532 :
1533 0 : ani->listen_time = 0;
1534 0 : ani->ofdm_phy_err_count = 0;
1535 0 : ani->cck_phy_err_count = 0;
1536 0 : }
1537 :
1538 : void
1539 0 : athn_ani_monitor(struct athn_softc *sc)
1540 : {
1541 0 : struct athn_ani *ani = &sc->ani;
1542 : uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2;
1543 : int32_t cycdelta, txfdelta, rxfdelta;
1544 : int32_t listen_time;
1545 :
1546 0 : txfcnt = AR_READ(sc, AR_TFCNT); /* Tx frame count. */
1547 0 : rxfcnt = AR_READ(sc, AR_RFCNT); /* Rx frame count. */
1548 0 : cyccnt = AR_READ(sc, AR_CCCNT); /* Cycle count. */
1549 :
1550 0 : if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) {
1551 0 : cycdelta = cyccnt - ani->cyccnt;
1552 0 : txfdelta = txfcnt - ani->txfcnt;
1553 0 : rxfdelta = rxfcnt - ani->rxfcnt;
1554 :
1555 0 : listen_time = (cycdelta - txfdelta - rxfdelta) /
1556 0 : (athn_clock_rate(sc) * 1000);
1557 0 : } else
1558 : listen_time = 0;
1559 :
1560 0 : ani->cyccnt = cyccnt;
1561 0 : ani->txfcnt = txfcnt;
1562 0 : ani->rxfcnt = rxfcnt;
1563 :
1564 0 : if (listen_time < 0) {
1565 0 : athn_ani_restart(sc);
1566 0 : return;
1567 : }
1568 0 : ani->listen_time += listen_time;
1569 :
1570 0 : phy1 = AR_READ(sc, AR_PHY_ERR_1);
1571 0 : phy2 = AR_READ(sc, AR_PHY_ERR_2);
1572 :
1573 0 : if (phy1 < ani->ofdm_phy_err_base) {
1574 0 : AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base);
1575 0 : AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1576 0 : }
1577 0 : if (phy2 < ani->cck_phy_err_base) {
1578 0 : AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base);
1579 0 : AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1580 0 : }
1581 0 : if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) {
1582 0 : AR_WRITE_BARRIER(sc);
1583 0 : return;
1584 : }
1585 0 : ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base;
1586 0 : ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base;
1587 :
1588 0 : if (ani->listen_time > 5 * ATHN_ANI_PERIOD) {
1589 : /* Check to see if we need to lower immunity. */
1590 0 : if (ani->ofdm_phy_err_count <=
1591 0 : ani->listen_time * ani->ofdm_trig_low / 1000 &&
1592 0 : ani->cck_phy_err_count <=
1593 0 : ani->listen_time * ani->cck_trig_low / 1000)
1594 0 : athn_ani_lower_immunity(sc);
1595 0 : athn_ani_restart(sc);
1596 :
1597 0 : } else if (ani->listen_time > ATHN_ANI_PERIOD) {
1598 : /* Check to see if we need to raise immunity. */
1599 0 : if (ani->ofdm_phy_err_count >
1600 0 : ani->listen_time * ani->ofdm_trig_high / 1000) {
1601 0 : athn_ani_ofdm_err_trigger(sc);
1602 0 : athn_ani_restart(sc);
1603 0 : } else if (ani->cck_phy_err_count >
1604 0 : ani->listen_time * ani->cck_trig_high / 1000) {
1605 0 : athn_ani_cck_err_trigger(sc);
1606 0 : athn_ani_restart(sc);
1607 0 : }
1608 : }
1609 0 : }
1610 :
1611 : uint8_t
1612 0 : athn_chan2fbin(struct ieee80211_channel *c)
1613 : {
1614 0 : if (IEEE80211_IS_CHAN_2GHZ(c))
1615 0 : return (c->ic_freq - 2300);
1616 : else
1617 0 : return ((c->ic_freq - 4800) / 5);
1618 0 : }
1619 :
1620 : int
1621 0 : athn_interpolate(int x, int x1, int y1, int x2, int y2)
1622 : {
1623 0 : if (x1 == x2) /* Prevents division by zero. */
1624 0 : return (y1);
1625 : /* Linear interpolation. */
1626 0 : return (y1 + ((x - x1) * (y2 - y1)) / (x2 - x1));
1627 0 : }
1628 :
1629 : void
1630 0 : athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers,
1631 : int *lo, int *hi)
1632 : {
1633 : int i;
1634 :
1635 0 : for (i = 0; i < npiers; i++)
1636 0 : if (pierfreq[i] == AR_BCHAN_UNUSED ||
1637 0 : pierfreq[i] > fbin)
1638 : break;
1639 0 : *hi = i;
1640 0 : *lo = *hi - 1;
1641 0 : if (*lo == -1)
1642 0 : *lo = *hi;
1643 0 : else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED)
1644 0 : *hi = *lo;
1645 0 : }
1646 :
1647 : void
1648 0 : athn_init_dma(struct athn_softc *sc)
1649 : {
1650 : uint32_t reg;
1651 :
1652 0 : if (!AR_SREV_9380_10_OR_LATER(sc)) {
1653 : /* Set AHB not to do cacheline prefetches. */
1654 0 : AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1655 0 : }
1656 0 : reg = AR_READ(sc, AR_TXCFG);
1657 : /* Let MAC DMA reads be in 128-byte chunks. */
1658 0 : reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B);
1659 :
1660 : /* Set initial Tx trigger level. */
1661 0 : if (AR_SREV_9285(sc) || AR_SREV_9271(sc))
1662 0 : reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B);
1663 0 : else if (!AR_SREV_9380_10_OR_LATER(sc))
1664 0 : reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B);
1665 0 : AR_WRITE(sc, AR_TXCFG, reg);
1666 :
1667 : /* Let MAC DMA writes be in 128-byte chunks. */
1668 0 : reg = AR_READ(sc, AR_RXCFG);
1669 0 : reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B);
1670 0 : AR_WRITE(sc, AR_RXCFG, reg);
1671 :
1672 : /* Setup Rx FIFO threshold to hold off Tx activities. */
1673 0 : AR_WRITE(sc, AR_RXFIFO_CFG, 512);
1674 :
1675 : /* Reduce the number of entries in PCU TXBUF to avoid wrap around. */
1676 0 : if (AR_SREV_9285(sc)) {
1677 0 : AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
1678 : AR9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1679 0 : } else if (!AR_SREV_9271(sc)) {
1680 0 : AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
1681 : AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1682 0 : }
1683 0 : AR_WRITE_BARRIER(sc);
1684 :
1685 : /* Reset Tx status ring. */
1686 0 : if (AR_SREV_9380_10_OR_LATER(sc))
1687 0 : ar9003_reset_txsring(sc);
1688 0 : }
1689 :
1690 : void
1691 0 : athn_inc_tx_trigger_level(struct athn_softc *sc)
1692 : {
1693 : uint32_t reg, ftrig;
1694 :
1695 0 : reg = AR_READ(sc, AR_TXCFG);
1696 0 : ftrig = MS(reg, AR_TXCFG_FTRIG);
1697 : /*
1698 : * NB: The AR9285 and all single-stream parts have an issue that
1699 : * limits the size of the PCU Tx FIFO to 2KB instead of 4KB.
1700 : */
1701 0 : if (ftrig == ((AR_SREV_9285(sc) || AR_SREV_9271(sc)) ? 0x1f : 0x3f))
1702 0 : return; /* Already at max. */
1703 0 : reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1);
1704 0 : AR_WRITE(sc, AR_TXCFG, reg);
1705 0 : AR_WRITE_BARRIER(sc);
1706 0 : }
1707 :
1708 : int
1709 0 : athn_stop_rx_dma(struct athn_softc *sc)
1710 : {
1711 : int ntries;
1712 :
1713 0 : AR_WRITE(sc, AR_CR, AR_CR_RXD);
1714 : /* Wait for Rx enable bit to go low. */
1715 0 : for (ntries = 0; ntries < 100; ntries++) {
1716 0 : if (!(AR_READ(sc, AR_CR) & AR_CR_RXE))
1717 0 : return (0);
1718 0 : DELAY(100);
1719 : }
1720 : DPRINTF(("Rx DMA failed to stop\n"));
1721 0 : return (ETIMEDOUT);
1722 0 : }
1723 :
1724 : int
1725 0 : athn_rx_abort(struct athn_softc *sc)
1726 : {
1727 : int ntries;
1728 :
1729 0 : AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
1730 0 : for (ntries = 0; ntries < 1000; ntries++) {
1731 0 : if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE) == 0)
1732 0 : return (0);
1733 0 : DELAY(10);
1734 : }
1735 : DPRINTF(("Rx failed to go idle in 10ms\n"));
1736 0 : AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
1737 0 : AR_WRITE_BARRIER(sc);
1738 0 : return (ETIMEDOUT);
1739 0 : }
1740 :
1741 : void
1742 0 : athn_tx_reclaim(struct athn_softc *sc, int qid)
1743 : {
1744 0 : struct athn_txq *txq = &sc->txq[qid];
1745 : struct athn_tx_buf *bf;
1746 :
1747 : /* Reclaim all buffers queued in the specified Tx queue. */
1748 : /* NB: Tx DMA must be stopped. */
1749 0 : while ((bf = SIMPLEQ_FIRST(&txq->head)) != NULL) {
1750 0 : SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list);
1751 :
1752 0 : bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,
1753 : bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1754 0 : bus_dmamap_unload(sc->sc_dmat, bf->bf_map);
1755 0 : m_freem(bf->bf_m);
1756 0 : bf->bf_m = NULL;
1757 0 : bf->bf_ni = NULL; /* Nodes already freed! */
1758 :
1759 : /* Link Tx buffer back to global free list. */
1760 0 : SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list);
1761 : }
1762 0 : }
1763 :
1764 : int
1765 0 : athn_tx_pending(struct athn_softc *sc, int qid)
1766 : {
1767 0 : return (MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT) != 0 ||
1768 0 : (AR_READ(sc, AR_Q_TXE) & (1 << qid)) != 0);
1769 : }
1770 :
1771 : void
1772 0 : athn_stop_tx_dma(struct athn_softc *sc, int qid)
1773 : {
1774 : uint32_t tsflo;
1775 : int ntries, i;
1776 :
1777 0 : AR_WRITE(sc, AR_Q_TXD, 1 << qid);
1778 0 : for (ntries = 0; ntries < 40; ntries++) {
1779 0 : if (!athn_tx_pending(sc, qid))
1780 : break;
1781 0 : DELAY(100);
1782 : }
1783 0 : if (ntries == 40) {
1784 0 : for (i = 0; i < 2; i++) {
1785 0 : tsflo = AR_READ(sc, AR_TSF_L32) / 1024;
1786 0 : AR_WRITE(sc, AR_QUIET2,
1787 : SM(AR_QUIET2_QUIET_DUR, 10));
1788 0 : AR_WRITE(sc, AR_QUIET_PERIOD, 100);
1789 0 : AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo);
1790 0 : AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
1791 0 : if (AR_READ(sc, AR_TSF_L32) / 1024 == tsflo)
1792 : break;
1793 : }
1794 0 : AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
1795 0 : AR_WRITE_BARRIER(sc);
1796 0 : DELAY(200);
1797 0 : AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
1798 0 : AR_WRITE_BARRIER(sc);
1799 :
1800 0 : for (ntries = 0; ntries < 40; ntries++) {
1801 0 : if (!athn_tx_pending(sc, qid))
1802 : break;
1803 0 : DELAY(100);
1804 : }
1805 :
1806 0 : AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
1807 0 : }
1808 0 : AR_WRITE(sc, AR_Q_TXD, 0);
1809 0 : AR_WRITE_BARRIER(sc);
1810 0 : }
1811 :
1812 : int
1813 0 : athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags)
1814 : {
1815 0 : struct ieee80211com *ic = &sc->sc_ic;
1816 : #define divround(a, b) (((a) + (b) - 1) / (b))
1817 : int txtime;
1818 :
1819 0 : if (athn_rates[ridx].hwrate & 0x80) { /* MCS */
1820 : /* Assumes a 20MHz channel, HT-mixed frame format, no STBC. */
1821 : txtime = 8 + 8 + 4 + 4 + 4 * 4 + 8 /* HT PLCP */
1822 0 : + 4 * ((8 * len + 16 + 6) / (athn_rates[ridx].rate * 2));
1823 0 : if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan))
1824 0 : txtime += 6; /* aSignalExtension */
1825 0 : } else if (athn_rates[ridx].phy == IEEE80211_T_OFDM) {
1826 0 : txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate);
1827 : /* SIFS is 10us for 11g but Signal Extension adds 6us. */
1828 0 : txtime = 16 + 4 + 4 * txtime + 16;
1829 0 : } else {
1830 0 : txtime = divround(16 * len, athn_rates[ridx].rate);
1831 0 : if (ridx != ATHN_RIDX_CCK1 && (flags & IEEE80211_F_SHPREAMBLE))
1832 0 : txtime += 72 + 24;
1833 : else
1834 0 : txtime += 144 + 48;
1835 0 : txtime += 10; /* 10us SIFS. */
1836 : }
1837 0 : return (txtime);
1838 : #undef divround
1839 : }
1840 :
1841 : void
1842 0 : athn_init_tx_queues(struct athn_softc *sc)
1843 : {
1844 : int qid;
1845 :
1846 0 : for (qid = 0; qid < ATHN_QID_COUNT; qid++) {
1847 0 : SIMPLEQ_INIT(&sc->txq[qid].head);
1848 0 : sc->txq[qid].lastds = NULL;
1849 0 : sc->txq[qid].wait = NULL;
1850 0 : sc->txq[qid].queued = 0;
1851 :
1852 0 : AR_WRITE(sc, AR_DRETRY_LIMIT(qid),
1853 : SM(AR_D_RETRY_LIMIT_STA_SH, 32) |
1854 : SM(AR_D_RETRY_LIMIT_STA_LG, 32) |
1855 : SM(AR_D_RETRY_LIMIT_FR_SH, 10));
1856 0 : AR_WRITE(sc, AR_QMISC(qid),
1857 : AR_Q_MISC_DCU_EARLY_TERM_REQ);
1858 0 : AR_WRITE(sc, AR_DMISC(qid),
1859 : SM(AR_D_MISC_BKOFF_THRESH, 2) |
1860 : AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN);
1861 : }
1862 :
1863 : /* Init beacon queue. */
1864 0 : AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON),
1865 : AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE |
1866 : AR_Q_MISC_CBR_INCR_DIS1);
1867 0 : AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON),
1868 : SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,
1869 : AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) |
1870 : AR_D_MISC_BEACON_USE |
1871 : AR_D_MISC_POST_FR_BKOFF_DIS);
1872 0 : AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON),
1873 : SM(AR_D_LCL_IFS_CWMIN, 0) |
1874 : SM(AR_D_LCL_IFS_CWMAX, 0) |
1875 : SM(AR_D_LCL_IFS_AIFS, 1));
1876 :
1877 : /* Init CAB (Content After Beacon) queue. */
1878 0 : AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB),
1879 : AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 |
1880 : AR_Q_MISC_CBR_INCR_DIS0);
1881 0 : AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB),
1882 : SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,
1883 : AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL));
1884 :
1885 : /* Init PS-Poll queue. */
1886 0 : AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL),
1887 : AR_Q_MISC_CBR_INCR_DIS1);
1888 :
1889 : /* Init UAPSD queue. */
1890 0 : AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD),
1891 : AR_D_MISC_POST_FR_BKOFF_DIS);
1892 :
1893 0 : if (AR_SREV_9380_10_OR_LATER(sc)) {
1894 : /* Enable MAC descriptor CRC check. */
1895 0 : AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
1896 0 : }
1897 : /* Enable DESC interrupts for all Tx queues. */
1898 0 : AR_WRITE(sc, AR_IMR_S0, 0x00ff0000);
1899 : /* Enable EOL interrupts for all Tx queues except UAPSD. */
1900 0 : AR_WRITE(sc, AR_IMR_S1, 0x00df0000);
1901 0 : AR_WRITE_BARRIER(sc);
1902 0 : }
1903 :
1904 : void
1905 0 : athn_set_sta_timers(struct athn_softc *sc)
1906 : {
1907 0 : struct ieee80211com *ic = &sc->sc_ic;
1908 : uint32_t tsfhi, tsflo, tsftu, reg;
1909 : uint32_t intval, next_tbtt, next_dtim;
1910 : int dtim_period, dtim_count, rem_dtim_count;
1911 :
1912 0 : tsfhi = AR_READ(sc, AR_TSF_U32);
1913 0 : tsflo = AR_READ(sc, AR_TSF_L32);
1914 0 : tsftu = AR_TSF_TO_TU(tsfhi, tsflo) + AR_FUDGE;
1915 :
1916 : /* Beacon interval in TU. */
1917 0 : intval = ic->ic_bss->ni_intval;
1918 :
1919 0 : next_tbtt = roundup(tsftu, intval);
1920 : #ifdef notyet
1921 : dtim_period = ic->ic_dtim_period;
1922 : if (dtim_period <= 0)
1923 : #endif
1924 : dtim_period = 1; /* Assume all TIMs are DTIMs. */
1925 :
1926 : #ifdef notyet
1927 : dtim_count = ic->ic_dtim_count;
1928 : if (dtim_count >= dtim_period) /* Should not happen. */
1929 : #endif
1930 : dtim_count = 0; /* Assume last TIM was a DTIM. */
1931 :
1932 : /* Compute number of remaining TIMs until next DTIM. */
1933 : rem_dtim_count = 0; /* XXX */
1934 : next_dtim = next_tbtt + rem_dtim_count * intval;
1935 :
1936 0 : AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
1937 0 : AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
1938 0 : AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
1939 :
1940 : /*
1941 : * Set the number of consecutive beacons to miss before raising
1942 : * a BMISS interrupt to 10.
1943 : */
1944 0 : reg = AR_READ(sc, AR_RSSI_THR);
1945 0 : reg = RW(reg, AR_RSSI_THR_BM_THR, 10);
1946 0 : AR_WRITE(sc, AR_RSSI_THR, reg);
1947 :
1948 0 : AR_WRITE(sc, AR_NEXT_DTIM,
1949 : (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU);
1950 0 : AR_WRITE(sc, AR_NEXT_TIM,
1951 : (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU);
1952 :
1953 : /* CAB timeout is in 1/8 TU. */
1954 0 : AR_WRITE(sc, AR_SLEEP1,
1955 : SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) |
1956 : AR_SLEEP1_ASSUME_DTIM);
1957 0 : AR_WRITE(sc, AR_SLEEP2,
1958 : SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL));
1959 :
1960 0 : AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU);
1961 0 : AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU);
1962 :
1963 0 : AR_SETBITS(sc, AR_TIMER_MODE,
1964 : AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN);
1965 :
1966 : /* Set TSF out-of-range threshold (fixed at 16k us). */
1967 0 : AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240);
1968 :
1969 0 : AR_WRITE_BARRIER(sc);
1970 0 : }
1971 :
1972 : #ifndef IEEE80211_STA_ONLY
1973 : void
1974 0 : athn_set_hostap_timers(struct athn_softc *sc)
1975 : {
1976 0 : struct ieee80211com *ic = &sc->sc_ic;
1977 : uint32_t intval, next_tbtt;
1978 :
1979 : /* Beacon interval in TU. */
1980 0 : intval = ic->ic_bss->ni_intval;
1981 : next_tbtt = intval;
1982 :
1983 0 : AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
1984 0 : AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT,
1985 : (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU);
1986 0 : AR_WRITE(sc, AR_NEXT_CFP,
1987 : (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU);
1988 :
1989 0 : AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
1990 0 : AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
1991 0 : AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU);
1992 0 : AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU);
1993 :
1994 0 : AR_WRITE(sc, AR_TIMER_MODE,
1995 : AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN);
1996 :
1997 0 : AR_WRITE_BARRIER(sc);
1998 0 : }
1999 : #endif
2000 :
2001 : void
2002 0 : athn_set_opmode(struct athn_softc *sc)
2003 : {
2004 : uint32_t reg;
2005 :
2006 0 : switch (sc->sc_ic.ic_opmode) {
2007 : #ifndef IEEE80211_STA_ONLY
2008 : case IEEE80211_M_HOSTAP:
2009 0 : reg = AR_READ(sc, AR_STA_ID1);
2010 0 : reg &= ~AR_STA_ID1_ADHOC;
2011 0 : reg |= AR_STA_ID1_STA_AP | AR_STA_ID1_KSRCH_MODE;
2012 0 : AR_WRITE(sc, AR_STA_ID1, reg);
2013 :
2014 0 : AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
2015 0 : break;
2016 : case IEEE80211_M_IBSS:
2017 : case IEEE80211_M_AHDEMO:
2018 0 : reg = AR_READ(sc, AR_STA_ID1);
2019 0 : reg &= ~AR_STA_ID1_STA_AP;
2020 0 : reg |= AR_STA_ID1_ADHOC | AR_STA_ID1_KSRCH_MODE;
2021 0 : AR_WRITE(sc, AR_STA_ID1, reg);
2022 :
2023 0 : AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
2024 0 : break;
2025 : #endif
2026 : default:
2027 0 : reg = AR_READ(sc, AR_STA_ID1);
2028 0 : reg &= ~(AR_STA_ID1_ADHOC | AR_STA_ID1_STA_AP);
2029 0 : reg |= AR_STA_ID1_KSRCH_MODE;
2030 0 : AR_WRITE(sc, AR_STA_ID1, reg);
2031 0 : break;
2032 : }
2033 0 : AR_WRITE_BARRIER(sc);
2034 0 : }
2035 :
2036 : void
2037 0 : athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni)
2038 : {
2039 0 : const uint8_t *bssid = ni->ni_bssid;
2040 :
2041 0 : AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0]));
2042 0 : AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) |
2043 : SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd)));
2044 0 : AR_WRITE_BARRIER(sc);
2045 0 : }
2046 :
2047 : void
2048 0 : athn_enable_interrupts(struct athn_softc *sc)
2049 : {
2050 : uint32_t mask2;
2051 :
2052 0 : athn_disable_interrupts(sc); /* XXX */
2053 :
2054 0 : AR_WRITE(sc, AR_IMR, sc->imask);
2055 :
2056 0 : mask2 = AR_READ(sc, AR_IMR_S2);
2057 0 : mask2 &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2058 : AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR);
2059 0 : mask2 |= AR_IMR_S2_GTT | AR_IMR_S2_CST;
2060 0 : AR_WRITE(sc, AR_IMR_S2, mask2);
2061 :
2062 0 : AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2063 :
2064 0 : AR_WRITE(sc, AR_IER, AR_IER_ENABLE);
2065 :
2066 0 : AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
2067 0 : AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2068 :
2069 0 : AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync);
2070 0 : AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->isync);
2071 0 : AR_WRITE_BARRIER(sc);
2072 0 : }
2073 :
2074 : void
2075 0 : athn_disable_interrupts(struct athn_softc *sc)
2076 : {
2077 0 : AR_WRITE(sc, AR_IER, 0);
2078 0 : (void)AR_READ(sc, AR_IER);
2079 :
2080 0 : AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0);
2081 0 : (void)AR_READ(sc, AR_INTR_ASYNC_ENABLE);
2082 :
2083 0 : AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
2084 0 : (void)AR_READ(sc, AR_INTR_SYNC_ENABLE);
2085 :
2086 0 : AR_WRITE(sc, AR_IMR, 0);
2087 :
2088 0 : AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM |
2089 : AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2090 : AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2091 :
2092 0 : AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2093 0 : AR_WRITE_BARRIER(sc);
2094 0 : }
2095 :
2096 : void
2097 0 : athn_init_qos(struct athn_softc *sc)
2098 : {
2099 : /* Initialize QoS settings. */
2100 0 : AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa);
2101 0 : AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210);
2102 0 : AR_WRITE(sc, AR_QOS_NO_ACK,
2103 : SM(AR_QOS_NO_ACK_TWO_BIT, 2) |
2104 : SM(AR_QOS_NO_ACK_BIT_OFF, 5) |
2105 : SM(AR_QOS_NO_ACK_BYTE_OFF, 0));
2106 0 : AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL);
2107 : /* Initialize TXOP for all TIDs. */
2108 0 : AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff);
2109 0 : AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff);
2110 0 : AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff);
2111 0 : AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff);
2112 0 : AR_WRITE_BARRIER(sc);
2113 0 : }
2114 :
2115 : int
2116 0 : athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
2117 : struct ieee80211_channel *extc, int init)
2118 : {
2119 0 : struct ieee80211com *ic = &sc->sc_ic;
2120 0 : struct athn_ops *ops = &sc->ops;
2121 : uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi;
2122 : int i, error;
2123 :
2124 : /* XXX not if already awake */
2125 0 : if ((error = athn_set_power_awake(sc)) != 0) {
2126 0 : printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname);
2127 0 : return (error);
2128 : }
2129 :
2130 : /* Preserve the antenna on a channel switch. */
2131 0 : if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)) == 0)
2132 : def_ant = 1;
2133 : /* Preserve other registers. */
2134 0 : sta_id1 = AR_READ(sc, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2135 0 : cfg_led = AR_READ(sc, AR_CFG_LED) & (AR_CFG_LED_ASSOC_CTL_M |
2136 : AR_CFG_LED_MODE_SEL_M | AR_CFG_LED_BLINK_THRESH_SEL_M |
2137 : AR_CFG_LED_BLINK_SLOW);
2138 :
2139 : /* Mark PHY as inactive. */
2140 0 : ops->disable_phy(sc);
2141 :
2142 0 : if (init && AR_SREV_9271(sc)) {
2143 0 : AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
2144 : AR9271_RADIO_RF_RST);
2145 0 : DELAY(50);
2146 0 : }
2147 0 : if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) {
2148 : /* Save TSF before it gets cleared. */
2149 0 : tsfhi = AR_READ(sc, AR_TSF_U32);
2150 0 : tsflo = AR_READ(sc, AR_TSF_L32);
2151 :
2152 : /* NB: RTC reset clears TSF. */
2153 0 : error = athn_reset_power_on(sc);
2154 0 : } else
2155 0 : error = athn_reset(sc, 0);
2156 0 : if (error != 0) {
2157 0 : printf("%s: could not reset chip (error=%d)\n",
2158 0 : sc->sc_dev.dv_xname, error);
2159 0 : return (error);
2160 : }
2161 :
2162 : /* XXX not if already awake */
2163 0 : if ((error = athn_set_power_awake(sc)) != 0) {
2164 0 : printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname);
2165 0 : return (error);
2166 : }
2167 :
2168 0 : athn_init_pll(sc, c);
2169 0 : ops->set_rf_mode(sc, c);
2170 :
2171 0 : if (sc->flags & ATHN_FLAG_RFSILENT) {
2172 : /* Check that the radio is not disabled by hardware switch. */
2173 0 : reg = ops->gpio_read(sc, sc->rfsilent_pin);
2174 0 : if (sc->flags & ATHN_FLAG_RFSILENT_REVERSED)
2175 0 : reg = !reg;
2176 0 : if (!reg) {
2177 0 : printf("%s: radio is disabled by hardware switch\n",
2178 0 : sc->sc_dev.dv_xname);
2179 0 : return (EPERM);
2180 : }
2181 : }
2182 0 : if (init && AR_SREV_9271(sc)) {
2183 0 : AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
2184 : AR9271_GATE_MAC_CTL);
2185 0 : DELAY(50);
2186 0 : }
2187 0 : if (AR_SREV_9280(sc) && (sc->flags & ATHN_FLAG_OLPC)) {
2188 : /* Restore TSF if it got cleared. */
2189 0 : AR_WRITE(sc, AR_TSF_L32, tsflo);
2190 0 : AR_WRITE(sc, AR_TSF_U32, tsfhi);
2191 0 : }
2192 :
2193 0 : if (AR_SREV_9280_10_OR_LATER(sc))
2194 0 : AR_SETBITS(sc, sc->gpio_input_en_off, AR_GPIO_JTAG_DISABLE);
2195 :
2196 0 : if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
2197 0 : ar9287_1_3_enable_async_fifo(sc);
2198 :
2199 : /* Write init values to hardware. */
2200 0 : ops->hw_init(sc, c, extc);
2201 :
2202 : /*
2203 : * Only >=AR9280 2.0 parts are capable of encrypting unicast
2204 : * management frames using CCMP.
2205 : */
2206 0 : if (AR_SREV_9280_20_OR_LATER(sc)) {
2207 0 : reg = AR_READ(sc, AR_AES_MUTE_MASK1);
2208 : /* Do not mask the subtype field in management frames. */
2209 0 : reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff);
2210 0 : reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,
2211 : ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT |
2212 : IEEE80211_FC1_MORE_DATA));
2213 0 : AR_WRITE(sc, AR_AES_MUTE_MASK1, reg);
2214 0 : } else if (AR_SREV_9160_10_OR_LATER(sc)) {
2215 : /* Disable hardware crypto for management frames. */
2216 0 : AR_CLRBITS(sc, AR_PCU_MISC_MODE2,
2217 : AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2218 0 : AR_SETBITS(sc, AR_PCU_MISC_MODE2,
2219 : AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2220 0 : }
2221 :
2222 0 : if (ic->ic_curmode != IEEE80211_MODE_11B)
2223 0 : ops->set_delta_slope(sc, c, extc);
2224 :
2225 0 : ops->spur_mitigate(sc, c, extc);
2226 0 : ops->init_from_rom(sc, c, extc);
2227 :
2228 : /* XXX */
2229 0 : AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0]));
2230 0 : AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) |
2231 : sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE);
2232 :
2233 0 : athn_set_opmode(sc);
2234 :
2235 0 : AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
2236 0 : AR_WRITE(sc, AR_BSSMSKU, 0xffff);
2237 :
2238 : /* Restore previous antenna. */
2239 0 : AR_WRITE(sc, AR_DEF_ANTENNA, def_ant);
2240 :
2241 0 : AR_WRITE(sc, AR_BSS_ID0, 0);
2242 0 : AR_WRITE(sc, AR_BSS_ID1, 0);
2243 :
2244 0 : AR_WRITE(sc, AR_ISR, 0xffffffff);
2245 :
2246 0 : AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7));
2247 :
2248 0 : if ((error = ops->set_synth(sc, c, extc)) != 0) {
2249 0 : printf("%s: could not set channel\n", sc->sc_dev.dv_xname);
2250 0 : return (error);
2251 : }
2252 0 : sc->curchan = c;
2253 0 : sc->curchanext = extc;
2254 :
2255 0 : for (i = 0; i < AR_NUM_DCU; i++)
2256 0 : AR_WRITE(sc, AR_DQCUMASK(i), 1 << i);
2257 :
2258 0 : athn_init_tx_queues(sc);
2259 :
2260 : /* Initialize interrupt mask. */
2261 0 : sc->imask =
2262 : AR_IMR_TXDESC | AR_IMR_TXEOL |
2263 : AR_IMR_RXERR | AR_IMR_RXEOL | AR_IMR_RXORN |
2264 : AR_IMR_RXMINTR | AR_IMR_RXINTM |
2265 : AR_IMR_GENTMR | AR_IMR_BCNMISC;
2266 0 : if (AR_SREV_9380_10_OR_LATER(sc))
2267 0 : sc->imask |= AR_IMR_RXERR | AR_IMR_HP_RXOK;
2268 : #ifndef IEEE80211_STA_ONLY
2269 : if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP)
2270 : sc->imask |= AR_IMR_MIB;
2271 : #endif
2272 0 : AR_WRITE(sc, AR_IMR, sc->imask);
2273 0 : AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT);
2274 0 : AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
2275 0 : sc->isync = AR_INTR_SYNC_DEFAULT;
2276 0 : if (sc->flags & ATHN_FLAG_RFSILENT)
2277 0 : sc->isync |= AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin);
2278 0 : AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync);
2279 0 : AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
2280 0 : if (AR_SREV_9380_10_OR_LATER(sc)) {
2281 0 : AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
2282 0 : AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
2283 0 : AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0);
2284 0 : AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0);
2285 0 : }
2286 :
2287 0 : athn_init_qos(sc);
2288 :
2289 0 : AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA);
2290 :
2291 0 : if (AR_SREV_9287_13_OR_LATER(sc) && !AR_SREV_9380_10_OR_LATER(sc))
2292 0 : ar9287_1_3_setup_async_fifo(sc);
2293 :
2294 : /* Disable sequence number generation in hardware. */
2295 0 : AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2296 :
2297 0 : athn_init_dma(sc);
2298 :
2299 : /* Program observation bus to see MAC interrupts. */
2300 0 : AR_WRITE(sc, sc->obs_off, 8);
2301 :
2302 : /* Setup Rx interrupt mitigation. */
2303 0 : AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500));
2304 :
2305 0 : ops->init_baseband(sc);
2306 :
2307 0 : if ((error = athn_init_calib(sc, c, extc)) != 0) {
2308 0 : printf("%s: could not initialize calibration\n",
2309 0 : sc->sc_dev.dv_xname);
2310 0 : return (error);
2311 : }
2312 :
2313 0 : ops->set_rxchains(sc);
2314 :
2315 0 : AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ);
2316 :
2317 0 : if (sc->flags & ATHN_FLAG_USB) {
2318 0 : if (AR_SREV_9271(sc))
2319 0 : AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2320 : else
2321 0 : AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2322 : }
2323 : #if BYTE_ORDER == BIG_ENDIAN
2324 : else {
2325 : /* Default is LE, turn on swapping for BE. */
2326 : AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2327 : }
2328 : #endif
2329 0 : AR_WRITE_BARRIER(sc);
2330 :
2331 0 : return (0);
2332 0 : }
2333 :
2334 : struct ieee80211_node *
2335 0 : athn_node_alloc(struct ieee80211com *ic)
2336 : {
2337 : struct athn_node *an;
2338 :
2339 0 : an = malloc(sizeof(struct athn_node), M_DEVBUF, M_NOWAIT | M_ZERO);
2340 0 : if (an && (ic->ic_flags & IEEE80211_F_HTON))
2341 0 : ieee80211_mira_node_init(&an->mn);
2342 0 : return (struct ieee80211_node *)an;
2343 : }
2344 :
2345 : void
2346 0 : athn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew)
2347 : {
2348 0 : struct athn_softc *sc = ic->ic_softc;
2349 0 : struct athn_node *an = (void *)ni;
2350 0 : struct ieee80211_rateset *rs = &ni->ni_rates;
2351 : uint8_t rate;
2352 : int ridx, i, j;
2353 :
2354 0 : if ((ni->ni_flags & IEEE80211_NODE_HT) == 0)
2355 0 : ieee80211_amrr_node_init(&sc->amrr, &an->amn);
2356 0 : else if (ic->ic_opmode == IEEE80211_M_STA)
2357 0 : ieee80211_mira_node_init(&an->mn);
2358 :
2359 : /* Start at lowest available bit-rate, AMRR will raise. */
2360 0 : ni->ni_txrate = 0;
2361 :
2362 0 : for (i = 0; i < rs->rs_nrates; i++) {
2363 0 : rate = rs->rs_rates[i] & IEEE80211_RATE_VAL;
2364 :
2365 : /* Map 802.11 rate to HW rate index. */
2366 0 : for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++)
2367 0 : if (athn_rates[ridx].rate == rate)
2368 : break;
2369 0 : an->ridx[i] = ridx;
2370 : DPRINTFN(2, ("rate %d index %d\n", rate, ridx));
2371 :
2372 : /* Compute fallback rate for retries. */
2373 0 : an->fallback[i] = i;
2374 0 : for (j = i - 1; j >= 0; j--) {
2375 0 : if (athn_rates[an->ridx[j]].phy ==
2376 0 : athn_rates[an->ridx[i]].phy) {
2377 0 : an->fallback[i] = j;
2378 0 : break;
2379 : }
2380 : }
2381 : DPRINTFN(2, ("%d fallbacks to %d\n", i, an->fallback[i]));
2382 : }
2383 :
2384 : /* In 11n mode, start at lowest available bit-rate, MiRA will raise. */
2385 0 : ni->ni_txmcs = 0;
2386 :
2387 0 : for (i = 0; i <= ATHN_MCS_MAX; i++) {
2388 : /* Map MCS index to HW rate index. */
2389 0 : ridx = ATHN_NUM_LEGACY_RATES + i;
2390 0 : an->ridx[ridx] = ATHN_RIDX_MCS0 + i;
2391 :
2392 : DPRINTFN(2, ("mcs %d index %d ", i, ridx));
2393 : /* Compute fallback rate for retries. */
2394 0 : if (i == 0 || i == 8) {
2395 : /* MCS 0 and 8 fall back to the lowest legacy rate. */
2396 0 : if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan))
2397 0 : an->fallback[ridx] = ATHN_RIDX_OFDM6;
2398 : else
2399 0 : an->fallback[ridx] = ATHN_RIDX_CCK1;
2400 : } else {
2401 : /* Other MCS fall back to next supported lower MCS. */
2402 0 : an->fallback[ridx] = ATHN_NUM_LEGACY_RATES + i;
2403 0 : for (j = i - 1; j >= 0; j--) {
2404 0 : if (!isset(ni->ni_rxmcs, j))
2405 : continue;
2406 0 : an->fallback[ridx] = ATHN_NUM_LEGACY_RATES + j;
2407 0 : break;
2408 : }
2409 : }
2410 : DPRINTFN(2, (" fallback to %d\n", an->fallback[ridx]));
2411 : }
2412 0 : }
2413 :
2414 : #ifndef IEEE80211_STA_ONLY
2415 : void
2416 0 : athn_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni)
2417 : {
2418 0 : struct athn_node *an = (void *)ni;
2419 0 : if (ic->ic_flags & IEEE80211_F_HTON)
2420 0 : ieee80211_mira_cancel_timeouts(&an->mn);
2421 0 : }
2422 : #endif
2423 :
2424 : int
2425 0 : athn_media_change(struct ifnet *ifp)
2426 : {
2427 0 : struct athn_softc *sc = ifp->if_softc;
2428 0 : struct ieee80211com *ic = &sc->sc_ic;
2429 : uint8_t rate, ridx;
2430 : int error;
2431 :
2432 0 : error = ieee80211_media_change(ifp);
2433 0 : if (error != ENETRESET)
2434 0 : return (error);
2435 :
2436 0 : if (ic->ic_fixed_rate != -1) {
2437 0 : rate = ic->ic_sup_rates[ic->ic_curmode].
2438 0 : rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL;
2439 : /* Map 802.11 rate to HW rate index. */
2440 0 : for (ridx = 0; ridx <= ATHN_RIDX_MAX; ridx++)
2441 0 : if (athn_rates[ridx].rate == rate)
2442 : break;
2443 0 : sc->fixed_ridx = ridx;
2444 0 : }
2445 0 : if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
2446 : (IFF_UP | IFF_RUNNING)) {
2447 0 : athn_stop(ifp, 0);
2448 0 : error = athn_init(ifp);
2449 0 : }
2450 0 : return (error);
2451 0 : }
2452 :
2453 : void
2454 0 : athn_next_scan(void *arg)
2455 : {
2456 0 : struct athn_softc *sc = arg;
2457 0 : struct ieee80211com *ic = &sc->sc_ic;
2458 : int s;
2459 :
2460 0 : s = splnet();
2461 0 : if (ic->ic_state == IEEE80211_S_SCAN)
2462 0 : ieee80211_next_scan(&ic->ic_if);
2463 0 : splx(s);
2464 0 : }
2465 :
2466 : void
2467 0 : athn_iter_mira_delete(void *arg, struct ieee80211_node *ni)
2468 : {
2469 0 : struct athn_node *an = (struct athn_node *)ni;
2470 0 : ieee80211_mira_cancel_timeouts(&an->mn);
2471 0 : }
2472 :
2473 : /* Delete pending timeouts managed by MiRA. */
2474 : void
2475 0 : athn_delete_mira_nodes(struct athn_softc *sc)
2476 : {
2477 0 : struct ieee80211com *ic = &sc->sc_ic;
2478 :
2479 0 : if (ic->ic_opmode == IEEE80211_M_STA) {
2480 0 : struct athn_node *an = (struct athn_node *)ic->ic_bss;
2481 0 : ieee80211_mira_cancel_timeouts(&an->mn);
2482 0 : } else
2483 0 : ieee80211_iterate_nodes(ic, athn_iter_mira_delete, sc);
2484 0 : }
2485 :
2486 : int
2487 0 : athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
2488 : {
2489 0 : struct ifnet *ifp = &ic->ic_if;
2490 0 : struct athn_softc *sc = ifp->if_softc;
2491 : uint32_t reg;
2492 : int error;
2493 :
2494 0 : timeout_del(&sc->calib_to);
2495 :
2496 0 : if ((ic->ic_flags & IEEE80211_F_HTON) &&
2497 0 : ic->ic_state == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN)
2498 0 : athn_delete_mira_nodes(sc);
2499 :
2500 0 : switch (nstate) {
2501 : case IEEE80211_S_INIT:
2502 0 : athn_set_led(sc, 0);
2503 0 : break;
2504 : case IEEE80211_S_SCAN:
2505 : /* Make the LED blink while scanning. */
2506 0 : athn_set_led(sc, !sc->led_state);
2507 0 : error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL);
2508 0 : if (error != 0)
2509 0 : return (error);
2510 0 : timeout_add_msec(&sc->scan_to, 200);
2511 0 : break;
2512 : case IEEE80211_S_AUTH:
2513 0 : athn_set_led(sc, 0);
2514 0 : error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL);
2515 0 : if (error != 0)
2516 0 : return (error);
2517 : break;
2518 : case IEEE80211_S_ASSOC:
2519 : break;
2520 : case IEEE80211_S_RUN:
2521 0 : athn_set_led(sc, 1);
2522 :
2523 0 : if (ic->ic_opmode == IEEE80211_M_MONITOR)
2524 : break;
2525 :
2526 : /* Fake a join to initialize the Tx rate. */
2527 0 : athn_newassoc(ic, ic->ic_bss, 1);
2528 :
2529 0 : athn_set_bss(sc, ic->ic_bss);
2530 0 : athn_disable_interrupts(sc);
2531 : #ifndef IEEE80211_STA_ONLY
2532 0 : if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2533 0 : athn_set_hostap_timers(sc);
2534 : /* Enable software beacon alert interrupts. */
2535 0 : sc->imask |= AR_IMR_SWBA;
2536 0 : } else
2537 : #endif
2538 : {
2539 0 : athn_set_sta_timers(sc);
2540 : /* Enable beacon miss interrupts. */
2541 0 : sc->imask |= AR_IMR_BMISS;
2542 :
2543 : /* Stop receiving beacons from other BSS. */
2544 0 : reg = AR_READ(sc, AR_RX_FILTER);
2545 0 : reg = (reg & ~AR_RX_FILTER_BEACON) |
2546 : AR_RX_FILTER_MYBEACON;
2547 0 : AR_WRITE(sc, AR_RX_FILTER, reg);
2548 0 : AR_WRITE_BARRIER(sc);
2549 : }
2550 0 : athn_enable_interrupts(sc);
2551 :
2552 0 : if (sc->sup_calib_mask != 0) {
2553 0 : memset(&sc->calib, 0, sizeof(sc->calib));
2554 0 : sc->cur_calib_mask = sc->sup_calib_mask;
2555 : /* ops->do_calib(sc); */
2556 0 : }
2557 : /* XXX Start ANI. */
2558 :
2559 0 : timeout_add_msec(&sc->calib_to, 500);
2560 0 : break;
2561 : }
2562 :
2563 0 : return (sc->sc_newstate(ic, nstate, arg));
2564 0 : }
2565 :
2566 : void
2567 0 : athn_updateedca(struct ieee80211com *ic)
2568 : {
2569 : #define ATHN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
2570 0 : struct athn_softc *sc = ic->ic_softc;
2571 : const struct ieee80211_edca_ac_params *ac;
2572 : int aci, qid;
2573 :
2574 0 : for (aci = 0; aci < EDCA_NUM_AC; aci++) {
2575 0 : ac = &ic->ic_edca_ac[aci];
2576 0 : qid = athn_ac2qid[aci];
2577 :
2578 0 : AR_WRITE(sc, AR_DLCL_IFS(qid),
2579 : SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) |
2580 : SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) |
2581 : SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn));
2582 0 : if (ac->ac_txoplimit != 0) {
2583 0 : AR_WRITE(sc, AR_DCHNTIME(qid),
2584 : SM(AR_D_CHNTIME_DUR,
2585 : IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) |
2586 : AR_D_CHNTIME_EN);
2587 0 : } else
2588 0 : AR_WRITE(sc, AR_DCHNTIME(qid), 0);
2589 : }
2590 0 : AR_WRITE_BARRIER(sc);
2591 : #undef ATHN_EXP2
2592 0 : }
2593 :
2594 : int
2595 0 : athn_clock_rate(struct athn_softc *sc)
2596 : {
2597 0 : struct ieee80211com *ic = &sc->sc_ic;
2598 : int clockrate; /* MHz. */
2599 :
2600 0 : if (ic->ic_bss->ni_chan != IEEE80211_CHAN_ANYC &&
2601 0 : IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)) {
2602 0 : if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK)
2603 0 : clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM;
2604 : else
2605 : clockrate = AR_CLOCK_RATE_5GHZ_OFDM;
2606 0 : } else if (ic->ic_curmode == IEEE80211_MODE_11B) {
2607 : clockrate = AR_CLOCK_RATE_CCK;
2608 0 : } else
2609 : clockrate = AR_CLOCK_RATE_2GHZ_OFDM;
2610 0 : if (sc->curchanext != NULL)
2611 0 : clockrate *= 2;
2612 :
2613 0 : return (clockrate);
2614 : }
2615 :
2616 : void
2617 0 : athn_updateslot(struct ieee80211com *ic)
2618 : {
2619 0 : struct athn_softc *sc = ic->ic_softc;
2620 : int slot;
2621 :
2622 0 : slot = (ic->ic_flags & IEEE80211_F_SHSLOT) ?
2623 : IEEE80211_DUR_DS_SHSLOT : IEEE80211_DUR_DS_SLOT;
2624 0 : AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc));
2625 0 : AR_WRITE_BARRIER(sc);
2626 0 : }
2627 :
2628 : void
2629 0 : athn_start(struct ifnet *ifp)
2630 : {
2631 0 : struct athn_softc *sc = ifp->if_softc;
2632 0 : struct ieee80211com *ic = &sc->sc_ic;
2633 0 : struct ieee80211_node *ni;
2634 : struct mbuf *m;
2635 :
2636 0 : if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd))
2637 0 : return;
2638 :
2639 0 : for (;;) {
2640 0 : if (SIMPLEQ_EMPTY(&sc->txbufs)) {
2641 0 : ifq_set_oactive(&ifp->if_snd);
2642 0 : break;
2643 : }
2644 : /* Send pending management frames first. */
2645 0 : m = mq_dequeue(&ic->ic_mgtq);
2646 0 : if (m != NULL) {
2647 0 : ni = m->m_pkthdr.ph_cookie;
2648 0 : goto sendit;
2649 : }
2650 0 : if (ic->ic_state != IEEE80211_S_RUN)
2651 : break;
2652 :
2653 0 : m = mq_dequeue(&ic->ic_pwrsaveq);
2654 0 : if (m != NULL) {
2655 0 : ni = m->m_pkthdr.ph_cookie;
2656 0 : goto sendit;
2657 : }
2658 0 : if (ic->ic_state != IEEE80211_S_RUN)
2659 : break;
2660 :
2661 : /* Encapsulate and send data frames. */
2662 0 : IFQ_DEQUEUE(&ifp->if_snd, m);
2663 0 : if (m == NULL)
2664 : break;
2665 : #if NBPFILTER > 0
2666 0 : if (ifp->if_bpf != NULL)
2667 0 : bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
2668 : #endif
2669 0 : if ((m = ieee80211_encap(ifp, m, &ni)) == NULL)
2670 0 : continue;
2671 : sendit:
2672 : #if NBPFILTER > 0
2673 0 : if (ic->ic_rawbpf != NULL)
2674 0 : bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT);
2675 : #endif
2676 0 : if (sc->ops.tx(sc, m, ni, 0) != 0) {
2677 0 : ieee80211_release_node(ic, ni);
2678 0 : ifp->if_oerrors++;
2679 0 : continue;
2680 : }
2681 :
2682 0 : sc->sc_tx_timer = 5;
2683 0 : ifp->if_timer = 1;
2684 : }
2685 0 : }
2686 :
2687 : void
2688 0 : athn_watchdog(struct ifnet *ifp)
2689 : {
2690 0 : struct athn_softc *sc = ifp->if_softc;
2691 :
2692 0 : ifp->if_timer = 0;
2693 :
2694 0 : if (sc->sc_tx_timer > 0) {
2695 0 : if (--sc->sc_tx_timer == 0) {
2696 0 : printf("%s: device timeout\n", sc->sc_dev.dv_xname);
2697 0 : athn_stop(ifp, 1);
2698 0 : (void)athn_init(ifp);
2699 0 : ifp->if_oerrors++;
2700 0 : return;
2701 : }
2702 0 : ifp->if_timer = 1;
2703 0 : }
2704 :
2705 0 : ieee80211_watchdog(ifp);
2706 0 : }
2707 :
2708 : void
2709 0 : athn_set_multi(struct athn_softc *sc)
2710 : {
2711 0 : struct arpcom *ac = &sc->sc_ic.ic_ac;
2712 0 : struct ifnet *ifp = &ac->ac_if;
2713 : struct ether_multi *enm;
2714 : struct ether_multistep step;
2715 : const uint8_t *addr;
2716 : uint32_t val, lo, hi;
2717 : uint8_t bit;
2718 :
2719 0 : if (ac->ac_multirangecnt > 0)
2720 0 : ifp->if_flags |= IFF_ALLMULTI;
2721 :
2722 0 : if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2723 : lo = hi = 0xffffffff;
2724 0 : goto done;
2725 : }
2726 : lo = hi = 0;
2727 0 : ETHER_FIRST_MULTI(step, ac, enm);
2728 0 : while (enm != NULL) {
2729 0 : addr = enm->enm_addrlo;
2730 : /* Calculate the XOR value of all eight 6-bit words. */
2731 0 : val = addr[0] | addr[1] << 8 | addr[2] << 16;
2732 0 : bit = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2733 0 : val = addr[3] | addr[4] << 8 | addr[5] << 16;
2734 0 : bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2735 0 : bit &= 0x3f;
2736 0 : if (bit < 32)
2737 0 : lo |= 1 << bit;
2738 : else
2739 0 : hi |= 1 << (bit - 32);
2740 0 : ETHER_NEXT_MULTI(step, enm);
2741 : }
2742 : done:
2743 0 : AR_WRITE(sc, AR_MCAST_FIL0, lo);
2744 0 : AR_WRITE(sc, AR_MCAST_FIL1, hi);
2745 0 : AR_WRITE_BARRIER(sc);
2746 0 : }
2747 :
2748 : int
2749 0 : athn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2750 : {
2751 0 : struct athn_softc *sc = ifp->if_softc;
2752 0 : struct ieee80211com *ic = &sc->sc_ic;
2753 : struct ifreq *ifr;
2754 : int s, error = 0;
2755 :
2756 0 : s = splnet();
2757 :
2758 0 : switch (cmd) {
2759 : case SIOCSIFADDR:
2760 0 : ifp->if_flags |= IFF_UP;
2761 : /* FALLTHROUGH */
2762 : case SIOCSIFFLAGS:
2763 0 : if (ifp->if_flags & IFF_UP) {
2764 0 : if ((ifp->if_flags & IFF_RUNNING) &&
2765 0 : ((ifp->if_flags ^ sc->sc_if_flags) &
2766 0 : (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2767 0 : athn_set_multi(sc);
2768 0 : } else if (!(ifp->if_flags & IFF_RUNNING))
2769 0 : error = athn_init(ifp);
2770 : } else {
2771 0 : if (ifp->if_flags & IFF_RUNNING)
2772 0 : athn_stop(ifp, 1);
2773 : }
2774 0 : sc->sc_if_flags = ifp->if_flags;
2775 0 : break;
2776 :
2777 : case SIOCADDMULTI:
2778 : case SIOCDELMULTI:
2779 0 : ifr = (struct ifreq *)data;
2780 0 : error = (cmd == SIOCADDMULTI) ?
2781 0 : ether_addmulti(ifr, &ic->ic_ac) :
2782 0 : ether_delmulti(ifr, &ic->ic_ac);
2783 0 : if (error == ENETRESET) {
2784 0 : athn_set_multi(sc);
2785 : error = 0;
2786 0 : }
2787 : break;
2788 :
2789 : case SIOCS80211CHANNEL:
2790 0 : error = ieee80211_ioctl(ifp, cmd, data);
2791 0 : if (error == ENETRESET &&
2792 0 : ic->ic_opmode == IEEE80211_M_MONITOR) {
2793 0 : if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
2794 : (IFF_UP | IFF_RUNNING))
2795 0 : athn_switch_chan(sc, ic->ic_ibss_chan, NULL);
2796 : error = 0;
2797 0 : }
2798 : break;
2799 :
2800 : default:
2801 0 : error = ieee80211_ioctl(ifp, cmd, data);
2802 0 : }
2803 :
2804 0 : if (error == ENETRESET) {
2805 : error = 0;
2806 0 : if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
2807 : (IFF_UP | IFF_RUNNING)) {
2808 0 : athn_stop(ifp, 0);
2809 0 : error = athn_init(ifp);
2810 0 : }
2811 : }
2812 :
2813 0 : splx(s);
2814 0 : return (error);
2815 : }
2816 :
2817 : int
2818 0 : athn_init(struct ifnet *ifp)
2819 : {
2820 0 : struct athn_softc *sc = ifp->if_softc;
2821 0 : struct athn_ops *ops = &sc->ops;
2822 0 : struct ieee80211com *ic = &sc->sc_ic;
2823 : struct ieee80211_channel *c, *extc;
2824 : int i, error;
2825 :
2826 0 : c = ic->ic_bss->ni_chan = ic->ic_ibss_chan;
2827 : extc = NULL;
2828 :
2829 : /* In case a new MAC address has been configured. */
2830 0 : IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl));
2831 :
2832 : /* For CardBus, power on the socket. */
2833 0 : if (sc->sc_enable != NULL) {
2834 0 : if ((error = sc->sc_enable(sc)) != 0) {
2835 0 : printf("%s: could not enable device\n",
2836 0 : sc->sc_dev.dv_xname);
2837 0 : goto fail;
2838 : }
2839 0 : if ((error = athn_reset_power_on(sc)) != 0) {
2840 0 : printf("%s: could not power on device\n",
2841 0 : sc->sc_dev.dv_xname);
2842 0 : goto fail;
2843 : }
2844 : }
2845 0 : if (!(sc->flags & ATHN_FLAG_PCIE))
2846 0 : athn_config_nonpcie(sc);
2847 : else
2848 0 : athn_config_pcie(sc);
2849 :
2850 : /* Reset HW key cache entries. */
2851 0 : for (i = 0; i < sc->kc_entries; i++)
2852 0 : athn_reset_key(sc, i);
2853 :
2854 0 : ops->enable_antenna_diversity(sc);
2855 :
2856 : #ifdef ATHN_BT_COEXISTENCE
2857 : /* Configure bluetooth coexistence for combo chips. */
2858 : if (sc->flags & ATHN_FLAG_BTCOEX)
2859 : athn_btcoex_init(sc);
2860 : #endif
2861 :
2862 : /* Configure LED. */
2863 0 : athn_led_init(sc);
2864 :
2865 : /* Configure hardware radio switch. */
2866 0 : if (sc->flags & ATHN_FLAG_RFSILENT)
2867 0 : ops->rfsilent_init(sc);
2868 :
2869 0 : if ((error = athn_hw_reset(sc, c, extc, 1)) != 0) {
2870 0 : printf("%s: unable to reset hardware; reset status %d\n",
2871 0 : sc->sc_dev.dv_xname, error);
2872 0 : goto fail;
2873 : }
2874 :
2875 : /* Enable Rx. */
2876 0 : athn_rx_start(sc);
2877 :
2878 : /* Enable interrupts. */
2879 0 : athn_enable_interrupts(sc);
2880 :
2881 : #ifdef ATHN_BT_COEXISTENCE
2882 : /* Enable bluetooth coexistence for combo chips. */
2883 : if (sc->flags & ATHN_FLAG_BTCOEX)
2884 : athn_btcoex_enable(sc);
2885 : #endif
2886 :
2887 0 : ifq_clr_oactive(&ifp->if_snd);
2888 0 : ifp->if_flags |= IFF_RUNNING;
2889 :
2890 : #ifdef notyet
2891 : if (ic->ic_flags & IEEE80211_F_WEPON) {
2892 : /* Configure WEP keys. */
2893 : for (i = 0; i < IEEE80211_WEP_NKID; i++)
2894 : athn_set_key(ic, NULL, &ic->ic_nw_keys[i]);
2895 : }
2896 : #endif
2897 0 : if (ic->ic_opmode == IEEE80211_M_MONITOR)
2898 0 : ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2899 : else
2900 0 : ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2901 :
2902 0 : return (0);
2903 : fail:
2904 0 : athn_stop(ifp, 1);
2905 0 : return (error);
2906 0 : }
2907 :
2908 : void
2909 0 : athn_stop(struct ifnet *ifp, int disable)
2910 : {
2911 0 : struct athn_softc *sc = ifp->if_softc;
2912 0 : struct ieee80211com *ic = &sc->sc_ic;
2913 : int qid;
2914 :
2915 0 : ifp->if_timer = sc->sc_tx_timer = 0;
2916 0 : ifp->if_flags &= ~IFF_RUNNING;
2917 0 : ifq_clr_oactive(&ifp->if_snd);
2918 :
2919 0 : timeout_del(&sc->scan_to);
2920 :
2921 0 : ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2922 :
2923 : #ifdef ATHN_BT_COEXISTENCE
2924 : /* Disable bluetooth coexistence for combo chips. */
2925 : if (sc->flags & ATHN_FLAG_BTCOEX)
2926 : athn_btcoex_disable(sc);
2927 : #endif
2928 :
2929 : /* Disable interrupts. */
2930 0 : athn_disable_interrupts(sc);
2931 : /* Acknowledge interrupts (avoids interrupt storms). */
2932 0 : AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
2933 0 : AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
2934 :
2935 0 : for (qid = 0; qid < ATHN_QID_COUNT; qid++)
2936 0 : athn_stop_tx_dma(sc, qid);
2937 : /* XXX call athn_hw_reset if Tx still pending? */
2938 0 : for (qid = 0; qid < ATHN_QID_COUNT; qid++)
2939 0 : athn_tx_reclaim(sc, qid);
2940 :
2941 : /* Stop Rx. */
2942 0 : AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT);
2943 0 : AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
2944 0 : AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
2945 0 : AR_WRITE(sc, AR_FILT_OFDM, 0);
2946 0 : AR_WRITE(sc, AR_FILT_CCK, 0);
2947 0 : AR_WRITE_BARRIER(sc);
2948 0 : athn_set_rxfilter(sc, 0);
2949 0 : athn_stop_rx_dma(sc);
2950 :
2951 0 : athn_reset(sc, 0);
2952 0 : athn_init_pll(sc, NULL);
2953 0 : athn_set_power_awake(sc);
2954 0 : athn_reset(sc, 1);
2955 0 : athn_init_pll(sc, NULL);
2956 :
2957 0 : athn_set_power_sleep(sc);
2958 :
2959 : /* For CardBus, power down the socket. */
2960 0 : if (disable && sc->sc_disable != NULL)
2961 0 : sc->sc_disable(sc);
2962 0 : }
2963 :
2964 : void
2965 0 : athn_suspend(struct athn_softc *sc)
2966 : {
2967 0 : struct ifnet *ifp = &sc->sc_ic.ic_if;
2968 :
2969 0 : if (ifp->if_flags & IFF_RUNNING)
2970 0 : athn_stop(ifp, 1);
2971 0 : }
2972 :
2973 : void
2974 0 : athn_wakeup(struct athn_softc *sc)
2975 : {
2976 0 : struct ifnet *ifp = &sc->sc_ic.ic_if;
2977 :
2978 0 : if (ifp->if_flags & IFF_UP)
2979 0 : athn_init(ifp);
2980 0 : }
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