Line data Source code
1 : /* $OpenBSD: atphy.c,v 1.11 2016/07/09 15:59:22 kettenis Exp $ */
2 :
3 : /*-
4 : * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 : * All rights reserved.
6 : *
7 : * Redistribution and use in source and binary forms, with or without
8 : * modification, are permitted provided that the following conditions
9 : * are met:
10 : * 1. Redistributions of source code must retain the above copyright
11 : * notice unmodified, this list of conditions, and the following
12 : * disclaimer.
13 : * 2. Redistributions in binary form must reproduce the above copyright
14 : * notice, this list of conditions and the following disclaimer in the
15 : * documentation and/or other materials provided with the distribution.
16 : *
17 : * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 : * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 : * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 : * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 : * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 : * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 : * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 : * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 : * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 : * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 : * SUCH DAMAGE.
28 : */
29 :
30 : /*
31 : * Driver for the Attansic F1 10/100/1000 PHY.
32 : */
33 :
34 : #include <sys/param.h>
35 : #include <sys/systm.h>
36 : #include <sys/device.h>
37 : #include <sys/socket.h>
38 :
39 : #include <net/if.h>
40 : #include <net/if_var.h>
41 : #include <net/if_media.h>
42 :
43 : #include <dev/mii/mii.h>
44 : #include <dev/mii/miivar.h>
45 : #include <dev/mii/miidevs.h>
46 :
47 : /* Special Control Register */
48 : #define ATPHY_SCR 0x10
49 : #define ATPHY_SCR_JABBER_DISABLE 0x0001
50 : #define ATPHY_SCR_POLARITY_REVERSAL 0x0002
51 : #define ATPHY_SCR_SQE_TEST 0x0004
52 : #define ATPHY_SCR_MAC_PDOWN 0x0008
53 : #define ATPHY_SCR_CLK125_DISABLE 0x0010
54 : #define ATPHY_SCR_MDI_MANUAL_MODE 0x0000
55 : #define ATPHY_SCR_MDIX_MANUAL_MODE 0x0020
56 : #define ATPHY_SCR_AUTO_X_1000T 0x0040
57 : #define ATPHY_SCR_AUTO_X_MODE 0x0060
58 : #define ATPHY_SCR_10BT_EXT_ENABLE 0x0080
59 : #define ATPHY_SCR_MII_5BIT_ENABLE 0x0100
60 : #define ATPHY_SCR_SCRAMBLER_DISABLE 0x0200
61 : #define ATPHY_SCR_FORCE_LINK_GOOD 0x0400
62 : #define ATPHY_SCR_ASSERT_CRS_ON_TX 0x0800
63 :
64 : /* Special Status Register. */
65 : #define ATPHY_SSR 0x11
66 : #define ATPHY_SSR_SPD_DPLX_RESOLVED 0x0800
67 : #define ATPHY_SSR_DUPLEX 0x2000
68 : #define ATPHY_SSR_SPEED_MASK 0xC000
69 : #define ATPHY_SSR_10MBS 0x0000
70 : #define ATPHY_SSR_100MBS 0x4000
71 : #define ATPHY_SSR_1000MBS 0x8000
72 :
73 : int atphy_service(struct mii_softc *, struct mii_data *, int);
74 : void atphy_attach(struct device *, struct device *, void *);
75 : int atphy_match(struct device *, void *, void *);
76 : void atphy_reset(struct mii_softc *);
77 : void atphy_status(struct mii_softc *);
78 : int atphy_mii_phy_auto(struct mii_softc *);
79 :
80 : const struct mii_phy_funcs atphy_funcs = {
81 : atphy_service, atphy_status, atphy_reset,
82 : };
83 :
84 : static const struct mii_phydesc atphys[] = {
85 : { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F1,
86 : MII_STR_ATHEROS_F1 },
87 : { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_F2,
88 : MII_STR_ATHEROS_F2 },
89 : { MII_OUI_ATHEROS, MII_MODEL_ATHEROS_AR8035,
90 : MII_STR_ATHEROS_AR8035 },
91 : { 0, 0,
92 : NULL },
93 : };
94 :
95 : struct cfattach atphy_ca = {
96 : sizeof (struct mii_softc), atphy_match, atphy_attach,
97 : mii_phy_detach
98 : };
99 :
100 : struct cfdriver atphy_cd = {
101 : NULL, "atphy", DV_DULL
102 : };
103 :
104 : int
105 0 : atphy_match(struct device *parent, void *match, void *aux)
106 : {
107 0 : struct mii_attach_args *ma = aux;
108 :
109 0 : if (mii_phy_match(ma, atphys) != NULL)
110 0 : return (10);
111 :
112 0 : return (0);
113 0 : }
114 :
115 : void
116 0 : atphy_attach(struct device *parent, struct device *self, void *aux)
117 : {
118 0 : struct mii_softc *sc = (struct mii_softc *)self;
119 0 : struct mii_attach_args *ma = aux;
120 0 : struct mii_data *mii = ma->mii_data;
121 : const struct mii_phydesc *mpd;
122 :
123 0 : mpd = mii_phy_match(ma, atphys);
124 0 : printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
125 :
126 0 : sc->mii_inst = mii->mii_instance;
127 0 : sc->mii_phy = ma->mii_phyno;
128 0 : sc->mii_funcs = &atphy_funcs;
129 0 : sc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
130 0 : sc->mii_model = MII_MODEL(ma->mii_id2);
131 0 : sc->mii_pdata = mii;
132 0 : sc->mii_flags = ma->mii_flags;
133 0 : sc->mii_anegticks = MII_ANEGTICKS_GIGE;
134 :
135 0 : sc->mii_flags |= MIIF_NOLOOP;
136 :
137 0 : PHY_RESET(sc);
138 :
139 0 : sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
140 0 : if (sc->mii_capabilities & BMSR_EXTSTAT)
141 0 : sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
142 :
143 0 : mii_phy_add_media(sc);
144 0 : }
145 :
146 : int
147 0 : atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
148 : {
149 0 : struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
150 : uint16_t anar, bmcr, bmsr;
151 :
152 0 : switch (cmd) {
153 : case MII_POLLSTAT:
154 : /*
155 : * If we're not polling our PHY instance, just return.
156 : */
157 0 : if (IFM_INST(ife->ifm_media) != sc->mii_inst)
158 0 : return (0);
159 : break;
160 :
161 : case MII_MEDIACHG:
162 : /*
163 : * If the media indicates a different PHY instance,
164 : * isolate ourselves.
165 : */
166 0 : if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
167 0 : bmcr = PHY_READ(sc, MII_BMCR);
168 0 : PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
169 0 : return (0);
170 : }
171 :
172 : /*
173 : * If the interface is not up, don't do anything.
174 : */
175 0 : if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
176 : break;
177 :
178 : bmcr = 0;
179 0 : switch (IFM_SUBTYPE(ife->ifm_media)) {
180 : case IFM_AUTO:
181 : case IFM_1000_T:
182 0 : atphy_mii_phy_auto(sc);
183 0 : goto done;
184 : case IFM_100_TX:
185 : bmcr = BMCR_S100;
186 0 : break;
187 : case IFM_10_T:
188 : bmcr = BMCR_S10;
189 0 : break;
190 : case IFM_NONE:
191 0 : bmcr = PHY_READ(sc, MII_BMCR);
192 : /*
193 : * XXX
194 : * Due to an unknown reason powering down PHY resulted
195 : * in unexpected results such as inaccessibility of
196 : * hardware of freshly rebooted system. Disable
197 : * powering down PHY until I got more information for
198 : * Attansic/Atheros PHY hardwares.
199 : */
200 0 : PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
201 0 : goto done;
202 : default:
203 0 : return (EINVAL);
204 : }
205 :
206 0 : anar = mii_anar(ife->ifm_media);
207 0 : if (((ife->ifm_media & IFM_GMASK) & IFM_FDX) != 0) {
208 0 : bmcr |= BMCR_FDX;
209 : /* Enable pause. */
210 0 : if (sc->mii_flags & MIIF_DOPAUSE)
211 0 : anar |= ANAR_PAUSE_TOWARDS;
212 : }
213 :
214 0 : if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
215 0 : EXTSR_1000THDX)) != 0)
216 0 : PHY_WRITE(sc, MII_100T2CR, 0);
217 0 : PHY_WRITE(sc, MII_ANAR, anar);
218 :
219 : /*
220 : * Reset the PHY so all changes take effect.
221 : */
222 0 : PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
223 : BMCR_STARTNEG);
224 : done:
225 : break;
226 :
227 : case MII_TICK:
228 : /*
229 : * If we're not currently selected, just return.
230 : */
231 0 : if (IFM_INST(ife->ifm_media) != sc->mii_inst)
232 0 : return (0);
233 :
234 : /*
235 : * Is the interface even up?
236 : */
237 0 : if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
238 0 : return (0);
239 :
240 : /*
241 : * Only used for autonegotiation.
242 : */
243 0 : if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
244 0 : sc->mii_ticks = 0;
245 0 : break;
246 : }
247 :
248 : /*
249 : * Check for link.
250 : * Read the status register twice; BMSR_LINK is latch-low.
251 : */
252 0 : bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
253 0 : if (bmsr & BMSR_LINK) {
254 0 : sc->mii_ticks = 0;
255 0 : break;
256 : }
257 :
258 : /* Announce link loss right after it happens. */
259 0 : if (sc->mii_ticks++ == 0)
260 : break;
261 :
262 : /*
263 : * Only retry autonegotiation every mii_anegticks seconds.
264 : */
265 0 : if (sc->mii_ticks <= sc->mii_anegticks)
266 0 : return (0);
267 :
268 0 : sc->mii_ticks = 0;
269 0 : atphy_mii_phy_auto(sc);
270 0 : break;
271 : }
272 :
273 : /* Update the media status. */
274 0 : mii_phy_status(sc);
275 :
276 : /* Callback if something changed. */
277 0 : mii_phy_update(sc, cmd);
278 0 : return (0);
279 0 : }
280 :
281 : void
282 0 : atphy_status(struct mii_softc *sc)
283 : {
284 0 : struct mii_data *mii = sc->mii_pdata;
285 : uint32_t bmsr, bmcr, gsr, ssr;
286 :
287 0 : mii->mii_media_status = IFM_AVALID;
288 0 : mii->mii_media_active = IFM_ETHER;
289 :
290 0 : bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
291 0 : if (bmsr & BMSR_LINK)
292 0 : mii->mii_media_status |= IFM_ACTIVE;
293 :
294 0 : bmcr = PHY_READ(sc, MII_BMCR);
295 0 : if (bmcr & BMCR_ISO) {
296 0 : mii->mii_media_active |= IFM_NONE;
297 0 : mii->mii_media_status = 0;
298 0 : return;
299 : }
300 :
301 0 : if (bmcr & BMCR_LOOP)
302 0 : mii->mii_media_active |= IFM_LOOP;
303 :
304 0 : ssr = PHY_READ(sc, ATPHY_SSR);
305 0 : if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED)) {
306 : /* Erg, still trying, I guess... */
307 0 : mii->mii_media_active |= IFM_NONE;
308 0 : return;
309 : }
310 :
311 0 : switch (ssr & ATPHY_SSR_SPEED_MASK) {
312 : case ATPHY_SSR_1000MBS:
313 0 : mii->mii_media_active |= IFM_1000_T;
314 : /*
315 : * atphy(4) has a valid link so reset mii_ticks.
316 : * Resetting mii_ticks is needed in order to
317 : * detect link loss after auto-negotiation.
318 : */
319 0 : sc->mii_ticks = 0;
320 0 : break;
321 : case ATPHY_SSR_100MBS:
322 0 : mii->mii_media_active |= IFM_100_TX;
323 0 : sc->mii_ticks = 0;
324 0 : break;
325 : case ATPHY_SSR_10MBS:
326 0 : mii->mii_media_active |= IFM_10_T;
327 0 : sc->mii_ticks = 0;
328 0 : break;
329 : default:
330 0 : mii->mii_media_active |= IFM_NONE;
331 0 : return;
332 : }
333 :
334 0 : if (ssr & ATPHY_SSR_DUPLEX)
335 0 : mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
336 : else
337 0 : mii->mii_media_active |= IFM_HDX;
338 :
339 0 : gsr = PHY_READ(sc, MII_100T2SR);
340 0 : if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
341 0 : gsr & GTSR_MS_RES)
342 0 : mii->mii_media_active |= IFM_ETH_MASTER;
343 0 : }
344 :
345 : void
346 0 : atphy_reset(struct mii_softc *sc)
347 : {
348 : uint32_t reg;
349 : int i;
350 :
351 : /* Take PHY out of power down mode. */
352 0 : PHY_WRITE(sc, 29, 0x29);
353 0 : PHY_WRITE(sc, 30, 0);
354 :
355 0 : reg = PHY_READ(sc, ATPHY_SCR);
356 : /* Enable automatic crossover. */
357 0 : reg |= ATPHY_SCR_AUTO_X_MODE;
358 : /* Disable power down. */
359 0 : reg &= ~ATPHY_SCR_MAC_PDOWN;
360 : /* Enable CRS on Tx. */
361 0 : reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
362 : /* Auto correction for reversed cable polarity. */
363 0 : reg |= ATPHY_SCR_POLARITY_REVERSAL;
364 0 : PHY_WRITE(sc, ATPHY_SCR, reg);
365 :
366 : /* Workaround F1 bug to reset phy. */
367 0 : atphy_mii_phy_auto(sc);
368 :
369 0 : for (i = 0; i < 1000; i++) {
370 0 : DELAY(1);
371 0 : if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
372 : break;
373 : }
374 0 : }
375 :
376 : int
377 0 : atphy_mii_phy_auto(struct mii_softc *sc)
378 : {
379 : uint16_t anar;
380 :
381 0 : anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
382 0 : if (sc->mii_flags & MIIF_DOPAUSE)
383 0 : anar |= ANAR_PAUSE_TOWARDS;
384 0 : PHY_WRITE(sc, MII_ANAR, anar);
385 0 : if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
386 0 : PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
387 : GTCR_ADV_1000THDX);
388 0 : else if (sc->mii_model == MII_MODEL_ATHEROS_F1) {
389 : /*
390 : * AR8132 has 10/100 PHY and the PHY uses the same
391 : * model number of F1 gigabit PHY. The PHY has no
392 : * ability to establish gigabit link so explicitly
393 : * disable 1000baseT configuration for the PHY.
394 : * Otherwise, there is a case that atphy(4) could
395 : * not establish a link against gigabit link partner
396 : * unless the link partner supports down-shifting.
397 : */
398 0 : PHY_WRITE(sc, MII_100T2CR, 0);
399 0 : }
400 0 : PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
401 :
402 0 : return (EJUSTRETURN);
403 : }
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