Line data Source code
1 : /* $OpenBSD: rgephy.c,v 1.40 2018/02/27 19:47:10 kettenis Exp $ */
2 : /*
3 : * Copyright (c) 2003
4 : * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 : *
6 : * Redistribution and use in source and binary forms, with or without
7 : * modification, are permitted provided that the following conditions
8 : * are met:
9 : * 1. Redistributions of source code must retain the above copyright
10 : * notice, this list of conditions and the following disclaimer.
11 : * 2. Redistributions in binary form must reproduce the above copyright
12 : * notice, this list of conditions and the following disclaimer in the
13 : * documentation and/or other materials provided with the distribution.
14 : * 3. All advertising materials mentioning features or use of this software
15 : * must display the following acknowledgement:
16 : * This product includes software developed by Bill Paul.
17 : * 4. Neither the name of the author nor the names of any co-contributors
18 : * may be used to endorse or promote products derived from this software
19 : * without specific prior written permission.
20 : *
21 : * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 : * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 : * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 : * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 : * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 : * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 : * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 : * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 : * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 : * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 : * THE POSSIBILITY OF SUCH DAMAGE.
32 : *
33 : * $FreeBSD: rgephy.c,v 1.5 2004/05/30 17:57:40 phk Exp $
34 : */
35 :
36 : /*
37 : * Driver for the Realtek 8169S/8110S internal 10/100/1000 PHY.
38 : */
39 :
40 : #include <sys/param.h>
41 : #include <sys/systm.h>
42 : #include <sys/kernel.h>
43 : #include <sys/device.h>
44 : #include <sys/socket.h>
45 : #include <sys/errno.h>
46 :
47 : #include <machine/bus.h>
48 :
49 : #include <net/if.h>
50 : #include <net/if_media.h>
51 :
52 : #include <netinet/in.h>
53 : #include <netinet/if_ether.h>
54 :
55 : #include <dev/mii/mii.h>
56 : #include <dev/mii/miivar.h>
57 : #include <dev/mii/miidevs.h>
58 :
59 : #include <dev/mii/rgephyreg.h>
60 :
61 : #include <dev/ic/rtl81x9reg.h>
62 :
63 : int rgephymatch(struct device *, void *, void *);
64 : void rgephyattach(struct device *, struct device *, void *);
65 :
66 : struct cfattach rgephy_ca = { sizeof(struct mii_softc),
67 : rgephymatch, rgephyattach, mii_phy_detach,
68 : };
69 :
70 : struct cfdriver rgephy_cd = {
71 : NULL, "rgephy", DV_DULL
72 : };
73 :
74 : int rgephy_service(struct mii_softc *, struct mii_data *, int);
75 : void rgephy_status(struct mii_softc *);
76 : int rgephy_mii_phy_auto(struct mii_softc *);
77 : void rgephy_reset(struct mii_softc *);
78 : void rgephy_loop(struct mii_softc *);
79 : void rgephy_load_dspcode(struct mii_softc *);
80 :
81 : const struct mii_phy_funcs rgephy_funcs = {
82 : rgephy_service, rgephy_status, rgephy_reset,
83 : };
84 :
85 : static const struct mii_phydesc rgephys[] = {
86 : { MII_OUI_REALTEK2, MII_MODEL_xxREALTEK_RTL8169S,
87 : MII_STR_xxREALTEK_RTL8169S },
88 : { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S,
89 : MII_STR_xxREALTEK_RTL8169S },
90 : { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8251,
91 : MII_STR_xxREALTEK_RTL8251 },
92 :
93 : { 0, 0,
94 : NULL },
95 : };
96 :
97 : int
98 0 : rgephymatch(struct device *parent, void *match, void *aux)
99 : {
100 0 : struct mii_attach_args *ma = aux;
101 :
102 0 : if (mii_phy_match(ma, rgephys) != NULL)
103 0 : return (10);
104 :
105 0 : return (0);
106 0 : }
107 :
108 : void
109 0 : rgephyattach(struct device *parent, struct device *self, void *aux)
110 : {
111 0 : struct mii_softc *sc = (struct mii_softc *)self;
112 0 : struct mii_attach_args *ma = aux;
113 0 : struct mii_data *mii = ma->mii_data;
114 : const struct mii_phydesc *mpd;
115 :
116 0 : mpd = mii_phy_match(ma, rgephys);
117 0 : printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
118 :
119 0 : sc->mii_inst = mii->mii_instance;
120 0 : sc->mii_phy = ma->mii_phyno;
121 0 : sc->mii_funcs = &rgephy_funcs;
122 0 : sc->mii_model = MII_MODEL(ma->mii_id2);
123 0 : sc->mii_rev = MII_REV(ma->mii_id2);
124 0 : sc->mii_pdata = mii;
125 0 : sc->mii_flags = ma->mii_flags;
126 0 : sc->mii_anegticks = MII_ANEGTICKS_GIGE;
127 :
128 0 : sc->mii_flags |= MIIF_NOISOLATE;
129 :
130 0 : sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
131 :
132 0 : if (sc->mii_capabilities & BMSR_EXTSTAT)
133 0 : sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
134 0 : if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
135 0 : (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
136 0 : mii_phy_add_media(sc);
137 :
138 0 : PHY_RESET(sc);
139 0 : }
140 :
141 : int
142 0 : rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
143 : {
144 0 : struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
145 : int anar, reg, speed, gig = 0;
146 : char *devname;
147 :
148 0 : devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name;
149 :
150 0 : switch (cmd) {
151 : case MII_POLLSTAT:
152 : /*
153 : * If we're not polling our PHY instance, just return.
154 : */
155 0 : if (IFM_INST(ife->ifm_media) != sc->mii_inst)
156 0 : return (0);
157 : break;
158 :
159 : case MII_MEDIACHG:
160 : /*
161 : * If the media indicates a different PHY instance,
162 : * isolate ourselves.
163 : */
164 0 : if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
165 0 : reg = PHY_READ(sc, MII_BMCR);
166 0 : PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
167 0 : return (0);
168 : }
169 :
170 : /*
171 : * If the interface is not up, don't do anything.
172 : */
173 0 : if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
174 : break;
175 :
176 0 : PHY_RESET(sc); /* XXX hardware bug work-around */
177 :
178 0 : anar = PHY_READ(sc, MII_ANAR);
179 0 : anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10);
180 :
181 0 : switch (IFM_SUBTYPE(ife->ifm_media)) {
182 : case IFM_AUTO:
183 0 : (void) rgephy_mii_phy_auto(sc);
184 0 : break;
185 : case IFM_1000_T:
186 : speed = BMCR_S1000;
187 0 : goto setit;
188 : case IFM_100_TX:
189 : speed = BMCR_S100;
190 0 : anar |= ANAR_TX_FD | ANAR_TX;
191 0 : goto setit;
192 : case IFM_10_T:
193 : speed = BMCR_S10;
194 0 : anar |= ANAR_10_FD | ANAR_10;
195 : setit:
196 0 : rgephy_loop(sc);
197 0 : if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
198 0 : speed |= BMCR_FDX;
199 0 : if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T)
200 0 : gig = GTCR_ADV_1000TFDX;
201 0 : anar &= ~(ANAR_TX | ANAR_10);
202 0 : } else {
203 0 : if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T)
204 0 : gig = GTCR_ADV_1000THDX;
205 0 : anar &=
206 : ~(ANAR_TX_FD | ANAR_10_FD);
207 : }
208 :
209 0 : if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T &&
210 0 : mii->mii_media.ifm_media & IFM_ETH_MASTER)
211 0 : gig |= GTCR_MAN_MS|GTCR_ADV_MS;
212 :
213 0 : PHY_WRITE(sc, MII_100T2CR, gig);
214 0 : PHY_WRITE(sc, MII_BMCR, speed | BMCR_AUTOEN |
215 : BMCR_STARTNEG);
216 0 : PHY_WRITE(sc, MII_ANAR, anar);
217 0 : break;
218 : #if 0
219 : case IFM_NONE:
220 : PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
221 : break;
222 : #endif
223 : default:
224 0 : return (EINVAL);
225 : }
226 : break;
227 :
228 : case MII_TICK:
229 : /*
230 : * If we're not currently selected, just return.
231 : */
232 0 : if (IFM_INST(ife->ifm_media) != sc->mii_inst)
233 0 : return (0);
234 :
235 : /*
236 : * Is the interface even up?
237 : */
238 0 : if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
239 0 : return (0);
240 :
241 : /*
242 : * Only used for autonegotiation.
243 : */
244 0 : if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
245 : break;
246 :
247 : /*
248 : * Check to see if we have link. If we do, we don't
249 : * need to restart the autonegotiation process. Read
250 : * the BMSR twice in case it's latched.
251 : */
252 0 : if (strcmp(devname, "re") == 0 || strcmp(devname, "ure") == 0) {
253 0 : reg = PHY_READ(sc, RL_GMEDIASTAT);
254 0 : if (reg & RL_GMEDIASTAT_LINK) {
255 0 : sc->mii_ticks = 0;
256 0 : break;
257 : }
258 0 : } else if (sc->mii_rev == RGEPHY_8211F) {
259 0 : reg = PHY_READ(sc, RGEPHY_F_SR);
260 0 : if (reg & RGEPHY_F_SR_LINK) {
261 0 : sc->mii_ticks = 0;
262 0 : }
263 : } else {
264 0 : reg = PHY_READ(sc, RGEPHY_SR);
265 0 : if (reg & RGEPHY_SR_LINK) {
266 0 : sc->mii_ticks = 0;
267 0 : break;
268 : }
269 : }
270 :
271 : /*
272 : * Only retry autonegotiation every mii_anegticks seconds.
273 : */
274 0 : if (++sc->mii_ticks <= sc->mii_anegticks)
275 : break;
276 :
277 0 : sc->mii_ticks = 0;
278 0 : rgephy_mii_phy_auto(sc);
279 0 : break;
280 : }
281 :
282 : /* Update the media status. */
283 0 : mii_phy_status(sc);
284 :
285 : /*
286 : * Callback if something changed. Note that we need to poke
287 : * the DSP on the Realtek PHYs if the media changes.
288 : *
289 : */
290 0 : if (sc->mii_media_active != mii->mii_media_active ||
291 0 : sc->mii_media_status != mii->mii_media_status ||
292 0 : cmd == MII_MEDIACHG)
293 0 : rgephy_load_dspcode(sc);
294 :
295 : /* Callback if something changed. */
296 0 : mii_phy_update(sc, cmd);
297 :
298 0 : return (0);
299 0 : }
300 :
301 : void
302 0 : rgephy_status(struct mii_softc *sc)
303 : {
304 0 : struct mii_data *mii = sc->mii_pdata;
305 : int bmsr, bmcr, gtsr;
306 : char *devname;
307 :
308 0 : devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name;
309 :
310 0 : mii->mii_media_status = IFM_AVALID;
311 0 : mii->mii_media_active = IFM_ETHER;
312 :
313 0 : if (strcmp(devname, "re") == 0 || strcmp(devname, "ure") == 0) {
314 0 : bmsr = PHY_READ(sc, RL_GMEDIASTAT);
315 0 : if (bmsr & RL_GMEDIASTAT_LINK)
316 0 : mii->mii_media_status |= IFM_ACTIVE;
317 0 : } else if (sc->mii_rev == RGEPHY_8211F) {
318 0 : bmsr = PHY_READ(sc, RGEPHY_F_SR);
319 0 : if (bmsr & RGEPHY_F_SR_LINK)
320 0 : mii->mii_media_status |= IFM_ACTIVE;
321 : } else {
322 0 : bmsr = PHY_READ(sc, RGEPHY_SR);
323 0 : if (bmsr & RGEPHY_SR_LINK)
324 0 : mii->mii_media_status |= IFM_ACTIVE;
325 : }
326 :
327 0 : bmsr = PHY_READ(sc, MII_BMSR);
328 :
329 0 : bmcr = PHY_READ(sc, MII_BMCR);
330 :
331 0 : if (bmcr & BMCR_LOOP)
332 0 : mii->mii_media_active |= IFM_LOOP;
333 :
334 0 : if (bmcr & BMCR_AUTOEN) {
335 0 : if ((bmsr & BMSR_ACOMP) == 0) {
336 : /* Erg, still trying, I guess... */
337 0 : mii->mii_media_active |= IFM_NONE;
338 0 : return;
339 : }
340 : }
341 :
342 0 : if (strcmp(devname, "re") == 0 || strcmp(devname, "ure") == 0) {
343 0 : bmsr = PHY_READ(sc, RL_GMEDIASTAT);
344 0 : if (bmsr & RL_GMEDIASTAT_1000MBPS)
345 0 : mii->mii_media_active |= IFM_1000_T;
346 0 : else if (bmsr & RL_GMEDIASTAT_100MBPS)
347 0 : mii->mii_media_active |= IFM_100_TX;
348 0 : else if (bmsr & RL_GMEDIASTAT_10MBPS)
349 0 : mii->mii_media_active |= IFM_10_T;
350 :
351 0 : if (bmsr & RL_GMEDIASTAT_FDX)
352 0 : mii->mii_media_active |= mii_phy_flowstatus(sc) |
353 : IFM_FDX;
354 : else
355 0 : mii->mii_media_active |= IFM_HDX;
356 0 : } else if (sc->mii_rev == RGEPHY_8211F) {
357 0 : bmsr = PHY_READ(sc, RGEPHY_F_SR);
358 0 : if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_1000MBPS)
359 0 : mii->mii_media_active |= IFM_1000_T;
360 0 : else if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_100MBPS)
361 0 : mii->mii_media_active |= IFM_100_TX;
362 0 : else if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_10MBPS)
363 0 : mii->mii_media_active |= IFM_10_T;
364 :
365 0 : if (bmsr & RGEPHY_F_SR_FDX)
366 0 : mii->mii_media_active |= mii_phy_flowstatus(sc) |
367 : IFM_FDX;
368 : else
369 0 : mii->mii_media_active |= IFM_HDX;
370 : } else {
371 0 : bmsr = PHY_READ(sc, RGEPHY_SR);
372 0 : if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_1000MBPS)
373 0 : mii->mii_media_active |= IFM_1000_T;
374 0 : else if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_100MBPS)
375 0 : mii->mii_media_active |= IFM_100_TX;
376 0 : else if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_10MBPS)
377 0 : mii->mii_media_active |= IFM_10_T;
378 :
379 0 : if (bmsr & RGEPHY_SR_FDX)
380 0 : mii->mii_media_active |= mii_phy_flowstatus(sc) |
381 : IFM_FDX;
382 : else
383 0 : mii->mii_media_active |= IFM_HDX;
384 : }
385 :
386 0 : gtsr = PHY_READ(sc, MII_100T2SR);
387 0 : if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
388 0 : gtsr & GTSR_MS_RES)
389 0 : mii->mii_media_active |= IFM_ETH_MASTER;
390 0 : }
391 :
392 :
393 : int
394 0 : rgephy_mii_phy_auto(struct mii_softc *sc)
395 : {
396 : int anar;
397 :
398 0 : rgephy_loop(sc);
399 0 : PHY_RESET(sc);
400 :
401 0 : anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
402 0 : if (sc->mii_flags & MIIF_DOPAUSE)
403 0 : anar |= ANAR_FC | ANAR_X_PAUSE_ASYM;
404 :
405 0 : PHY_WRITE(sc, MII_ANAR, anar);
406 0 : DELAY(1000);
407 0 : PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX);
408 0 : DELAY(1000);
409 0 : PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
410 0 : DELAY(100);
411 :
412 0 : return (EJUSTRETURN);
413 : }
414 :
415 : void
416 0 : rgephy_loop(struct mii_softc *sc)
417 : {
418 : u_int32_t bmsr;
419 : int i;
420 :
421 0 : if (sc->mii_model != MII_MODEL_xxREALTEK_RTL8251 &&
422 0 : sc->mii_rev < 2) {
423 0 : PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
424 0 : DELAY(1000);
425 0 : }
426 :
427 0 : for (i = 0; i < 15000; i++) {
428 0 : bmsr = PHY_READ(sc, MII_BMSR);
429 0 : if (!(bmsr & BMSR_LINK))
430 : break;
431 0 : DELAY(10);
432 : }
433 0 : }
434 :
435 : #define PHY_SETBIT(x, y, z) \
436 : PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
437 : #define PHY_CLRBIT(x, y, z) \
438 : PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
439 :
440 : /*
441 : * Initialize Realtek PHY per the datasheet. The DSP in the PHYs of
442 : * existing revisions of the 8169S/8110S chips need to be tuned in
443 : * order to reliably negotiate a 1000Mbps link. This is only needed
444 : * for rev 0 and rev 1 of the PHY. Later versions work without
445 : * any fixups.
446 : */
447 : void
448 0 : rgephy_load_dspcode(struct mii_softc *sc)
449 : {
450 : int val;
451 :
452 0 : if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8251 ||
453 0 : sc->mii_rev > 1)
454 0 : return;
455 :
456 0 : PHY_WRITE(sc, 31, 0x0001);
457 0 : PHY_WRITE(sc, 21, 0x1000);
458 0 : PHY_WRITE(sc, 24, 0x65C7);
459 0 : PHY_CLRBIT(sc, 4, 0x0800);
460 0 : val = PHY_READ(sc, 4) & 0xFFF;
461 0 : PHY_WRITE(sc, 4, val);
462 0 : PHY_WRITE(sc, 3, 0x00A1);
463 0 : PHY_WRITE(sc, 2, 0x0008);
464 0 : PHY_WRITE(sc, 1, 0x1020);
465 0 : PHY_WRITE(sc, 0, 0x1000);
466 0 : PHY_SETBIT(sc, 4, 0x0800);
467 0 : PHY_CLRBIT(sc, 4, 0x0800);
468 0 : val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
469 0 : PHY_WRITE(sc, 4, val);
470 0 : PHY_WRITE(sc, 3, 0xFF41);
471 0 : PHY_WRITE(sc, 2, 0xDE60);
472 0 : PHY_WRITE(sc, 1, 0x0140);
473 0 : PHY_WRITE(sc, 0, 0x0077);
474 0 : val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
475 0 : PHY_WRITE(sc, 4, val);
476 0 : PHY_WRITE(sc, 3, 0xDF01);
477 0 : PHY_WRITE(sc, 2, 0xDF20);
478 0 : PHY_WRITE(sc, 1, 0xFF95);
479 0 : PHY_WRITE(sc, 0, 0xFA00);
480 0 : val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
481 0 : PHY_WRITE(sc, 4, val);
482 0 : PHY_WRITE(sc, 3, 0xFF41);
483 0 : PHY_WRITE(sc, 2, 0xDE20);
484 0 : PHY_WRITE(sc, 1, 0x0140);
485 0 : PHY_WRITE(sc, 0, 0x00BB);
486 0 : val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
487 0 : PHY_WRITE(sc, 4, val);
488 0 : PHY_WRITE(sc, 3, 0xDF01);
489 0 : PHY_WRITE(sc, 2, 0xDF20);
490 0 : PHY_WRITE(sc, 1, 0xFF95);
491 0 : PHY_WRITE(sc, 0, 0xBF00);
492 0 : PHY_SETBIT(sc, 4, 0x0800);
493 0 : PHY_CLRBIT(sc, 4, 0x0800);
494 0 : PHY_WRITE(sc, 31, 0x0000);
495 :
496 0 : DELAY(40);
497 0 : }
498 :
499 : void
500 0 : rgephy_reset(struct mii_softc *sc)
501 : {
502 0 : mii_phy_reset(sc);
503 0 : DELAY(1000);
504 0 : rgephy_load_dspcode(sc);
505 0 : }
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