Line data Source code
1 : /* $OpenBSD: cy82c693.c,v 1.8 2015/03/14 03:38:48 jsg Exp $ */
2 : /* $NetBSD: cy82c693.c,v 1.1 2000/06/06 03:07:39 thorpej Exp $ */
3 :
4 : /*-
5 : * Copyright (c) 2000 The NetBSD Foundation, Inc.
6 : * All rights reserved.
7 : *
8 : * This code is derived from software contributed to The NetBSD Foundation
9 : * by Jason R. Thorpe.
10 : *
11 : * Redistribution and use in source and binary forms, with or without
12 : * modification, are permitted provided that the following conditions
13 : * are met:
14 : * 1. Redistributions of source code must retain the above copyright
15 : * notice, this list of conditions and the following disclaimer.
16 : * 2. Redistributions in binary form must reproduce the above copyright
17 : * notice, this list of conditions and the following disclaimer in the
18 : * documentation and/or other materials provided with the distribution.
19 : *
20 : * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 : * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 : * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 : * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 : * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 : * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 : * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 : * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 : * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 : * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 : * POSSIBILITY OF SUCH DAMAGE.
31 : */
32 :
33 : /*
34 : * Common routines to read/write control registers on the Cypress 82c693
35 : * hyperCache(tm) Stand-Alone PCI Peripheral Controller with USB.
36 : */
37 :
38 : #include <sys/param.h>
39 : #include <sys/device.h>
40 : #include <sys/systm.h>
41 :
42 : #include <machine/bus.h>
43 :
44 : #include <dev/pci/pcivar.h>
45 :
46 : #include <dev/pci/cy82c693reg.h>
47 : #include <dev/pci/cy82c693var.h>
48 :
49 : static struct cy82c693_handle cyhc_handle;
50 : static int cyhc_initialized;
51 :
52 : const struct cy82c693_handle *
53 0 : cy82c693_init(bus_space_tag_t iot)
54 : {
55 0 : bus_space_handle_t ioh;
56 : int error;
57 :
58 0 : if (cyhc_initialized) {
59 0 : if (iot != cyhc_handle.cyhc_iot)
60 0 : panic("cy82c693_init");
61 0 : return (&cyhc_handle);
62 : }
63 :
64 0 : if ((error = bus_space_map(iot, CYHC_CONFIG_ADDR, 2, 0, &ioh)) != 0) {
65 0 : printf("cy82c693_init: bus_space_map failed (%d)", error);
66 0 : return (NULL);
67 : }
68 :
69 0 : cyhc_handle.cyhc_iot = iot;
70 0 : cyhc_handle.cyhc_ioh = ioh;
71 :
72 0 : cyhc_initialized = 1;
73 :
74 0 : return (&cyhc_handle);
75 0 : }
76 :
77 : u_int8_t
78 0 : cy82c693_read(const struct cy82c693_handle *cyhc, int reg)
79 : {
80 : u_int8_t rv;
81 :
82 0 : if (cyhc_initialized == 0)
83 0 : panic("cy82c693_read");
84 :
85 0 : bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
86 0 : rv = bus_space_read_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 1);
87 :
88 0 : return (rv);
89 : }
90 :
91 : void
92 0 : cy82c693_write(const struct cy82c693_handle *cyhc, int reg, u_int8_t val)
93 : {
94 0 : if (cyhc_initialized == 0)
95 0 : panic("cy82c693_write");
96 :
97 0 : bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 0, reg);
98 0 : bus_space_write_1(cyhc->cyhc_iot, cyhc->cyhc_ioh, 1, val);
99 0 : }
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