Line data Source code
1 : /*
2 : * Copyright © 2008 Keith Packard
3 : *
4 : * Permission to use, copy, modify, distribute, and sell this software and its
5 : * documentation for any purpose is hereby granted without fee, provided that
6 : * the above copyright notice appear in all copies and that both that copyright
7 : * notice and this permission notice appear in supporting documentation, and
8 : * that the name of the copyright holders not be used in advertising or
9 : * publicity pertaining to distribution of the software without specific,
10 : * written prior permission. The copyright holders make no representations
11 : * about the suitability of this software for any purpose. It is provided "as
12 : * is" without express or implied warranty.
13 : *
14 : * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 : * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 : * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 : * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 : * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 : * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 : * OF THIS SOFTWARE.
21 : */
22 :
23 : #ifndef _DRM_DP_HELPER_H_
24 : #define _DRM_DP_HELPER_H_
25 :
26 : #ifdef __linux__
27 : #include <linux/types.h>
28 : #include <linux/i2c.h>
29 : #include <linux/delay.h>
30 : #else
31 : #include <dev/pci/drm/drm_linux.h>
32 : #endif
33 :
34 : /*
35 : * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
36 : * DP and DPCD versions are independent. Differences from 1.0 are not noted,
37 : * 1.0 devices basically don't exist in the wild.
38 : *
39 : * Abbreviations, in chronological order:
40 : *
41 : * eDP: Embedded DisplayPort version 1
42 : * DPI: DisplayPort Interoperability Guideline v1.1a
43 : * 1.2: DisplayPort 1.2
44 : * MST: Multistream Transport - part of DP 1.2a
45 : *
46 : * 1.2 formally includes both eDP and DPI definitions.
47 : */
48 :
49 : #define DP_AUX_MAX_PAYLOAD_BYTES 16
50 :
51 : #define DP_AUX_I2C_WRITE 0x0
52 : #define DP_AUX_I2C_READ 0x1
53 : #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
54 : #define DP_AUX_I2C_MOT 0x4
55 : #define DP_AUX_NATIVE_WRITE 0x8
56 : #define DP_AUX_NATIVE_READ 0x9
57 :
58 : #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
59 : #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
60 : #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
61 : #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
62 :
63 : #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
64 : #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
65 : #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
66 : #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
67 :
68 : /* AUX CH addresses */
69 : /* DPCD */
70 : #define DP_DPCD_REV 0x000
71 :
72 : #define DP_MAX_LINK_RATE 0x001
73 :
74 : #define DP_MAX_LANE_COUNT 0x002
75 : # define DP_MAX_LANE_COUNT_MASK 0x1f
76 : # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
77 : # define DP_ENHANCED_FRAME_CAP (1 << 7)
78 :
79 : #define DP_MAX_DOWNSPREAD 0x003
80 : # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
81 :
82 : #define DP_NORP 0x004
83 :
84 : #define DP_DOWNSTREAMPORT_PRESENT 0x005
85 : # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
86 : # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
87 : # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
88 : # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
89 : # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
90 : # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
91 : # define DP_FORMAT_CONVERSION (1 << 3)
92 : # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
93 :
94 : #define DP_MAIN_LINK_CHANNEL_CODING 0x006
95 :
96 : #define DP_DOWN_STREAM_PORT_COUNT 0x007
97 : # define DP_PORT_COUNT_MASK 0x0f
98 : # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
99 : # define DP_OUI_SUPPORT (1 << 7)
100 :
101 : #define DP_RECEIVE_PORT_0_CAP_0 0x008
102 : # define DP_LOCAL_EDID_PRESENT (1 << 1)
103 : # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
104 :
105 : #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
106 :
107 : #define DP_RECEIVE_PORT_1_CAP_0 0x00a
108 : #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
109 :
110 : #define DP_I2C_SPEED_CAP 0x00c /* DPI */
111 : # define DP_I2C_SPEED_1K 0x01
112 : # define DP_I2C_SPEED_5K 0x02
113 : # define DP_I2C_SPEED_10K 0x04
114 : # define DP_I2C_SPEED_100K 0x08
115 : # define DP_I2C_SPEED_400K 0x10
116 : # define DP_I2C_SPEED_1M 0x20
117 :
118 : #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
119 : # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
120 : # define DP_FRAMING_CHANGE_CAP (1 << 1)
121 : # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
122 :
123 : #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
124 :
125 : #define DP_ADAPTER_CAP 0x00f /* 1.2 */
126 : # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
127 : # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
128 :
129 : #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
130 : # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
131 :
132 : /* Multiple stream transport */
133 : #define DP_FAUX_CAP 0x020 /* 1.2 */
134 : # define DP_FAUX_CAP_1 (1 << 0)
135 :
136 : #define DP_MSTM_CAP 0x021 /* 1.2 */
137 : # define DP_MST_CAP (1 << 0)
138 :
139 : #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
140 :
141 : /* AV_SYNC_DATA_BLOCK 1.2 */
142 : #define DP_AV_GRANULARITY 0x023
143 : # define DP_AG_FACTOR_MASK (0xf << 0)
144 : # define DP_AG_FACTOR_3MS (0 << 0)
145 : # define DP_AG_FACTOR_2MS (1 << 0)
146 : # define DP_AG_FACTOR_1MS (2 << 0)
147 : # define DP_AG_FACTOR_500US (3 << 0)
148 : # define DP_AG_FACTOR_200US (4 << 0)
149 : # define DP_AG_FACTOR_100US (5 << 0)
150 : # define DP_AG_FACTOR_10US (6 << 0)
151 : # define DP_AG_FACTOR_1US (7 << 0)
152 : # define DP_VG_FACTOR_MASK (0xf << 4)
153 : # define DP_VG_FACTOR_3MS (0 << 4)
154 : # define DP_VG_FACTOR_2MS (1 << 4)
155 : # define DP_VG_FACTOR_1MS (2 << 4)
156 : # define DP_VG_FACTOR_500US (3 << 4)
157 : # define DP_VG_FACTOR_200US (4 << 4)
158 : # define DP_VG_FACTOR_100US (5 << 4)
159 :
160 : #define DP_AUD_DEC_LAT0 0x024
161 : #define DP_AUD_DEC_LAT1 0x025
162 :
163 : #define DP_AUD_PP_LAT0 0x026
164 : #define DP_AUD_PP_LAT1 0x027
165 :
166 : #define DP_VID_INTER_LAT 0x028
167 :
168 : #define DP_VID_PROG_LAT 0x029
169 :
170 : #define DP_REP_LAT 0x02a
171 :
172 : #define DP_AUD_DEL_INS0 0x02b
173 : #define DP_AUD_DEL_INS1 0x02c
174 : #define DP_AUD_DEL_INS2 0x02d
175 : /* End of AV_SYNC_DATA_BLOCK */
176 :
177 : #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
178 : # define DP_ALPM_CAP (1 << 0)
179 :
180 : #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
181 : # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
182 :
183 : #define DP_GUID 0x030 /* 1.2 */
184 :
185 : #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
186 : # define DP_PSR_IS_SUPPORTED 1
187 : # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
188 :
189 : #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
190 : # define DP_PSR_NO_TRAIN_ON_EXIT 1
191 : # define DP_PSR_SETUP_TIME_330 (0 << 1)
192 : # define DP_PSR_SETUP_TIME_275 (1 << 1)
193 : # define DP_PSR_SETUP_TIME_220 (2 << 1)
194 : # define DP_PSR_SETUP_TIME_165 (3 << 1)
195 : # define DP_PSR_SETUP_TIME_110 (4 << 1)
196 : # define DP_PSR_SETUP_TIME_55 (5 << 1)
197 : # define DP_PSR_SETUP_TIME_0 (6 << 1)
198 : # define DP_PSR_SETUP_TIME_MASK (7 << 1)
199 : # define DP_PSR_SETUP_TIME_SHIFT 1
200 :
201 : /*
202 : * 0x80-0x8f describe downstream port capabilities, but there are two layouts
203 : * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
204 : * each port's descriptor is one byte wide. If it was set, each port's is
205 : * four bytes wide, starting with the one byte from the base info. As of
206 : * DP interop v1.1a only VGA defines additional detail.
207 : */
208 :
209 : /* offset 0 */
210 : #define DP_DOWNSTREAM_PORT_0 0x80
211 : # define DP_DS_PORT_TYPE_MASK (7 << 0)
212 : # define DP_DS_PORT_TYPE_DP 0
213 : # define DP_DS_PORT_TYPE_VGA 1
214 : # define DP_DS_PORT_TYPE_DVI 2
215 : # define DP_DS_PORT_TYPE_HDMI 3
216 : # define DP_DS_PORT_TYPE_NON_EDID 4
217 : # define DP_DS_PORT_HPD (1 << 3)
218 : /* offset 1 for VGA is maximum megapixels per second / 8 */
219 : /* offset 2 */
220 : # define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
221 : # define DP_DS_VGA_8BPC 0
222 : # define DP_DS_VGA_10BPC 1
223 : # define DP_DS_VGA_12BPC 2
224 : # define DP_DS_VGA_16BPC 3
225 :
226 : /* link configuration */
227 : #define DP_LINK_BW_SET 0x100
228 : # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
229 : # define DP_LINK_BW_1_62 0x06
230 : # define DP_LINK_BW_2_7 0x0a
231 : # define DP_LINK_BW_5_4 0x14 /* 1.2 */
232 :
233 : #define DP_LANE_COUNT_SET 0x101
234 : # define DP_LANE_COUNT_MASK 0x0f
235 : # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
236 :
237 : #define DP_TRAINING_PATTERN_SET 0x102
238 : # define DP_TRAINING_PATTERN_DISABLE 0
239 : # define DP_TRAINING_PATTERN_1 1
240 : # define DP_TRAINING_PATTERN_2 2
241 : # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
242 : # define DP_TRAINING_PATTERN_MASK 0x3
243 :
244 : /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
245 : # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
246 : # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
247 : # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
248 : # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
249 : # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
250 :
251 : # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
252 : # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
253 :
254 : # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
255 : # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
256 : # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
257 : # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
258 :
259 : #define DP_TRAINING_LANE0_SET 0x103
260 : #define DP_TRAINING_LANE1_SET 0x104
261 : #define DP_TRAINING_LANE2_SET 0x105
262 : #define DP_TRAINING_LANE3_SET 0x106
263 :
264 : # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
265 : # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
266 : # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
267 : # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
268 : # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
269 : # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
270 : # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
271 :
272 : # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
273 : # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
274 : # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
275 : # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
276 : # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
277 :
278 : # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
279 : # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
280 :
281 : #define DP_DOWNSPREAD_CTRL 0x107
282 : # define DP_SPREAD_AMP_0_5 (1 << 4)
283 : # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
284 :
285 : #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
286 : # define DP_SET_ANSI_8B10B (1 << 0)
287 :
288 : #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
289 : /* bitmask as for DP_I2C_SPEED_CAP */
290 :
291 : #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
292 : # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
293 : # define DP_FRAMING_CHANGE_ENABLE (1 << 1)
294 : # define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
295 :
296 : #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
297 : #define DP_LINK_QUAL_LANE1_SET 0x10c
298 : #define DP_LINK_QUAL_LANE2_SET 0x10d
299 : #define DP_LINK_QUAL_LANE3_SET 0x10e
300 : # define DP_LINK_QUAL_PATTERN_DISABLE 0
301 : # define DP_LINK_QUAL_PATTERN_D10_2 1
302 : # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
303 : # define DP_LINK_QUAL_PATTERN_PRBS7 3
304 : # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
305 : # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
306 : # define DP_LINK_QUAL_PATTERN_MASK 7
307 :
308 : #define DP_TRAINING_LANE0_1_SET2 0x10f
309 : #define DP_TRAINING_LANE2_3_SET2 0x110
310 : # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
311 : # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
312 : # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
313 : # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
314 :
315 : #define DP_MSTM_CTRL 0x111 /* 1.2 */
316 : # define DP_MST_EN (1 << 0)
317 : # define DP_UP_REQ_EN (1 << 1)
318 : # define DP_UPSTREAM_IS_SRC (1 << 2)
319 :
320 : #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
321 : #define DP_AUDIO_DELAY1 0x113
322 : #define DP_AUDIO_DELAY2 0x114
323 :
324 : #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
325 : # define DP_LINK_RATE_SET_SHIFT 0
326 : # define DP_LINK_RATE_SET_MASK (7 << 0)
327 :
328 : #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
329 : # define DP_ALPM_ENABLE (1 << 0)
330 : # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
331 :
332 : #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
333 : # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
334 : # define DP_IRQ_HPD_ENABLE (1 << 1)
335 :
336 : #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
337 : # define DP_PWR_NOT_NEEDED (1 << 0)
338 :
339 : #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
340 : # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
341 :
342 : #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
343 : # define DP_PSR_ENABLE (1 << 0)
344 : # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
345 : # define DP_PSR_CRC_VERIFICATION (1 << 2)
346 : # define DP_PSR_FRAME_CAPTURE (1 << 3)
347 : # define DP_PSR_SELECTIVE_UPDATE (1 << 4)
348 : # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
349 : # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
350 :
351 : #define DP_ADAPTER_CTRL 0x1a0
352 : # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
353 :
354 : #define DP_BRANCH_DEVICE_CTRL 0x1a1
355 : # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
356 :
357 : #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
358 : #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
359 : #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
360 :
361 : #define DP_SINK_COUNT 0x200
362 : /* prior to 1.2 bit 7 was reserved mbz */
363 : # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
364 : # define DP_SINK_CP_READY (1 << 6)
365 :
366 : #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
367 : # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
368 : # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
369 : # define DP_CP_IRQ (1 << 2)
370 : # define DP_MCCS_IRQ (1 << 3)
371 : # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
372 : # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
373 : # define DP_SINK_SPECIFIC_IRQ (1 << 6)
374 :
375 : #define DP_LANE0_1_STATUS 0x202
376 : #define DP_LANE2_3_STATUS 0x203
377 : # define DP_LANE_CR_DONE (1 << 0)
378 : # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
379 : # define DP_LANE_SYMBOL_LOCKED (1 << 2)
380 :
381 : #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
382 : DP_LANE_CHANNEL_EQ_DONE | \
383 : DP_LANE_SYMBOL_LOCKED)
384 :
385 : #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
386 :
387 : #define DP_INTERLANE_ALIGN_DONE (1 << 0)
388 : #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
389 : #define DP_LINK_STATUS_UPDATED (1 << 7)
390 :
391 : #define DP_SINK_STATUS 0x205
392 :
393 : #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
394 : #define DP_RECEIVE_PORT_1_STATUS (1 << 1)
395 :
396 : #define DP_ADJUST_REQUEST_LANE0_1 0x206
397 : #define DP_ADJUST_REQUEST_LANE2_3 0x207
398 : # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
399 : # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
400 : # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
401 : # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
402 : # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
403 : # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
404 : # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
405 : # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
406 :
407 : #define DP_TEST_REQUEST 0x218
408 : # define DP_TEST_LINK_TRAINING (1 << 0)
409 : # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
410 : # define DP_TEST_LINK_EDID_READ (1 << 2)
411 : # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
412 : # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
413 :
414 : #define DP_TEST_LINK_RATE 0x219
415 : # define DP_LINK_RATE_162 (0x6)
416 : # define DP_LINK_RATE_27 (0xa)
417 :
418 : #define DP_TEST_LANE_COUNT 0x220
419 :
420 : #define DP_TEST_PATTERN 0x221
421 :
422 : #define DP_TEST_CRC_R_CR 0x240
423 : #define DP_TEST_CRC_G_Y 0x242
424 : #define DP_TEST_CRC_B_CB 0x244
425 :
426 : #define DP_TEST_SINK_MISC 0x246
427 : # define DP_TEST_CRC_SUPPORTED (1 << 5)
428 : # define DP_TEST_COUNT_MASK 0xf
429 :
430 : #define DP_TEST_RESPONSE 0x260
431 : # define DP_TEST_ACK (1 << 0)
432 : # define DP_TEST_NAK (1 << 1)
433 : # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
434 :
435 : #define DP_TEST_EDID_CHECKSUM 0x261
436 :
437 : #define DP_TEST_SINK 0x270
438 : # define DP_TEST_SINK_START (1 << 0)
439 :
440 : #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
441 : # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
442 : # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
443 :
444 : #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
445 : /* up to ID_SLOT_63 at 0x2ff */
446 :
447 : #define DP_SOURCE_OUI 0x300
448 : #define DP_SINK_OUI 0x400
449 : #define DP_BRANCH_OUI 0x500
450 :
451 : #define DP_SET_POWER 0x600
452 : # define DP_SET_POWER_D0 0x1
453 : # define DP_SET_POWER_D3 0x2
454 : # define DP_SET_POWER_MASK 0x3
455 :
456 : #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
457 : # define DP_EDP_11 0x00
458 : # define DP_EDP_12 0x01
459 : # define DP_EDP_13 0x02
460 : # define DP_EDP_14 0x03
461 :
462 : #define DP_EDP_GENERAL_CAP_1 0x701
463 :
464 : #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
465 :
466 : #define DP_EDP_GENERAL_CAP_2 0x703
467 :
468 : #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
469 :
470 : #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
471 :
472 : #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
473 :
474 : #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
475 : #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
476 :
477 : #define DP_EDP_PWMGEN_BIT_COUNT 0x724
478 : #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
479 : #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
480 :
481 : #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
482 :
483 : #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
484 :
485 : #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
486 : #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
487 : #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
488 :
489 : #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
490 : #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
491 : #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
492 :
493 : #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
494 : #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
495 :
496 : #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
497 : #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
498 :
499 : #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
500 : #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
501 : #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
502 : #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
503 :
504 : #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
505 : /* 0-5 sink count */
506 : # define DP_SINK_COUNT_CP_READY (1 << 6)
507 :
508 : #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
509 :
510 : #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
511 :
512 : #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
513 :
514 : #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
515 : # define DP_PSR_LINK_CRC_ERROR (1 << 0)
516 : # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
517 : # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
518 :
519 : #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
520 : # define DP_PSR_CAPS_CHANGE (1 << 0)
521 :
522 : #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
523 : # define DP_PSR_SINK_INACTIVE 0
524 : # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
525 : # define DP_PSR_SINK_ACTIVE_RFB 2
526 : # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
527 : # define DP_PSR_SINK_ACTIVE_RESYNC 4
528 : # define DP_PSR_SINK_INTERNAL_ERROR 7
529 : # define DP_PSR_SINK_STATE_MASK 0x07
530 :
531 : #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
532 : # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
533 :
534 : /* DP 1.2 Sideband message defines */
535 : /* peer device type - DP 1.2a Table 2-92 */
536 : #define DP_PEER_DEVICE_NONE 0x0
537 : #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
538 : #define DP_PEER_DEVICE_MST_BRANCHING 0x2
539 : #define DP_PEER_DEVICE_SST_SINK 0x3
540 : #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
541 :
542 : /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
543 : #define DP_LINK_ADDRESS 0x01
544 : #define DP_CONNECTION_STATUS_NOTIFY 0x02
545 : #define DP_ENUM_PATH_RESOURCES 0x10
546 : #define DP_ALLOCATE_PAYLOAD 0x11
547 : #define DP_QUERY_PAYLOAD 0x12
548 : #define DP_RESOURCE_STATUS_NOTIFY 0x13
549 : #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
550 : #define DP_REMOTE_DPCD_READ 0x20
551 : #define DP_REMOTE_DPCD_WRITE 0x21
552 : #define DP_REMOTE_I2C_READ 0x22
553 : #define DP_REMOTE_I2C_WRITE 0x23
554 : #define DP_POWER_UP_PHY 0x24
555 : #define DP_POWER_DOWN_PHY 0x25
556 : #define DP_SINK_EVENT_NOTIFY 0x30
557 : #define DP_QUERY_STREAM_ENC_STATUS 0x38
558 :
559 : /* DP 1.2 MST sideband nak reasons - table 2.84 */
560 : #define DP_NAK_WRITE_FAILURE 0x01
561 : #define DP_NAK_INVALID_READ 0x02
562 : #define DP_NAK_CRC_FAILURE 0x03
563 : #define DP_NAK_BAD_PARAM 0x04
564 : #define DP_NAK_DEFER 0x05
565 : #define DP_NAK_LINK_FAILURE 0x06
566 : #define DP_NAK_NO_RESOURCES 0x07
567 : #define DP_NAK_DPCD_FAIL 0x08
568 : #define DP_NAK_I2C_NAK 0x09
569 : #define DP_NAK_ALLOCATE_FAIL 0x0a
570 :
571 : #define MODE_I2C_START 1
572 : #define MODE_I2C_WRITE 2
573 : #define MODE_I2C_READ 4
574 : #define MODE_I2C_STOP 8
575 :
576 : /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
577 : #define DP_MST_PHYSICAL_PORT_0 0
578 : #define DP_MST_LOGICAL_PORT_0 8
579 :
580 : #define DP_LINK_STATUS_SIZE 6
581 : bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
582 : int lane_count);
583 : bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
584 : int lane_count);
585 : u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
586 : int lane);
587 : u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
588 : int lane);
589 :
590 : #define DP_BRANCH_OUI_HEADER_SIZE 0xc
591 : #define DP_RECEIVER_CAP_SIZE 0xf
592 : #define EDP_PSR_RECEIVER_CAP_SIZE 2
593 :
594 : void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
595 : void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
596 :
597 : u8 drm_dp_link_rate_to_bw_code(int link_rate);
598 : int drm_dp_bw_code_to_link_rate(u8 link_bw);
599 :
600 : struct edp_sdp_header {
601 : u8 HB0; /* Secondary Data Packet ID */
602 : u8 HB1; /* Secondary Data Packet Type */
603 : u8 HB2; /* 7:5 reserved, 4:0 revision number */
604 : u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
605 : } __packed;
606 :
607 : #define EDP_SDP_HEADER_REVISION_MASK 0x1F
608 : #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
609 :
610 : struct edp_vsc_psr {
611 : struct edp_sdp_header sdp_header;
612 : u8 DB0; /* Stereo Interface */
613 : u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
614 : u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
615 : u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
616 : u8 DB4; /* CRC value bits 7:0 of the G or Y component */
617 : u8 DB5; /* CRC value bits 15:8 of the G or Y component */
618 : u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
619 : u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
620 : u8 DB8_31[24]; /* Reserved */
621 : } __packed;
622 :
623 : #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
624 : #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
625 : #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
626 :
627 : static inline int
628 0 : drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
629 : {
630 0 : return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
631 : }
632 :
633 : static inline u8
634 0 : drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
635 : {
636 0 : return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
637 : }
638 :
639 : static inline bool
640 0 : drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
641 : {
642 0 : return dpcd[DP_DPCD_REV] >= 0x11 &&
643 0 : (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
644 : }
645 :
646 : static inline bool
647 0 : drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
648 : {
649 0 : return dpcd[DP_DPCD_REV] >= 0x12 &&
650 0 : dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
651 : }
652 :
653 : /*
654 : * DisplayPort AUX channel
655 : */
656 :
657 : /**
658 : * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
659 : * @address: address of the (first) register to access
660 : * @request: contains the type of transaction (see DP_AUX_* macros)
661 : * @reply: upon completion, contains the reply type of the transaction
662 : * @buffer: pointer to a transmission or reception buffer
663 : * @size: size of @buffer
664 : */
665 : struct drm_dp_aux_msg {
666 : unsigned int address;
667 : u8 request;
668 : u8 reply;
669 : void *buffer;
670 : size_t size;
671 : };
672 :
673 : /**
674 : * struct drm_dp_aux - DisplayPort AUX channel
675 : * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
676 : * @ddc: I2C adapter that can be used for I2C-over-AUX communication
677 : * @dev: pointer to struct device that is the parent for this AUX channel
678 : * @hw_mutex: internal mutex used for locking transfers
679 : * @transfer: transfers a message representing a single AUX transaction
680 : *
681 : * The .dev field should be set to a pointer to the device that implements
682 : * the AUX channel.
683 : *
684 : * The .name field may be used to specify the name of the I2C adapter. If set to
685 : * NULL, dev_name() of .dev will be used.
686 : *
687 : * Drivers provide a hardware-specific implementation of how transactions
688 : * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
689 : * structure describing the transaction is passed into this function. Upon
690 : * success, the implementation should return the number of payload bytes
691 : * that were transferred, or a negative error-code on failure. Helpers
692 : * propagate errors from the .transfer() function, with the exception of
693 : * the -EBUSY error, which causes a transaction to be retried. On a short,
694 : * helpers will return -EPROTO to make it simpler to check for failure.
695 : *
696 : * An AUX channel can also be used to transport I2C messages to a sink. A
697 : * typical application of that is to access an EDID that's present in the
698 : * sink device. The .transfer() function can also be used to execute such
699 : * transactions. The drm_dp_aux_register() function registers an I2C
700 : * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
701 : * should call drm_dp_aux_unregister() to remove the I2C adapter.
702 : * The I2C adapter uses long transfers by default; if a partial response is
703 : * received, the adapter will drop down to the size given by the partial
704 : * response for this transaction only.
705 : *
706 : * Note that the aux helper code assumes that the .transfer() function
707 : * only modifies the reply field of the drm_dp_aux_msg structure. The
708 : * retry logic and i2c helpers assume this is the case.
709 : */
710 : struct drm_dp_aux {
711 : const char *name;
712 : struct i2c_adapter ddc;
713 : struct device *dev;
714 : struct rwlock hw_mutex;
715 : ssize_t (*transfer)(struct drm_dp_aux *aux,
716 : struct drm_dp_aux_msg *msg);
717 : unsigned i2c_nack_count, i2c_defer_count;
718 : };
719 :
720 : ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
721 : void *buffer, size_t size);
722 : ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
723 : void *buffer, size_t size);
724 :
725 : /**
726 : * drm_dp_dpcd_readb() - read a single byte from the DPCD
727 : * @aux: DisplayPort AUX channel
728 : * @offset: address of the register to read
729 : * @valuep: location where the value of the register will be stored
730 : *
731 : * Returns the number of bytes transferred (1) on success, or a negative
732 : * error code on failure.
733 : */
734 0 : static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
735 : unsigned int offset, u8 *valuep)
736 : {
737 0 : return drm_dp_dpcd_read(aux, offset, valuep, 1);
738 : }
739 :
740 : /**
741 : * drm_dp_dpcd_writeb() - write a single byte to the DPCD
742 : * @aux: DisplayPort AUX channel
743 : * @offset: address of the register to write
744 : * @value: value to write to the register
745 : *
746 : * Returns the number of bytes transferred (1) on success, or a negative
747 : * error code on failure.
748 : */
749 0 : static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
750 : unsigned int offset, u8 value)
751 : {
752 0 : return drm_dp_dpcd_write(aux, offset, &value, 1);
753 : }
754 :
755 : int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
756 : u8 status[DP_LINK_STATUS_SIZE]);
757 :
758 : /*
759 : * DisplayPort link
760 : */
761 : #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
762 :
763 : struct drm_dp_link {
764 : unsigned char revision;
765 : unsigned int rate;
766 : unsigned int num_lanes;
767 : unsigned long capabilities;
768 : };
769 :
770 : int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
771 : int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
772 : int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
773 : int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
774 :
775 : int drm_dp_aux_register(struct drm_dp_aux *aux);
776 : void drm_dp_aux_unregister(struct drm_dp_aux *aux);
777 :
778 : #endif /* _DRM_DP_HELPER_H_ */
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