Line data Source code
1 : /*
2 : * Copyright © 2011-2012 Intel Corporation
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice (including the next
12 : * paragraph) shall be included in all copies or substantial portions of the
13 : * Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 : * IN THE SOFTWARE.
22 : *
23 : * Authors:
24 : * Ben Widawsky <ben@bwidawsk.net>
25 : *
26 : */
27 :
28 : /*
29 : * This file implements HW context support. On gen5+ a HW context consists of an
30 : * opaque GPU object which is referenced at times of context saves and restores.
31 : * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 : * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 : * something like a context does exist for the media ring, the code only
34 : * supports contexts for the render ring.
35 : *
36 : * In software, there is a distinction between contexts created by the user,
37 : * and the default HW context. The default HW context is used by GPU clients
38 : * that do not request setup of their own hardware context. The default
39 : * context's state is never restored to help prevent programming errors. This
40 : * would happen if a client ran and piggy-backed off another clients GPU state.
41 : * The default context only exists to give the GPU some offset to load as the
42 : * current to invoke a save of the context we actually care about. In fact, the
43 : * code could likely be constructed, albeit in a more complicated fashion, to
44 : * never use the default context, though that limits the driver's ability to
45 : * swap out, and/or destroy other contexts.
46 : *
47 : * All other contexts are created as a request by the GPU client. These contexts
48 : * store GPU state, and thus allow GPU clients to not re-emit state (and
49 : * potentially query certain state) at any time. The kernel driver makes
50 : * certain that the appropriate commands are inserted.
51 : *
52 : * The context life cycle is semi-complicated in that context BOs may live
53 : * longer than the context itself because of the way the hardware, and object
54 : * tracking works. Below is a very crude representation of the state machine
55 : * describing the context life.
56 : * refcount pincount active
57 : * S0: initial state 0 0 0
58 : * S1: context created 1 0 0
59 : * S2: context is currently running 2 1 X
60 : * S3: GPU referenced, but not current 2 0 1
61 : * S4: context is current, but destroyed 1 1 0
62 : * S5: like S3, but destroyed 1 0 1
63 : *
64 : * The most common (but not all) transitions:
65 : * S0->S1: client creates a context
66 : * S1->S2: client submits execbuf with context
67 : * S2->S3: other clients submits execbuf with context
68 : * S3->S1: context object was retired
69 : * S3->S2: clients submits another execbuf
70 : * S2->S4: context destroy called with current context
71 : * S3->S5->S0: destroy path
72 : * S4->S5->S0: destroy path on current context
73 : *
74 : * There are two confusing terms used above:
75 : * The "current context" means the context which is currently running on the
76 : * GPU. The GPU has loaded its state already and has stored away the gtt
77 : * offset of the BO. The GPU is not actively referencing the data at this
78 : * offset, but it will on the next context switch. The only way to avoid this
79 : * is to do a GPU reset.
80 : *
81 : * An "active context' is one which was previously the "current context" and is
82 : * on the active list waiting for the next context switch to occur. Until this
83 : * happens, the object must remain at the same gtt offset. It is therefore
84 : * possible to destroy a context, but it is still active.
85 : *
86 : */
87 :
88 : #include <dev/pci/drm/drmP.h>
89 : #include <dev/pci/drm/i915_drm.h>
90 : #include "i915_drv.h"
91 : #include "i915_trace.h"
92 :
93 : /* This is a HW constraint. The value below is the largest known requirement
94 : * I've seen in a spec to date, and that was a workaround for a non-shipping
95 : * part. It should be safe to decrease this, but it's more future proof as is.
96 : */
97 : #define GEN6_CONTEXT_ALIGN (64<<10)
98 : #define GEN7_CONTEXT_ALIGN 4096
99 :
100 0 : static size_t get_context_alignment(struct drm_device *dev)
101 : {
102 0 : if (IS_GEN6(dev))
103 0 : return GEN6_CONTEXT_ALIGN;
104 :
105 0 : return GEN7_CONTEXT_ALIGN;
106 0 : }
107 :
108 0 : static int get_context_size(struct drm_device *dev)
109 : {
110 0 : struct drm_i915_private *dev_priv = dev->dev_private;
111 : int ret;
112 : u32 reg;
113 :
114 0 : switch (INTEL_INFO(dev)->gen) {
115 : case 6:
116 0 : reg = I915_READ(CXT_SIZE);
117 0 : ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
118 0 : break;
119 : case 7:
120 0 : reg = I915_READ(GEN7_CXT_SIZE);
121 0 : if (IS_HASWELL(dev))
122 0 : ret = HSW_CXT_TOTAL_SIZE;
123 : else
124 0 : ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
125 : break;
126 : case 8:
127 : ret = GEN8_CXT_TOTAL_SIZE;
128 0 : break;
129 : default:
130 0 : BUG();
131 : }
132 :
133 0 : return ret;
134 : }
135 :
136 0 : static void i915_gem_context_clean(struct intel_context *ctx)
137 : {
138 0 : struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
139 : struct i915_vma *vma, *next;
140 :
141 0 : if (!ppgtt)
142 0 : return;
143 :
144 0 : list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
145 : mm_list) {
146 0 : if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
147 : break;
148 : }
149 0 : }
150 :
151 0 : void i915_gem_context_free(struct kref *ctx_ref)
152 : {
153 0 : struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
154 :
155 0 : trace_i915_context_free(ctx);
156 :
157 0 : if (i915.enable_execlists)
158 0 : intel_lr_context_free(ctx);
159 :
160 : /*
161 : * This context is going away and we need to remove all VMAs still
162 : * around. This is to handle imported shared objects for which
163 : * destructor did not run when their handles were closed.
164 : */
165 0 : i915_gem_context_clean(ctx);
166 :
167 0 : i915_ppgtt_put(ctx->ppgtt);
168 :
169 0 : if (ctx->legacy_hw_ctx.rcs_state)
170 0 : drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
171 0 : list_del(&ctx->link);
172 0 : kfree(ctx);
173 0 : }
174 :
175 : struct drm_i915_gem_object *
176 0 : i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
177 : {
178 : struct drm_i915_gem_object *obj;
179 : int ret;
180 :
181 0 : obj = i915_gem_alloc_object(dev, size);
182 0 : if (obj == NULL)
183 0 : return ERR_PTR(-ENOMEM);
184 :
185 : /*
186 : * Try to make the context utilize L3 as well as LLC.
187 : *
188 : * On VLV we don't have L3 controls in the PTEs so we
189 : * shouldn't touch the cache level, especially as that
190 : * would make the object snooped which might have a
191 : * negative performance impact.
192 : */
193 0 : if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
194 0 : ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
195 : /* Failure shouldn't ever happen this early */
196 0 : if (WARN_ON(ret)) {
197 0 : drm_gem_object_unreference(&obj->base);
198 0 : return ERR_PTR(ret);
199 : }
200 : }
201 :
202 0 : return obj;
203 0 : }
204 :
205 : static struct intel_context *
206 0 : __create_hw_context(struct drm_device *dev,
207 : struct drm_i915_file_private *file_priv)
208 : {
209 0 : struct drm_i915_private *dev_priv = dev->dev_private;
210 : struct intel_context *ctx;
211 : int ret;
212 :
213 0 : ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
214 0 : if (ctx == NULL)
215 0 : return ERR_PTR(-ENOMEM);
216 :
217 0 : kref_init(&ctx->ref);
218 0 : list_add_tail(&ctx->link, &dev_priv->context_list);
219 0 : ctx->i915 = dev_priv;
220 :
221 0 : if (dev_priv->hw_context_size) {
222 : struct drm_i915_gem_object *obj =
223 0 : i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
224 0 : if (IS_ERR(obj)) {
225 0 : ret = PTR_ERR(obj);
226 0 : goto err_out;
227 : }
228 0 : ctx->legacy_hw_ctx.rcs_state = obj;
229 0 : }
230 :
231 : /* Default context will never have a file_priv */
232 0 : if (file_priv != NULL) {
233 0 : ret = idr_alloc(&file_priv->context_idr, ctx,
234 : DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
235 0 : if (ret < 0)
236 : goto err_out;
237 : } else
238 : ret = DEFAULT_CONTEXT_HANDLE;
239 :
240 0 : ctx->file_priv = file_priv;
241 0 : ctx->user_handle = ret;
242 : /* NB: Mark all slices as needing a remap so that when the context first
243 : * loads it will restore whatever remap state already exists. If there
244 : * is no remap info, it will be a NOP. */
245 0 : ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
246 :
247 0 : ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
248 :
249 0 : return ctx;
250 :
251 : err_out:
252 0 : i915_gem_context_unreference(ctx);
253 0 : return ERR_PTR(ret);
254 0 : }
255 :
256 : /**
257 : * The default context needs to exist per ring that uses contexts. It stores the
258 : * context state of the GPU for applications that don't utilize HW contexts, as
259 : * well as an idle case.
260 : */
261 : static struct intel_context *
262 0 : i915_gem_create_context(struct drm_device *dev,
263 : struct drm_i915_file_private *file_priv)
264 : {
265 0 : const bool is_global_default_ctx = file_priv == NULL;
266 : struct intel_context *ctx;
267 : int ret = 0;
268 :
269 0 : BUG_ON(!mutex_is_locked(&dev->struct_mutex));
270 :
271 0 : ctx = __create_hw_context(dev, file_priv);
272 0 : if (IS_ERR(ctx))
273 0 : return ctx;
274 :
275 0 : if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) {
276 : /* We may need to do things with the shrinker which
277 : * require us to immediately switch back to the default
278 : * context. This can cause a problem as pinning the
279 : * default context also requires GTT space which may not
280 : * be available. To avoid this we always pin the default
281 : * context.
282 : */
283 0 : ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
284 0 : get_context_alignment(dev), 0);
285 0 : if (ret) {
286 : DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
287 : goto err_destroy;
288 : }
289 : }
290 :
291 0 : if (USES_FULL_PPGTT(dev)) {
292 0 : struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
293 :
294 0 : if (IS_ERR_OR_NULL(ppgtt)) {
295 : DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
296 : PTR_ERR(ppgtt));
297 0 : ret = PTR_ERR(ppgtt);
298 0 : goto err_unpin;
299 : }
300 :
301 0 : ctx->ppgtt = ppgtt;
302 0 : }
303 :
304 0 : trace_i915_context_create(ctx);
305 :
306 0 : return ctx;
307 :
308 : err_unpin:
309 0 : if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state)
310 0 : i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state);
311 : err_destroy:
312 0 : idr_remove(&file_priv->context_idr, ctx->user_handle);
313 0 : i915_gem_context_unreference(ctx);
314 0 : return ERR_PTR(ret);
315 0 : }
316 :
317 0 : void i915_gem_context_reset(struct drm_device *dev)
318 : {
319 0 : struct drm_i915_private *dev_priv = dev->dev_private;
320 : int i;
321 :
322 0 : if (i915.enable_execlists) {
323 : struct intel_context *ctx;
324 :
325 0 : list_for_each_entry(ctx, &dev_priv->context_list, link) {
326 0 : intel_lr_context_reset(dev, ctx);
327 : }
328 :
329 : return;
330 : }
331 :
332 0 : for (i = 0; i < I915_NUM_RINGS; i++) {
333 0 : struct intel_engine_cs *ring = &dev_priv->ring[i];
334 0 : struct intel_context *lctx = ring->last_context;
335 :
336 0 : if (lctx) {
337 0 : if (lctx->legacy_hw_ctx.rcs_state && i == RCS)
338 0 : i915_gem_object_ggtt_unpin(lctx->legacy_hw_ctx.rcs_state);
339 :
340 0 : i915_gem_context_unreference(lctx);
341 0 : ring->last_context = NULL;
342 0 : }
343 :
344 : /* Force the GPU state to be reinitialised on enabling */
345 0 : if (ring->default_context)
346 0 : ring->default_context->legacy_hw_ctx.initialized = false;
347 : }
348 0 : }
349 :
350 0 : int i915_gem_context_init(struct drm_device *dev)
351 : {
352 0 : struct drm_i915_private *dev_priv = dev->dev_private;
353 : struct intel_context *ctx;
354 : int i;
355 :
356 : /* Init should only be called once per module load. Eventually the
357 : * restriction on the context_disabled check can be loosened. */
358 0 : if (WARN_ON(dev_priv->ring[RCS].default_context))
359 0 : return 0;
360 :
361 0 : if (intel_vgpu_active(dev) && HAS_LOGICAL_RING_CONTEXTS(dev)) {
362 0 : if (!i915.enable_execlists) {
363 : DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
364 0 : return -EINVAL;
365 : }
366 : }
367 :
368 0 : if (i915.enable_execlists) {
369 : /* NB: intentionally left blank. We will allocate our own
370 : * backing objects as we need them, thank you very much */
371 0 : dev_priv->hw_context_size = 0;
372 0 : } else if (HAS_HW_CONTEXTS(dev)) {
373 0 : dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
374 0 : if (dev_priv->hw_context_size > (1<<20)) {
375 : DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
376 : dev_priv->hw_context_size);
377 0 : dev_priv->hw_context_size = 0;
378 0 : }
379 : }
380 :
381 0 : ctx = i915_gem_create_context(dev, NULL);
382 0 : if (IS_ERR(ctx)) {
383 0 : DRM_ERROR("Failed to create default global context (error %ld)\n",
384 : PTR_ERR(ctx));
385 0 : return PTR_ERR(ctx);
386 : }
387 :
388 0 : for (i = 0; i < I915_NUM_RINGS; i++) {
389 0 : struct intel_engine_cs *ring = &dev_priv->ring[i];
390 :
391 : /* NB: RCS will hold a ref for all rings */
392 0 : ring->default_context = ctx;
393 : }
394 :
395 : DRM_DEBUG_DRIVER("%s context support initialized\n",
396 : i915.enable_execlists ? "LR" :
397 : dev_priv->hw_context_size ? "HW" : "fake");
398 0 : return 0;
399 0 : }
400 :
401 0 : void i915_gem_context_fini(struct drm_device *dev)
402 : {
403 0 : struct drm_i915_private *dev_priv = dev->dev_private;
404 0 : struct intel_context *dctx = dev_priv->ring[RCS].default_context;
405 : int i;
406 :
407 0 : if (dctx->legacy_hw_ctx.rcs_state) {
408 : /* The only known way to stop the gpu from accessing the hw context is
409 : * to reset it. Do this as the very last operation to avoid confusing
410 : * other code, leading to spurious errors. */
411 0 : intel_gpu_reset(dev);
412 :
413 : /* When default context is created and switched to, base object refcount
414 : * will be 2 (+1 from object creation and +1 from do_switch()).
415 : * i915_gem_context_fini() will be called after gpu_idle() has switched
416 : * to default context. So we need to unreference the base object once
417 : * to offset the do_switch part, so that i915_gem_context_unreference()
418 : * can then free the base object correctly. */
419 0 : WARN_ON(!dev_priv->ring[RCS].last_context);
420 0 : if (dev_priv->ring[RCS].last_context == dctx) {
421 : /* Fake switch to NULL context */
422 0 : WARN_ON(dctx->legacy_hw_ctx.rcs_state->active);
423 0 : i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
424 0 : i915_gem_context_unreference(dctx);
425 0 : dev_priv->ring[RCS].last_context = NULL;
426 0 : }
427 :
428 0 : i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
429 0 : }
430 :
431 0 : for (i = 0; i < I915_NUM_RINGS; i++) {
432 0 : struct intel_engine_cs *ring = &dev_priv->ring[i];
433 :
434 0 : if (ring->last_context)
435 0 : i915_gem_context_unreference(ring->last_context);
436 :
437 0 : ring->default_context = NULL;
438 0 : ring->last_context = NULL;
439 : }
440 :
441 0 : i915_gem_context_unreference(dctx);
442 0 : }
443 :
444 0 : int i915_gem_context_enable(struct drm_i915_gem_request *req)
445 : {
446 0 : struct intel_engine_cs *ring = req->ring;
447 : int ret;
448 :
449 0 : if (i915.enable_execlists) {
450 0 : if (ring->init_context == NULL)
451 0 : return 0;
452 :
453 0 : ret = ring->init_context(req);
454 0 : } else
455 0 : ret = i915_switch_context(req);
456 :
457 0 : if (ret) {
458 0 : DRM_ERROR("ring init context: %d\n", ret);
459 0 : return ret;
460 : }
461 :
462 0 : return 0;
463 0 : }
464 :
465 0 : static int context_idr_cleanup(int id, void *p, void *data)
466 : {
467 0 : struct intel_context *ctx = p;
468 :
469 0 : i915_gem_context_unreference(ctx);
470 0 : return 0;
471 : }
472 :
473 0 : int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
474 : {
475 0 : struct drm_i915_file_private *file_priv = file->driver_priv;
476 : struct intel_context *ctx;
477 :
478 0 : idr_init(&file_priv->context_idr);
479 :
480 0 : mutex_lock(&dev->struct_mutex);
481 0 : ctx = i915_gem_create_context(dev, file_priv);
482 0 : mutex_unlock(&dev->struct_mutex);
483 :
484 0 : if (IS_ERR(ctx)) {
485 0 : idr_destroy(&file_priv->context_idr);
486 0 : return PTR_ERR(ctx);
487 : }
488 :
489 0 : return 0;
490 0 : }
491 :
492 0 : void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
493 : {
494 0 : struct drm_i915_file_private *file_priv = file->driver_priv;
495 :
496 0 : idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
497 0 : idr_destroy(&file_priv->context_idr);
498 0 : }
499 :
500 : struct intel_context *
501 0 : i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
502 : {
503 : struct intel_context *ctx;
504 :
505 0 : ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id);
506 0 : if (!ctx)
507 0 : return ERR_PTR(-ENOENT);
508 :
509 0 : return ctx;
510 0 : }
511 :
512 : static inline int
513 0 : mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
514 : {
515 0 : struct intel_engine_cs *ring = req->ring;
516 0 : u32 flags = hw_flags | MI_MM_SPACE_GTT;
517 : const int num_rings =
518 : /* Use an extended w/a on ivb+ if signalling from other rings */
519 0 : i915_semaphore_is_enabled(ring->dev) ?
520 0 : hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
521 : 0;
522 : int len, i, ret;
523 :
524 : /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
525 : * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
526 : * explicitly, so we rely on the value at ring init, stored in
527 : * itlb_before_ctx_switch.
528 : */
529 0 : if (IS_GEN6(ring->dev)) {
530 0 : ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
531 0 : if (ret)
532 0 : return ret;
533 : }
534 :
535 : /* These flags are for resource streamer on HSW+ */
536 0 : if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8)
537 0 : flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
538 0 : else if (INTEL_INFO(ring->dev)->gen < 8)
539 0 : flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
540 :
541 :
542 : len = 4;
543 0 : if (INTEL_INFO(ring->dev)->gen >= 7)
544 0 : len += 2 + (num_rings ? 4*num_rings + 2 : 0);
545 :
546 0 : ret = intel_ring_begin(req, len);
547 0 : if (ret)
548 0 : return ret;
549 :
550 : /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
551 0 : if (INTEL_INFO(ring->dev)->gen >= 7) {
552 0 : intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
553 0 : if (num_rings) {
554 : struct intel_engine_cs *signaller;
555 :
556 0 : intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
557 0 : for_each_ring(signaller, to_i915(ring->dev), i) {
558 0 : if (signaller == ring)
559 : continue;
560 :
561 0 : intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
562 0 : intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
563 0 : }
564 0 : }
565 : }
566 :
567 0 : intel_ring_emit(ring, MI_NOOP);
568 0 : intel_ring_emit(ring, MI_SET_CONTEXT);
569 0 : intel_ring_emit(ring, i915_gem_obj_ggtt_offset(req->ctx->legacy_hw_ctx.rcs_state) |
570 0 : flags);
571 : /*
572 : * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
573 : * WaMiSetContext_Hang:snb,ivb,vlv
574 : */
575 0 : intel_ring_emit(ring, MI_NOOP);
576 :
577 0 : if (INTEL_INFO(ring->dev)->gen >= 7) {
578 0 : if (num_rings) {
579 : struct intel_engine_cs *signaller;
580 :
581 0 : intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
582 0 : for_each_ring(signaller, to_i915(ring->dev), i) {
583 0 : if (signaller == ring)
584 : continue;
585 :
586 0 : intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
587 0 : intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
588 0 : }
589 0 : }
590 0 : intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
591 0 : }
592 :
593 0 : intel_ring_advance(ring);
594 :
595 0 : return ret;
596 0 : }
597 :
598 0 : static inline bool should_skip_switch(struct intel_engine_cs *ring,
599 : struct intel_context *from,
600 : struct intel_context *to)
601 : {
602 0 : if (to->remap_slice)
603 0 : return false;
604 :
605 0 : if (to->ppgtt && from == to &&
606 0 : !(intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings))
607 0 : return true;
608 :
609 0 : return false;
610 0 : }
611 :
612 : static bool
613 0 : needs_pd_load_pre(struct intel_engine_cs *ring, struct intel_context *to)
614 : {
615 0 : struct drm_i915_private *dev_priv = ring->dev->dev_private;
616 :
617 0 : if (!to->ppgtt)
618 0 : return false;
619 :
620 0 : if (INTEL_INFO(ring->dev)->gen < 8)
621 0 : return true;
622 :
623 0 : if (ring != &dev_priv->ring[RCS])
624 0 : return true;
625 :
626 0 : return false;
627 0 : }
628 :
629 : static bool
630 0 : needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to,
631 : u32 hw_flags)
632 : {
633 0 : struct drm_i915_private *dev_priv = ring->dev->dev_private;
634 :
635 0 : if (!to->ppgtt)
636 0 : return false;
637 :
638 0 : if (!IS_GEN8(ring->dev))
639 0 : return false;
640 :
641 0 : if (ring != &dev_priv->ring[RCS])
642 0 : return false;
643 :
644 0 : if (hw_flags & MI_RESTORE_INHIBIT)
645 0 : return true;
646 :
647 0 : return false;
648 0 : }
649 :
650 0 : static int do_switch(struct drm_i915_gem_request *req)
651 : {
652 0 : struct intel_context *to = req->ctx;
653 0 : struct intel_engine_cs *ring = req->ring;
654 0 : struct drm_i915_private *dev_priv = ring->dev->dev_private;
655 0 : struct intel_context *from = ring->last_context;
656 : u32 hw_flags = 0;
657 : bool uninitialized = false;
658 : int ret, i;
659 :
660 0 : if (from != NULL && ring == &dev_priv->ring[RCS]) {
661 0 : BUG_ON(from->legacy_hw_ctx.rcs_state == NULL);
662 0 : BUG_ON(!i915_gem_obj_is_pinned(from->legacy_hw_ctx.rcs_state));
663 : }
664 :
665 0 : if (should_skip_switch(ring, from, to))
666 0 : return 0;
667 :
668 : /* Trying to pin first makes error handling easier. */
669 0 : if (ring == &dev_priv->ring[RCS]) {
670 0 : ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
671 0 : get_context_alignment(ring->dev), 0);
672 0 : if (ret)
673 0 : return ret;
674 : }
675 :
676 : /*
677 : * Pin can switch back to the default context if we end up calling into
678 : * evict_everything - as a last ditch gtt defrag effort that also
679 : * switches to the default context. Hence we need to reload from here.
680 : */
681 0 : from = ring->last_context;
682 :
683 0 : if (needs_pd_load_pre(ring, to)) {
684 : /* Older GENs and non render rings still want the load first,
685 : * "PP_DCLV followed by PP_DIR_BASE register through Load
686 : * Register Immediate commands in Ring Buffer before submitting
687 : * a context."*/
688 0 : trace_switch_mm(ring, to);
689 0 : ret = to->ppgtt->switch_mm(to->ppgtt, req);
690 0 : if (ret)
691 : goto unpin_out;
692 :
693 : /* Doing a PD load always reloads the page dirs */
694 0 : to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
695 0 : }
696 :
697 0 : if (ring != &dev_priv->ring[RCS]) {
698 0 : if (from)
699 0 : i915_gem_context_unreference(from);
700 : goto done;
701 : }
702 :
703 : /*
704 : * Clear this page out of any CPU caches for coherent swap-in/out. Note
705 : * that thanks to write = false in this call and us not setting any gpu
706 : * write domains when putting a context object onto the active list
707 : * (when switching away from it), this won't block.
708 : *
709 : * XXX: We need a real interface to do this instead of trickery.
710 : */
711 0 : ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false);
712 0 : if (ret)
713 : goto unpin_out;
714 :
715 0 : if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) {
716 : hw_flags |= MI_RESTORE_INHIBIT;
717 : /* NB: If we inhibit the restore, the context is not allowed to
718 : * die because future work may end up depending on valid address
719 : * space. This means we must enforce that a page table load
720 : * occur when this occurs. */
721 0 : } else if (to->ppgtt &&
722 0 : (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) {
723 : hw_flags |= MI_FORCE_RESTORE;
724 0 : to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
725 0 : }
726 :
727 : /* We should never emit switch_mm more than once */
728 0 : WARN_ON(needs_pd_load_pre(ring, to) &&
729 : needs_pd_load_post(ring, to, hw_flags));
730 :
731 0 : ret = mi_set_context(req, hw_flags);
732 0 : if (ret)
733 : goto unpin_out;
734 :
735 : /* GEN8 does *not* require an explicit reload if the PDPs have been
736 : * setup, and we do not wish to move them.
737 : */
738 0 : if (needs_pd_load_post(ring, to, hw_flags)) {
739 0 : trace_switch_mm(ring, to);
740 0 : ret = to->ppgtt->switch_mm(to->ppgtt, req);
741 : /* The hardware context switch is emitted, but we haven't
742 : * actually changed the state - so it's probably safe to bail
743 : * here. Still, let the user know something dangerous has
744 : * happened.
745 : */
746 0 : if (ret) {
747 0 : DRM_ERROR("Failed to change address space on context switch\n");
748 0 : goto unpin_out;
749 : }
750 : }
751 :
752 0 : for (i = 0; i < MAX_L3_SLICES; i++) {
753 0 : if (!(to->remap_slice & (1<<i)))
754 : continue;
755 :
756 0 : ret = i915_gem_l3_remap(req, i);
757 : /* If it failed, try again next round */
758 0 : if (ret)
759 : DRM_DEBUG_DRIVER("L3 remapping failed\n");
760 : else
761 0 : to->remap_slice &= ~(1<<i);
762 : }
763 :
764 : /* The backing object for the context is done after switching to the
765 : * *next* context. Therefore we cannot retire the previous context until
766 : * the next context has already started running. In fact, the below code
767 : * is a bit suboptimal because the retiring can occur simply after the
768 : * MI_SET_CONTEXT instead of when the next seqno has completed.
769 : */
770 0 : if (from != NULL) {
771 0 : from->legacy_hw_ctx.rcs_state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
772 0 : i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->legacy_hw_ctx.rcs_state), req);
773 : /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
774 : * whole damn pipeline, we don't need to explicitly mark the
775 : * object dirty. The only exception is that the context must be
776 : * correct in case the object gets swapped out. Ideally we'd be
777 : * able to defer doing this until we know the object would be
778 : * swapped, but there is no way to do that yet.
779 : */
780 0 : from->legacy_hw_ctx.rcs_state->dirty = 1;
781 :
782 : /* obj is kept alive until the next request by its active ref */
783 0 : i915_gem_object_ggtt_unpin(from->legacy_hw_ctx.rcs_state);
784 0 : i915_gem_context_unreference(from);
785 0 : }
786 :
787 0 : uninitialized = !to->legacy_hw_ctx.initialized;
788 0 : to->legacy_hw_ctx.initialized = true;
789 :
790 : done:
791 0 : i915_gem_context_reference(to);
792 0 : ring->last_context = to;
793 :
794 0 : if (uninitialized) {
795 0 : if (ring->init_context) {
796 0 : ret = ring->init_context(req);
797 0 : if (ret)
798 0 : DRM_ERROR("ring init context: %d\n", ret);
799 : }
800 : }
801 :
802 0 : return 0;
803 :
804 : unpin_out:
805 0 : if (ring->id == RCS)
806 0 : i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
807 0 : return ret;
808 0 : }
809 :
810 : /**
811 : * i915_switch_context() - perform a GPU context switch.
812 : * @req: request for which we'll execute the context switch
813 : *
814 : * The context life cycle is simple. The context refcount is incremented and
815 : * decremented by 1 and create and destroy. If the context is in use by the GPU,
816 : * it will have a refcount > 1. This allows us to destroy the context abstract
817 : * object while letting the normal object tracking destroy the backing BO.
818 : *
819 : * This function should not be used in execlists mode. Instead the context is
820 : * switched by writing to the ELSP and requests keep a reference to their
821 : * context.
822 : */
823 0 : int i915_switch_context(struct drm_i915_gem_request *req)
824 : {
825 0 : struct intel_engine_cs *ring = req->ring;
826 0 : struct drm_i915_private *dev_priv = ring->dev->dev_private;
827 :
828 0 : WARN_ON(i915.enable_execlists);
829 0 : WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
830 :
831 0 : if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
832 0 : if (req->ctx != ring->last_context) {
833 0 : i915_gem_context_reference(req->ctx);
834 0 : if (ring->last_context)
835 0 : i915_gem_context_unreference(ring->last_context);
836 0 : ring->last_context = req->ctx;
837 0 : }
838 0 : return 0;
839 : }
840 :
841 0 : return do_switch(req);
842 0 : }
843 :
844 0 : static bool contexts_enabled(struct drm_device *dev)
845 : {
846 0 : return i915.enable_execlists || to_i915(dev)->hw_context_size;
847 : }
848 :
849 0 : int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
850 : struct drm_file *file)
851 : {
852 0 : struct drm_i915_gem_context_create *args = data;
853 0 : struct drm_i915_file_private *file_priv = file->driver_priv;
854 : struct intel_context *ctx;
855 : int ret;
856 :
857 0 : if (!contexts_enabled(dev))
858 0 : return -ENODEV;
859 :
860 0 : ret = i915_mutex_lock_interruptible(dev);
861 0 : if (ret)
862 0 : return ret;
863 :
864 0 : ctx = i915_gem_create_context(dev, file_priv);
865 0 : mutex_unlock(&dev->struct_mutex);
866 0 : if (IS_ERR(ctx))
867 0 : return PTR_ERR(ctx);
868 :
869 0 : args->ctx_id = ctx->user_handle;
870 : DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
871 :
872 0 : return 0;
873 0 : }
874 :
875 0 : int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
876 : struct drm_file *file)
877 : {
878 0 : struct drm_i915_gem_context_destroy *args = data;
879 0 : struct drm_i915_file_private *file_priv = file->driver_priv;
880 : struct intel_context *ctx;
881 : int ret;
882 :
883 0 : if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
884 0 : return -ENOENT;
885 :
886 0 : ret = i915_mutex_lock_interruptible(dev);
887 0 : if (ret)
888 0 : return ret;
889 :
890 0 : ctx = i915_gem_context_get(file_priv, args->ctx_id);
891 0 : if (IS_ERR(ctx)) {
892 0 : mutex_unlock(&dev->struct_mutex);
893 0 : return PTR_ERR(ctx);
894 : }
895 :
896 0 : idr_remove(&ctx->file_priv->context_idr, ctx->user_handle);
897 0 : i915_gem_context_unreference(ctx);
898 0 : mutex_unlock(&dev->struct_mutex);
899 :
900 : DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
901 0 : return 0;
902 0 : }
903 :
904 0 : int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
905 : struct drm_file *file)
906 : {
907 0 : struct drm_i915_file_private *file_priv = file->driver_priv;
908 0 : struct drm_i915_gem_context_param *args = data;
909 : struct intel_context *ctx;
910 : int ret;
911 :
912 0 : ret = i915_mutex_lock_interruptible(dev);
913 0 : if (ret)
914 0 : return ret;
915 :
916 0 : ctx = i915_gem_context_get(file_priv, args->ctx_id);
917 0 : if (IS_ERR(ctx)) {
918 0 : mutex_unlock(&dev->struct_mutex);
919 0 : return PTR_ERR(ctx);
920 : }
921 :
922 0 : args->size = 0;
923 0 : switch (args->param) {
924 : case I915_CONTEXT_PARAM_BAN_PERIOD:
925 0 : args->value = ctx->hang_stats.ban_period_seconds;
926 0 : break;
927 : case I915_CONTEXT_PARAM_NO_ZEROMAP:
928 0 : args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
929 0 : break;
930 : default:
931 : ret = -EINVAL;
932 0 : break;
933 : }
934 0 : mutex_unlock(&dev->struct_mutex);
935 :
936 0 : return ret;
937 0 : }
938 :
939 0 : int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
940 : struct drm_file *file)
941 : {
942 0 : struct drm_i915_file_private *file_priv = file->driver_priv;
943 0 : struct drm_i915_gem_context_param *args = data;
944 : struct intel_context *ctx;
945 : int ret;
946 :
947 0 : ret = i915_mutex_lock_interruptible(dev);
948 0 : if (ret)
949 0 : return ret;
950 :
951 0 : ctx = i915_gem_context_get(file_priv, args->ctx_id);
952 0 : if (IS_ERR(ctx)) {
953 0 : mutex_unlock(&dev->struct_mutex);
954 0 : return PTR_ERR(ctx);
955 : }
956 :
957 0 : switch (args->param) {
958 : case I915_CONTEXT_PARAM_BAN_PERIOD:
959 0 : if (args->size)
960 0 : ret = -EINVAL;
961 0 : else if (args->value < ctx->hang_stats.ban_period_seconds &&
962 0 : !capable(CAP_SYS_ADMIN))
963 0 : ret = -EPERM;
964 : else
965 0 : ctx->hang_stats.ban_period_seconds = args->value;
966 : break;
967 : case I915_CONTEXT_PARAM_NO_ZEROMAP:
968 0 : if (args->size) {
969 : ret = -EINVAL;
970 0 : } else {
971 0 : ctx->flags &= ~CONTEXT_NO_ZEROMAP;
972 0 : ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
973 : }
974 : break;
975 : default:
976 : ret = -EINVAL;
977 0 : break;
978 : }
979 0 : mutex_unlock(&dev->struct_mutex);
980 :
981 0 : return ret;
982 0 : }
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