Line data Source code
1 : /*
2 : * Copyright (c) 2008 Intel Corporation
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice (including the next
12 : * paragraph) shall be included in all copies or substantial portions of the
13 : * Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 : * IN THE SOFTWARE.
22 : *
23 : * Authors:
24 : * Eric Anholt <eric@anholt.net>
25 : * Keith Packard <keithp@keithp.com>
26 : * Mika Kuoppala <mika.kuoppala@intel.com>
27 : *
28 : */
29 :
30 : #include "i915_drv.h"
31 :
32 0 : static const char *ring_str(int ring)
33 : {
34 0 : switch (ring) {
35 0 : case RCS: return "render";
36 0 : case VCS: return "bsd";
37 0 : case BCS: return "blt";
38 0 : case VECS: return "vebox";
39 0 : case VCS2: return "bsd2";
40 0 : default: return "";
41 : }
42 0 : }
43 :
44 0 : static const char *pin_flag(int pinned)
45 : {
46 0 : if (pinned > 0)
47 0 : return " P";
48 0 : else if (pinned < 0)
49 0 : return " p";
50 : else
51 0 : return "";
52 0 : }
53 :
54 0 : static const char *tiling_flag(int tiling)
55 : {
56 0 : switch (tiling) {
57 : default:
58 0 : case I915_TILING_NONE: return "";
59 0 : case I915_TILING_X: return " X";
60 0 : case I915_TILING_Y: return " Y";
61 : }
62 0 : }
63 :
64 0 : static const char *dirty_flag(int dirty)
65 : {
66 0 : return dirty ? " dirty" : "";
67 : }
68 :
69 0 : static const char *purgeable_flag(int purgeable)
70 : {
71 0 : return purgeable ? " purgeable" : "";
72 : }
73 :
74 0 : static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
75 : {
76 :
77 0 : if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
78 0 : e->err = -ENOSPC;
79 0 : return false;
80 : }
81 :
82 0 : if (e->bytes == e->size - 1 || e->err)
83 0 : return false;
84 :
85 0 : return true;
86 0 : }
87 :
88 0 : static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
89 : unsigned len)
90 : {
91 0 : if (e->pos + len <= e->start) {
92 0 : e->pos += len;
93 0 : return false;
94 : }
95 :
96 : /* First vsnprintf needs to fit in its entirety for memmove */
97 0 : if (len >= e->size) {
98 0 : e->err = -EIO;
99 0 : return false;
100 : }
101 :
102 0 : return true;
103 0 : }
104 :
105 0 : static void __i915_error_advance(struct drm_i915_error_state_buf *e,
106 : unsigned len)
107 : {
108 : /* If this is first printf in this window, adjust it so that
109 : * start position matches start of the buffer
110 : */
111 :
112 0 : if (e->pos < e->start) {
113 0 : const size_t off = e->start - e->pos;
114 :
115 : /* Should not happen but be paranoid */
116 0 : if (off > len || e->bytes) {
117 0 : e->err = -EIO;
118 0 : return;
119 : }
120 :
121 0 : memmove(e->buf, e->buf + off, len - off);
122 0 : e->bytes = len - off;
123 0 : e->pos = e->start;
124 0 : return;
125 : }
126 :
127 0 : e->bytes += len;
128 0 : e->pos += len;
129 0 : }
130 :
131 0 : static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
132 : const char *f, va_list args)
133 : {
134 : unsigned len;
135 :
136 0 : if (!__i915_error_ok(e))
137 0 : return;
138 :
139 : /* Seek the first printf which is hits start position */
140 0 : if (e->pos < e->start) {
141 0 : va_list tmp;
142 :
143 0 : va_copy(tmp, args);
144 0 : len = vsnprintf(NULL, 0, f, tmp);
145 0 : va_end(tmp);
146 :
147 0 : if (!__i915_error_seek(e, len))
148 0 : return;
149 0 : }
150 :
151 0 : len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
152 0 : if (len >= e->size - e->bytes)
153 0 : len = e->size - e->bytes - 1;
154 :
155 0 : __i915_error_advance(e, len);
156 0 : }
157 :
158 0 : static void i915_error_puts(struct drm_i915_error_state_buf *e,
159 : const char *str)
160 : {
161 : unsigned len;
162 :
163 0 : if (!__i915_error_ok(e))
164 0 : return;
165 :
166 0 : len = strlen(str);
167 :
168 : /* Seek the first printf which is hits start position */
169 0 : if (e->pos < e->start) {
170 0 : if (!__i915_error_seek(e, len))
171 0 : return;
172 : }
173 :
174 0 : if (len >= e->size - e->bytes)
175 0 : len = e->size - e->bytes - 1;
176 0 : memcpy(e->buf + e->bytes, str, len);
177 :
178 0 : __i915_error_advance(e, len);
179 0 : }
180 :
181 : #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
182 : #define err_puts(e, s) i915_error_puts(e, s)
183 :
184 0 : static void print_error_buffers(struct drm_i915_error_state_buf *m,
185 : const char *name,
186 : struct drm_i915_error_buffer *err,
187 : int count)
188 : {
189 : int i;
190 :
191 0 : err_printf(m, " %s [%d]:\n", name, count);
192 :
193 0 : while (count--) {
194 0 : err_printf(m, " %08x_%08x %8u %02x %02x [ ",
195 : upper_32_bits(err->gtt_offset),
196 : lower_32_bits(err->gtt_offset),
197 : err->size,
198 : err->read_domains,
199 : err->write_domain);
200 0 : for (i = 0; i < I915_NUM_RINGS; i++)
201 0 : err_printf(m, "%02x ", err->rseqno[i]);
202 :
203 0 : err_printf(m, "] %02x", err->wseqno);
204 0 : err_puts(m, pin_flag(err->pinned));
205 0 : err_puts(m, tiling_flag(err->tiling));
206 0 : err_puts(m, dirty_flag(err->dirty));
207 0 : err_puts(m, purgeable_flag(err->purgeable));
208 0 : err_puts(m, err->userptr ? " userptr" : "");
209 0 : err_puts(m, err->ring != -1 ? " " : "");
210 0 : err_puts(m, ring_str(err->ring));
211 0 : err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
212 :
213 0 : if (err->name)
214 0 : err_printf(m, " (name: %d)", err->name);
215 0 : if (err->fence_reg != I915_FENCE_REG_NONE)
216 0 : err_printf(m, " (fence: %d)", err->fence_reg);
217 :
218 0 : err_puts(m, "\n");
219 0 : err++;
220 : }
221 0 : }
222 :
223 0 : static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
224 : {
225 0 : switch (a) {
226 : case HANGCHECK_IDLE:
227 0 : return "idle";
228 : case HANGCHECK_WAIT:
229 0 : return "wait";
230 : case HANGCHECK_ACTIVE:
231 0 : return "active";
232 : case HANGCHECK_ACTIVE_LOOP:
233 0 : return "active (loop)";
234 : case HANGCHECK_KICK:
235 0 : return "kick";
236 : case HANGCHECK_HUNG:
237 0 : return "hung";
238 : }
239 :
240 0 : return "unknown";
241 0 : }
242 :
243 0 : static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
244 : struct drm_device *dev,
245 : struct drm_i915_error_state *error,
246 : int ring_idx)
247 : {
248 0 : struct drm_i915_error_ring *ring = &error->ring[ring_idx];
249 :
250 0 : if (!ring->valid)
251 0 : return;
252 :
253 0 : err_printf(m, "%s command stream:\n", ring_str(ring_idx));
254 0 : err_printf(m, " START: 0x%08x\n", ring->start);
255 0 : err_printf(m, " HEAD: 0x%08x\n", ring->head);
256 0 : err_printf(m, " TAIL: 0x%08x\n", ring->tail);
257 0 : err_printf(m, " CTL: 0x%08x\n", ring->ctl);
258 0 : err_printf(m, " HWS: 0x%08x\n", ring->hws);
259 0 : err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
260 0 : err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
261 0 : err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
262 0 : err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
263 0 : if (INTEL_INFO(dev)->gen >= 4) {
264 0 : err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
265 0 : err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
266 0 : err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
267 0 : }
268 0 : err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
269 0 : err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
270 : lower_32_bits(ring->faddr));
271 0 : if (INTEL_INFO(dev)->gen >= 6) {
272 0 : err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
273 0 : err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
274 0 : err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
275 : ring->semaphore_mboxes[0],
276 : ring->semaphore_seqno[0]);
277 0 : err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
278 : ring->semaphore_mboxes[1],
279 : ring->semaphore_seqno[1]);
280 0 : if (HAS_VEBOX(dev)) {
281 0 : err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
282 : ring->semaphore_mboxes[2],
283 : ring->semaphore_seqno[2]);
284 0 : }
285 : }
286 0 : if (USES_PPGTT(dev)) {
287 0 : err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
288 :
289 0 : if (INTEL_INFO(dev)->gen >= 8) {
290 : int i;
291 0 : for (i = 0; i < 4; i++)
292 0 : err_printf(m, " PDP%d: 0x%016llx\n",
293 : i, ring->vm_info.pdp[i]);
294 0 : } else {
295 0 : err_printf(m, " PP_DIR_BASE: 0x%08x\n",
296 : ring->vm_info.pp_dir_base);
297 : }
298 : }
299 0 : err_printf(m, " seqno: 0x%08x\n", ring->seqno);
300 0 : err_printf(m, " waiting: %s\n", yesno(ring->waiting));
301 0 : err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
302 0 : err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
303 0 : err_printf(m, " hangcheck: %s [%d]\n",
304 : hangcheck_action_to_str(ring->hangcheck_action),
305 : ring->hangcheck_score);
306 0 : }
307 :
308 0 : void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
309 : {
310 0 : va_list args;
311 :
312 0 : va_start(args, f);
313 0 : i915_error_vprintf(e, f, args);
314 0 : va_end(args);
315 0 : }
316 :
317 0 : static void print_error_obj(struct drm_i915_error_state_buf *m,
318 : struct drm_i915_error_object *obj)
319 : {
320 : int page, offset, elt;
321 :
322 0 : for (page = offset = 0; page < obj->page_count; page++) {
323 0 : for (elt = 0; elt < PAGE_SIZE/4; elt++) {
324 0 : err_printf(m, "%08x : %08x\n", offset,
325 : obj->pages[page][elt]);
326 0 : offset += 4;
327 : }
328 : }
329 0 : }
330 :
331 0 : static void xprint_error_obj(struct drm_i915_error_object *obj)
332 : {
333 : int page, offset, elt;
334 :
335 0 : for (page = offset = 0; page < obj->page_count; page++) {
336 0 : for (elt = 0; elt < PAGE_SIZE/64; elt++) {
337 0 : printf("%08x : %08x\n", offset,
338 0 : obj->pages[page][elt]);
339 0 : offset += 4;
340 : }
341 : break;
342 : }
343 0 : }
344 :
345 0 : int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
346 : const struct i915_error_state_file_priv *error_priv)
347 : {
348 0 : struct drm_device *dev = error_priv->dev;
349 0 : struct drm_i915_private *dev_priv = dev->dev_private;
350 0 : struct drm_i915_error_state *error = error_priv->error;
351 : struct drm_i915_error_object *obj;
352 : int i, j, offset, elt;
353 : int max_hangcheck_score;
354 :
355 0 : if (!error) {
356 0 : err_printf(m, "no error state collected\n");
357 0 : goto out;
358 : }
359 :
360 0 : err_printf(m, "%s\n", error->error_msg);
361 0 : err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
362 : error->time.tv_usec);
363 0 : err_printf(m, "Kernel: " UTS_RELEASE "\n");
364 : max_hangcheck_score = 0;
365 0 : for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
366 0 : if (error->ring[i].hangcheck_score > max_hangcheck_score)
367 0 : max_hangcheck_score = error->ring[i].hangcheck_score;
368 : }
369 0 : for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
370 0 : if (error->ring[i].hangcheck_score == max_hangcheck_score &&
371 0 : error->ring[i].pid != -1) {
372 0 : err_printf(m, "Active process (on ring %s): %s [%d]\n",
373 : ring_str(i),
374 : error->ring[i].comm,
375 : error->ring[i].pid);
376 0 : }
377 : }
378 0 : err_printf(m, "Reset count: %u\n", error->reset_count);
379 0 : err_printf(m, "Suspend count: %u\n", error->suspend_count);
380 0 : err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
381 0 : err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
382 0 : err_printf(m, "EIR: 0x%08x\n", error->eir);
383 0 : err_printf(m, "IER: 0x%08x\n", error->ier);
384 0 : if (INTEL_INFO(dev)->gen >= 8) {
385 0 : for (i = 0; i < 4; i++)
386 0 : err_printf(m, "GTIER gt %d: 0x%08x\n", i,
387 : error->gtier[i]);
388 0 : } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
389 0 : err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
390 0 : err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
391 0 : err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
392 0 : err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
393 0 : err_printf(m, "CCID: 0x%08x\n", error->ccid);
394 0 : err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
395 :
396 0 : for (i = 0; i < dev_priv->num_fence_regs; i++)
397 0 : err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
398 :
399 0 : for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
400 0 : err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
401 : error->extra_instdone[i]);
402 :
403 0 : if (INTEL_INFO(dev)->gen >= 6) {
404 0 : err_printf(m, "ERROR: 0x%08x\n", error->error);
405 :
406 0 : if (INTEL_INFO(dev)->gen >= 8)
407 0 : err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
408 : error->fault_data1, error->fault_data0);
409 :
410 0 : err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
411 0 : }
412 :
413 0 : if (INTEL_INFO(dev)->gen == 7)
414 0 : err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
415 :
416 0 : for (i = 0; i < ARRAY_SIZE(error->ring); i++)
417 0 : i915_ring_error_state(m, dev, error, i);
418 :
419 0 : for (i = 0; i < error->vm_count; i++) {
420 0 : err_printf(m, "vm[%d]\n", i);
421 :
422 0 : print_error_buffers(m, "Active",
423 0 : error->active_bo[i],
424 0 : error->active_bo_count[i]);
425 :
426 0 : print_error_buffers(m, "Pinned",
427 0 : error->pinned_bo[i],
428 0 : error->pinned_bo_count[i]);
429 : }
430 :
431 0 : for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
432 0 : obj = error->ring[i].batchbuffer;
433 0 : if (obj) {
434 0 : err_puts(m, dev_priv->ring[i].name);
435 0 : if (error->ring[i].pid != -1)
436 0 : err_printf(m, " (submitted by %s [%d])",
437 : error->ring[i].comm,
438 : error->ring[i].pid);
439 0 : err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
440 : upper_32_bits(obj->gtt_offset),
441 : lower_32_bits(obj->gtt_offset));
442 0 : print_error_obj(m, obj);
443 0 : }
444 :
445 0 : obj = error->ring[i].wa_batchbuffer;
446 0 : if (obj) {
447 0 : err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
448 : dev_priv->ring[i].name,
449 : lower_32_bits(obj->gtt_offset));
450 0 : print_error_obj(m, obj);
451 0 : }
452 :
453 0 : if (error->ring[i].num_requests) {
454 0 : err_printf(m, "%s --- %d requests\n",
455 : dev_priv->ring[i].name,
456 : error->ring[i].num_requests);
457 0 : for (j = 0; j < error->ring[i].num_requests; j++) {
458 0 : err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
459 : error->ring[i].requests[j].seqno,
460 : error->ring[i].requests[j].jiffies,
461 : error->ring[i].requests[j].tail);
462 : }
463 : }
464 :
465 0 : if ((obj = error->ring[i].ringbuffer)) {
466 0 : err_printf(m, "%s --- ringbuffer = 0x%08x\n",
467 : dev_priv->ring[i].name,
468 : lower_32_bits(obj->gtt_offset));
469 0 : print_error_obj(m, obj);
470 0 : }
471 :
472 0 : if ((obj = error->ring[i].hws_page)) {
473 0 : u64 hws_offset = obj->gtt_offset;
474 0 : u32 *hws_page = &obj->pages[0][0];
475 :
476 0 : if (i915.enable_execlists) {
477 0 : hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
478 0 : hws_page = &obj->pages[LRC_PPHWSP_PN][0];
479 0 : }
480 0 : err_printf(m, "%s --- HW Status = 0x%08llx\n",
481 : dev_priv->ring[i].name, hws_offset);
482 : offset = 0;
483 0 : for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
484 0 : err_printf(m, "[%04x] %08x %08x %08x %08x\n",
485 : offset,
486 : hws_page[elt],
487 : hws_page[elt+1],
488 : hws_page[elt+2],
489 : hws_page[elt+3]);
490 0 : offset += 16;
491 : }
492 0 : }
493 :
494 0 : if ((obj = error->ring[i].ctx)) {
495 0 : err_printf(m, "%s --- HW Context = 0x%08x\n",
496 : dev_priv->ring[i].name,
497 : lower_32_bits(obj->gtt_offset));
498 0 : print_error_obj(m, obj);
499 0 : }
500 : }
501 :
502 0 : if ((obj = error->semaphore_obj)) {
503 0 : err_printf(m, "Semaphore page = 0x%08x\n",
504 : lower_32_bits(obj->gtt_offset));
505 0 : for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
506 0 : err_printf(m, "[%04x] %08x %08x %08x %08x\n",
507 : elt * 4,
508 : obj->pages[0][elt],
509 : obj->pages[0][elt+1],
510 : obj->pages[0][elt+2],
511 : obj->pages[0][elt+3]);
512 : }
513 : }
514 :
515 0 : if (error->overlay)
516 0 : intel_overlay_print_error_state(m, error->overlay);
517 :
518 0 : if (error->display)
519 0 : intel_display_print_error_state(m, dev, error->display);
520 :
521 : out:
522 0 : if (m->bytes == 0 && m->err)
523 0 : return m->err;
524 :
525 0 : return 0;
526 0 : }
527 :
528 0 : int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
529 : struct drm_i915_private *i915,
530 : size_t count, loff_t pos)
531 : {
532 0 : memset(ebuf, 0, sizeof(*ebuf));
533 0 : ebuf->i915 = i915;
534 :
535 : /* We need to have enough room to store any i915_error_state printf
536 : * so that we can move it to start position.
537 : */
538 0 : ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
539 0 : ebuf->buf = kmalloc(ebuf->size,
540 : GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
541 :
542 0 : if (ebuf->buf == NULL) {
543 0 : ebuf->size = PAGE_SIZE;
544 0 : ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
545 0 : }
546 :
547 0 : if (ebuf->buf == NULL) {
548 0 : ebuf->size = 128;
549 0 : ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
550 0 : }
551 :
552 0 : if (ebuf->buf == NULL)
553 0 : return -ENOMEM;
554 :
555 0 : ebuf->start = pos;
556 :
557 0 : return 0;
558 0 : }
559 :
560 0 : static void i915_error_object_free(struct drm_i915_error_object *obj)
561 : {
562 : int page;
563 :
564 0 : if (obj == NULL)
565 0 : return;
566 :
567 0 : for (page = 0; page < obj->page_count; page++)
568 0 : kfree(obj->pages[page]);
569 :
570 0 : kfree(obj);
571 0 : }
572 :
573 0 : static void i915_error_state_free(struct kref *error_ref)
574 : {
575 0 : struct drm_i915_error_state *error = container_of(error_ref,
576 : typeof(*error), ref);
577 : int i;
578 :
579 0 : for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
580 0 : i915_error_object_free(error->ring[i].batchbuffer);
581 0 : i915_error_object_free(error->ring[i].wa_batchbuffer);
582 0 : i915_error_object_free(error->ring[i].ringbuffer);
583 0 : i915_error_object_free(error->ring[i].hws_page);
584 0 : i915_error_object_free(error->ring[i].ctx);
585 0 : kfree(error->ring[i].requests);
586 : }
587 :
588 0 : i915_error_object_free(error->semaphore_obj);
589 :
590 0 : for (i = 0; i < error->vm_count; i++)
591 0 : kfree(error->active_bo[i]);
592 :
593 0 : kfree(error->active_bo);
594 0 : kfree(error->active_bo_count);
595 0 : kfree(error->pinned_bo);
596 0 : kfree(error->pinned_bo_count);
597 0 : kfree(error->overlay);
598 0 : kfree(error->display);
599 0 : kfree(error);
600 0 : }
601 :
602 : static struct drm_i915_error_object *
603 0 : i915_error_object_create(struct drm_i915_private *dev_priv,
604 : struct drm_i915_gem_object *src,
605 : struct i915_address_space *vm)
606 : {
607 : struct drm_i915_error_object *dst;
608 : struct i915_vma *vma = NULL;
609 : int num_pages;
610 : bool use_ggtt;
611 : int i = 0;
612 : u64 reloc_offset;
613 :
614 0 : if (src == NULL || src->pages == NULL)
615 0 : return NULL;
616 :
617 0 : num_pages = src->base.size >> PAGE_SHIFT;
618 :
619 0 : dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
620 0 : if (dst == NULL)
621 0 : return NULL;
622 :
623 0 : if (i915_gem_obj_bound(src, vm))
624 0 : dst->gtt_offset = i915_gem_obj_offset(src, vm);
625 : else
626 0 : dst->gtt_offset = -1;
627 :
628 0 : reloc_offset = dst->gtt_offset;
629 0 : if (i915_is_ggtt(vm))
630 0 : vma = i915_gem_obj_to_ggtt(src);
631 0 : use_ggtt = (src->cache_level == I915_CACHE_NONE &&
632 0 : vma && (vma->bound & GLOBAL_BIND) &&
633 0 : reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
634 :
635 : /* Cannot access stolen address directly, try to use the aperture */
636 0 : if (src->stolen) {
637 : use_ggtt = true;
638 :
639 0 : if (!(vma && vma->bound & GLOBAL_BIND))
640 : goto unwind;
641 :
642 0 : reloc_offset = i915_gem_obj_ggtt_offset(src);
643 0 : if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
644 : goto unwind;
645 : }
646 :
647 : /* Cannot access snooped pages through the aperture */
648 0 : if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
649 : goto unwind;
650 :
651 0 : dst->page_count = num_pages;
652 0 : while (num_pages--) {
653 : unsigned long flags;
654 : void *d;
655 :
656 0 : d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
657 0 : if (d == NULL)
658 0 : goto unwind;
659 :
660 0 : local_irq_save(flags);
661 0 : if (use_ggtt) {
662 0 : bus_space_handle_t bsh;
663 : void __iomem *s;
664 :
665 : /* Simply ignore tiling or any overlapping fence.
666 : * It's part of the error state, and this hopefully
667 : * captures what the GPU read.
668 : */
669 :
670 : #ifdef __linux__
671 : s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
672 : reloc_offset);
673 : #else
674 0 : agp_map_atomic(dev_priv->agph, reloc_offset, &bsh);
675 0 : s = bus_space_vaddr(dev_priv->bst, bsh);
676 : #endif
677 0 : memcpy_fromio(d, s, PAGE_SIZE);
678 : #ifdef __linux__
679 : io_mapping_unmap_atomic(s);
680 : #else
681 0 : agp_unmap_atomic(dev_priv->agph, bsh);
682 : #endif
683 0 : } else {
684 0 : struct vm_page *page;
685 : void *s;
686 :
687 0 : page = i915_gem_object_get_page(src, i);
688 :
689 0 : drm_clflush_pages(&page, 1);
690 :
691 0 : s = kmap_atomic(page);
692 0 : memcpy(d, s, PAGE_SIZE);
693 0 : kunmap_atomic(s);
694 :
695 0 : drm_clflush_pages(&page, 1);
696 0 : }
697 0 : local_irq_restore(flags);
698 :
699 0 : dst->pages[i++] = d;
700 0 : reloc_offset += PAGE_SIZE;
701 0 : }
702 :
703 0 : return dst;
704 :
705 : unwind:
706 0 : while (i--)
707 0 : kfree(dst->pages[i]);
708 0 : kfree(dst);
709 0 : return NULL;
710 0 : }
711 : #define i915_error_ggtt_object_create(dev_priv, src) \
712 : i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
713 :
714 0 : static void capture_bo(struct drm_i915_error_buffer *err,
715 : struct i915_vma *vma)
716 : {
717 0 : struct drm_i915_gem_object *obj = vma->obj;
718 : int i;
719 :
720 0 : err->size = obj->base.size;
721 0 : err->name = obj->base.name;
722 0 : for (i = 0; i < I915_NUM_RINGS; i++)
723 0 : err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
724 0 : err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
725 0 : err->gtt_offset = vma->node.start;
726 0 : err->read_domains = obj->base.read_domains;
727 0 : err->write_domain = obj->base.write_domain;
728 0 : err->fence_reg = obj->fence_reg;
729 0 : err->pinned = 0;
730 0 : if (i915_gem_obj_is_pinned(obj))
731 0 : err->pinned = 1;
732 0 : err->tiling = obj->tiling_mode;
733 0 : err->dirty = obj->dirty;
734 0 : err->purgeable = obj->madv != I915_MADV_WILLNEED;
735 0 : err->userptr = obj->userptr.mm != NULL;
736 0 : err->ring = obj->last_write_req ?
737 0 : i915_gem_request_get_ring(obj->last_write_req)->id : -1;
738 0 : err->cache_level = obj->cache_level;
739 0 : }
740 :
741 0 : static u32 capture_active_bo(struct drm_i915_error_buffer *err,
742 : int count, struct list_head *head)
743 : {
744 : struct i915_vma *vma;
745 : int i = 0;
746 :
747 0 : list_for_each_entry(vma, head, mm_list) {
748 0 : capture_bo(err++, vma);
749 0 : if (++i == count)
750 : break;
751 : }
752 :
753 0 : return i;
754 : }
755 :
756 0 : static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
757 : int count, struct list_head *head,
758 : struct i915_address_space *vm)
759 : {
760 : struct drm_i915_gem_object *obj;
761 : struct drm_i915_error_buffer * const first = err;
762 0 : struct drm_i915_error_buffer * const last = err + count;
763 :
764 0 : list_for_each_entry(obj, head, global_list) {
765 : struct i915_vma *vma;
766 :
767 0 : if (err == last)
768 0 : break;
769 :
770 0 : list_for_each_entry(vma, &obj->vma_list, vma_link)
771 0 : if (vma->vm == vm && vma->pin_count > 0)
772 0 : capture_bo(err++, vma);
773 0 : }
774 :
775 0 : return err - first;
776 : }
777 :
778 : /* Generate a semi-unique error code. The code is not meant to have meaning, The
779 : * code's only purpose is to try to prevent false duplicated bug reports by
780 : * grossly estimating a GPU error state.
781 : *
782 : * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
783 : * the hang if we could strip the GTT offset information from it.
784 : *
785 : * It's only a small step better than a random number in its current form.
786 : */
787 0 : static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
788 : struct drm_i915_error_state *error,
789 : int *ring_id)
790 : {
791 : uint32_t error_code = 0;
792 : int i;
793 :
794 : /* IPEHR would be an ideal way to detect errors, as it's the gross
795 : * measure of "the command that hung." However, has some very common
796 : * synchronization commands which almost always appear in the case
797 : * strictly a client bug. Use instdone to differentiate those some.
798 : */
799 0 : for (i = 0; i < I915_NUM_RINGS; i++) {
800 0 : if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
801 0 : if (ring_id)
802 0 : *ring_id = i;
803 :
804 0 : return error->ring[i].ipehr ^ error->ring[i].instdone;
805 : }
806 : }
807 :
808 0 : return error_code;
809 0 : }
810 :
811 0 : static void i915_gem_record_fences(struct drm_device *dev,
812 : struct drm_i915_error_state *error)
813 : {
814 0 : struct drm_i915_private *dev_priv = dev->dev_private;
815 : int i;
816 :
817 0 : if (IS_GEN3(dev) || IS_GEN2(dev)) {
818 0 : for (i = 0; i < dev_priv->num_fence_regs; i++)
819 0 : error->fence[i] = I915_READ(FENCE_REG(i));
820 0 : } else if (IS_GEN5(dev) || IS_GEN4(dev)) {
821 0 : for (i = 0; i < dev_priv->num_fence_regs; i++)
822 0 : error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
823 0 : } else if (INTEL_INFO(dev)->gen >= 6) {
824 0 : for (i = 0; i < dev_priv->num_fence_regs; i++)
825 0 : error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
826 : }
827 0 : }
828 :
829 :
830 0 : static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
831 : struct drm_i915_error_state *error,
832 : struct intel_engine_cs *ring,
833 : struct drm_i915_error_ring *ering)
834 : {
835 : struct intel_engine_cs *to;
836 : int i;
837 :
838 0 : if (!i915_semaphore_is_enabled(dev_priv->dev))
839 0 : return;
840 :
841 0 : if (!error->semaphore_obj)
842 0 : error->semaphore_obj =
843 0 : i915_error_ggtt_object_create(dev_priv,
844 : dev_priv->semaphore_obj);
845 :
846 0 : for_each_ring(to, dev_priv, i) {
847 : int idx;
848 : u16 signal_offset;
849 : u32 *tmp;
850 :
851 0 : if (ring == to)
852 0 : continue;
853 :
854 0 : signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
855 0 : / 4;
856 0 : tmp = error->semaphore_obj->pages[0];
857 0 : idx = intel_ring_sync_index(ring, to);
858 :
859 0 : ering->semaphore_mboxes[idx] = tmp[signal_offset];
860 0 : ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
861 0 : }
862 0 : }
863 :
864 0 : static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
865 : struct intel_engine_cs *ring,
866 : struct drm_i915_error_ring *ering)
867 : {
868 0 : ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
869 0 : ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
870 0 : ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
871 0 : ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
872 :
873 0 : if (HAS_VEBOX(dev_priv->dev)) {
874 0 : ering->semaphore_mboxes[2] =
875 0 : I915_READ(RING_SYNC_2(ring->mmio_base));
876 0 : ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
877 0 : }
878 0 : }
879 :
880 0 : static void i915_record_ring_state(struct drm_device *dev,
881 : struct drm_i915_error_state *error,
882 : struct intel_engine_cs *ring,
883 : struct drm_i915_error_ring *ering)
884 : {
885 0 : struct drm_i915_private *dev_priv = dev->dev_private;
886 :
887 0 : if (INTEL_INFO(dev)->gen >= 6) {
888 0 : ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
889 0 : ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
890 0 : if (INTEL_INFO(dev)->gen >= 8)
891 0 : gen8_record_semaphore_state(dev_priv, error, ring, ering);
892 : else
893 0 : gen6_record_semaphore_state(dev_priv, ring, ering);
894 : }
895 :
896 0 : if (INTEL_INFO(dev)->gen >= 4) {
897 0 : ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
898 0 : ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
899 0 : ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
900 0 : ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
901 0 : ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
902 0 : ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
903 0 : if (INTEL_INFO(dev)->gen >= 8) {
904 0 : ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
905 0 : ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
906 0 : }
907 0 : ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
908 0 : } else {
909 0 : ering->faddr = I915_READ(DMA_FADD_I8XX);
910 0 : ering->ipeir = I915_READ(IPEIR);
911 0 : ering->ipehr = I915_READ(IPEHR);
912 0 : ering->instdone = I915_READ(GEN2_INSTDONE);
913 : }
914 :
915 0 : ering->waiting = waitqueue_active(&ring->irq_queue);
916 0 : ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
917 0 : ering->seqno = ring->get_seqno(ring, false);
918 0 : ering->acthd = intel_ring_get_active_head(ring);
919 0 : ering->start = I915_READ_START(ring);
920 0 : ering->head = I915_READ_HEAD(ring);
921 0 : ering->tail = I915_READ_TAIL(ring);
922 0 : ering->ctl = I915_READ_CTL(ring);
923 :
924 0 : if (I915_NEED_GFX_HWS(dev)) {
925 : int mmio;
926 :
927 0 : if (IS_GEN7(dev)) {
928 0 : switch (ring->id) {
929 : default:
930 : case RCS:
931 : mmio = RENDER_HWS_PGA_GEN7;
932 0 : break;
933 : case BCS:
934 : mmio = BLT_HWS_PGA_GEN7;
935 0 : break;
936 : case VCS:
937 : mmio = BSD_HWS_PGA_GEN7;
938 0 : break;
939 : case VECS:
940 : mmio = VEBOX_HWS_PGA_GEN7;
941 0 : break;
942 : }
943 0 : } else if (IS_GEN6(ring->dev)) {
944 0 : mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
945 0 : } else {
946 : /* XXX: gen8 returns to sanity */
947 0 : mmio = RING_HWS_PGA(ring->mmio_base);
948 : }
949 :
950 0 : ering->hws = I915_READ(mmio);
951 0 : }
952 :
953 0 : ering->hangcheck_score = ring->hangcheck.score;
954 0 : ering->hangcheck_action = ring->hangcheck.action;
955 :
956 0 : if (USES_PPGTT(dev)) {
957 : int i;
958 :
959 0 : ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
960 :
961 0 : if (IS_GEN6(dev))
962 0 : ering->vm_info.pp_dir_base =
963 0 : I915_READ(RING_PP_DIR_BASE_READ(ring));
964 0 : else if (IS_GEN7(dev))
965 0 : ering->vm_info.pp_dir_base =
966 0 : I915_READ(RING_PP_DIR_BASE(ring));
967 0 : else if (INTEL_INFO(dev)->gen >= 8)
968 0 : for (i = 0; i < 4; i++) {
969 0 : ering->vm_info.pdp[i] =
970 0 : I915_READ(GEN8_RING_PDP_UDW(ring, i));
971 0 : ering->vm_info.pdp[i] <<= 32;
972 0 : ering->vm_info.pdp[i] |=
973 0 : I915_READ(GEN8_RING_PDP_LDW(ring, i));
974 : }
975 0 : }
976 0 : }
977 :
978 :
979 0 : static void i915_gem_record_active_context(struct intel_engine_cs *ring,
980 : struct drm_i915_error_state *error,
981 : struct drm_i915_error_ring *ering)
982 : {
983 0 : struct drm_i915_private *dev_priv = ring->dev->dev_private;
984 : struct drm_i915_gem_object *obj;
985 :
986 : /* Currently render ring is the only HW context user */
987 0 : if (ring->id != RCS || !error->ccid)
988 0 : return;
989 :
990 0 : list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
991 0 : if (!i915_gem_obj_ggtt_bound(obj))
992 : continue;
993 :
994 0 : if (trunc_page(error->ccid) == i915_gem_obj_ggtt_offset(obj)) {
995 0 : ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
996 0 : break;
997 : }
998 : }
999 0 : }
1000 :
1001 0 : static void i915_gem_record_rings(struct drm_device *dev,
1002 : struct drm_i915_error_state *error)
1003 : {
1004 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1005 : struct drm_i915_gem_request *request;
1006 : int i, count;
1007 :
1008 0 : for (i = 0; i < I915_NUM_RINGS; i++) {
1009 0 : struct intel_engine_cs *ring = &dev_priv->ring[i];
1010 : struct intel_ringbuffer *rbuf;
1011 :
1012 0 : error->ring[i].pid = -1;
1013 :
1014 0 : if (ring->dev == NULL)
1015 0 : continue;
1016 :
1017 0 : error->ring[i].valid = true;
1018 :
1019 0 : i915_record_ring_state(dev, error, ring, &error->ring[i]);
1020 :
1021 0 : request = i915_gem_find_active_request(ring);
1022 0 : if (request) {
1023 : struct i915_address_space *vm;
1024 :
1025 0 : vm = request->ctx && request->ctx->ppgtt ?
1026 0 : &request->ctx->ppgtt->base :
1027 0 : &dev_priv->gtt.base;
1028 :
1029 : /* We need to copy these to an anonymous buffer
1030 : * as the simplest method to avoid being overwritten
1031 : * by userspace.
1032 : */
1033 0 : error->ring[i].batchbuffer =
1034 0 : i915_error_object_create(dev_priv,
1035 0 : request->batch_obj,
1036 : vm);
1037 :
1038 0 : if (HAS_BROKEN_CS_TLB(dev_priv->dev))
1039 0 : error->ring[i].wa_batchbuffer =
1040 0 : i915_error_ggtt_object_create(dev_priv,
1041 : ring->scratch.obj);
1042 :
1043 : #ifdef __linux__
1044 : if (request->pid) {
1045 : struct task_struct *task;
1046 :
1047 : rcu_read_lock();
1048 : task = pid_task(request->pid, PIDTYPE_PID);
1049 : if (task) {
1050 : strcpy(error->ring[i].comm, task->comm);
1051 : error->ring[i].pid = task->pid;
1052 : }
1053 : rcu_read_unlock();
1054 : }
1055 : #endif
1056 0 : }
1057 :
1058 0 : if (i915.enable_execlists) {
1059 : /* TODO: This is only a small fix to keep basic error
1060 : * capture working, but we need to add more information
1061 : * for it to be useful (e.g. dump the context being
1062 : * executed).
1063 : */
1064 0 : if (request)
1065 0 : rbuf = request->ctx->engine[ring->id].ringbuf;
1066 : else
1067 0 : rbuf = ring->default_context->engine[ring->id].ringbuf;
1068 : } else
1069 0 : rbuf = ring->buffer;
1070 :
1071 0 : error->ring[i].cpu_ring_head = rbuf->head;
1072 0 : error->ring[i].cpu_ring_tail = rbuf->tail;
1073 :
1074 0 : error->ring[i].ringbuffer =
1075 0 : i915_error_ggtt_object_create(dev_priv, rbuf->obj);
1076 :
1077 0 : error->ring[i].hws_page =
1078 0 : i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
1079 :
1080 0 : i915_gem_record_active_context(ring, error, &error->ring[i]);
1081 :
1082 : count = 0;
1083 0 : list_for_each_entry(request, &ring->request_list, list)
1084 0 : count++;
1085 :
1086 0 : error->ring[i].num_requests = count;
1087 0 : error->ring[i].requests =
1088 0 : kcalloc(count, sizeof(*error->ring[i].requests),
1089 : GFP_ATOMIC);
1090 0 : if (error->ring[i].requests == NULL) {
1091 0 : error->ring[i].num_requests = 0;
1092 0 : continue;
1093 : }
1094 :
1095 : count = 0;
1096 0 : list_for_each_entry(request, &ring->request_list, list) {
1097 : struct drm_i915_error_request *erq;
1098 :
1099 0 : erq = &error->ring[i].requests[count++];
1100 0 : erq->seqno = request->seqno;
1101 0 : erq->jiffies = request->emitted_jiffies;
1102 0 : erq->tail = request->postfix;
1103 : }
1104 0 : }
1105 0 : }
1106 :
1107 : /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
1108 : * VM.
1109 : */
1110 0 : static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
1111 : struct drm_i915_error_state *error,
1112 : struct i915_address_space *vm,
1113 : const int ndx)
1114 : {
1115 : struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
1116 : struct drm_i915_gem_object *obj;
1117 : struct i915_vma *vma;
1118 : int i;
1119 :
1120 : i = 0;
1121 0 : list_for_each_entry(vma, &vm->active_list, mm_list)
1122 0 : i++;
1123 0 : error->active_bo_count[ndx] = i;
1124 :
1125 0 : list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1126 0 : list_for_each_entry(vma, &obj->vma_list, vma_link)
1127 0 : if (vma->vm == vm && vma->pin_count > 0)
1128 0 : i++;
1129 : }
1130 0 : error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1131 :
1132 0 : if (i) {
1133 0 : active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1134 0 : if (active_bo)
1135 0 : pinned_bo = active_bo + error->active_bo_count[ndx];
1136 : }
1137 :
1138 0 : if (active_bo)
1139 0 : error->active_bo_count[ndx] =
1140 0 : capture_active_bo(active_bo,
1141 0 : error->active_bo_count[ndx],
1142 : &vm->active_list);
1143 :
1144 0 : if (pinned_bo)
1145 0 : error->pinned_bo_count[ndx] =
1146 0 : capture_pinned_bo(pinned_bo,
1147 0 : error->pinned_bo_count[ndx],
1148 : &dev_priv->mm.bound_list, vm);
1149 0 : error->active_bo[ndx] = active_bo;
1150 0 : error->pinned_bo[ndx] = pinned_bo;
1151 0 : }
1152 :
1153 0 : static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1154 : struct drm_i915_error_state *error)
1155 : {
1156 : struct i915_address_space *vm;
1157 : int cnt = 0, i = 0;
1158 :
1159 0 : list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1160 0 : cnt++;
1161 :
1162 0 : error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1163 0 : error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1164 0 : error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1165 : GFP_ATOMIC);
1166 0 : error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1167 : GFP_ATOMIC);
1168 :
1169 0 : if (error->active_bo == NULL ||
1170 0 : error->pinned_bo == NULL ||
1171 0 : error->active_bo_count == NULL ||
1172 0 : error->pinned_bo_count == NULL) {
1173 0 : kfree(error->active_bo);
1174 0 : kfree(error->active_bo_count);
1175 0 : kfree(error->pinned_bo);
1176 0 : kfree(error->pinned_bo_count);
1177 :
1178 0 : error->active_bo = NULL;
1179 0 : error->active_bo_count = NULL;
1180 0 : error->pinned_bo = NULL;
1181 0 : error->pinned_bo_count = NULL;
1182 0 : } else {
1183 0 : list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1184 0 : i915_gem_capture_vm(dev_priv, error, vm, i++);
1185 :
1186 0 : error->vm_count = cnt;
1187 : }
1188 0 : }
1189 :
1190 : /* Capture all registers which don't fit into another category. */
1191 0 : static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1192 : struct drm_i915_error_state *error)
1193 : {
1194 0 : struct drm_device *dev = dev_priv->dev;
1195 : int i;
1196 :
1197 : /* General organization
1198 : * 1. Registers specific to a single generation
1199 : * 2. Registers which belong to multiple generations
1200 : * 3. Feature specific registers.
1201 : * 4. Everything else
1202 : * Please try to follow the order.
1203 : */
1204 :
1205 : /* 1: Registers specific to a single generation */
1206 0 : if (IS_VALLEYVIEW(dev)) {
1207 0 : error->gtier[0] = I915_READ(GTIER);
1208 0 : error->ier = I915_READ(VLV_IER);
1209 0 : error->forcewake = I915_READ(FORCEWAKE_VLV);
1210 0 : }
1211 :
1212 0 : if (IS_GEN7(dev))
1213 0 : error->err_int = I915_READ(GEN7_ERR_INT);
1214 :
1215 0 : if (INTEL_INFO(dev)->gen >= 8) {
1216 0 : error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1217 0 : error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1218 0 : }
1219 :
1220 0 : if (IS_GEN6(dev)) {
1221 0 : error->forcewake = I915_READ(FORCEWAKE);
1222 0 : error->gab_ctl = I915_READ(GAB_CTL);
1223 0 : error->gfx_mode = I915_READ(GFX_MODE);
1224 0 : }
1225 :
1226 : /* 2: Registers which belong to multiple generations */
1227 0 : if (INTEL_INFO(dev)->gen >= 7)
1228 0 : error->forcewake = I915_READ(FORCEWAKE_MT);
1229 :
1230 0 : if (INTEL_INFO(dev)->gen >= 6) {
1231 0 : error->derrmr = I915_READ(DERRMR);
1232 0 : error->error = I915_READ(ERROR_GEN6);
1233 0 : error->done_reg = I915_READ(DONE_REG);
1234 0 : }
1235 :
1236 : /* 3: Feature specific registers */
1237 0 : if (IS_GEN6(dev) || IS_GEN7(dev)) {
1238 0 : error->gam_ecochk = I915_READ(GAM_ECOCHK);
1239 0 : error->gac_eco = I915_READ(GAC_ECO_BITS);
1240 0 : }
1241 :
1242 : /* 4: Everything else */
1243 0 : if (HAS_HW_CONTEXTS(dev))
1244 0 : error->ccid = I915_READ(CCID);
1245 :
1246 0 : if (INTEL_INFO(dev)->gen >= 8) {
1247 0 : error->ier = I915_READ(GEN8_DE_MISC_IER);
1248 0 : for (i = 0; i < 4; i++)
1249 0 : error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1250 0 : } else if (HAS_PCH_SPLIT(dev)) {
1251 0 : error->ier = I915_READ(DEIER);
1252 0 : error->gtier[0] = I915_READ(GTIER);
1253 0 : } else if (IS_GEN2(dev)) {
1254 0 : error->ier = I915_READ16(IER);
1255 0 : } else if (!IS_VALLEYVIEW(dev)) {
1256 0 : error->ier = I915_READ(IER);
1257 0 : }
1258 0 : error->eir = I915_READ(EIR);
1259 0 : error->pgtbl_er = I915_READ(PGTBL_ER);
1260 :
1261 0 : i915_get_extra_instdone(dev, error->extra_instdone);
1262 0 : }
1263 :
1264 0 : static void i915_error_capture_msg(struct drm_device *dev,
1265 : struct drm_i915_error_state *error,
1266 : bool wedged,
1267 : const char *error_msg)
1268 : {
1269 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1270 : u32 ecode;
1271 0 : int ring_id = -1, len;
1272 :
1273 0 : ecode = i915_error_generate_code(dev_priv, error, &ring_id);
1274 :
1275 0 : len = scnprintf(error->error_msg, sizeof(error->error_msg),
1276 : "GPU HANG: ecode %d:%d:0x%08x",
1277 : INTEL_INFO(dev)->gen, ring_id, ecode);
1278 :
1279 0 : if (ring_id != -1 && error->ring[ring_id].pid != -1)
1280 0 : len += scnprintf(error->error_msg + len,
1281 : sizeof(error->error_msg) - len,
1282 : ", in %s [%d]",
1283 : error->ring[ring_id].comm,
1284 : error->ring[ring_id].pid);
1285 :
1286 0 : scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1287 : ", reason: %s, action: %s",
1288 : error_msg,
1289 : wedged ? "reset" : "continue");
1290 0 : }
1291 :
1292 0 : static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
1293 : struct drm_i915_error_state *error)
1294 : {
1295 0 : error->iommu = -1;
1296 : #ifdef CONFIG_INTEL_IOMMU
1297 : error->iommu = intel_iommu_gfx_mapped;
1298 : #endif
1299 0 : error->reset_count = i915_reset_count(&dev_priv->gpu_error);
1300 0 : error->suspend_count = dev_priv->suspend_count;
1301 0 : }
1302 :
1303 : /**
1304 : * i915_capture_error_state - capture an error record for later analysis
1305 : * @dev: drm device
1306 : *
1307 : * Should be called when an error is detected (either a hang or an error
1308 : * interrupt) to capture error state from the time of the error. Fills
1309 : * out a structure which becomes available in debugfs for user level tools
1310 : * to pick up.
1311 : */
1312 0 : void i915_capture_error_state(struct drm_device *dev, bool wedged,
1313 : const char *error_msg)
1314 : {
1315 : static bool warned;
1316 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1317 : struct drm_i915_error_state *error;
1318 : unsigned long flags;
1319 :
1320 : /* Account for pipe specific data like PIPE*STAT */
1321 0 : error = kzalloc(sizeof(*error), GFP_ATOMIC);
1322 0 : if (!error) {
1323 : DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1324 0 : return;
1325 : }
1326 :
1327 0 : kref_init(&error->ref);
1328 :
1329 0 : i915_capture_gen_state(dev_priv, error);
1330 0 : i915_capture_reg_state(dev_priv, error);
1331 0 : i915_gem_capture_buffers(dev_priv, error);
1332 0 : i915_gem_record_fences(dev, error);
1333 0 : i915_gem_record_rings(dev, error);
1334 :
1335 0 : do_gettimeofday(&error->time);
1336 :
1337 0 : error->overlay = intel_overlay_capture_error_state(dev);
1338 0 : error->display = intel_display_capture_error_state(dev);
1339 :
1340 0 : i915_error_capture_msg(dev, error, wedged, error_msg);
1341 : DRM_INFO("%s\n", error->error_msg);
1342 :
1343 : int i, offset, elt;
1344 : struct drm_i915_error_object *obj;
1345 : static bool printed;
1346 :
1347 0 : if (printed)
1348 : goto end;
1349 0 : printed = 1;
1350 :
1351 0 : printf("EIR: 0x%08x\n", error->eir);
1352 0 : printf("IER: 0x%08x\n", error->ier);
1353 0 : if (INTEL_INFO(dev)->gen >= 8) {
1354 0 : for (i = 0; i < 4; i++)
1355 0 : printf("GTIER gt %d: 0x%08x\n", i,
1356 0 : error->gtier[i]);
1357 0 : } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
1358 0 : printf("GTIER: 0x%08x\n", error->gtier[0]);
1359 0 : printf("PGTBL_ER: 0x%08x\n", error->pgtbl_er);
1360 0 : printf("FORCEWAKE: 0x%08x\n", error->forcewake);
1361 0 : printf("DERRMR: 0x%08x\n", error->derrmr);
1362 0 : printf("CCID: 0x%08x\n", error->ccid);
1363 0 : printf("Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
1364 :
1365 0 : for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
1366 0 : printf(" INSTDONE_%d: 0x%08x\n", i,
1367 0 : error->extra_instdone[i]);
1368 :
1369 0 : if (INTEL_INFO(dev)->gen >= 6) {
1370 0 : printf("ERROR: 0x%08x\n", error->error);
1371 :
1372 0 : if (INTEL_INFO(dev)->gen >= 8)
1373 0 : printf("FAULT_TLB_DATA: 0x%08x 0x%08x\n",
1374 0 : error->fault_data1, error->fault_data0);
1375 :
1376 0 : printf("DONE_REG: 0x%08x\n", error->done_reg);
1377 0 : }
1378 :
1379 0 : for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1380 0 : struct drm_i915_error_ring *ring = &error->ring[i];
1381 :
1382 0 : if (!ring->valid)
1383 0 : continue;
1384 :
1385 0 : printf("%s command stream:\n", ring_str(i));
1386 0 : printf(" START: 0x%08x\n", ring->start);
1387 0 : printf(" HEAD: 0x%08x\n", ring->head);
1388 0 : printf(" TAIL: 0x%08x\n", ring->tail);
1389 0 : printf(" CTL: 0x%08x\n", ring->ctl);
1390 0 : printf(" HWS: 0x%08x\n", ring->hws);
1391 0 : printf(" ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
1392 0 : printf(" IPEIR: 0x%08x\n", ring->ipeir);
1393 0 : printf(" IPEHR: 0x%08x\n", ring->ipehr);
1394 0 : printf(" INSTDONE: 0x%08x\n", ring->instdone);
1395 0 : if (INTEL_INFO(dev)->gen >= 4) {
1396 0 : printf(" BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
1397 0 : printf(" BB_STATE: 0x%08x\n", ring->bbstate);
1398 0 : printf(" INSTPS: 0x%08x\n", ring->instps);
1399 0 : }
1400 0 : printf(" INSTPM: 0x%08x\n", ring->instpm);
1401 0 : printf(" FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
1402 0 : lower_32_bits(ring->faddr));
1403 0 : if (INTEL_INFO(dev)->gen >= 6) {
1404 0 : printf(" RC PSMI: 0x%08x\n", ring->rc_psmi);
1405 0 : printf(" FAULT_REG: 0x%08x\n", ring->fault_reg);
1406 0 : printf(" SYNC_0: 0x%08x [last synced 0x%08x]\n",
1407 0 : ring->semaphore_mboxes[0],
1408 0 : ring->semaphore_seqno[0]);
1409 0 : printf(" SYNC_1: 0x%08x [last synced 0x%08x]\n",
1410 0 : ring->semaphore_mboxes[1],
1411 0 : ring->semaphore_seqno[1]);
1412 0 : if (HAS_VEBOX(dev)) {
1413 0 : printf(" SYNC_2: 0x%08x [last synced 0x%08x]\n",
1414 0 : ring->semaphore_mboxes[2],
1415 0 : ring->semaphore_seqno[2]);
1416 0 : }
1417 : }
1418 0 : if (USES_PPGTT(dev)) {
1419 0 : printf(" GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
1420 :
1421 0 : if (INTEL_INFO(dev)->gen >= 8) {
1422 : int i;
1423 0 : for (i = 0; i < 4; i++)
1424 0 : printf(" PDP%d: 0x%016llx\n",
1425 0 : i, ring->vm_info.pdp[i]);
1426 0 : } else {
1427 0 : printf(" PP_DIR_BASE: 0x%08x\n",
1428 0 : ring->vm_info.pp_dir_base);
1429 : }
1430 : }
1431 0 : printf(" seqno: 0x%08x\n", ring->seqno);
1432 0 : printf(" waiting: %s\n", yesno(ring->waiting));
1433 0 : printf(" ring->head: 0x%08x\n", ring->cpu_ring_head);
1434 0 : printf(" ring->tail: 0x%08x\n", ring->cpu_ring_tail);
1435 0 : printf(" hangcheck: %s [%d]\n",
1436 0 : hangcheck_action_to_str(ring->hangcheck_action),
1437 0 : ring->hangcheck_score);
1438 :
1439 0 : if ((obj = error->ring[i].ringbuffer)) {
1440 0 : printf("%s --- ringbuffer = 0x%08x\n",
1441 0 : dev_priv->ring[i].name,
1442 0 : lower_32_bits(obj->gtt_offset));
1443 0 : xprint_error_obj(obj);
1444 0 : }
1445 :
1446 0 : if ((obj = error->ring[i].hws_page)) {
1447 0 : u64 hws_offset = obj->gtt_offset;
1448 0 : u32 *hws_page = &obj->pages[0][0];
1449 :
1450 0 : if (i915.enable_execlists) {
1451 0 : hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
1452 0 : hws_page = &obj->pages[LRC_PPHWSP_PN][0];
1453 0 : }
1454 0 : printf("%s --- HW Status = 0x%08llx\n",
1455 0 : dev_priv->ring[i].name, hws_offset);
1456 : offset = 0;
1457 0 : for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
1458 0 : printf("[%04x] %08x %08x %08x %08x\n",
1459 : offset,
1460 0 : hws_page[elt],
1461 0 : hws_page[elt+1],
1462 0 : hws_page[elt+2],
1463 0 : hws_page[elt+3]);
1464 0 : offset += 16;
1465 : }
1466 0 : }
1467 :
1468 0 : if ((obj = error->ring[i].ctx)) {
1469 0 : printf("%s --- HW Context = 0x%08x\n",
1470 0 : dev_priv->ring[i].name,
1471 0 : lower_32_bits(obj->gtt_offset));
1472 : // print_error_obj(m, obj);
1473 0 : }
1474 0 : }
1475 :
1476 : end:
1477 0 : spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1478 0 : if (dev_priv->gpu_error.first_error == NULL) {
1479 0 : dev_priv->gpu_error.first_error = error;
1480 : error = NULL;
1481 0 : }
1482 0 : spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1483 :
1484 0 : if (error) {
1485 0 : i915_error_state_free(&error->ref);
1486 0 : return;
1487 : }
1488 :
1489 0 : if (!warned) {
1490 : #ifdef __linux__
1491 : DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1492 : DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1493 : DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1494 : DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1495 : DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
1496 : #endif
1497 0 : warned = true;
1498 0 : }
1499 0 : }
1500 :
1501 0 : void i915_error_state_get(struct drm_device *dev,
1502 : struct i915_error_state_file_priv *error_priv)
1503 : {
1504 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1505 :
1506 0 : spin_lock_irq(&dev_priv->gpu_error.lock);
1507 0 : error_priv->error = dev_priv->gpu_error.first_error;
1508 0 : if (error_priv->error)
1509 0 : kref_get(&error_priv->error->ref);
1510 0 : spin_unlock_irq(&dev_priv->gpu_error.lock);
1511 :
1512 0 : }
1513 :
1514 0 : void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1515 : {
1516 0 : if (error_priv->error)
1517 0 : kref_put(&error_priv->error->ref, i915_error_state_free);
1518 0 : }
1519 :
1520 0 : void i915_destroy_error_state(struct drm_device *dev)
1521 : {
1522 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1523 : struct drm_i915_error_state *error;
1524 :
1525 0 : spin_lock_irq(&dev_priv->gpu_error.lock);
1526 0 : error = dev_priv->gpu_error.first_error;
1527 0 : dev_priv->gpu_error.first_error = NULL;
1528 0 : spin_unlock_irq(&dev_priv->gpu_error.lock);
1529 :
1530 0 : if (error)
1531 0 : kref_put(&error->ref, i915_error_state_free);
1532 0 : }
1533 :
1534 0 : const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1535 : {
1536 0 : switch (type) {
1537 0 : case I915_CACHE_NONE: return " uncached";
1538 0 : case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1539 0 : case I915_CACHE_L3_LLC: return " L3+LLC";
1540 0 : case I915_CACHE_WT: return " WT";
1541 0 : default: return "";
1542 : }
1543 0 : }
1544 :
1545 : /* NB: please notice the memset */
1546 0 : void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1547 : {
1548 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1549 0 : memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1550 :
1551 0 : if (IS_GEN2(dev) || IS_GEN3(dev))
1552 0 : instdone[0] = I915_READ(GEN2_INSTDONE);
1553 0 : else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1554 0 : instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1555 0 : instdone[1] = I915_READ(GEN4_INSTDONE1);
1556 0 : } else if (INTEL_INFO(dev)->gen >= 7) {
1557 0 : instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
1558 0 : instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1559 0 : instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1560 0 : instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1561 0 : }
1562 0 : }
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