Line data Source code
1 : /*
2 : * Copyright © 2014 Intel Corporation
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice (including the next
12 : * paragraph) shall be included in all copies or substantial portions of the
13 : * Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 : * IN THE SOFTWARE.
22 : *
23 : */
24 : #ifdef __linux__
25 : #include <linux/firmware.h>
26 : #include <linux/circ_buf.h>
27 : #endif
28 : #include "i915_drv.h"
29 : #include "intel_guc.h"
30 :
31 : #ifdef notyet
32 :
33 : /**
34 : * DOC: GuC Client
35 : *
36 : * i915_guc_client:
37 : * We use the term client to avoid confusion with contexts. A i915_guc_client is
38 : * equivalent to GuC object guc_context_desc. This context descriptor is
39 : * allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
40 : * and workqueue for it. Also the process descriptor (guc_process_desc), which
41 : * is mapped to client space. So the client can write Work Item then ring the
42 : * doorbell.
43 : *
44 : * To simplify the implementation, we allocate one gem object that contains all
45 : * pages for doorbell, process descriptor and workqueue.
46 : *
47 : * The Scratch registers:
48 : * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
49 : * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
50 : * triggers an interrupt on the GuC via another register write (0xC4C8).
51 : * Firmware writes a success/fail code back to the action register after
52 : * processes the request. The kernel driver polls waiting for this update and
53 : * then proceeds.
54 : * See host2guc_action()
55 : *
56 : * Doorbells:
57 : * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
58 : * mapped into process space.
59 : *
60 : * Work Items:
61 : * There are several types of work items that the host may place into a
62 : * workqueue, each with its own requirements and limitations. Currently only
63 : * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
64 : * represents in-order queue. The kernel driver packs ring tail pointer and an
65 : * ELSP context descriptor dword into Work Item.
66 : * See guc_add_workqueue_item()
67 : *
68 : */
69 :
70 : /*
71 : * Read GuC command/status register (SOFT_SCRATCH_0)
72 : * Return true if it contains a response rather than a command
73 : */
74 : static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
75 : u32 *status)
76 : {
77 : u32 val = I915_READ(SOFT_SCRATCH(0));
78 : *status = val;
79 : return GUC2HOST_IS_RESPONSE(val);
80 : }
81 :
82 : static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
83 : {
84 : struct drm_i915_private *dev_priv = guc_to_i915(guc);
85 : u32 status;
86 : int i;
87 : int ret;
88 :
89 : if (WARN_ON(len < 1 || len > 15))
90 : return -EINVAL;
91 :
92 : intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
93 : spin_lock(&dev_priv->guc.host2guc_lock);
94 :
95 : dev_priv->guc.action_count += 1;
96 : dev_priv->guc.action_cmd = data[0];
97 :
98 : for (i = 0; i < len; i++)
99 : I915_WRITE(SOFT_SCRATCH(i), data[i]);
100 :
101 : POSTING_READ(SOFT_SCRATCH(i - 1));
102 :
103 : I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
104 :
105 : /* No HOST2GUC command should take longer than 10ms */
106 : ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10);
107 : if (status != GUC2HOST_STATUS_SUCCESS) {
108 : /*
109 : * Either the GuC explicitly returned an error (which
110 : * we convert to -EIO here) or no response at all was
111 : * received within the timeout limit (-ETIMEDOUT)
112 : */
113 : if (ret != -ETIMEDOUT)
114 : ret = -EIO;
115 :
116 : DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
117 : "status=0x%08X response=0x%08X\n",
118 : data[0], ret, status,
119 : I915_READ(SOFT_SCRATCH(15)));
120 :
121 : dev_priv->guc.action_fail += 1;
122 : dev_priv->guc.action_err = ret;
123 : }
124 : dev_priv->guc.action_status = status;
125 :
126 : spin_unlock(&dev_priv->guc.host2guc_lock);
127 : intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
128 :
129 : return ret;
130 : }
131 :
132 : /*
133 : * Tell the GuC to allocate or deallocate a specific doorbell
134 : */
135 :
136 : static int host2guc_allocate_doorbell(struct intel_guc *guc,
137 : struct i915_guc_client *client)
138 : {
139 : u32 data[2];
140 :
141 : data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
142 : data[1] = client->ctx_index;
143 :
144 : return host2guc_action(guc, data, 2);
145 : }
146 :
147 : static int host2guc_release_doorbell(struct intel_guc *guc,
148 : struct i915_guc_client *client)
149 : {
150 : u32 data[2];
151 :
152 : data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
153 : data[1] = client->ctx_index;
154 :
155 : return host2guc_action(guc, data, 2);
156 : }
157 :
158 : static int host2guc_sample_forcewake(struct intel_guc *guc,
159 : struct i915_guc_client *client)
160 : {
161 : struct drm_i915_private *dev_priv = guc_to_i915(guc);
162 : struct drm_device *dev = dev_priv->dev;
163 : u32 data[2];
164 :
165 : data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
166 : /* WaRsDisableCoarsePowerGating:skl,bxt */
167 : if (!intel_enable_rc6(dev_priv->dev) ||
168 : IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
169 : (IS_SKL_GT3(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)) ||
170 : (IS_SKL_GT4(dev) && IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
171 : data[1] = 0;
172 : else
173 : /* bit 0 and 1 are for Render and Media domain separately */
174 : data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
175 :
176 : return host2guc_action(guc, data, ARRAY_SIZE(data));
177 : }
178 :
179 : /*
180 : * Initialise, update, or clear doorbell data shared with the GuC
181 : *
182 : * These functions modify shared data and so need access to the mapped
183 : * client object which contains the page being used for the doorbell
184 : */
185 :
186 : static void guc_init_doorbell(struct intel_guc *guc,
187 : struct i915_guc_client *client)
188 : {
189 : struct guc_doorbell_info *doorbell;
190 : void *base;
191 :
192 : base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
193 : doorbell = base + client->doorbell_offset;
194 :
195 : doorbell->db_status = 1;
196 : doorbell->cookie = 0;
197 :
198 : kunmap_atomic(base);
199 : }
200 :
201 : static int guc_ring_doorbell(struct i915_guc_client *gc)
202 : {
203 : struct guc_process_desc *desc;
204 : union guc_doorbell_qw db_cmp, db_exc, db_ret;
205 : union guc_doorbell_qw *db;
206 : void *base;
207 : int attempt = 2, ret = -EAGAIN;
208 :
209 : base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
210 : desc = base + gc->proc_desc_offset;
211 :
212 : /* Update the tail so it is visible to GuC */
213 : desc->tail = gc->wq_tail;
214 :
215 : /* current cookie */
216 : db_cmp.db_status = GUC_DOORBELL_ENABLED;
217 : db_cmp.cookie = gc->cookie;
218 :
219 : /* cookie to be updated */
220 : db_exc.db_status = GUC_DOORBELL_ENABLED;
221 : db_exc.cookie = gc->cookie + 1;
222 : if (db_exc.cookie == 0)
223 : db_exc.cookie = 1;
224 :
225 : /* pointer of current doorbell cacheline */
226 : db = base + gc->doorbell_offset;
227 :
228 : while (attempt--) {
229 : /* lets ring the doorbell */
230 : db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
231 : db_cmp.value_qw, db_exc.value_qw);
232 :
233 : /* if the exchange was successfully executed */
234 : if (db_ret.value_qw == db_cmp.value_qw) {
235 : /* db was successfully rung */
236 : gc->cookie = db_exc.cookie;
237 : ret = 0;
238 : break;
239 : }
240 :
241 : /* XXX: doorbell was lost and need to acquire it again */
242 : if (db_ret.db_status == GUC_DOORBELL_DISABLED)
243 : break;
244 :
245 : DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
246 : db_cmp.cookie, db_ret.cookie);
247 :
248 : /* update the cookie to newly read cookie from GuC */
249 : db_cmp.cookie = db_ret.cookie;
250 : db_exc.cookie = db_ret.cookie + 1;
251 : if (db_exc.cookie == 0)
252 : db_exc.cookie = 1;
253 : }
254 :
255 : kunmap_atomic(base);
256 : return ret;
257 : }
258 :
259 : static void guc_disable_doorbell(struct intel_guc *guc,
260 : struct i915_guc_client *client)
261 : {
262 : struct drm_i915_private *dev_priv = guc_to_i915(guc);
263 : struct guc_doorbell_info *doorbell;
264 : void *base;
265 : int drbreg = GEN8_DRBREGL(client->doorbell_id);
266 : int value;
267 :
268 : base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
269 : doorbell = base + client->doorbell_offset;
270 :
271 : doorbell->db_status = 0;
272 :
273 : kunmap_atomic(base);
274 :
275 : I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID);
276 :
277 : value = I915_READ(drbreg);
278 : WARN_ON((value & GEN8_DRB_VALID) != 0);
279 :
280 : I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0);
281 : I915_WRITE(drbreg, 0);
282 :
283 : /* XXX: wait for any interrupts */
284 : /* XXX: wait for workqueue to drain */
285 : }
286 :
287 : /*
288 : * Select, assign and relase doorbell cachelines
289 : *
290 : * These functions track which doorbell cachelines are in use.
291 : * The data they manipulate is protected by the host2guc lock.
292 : */
293 :
294 : static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
295 : {
296 : const uint32_t cacheline_size = cache_line_size();
297 : uint32_t offset;
298 :
299 : spin_lock(&guc->host2guc_lock);
300 :
301 : /* Doorbell uses a single cache line within a page */
302 : offset = offset_in_page(guc->db_cacheline);
303 :
304 : /* Moving to next cache line to reduce contention */
305 : guc->db_cacheline += cacheline_size;
306 :
307 : spin_unlock(&guc->host2guc_lock);
308 :
309 : DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
310 : offset, guc->db_cacheline, cacheline_size);
311 :
312 : return offset;
313 : }
314 :
315 : static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority)
316 : {
317 : /*
318 : * The bitmap is split into two halves; the first half is used for
319 : * normal priority contexts, the second half for high-priority ones.
320 : * Note that logically higher priorities are numerically less than
321 : * normal ones, so the test below means "is it high-priority?"
322 : */
323 : const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
324 : const uint16_t half = GUC_MAX_DOORBELLS / 2;
325 : const uint16_t start = hi_pri ? half : 0;
326 : const uint16_t end = start + half;
327 : uint16_t id;
328 :
329 : spin_lock(&guc->host2guc_lock);
330 : id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
331 : if (id == end)
332 : id = GUC_INVALID_DOORBELL_ID;
333 : else
334 : bitmap_set(guc->doorbell_bitmap, id, 1);
335 : spin_unlock(&guc->host2guc_lock);
336 :
337 : DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
338 : hi_pri ? "high" : "normal", id);
339 :
340 : return id;
341 : }
342 :
343 : static void release_doorbell(struct intel_guc *guc, uint16_t id)
344 : {
345 : spin_lock(&guc->host2guc_lock);
346 : bitmap_clear(guc->doorbell_bitmap, id, 1);
347 : spin_unlock(&guc->host2guc_lock);
348 : }
349 :
350 : /*
351 : * Initialise the process descriptor shared with the GuC firmware.
352 : */
353 : static void guc_init_proc_desc(struct intel_guc *guc,
354 : struct i915_guc_client *client)
355 : {
356 : struct guc_process_desc *desc;
357 : void *base;
358 :
359 : base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
360 : desc = base + client->proc_desc_offset;
361 :
362 : memset(desc, 0, sizeof(*desc));
363 :
364 : /*
365 : * XXX: pDoorbell and WQVBaseAddress are pointers in process address
366 : * space for ring3 clients (set them as in mmap_ioctl) or kernel
367 : * space for kernel clients (map on demand instead? May make debug
368 : * easier to have it mapped).
369 : */
370 : desc->wq_base_addr = 0;
371 : desc->db_base_addr = 0;
372 :
373 : desc->context_id = client->ctx_index;
374 : desc->wq_size_bytes = client->wq_size;
375 : desc->wq_status = WQ_STATUS_ACTIVE;
376 : desc->priority = client->priority;
377 :
378 : kunmap_atomic(base);
379 : }
380 :
381 : /*
382 : * Initialise/clear the context descriptor shared with the GuC firmware.
383 : *
384 : * This descriptor tells the GuC where (in GGTT space) to find the important
385 : * data structures relating to this client (doorbell, process descriptor,
386 : * write queue, etc).
387 : */
388 :
389 : static void guc_init_ctx_desc(struct intel_guc *guc,
390 : struct i915_guc_client *client)
391 : {
392 : struct intel_context *ctx = client->owner;
393 : struct guc_context_desc desc;
394 : struct sg_table *sg;
395 : int i;
396 :
397 : memset(&desc, 0, sizeof(desc));
398 :
399 : desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
400 : desc.context_id = client->ctx_index;
401 : desc.priority = client->priority;
402 : desc.db_id = client->doorbell_id;
403 :
404 : for (i = 0; i < I915_NUM_RINGS; i++) {
405 : struct guc_execlist_context *lrc = &desc.lrc[i];
406 : struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf;
407 : struct intel_engine_cs *ring;
408 : struct drm_i915_gem_object *obj;
409 : uint64_t ctx_desc;
410 :
411 : /* TODO: We have a design issue to be solved here. Only when we
412 : * receive the first batch, we know which engine is used by the
413 : * user. But here GuC expects the lrc and ring to be pinned. It
414 : * is not an issue for default context, which is the only one
415 : * for now who owns a GuC client. But for future owner of GuC
416 : * client, need to make sure lrc is pinned prior to enter here.
417 : */
418 : obj = ctx->engine[i].state;
419 : if (!obj)
420 : break; /* XXX: continue? */
421 :
422 : ring = ringbuf->ring;
423 : ctx_desc = intel_lr_context_descriptor(ctx, ring);
424 : lrc->context_desc = (u32)ctx_desc;
425 :
426 : /* The state page is after PPHWSP */
427 : lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) +
428 : LRC_STATE_PN * PAGE_SIZE;
429 : lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
430 : (ring->id << GUC_ELC_ENGINE_OFFSET);
431 :
432 : obj = ringbuf->obj;
433 :
434 : lrc->ring_begin = i915_gem_obj_ggtt_offset(obj);
435 : lrc->ring_end = lrc->ring_begin + obj->base.size - 1;
436 : lrc->ring_next_free_location = lrc->ring_begin;
437 : lrc->ring_current_tail_pointer_value = 0;
438 :
439 : desc.engines_used |= (1 << ring->id);
440 : }
441 :
442 : WARN_ON(desc.engines_used == 0);
443 :
444 : /*
445 : * The CPU address is only needed at certain points, so kmap_atomic on
446 : * demand instead of storing it in the ctx descriptor.
447 : * XXX: May make debug easier to have it mapped
448 : */
449 : desc.db_trigger_cpu = 0;
450 : desc.db_trigger_uk = client->doorbell_offset +
451 : i915_gem_obj_ggtt_offset(client->client_obj);
452 : desc.db_trigger_phy = client->doorbell_offset +
453 : sg_dma_address(client->client_obj->pages->sgl);
454 :
455 : desc.process_desc = client->proc_desc_offset +
456 : i915_gem_obj_ggtt_offset(client->client_obj);
457 :
458 : desc.wq_addr = client->wq_offset +
459 : i915_gem_obj_ggtt_offset(client->client_obj);
460 :
461 : desc.wq_size = client->wq_size;
462 :
463 : /*
464 : * XXX: Take LRCs from an existing intel_context if this is not an
465 : * IsKMDCreatedContext client
466 : */
467 : desc.desc_private = (uintptr_t)client;
468 :
469 : /* Pool context is pinned already */
470 : sg = guc->ctx_pool_obj->pages;
471 : sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
472 : sizeof(desc) * client->ctx_index);
473 : }
474 :
475 : static void guc_fini_ctx_desc(struct intel_guc *guc,
476 : struct i915_guc_client *client)
477 : {
478 : struct guc_context_desc desc;
479 : struct sg_table *sg;
480 :
481 : memset(&desc, 0, sizeof(desc));
482 :
483 : sg = guc->ctx_pool_obj->pages;
484 : sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
485 : sizeof(desc) * client->ctx_index);
486 : }
487 :
488 : /* Get valid workqueue item and return it back to offset */
489 : static int guc_get_workqueue_space(struct i915_guc_client *gc, u32 *offset)
490 : {
491 : struct guc_process_desc *desc;
492 : void *base;
493 : u32 size = sizeof(struct guc_wq_item);
494 : int ret = 0, timeout_counter = 200;
495 :
496 : base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
497 : desc = base + gc->proc_desc_offset;
498 :
499 : while (timeout_counter-- > 0) {
500 : ret = wait_for_atomic(CIRC_SPACE(gc->wq_tail, desc->head,
501 : gc->wq_size) >= size, 1);
502 :
503 : if (!ret) {
504 : *offset = gc->wq_tail;
505 :
506 : /* advance the tail for next workqueue item */
507 : gc->wq_tail += size;
508 : gc->wq_tail &= gc->wq_size - 1;
509 :
510 : /* this will break the loop */
511 : timeout_counter = 0;
512 : }
513 : };
514 :
515 : kunmap_atomic(base);
516 :
517 : return ret;
518 : }
519 :
520 : static int guc_add_workqueue_item(struct i915_guc_client *gc,
521 : struct drm_i915_gem_request *rq)
522 : {
523 : enum intel_ring_id ring_id = rq->ring->id;
524 : struct guc_wq_item *wqi;
525 : void *base;
526 : u32 tail, wq_len, wq_off = 0;
527 : int ret;
528 :
529 : ret = guc_get_workqueue_space(gc, &wq_off);
530 : if (ret)
531 : return ret;
532 :
533 : /* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
534 : * should not have the case where structure wqi is across page, neither
535 : * wrapped to the beginning. This simplifies the implementation below.
536 : *
537 : * XXX: if not the case, we need save data to a temp wqi and copy it to
538 : * workqueue buffer dw by dw.
539 : */
540 : WARN_ON(sizeof(struct guc_wq_item) != 16);
541 : WARN_ON(wq_off & 3);
542 :
543 : /* wq starts from the page after doorbell / process_desc */
544 : base = kmap_atomic(i915_gem_object_get_page(gc->client_obj,
545 : (wq_off + GUC_DB_SIZE) >> PAGE_SHIFT));
546 : wq_off &= PAGE_SIZE - 1;
547 : wqi = (struct guc_wq_item *)((char *)base + wq_off);
548 :
549 : /* len does not include the header */
550 : wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1;
551 : wqi->header = WQ_TYPE_INORDER |
552 : (wq_len << WQ_LEN_SHIFT) |
553 : (ring_id << WQ_TARGET_SHIFT) |
554 : WQ_NO_WCFLUSH_WAIT;
555 :
556 : /* The GuC wants only the low-order word of the context descriptor */
557 : wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring);
558 :
559 : /* The GuC firmware wants the tail index in QWords, not bytes */
560 : tail = rq->ringbuf->tail >> 3;
561 : wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
562 : wqi->fence_id = 0; /*XXX: what fence to be here */
563 :
564 : kunmap_atomic(base);
565 :
566 : return 0;
567 : }
568 :
569 : #define CTX_RING_BUFFER_START 0x08
570 :
571 : /* Update the ringbuffer pointer in a saved context image */
572 : static void lr_context_update(struct drm_i915_gem_request *rq)
573 : {
574 : enum intel_ring_id ring_id = rq->ring->id;
575 : struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring_id].state;
576 : struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
577 : struct page *page;
578 : uint32_t *reg_state;
579 :
580 : BUG_ON(!ctx_obj);
581 : WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
582 : WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
583 :
584 : page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
585 : reg_state = kmap_atomic(page);
586 :
587 : reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
588 :
589 : kunmap_atomic(reg_state);
590 : }
591 :
592 : /**
593 : * i915_guc_submit() - Submit commands through GuC
594 : * @client: the guc client where commands will go through
595 : * @ctx: LRC where commands come from
596 : * @ring: HW engine that will excute the commands
597 : *
598 : * Return: 0 if succeed
599 : */
600 : int i915_guc_submit(struct i915_guc_client *client,
601 : struct drm_i915_gem_request *rq)
602 : {
603 : struct intel_guc *guc = client->guc;
604 : enum intel_ring_id ring_id = rq->ring->id;
605 : unsigned long flags;
606 : int q_ret, b_ret;
607 :
608 : /* Need this because of the deferred pin ctx and ring */
609 : /* Shall we move this right after ring is pinned? */
610 : lr_context_update(rq);
611 :
612 : spin_lock_irqsave(&client->wq_lock, flags);
613 :
614 : q_ret = guc_add_workqueue_item(client, rq);
615 : if (q_ret == 0)
616 : b_ret = guc_ring_doorbell(client);
617 :
618 : client->submissions[ring_id] += 1;
619 : if (q_ret) {
620 : client->q_fail += 1;
621 : client->retcode = q_ret;
622 : } else if (b_ret) {
623 : client->b_fail += 1;
624 : client->retcode = q_ret = b_ret;
625 : } else {
626 : client->retcode = 0;
627 : }
628 : spin_unlock_irqrestore(&client->wq_lock, flags);
629 :
630 : spin_lock(&guc->host2guc_lock);
631 : guc->submissions[ring_id] += 1;
632 : guc->last_seqno[ring_id] = rq->seqno;
633 : spin_unlock(&guc->host2guc_lock);
634 :
635 : return q_ret;
636 : }
637 :
638 : /*
639 : * Everything below here is concerned with setup & teardown, and is
640 : * therefore not part of the somewhat time-critical batch-submission
641 : * path of i915_guc_submit() above.
642 : */
643 :
644 : /**
645 : * gem_allocate_guc_obj() - Allocate gem object for GuC usage
646 : * @dev: drm device
647 : * @size: size of object
648 : *
649 : * This is a wrapper to create a gem obj. In order to use it inside GuC, the
650 : * object needs to be pinned lifetime. Also we must pin it to gtt space other
651 : * than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC.
652 : *
653 : * Return: A drm_i915_gem_object if successful, otherwise NULL.
654 : */
655 : static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
656 : u32 size)
657 : {
658 : struct drm_i915_private *dev_priv = dev->dev_private;
659 : struct drm_i915_gem_object *obj;
660 :
661 : obj = i915_gem_alloc_object(dev, size);
662 : if (!obj)
663 : return NULL;
664 :
665 : if (i915_gem_object_get_pages(obj)) {
666 : drm_gem_object_unreference(&obj->base);
667 : return NULL;
668 : }
669 :
670 : if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
671 : PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) {
672 : drm_gem_object_unreference(&obj->base);
673 : return NULL;
674 : }
675 :
676 : /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
677 : I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
678 :
679 : return obj;
680 : }
681 :
682 : /**
683 : * gem_release_guc_obj() - Release gem object allocated for GuC usage
684 : * @obj: gem obj to be released
685 : */
686 : static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
687 : {
688 : if (!obj)
689 : return;
690 :
691 : if (i915_gem_obj_is_pinned(obj))
692 : i915_gem_object_ggtt_unpin(obj);
693 :
694 : drm_gem_object_unreference(&obj->base);
695 : }
696 :
697 : static void guc_client_free(struct drm_device *dev,
698 : struct i915_guc_client *client)
699 : {
700 : struct drm_i915_private *dev_priv = dev->dev_private;
701 : struct intel_guc *guc = &dev_priv->guc;
702 :
703 : if (!client)
704 : return;
705 :
706 : if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) {
707 : /*
708 : * First disable the doorbell, then tell the GuC we've
709 : * finished with it, finally deallocate it in our bitmap
710 : */
711 : guc_disable_doorbell(guc, client);
712 : host2guc_release_doorbell(guc, client);
713 : release_doorbell(guc, client->doorbell_id);
714 : }
715 :
716 : /*
717 : * XXX: wait for any outstanding submissions before freeing memory.
718 : * Be sure to drop any locks
719 : */
720 :
721 : gem_release_guc_obj(client->client_obj);
722 :
723 : if (client->ctx_index != GUC_INVALID_CTX_ID) {
724 : guc_fini_ctx_desc(guc, client);
725 : ida_simple_remove(&guc->ctx_ids, client->ctx_index);
726 : }
727 :
728 : kfree(client);
729 : }
730 :
731 : /**
732 : * guc_client_alloc() - Allocate an i915_guc_client
733 : * @dev: drm device
734 : * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
735 : * The kernel client to replace ExecList submission is created with
736 : * NORMAL priority. Priority of a client for scheduler can be HIGH,
737 : * while a preemption context can use CRITICAL.
738 : * @ctx the context to own the client (we use the default render context)
739 : *
740 : * Return: An i915_guc_client object if success.
741 : */
742 : static struct i915_guc_client *guc_client_alloc(struct drm_device *dev,
743 : uint32_t priority,
744 : struct intel_context *ctx)
745 : {
746 : struct i915_guc_client *client;
747 : struct drm_i915_private *dev_priv = dev->dev_private;
748 : struct intel_guc *guc = &dev_priv->guc;
749 : struct drm_i915_gem_object *obj;
750 :
751 : client = kzalloc(sizeof(*client), GFP_KERNEL);
752 : if (!client)
753 : return NULL;
754 :
755 : client->doorbell_id = GUC_INVALID_DOORBELL_ID;
756 : client->priority = priority;
757 : client->owner = ctx;
758 : client->guc = guc;
759 :
760 : client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
761 : GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
762 : if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
763 : client->ctx_index = GUC_INVALID_CTX_ID;
764 : goto err;
765 : }
766 :
767 : /* The first page is doorbell/proc_desc. Two followed pages are wq. */
768 : obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE);
769 : if (!obj)
770 : goto err;
771 :
772 : client->client_obj = obj;
773 : client->wq_offset = GUC_DB_SIZE;
774 : client->wq_size = GUC_WQ_SIZE;
775 : spin_lock_init(&client->wq_lock);
776 :
777 : client->doorbell_offset = select_doorbell_cacheline(guc);
778 :
779 : /*
780 : * Since the doorbell only requires a single cacheline, we can save
781 : * space by putting the application process descriptor in the same
782 : * page. Use the half of the page that doesn't include the doorbell.
783 : */
784 : if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
785 : client->proc_desc_offset = 0;
786 : else
787 : client->proc_desc_offset = (GUC_DB_SIZE / 2);
788 :
789 : client->doorbell_id = assign_doorbell(guc, client->priority);
790 : if (client->doorbell_id == GUC_INVALID_DOORBELL_ID)
791 : /* XXX: evict a doorbell instead */
792 : goto err;
793 :
794 : guc_init_proc_desc(guc, client);
795 : guc_init_ctx_desc(guc, client);
796 : guc_init_doorbell(guc, client);
797 :
798 : /* XXX: Any cache flushes needed? General domain mgmt calls? */
799 :
800 : if (host2guc_allocate_doorbell(guc, client))
801 : goto err;
802 :
803 : DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n",
804 : priority, client, client->ctx_index, client->doorbell_id);
805 :
806 : return client;
807 :
808 : err:
809 : DRM_ERROR("FAILED to create priority %u GuC client!\n", priority);
810 :
811 : guc_client_free(dev, client);
812 : return NULL;
813 : }
814 :
815 : static void guc_create_log(struct intel_guc *guc)
816 : {
817 : struct drm_i915_private *dev_priv = guc_to_i915(guc);
818 : struct drm_i915_gem_object *obj;
819 : unsigned long offset;
820 : uint32_t size, flags;
821 :
822 : if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN)
823 : return;
824 :
825 : if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
826 : i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
827 :
828 : /* The first page is to save log buffer state. Allocate one
829 : * extra page for others in case for overlap */
830 : size = (1 + GUC_LOG_DPC_PAGES + 1 +
831 : GUC_LOG_ISR_PAGES + 1 +
832 : GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
833 :
834 : obj = guc->log_obj;
835 : if (!obj) {
836 : obj = gem_allocate_guc_obj(dev_priv->dev, size);
837 : if (!obj) {
838 : /* logging will be off */
839 : i915.guc_log_level = -1;
840 : return;
841 : }
842 :
843 : guc->log_obj = obj;
844 : }
845 :
846 : /* each allocated unit is a page */
847 : flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
848 : (GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
849 : (GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
850 : (GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
851 :
852 : offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */
853 : guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
854 : }
855 :
856 : /*
857 : * Set up the memory resources to be shared with the GuC. At this point,
858 : * we require just one object that can be mapped through the GGTT.
859 : */
860 : int i915_guc_submission_init(struct drm_device *dev)
861 : {
862 : struct drm_i915_private *dev_priv = dev->dev_private;
863 : const size_t ctxsize = sizeof(struct guc_context_desc);
864 : const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
865 : const size_t gemsize = round_up(poolsize, PAGE_SIZE);
866 : struct intel_guc *guc = &dev_priv->guc;
867 :
868 : if (!i915.enable_guc_submission)
869 : return 0; /* not enabled */
870 :
871 : if (guc->ctx_pool_obj)
872 : return 0; /* already allocated */
873 :
874 : guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize);
875 : if (!guc->ctx_pool_obj)
876 : return -ENOMEM;
877 :
878 : spin_lock_init(&dev_priv->guc.host2guc_lock);
879 :
880 : ida_init(&guc->ctx_ids);
881 :
882 : guc_create_log(guc);
883 :
884 : return 0;
885 : }
886 :
887 : int i915_guc_submission_enable(struct drm_device *dev)
888 : {
889 : struct drm_i915_private *dev_priv = dev->dev_private;
890 : struct intel_guc *guc = &dev_priv->guc;
891 : struct intel_context *ctx = dev_priv->ring[RCS].default_context;
892 : struct i915_guc_client *client;
893 :
894 : /* client for execbuf submission */
895 : client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx);
896 : if (!client) {
897 : DRM_ERROR("Failed to create execbuf guc_client\n");
898 : return -ENOMEM;
899 : }
900 :
901 : guc->execbuf_client = client;
902 :
903 : host2guc_sample_forcewake(guc, client);
904 :
905 : return 0;
906 : }
907 :
908 : void i915_guc_submission_disable(struct drm_device *dev)
909 : {
910 : struct drm_i915_private *dev_priv = dev->dev_private;
911 : struct intel_guc *guc = &dev_priv->guc;
912 :
913 : guc_client_free(dev, guc->execbuf_client);
914 : guc->execbuf_client = NULL;
915 : }
916 :
917 : void i915_guc_submission_fini(struct drm_device *dev)
918 : {
919 : struct drm_i915_private *dev_priv = dev->dev_private;
920 : struct intel_guc *guc = &dev_priv->guc;
921 :
922 : gem_release_guc_obj(dev_priv->guc.log_obj);
923 : guc->log_obj = NULL;
924 :
925 : if (guc->ctx_pool_obj)
926 : ida_destroy(&guc->ctx_ids);
927 : gem_release_guc_obj(guc->ctx_pool_obj);
928 : guc->ctx_pool_obj = NULL;
929 : }
930 :
931 : /**
932 : * intel_guc_suspend() - notify GuC entering suspend state
933 : * @dev: drm device
934 : */
935 : int intel_guc_suspend(struct drm_device *dev)
936 : {
937 : struct drm_i915_private *dev_priv = dev->dev_private;
938 : struct intel_guc *guc = &dev_priv->guc;
939 : struct intel_context *ctx;
940 : u32 data[3];
941 :
942 : if (!i915.enable_guc_submission)
943 : return 0;
944 :
945 : ctx = dev_priv->ring[RCS].default_context;
946 :
947 : data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
948 : /* any value greater than GUC_POWER_D0 */
949 : data[1] = GUC_POWER_D1;
950 : /* first page is shared data with GuC */
951 : data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
952 :
953 : return host2guc_action(guc, data, ARRAY_SIZE(data));
954 : }
955 :
956 :
957 : /**
958 : * intel_guc_resume() - notify GuC resuming from suspend state
959 : * @dev: drm device
960 : */
961 : int intel_guc_resume(struct drm_device *dev)
962 : {
963 : struct drm_i915_private *dev_priv = dev->dev_private;
964 : struct intel_guc *guc = &dev_priv->guc;
965 : struct intel_context *ctx;
966 : u32 data[3];
967 :
968 : if (!i915.enable_guc_submission)
969 : return 0;
970 :
971 : ctx = dev_priv->ring[RCS].default_context;
972 :
973 : data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
974 : data[1] = GUC_POWER_D0;
975 : /* first page is shared data with GuC */
976 : data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
977 :
978 : return host2guc_action(guc, data, ARRAY_SIZE(data));
979 : }
980 :
981 : #else
982 :
983 0 : int i915_guc_submit(struct i915_guc_client *client,
984 : struct drm_i915_gem_request *rq)
985 : {
986 0 : panic("%s", __func__);
987 : }
988 :
989 : #endif
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