Line data Source code
1 : /*
2 : * Copyright © 2012 Intel Corporation
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice (including the next
12 : * paragraph) shall be included in all copies or substantial portions of the
13 : * Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 : * IN THE SOFTWARE.
22 : *
23 : * Authors:
24 : * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 : *
26 : */
27 :
28 : #include "i915_drv.h"
29 : #include "intel_drv.h"
30 :
31 : struct ddi_buf_trans {
32 : u32 trans1; /* balance leg enable, de-emph level */
33 : u32 trans2; /* vref sel, vswing */
34 : u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 : };
36 :
37 : /* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 : * them for both DP and FDI transports, allowing those ports to
39 : * automatically adapt to HDMI connections as well
40 : */
41 : static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
42 : { 0x00FFFFFF, 0x0006000E, 0x0 },
43 : { 0x00D75FFF, 0x0005000A, 0x0 },
44 : { 0x00C30FFF, 0x00040006, 0x0 },
45 : { 0x80AAAFFF, 0x000B0000, 0x0 },
46 : { 0x00FFFFFF, 0x0005000A, 0x0 },
47 : { 0x00D75FFF, 0x000C0004, 0x0 },
48 : { 0x80C30FFF, 0x000B0000, 0x0 },
49 : { 0x00FFFFFF, 0x00040006, 0x0 },
50 : { 0x80D75FFF, 0x000B0000, 0x0 },
51 : };
52 :
53 : static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
54 : { 0x00FFFFFF, 0x0007000E, 0x0 },
55 : { 0x00D75FFF, 0x000F000A, 0x0 },
56 : { 0x00C30FFF, 0x00060006, 0x0 },
57 : { 0x00AAAFFF, 0x001E0000, 0x0 },
58 : { 0x00FFFFFF, 0x000F000A, 0x0 },
59 : { 0x00D75FFF, 0x00160004, 0x0 },
60 : { 0x00C30FFF, 0x001E0000, 0x0 },
61 : { 0x00FFFFFF, 0x00060006, 0x0 },
62 : { 0x00D75FFF, 0x001E0000, 0x0 },
63 : };
64 :
65 : static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 : /* Idx NT mV d T mV d db */
67 : { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 : { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 : { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 : { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 : { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 : { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 : { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 : { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 : { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 : { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 : { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 : { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
79 : };
80 :
81 : static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
82 : { 0x00FFFFFF, 0x00000012, 0x0 },
83 : { 0x00EBAFFF, 0x00020011, 0x0 },
84 : { 0x00C71FFF, 0x0006000F, 0x0 },
85 : { 0x00AAAFFF, 0x000E000A, 0x0 },
86 : { 0x00FFFFFF, 0x00020011, 0x0 },
87 : { 0x00DB6FFF, 0x0005000F, 0x0 },
88 : { 0x00BEEFFF, 0x000A000C, 0x0 },
89 : { 0x00FFFFFF, 0x0005000F, 0x0 },
90 : { 0x00DB6FFF, 0x000A000C, 0x0 },
91 : };
92 :
93 : static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
94 : { 0x00FFFFFF, 0x0007000E, 0x0 },
95 : { 0x00D75FFF, 0x000E000A, 0x0 },
96 : { 0x00BEFFFF, 0x00140006, 0x0 },
97 : { 0x80B2CFFF, 0x001B0002, 0x0 },
98 : { 0x00FFFFFF, 0x000E000A, 0x0 },
99 : { 0x00DB6FFF, 0x00160005, 0x0 },
100 : { 0x80C71FFF, 0x001A0002, 0x0 },
101 : { 0x00F7DFFF, 0x00180004, 0x0 },
102 : { 0x80D75FFF, 0x001B0002, 0x0 },
103 : };
104 :
105 : static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
106 : { 0x00FFFFFF, 0x0001000E, 0x0 },
107 : { 0x00D75FFF, 0x0004000A, 0x0 },
108 : { 0x00C30FFF, 0x00070006, 0x0 },
109 : { 0x00AAAFFF, 0x000C0000, 0x0 },
110 : { 0x00FFFFFF, 0x0004000A, 0x0 },
111 : { 0x00D75FFF, 0x00090004, 0x0 },
112 : { 0x00C30FFF, 0x000C0000, 0x0 },
113 : { 0x00FFFFFF, 0x00070006, 0x0 },
114 : { 0x00D75FFF, 0x000C0000, 0x0 },
115 : };
116 :
117 : static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 : /* Idx NT mV d T mV df db */
119 : { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 : { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 : { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 : { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 : { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 : { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 : { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 : { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 : { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 : { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
129 : };
130 :
131 : /* Skylake H and S */
132 : static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
133 : { 0x00002016, 0x000000A0, 0x0 },
134 : { 0x00005012, 0x0000009B, 0x0 },
135 : { 0x00007011, 0x00000088, 0x0 },
136 : { 0x00009010, 0x000000C7, 0x0 },
137 : { 0x00002016, 0x0000009B, 0x0 },
138 : { 0x00005012, 0x00000088, 0x0 },
139 : { 0x00007011, 0x000000C7, 0x0 },
140 : { 0x00002016, 0x000000DF, 0x0 },
141 : { 0x00005012, 0x000000C7, 0x0 },
142 : };
143 :
144 : /* Skylake U */
145 : static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 : { 0x0000201B, 0x000000A2, 0x0 },
147 : { 0x00005012, 0x00000088, 0x0 },
148 : { 0x00007011, 0x00000087, 0x0 },
149 : { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */
150 : { 0x0000201B, 0x0000009D, 0x0 },
151 : { 0x00005012, 0x000000C7, 0x0 },
152 : { 0x00007011, 0x000000C7, 0x0 },
153 : { 0x00002016, 0x00000088, 0x0 },
154 : { 0x00005012, 0x000000C7, 0x0 },
155 : };
156 :
157 : /* Skylake Y */
158 : static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
159 : { 0x00000018, 0x000000A2, 0x0 },
160 : { 0x00005012, 0x00000088, 0x0 },
161 : { 0x00007011, 0x00000087, 0x0 },
162 : { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */
163 : { 0x00000018, 0x0000009D, 0x0 },
164 : { 0x00005012, 0x000000C7, 0x0 },
165 : { 0x00007011, 0x000000C7, 0x0 },
166 : { 0x00000018, 0x00000088, 0x0 },
167 : { 0x00005012, 0x000000C7, 0x0 },
168 : };
169 :
170 : /*
171 : * Skylake H and S
172 : * eDP 1.4 low vswing translation parameters
173 : */
174 : static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
175 : { 0x00000018, 0x000000A8, 0x0 },
176 : { 0x00004013, 0x000000A9, 0x0 },
177 : { 0x00007011, 0x000000A2, 0x0 },
178 : { 0x00009010, 0x0000009C, 0x0 },
179 : { 0x00000018, 0x000000A9, 0x0 },
180 : { 0x00006013, 0x000000A2, 0x0 },
181 : { 0x00007011, 0x000000A6, 0x0 },
182 : { 0x00000018, 0x000000AB, 0x0 },
183 : { 0x00007013, 0x0000009F, 0x0 },
184 : { 0x00000018, 0x000000DF, 0x0 },
185 : };
186 :
187 : /*
188 : * Skylake U
189 : * eDP 1.4 low vswing translation parameters
190 : */
191 : static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 : { 0x00000018, 0x000000A8, 0x0 },
193 : { 0x00004013, 0x000000A9, 0x0 },
194 : { 0x00007011, 0x000000A2, 0x0 },
195 : { 0x00009010, 0x0000009C, 0x0 },
196 : { 0x00000018, 0x000000A9, 0x0 },
197 : { 0x00006013, 0x000000A2, 0x0 },
198 : { 0x00007011, 0x000000A6, 0x0 },
199 : { 0x00002016, 0x000000AB, 0x0 },
200 : { 0x00005013, 0x0000009F, 0x0 },
201 : { 0x00000018, 0x000000DF, 0x0 },
202 : };
203 :
204 : /*
205 : * Skylake Y
206 : * eDP 1.4 low vswing translation parameters
207 : */
208 : static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
209 : { 0x00000018, 0x000000A8, 0x0 },
210 : { 0x00004013, 0x000000AB, 0x0 },
211 : { 0x00007011, 0x000000A4, 0x0 },
212 : { 0x00009010, 0x000000DF, 0x0 },
213 : { 0x00000018, 0x000000AA, 0x0 },
214 : { 0x00006013, 0x000000A4, 0x0 },
215 : { 0x00007011, 0x0000009D, 0x0 },
216 : { 0x00000018, 0x000000A0, 0x0 },
217 : { 0x00006012, 0x000000DF, 0x0 },
218 : { 0x00000018, 0x0000008A, 0x0 },
219 : };
220 :
221 : /* Skylake U, H and S */
222 : static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
223 : { 0x00000018, 0x000000AC, 0x0 },
224 : { 0x00005012, 0x0000009D, 0x0 },
225 : { 0x00007011, 0x00000088, 0x0 },
226 : { 0x00000018, 0x000000A1, 0x0 },
227 : { 0x00000018, 0x00000098, 0x0 },
228 : { 0x00004013, 0x00000088, 0x0 },
229 : { 0x00006012, 0x00000087, 0x0 },
230 : { 0x00000018, 0x000000DF, 0x0 },
231 : { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 : { 0x00003015, 0x000000C7, 0x0 },
233 : { 0x00000018, 0x000000C7, 0x0 },
234 : };
235 :
236 : /* Skylake Y */
237 : static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
238 : { 0x00000018, 0x000000A1, 0x0 },
239 : { 0x00005012, 0x000000DF, 0x0 },
240 : { 0x00007011, 0x00000084, 0x0 },
241 : { 0x00000018, 0x000000A4, 0x0 },
242 : { 0x00000018, 0x0000009D, 0x0 },
243 : { 0x00004013, 0x00000080, 0x0 },
244 : { 0x00006013, 0x000000C7, 0x0 },
245 : { 0x00000018, 0x0000008A, 0x0 },
246 : { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 : { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */
248 : { 0x00000018, 0x000000C7, 0x0 },
249 : };
250 :
251 : struct bxt_ddi_buf_trans {
252 : u32 margin; /* swing value */
253 : u32 scale; /* scale value */
254 : u32 enable; /* scale enable */
255 : u32 deemphasis;
256 : bool default_index; /* true if the entry represents default value */
257 : };
258 :
259 : static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 : /* Idx NT mV diff db */
261 : { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 : { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 : { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 : { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 : { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 : { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 : { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 : { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 : { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
270 : { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
271 : };
272 :
273 : static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 : /* Idx NT mV diff db */
275 : { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 : { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 : { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 : { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 : { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 : { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 : { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 : { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 : { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 : { 48, 0, 0, 128, false }, /* 9: 300 0 */
285 : };
286 :
287 : /* BSpec has 2 recommended values - entries 0 and 8.
288 : * Using the entry with higher vswing.
289 : */
290 : static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 : /* Idx NT mV diff db */
292 : { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 : { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 : { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 : { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 : { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 : { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 : { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 : { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 : { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
301 : { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302 : };
303 :
304 : static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
305 : enum port port, int type);
306 :
307 0 : static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 : struct intel_digital_port **dig_port,
309 : enum port *port)
310 : {
311 0 : struct drm_encoder *encoder = &intel_encoder->base;
312 :
313 0 : switch (intel_encoder->type) {
314 : case INTEL_OUTPUT_DP_MST:
315 0 : *dig_port = enc_to_mst(encoder)->primary;
316 0 : *port = (*dig_port)->port;
317 0 : break;
318 : case INTEL_OUTPUT_DISPLAYPORT:
319 : case INTEL_OUTPUT_EDP:
320 : case INTEL_OUTPUT_HDMI:
321 : case INTEL_OUTPUT_UNKNOWN:
322 0 : *dig_port = enc_to_dig_port(encoder);
323 0 : *port = (*dig_port)->port;
324 0 : break;
325 : case INTEL_OUTPUT_ANALOG:
326 0 : *dig_port = NULL;
327 0 : *port = PORT_E;
328 0 : break;
329 : default:
330 0 : WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
331 0 : break;
332 : }
333 0 : }
334 :
335 0 : enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336 : {
337 0 : struct intel_digital_port *dig_port;
338 0 : enum port port;
339 :
340 0 : ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341 :
342 0 : return port;
343 0 : }
344 :
345 : static bool
346 0 : intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
347 : {
348 0 : return intel_dig_port->hdmi.hdmi_reg;
349 : }
350 :
351 0 : static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
352 : int *n_entries)
353 : {
354 : const struct ddi_buf_trans *ddi_translations;
355 :
356 0 : if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
357 : ddi_translations = skl_y_ddi_translations_dp;
358 0 : *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
359 0 : } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
360 : ddi_translations = skl_u_ddi_translations_dp;
361 0 : *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
362 0 : } else {
363 : ddi_translations = skl_ddi_translations_dp;
364 0 : *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
365 : }
366 :
367 0 : return ddi_translations;
368 : }
369 :
370 0 : static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
371 : int *n_entries)
372 : {
373 0 : struct drm_i915_private *dev_priv = dev->dev_private;
374 : const struct ddi_buf_trans *ddi_translations;
375 :
376 0 : if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
377 0 : if (dev_priv->edp_low_vswing) {
378 : ddi_translations = skl_y_ddi_translations_edp;
379 0 : *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
380 0 : } else {
381 : ddi_translations = skl_y_ddi_translations_dp;
382 0 : *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
383 : }
384 0 : } else if (IS_SKL_ULT(dev) || IS_KBL_ULT(dev)) {
385 0 : if (dev_priv->edp_low_vswing) {
386 : ddi_translations = skl_u_ddi_translations_edp;
387 0 : *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
388 0 : } else {
389 : ddi_translations = skl_u_ddi_translations_dp;
390 0 : *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
391 : }
392 : } else {
393 0 : if (dev_priv->edp_low_vswing) {
394 : ddi_translations = skl_ddi_translations_edp;
395 0 : *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
396 0 : } else {
397 : ddi_translations = skl_ddi_translations_dp;
398 0 : *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
399 : }
400 : }
401 :
402 0 : return ddi_translations;
403 : }
404 :
405 : static const struct ddi_buf_trans *
406 0 : skl_get_buf_trans_hdmi(struct drm_device *dev,
407 : int *n_entries)
408 : {
409 : const struct ddi_buf_trans *ddi_translations;
410 :
411 0 : if (IS_SKL_ULX(dev) || IS_KBL_ULX(dev)) {
412 : ddi_translations = skl_y_ddi_translations_hdmi;
413 0 : *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
414 0 : } else {
415 : ddi_translations = skl_ddi_translations_hdmi;
416 0 : *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
417 : }
418 :
419 0 : return ddi_translations;
420 : }
421 :
422 : /*
423 : * Starting with Haswell, DDI port buffers must be programmed with correct
424 : * values in advance. The buffer values are different for FDI and DP modes,
425 : * but the HDMI/DVI fields are shared among those. So we program the DDI
426 : * in either FDI or DP modes only, as HDMI connections will work with both
427 : * of those
428 : */
429 0 : static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
430 : bool supports_hdmi)
431 : {
432 0 : struct drm_i915_private *dev_priv = dev->dev_private;
433 : u32 iboost_bit = 0;
434 0 : int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
435 : size;
436 0 : int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
437 : const struct ddi_buf_trans *ddi_translations_fdi;
438 : const struct ddi_buf_trans *ddi_translations_dp;
439 : const struct ddi_buf_trans *ddi_translations_edp;
440 : const struct ddi_buf_trans *ddi_translations_hdmi;
441 : const struct ddi_buf_trans *ddi_translations;
442 :
443 0 : if (IS_BROXTON(dev)) {
444 0 : if (!supports_hdmi)
445 0 : return;
446 :
447 : /* Vswing programming for HDMI */
448 0 : bxt_ddi_vswing_sequence(dev, hdmi_level, port,
449 : INTEL_OUTPUT_HDMI);
450 0 : return;
451 0 : } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
452 : ddi_translations_fdi = NULL;
453 : ddi_translations_dp =
454 0 : skl_get_buf_trans_dp(dev, &n_dp_entries);
455 : ddi_translations_edp =
456 0 : skl_get_buf_trans_edp(dev, &n_edp_entries);
457 : ddi_translations_hdmi =
458 0 : skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
459 : hdmi_default_entry = 8;
460 : /* If we're boosting the current, set bit 31 of trans1 */
461 0 : if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
462 0 : dev_priv->vbt.ddi_port_info[port].dp_boost_level)
463 0 : iboost_bit = 1<<31;
464 0 : } else if (IS_BROADWELL(dev)) {
465 : ddi_translations_fdi = bdw_ddi_translations_fdi;
466 : ddi_translations_dp = bdw_ddi_translations_dp;
467 :
468 0 : if (dev_priv->edp_low_vswing) {
469 : ddi_translations_edp = bdw_ddi_translations_edp;
470 0 : n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
471 0 : } else {
472 : ddi_translations_edp = bdw_ddi_translations_dp;
473 0 : n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
474 : }
475 :
476 : ddi_translations_hdmi = bdw_ddi_translations_hdmi;
477 :
478 0 : n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
479 0 : n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
480 : hdmi_default_entry = 7;
481 0 : } else if (IS_HASWELL(dev)) {
482 : ddi_translations_fdi = hsw_ddi_translations_fdi;
483 : ddi_translations_dp = hsw_ddi_translations_dp;
484 : ddi_translations_edp = hsw_ddi_translations_dp;
485 : ddi_translations_hdmi = hsw_ddi_translations_hdmi;
486 0 : n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
487 0 : n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
488 : hdmi_default_entry = 6;
489 0 : } else {
490 0 : WARN(1, "ddi translation table missing\n");
491 : ddi_translations_edp = bdw_ddi_translations_dp;
492 : ddi_translations_fdi = bdw_ddi_translations_fdi;
493 : ddi_translations_dp = bdw_ddi_translations_dp;
494 : ddi_translations_hdmi = bdw_ddi_translations_hdmi;
495 0 : n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
496 0 : n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
497 0 : n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
498 : hdmi_default_entry = 7;
499 : }
500 :
501 0 : switch (port) {
502 : case PORT_A:
503 : ddi_translations = ddi_translations_edp;
504 0 : size = n_edp_entries;
505 0 : break;
506 : case PORT_B:
507 : case PORT_C:
508 : ddi_translations = ddi_translations_dp;
509 0 : size = n_dp_entries;
510 0 : break;
511 : case PORT_D:
512 0 : if (intel_dp_is_edp(dev, PORT_D)) {
513 : ddi_translations = ddi_translations_edp;
514 0 : size = n_edp_entries;
515 0 : } else {
516 : ddi_translations = ddi_translations_dp;
517 0 : size = n_dp_entries;
518 : }
519 : break;
520 : case PORT_E:
521 0 : if (ddi_translations_fdi)
522 0 : ddi_translations = ddi_translations_fdi;
523 : else
524 : ddi_translations = ddi_translations_dp;
525 0 : size = n_dp_entries;
526 0 : break;
527 : default:
528 0 : BUG();
529 : }
530 :
531 0 : for (i = 0; i < size; i++) {
532 0 : I915_WRITE(DDI_BUF_TRANS_LO(port, i),
533 : ddi_translations[i].trans1 | iboost_bit);
534 0 : I915_WRITE(DDI_BUF_TRANS_HI(port, i),
535 : ddi_translations[i].trans2);
536 : }
537 :
538 0 : if (!supports_hdmi)
539 0 : return;
540 :
541 : /* Choose a good default if VBT is badly populated */
542 0 : if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
543 0 : hdmi_level >= n_hdmi_entries)
544 0 : hdmi_level = hdmi_default_entry;
545 :
546 : /* Entry 9 is for HDMI: */
547 0 : I915_WRITE(DDI_BUF_TRANS_LO(port, i),
548 : ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
549 0 : I915_WRITE(DDI_BUF_TRANS_HI(port, i),
550 : ddi_translations_hdmi[hdmi_level].trans2);
551 0 : }
552 :
553 : /* Program DDI buffers translations for DP. By default, program ports A-D in DP
554 : * mode and port E for FDI.
555 : */
556 0 : void intel_prepare_ddi(struct drm_device *dev)
557 : {
558 : struct intel_encoder *intel_encoder;
559 0 : bool visited[I915_MAX_PORTS] = { 0, };
560 :
561 0 : if (!HAS_DDI(dev))
562 0 : return;
563 :
564 0 : for_each_intel_encoder(dev, intel_encoder) {
565 0 : struct intel_digital_port *intel_dig_port;
566 0 : enum port port;
567 : bool supports_hdmi;
568 :
569 0 : if (intel_encoder->type == INTEL_OUTPUT_DSI)
570 0 : continue;
571 :
572 0 : ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
573 0 : if (visited[port])
574 0 : continue;
575 :
576 0 : supports_hdmi = intel_dig_port &&
577 0 : intel_dig_port_supports_hdmi(intel_dig_port);
578 :
579 0 : intel_prepare_ddi_buffers(dev, port, supports_hdmi);
580 0 : visited[port] = true;
581 0 : }
582 0 : }
583 :
584 0 : static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
585 : enum port port)
586 : {
587 0 : uint32_t reg = DDI_BUF_CTL(port);
588 : int i;
589 :
590 0 : for (i = 0; i < 16; i++) {
591 0 : udelay(1);
592 0 : if (I915_READ(reg) & DDI_BUF_IS_IDLE)
593 0 : return;
594 : }
595 0 : DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
596 0 : }
597 :
598 : /* Starting with Haswell, different DDI ports can work in FDI mode for
599 : * connection to the PCH-located connectors. For this, it is necessary to train
600 : * both the DDI port and PCH receiver for the desired DDI buffer settings.
601 : *
602 : * The recommended port to work in FDI mode is DDI E, which we use here. Also,
603 : * please note that when FDI mode is active on DDI E, it shares 2 lines with
604 : * DDI A (which is used for eDP)
605 : */
606 :
607 0 : void hsw_fdi_link_train(struct drm_crtc *crtc)
608 : {
609 0 : struct drm_device *dev = crtc->dev;
610 0 : struct drm_i915_private *dev_priv = dev->dev_private;
611 0 : struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
612 : u32 temp, i, rx_ctl_val;
613 :
614 : /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
615 : * mode set "sequence for CRT port" document:
616 : * - TP1 to TP2 time with the default value
617 : * - FDI delay to 90h
618 : *
619 : * WaFDIAutoLinkSetTimingOverrride:hsw
620 : */
621 0 : I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
622 : FDI_RX_PWRDN_LANE0_VAL(2) |
623 : FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
624 :
625 : /* Enable the PCH Receiver FDI PLL */
626 0 : rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
627 0 : FDI_RX_PLL_ENABLE |
628 0 : FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
629 0 : I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
630 0 : POSTING_READ(FDI_RX_CTL(PIPE_A));
631 0 : udelay(220);
632 :
633 : /* Switch from Rawclk to PCDclk */
634 0 : rx_ctl_val |= FDI_PCDCLK;
635 0 : I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
636 :
637 : /* Configure Port Clock Select */
638 0 : I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
639 0 : WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
640 :
641 : /* Start the training iterating through available voltages and emphasis,
642 : * testing each value twice. */
643 0 : for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
644 : /* Configure DP_TP_CTL with auto-training */
645 0 : I915_WRITE(DP_TP_CTL(PORT_E),
646 : DP_TP_CTL_FDI_AUTOTRAIN |
647 : DP_TP_CTL_ENHANCED_FRAME_ENABLE |
648 : DP_TP_CTL_LINK_TRAIN_PAT1 |
649 : DP_TP_CTL_ENABLE);
650 :
651 : /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
652 : * DDI E does not support port reversal, the functionality is
653 : * achieved on the PCH side in FDI_RX_CTL, so no need to set the
654 : * port reversal bit */
655 0 : I915_WRITE(DDI_BUF_CTL(PORT_E),
656 : DDI_BUF_CTL_ENABLE |
657 : ((intel_crtc->config->fdi_lanes - 1) << 1) |
658 : DDI_BUF_TRANS_SELECT(i / 2));
659 0 : POSTING_READ(DDI_BUF_CTL(PORT_E));
660 :
661 0 : udelay(600);
662 :
663 : /* Program PCH FDI Receiver TU */
664 0 : I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
665 :
666 : /* Enable PCH FDI Receiver with auto-training */
667 0 : rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
668 0 : I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
669 0 : POSTING_READ(FDI_RX_CTL(PIPE_A));
670 :
671 : /* Wait for FDI receiver lane calibration */
672 0 : udelay(30);
673 :
674 : /* Unset FDI_RX_MISC pwrdn lanes */
675 0 : temp = I915_READ(FDI_RX_MISC(PIPE_A));
676 0 : temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
677 0 : I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
678 0 : POSTING_READ(FDI_RX_MISC(PIPE_A));
679 :
680 : /* Wait for FDI auto training time */
681 0 : udelay(5);
682 :
683 0 : temp = I915_READ(DP_TP_STATUS(PORT_E));
684 0 : if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
685 : DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
686 :
687 : /* Enable normal pixel sending for FDI */
688 0 : I915_WRITE(DP_TP_CTL(PORT_E),
689 : DP_TP_CTL_FDI_AUTOTRAIN |
690 : DP_TP_CTL_LINK_TRAIN_NORMAL |
691 : DP_TP_CTL_ENHANCED_FRAME_ENABLE |
692 : DP_TP_CTL_ENABLE);
693 :
694 0 : return;
695 : }
696 :
697 0 : temp = I915_READ(DDI_BUF_CTL(PORT_E));
698 0 : temp &= ~DDI_BUF_CTL_ENABLE;
699 0 : I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
700 0 : POSTING_READ(DDI_BUF_CTL(PORT_E));
701 :
702 : /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
703 0 : temp = I915_READ(DP_TP_CTL(PORT_E));
704 0 : temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
705 : temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
706 0 : I915_WRITE(DP_TP_CTL(PORT_E), temp);
707 0 : POSTING_READ(DP_TP_CTL(PORT_E));
708 :
709 0 : intel_wait_ddi_buf_idle(dev_priv, PORT_E);
710 :
711 0 : rx_ctl_val &= ~FDI_RX_ENABLE;
712 0 : I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
713 0 : POSTING_READ(FDI_RX_CTL(PIPE_A));
714 :
715 : /* Reset FDI_RX_MISC pwrdn lanes */
716 0 : temp = I915_READ(FDI_RX_MISC(PIPE_A));
717 0 : temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
718 0 : temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
719 0 : I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
720 0 : POSTING_READ(FDI_RX_MISC(PIPE_A));
721 : }
722 :
723 0 : DRM_ERROR("FDI link training failed!\n");
724 0 : }
725 :
726 0 : void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
727 : {
728 0 : struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
729 : struct intel_digital_port *intel_dig_port =
730 0 : enc_to_dig_port(&encoder->base);
731 :
732 0 : intel_dp->DP = intel_dig_port->saved_port_bits |
733 : DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
734 0 : intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
735 0 : }
736 :
737 : static struct intel_encoder *
738 0 : intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
739 : {
740 0 : struct drm_device *dev = crtc->dev;
741 0 : struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742 : struct intel_encoder *intel_encoder, *ret = NULL;
743 : int num_encoders = 0;
744 :
745 0 : for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
746 : ret = intel_encoder;
747 0 : num_encoders++;
748 0 : }
749 :
750 0 : if (num_encoders != 1)
751 0 : WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
752 : pipe_name(intel_crtc->pipe));
753 :
754 0 : BUG_ON(ret == NULL);
755 0 : return ret;
756 : }
757 :
758 : struct intel_encoder *
759 0 : intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
760 : {
761 0 : struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
762 : struct intel_encoder *ret = NULL;
763 : struct drm_atomic_state *state;
764 : struct drm_connector *connector;
765 : struct drm_connector_state *connector_state;
766 : int num_encoders = 0;
767 : int i;
768 :
769 0 : state = crtc_state->base.state;
770 :
771 0 : for_each_connector_in_state(state, connector, connector_state, i) {
772 0 : if (connector_state->crtc != crtc_state->base.crtc)
773 : continue;
774 :
775 0 : ret = to_intel_encoder(connector_state->best_encoder);
776 0 : num_encoders++;
777 0 : }
778 :
779 0 : WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
780 : pipe_name(crtc->pipe));
781 :
782 0 : BUG_ON(ret == NULL);
783 0 : return ret;
784 : }
785 :
786 : #define LC_FREQ 2700
787 : #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
788 :
789 : #define P_MIN 2
790 : #define P_MAX 64
791 : #define P_INC 2
792 :
793 : /* Constraints for PLL good behavior */
794 : #define REF_MIN 48
795 : #define REF_MAX 400
796 : #define VCO_MIN 2400
797 : #define VCO_MAX 4800
798 :
799 : #define abs_diff(a, b) ({ \
800 : typeof(a) __a = (a); \
801 : typeof(b) __b = (b); \
802 : (void) (&__a == &__b); \
803 : __a > __b ? (__a - __b) : (__b - __a); })
804 :
805 : struct hsw_wrpll_rnp {
806 : unsigned p, n2, r2;
807 : };
808 :
809 0 : static unsigned hsw_wrpll_get_budget_for_freq(int clock)
810 : {
811 : unsigned budget;
812 :
813 0 : switch (clock) {
814 : case 25175000:
815 : case 25200000:
816 : case 27000000:
817 : case 27027000:
818 : case 37762500:
819 : case 37800000:
820 : case 40500000:
821 : case 40541000:
822 : case 54000000:
823 : case 54054000:
824 : case 59341000:
825 : case 59400000:
826 : case 72000000:
827 : case 74176000:
828 : case 74250000:
829 : case 81000000:
830 : case 81081000:
831 : case 89012000:
832 : case 89100000:
833 : case 108000000:
834 : case 108108000:
835 : case 111264000:
836 : case 111375000:
837 : case 148352000:
838 : case 148500000:
839 : case 162000000:
840 : case 162162000:
841 : case 222525000:
842 : case 222750000:
843 : case 296703000:
844 : case 297000000:
845 : budget = 0;
846 0 : break;
847 : case 233500000:
848 : case 245250000:
849 : case 247750000:
850 : case 253250000:
851 : case 298000000:
852 : budget = 1500;
853 0 : break;
854 : case 169128000:
855 : case 169500000:
856 : case 179500000:
857 : case 202000000:
858 : budget = 2000;
859 0 : break;
860 : case 256250000:
861 : case 262500000:
862 : case 270000000:
863 : case 272500000:
864 : case 273750000:
865 : case 280750000:
866 : case 281250000:
867 : case 286000000:
868 : case 291750000:
869 : budget = 4000;
870 0 : break;
871 : case 267250000:
872 : case 268500000:
873 : budget = 5000;
874 0 : break;
875 : default:
876 : budget = 1000;
877 0 : break;
878 : }
879 :
880 0 : return budget;
881 : }
882 :
883 0 : static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
884 : unsigned r2, unsigned n2, unsigned p,
885 : struct hsw_wrpll_rnp *best)
886 : {
887 : uint64_t a, b, c, d, diff, diff_best;
888 :
889 : /* No best (r,n,p) yet */
890 0 : if (best->p == 0) {
891 0 : best->p = p;
892 0 : best->n2 = n2;
893 0 : best->r2 = r2;
894 0 : return;
895 : }
896 :
897 : /*
898 : * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
899 : * freq2k.
900 : *
901 : * delta = 1e6 *
902 : * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
903 : * freq2k;
904 : *
905 : * and we would like delta <= budget.
906 : *
907 : * If the discrepancy is above the PPM-based budget, always prefer to
908 : * improve upon the previous solution. However, if you're within the
909 : * budget, try to maximize Ref * VCO, that is N / (P * R^2).
910 : */
911 0 : a = freq2k * budget * p * r2;
912 0 : b = freq2k * budget * best->p * best->r2;
913 0 : diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
914 0 : diff_best = abs_diff(freq2k * best->p * best->r2,
915 : LC_FREQ_2K * best->n2);
916 0 : c = 1000000 * diff;
917 0 : d = 1000000 * diff_best;
918 :
919 0 : if (a < c && b < d) {
920 : /* If both are above the budget, pick the closer */
921 0 : if (best->p * best->r2 * diff < p * r2 * diff_best) {
922 0 : best->p = p;
923 0 : best->n2 = n2;
924 0 : best->r2 = r2;
925 0 : }
926 0 : } else if (a >= c && b < d) {
927 : /* If A is below the threshold but B is above it? Update. */
928 0 : best->p = p;
929 0 : best->n2 = n2;
930 0 : best->r2 = r2;
931 0 : } else if (a >= c && b >= d) {
932 : /* Both are below the limit, so pick the higher n2/(r2*r2) */
933 0 : if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
934 0 : best->p = p;
935 0 : best->n2 = n2;
936 0 : best->r2 = r2;
937 0 : }
938 : }
939 : /* Otherwise a < c && b >= d, do nothing */
940 0 : }
941 :
942 0 : static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
943 : {
944 : int refclk = LC_FREQ;
945 : int n, p, r;
946 : u32 wrpll;
947 :
948 0 : wrpll = I915_READ(reg);
949 0 : switch (wrpll & WRPLL_PLL_REF_MASK) {
950 : case WRPLL_PLL_SSC:
951 : case WRPLL_PLL_NON_SSC:
952 : /*
953 : * We could calculate spread here, but our checking
954 : * code only cares about 5% accuracy, and spread is a max of
955 : * 0.5% downspread.
956 : */
957 : refclk = 135;
958 0 : break;
959 : case WRPLL_PLL_LCPLL:
960 : refclk = LC_FREQ;
961 0 : break;
962 : default:
963 0 : WARN(1, "bad wrpll refclk\n");
964 0 : return 0;
965 : }
966 :
967 0 : r = wrpll & WRPLL_DIVIDER_REF_MASK;
968 0 : p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
969 0 : n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
970 :
971 : /* Convert to KHz, p & r have a fixed point portion */
972 0 : return (refclk * n * 100) / (p * r);
973 0 : }
974 :
975 0 : static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
976 : uint32_t dpll)
977 : {
978 : uint32_t cfgcr1_reg, cfgcr2_reg;
979 : uint32_t cfgcr1_val, cfgcr2_val;
980 : uint32_t p0, p1, p2, dco_freq;
981 :
982 0 : cfgcr1_reg = DPLL_CFGCR1(dpll);
983 0 : cfgcr2_reg = DPLL_CFGCR2(dpll);
984 :
985 0 : cfgcr1_val = I915_READ(cfgcr1_reg);
986 0 : cfgcr2_val = I915_READ(cfgcr2_reg);
987 :
988 0 : p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
989 0 : p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
990 :
991 0 : if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
992 0 : p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
993 : else
994 : p1 = 1;
995 :
996 :
997 0 : switch (p0) {
998 : case DPLL_CFGCR2_PDIV_1:
999 : p0 = 1;
1000 0 : break;
1001 : case DPLL_CFGCR2_PDIV_2:
1002 : p0 = 2;
1003 0 : break;
1004 : case DPLL_CFGCR2_PDIV_3:
1005 : p0 = 3;
1006 0 : break;
1007 : case DPLL_CFGCR2_PDIV_7:
1008 : p0 = 7;
1009 0 : break;
1010 : }
1011 :
1012 0 : switch (p2) {
1013 : case DPLL_CFGCR2_KDIV_5:
1014 : p2 = 5;
1015 0 : break;
1016 : case DPLL_CFGCR2_KDIV_2:
1017 : p2 = 2;
1018 0 : break;
1019 : case DPLL_CFGCR2_KDIV_3:
1020 : p2 = 3;
1021 0 : break;
1022 : case DPLL_CFGCR2_KDIV_1:
1023 : p2 = 1;
1024 0 : break;
1025 : }
1026 :
1027 0 : dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1028 :
1029 0 : dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1030 0 : 1000) / 0x8000;
1031 :
1032 0 : return dco_freq / (p0 * p1 * p2 * 5);
1033 : }
1034 :
1035 0 : static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1036 : {
1037 : int dotclock;
1038 :
1039 0 : if (pipe_config->has_pch_encoder)
1040 0 : dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1041 0 : &pipe_config->fdi_m_n);
1042 0 : else if (pipe_config->has_dp_encoder)
1043 0 : dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1044 0 : &pipe_config->dp_m_n);
1045 0 : else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
1046 0 : dotclock = pipe_config->port_clock * 2 / 3;
1047 : else
1048 0 : dotclock = pipe_config->port_clock;
1049 :
1050 0 : if (pipe_config->pixel_multiplier)
1051 0 : dotclock /= pipe_config->pixel_multiplier;
1052 :
1053 0 : pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1054 0 : }
1055 :
1056 0 : static void skl_ddi_clock_get(struct intel_encoder *encoder,
1057 : struct intel_crtc_state *pipe_config)
1058 : {
1059 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1060 : int link_clock = 0;
1061 : uint32_t dpll_ctl1, dpll;
1062 :
1063 0 : dpll = pipe_config->ddi_pll_sel;
1064 :
1065 0 : dpll_ctl1 = I915_READ(DPLL_CTRL1);
1066 :
1067 0 : if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1068 0 : link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1069 0 : } else {
1070 0 : link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1071 0 : link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1072 :
1073 0 : switch (link_clock) {
1074 : case DPLL_CTRL1_LINK_RATE_810:
1075 : link_clock = 81000;
1076 0 : break;
1077 : case DPLL_CTRL1_LINK_RATE_1080:
1078 : link_clock = 108000;
1079 0 : break;
1080 : case DPLL_CTRL1_LINK_RATE_1350:
1081 : link_clock = 135000;
1082 0 : break;
1083 : case DPLL_CTRL1_LINK_RATE_1620:
1084 : link_clock = 162000;
1085 0 : break;
1086 : case DPLL_CTRL1_LINK_RATE_2160:
1087 : link_clock = 216000;
1088 0 : break;
1089 : case DPLL_CTRL1_LINK_RATE_2700:
1090 : link_clock = 270000;
1091 0 : break;
1092 : default:
1093 0 : WARN(1, "Unsupported link rate\n");
1094 0 : break;
1095 : }
1096 0 : link_clock *= 2;
1097 : }
1098 :
1099 0 : pipe_config->port_clock = link_clock;
1100 :
1101 0 : ddi_dotclock_get(pipe_config);
1102 0 : }
1103 :
1104 0 : static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1105 : struct intel_crtc_state *pipe_config)
1106 : {
1107 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1108 : int link_clock = 0;
1109 : u32 val, pll;
1110 :
1111 0 : val = pipe_config->ddi_pll_sel;
1112 0 : switch (val & PORT_CLK_SEL_MASK) {
1113 : case PORT_CLK_SEL_LCPLL_810:
1114 : link_clock = 81000;
1115 0 : break;
1116 : case PORT_CLK_SEL_LCPLL_1350:
1117 : link_clock = 135000;
1118 0 : break;
1119 : case PORT_CLK_SEL_LCPLL_2700:
1120 : link_clock = 270000;
1121 0 : break;
1122 : case PORT_CLK_SEL_WRPLL1:
1123 0 : link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
1124 0 : break;
1125 : case PORT_CLK_SEL_WRPLL2:
1126 0 : link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
1127 0 : break;
1128 : case PORT_CLK_SEL_SPLL:
1129 0 : pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1130 0 : if (pll == SPLL_PLL_FREQ_810MHz)
1131 0 : link_clock = 81000;
1132 0 : else if (pll == SPLL_PLL_FREQ_1350MHz)
1133 0 : link_clock = 135000;
1134 0 : else if (pll == SPLL_PLL_FREQ_2700MHz)
1135 : link_clock = 270000;
1136 : else {
1137 0 : WARN(1, "bad spll freq\n");
1138 0 : return;
1139 : }
1140 : break;
1141 : default:
1142 0 : WARN(1, "bad port clock sel\n");
1143 0 : return;
1144 : }
1145 :
1146 0 : pipe_config->port_clock = link_clock * 2;
1147 :
1148 0 : ddi_dotclock_get(pipe_config);
1149 0 : }
1150 :
1151 0 : static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1152 : enum intel_dpll_id dpll)
1153 : {
1154 : struct intel_shared_dpll *pll;
1155 : struct intel_dpll_hw_state *state;
1156 0 : intel_clock_t clock;
1157 :
1158 : /* For DDI ports we always use a shared PLL. */
1159 0 : if (WARN_ON(dpll == DPLL_ID_PRIVATE))
1160 0 : return 0;
1161 :
1162 0 : pll = &dev_priv->shared_dplls[dpll];
1163 0 : state = &pll->config.hw_state;
1164 :
1165 0 : clock.m1 = 2;
1166 0 : clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
1167 0 : if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1168 0 : clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
1169 0 : clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1170 0 : clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1171 0 : clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1172 :
1173 0 : return chv_calc_dpll_params(100000, &clock);
1174 0 : }
1175 :
1176 0 : static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1177 : struct intel_crtc_state *pipe_config)
1178 : {
1179 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1180 0 : enum port port = intel_ddi_get_encoder_port(encoder);
1181 : uint32_t dpll = port;
1182 :
1183 0 : pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1184 :
1185 0 : ddi_dotclock_get(pipe_config);
1186 0 : }
1187 :
1188 0 : void intel_ddi_clock_get(struct intel_encoder *encoder,
1189 : struct intel_crtc_state *pipe_config)
1190 : {
1191 0 : struct drm_device *dev = encoder->base.dev;
1192 :
1193 0 : if (INTEL_INFO(dev)->gen <= 8)
1194 0 : hsw_ddi_clock_get(encoder, pipe_config);
1195 0 : else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1196 0 : skl_ddi_clock_get(encoder, pipe_config);
1197 0 : else if (IS_BROXTON(dev))
1198 0 : bxt_ddi_clock_get(encoder, pipe_config);
1199 0 : }
1200 :
1201 : static void
1202 0 : hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1203 : unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1204 : {
1205 : uint64_t freq2k;
1206 : unsigned p, n2, r2;
1207 0 : struct hsw_wrpll_rnp best = { 0, 0, 0 };
1208 : unsigned budget;
1209 :
1210 0 : freq2k = clock / 100;
1211 :
1212 0 : budget = hsw_wrpll_get_budget_for_freq(clock);
1213 :
1214 : /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1215 : * and directly pass the LC PLL to it. */
1216 0 : if (freq2k == 5400000) {
1217 0 : *n2_out = 2;
1218 0 : *p_out = 1;
1219 0 : *r2_out = 2;
1220 0 : return;
1221 : }
1222 :
1223 : /*
1224 : * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1225 : * the WR PLL.
1226 : *
1227 : * We want R so that REF_MIN <= Ref <= REF_MAX.
1228 : * Injecting R2 = 2 * R gives:
1229 : * REF_MAX * r2 > LC_FREQ * 2 and
1230 : * REF_MIN * r2 < LC_FREQ * 2
1231 : *
1232 : * Which means the desired boundaries for r2 are:
1233 : * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1234 : *
1235 : */
1236 0 : for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1237 0 : r2 <= LC_FREQ * 2 / REF_MIN;
1238 0 : r2++) {
1239 :
1240 : /*
1241 : * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1242 : *
1243 : * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1244 : * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1245 : * VCO_MAX * r2 > n2 * LC_FREQ and
1246 : * VCO_MIN * r2 < n2 * LC_FREQ)
1247 : *
1248 : * Which means the desired boundaries for n2 are:
1249 : * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1250 : */
1251 0 : for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1252 0 : n2 <= VCO_MAX * r2 / LC_FREQ;
1253 0 : n2++) {
1254 :
1255 0 : for (p = P_MIN; p <= P_MAX; p += P_INC)
1256 0 : hsw_wrpll_update_rnp(freq2k, budget,
1257 : r2, n2, p, &best);
1258 : }
1259 : }
1260 :
1261 0 : *n2_out = best.n2;
1262 0 : *p_out = best.p;
1263 0 : *r2_out = best.r2;
1264 0 : }
1265 :
1266 : static bool
1267 0 : hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
1268 : struct intel_crtc_state *crtc_state,
1269 : struct intel_encoder *intel_encoder)
1270 : {
1271 0 : int clock = crtc_state->port_clock;
1272 :
1273 0 : if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1274 : struct intel_shared_dpll *pll;
1275 : uint32_t val;
1276 0 : unsigned p, n2, r2;
1277 :
1278 0 : hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
1279 :
1280 0 : val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
1281 0 : WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1282 0 : WRPLL_DIVIDER_POST(p);
1283 :
1284 0 : memset(&crtc_state->dpll_hw_state, 0,
1285 : sizeof(crtc_state->dpll_hw_state));
1286 :
1287 0 : crtc_state->dpll_hw_state.wrpll = val;
1288 :
1289 0 : pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1290 0 : if (pll == NULL) {
1291 : DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1292 : pipe_name(intel_crtc->pipe));
1293 0 : return false;
1294 : }
1295 :
1296 0 : crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
1297 0 : } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) {
1298 0 : struct drm_atomic_state *state = crtc_state->base.state;
1299 : struct intel_shared_dpll_config *spll =
1300 0 : &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL];
1301 :
1302 0 : if (spll->crtc_mask &&
1303 0 : WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll))
1304 0 : return false;
1305 :
1306 0 : crtc_state->shared_dpll = DPLL_ID_SPLL;
1307 0 : spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
1308 0 : spll->crtc_mask |= 1 << intel_crtc->pipe;
1309 0 : }
1310 :
1311 0 : return true;
1312 0 : }
1313 :
1314 : struct skl_wrpll_context {
1315 : uint64_t min_deviation; /* current minimal deviation */
1316 : uint64_t central_freq; /* chosen central freq */
1317 : uint64_t dco_freq; /* chosen dco freq */
1318 : unsigned int p; /* chosen divider */
1319 : };
1320 :
1321 0 : static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1322 : {
1323 0 : memset(ctx, 0, sizeof(*ctx));
1324 :
1325 0 : ctx->min_deviation = U64_MAX;
1326 0 : }
1327 :
1328 : /* DCO freq must be within +1%/-6% of the DCO central freq */
1329 : #define SKL_DCO_MAX_PDEVIATION 100
1330 : #define SKL_DCO_MAX_NDEVIATION 600
1331 :
1332 0 : static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1333 : uint64_t central_freq,
1334 : uint64_t dco_freq,
1335 : unsigned int divider)
1336 : {
1337 : uint64_t deviation;
1338 :
1339 0 : deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1340 : central_freq);
1341 :
1342 : /* positive deviation */
1343 0 : if (dco_freq >= central_freq) {
1344 0 : if (deviation < SKL_DCO_MAX_PDEVIATION &&
1345 0 : deviation < ctx->min_deviation) {
1346 0 : ctx->min_deviation = deviation;
1347 0 : ctx->central_freq = central_freq;
1348 0 : ctx->dco_freq = dco_freq;
1349 0 : ctx->p = divider;
1350 0 : }
1351 : /* negative deviation */
1352 0 : } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1353 0 : deviation < ctx->min_deviation) {
1354 0 : ctx->min_deviation = deviation;
1355 0 : ctx->central_freq = central_freq;
1356 0 : ctx->dco_freq = dco_freq;
1357 0 : ctx->p = divider;
1358 0 : }
1359 0 : }
1360 :
1361 0 : static void skl_wrpll_get_multipliers(unsigned int p,
1362 : unsigned int *p0 /* out */,
1363 : unsigned int *p1 /* out */,
1364 : unsigned int *p2 /* out */)
1365 : {
1366 : /* even dividers */
1367 0 : if (p % 2 == 0) {
1368 0 : unsigned int half = p / 2;
1369 :
1370 0 : if (half == 1 || half == 2 || half == 3 || half == 5) {
1371 0 : *p0 = 2;
1372 0 : *p1 = 1;
1373 0 : *p2 = half;
1374 0 : } else if (half % 2 == 0) {
1375 0 : *p0 = 2;
1376 0 : *p1 = half / 2;
1377 0 : *p2 = 2;
1378 0 : } else if (half % 3 == 0) {
1379 0 : *p0 = 3;
1380 0 : *p1 = half / 3;
1381 0 : *p2 = 2;
1382 0 : } else if (half % 7 == 0) {
1383 0 : *p0 = 7;
1384 0 : *p1 = half / 7;
1385 0 : *p2 = 2;
1386 0 : }
1387 0 : } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1388 0 : *p0 = 3;
1389 0 : *p1 = 1;
1390 0 : *p2 = p / 3;
1391 0 : } else if (p == 5 || p == 7) {
1392 0 : *p0 = p;
1393 0 : *p1 = 1;
1394 0 : *p2 = 1;
1395 0 : } else if (p == 15) {
1396 0 : *p0 = 3;
1397 0 : *p1 = 1;
1398 0 : *p2 = 5;
1399 0 : } else if (p == 21) {
1400 0 : *p0 = 7;
1401 0 : *p1 = 1;
1402 0 : *p2 = 3;
1403 0 : } else if (p == 35) {
1404 0 : *p0 = 7;
1405 0 : *p1 = 1;
1406 0 : *p2 = 5;
1407 0 : }
1408 0 : }
1409 :
1410 : struct skl_wrpll_params {
1411 : uint32_t dco_fraction;
1412 : uint32_t dco_integer;
1413 : uint32_t qdiv_ratio;
1414 : uint32_t qdiv_mode;
1415 : uint32_t kdiv;
1416 : uint32_t pdiv;
1417 : uint32_t central_freq;
1418 : };
1419 :
1420 0 : static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1421 : uint64_t afe_clock,
1422 : uint64_t central_freq,
1423 : uint32_t p0, uint32_t p1, uint32_t p2)
1424 : {
1425 : uint64_t dco_freq;
1426 :
1427 0 : switch (central_freq) {
1428 : case 9600000000ULL:
1429 0 : params->central_freq = 0;
1430 0 : break;
1431 : case 9000000000ULL:
1432 0 : params->central_freq = 1;
1433 0 : break;
1434 : case 8400000000ULL:
1435 0 : params->central_freq = 3;
1436 0 : }
1437 :
1438 0 : switch (p0) {
1439 : case 1:
1440 0 : params->pdiv = 0;
1441 0 : break;
1442 : case 2:
1443 0 : params->pdiv = 1;
1444 0 : break;
1445 : case 3:
1446 0 : params->pdiv = 2;
1447 0 : break;
1448 : case 7:
1449 0 : params->pdiv = 4;
1450 0 : break;
1451 : default:
1452 0 : WARN(1, "Incorrect PDiv\n");
1453 0 : }
1454 :
1455 0 : switch (p2) {
1456 : case 5:
1457 0 : params->kdiv = 0;
1458 0 : break;
1459 : case 2:
1460 0 : params->kdiv = 1;
1461 0 : break;
1462 : case 3:
1463 0 : params->kdiv = 2;
1464 0 : break;
1465 : case 1:
1466 0 : params->kdiv = 3;
1467 0 : break;
1468 : default:
1469 0 : WARN(1, "Incorrect KDiv\n");
1470 0 : }
1471 :
1472 0 : params->qdiv_ratio = p1;
1473 0 : params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1474 :
1475 0 : dco_freq = p0 * p1 * p2 * afe_clock;
1476 :
1477 : /*
1478 : * Intermediate values are in Hz.
1479 : * Divide by MHz to match bsepc
1480 : */
1481 0 : params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1482 0 : params->dco_fraction =
1483 0 : div_u64((div_u64(dco_freq, 24) -
1484 0 : params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1485 0 : }
1486 :
1487 : static bool
1488 0 : skl_ddi_calculate_wrpll(int clock /* in Hz */,
1489 : struct skl_wrpll_params *wrpll_params)
1490 : {
1491 0 : uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1492 0 : uint64_t dco_central_freq[3] = {8400000000ULL,
1493 : 9000000000ULL,
1494 : 9600000000ULL};
1495 : static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1496 : 24, 28, 30, 32, 36, 40, 42, 44,
1497 : 48, 52, 54, 56, 60, 64, 66, 68,
1498 : 70, 72, 76, 78, 80, 84, 88, 90,
1499 : 92, 96, 98 };
1500 : static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1501 : static const struct {
1502 : const int *list;
1503 : int n_dividers;
1504 : } dividers[] = {
1505 : { even_dividers, ARRAY_SIZE(even_dividers) },
1506 : { odd_dividers, ARRAY_SIZE(odd_dividers) },
1507 : };
1508 0 : struct skl_wrpll_context ctx;
1509 : unsigned int dco, d, i;
1510 0 : unsigned int p0, p1, p2;
1511 :
1512 0 : skl_wrpll_context_init(&ctx);
1513 :
1514 0 : for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1515 0 : for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1516 0 : for (i = 0; i < dividers[d].n_dividers; i++) {
1517 0 : unsigned int p = dividers[d].list[i];
1518 0 : uint64_t dco_freq = p * afe_clock;
1519 :
1520 0 : skl_wrpll_try_divider(&ctx,
1521 0 : dco_central_freq[dco],
1522 : dco_freq,
1523 : p);
1524 : /*
1525 : * Skip the remaining dividers if we're sure to
1526 : * have found the definitive divider, we can't
1527 : * improve a 0 deviation.
1528 : */
1529 0 : if (ctx.min_deviation == 0)
1530 0 : goto skip_remaining_dividers;
1531 0 : }
1532 : }
1533 :
1534 : skip_remaining_dividers:
1535 : /*
1536 : * If a solution is found with an even divider, prefer
1537 : * this one.
1538 : */
1539 0 : if (d == 0 && ctx.p)
1540 : break;
1541 : }
1542 :
1543 0 : if (!ctx.p) {
1544 : DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1545 0 : return false;
1546 : }
1547 :
1548 : /*
1549 : * gcc incorrectly analyses that these can be used without being
1550 : * initialized. To be fair, it's hard to guess.
1551 : */
1552 0 : p0 = p1 = p2 = 0;
1553 0 : skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1554 0 : skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1555 0 : p0, p1, p2);
1556 :
1557 0 : return true;
1558 0 : }
1559 :
1560 : static bool
1561 0 : skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1562 : struct intel_crtc_state *crtc_state,
1563 : struct intel_encoder *intel_encoder)
1564 : {
1565 : struct intel_shared_dpll *pll;
1566 : uint32_t ctrl1, cfgcr1, cfgcr2;
1567 0 : int clock = crtc_state->port_clock;
1568 :
1569 : /*
1570 : * See comment in intel_dpll_hw_state to understand why we always use 0
1571 : * as the DPLL id in this function.
1572 : */
1573 :
1574 : ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1575 :
1576 0 : if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1577 0 : struct skl_wrpll_params wrpll_params = { 0, };
1578 :
1579 : ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1580 :
1581 0 : if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1582 0 : return false;
1583 :
1584 0 : cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1585 0 : DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1586 0 : wrpll_params.dco_integer;
1587 :
1588 0 : cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1589 0 : DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1590 0 : DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1591 0 : DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1592 0 : wrpll_params.central_freq;
1593 0 : } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1594 0 : intel_encoder->type == INTEL_OUTPUT_DP_MST) {
1595 0 : switch (crtc_state->port_clock / 2) {
1596 : case 81000:
1597 : ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1598 0 : break;
1599 : case 135000:
1600 : ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1601 0 : break;
1602 : case 270000:
1603 : ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1604 0 : break;
1605 : }
1606 :
1607 : cfgcr1 = cfgcr2 = 0;
1608 : } else /* eDP */
1609 0 : return true;
1610 :
1611 0 : memset(&crtc_state->dpll_hw_state, 0,
1612 : sizeof(crtc_state->dpll_hw_state));
1613 :
1614 0 : crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1615 0 : crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1616 0 : crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1617 :
1618 0 : pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1619 0 : if (pll == NULL) {
1620 : DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1621 : pipe_name(intel_crtc->pipe));
1622 0 : return false;
1623 : }
1624 :
1625 : /* shared DPLL id 0 is DPLL 1 */
1626 0 : crtc_state->ddi_pll_sel = pll->id + 1;
1627 :
1628 0 : return true;
1629 0 : }
1630 :
1631 : /* bxt clock parameters */
1632 : struct bxt_clk_div {
1633 : int clock;
1634 : uint32_t p1;
1635 : uint32_t p2;
1636 : uint32_t m2_int;
1637 : uint32_t m2_frac;
1638 : bool m2_frac_en;
1639 : uint32_t n;
1640 : };
1641 :
1642 : /* pre-calculated values for DP linkrates */
1643 : static const struct bxt_clk_div bxt_dp_clk_val[] = {
1644 : {162000, 4, 2, 32, 1677722, 1, 1},
1645 : {270000, 4, 1, 27, 0, 0, 1},
1646 : {540000, 2, 1, 27, 0, 0, 1},
1647 : {216000, 3, 2, 32, 1677722, 1, 1},
1648 : {243000, 4, 1, 24, 1258291, 1, 1},
1649 : {324000, 4, 1, 32, 1677722, 1, 1},
1650 : {432000, 3, 1, 32, 1677722, 1, 1}
1651 : };
1652 :
1653 : static bool
1654 0 : bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1655 : struct intel_crtc_state *crtc_state,
1656 : struct intel_encoder *intel_encoder)
1657 : {
1658 : struct intel_shared_dpll *pll;
1659 0 : struct bxt_clk_div clk_div = {0};
1660 : int vco = 0;
1661 : uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1662 : uint32_t lanestagger;
1663 0 : int clock = crtc_state->port_clock;
1664 :
1665 0 : if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1666 0 : intel_clock_t best_clock;
1667 :
1668 : /* Calculate HDMI div */
1669 : /*
1670 : * FIXME: tie the following calculation into
1671 : * i9xx_crtc_compute_clock
1672 : */
1673 0 : if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1674 : DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1675 : clock, pipe_name(intel_crtc->pipe));
1676 0 : return false;
1677 : }
1678 :
1679 0 : clk_div.p1 = best_clock.p1;
1680 0 : clk_div.p2 = best_clock.p2;
1681 0 : WARN_ON(best_clock.m1 != 2);
1682 0 : clk_div.n = best_clock.n;
1683 0 : clk_div.m2_int = best_clock.m2 >> 22;
1684 0 : clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1685 0 : clk_div.m2_frac_en = clk_div.m2_frac != 0;
1686 :
1687 0 : vco = best_clock.vco;
1688 0 : } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1689 0 : intel_encoder->type == INTEL_OUTPUT_EDP) {
1690 : int i;
1691 :
1692 0 : clk_div = bxt_dp_clk_val[0];
1693 0 : for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1694 0 : if (bxt_dp_clk_val[i].clock == clock) {
1695 0 : clk_div = bxt_dp_clk_val[i];
1696 0 : break;
1697 : }
1698 : }
1699 0 : vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1700 0 : }
1701 :
1702 0 : if (vco >= 6200000 && vco <= 6700000) {
1703 : prop_coef = 4;
1704 : int_coef = 9;
1705 : gain_ctl = 3;
1706 : targ_cnt = 8;
1707 0 : } else if ((vco > 5400000 && vco < 6200000) ||
1708 0 : (vco >= 4800000 && vco < 5400000)) {
1709 : prop_coef = 5;
1710 : int_coef = 11;
1711 : gain_ctl = 3;
1712 : targ_cnt = 9;
1713 0 : } else if (vco == 5400000) {
1714 : prop_coef = 3;
1715 : int_coef = 8;
1716 : gain_ctl = 1;
1717 : targ_cnt = 9;
1718 : } else {
1719 0 : DRM_ERROR("Invalid VCO\n");
1720 0 : return false;
1721 : }
1722 :
1723 0 : memset(&crtc_state->dpll_hw_state, 0,
1724 : sizeof(crtc_state->dpll_hw_state));
1725 :
1726 0 : if (clock > 270000)
1727 0 : lanestagger = 0x18;
1728 0 : else if (clock > 135000)
1729 0 : lanestagger = 0x0d;
1730 0 : else if (clock > 67000)
1731 0 : lanestagger = 0x07;
1732 0 : else if (clock > 33000)
1733 0 : lanestagger = 0x04;
1734 : else
1735 : lanestagger = 0x02;
1736 :
1737 0 : crtc_state->dpll_hw_state.ebb0 =
1738 0 : PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1739 0 : crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1740 0 : crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1741 0 : crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1742 :
1743 0 : if (clk_div.m2_frac_en)
1744 0 : crtc_state->dpll_hw_state.pll3 =
1745 : PORT_PLL_M2_FRAC_ENABLE;
1746 :
1747 0 : crtc_state->dpll_hw_state.pll6 =
1748 0 : prop_coef | PORT_PLL_INT_COEFF(int_coef);
1749 0 : crtc_state->dpll_hw_state.pll6 |=
1750 0 : PORT_PLL_GAIN_CTL(gain_ctl);
1751 :
1752 0 : crtc_state->dpll_hw_state.pll8 = targ_cnt;
1753 :
1754 0 : crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1755 :
1756 0 : crtc_state->dpll_hw_state.pll10 =
1757 : PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1758 : | PORT_PLL_DCO_AMP_OVR_EN_H;
1759 :
1760 0 : crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1761 :
1762 0 : crtc_state->dpll_hw_state.pcsdw12 =
1763 0 : LANESTAGGER_STRAP_OVRD | lanestagger;
1764 :
1765 0 : pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1766 0 : if (pll == NULL) {
1767 : DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1768 : pipe_name(intel_crtc->pipe));
1769 0 : return false;
1770 : }
1771 :
1772 : /* shared DPLL id 0 is DPLL A */
1773 0 : crtc_state->ddi_pll_sel = pll->id;
1774 :
1775 0 : return true;
1776 0 : }
1777 :
1778 : /*
1779 : * Tries to find a *shared* PLL for the CRTC and store it in
1780 : * intel_crtc->ddi_pll_sel.
1781 : *
1782 : * For private DPLLs, compute_config() should do the selection for us. This
1783 : * function should be folded into compute_config() eventually.
1784 : */
1785 0 : bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1786 : struct intel_crtc_state *crtc_state)
1787 : {
1788 0 : struct drm_device *dev = intel_crtc->base.dev;
1789 : struct intel_encoder *intel_encoder =
1790 0 : intel_ddi_get_crtc_new_encoder(crtc_state);
1791 :
1792 0 : if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1793 0 : return skl_ddi_pll_select(intel_crtc, crtc_state,
1794 : intel_encoder);
1795 0 : else if (IS_BROXTON(dev))
1796 0 : return bxt_ddi_pll_select(intel_crtc, crtc_state,
1797 : intel_encoder);
1798 : else
1799 0 : return hsw_ddi_pll_select(intel_crtc, crtc_state,
1800 : intel_encoder);
1801 0 : }
1802 :
1803 0 : void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1804 : {
1805 0 : struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1806 0 : struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1807 0 : struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1808 0 : enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1809 0 : int type = intel_encoder->type;
1810 : uint32_t temp;
1811 :
1812 0 : if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1813 : temp = TRANS_MSA_SYNC_CLK;
1814 0 : switch (intel_crtc->config->pipe_bpp) {
1815 : case 18:
1816 : temp |= TRANS_MSA_6_BPC;
1817 0 : break;
1818 : case 24:
1819 : temp |= TRANS_MSA_8_BPC;
1820 0 : break;
1821 : case 30:
1822 : temp |= TRANS_MSA_10_BPC;
1823 0 : break;
1824 : case 36:
1825 : temp |= TRANS_MSA_12_BPC;
1826 0 : break;
1827 : default:
1828 0 : BUG();
1829 : }
1830 0 : I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1831 0 : }
1832 0 : }
1833 :
1834 0 : void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1835 : {
1836 0 : struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837 0 : struct drm_device *dev = crtc->dev;
1838 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1839 0 : enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1840 : uint32_t temp;
1841 0 : temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1842 0 : if (state == true)
1843 0 : temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1844 : else
1845 0 : temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1846 0 : I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1847 0 : }
1848 :
1849 0 : void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1850 : {
1851 0 : struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1852 0 : struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1853 0 : struct drm_encoder *encoder = &intel_encoder->base;
1854 0 : struct drm_device *dev = crtc->dev;
1855 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1856 0 : enum pipe pipe = intel_crtc->pipe;
1857 0 : enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1858 0 : enum port port = intel_ddi_get_encoder_port(intel_encoder);
1859 0 : int type = intel_encoder->type;
1860 : uint32_t temp;
1861 :
1862 : /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1863 : temp = TRANS_DDI_FUNC_ENABLE;
1864 0 : temp |= TRANS_DDI_SELECT_PORT(port);
1865 :
1866 0 : switch (intel_crtc->config->pipe_bpp) {
1867 : case 18:
1868 0 : temp |= TRANS_DDI_BPC_6;
1869 0 : break;
1870 : case 24:
1871 : temp |= TRANS_DDI_BPC_8;
1872 0 : break;
1873 : case 30:
1874 0 : temp |= TRANS_DDI_BPC_10;
1875 0 : break;
1876 : case 36:
1877 0 : temp |= TRANS_DDI_BPC_12;
1878 0 : break;
1879 : default:
1880 0 : BUG();
1881 : }
1882 :
1883 0 : if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1884 0 : temp |= TRANS_DDI_PVSYNC;
1885 0 : if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1886 0 : temp |= TRANS_DDI_PHSYNC;
1887 :
1888 0 : if (cpu_transcoder == TRANSCODER_EDP) {
1889 0 : switch (pipe) {
1890 : case PIPE_A:
1891 : /* On Haswell, can only use the always-on power well for
1892 : * eDP when not using the panel fitter, and when not
1893 : * using motion blur mitigation (which we don't
1894 : * support). */
1895 0 : if (IS_HASWELL(dev) &&
1896 0 : (intel_crtc->config->pch_pfit.enabled ||
1897 0 : intel_crtc->config->pch_pfit.force_thru))
1898 0 : temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1899 : else
1900 : temp |= TRANS_DDI_EDP_INPUT_A_ON;
1901 : break;
1902 : case PIPE_B:
1903 0 : temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1904 0 : break;
1905 : case PIPE_C:
1906 0 : temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1907 0 : break;
1908 : default:
1909 0 : BUG();
1910 : break;
1911 : }
1912 : }
1913 :
1914 0 : if (type == INTEL_OUTPUT_HDMI) {
1915 0 : if (intel_crtc->config->has_hdmi_sink)
1916 0 : temp |= TRANS_DDI_MODE_SELECT_HDMI;
1917 : else
1918 0 : temp |= TRANS_DDI_MODE_SELECT_DVI;
1919 :
1920 0 : } else if (type == INTEL_OUTPUT_ANALOG) {
1921 0 : temp |= TRANS_DDI_MODE_SELECT_FDI;
1922 0 : temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1923 :
1924 0 : } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1925 0 : type == INTEL_OUTPUT_EDP) {
1926 0 : struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1927 :
1928 0 : if (intel_dp->is_mst) {
1929 0 : temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1930 0 : } else
1931 0 : temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1932 :
1933 0 : temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1934 0 : } else if (type == INTEL_OUTPUT_DP_MST) {
1935 0 : struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1936 :
1937 0 : if (intel_dp->is_mst) {
1938 0 : temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1939 0 : } else
1940 0 : temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1941 :
1942 0 : temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
1943 0 : } else {
1944 0 : WARN(1, "Invalid encoder type %d for pipe %c\n",
1945 : intel_encoder->type, pipe_name(pipe));
1946 : }
1947 :
1948 0 : I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1949 0 : }
1950 :
1951 0 : void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1952 : enum transcoder cpu_transcoder)
1953 : {
1954 0 : uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1955 0 : uint32_t val = I915_READ(reg);
1956 :
1957 0 : val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1958 : val |= TRANS_DDI_PORT_NONE;
1959 0 : I915_WRITE(reg, val);
1960 0 : }
1961 :
1962 0 : bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1963 : {
1964 0 : struct drm_device *dev = intel_connector->base.dev;
1965 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1966 0 : struct intel_encoder *intel_encoder = intel_connector->encoder;
1967 0 : int type = intel_connector->base.connector_type;
1968 0 : enum port port = intel_ddi_get_encoder_port(intel_encoder);
1969 0 : enum pipe pipe = 0;
1970 : enum transcoder cpu_transcoder;
1971 : enum intel_display_power_domain power_domain;
1972 : uint32_t tmp;
1973 :
1974 0 : power_domain = intel_display_port_power_domain(intel_encoder);
1975 0 : if (!intel_display_power_is_enabled(dev_priv, power_domain))
1976 0 : return false;
1977 :
1978 0 : if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1979 0 : return false;
1980 :
1981 0 : if (port == PORT_A)
1982 0 : cpu_transcoder = TRANSCODER_EDP;
1983 : else
1984 0 : cpu_transcoder = (enum transcoder) pipe;
1985 :
1986 0 : tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1987 :
1988 0 : switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1989 : case TRANS_DDI_MODE_SELECT_HDMI:
1990 : case TRANS_DDI_MODE_SELECT_DVI:
1991 0 : return (type == DRM_MODE_CONNECTOR_HDMIA);
1992 :
1993 : case TRANS_DDI_MODE_SELECT_DP_SST:
1994 0 : if (type == DRM_MODE_CONNECTOR_eDP)
1995 0 : return true;
1996 0 : return (type == DRM_MODE_CONNECTOR_DisplayPort);
1997 : case TRANS_DDI_MODE_SELECT_DP_MST:
1998 : /* if the transcoder is in MST state then
1999 : * connector isn't connected */
2000 0 : return false;
2001 :
2002 : case TRANS_DDI_MODE_SELECT_FDI:
2003 0 : return (type == DRM_MODE_CONNECTOR_VGA);
2004 :
2005 : default:
2006 0 : return false;
2007 : }
2008 0 : }
2009 :
2010 0 : bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2011 : enum pipe *pipe)
2012 : {
2013 0 : struct drm_device *dev = encoder->base.dev;
2014 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2015 0 : enum port port = intel_ddi_get_encoder_port(encoder);
2016 : enum intel_display_power_domain power_domain;
2017 : u32 tmp;
2018 : int i;
2019 :
2020 0 : power_domain = intel_display_port_power_domain(encoder);
2021 0 : if (!intel_display_power_is_enabled(dev_priv, power_domain))
2022 0 : return false;
2023 :
2024 0 : tmp = I915_READ(DDI_BUF_CTL(port));
2025 :
2026 0 : if (!(tmp & DDI_BUF_CTL_ENABLE))
2027 0 : return false;
2028 :
2029 0 : if (port == PORT_A) {
2030 0 : tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2031 :
2032 0 : switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2033 : case TRANS_DDI_EDP_INPUT_A_ON:
2034 : case TRANS_DDI_EDP_INPUT_A_ONOFF:
2035 0 : *pipe = PIPE_A;
2036 0 : break;
2037 : case TRANS_DDI_EDP_INPUT_B_ONOFF:
2038 0 : *pipe = PIPE_B;
2039 0 : break;
2040 : case TRANS_DDI_EDP_INPUT_C_ONOFF:
2041 0 : *pipe = PIPE_C;
2042 0 : break;
2043 : }
2044 :
2045 0 : return true;
2046 : } else {
2047 0 : for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2048 0 : tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2049 :
2050 0 : if ((tmp & TRANS_DDI_PORT_MASK)
2051 0 : == TRANS_DDI_SELECT_PORT(port)) {
2052 0 : if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2053 0 : return false;
2054 :
2055 0 : *pipe = i;
2056 0 : return true;
2057 : }
2058 : }
2059 : }
2060 :
2061 : DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
2062 :
2063 0 : return false;
2064 0 : }
2065 :
2066 0 : void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2067 : {
2068 0 : struct drm_crtc *crtc = &intel_crtc->base;
2069 0 : struct drm_device *dev = crtc->dev;
2070 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2071 0 : struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2072 0 : enum port port = intel_ddi_get_encoder_port(intel_encoder);
2073 0 : enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2074 :
2075 0 : if (cpu_transcoder != TRANSCODER_EDP)
2076 0 : I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2077 : TRANS_CLK_SEL_PORT(port));
2078 0 : }
2079 :
2080 0 : void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2081 : {
2082 0 : struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2083 0 : enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
2084 :
2085 0 : if (cpu_transcoder != TRANSCODER_EDP)
2086 0 : I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2087 : TRANS_CLK_SEL_DISABLED);
2088 0 : }
2089 :
2090 0 : static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2091 : enum port port, int type)
2092 : {
2093 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2094 : const struct ddi_buf_trans *ddi_translations;
2095 : uint8_t iboost;
2096 : uint8_t dp_iboost, hdmi_iboost;
2097 0 : int n_entries;
2098 : u32 reg;
2099 :
2100 : /* VBT may override standard boost values */
2101 0 : dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2102 0 : hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2103 :
2104 0 : if (type == INTEL_OUTPUT_DISPLAYPORT) {
2105 0 : if (dp_iboost) {
2106 : iboost = dp_iboost;
2107 0 : } else {
2108 0 : ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2109 0 : iboost = ddi_translations[port].i_boost;
2110 : }
2111 0 : } else if (type == INTEL_OUTPUT_EDP) {
2112 0 : if (dp_iboost) {
2113 : iboost = dp_iboost;
2114 0 : } else {
2115 0 : ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2116 0 : iboost = ddi_translations[port].i_boost;
2117 : }
2118 0 : } else if (type == INTEL_OUTPUT_HDMI) {
2119 0 : if (hdmi_iboost) {
2120 : iboost = hdmi_iboost;
2121 0 : } else {
2122 0 : ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2123 0 : iboost = ddi_translations[port].i_boost;
2124 : }
2125 : } else {
2126 0 : return;
2127 : }
2128 :
2129 : /* Make sure that the requested I_boost is valid */
2130 0 : if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2131 0 : DRM_ERROR("Invalid I_boost value %u\n", iboost);
2132 0 : return;
2133 : }
2134 :
2135 0 : reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2136 0 : reg &= ~BALANCE_LEG_MASK(port);
2137 0 : reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2138 :
2139 0 : if (iboost)
2140 0 : reg |= iboost << BALANCE_LEG_SHIFT(port);
2141 : else
2142 0 : reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2143 :
2144 0 : I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2145 0 : }
2146 :
2147 0 : static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2148 : enum port port, int type)
2149 : {
2150 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2151 : const struct bxt_ddi_buf_trans *ddi_translations;
2152 : u32 n_entries, i;
2153 : uint32_t val;
2154 :
2155 0 : if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
2156 : n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
2157 : ddi_translations = bxt_ddi_translations_edp;
2158 0 : } else if (type == INTEL_OUTPUT_DISPLAYPORT
2159 0 : || type == INTEL_OUTPUT_EDP) {
2160 : n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2161 : ddi_translations = bxt_ddi_translations_dp;
2162 0 : } else if (type == INTEL_OUTPUT_HDMI) {
2163 : n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2164 : ddi_translations = bxt_ddi_translations_hdmi;
2165 : } else {
2166 : DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2167 : type);
2168 0 : return;
2169 : }
2170 :
2171 : /* Check if default value has to be used */
2172 0 : if (level >= n_entries ||
2173 0 : (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2174 0 : for (i = 0; i < n_entries; i++) {
2175 0 : if (ddi_translations[i].default_index) {
2176 : level = i;
2177 0 : break;
2178 : }
2179 : }
2180 : }
2181 :
2182 : /*
2183 : * While we write to the group register to program all lanes at once we
2184 : * can read only lane registers and we pick lanes 0/1 for that.
2185 : */
2186 0 : val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2187 0 : val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2188 0 : I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2189 :
2190 0 : val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2191 0 : val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2192 0 : val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2193 0 : ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2194 0 : I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2195 :
2196 0 : val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2197 0 : val &= ~SCALE_DCOMP_METHOD;
2198 0 : if (ddi_translations[level].enable)
2199 0 : val |= SCALE_DCOMP_METHOD;
2200 :
2201 0 : if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
2202 0 : DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
2203 :
2204 0 : I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2205 :
2206 0 : val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2207 0 : val &= ~DE_EMPHASIS;
2208 0 : val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2209 0 : I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2210 :
2211 0 : val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2212 0 : val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2213 0 : I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2214 0 : }
2215 :
2216 0 : static uint32_t translate_signal_level(int signal_levels)
2217 : {
2218 : uint32_t level;
2219 :
2220 0 : switch (signal_levels) {
2221 : default:
2222 : DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2223 : signal_levels);
2224 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2225 : level = 0;
2226 0 : break;
2227 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2228 : level = 1;
2229 0 : break;
2230 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2231 : level = 2;
2232 0 : break;
2233 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2234 : level = 3;
2235 0 : break;
2236 :
2237 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2238 : level = 4;
2239 0 : break;
2240 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2241 : level = 5;
2242 0 : break;
2243 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2244 : level = 6;
2245 0 : break;
2246 :
2247 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2248 : level = 7;
2249 0 : break;
2250 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2251 : level = 8;
2252 0 : break;
2253 :
2254 : case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2255 : level = 9;
2256 0 : break;
2257 : }
2258 :
2259 0 : return level;
2260 : }
2261 :
2262 0 : uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2263 : {
2264 0 : struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2265 0 : struct drm_device *dev = dport->base.base.dev;
2266 : struct intel_encoder *encoder = &dport->base;
2267 0 : uint8_t train_set = intel_dp->train_set[0];
2268 0 : int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2269 : DP_TRAIN_PRE_EMPHASIS_MASK);
2270 0 : enum port port = dport->port;
2271 : uint32_t level;
2272 :
2273 0 : level = translate_signal_level(signal_levels);
2274 :
2275 0 : if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2276 0 : skl_ddi_set_iboost(dev, level, port, encoder->type);
2277 0 : else if (IS_BROXTON(dev))
2278 0 : bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2279 :
2280 0 : return DDI_BUF_TRANS_SELECT(level);
2281 : }
2282 :
2283 0 : static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
2284 : {
2285 0 : struct drm_encoder *encoder = &intel_encoder->base;
2286 0 : struct drm_device *dev = encoder->dev;
2287 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2288 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
2289 0 : enum port port = intel_ddi_get_encoder_port(intel_encoder);
2290 0 : int type = intel_encoder->type;
2291 : int hdmi_level;
2292 :
2293 0 : if (type == INTEL_OUTPUT_EDP) {
2294 0 : struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2295 0 : intel_edp_panel_on(intel_dp);
2296 0 : }
2297 :
2298 0 : if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2299 0 : uint32_t dpll = crtc->config->ddi_pll_sel;
2300 : uint32_t val;
2301 :
2302 : /*
2303 : * DPLL0 is used for eDP and is the only "private" DPLL (as
2304 : * opposed to shared) on SKL
2305 : */
2306 0 : if (type == INTEL_OUTPUT_EDP) {
2307 0 : WARN_ON(dpll != SKL_DPLL0);
2308 :
2309 0 : val = I915_READ(DPLL_CTRL1);
2310 :
2311 0 : val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2312 0 : DPLL_CTRL1_SSC(dpll) |
2313 0 : DPLL_CTRL1_LINK_RATE_MASK(dpll));
2314 0 : val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
2315 :
2316 0 : I915_WRITE(DPLL_CTRL1, val);
2317 0 : POSTING_READ(DPLL_CTRL1);
2318 0 : }
2319 :
2320 : /* DDI -> PLL mapping */
2321 0 : val = I915_READ(DPLL_CTRL2);
2322 :
2323 0 : val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2324 0 : DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2325 0 : val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2326 0 : DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2327 :
2328 0 : I915_WRITE(DPLL_CTRL2, val);
2329 :
2330 0 : } else if (INTEL_INFO(dev)->gen < 9) {
2331 0 : WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2332 0 : I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
2333 0 : }
2334 :
2335 0 : if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2336 0 : struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2337 :
2338 0 : intel_dp_set_link_params(intel_dp, crtc->config);
2339 :
2340 0 : intel_ddi_init_dp_buf_reg(intel_encoder);
2341 :
2342 0 : intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2343 0 : intel_dp_start_link_train(intel_dp);
2344 0 : if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
2345 0 : intel_dp_stop_link_train(intel_dp);
2346 0 : } else if (type == INTEL_OUTPUT_HDMI) {
2347 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2348 :
2349 0 : if (IS_BROXTON(dev)) {
2350 0 : hdmi_level = dev_priv->vbt.
2351 0 : ddi_port_info[port].hdmi_level_shift;
2352 0 : bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2353 : INTEL_OUTPUT_HDMI);
2354 0 : }
2355 0 : intel_hdmi->set_infoframes(encoder,
2356 0 : crtc->config->has_hdmi_sink,
2357 0 : &crtc->config->base.adjusted_mode);
2358 0 : }
2359 0 : }
2360 :
2361 0 : static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
2362 : {
2363 0 : struct drm_encoder *encoder = &intel_encoder->base;
2364 0 : struct drm_device *dev = encoder->dev;
2365 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2366 0 : enum port port = intel_ddi_get_encoder_port(intel_encoder);
2367 0 : int type = intel_encoder->type;
2368 : uint32_t val;
2369 : bool wait = false;
2370 :
2371 0 : val = I915_READ(DDI_BUF_CTL(port));
2372 0 : if (val & DDI_BUF_CTL_ENABLE) {
2373 0 : val &= ~DDI_BUF_CTL_ENABLE;
2374 0 : I915_WRITE(DDI_BUF_CTL(port), val);
2375 : wait = true;
2376 0 : }
2377 :
2378 0 : val = I915_READ(DP_TP_CTL(port));
2379 0 : val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2380 : val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2381 0 : I915_WRITE(DP_TP_CTL(port), val);
2382 :
2383 0 : if (wait)
2384 0 : intel_wait_ddi_buf_idle(dev_priv, port);
2385 :
2386 0 : if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2387 0 : struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2388 0 : intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2389 0 : intel_edp_panel_vdd_on(intel_dp);
2390 0 : intel_edp_panel_off(intel_dp);
2391 0 : }
2392 :
2393 0 : if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2394 0 : I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2395 : DPLL_CTRL2_DDI_CLK_OFF(port)));
2396 0 : else if (INTEL_INFO(dev)->gen < 9)
2397 0 : I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2398 0 : }
2399 :
2400 0 : static void intel_enable_ddi(struct intel_encoder *intel_encoder)
2401 : {
2402 0 : struct drm_encoder *encoder = &intel_encoder->base;
2403 0 : struct drm_crtc *crtc = encoder->crtc;
2404 0 : struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2405 0 : struct drm_device *dev = encoder->dev;
2406 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2407 0 : enum port port = intel_ddi_get_encoder_port(intel_encoder);
2408 0 : int type = intel_encoder->type;
2409 :
2410 0 : if (type == INTEL_OUTPUT_HDMI) {
2411 : struct intel_digital_port *intel_dig_port =
2412 0 : enc_to_dig_port(encoder);
2413 :
2414 : /* In HDMI/DVI mode, the port width, and swing/emphasis values
2415 : * are ignored so nothing special needs to be done besides
2416 : * enabling the port.
2417 : */
2418 0 : I915_WRITE(DDI_BUF_CTL(port),
2419 : intel_dig_port->saved_port_bits |
2420 : DDI_BUF_CTL_ENABLE);
2421 0 : } else if (type == INTEL_OUTPUT_EDP) {
2422 0 : struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2423 :
2424 0 : if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
2425 0 : intel_dp_stop_link_train(intel_dp);
2426 :
2427 0 : intel_edp_backlight_on(intel_dp);
2428 0 : intel_psr_enable(intel_dp);
2429 0 : intel_edp_drrs_enable(intel_dp);
2430 0 : }
2431 :
2432 0 : if (intel_crtc->config->has_audio) {
2433 0 : intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
2434 0 : intel_audio_codec_enable(intel_encoder);
2435 0 : }
2436 0 : }
2437 :
2438 0 : static void intel_disable_ddi(struct intel_encoder *intel_encoder)
2439 : {
2440 0 : struct drm_encoder *encoder = &intel_encoder->base;
2441 0 : struct drm_crtc *crtc = encoder->crtc;
2442 0 : struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2443 0 : int type = intel_encoder->type;
2444 0 : struct drm_device *dev = encoder->dev;
2445 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2446 :
2447 0 : if (intel_crtc->config->has_audio) {
2448 0 : intel_audio_codec_disable(intel_encoder);
2449 0 : intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2450 0 : }
2451 :
2452 0 : if (type == INTEL_OUTPUT_EDP) {
2453 0 : struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2454 :
2455 0 : intel_edp_drrs_disable(intel_dp);
2456 0 : intel_psr_disable(intel_dp);
2457 0 : intel_edp_backlight_off(intel_dp);
2458 0 : }
2459 0 : }
2460 :
2461 0 : static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
2462 : struct intel_shared_dpll *pll)
2463 : {
2464 0 : I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
2465 0 : POSTING_READ(WRPLL_CTL(pll->id));
2466 0 : udelay(20);
2467 0 : }
2468 :
2469 0 : static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
2470 : struct intel_shared_dpll *pll)
2471 : {
2472 0 : I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
2473 0 : POSTING_READ(SPLL_CTL);
2474 0 : udelay(20);
2475 0 : }
2476 :
2477 0 : static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
2478 : struct intel_shared_dpll *pll)
2479 : {
2480 : uint32_t val;
2481 :
2482 0 : val = I915_READ(WRPLL_CTL(pll->id));
2483 0 : I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2484 0 : POSTING_READ(WRPLL_CTL(pll->id));
2485 0 : }
2486 :
2487 0 : static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
2488 : struct intel_shared_dpll *pll)
2489 : {
2490 : uint32_t val;
2491 :
2492 0 : val = I915_READ(SPLL_CTL);
2493 0 : I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
2494 0 : POSTING_READ(SPLL_CTL);
2495 0 : }
2496 :
2497 0 : static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
2498 : struct intel_shared_dpll *pll,
2499 : struct intel_dpll_hw_state *hw_state)
2500 : {
2501 : uint32_t val;
2502 :
2503 0 : if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2504 0 : return false;
2505 :
2506 0 : val = I915_READ(WRPLL_CTL(pll->id));
2507 0 : hw_state->wrpll = val;
2508 :
2509 0 : return val & WRPLL_PLL_ENABLE;
2510 0 : }
2511 :
2512 0 : static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
2513 : struct intel_shared_dpll *pll,
2514 : struct intel_dpll_hw_state *hw_state)
2515 : {
2516 : uint32_t val;
2517 :
2518 0 : if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2519 0 : return false;
2520 :
2521 0 : val = I915_READ(SPLL_CTL);
2522 0 : hw_state->spll = val;
2523 :
2524 0 : return val & SPLL_PLL_ENABLE;
2525 0 : }
2526 :
2527 :
2528 : static const char * const hsw_ddi_pll_names[] = {
2529 : "WRPLL 1",
2530 : "WRPLL 2",
2531 : "SPLL"
2532 : };
2533 :
2534 0 : static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
2535 : {
2536 : int i;
2537 :
2538 0 : dev_priv->num_shared_dpll = 3;
2539 :
2540 0 : for (i = 0; i < 2; i++) {
2541 : dev_priv->shared_dplls[i].id = i;
2542 : dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2543 0 : dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
2544 0 : dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
2545 0 : dev_priv->shared_dplls[i].get_hw_state =
2546 : hsw_ddi_wrpll_get_hw_state;
2547 : }
2548 :
2549 : /* SPLL is special, but needs to be initialized anyway.. */
2550 : dev_priv->shared_dplls[i].id = i;
2551 : dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
2552 0 : dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
2553 0 : dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
2554 0 : dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
2555 :
2556 0 : }
2557 :
2558 : static const char * const skl_ddi_pll_names[] = {
2559 : "DPLL 1",
2560 : "DPLL 2",
2561 : "DPLL 3",
2562 : };
2563 :
2564 : struct skl_dpll_regs {
2565 : u32 ctl, cfgcr1, cfgcr2;
2566 : };
2567 :
2568 : /* this array is indexed by the *shared* pll id */
2569 : static const struct skl_dpll_regs skl_dpll_regs[3] = {
2570 : {
2571 : /* DPLL 1 */
2572 : .ctl = LCPLL2_CTL,
2573 : .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
2574 : .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
2575 : },
2576 : {
2577 : /* DPLL 2 */
2578 : .ctl = WRPLL_CTL1,
2579 : .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
2580 : .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
2581 : },
2582 : {
2583 : /* DPLL 3 */
2584 : .ctl = WRPLL_CTL2,
2585 : .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
2586 : .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
2587 : },
2588 : };
2589 :
2590 0 : static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2591 : struct intel_shared_dpll *pll)
2592 : {
2593 : uint32_t val;
2594 : unsigned int dpll;
2595 : const struct skl_dpll_regs *regs = skl_dpll_regs;
2596 :
2597 : /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2598 0 : dpll = pll->id + 1;
2599 :
2600 0 : val = I915_READ(DPLL_CTRL1);
2601 :
2602 0 : val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
2603 0 : DPLL_CTRL1_LINK_RATE_MASK(dpll));
2604 0 : val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2605 :
2606 0 : I915_WRITE(DPLL_CTRL1, val);
2607 0 : POSTING_READ(DPLL_CTRL1);
2608 :
2609 0 : I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2610 0 : I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2611 0 : POSTING_READ(regs[pll->id].cfgcr1);
2612 0 : POSTING_READ(regs[pll->id].cfgcr2);
2613 :
2614 : /* the enable bit is always bit 31 */
2615 0 : I915_WRITE(regs[pll->id].ctl,
2616 : I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2617 :
2618 0 : if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2619 0 : DRM_ERROR("DPLL %d not locked\n", dpll);
2620 0 : }
2621 :
2622 0 : static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2623 : struct intel_shared_dpll *pll)
2624 : {
2625 : const struct skl_dpll_regs *regs = skl_dpll_regs;
2626 :
2627 : /* the enable bit is always bit 31 */
2628 0 : I915_WRITE(regs[pll->id].ctl,
2629 : I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2630 0 : POSTING_READ(regs[pll->id].ctl);
2631 0 : }
2632 :
2633 0 : static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2634 : struct intel_shared_dpll *pll,
2635 : struct intel_dpll_hw_state *hw_state)
2636 : {
2637 : uint32_t val;
2638 : unsigned int dpll;
2639 : const struct skl_dpll_regs *regs = skl_dpll_regs;
2640 :
2641 0 : if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2642 0 : return false;
2643 :
2644 : /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2645 0 : dpll = pll->id + 1;
2646 :
2647 0 : val = I915_READ(regs[pll->id].ctl);
2648 0 : if (!(val & LCPLL_PLL_ENABLE))
2649 0 : return false;
2650 :
2651 0 : val = I915_READ(DPLL_CTRL1);
2652 0 : hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2653 :
2654 : /* avoid reading back stale values if HDMI mode is not enabled */
2655 0 : if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2656 0 : hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2657 0 : hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2658 0 : }
2659 :
2660 0 : return true;
2661 0 : }
2662 :
2663 0 : static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2664 : {
2665 : int i;
2666 :
2667 0 : dev_priv->num_shared_dpll = 3;
2668 :
2669 0 : for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2670 0 : dev_priv->shared_dplls[i].id = i;
2671 0 : dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2672 0 : dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2673 0 : dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2674 0 : dev_priv->shared_dplls[i].get_hw_state =
2675 : skl_ddi_pll_get_hw_state;
2676 : }
2677 0 : }
2678 :
2679 0 : static void broxton_phy_init(struct drm_i915_private *dev_priv,
2680 : enum dpio_phy phy)
2681 : {
2682 : enum port port;
2683 : uint32_t val;
2684 :
2685 0 : val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2686 0 : val |= GT_DISPLAY_POWER_ON(phy);
2687 0 : I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2688 :
2689 : /* Considering 10ms timeout until BSpec is updated */
2690 0 : if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2691 0 : DRM_ERROR("timeout during PHY%d power on\n", phy);
2692 :
2693 0 : for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2694 0 : port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2695 : int lane;
2696 :
2697 0 : for (lane = 0; lane < 4; lane++) {
2698 0 : val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2699 : /*
2700 : * Note that on CHV this flag is called UPAR, but has
2701 : * the same function.
2702 : */
2703 0 : val &= ~LATENCY_OPTIM;
2704 0 : if (lane != 1)
2705 0 : val |= LATENCY_OPTIM;
2706 :
2707 0 : I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2708 : }
2709 : }
2710 :
2711 : /* Program PLL Rcomp code offset */
2712 0 : val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2713 0 : val &= ~IREF0RC_OFFSET_MASK;
2714 0 : val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2715 0 : I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2716 :
2717 0 : val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2718 0 : val &= ~IREF1RC_OFFSET_MASK;
2719 0 : val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2720 0 : I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2721 :
2722 : /* Program power gating */
2723 0 : val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2724 0 : val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2725 : SUS_CLK_CONFIG;
2726 0 : I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2727 :
2728 0 : if (phy == DPIO_PHY0) {
2729 0 : val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2730 0 : val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2731 0 : I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2732 0 : }
2733 :
2734 0 : val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2735 0 : val &= ~OCL2_LDOFUSE_PWR_DIS;
2736 : /*
2737 : * On PHY1 disable power on the second channel, since no port is
2738 : * connected there. On PHY0 both channels have a port, so leave it
2739 : * enabled.
2740 : * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2741 : * power down the second channel on PHY0 as well.
2742 : */
2743 0 : if (phy == DPIO_PHY1)
2744 0 : val |= OCL2_LDOFUSE_PWR_DIS;
2745 0 : I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2746 :
2747 0 : if (phy == DPIO_PHY0) {
2748 : uint32_t grc_code;
2749 : /*
2750 : * PHY0 isn't connected to an RCOMP resistor so copy over
2751 : * the corresponding calibrated value from PHY1, and disable
2752 : * the automatic calibration on PHY0.
2753 : */
2754 0 : if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2755 : 10))
2756 0 : DRM_ERROR("timeout waiting for PHY1 GRC\n");
2757 :
2758 0 : val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2759 0 : val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2760 0 : grc_code = val << GRC_CODE_FAST_SHIFT |
2761 0 : val << GRC_CODE_SLOW_SHIFT |
2762 : val;
2763 0 : I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2764 :
2765 0 : val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2766 0 : val |= GRC_DIS | GRC_RDY_OVRD;
2767 0 : I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2768 0 : }
2769 :
2770 0 : val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2771 0 : val |= COMMON_RESET_DIS;
2772 0 : I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2773 0 : }
2774 :
2775 0 : void broxton_ddi_phy_init(struct drm_device *dev)
2776 : {
2777 : /* Enable PHY1 first since it provides Rcomp for PHY0 */
2778 0 : broxton_phy_init(dev->dev_private, DPIO_PHY1);
2779 0 : broxton_phy_init(dev->dev_private, DPIO_PHY0);
2780 0 : }
2781 :
2782 0 : static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2783 : enum dpio_phy phy)
2784 : {
2785 : uint32_t val;
2786 :
2787 0 : val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2788 0 : val &= ~COMMON_RESET_DIS;
2789 0 : I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2790 0 : }
2791 :
2792 0 : void broxton_ddi_phy_uninit(struct drm_device *dev)
2793 : {
2794 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2795 :
2796 0 : broxton_phy_uninit(dev_priv, DPIO_PHY1);
2797 0 : broxton_phy_uninit(dev_priv, DPIO_PHY0);
2798 :
2799 : /* FIXME: do this in broxton_phy_uninit per phy */
2800 0 : I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2801 0 : }
2802 :
2803 : static const char * const bxt_ddi_pll_names[] = {
2804 : "PORT PLL A",
2805 : "PORT PLL B",
2806 : "PORT PLL C",
2807 : };
2808 :
2809 0 : static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2810 : struct intel_shared_dpll *pll)
2811 : {
2812 : uint32_t temp;
2813 0 : enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2814 :
2815 0 : temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2816 0 : temp &= ~PORT_PLL_REF_SEL;
2817 : /* Non-SSC reference */
2818 0 : I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2819 :
2820 : /* Disable 10 bit clock */
2821 0 : temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2822 0 : temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2823 0 : I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2824 :
2825 : /* Write P1 & P2 */
2826 0 : temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2827 0 : temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2828 0 : temp |= pll->config.hw_state.ebb0;
2829 0 : I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2830 :
2831 : /* Write M2 integer */
2832 0 : temp = I915_READ(BXT_PORT_PLL(port, 0));
2833 0 : temp &= ~PORT_PLL_M2_MASK;
2834 0 : temp |= pll->config.hw_state.pll0;
2835 0 : I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2836 :
2837 : /* Write N */
2838 0 : temp = I915_READ(BXT_PORT_PLL(port, 1));
2839 0 : temp &= ~PORT_PLL_N_MASK;
2840 0 : temp |= pll->config.hw_state.pll1;
2841 0 : I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2842 :
2843 : /* Write M2 fraction */
2844 0 : temp = I915_READ(BXT_PORT_PLL(port, 2));
2845 0 : temp &= ~PORT_PLL_M2_FRAC_MASK;
2846 0 : temp |= pll->config.hw_state.pll2;
2847 0 : I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2848 :
2849 : /* Write M2 fraction enable */
2850 0 : temp = I915_READ(BXT_PORT_PLL(port, 3));
2851 0 : temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2852 0 : temp |= pll->config.hw_state.pll3;
2853 0 : I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2854 :
2855 : /* Write coeff */
2856 0 : temp = I915_READ(BXT_PORT_PLL(port, 6));
2857 0 : temp &= ~PORT_PLL_PROP_COEFF_MASK;
2858 0 : temp &= ~PORT_PLL_INT_COEFF_MASK;
2859 0 : temp &= ~PORT_PLL_GAIN_CTL_MASK;
2860 0 : temp |= pll->config.hw_state.pll6;
2861 0 : I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2862 :
2863 : /* Write calibration val */
2864 0 : temp = I915_READ(BXT_PORT_PLL(port, 8));
2865 0 : temp &= ~PORT_PLL_TARGET_CNT_MASK;
2866 0 : temp |= pll->config.hw_state.pll8;
2867 0 : I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2868 :
2869 0 : temp = I915_READ(BXT_PORT_PLL(port, 9));
2870 0 : temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2871 0 : temp |= pll->config.hw_state.pll9;
2872 0 : I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2873 :
2874 0 : temp = I915_READ(BXT_PORT_PLL(port, 10));
2875 0 : temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2876 0 : temp &= ~PORT_PLL_DCO_AMP_MASK;
2877 0 : temp |= pll->config.hw_state.pll10;
2878 0 : I915_WRITE(BXT_PORT_PLL(port, 10), temp);
2879 :
2880 : /* Recalibrate with new settings */
2881 0 : temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2882 0 : temp |= PORT_PLL_RECALIBRATE;
2883 0 : I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2884 0 : temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2885 0 : temp |= pll->config.hw_state.ebb4;
2886 0 : I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2887 :
2888 : /* Enable PLL */
2889 0 : temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2890 0 : temp |= PORT_PLL_ENABLE;
2891 0 : I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2892 0 : POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2893 :
2894 0 : if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2895 : PORT_PLL_LOCK), 200))
2896 0 : DRM_ERROR("PLL %d not locked\n", port);
2897 :
2898 : /*
2899 : * While we write to the group register to program all lanes at once we
2900 : * can read only lane registers and we pick lanes 0/1 for that.
2901 : */
2902 0 : temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2903 0 : temp &= ~LANE_STAGGER_MASK;
2904 0 : temp &= ~LANESTAGGER_STRAP_OVRD;
2905 0 : temp |= pll->config.hw_state.pcsdw12;
2906 0 : I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2907 0 : }
2908 :
2909 0 : static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2910 : struct intel_shared_dpll *pll)
2911 : {
2912 0 : enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2913 : uint32_t temp;
2914 :
2915 0 : temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2916 0 : temp &= ~PORT_PLL_ENABLE;
2917 0 : I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2918 0 : POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2919 0 : }
2920 :
2921 0 : static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2922 : struct intel_shared_dpll *pll,
2923 : struct intel_dpll_hw_state *hw_state)
2924 : {
2925 0 : enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2926 : uint32_t val;
2927 :
2928 0 : if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2929 0 : return false;
2930 :
2931 0 : val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2932 0 : if (!(val & PORT_PLL_ENABLE))
2933 0 : return false;
2934 :
2935 0 : hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2936 0 : hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2937 :
2938 0 : hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
2939 0 : hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2940 :
2941 0 : hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2942 0 : hw_state->pll0 &= PORT_PLL_M2_MASK;
2943 :
2944 0 : hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2945 0 : hw_state->pll1 &= PORT_PLL_N_MASK;
2946 :
2947 0 : hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2948 0 : hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2949 :
2950 0 : hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2951 0 : hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2952 :
2953 0 : hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2954 0 : hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2955 : PORT_PLL_INT_COEFF_MASK |
2956 : PORT_PLL_GAIN_CTL_MASK;
2957 :
2958 0 : hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
2959 0 : hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2960 :
2961 0 : hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
2962 0 : hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2963 :
2964 0 : hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
2965 0 : hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2966 : PORT_PLL_DCO_AMP_MASK;
2967 :
2968 : /*
2969 : * While we write to the group register to program all lanes at once we
2970 : * can read only lane registers. We configure all lanes the same way, so
2971 : * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2972 : */
2973 0 : hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2974 0 : if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
2975 : DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2976 : hw_state->pcsdw12,
2977 : I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2978 0 : hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2979 :
2980 0 : return true;
2981 0 : }
2982 :
2983 0 : static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2984 : {
2985 : int i;
2986 :
2987 0 : dev_priv->num_shared_dpll = 3;
2988 :
2989 0 : for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2990 0 : dev_priv->shared_dplls[i].id = i;
2991 0 : dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2992 0 : dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2993 0 : dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2994 0 : dev_priv->shared_dplls[i].get_hw_state =
2995 : bxt_ddi_pll_get_hw_state;
2996 : }
2997 0 : }
2998 :
2999 0 : void intel_ddi_pll_init(struct drm_device *dev)
3000 : {
3001 0 : struct drm_i915_private *dev_priv = dev->dev_private;
3002 0 : uint32_t val = I915_READ(LCPLL_CTL);
3003 :
3004 0 : if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
3005 0 : skl_shared_dplls_init(dev_priv);
3006 0 : else if (IS_BROXTON(dev))
3007 0 : bxt_shared_dplls_init(dev_priv);
3008 : else
3009 0 : hsw_shared_dplls_init(dev_priv);
3010 :
3011 0 : if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
3012 : int cdclk_freq;
3013 :
3014 0 : cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
3015 0 : dev_priv->skl_boot_cdclk = cdclk_freq;
3016 0 : if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
3017 0 : DRM_ERROR("LCPLL1 is disabled\n");
3018 : else
3019 0 : intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
3020 0 : } else if (IS_BROXTON(dev)) {
3021 0 : broxton_init_cdclk(dev);
3022 0 : broxton_ddi_phy_init(dev);
3023 0 : } else {
3024 : /*
3025 : * The LCPLL register should be turned on by the BIOS. For now
3026 : * let's just check its state and print errors in case
3027 : * something is wrong. Don't even try to turn it on.
3028 : */
3029 :
3030 0 : if (val & LCPLL_CD_SOURCE_FCLK)
3031 0 : DRM_ERROR("CDCLK source is not LCPLL\n");
3032 :
3033 0 : if (val & LCPLL_PLL_DISABLE)
3034 0 : DRM_ERROR("LCPLL is disabled\n");
3035 : }
3036 0 : }
3037 :
3038 0 : void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
3039 : {
3040 0 : struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3041 0 : struct intel_dp *intel_dp = &intel_dig_port->dp;
3042 0 : struct drm_i915_private *dev_priv = encoder->dev->dev_private;
3043 0 : enum port port = intel_dig_port->port;
3044 : uint32_t val;
3045 : bool wait = false;
3046 :
3047 0 : if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
3048 0 : val = I915_READ(DDI_BUF_CTL(port));
3049 0 : if (val & DDI_BUF_CTL_ENABLE) {
3050 0 : val &= ~DDI_BUF_CTL_ENABLE;
3051 0 : I915_WRITE(DDI_BUF_CTL(port), val);
3052 : wait = true;
3053 0 : }
3054 :
3055 0 : val = I915_READ(DP_TP_CTL(port));
3056 0 : val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3057 : val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3058 0 : I915_WRITE(DP_TP_CTL(port), val);
3059 0 : POSTING_READ(DP_TP_CTL(port));
3060 :
3061 0 : if (wait)
3062 0 : intel_wait_ddi_buf_idle(dev_priv, port);
3063 : }
3064 :
3065 : val = DP_TP_CTL_ENABLE |
3066 : DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
3067 0 : if (intel_dp->is_mst)
3068 0 : val |= DP_TP_CTL_MODE_MST;
3069 : else {
3070 : val |= DP_TP_CTL_MODE_SST;
3071 0 : if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3072 0 : val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3073 : }
3074 0 : I915_WRITE(DP_TP_CTL(port), val);
3075 0 : POSTING_READ(DP_TP_CTL(port));
3076 :
3077 0 : intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3078 0 : I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
3079 0 : POSTING_READ(DDI_BUF_CTL(port));
3080 :
3081 0 : udelay(600);
3082 0 : }
3083 :
3084 0 : void intel_ddi_fdi_disable(struct drm_crtc *crtc)
3085 : {
3086 0 : struct drm_i915_private *dev_priv = crtc->dev->dev_private;
3087 0 : struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
3088 : uint32_t val;
3089 :
3090 0 : intel_ddi_post_disable(intel_encoder);
3091 :
3092 0 : val = I915_READ(FDI_RX_CTL(PIPE_A));
3093 0 : val &= ~FDI_RX_ENABLE;
3094 0 : I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3095 :
3096 0 : val = I915_READ(FDI_RX_MISC(PIPE_A));
3097 0 : val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3098 0 : val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3099 0 : I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3100 :
3101 0 : val = I915_READ(FDI_RX_CTL(PIPE_A));
3102 0 : val &= ~FDI_PCDCLK;
3103 0 : I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3104 :
3105 0 : val = I915_READ(FDI_RX_CTL(PIPE_A));
3106 0 : val &= ~FDI_RX_PLL_ENABLE;
3107 0 : I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3108 0 : }
3109 :
3110 0 : void intel_ddi_get_config(struct intel_encoder *encoder,
3111 : struct intel_crtc_state *pipe_config)
3112 : {
3113 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
3114 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
3115 0 : enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3116 : struct intel_hdmi *intel_hdmi;
3117 : u32 temp, flags = 0;
3118 :
3119 0 : temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3120 0 : if (temp & TRANS_DDI_PHSYNC)
3121 0 : flags |= DRM_MODE_FLAG_PHSYNC;
3122 : else
3123 : flags |= DRM_MODE_FLAG_NHSYNC;
3124 0 : if (temp & TRANS_DDI_PVSYNC)
3125 0 : flags |= DRM_MODE_FLAG_PVSYNC;
3126 : else
3127 0 : flags |= DRM_MODE_FLAG_NVSYNC;
3128 :
3129 0 : pipe_config->base.adjusted_mode.flags |= flags;
3130 :
3131 0 : switch (temp & TRANS_DDI_BPC_MASK) {
3132 : case TRANS_DDI_BPC_6:
3133 0 : pipe_config->pipe_bpp = 18;
3134 0 : break;
3135 : case TRANS_DDI_BPC_8:
3136 0 : pipe_config->pipe_bpp = 24;
3137 0 : break;
3138 : case TRANS_DDI_BPC_10:
3139 0 : pipe_config->pipe_bpp = 30;
3140 0 : break;
3141 : case TRANS_DDI_BPC_12:
3142 0 : pipe_config->pipe_bpp = 36;
3143 0 : break;
3144 : default:
3145 : break;
3146 : }
3147 :
3148 0 : switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3149 : case TRANS_DDI_MODE_SELECT_HDMI:
3150 0 : pipe_config->has_hdmi_sink = true;
3151 0 : intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3152 :
3153 0 : if (intel_hdmi->infoframe_enabled(&encoder->base))
3154 0 : pipe_config->has_infoframe = true;
3155 : break;
3156 : case TRANS_DDI_MODE_SELECT_DVI:
3157 : case TRANS_DDI_MODE_SELECT_FDI:
3158 : break;
3159 : case TRANS_DDI_MODE_SELECT_DP_SST:
3160 : case TRANS_DDI_MODE_SELECT_DP_MST:
3161 0 : pipe_config->has_dp_encoder = true;
3162 0 : pipe_config->lane_count =
3163 0 : ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3164 0 : intel_dp_get_m_n(intel_crtc, pipe_config);
3165 0 : break;
3166 : default:
3167 : break;
3168 : }
3169 :
3170 0 : if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3171 0 : temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3172 0 : if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3173 0 : pipe_config->has_audio = true;
3174 : }
3175 :
3176 0 : if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3177 0 : pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3178 : /*
3179 : * This is a big fat ugly hack.
3180 : *
3181 : * Some machines in UEFI boot mode provide us a VBT that has 18
3182 : * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3183 : * unknown we fail to light up. Yet the same BIOS boots up with
3184 : * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3185 : * max, not what it tells us to use.
3186 : *
3187 : * Note: This will still be broken if the eDP panel is not lit
3188 : * up by the BIOS, and thus we can't get the mode at module
3189 : * load.
3190 : */
3191 : DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3192 : pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3193 0 : dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3194 0 : }
3195 :
3196 0 : intel_ddi_clock_get(encoder, pipe_config);
3197 0 : }
3198 :
3199 0 : static bool intel_ddi_compute_config(struct intel_encoder *encoder,
3200 : struct intel_crtc_state *pipe_config)
3201 : {
3202 0 : int type = encoder->type;
3203 0 : int port = intel_ddi_get_encoder_port(encoder);
3204 :
3205 0 : WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
3206 :
3207 0 : if (port == PORT_A)
3208 0 : pipe_config->cpu_transcoder = TRANSCODER_EDP;
3209 :
3210 0 : if (type == INTEL_OUTPUT_HDMI)
3211 0 : return intel_hdmi_compute_config(encoder, pipe_config);
3212 : else
3213 0 : return intel_dp_compute_config(encoder, pipe_config);
3214 0 : }
3215 :
3216 : static const struct drm_encoder_funcs intel_ddi_funcs = {
3217 : .reset = intel_dp_encoder_reset,
3218 : .destroy = intel_dp_encoder_destroy,
3219 : };
3220 :
3221 : static struct intel_connector *
3222 0 : intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3223 : {
3224 : struct intel_connector *connector;
3225 0 : enum port port = intel_dig_port->port;
3226 :
3227 0 : connector = intel_connector_alloc();
3228 0 : if (!connector)
3229 0 : return NULL;
3230 :
3231 0 : intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3232 0 : if (!intel_dp_init_connector(intel_dig_port, connector)) {
3233 0 : kfree(connector);
3234 0 : return NULL;
3235 : }
3236 :
3237 0 : return connector;
3238 0 : }
3239 :
3240 : static struct intel_connector *
3241 0 : intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3242 : {
3243 : struct intel_connector *connector;
3244 0 : enum port port = intel_dig_port->port;
3245 :
3246 0 : connector = intel_connector_alloc();
3247 0 : if (!connector)
3248 0 : return NULL;
3249 :
3250 0 : intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3251 0 : intel_hdmi_init_connector(intel_dig_port, connector);
3252 :
3253 0 : return connector;
3254 0 : }
3255 :
3256 0 : void intel_ddi_init(struct drm_device *dev, enum port port)
3257 : {
3258 0 : struct drm_i915_private *dev_priv = dev->dev_private;
3259 : struct intel_digital_port *intel_dig_port;
3260 : struct intel_encoder *intel_encoder;
3261 : struct drm_encoder *encoder;
3262 : bool init_hdmi, init_dp;
3263 :
3264 0 : init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3265 0 : dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3266 0 : init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3267 0 : if (!init_dp && !init_hdmi) {
3268 : DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
3269 : port_name(port));
3270 0 : return;
3271 : }
3272 :
3273 0 : intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3274 0 : if (!intel_dig_port)
3275 0 : return;
3276 :
3277 0 : intel_encoder = &intel_dig_port->base;
3278 0 : encoder = &intel_encoder->base;
3279 :
3280 0 : drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3281 : DRM_MODE_ENCODER_TMDS);
3282 :
3283 0 : intel_encoder->compute_config = intel_ddi_compute_config;
3284 0 : intel_encoder->enable = intel_enable_ddi;
3285 0 : intel_encoder->pre_enable = intel_ddi_pre_enable;
3286 0 : intel_encoder->disable = intel_disable_ddi;
3287 0 : intel_encoder->post_disable = intel_ddi_post_disable;
3288 0 : intel_encoder->get_hw_state = intel_ddi_get_hw_state;
3289 0 : intel_encoder->get_config = intel_ddi_get_config;
3290 0 : intel_encoder->suspend = intel_dp_encoder_suspend;
3291 :
3292 0 : intel_dig_port->port = port;
3293 0 : intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3294 : (DDI_BUF_PORT_REVERSAL |
3295 : DDI_A_4_LANES);
3296 :
3297 0 : intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
3298 0 : intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3299 0 : intel_encoder->cloneable = 0;
3300 :
3301 0 : if (init_dp) {
3302 0 : if (!intel_ddi_init_dp_connector(intel_dig_port))
3303 : goto err;
3304 :
3305 0 : intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
3306 : /*
3307 : * On BXT A0/A1, sw needs to activate DDIA HPD logic and
3308 : * interrupts to check the external panel connection.
3309 : */
3310 0 : if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
3311 0 : dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
3312 : else
3313 0 : dev_priv->hotplug.irq_port[port] = intel_dig_port;
3314 : }
3315 :
3316 : /* In theory we don't need the encoder->type check, but leave it just in
3317 : * case we have some really bad VBTs... */
3318 0 : if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3319 0 : if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3320 : goto err;
3321 : }
3322 :
3323 0 : return;
3324 :
3325 : err:
3326 0 : drm_encoder_cleanup(encoder);
3327 0 : kfree(intel_dig_port);
3328 0 : }
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