Line data Source code
1 : /*
2 : * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 : * Copyright (c) 2007-2008 Intel Corporation
4 : * Jesse Barnes <jesse.barnes@intel.com>
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice (including the next
14 : * paragraph) shall be included in all copies or substantial portions of the
15 : * Software.
16 : *
17 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 : * IN THE SOFTWARE.
24 : */
25 : #ifndef __INTEL_DRV_H__
26 : #define __INTEL_DRV_H__
27 :
28 : #ifdef __linux__
29 : #include <linux/async.h>
30 : #include <linux/i2c.h>
31 : #include <linux/hdmi.h>
32 : #else
33 : #include <dev/pci/drm/linux_hdmi.h>
34 : #endif
35 : #include <dev/pci/drm/i915_drm.h>
36 : #include "i915_drv.h"
37 : #include <dev/pci/drm/drm_crtc.h>
38 : #include <dev/pci/drm/drm_crtc_helper.h>
39 : #include <dev/pci/drm/drm_fb_helper.h>
40 : #include <dev/pci/drm/drm_dp_mst_helper.h>
41 : #include <dev/pci/drm/drm_rect.h>
42 : #include <dev/pci/drm/drm_atomic.h>
43 :
44 : /**
45 : * _wait_for - magic (register) wait macro
46 : *
47 : * Does the right thing for modeset paths when run under kdgb or similar atomic
48 : * contexts. Note that it's important that we check the condition again after
49 : * having timed out, since the timeout could be due to preemption or similar and
50 : * we've never had a chance to check the condition before the timeout.
51 : */
52 : #define _wait_for(COND, MS, W) ({ \
53 : unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
54 : int ret__ = 0; \
55 : while (!(COND)) { \
56 : if (time_after(jiffies, timeout__)) { \
57 : if (!(COND)) \
58 : ret__ = -ETIMEDOUT; \
59 : break; \
60 : } \
61 : if ((W) && drm_can_sleep()) { \
62 : usleep_range((W)*1000, (W)*2000); \
63 : } else { \
64 : cpu_relax(); \
65 : } \
66 : } \
67 : ret__; \
68 : })
69 :
70 : #define wait_for(COND, MS) _wait_for(COND, MS, 1)
71 : #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
72 : #define wait_for_atomic_us(COND, US) _wait_for((COND), \
73 : DIV_ROUND_UP((US), 1000), 0)
74 :
75 : #define KHz(x) (1000 * (x))
76 : #define MHz(x) KHz(1000 * (x))
77 :
78 : /*
79 : * Display related stuff
80 : */
81 :
82 : /* store information about an Ixxx DVO */
83 : /* The i830->i865 use multiple DVOs with multiple i2cs */
84 : /* the i915, i945 have a single sDVO i2c bus - which is different */
85 : #define MAX_OUTPUTS 6
86 : /* maximum connectors per crtcs in the mode set */
87 :
88 : /* Maximum cursor sizes */
89 : #define GEN2_CURSOR_WIDTH 64
90 : #define GEN2_CURSOR_HEIGHT 64
91 : #define MAX_CURSOR_WIDTH 256
92 : #define MAX_CURSOR_HEIGHT 256
93 :
94 : #define INTEL_I2C_BUS_DVO 1
95 : #define INTEL_I2C_BUS_SDVO 2
96 :
97 : /* these are outputs from the chip - integrated only
98 : external chips are via DVO or SDVO output */
99 : enum intel_output_type {
100 : INTEL_OUTPUT_UNUSED = 0,
101 : INTEL_OUTPUT_ANALOG = 1,
102 : INTEL_OUTPUT_DVO = 2,
103 : INTEL_OUTPUT_SDVO = 3,
104 : INTEL_OUTPUT_LVDS = 4,
105 : INTEL_OUTPUT_TVOUT = 5,
106 : INTEL_OUTPUT_HDMI = 6,
107 : INTEL_OUTPUT_DISPLAYPORT = 7,
108 : INTEL_OUTPUT_EDP = 8,
109 : INTEL_OUTPUT_DSI = 9,
110 : INTEL_OUTPUT_UNKNOWN = 10,
111 : INTEL_OUTPUT_DP_MST = 11,
112 : };
113 :
114 : #define INTEL_DVO_CHIP_NONE 0
115 : #define INTEL_DVO_CHIP_LVDS 1
116 : #define INTEL_DVO_CHIP_TMDS 2
117 : #define INTEL_DVO_CHIP_TVOUT 4
118 :
119 : #define INTEL_DSI_VIDEO_MODE 0
120 : #define INTEL_DSI_COMMAND_MODE 1
121 :
122 : struct intel_framebuffer {
123 : struct drm_framebuffer base;
124 : struct drm_i915_gem_object *obj;
125 : };
126 :
127 : struct intel_fbdev {
128 : struct drm_fb_helper helper;
129 : struct intel_framebuffer *fb;
130 : struct list_head fbdev_list;
131 : struct drm_display_mode *our_mode;
132 : int preferred_bpp;
133 : };
134 :
135 : struct intel_encoder {
136 : struct drm_encoder base;
137 :
138 : enum intel_output_type type;
139 : unsigned int cloneable;
140 : void (*hot_plug)(struct intel_encoder *);
141 : bool (*compute_config)(struct intel_encoder *,
142 : struct intel_crtc_state *);
143 : void (*pre_pll_enable)(struct intel_encoder *);
144 : void (*pre_enable)(struct intel_encoder *);
145 : void (*enable)(struct intel_encoder *);
146 : void (*mode_set)(struct intel_encoder *intel_encoder);
147 : void (*disable)(struct intel_encoder *);
148 : void (*post_disable)(struct intel_encoder *);
149 : void (*post_pll_disable)(struct intel_encoder *);
150 : /* Read out the current hw state of this connector, returning true if
151 : * the encoder is active. If the encoder is enabled it also set the pipe
152 : * it is connected to in the pipe parameter. */
153 : bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
154 : /* Reconstructs the equivalent mode flags for the current hardware
155 : * state. This must be called _after_ display->get_pipe_config has
156 : * pre-filled the pipe config. Note that intel_encoder->base.crtc must
157 : * be set correctly before calling this function. */
158 : void (*get_config)(struct intel_encoder *,
159 : struct intel_crtc_state *pipe_config);
160 : /*
161 : * Called during system suspend after all pending requests for the
162 : * encoder are flushed (for example for DP AUX transactions) and
163 : * device interrupts are disabled.
164 : */
165 : void (*suspend)(struct intel_encoder *);
166 : int crtc_mask;
167 : enum hpd_pin hpd_pin;
168 : };
169 :
170 : struct intel_panel {
171 : struct drm_display_mode *fixed_mode;
172 : struct drm_display_mode *downclock_mode;
173 : int fitting_mode;
174 :
175 : /* backlight */
176 : struct {
177 : bool present;
178 : u32 level;
179 : u32 min;
180 : u32 max;
181 : bool enabled;
182 : bool combination_mode; /* gen 2/4 only */
183 : bool active_low_pwm;
184 : bool alternate_pwm_increment; /* lpt+ */
185 :
186 : /* PWM chip */
187 : bool util_pin_active_low; /* bxt+ */
188 : u8 controller; /* bxt+ only */
189 : struct pwm_device *pwm;
190 :
191 : struct backlight_device *device;
192 :
193 : /* Connector and platform specific backlight functions */
194 : int (*setup)(struct intel_connector *connector, enum pipe pipe);
195 : uint32_t (*get)(struct intel_connector *connector);
196 : void (*set)(struct intel_connector *connector, uint32_t level);
197 : void (*disable)(struct intel_connector *connector);
198 : void (*enable)(struct intel_connector *connector);
199 : uint32_t (*hz_to_pwm)(struct intel_connector *connector,
200 : uint32_t hz);
201 : void (*power)(struct intel_connector *, bool enable);
202 : } backlight;
203 : };
204 :
205 : struct intel_connector {
206 : struct drm_connector base;
207 : /*
208 : * The fixed encoder this connector is connected to.
209 : */
210 : struct intel_encoder *encoder;
211 :
212 : /* Reads out the current hw, returning true if the connector is enabled
213 : * and active (i.e. dpms ON state). */
214 : bool (*get_hw_state)(struct intel_connector *);
215 :
216 : /*
217 : * Removes all interfaces through which the connector is accessible
218 : * - like sysfs, debugfs entries -, so that no new operations can be
219 : * started on the connector. Also makes sure all currently pending
220 : * operations finish before returing.
221 : */
222 : void (*unregister)(struct intel_connector *);
223 :
224 : /* Panel info for eDP and LVDS */
225 : struct intel_panel panel;
226 :
227 : /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
228 : struct edid *edid;
229 : struct edid *detect_edid;
230 :
231 : /* since POLL and HPD connectors may use the same HPD line keep the native
232 : state of connector->polled in case hotplug storm detection changes it */
233 : u8 polled;
234 :
235 : void *port; /* store this opaque as its illegal to dereference it */
236 :
237 : struct intel_dp *mst_port;
238 : };
239 :
240 : typedef struct dpll {
241 : /* given values */
242 : int n;
243 : int m1, m2;
244 : int p1, p2;
245 : /* derived values */
246 : int dot;
247 : int vco;
248 : int m;
249 : int p;
250 : } intel_clock_t;
251 :
252 : struct intel_atomic_state {
253 : struct drm_atomic_state base;
254 :
255 : unsigned int cdclk;
256 : bool dpll_set;
257 : struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
258 : };
259 :
260 : struct intel_plane_state {
261 : struct drm_plane_state base;
262 : struct drm_rect src;
263 : struct drm_rect dst;
264 : struct drm_rect clip;
265 : bool visible;
266 :
267 : /*
268 : * scaler_id
269 : * = -1 : not using a scaler
270 : * >= 0 : using a scalers
271 : *
272 : * plane requiring a scaler:
273 : * - During check_plane, its bit is set in
274 : * crtc_state->scaler_state.scaler_users by calling helper function
275 : * update_scaler_plane.
276 : * - scaler_id indicates the scaler it got assigned.
277 : *
278 : * plane doesn't require a scaler:
279 : * - this can happen when scaling is no more required or plane simply
280 : * got disabled.
281 : * - During check_plane, corresponding bit is reset in
282 : * crtc_state->scaler_state.scaler_users by calling helper function
283 : * update_scaler_plane.
284 : */
285 : int scaler_id;
286 :
287 : struct drm_intel_sprite_colorkey ckey;
288 : };
289 :
290 : struct intel_initial_plane_config {
291 : struct intel_framebuffer *fb;
292 : unsigned int tiling;
293 : int size;
294 : u32 base;
295 : };
296 :
297 : #define SKL_MIN_SRC_W 8
298 : #define SKL_MAX_SRC_W 4096
299 : #define SKL_MIN_SRC_H 8
300 : #define SKL_MAX_SRC_H 4096
301 : #define SKL_MIN_DST_W 8
302 : #define SKL_MAX_DST_W 4096
303 : #define SKL_MIN_DST_H 8
304 : #define SKL_MAX_DST_H 4096
305 :
306 : struct intel_scaler {
307 : int in_use;
308 : uint32_t mode;
309 : };
310 :
311 : struct intel_crtc_scaler_state {
312 : #define SKL_NUM_SCALERS 2
313 : struct intel_scaler scalers[SKL_NUM_SCALERS];
314 :
315 : /*
316 : * scaler_users: keeps track of users requesting scalers on this crtc.
317 : *
318 : * If a bit is set, a user is using a scaler.
319 : * Here user can be a plane or crtc as defined below:
320 : * bits 0-30 - plane (bit position is index from drm_plane_index)
321 : * bit 31 - crtc
322 : *
323 : * Instead of creating a new index to cover planes and crtc, using
324 : * existing drm_plane_index for planes which is well less than 31
325 : * planes and bit 31 for crtc. This should be fine to cover all
326 : * our platforms.
327 : *
328 : * intel_atomic_setup_scalers will setup available scalers to users
329 : * requesting scalers. It will gracefully fail if request exceeds
330 : * avilability.
331 : */
332 : #define SKL_CRTC_INDEX 31
333 : unsigned scaler_users;
334 :
335 : /* scaler used by crtc for panel fitting purpose */
336 : int scaler_id;
337 : };
338 :
339 : /* drm_mode->private_flags */
340 : #define I915_MODE_FLAG_INHERITED 1
341 :
342 : struct intel_crtc_state {
343 : struct drm_crtc_state base;
344 :
345 : /**
346 : * quirks - bitfield with hw state readout quirks
347 : *
348 : * For various reasons the hw state readout code might not be able to
349 : * completely faithfully read out the current state. These cases are
350 : * tracked with quirk flags so that fastboot and state checker can act
351 : * accordingly.
352 : */
353 : #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
354 : unsigned long quirks;
355 :
356 : bool update_pipe;
357 :
358 : /* Pipe source size (ie. panel fitter input size)
359 : * All planes will be positioned inside this space,
360 : * and get clipped at the edges. */
361 : int pipe_src_w, pipe_src_h;
362 :
363 : /* Whether to set up the PCH/FDI. Note that we never allow sharing
364 : * between pch encoders and cpu encoders. */
365 : bool has_pch_encoder;
366 :
367 : /* Are we sending infoframes on the attached port */
368 : bool has_infoframe;
369 :
370 : /* CPU Transcoder for the pipe. Currently this can only differ from the
371 : * pipe on Haswell (where we have a special eDP transcoder). */
372 : enum transcoder cpu_transcoder;
373 :
374 : /*
375 : * Use reduced/limited/broadcast rbg range, compressing from the full
376 : * range fed into the crtcs.
377 : */
378 : bool limited_color_range;
379 :
380 : /* DP has a bunch of special case unfortunately, so mark the pipe
381 : * accordingly. */
382 : bool has_dp_encoder;
383 :
384 : /* Whether we should send NULL infoframes. Required for audio. */
385 : bool has_hdmi_sink;
386 :
387 : /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
388 : * has_dp_encoder is set. */
389 : bool has_audio;
390 :
391 : /*
392 : * Enable dithering, used when the selected pipe bpp doesn't match the
393 : * plane bpp.
394 : */
395 : bool dither;
396 :
397 : /* Controls for the clock computation, to override various stages. */
398 : bool clock_set;
399 :
400 : /* SDVO TV has a bunch of special case. To make multifunction encoders
401 : * work correctly, we need to track this at runtime.*/
402 : bool sdvo_tv_clock;
403 :
404 : /*
405 : * crtc bandwidth limit, don't increase pipe bpp or clock if not really
406 : * required. This is set in the 2nd loop of calling encoder's
407 : * ->compute_config if the first pick doesn't work out.
408 : */
409 : bool bw_constrained;
410 :
411 : /* Settings for the intel dpll used on pretty much everything but
412 : * haswell. */
413 : struct dpll dpll;
414 :
415 : /* Selected dpll when shared or DPLL_ID_PRIVATE. */
416 : enum intel_dpll_id shared_dpll;
417 :
418 : /*
419 : * - PORT_CLK_SEL for DDI ports on HSW/BDW.
420 : * - enum skl_dpll on SKL
421 : */
422 : uint32_t ddi_pll_sel;
423 :
424 : /* Actual register state of the dpll, for shared dpll cross-checking. */
425 : struct intel_dpll_hw_state dpll_hw_state;
426 :
427 : int pipe_bpp;
428 : struct intel_link_m_n dp_m_n;
429 :
430 : /* m2_n2 for eDP downclock */
431 : struct intel_link_m_n dp_m2_n2;
432 : bool has_drrs;
433 :
434 : /*
435 : * Frequence the dpll for the port should run at. Differs from the
436 : * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
437 : * already multiplied by pixel_multiplier.
438 : */
439 : int port_clock;
440 :
441 : /* Used by SDVO (and if we ever fix it, HDMI). */
442 : unsigned pixel_multiplier;
443 :
444 : uint8_t lane_count;
445 :
446 : /* Panel fitter controls for gen2-gen4 + VLV */
447 : struct {
448 : u32 control;
449 : u32 pgm_ratios;
450 : u32 lvds_border_bits;
451 : } gmch_pfit;
452 :
453 : /* Panel fitter placement and size for Ironlake+ */
454 : struct {
455 : u32 pos;
456 : u32 size;
457 : bool enabled;
458 : bool force_thru;
459 : } pch_pfit;
460 :
461 : /* FDI configuration, only valid if has_pch_encoder is set. */
462 : int fdi_lanes;
463 : struct intel_link_m_n fdi_m_n;
464 :
465 : bool ips_enabled;
466 :
467 : bool double_wide;
468 :
469 : bool dp_encoder_is_mst;
470 : int pbn;
471 :
472 : struct intel_crtc_scaler_state scaler_state;
473 :
474 : /* w/a for waiting 2 vblanks during crtc enable */
475 : enum pipe hsw_workaround_pipe;
476 : };
477 :
478 : struct vlv_wm_state {
479 : struct vlv_pipe_wm wm[3];
480 : struct vlv_sr_wm sr[3];
481 : uint8_t num_active_planes;
482 : uint8_t num_levels;
483 : uint8_t level;
484 : bool cxsr;
485 : };
486 :
487 : struct intel_pipe_wm {
488 : struct intel_wm_level wm[5];
489 : uint32_t linetime;
490 : bool fbc_wm_enabled;
491 : bool pipe_enabled;
492 : bool sprites_enabled;
493 : bool sprites_scaled;
494 : };
495 :
496 : struct intel_mmio_flip {
497 : struct work_struct work;
498 : struct drm_i915_private *i915;
499 : struct drm_i915_gem_request *req;
500 : struct intel_crtc *crtc;
501 : };
502 :
503 : struct skl_pipe_wm {
504 : struct skl_wm_level wm[8];
505 : struct skl_wm_level trans_wm;
506 : uint32_t linetime;
507 : };
508 :
509 : /*
510 : * Tracking of operations that need to be performed at the beginning/end of an
511 : * atomic commit, outside the atomic section where interrupts are disabled.
512 : * These are generally operations that grab mutexes or might otherwise sleep
513 : * and thus can't be run with interrupts disabled.
514 : */
515 : struct intel_crtc_atomic_commit {
516 : /* Sleepable operations to perform before commit */
517 : bool wait_for_flips;
518 : bool disable_fbc;
519 : bool disable_ips;
520 : bool disable_cxsr;
521 : bool pre_disable_primary;
522 : bool update_wm_pre, update_wm_post;
523 : unsigned disabled_planes;
524 :
525 : /* Sleepable operations to perform after commit */
526 : unsigned fb_bits;
527 : bool wait_vblank;
528 : bool update_fbc;
529 : bool post_enable_primary;
530 : unsigned update_sprite_watermarks;
531 : };
532 :
533 : struct intel_crtc {
534 : struct drm_crtc base;
535 : enum pipe pipe;
536 : enum plane plane;
537 : u8 lut_r[256], lut_g[256], lut_b[256];
538 : /*
539 : * Whether the crtc and the connected output pipeline is active. Implies
540 : * that crtc->enabled is set, i.e. the current mode configuration has
541 : * some outputs connected to this crtc.
542 : */
543 : bool active;
544 : unsigned long enabled_power_domains;
545 : bool lowfreq_avail;
546 : struct intel_overlay *overlay;
547 : struct intel_unpin_work *unpin_work;
548 :
549 : atomic_t unpin_work_count;
550 :
551 : /* Display surface base address adjustement for pageflips. Note that on
552 : * gen4+ this only adjusts up to a tile, offsets within a tile are
553 : * handled in the hw itself (with the TILEOFF register). */
554 : unsigned long dspaddr_offset;
555 : int adjusted_x;
556 : int adjusted_y;
557 :
558 : uint32_t cursor_addr;
559 : uint32_t cursor_cntl;
560 : uint32_t cursor_size;
561 : uint32_t cursor_base;
562 :
563 : struct intel_crtc_state *config;
564 :
565 : /* reset counter value when the last flip was submitted */
566 : unsigned int reset_counter;
567 :
568 : /* Access to these should be protected by dev_priv->irq_lock. */
569 : bool cpu_fifo_underrun_disabled;
570 : bool pch_fifo_underrun_disabled;
571 :
572 : /* per-pipe watermark state */
573 : struct {
574 : /* watermarks currently being used */
575 : struct intel_pipe_wm active;
576 : /* SKL wm values currently in use */
577 : struct skl_pipe_wm skl_active;
578 : /* allow CxSR on this pipe */
579 : bool cxsr_allowed;
580 : } wm;
581 :
582 : int scanline_offset;
583 :
584 : struct {
585 : unsigned start_vbl_count;
586 : ktime_t start_vbl_time;
587 : int min_vbl, max_vbl;
588 : int scanline_start;
589 : } debug;
590 :
591 : struct intel_crtc_atomic_commit atomic;
592 :
593 : /* scalers available on this crtc */
594 : int num_scalers;
595 :
596 : struct vlv_wm_state wm_state;
597 : };
598 :
599 : struct intel_plane_wm_parameters {
600 : uint32_t horiz_pixels;
601 : uint32_t vert_pixels;
602 : /*
603 : * For packed pixel formats:
604 : * bytes_per_pixel - holds bytes per pixel
605 : * For planar pixel formats:
606 : * bytes_per_pixel - holds bytes per pixel for uv-plane
607 : * y_bytes_per_pixel - holds bytes per pixel for y-plane
608 : */
609 : uint8_t bytes_per_pixel;
610 : uint8_t y_bytes_per_pixel;
611 : bool enabled;
612 : bool scaled;
613 : u64 tiling;
614 : unsigned int rotation;
615 : uint16_t fifo_size;
616 : };
617 :
618 : struct intel_plane {
619 : struct drm_plane base;
620 : int plane;
621 : enum pipe pipe;
622 : bool can_scale;
623 : int max_downscale;
624 : uint32_t frontbuffer_bit;
625 :
626 : /* Since we need to change the watermarks before/after
627 : * enabling/disabling the planes, we need to store the parameters here
628 : * as the other pieces of the struct may not reflect the values we want
629 : * for the watermark calculations. Currently only Haswell uses this.
630 : */
631 : struct intel_plane_wm_parameters wm;
632 :
633 : /*
634 : * NOTE: Do not place new plane state fields here (e.g., when adding
635 : * new plane properties). New runtime state should now be placed in
636 : * the intel_plane_state structure and accessed via drm_plane->state.
637 : */
638 :
639 : void (*update_plane)(struct drm_plane *plane,
640 : struct drm_crtc *crtc,
641 : struct drm_framebuffer *fb,
642 : int crtc_x, int crtc_y,
643 : unsigned int crtc_w, unsigned int crtc_h,
644 : uint32_t x, uint32_t y,
645 : uint32_t src_w, uint32_t src_h);
646 : void (*disable_plane)(struct drm_plane *plane,
647 : struct drm_crtc *crtc);
648 : int (*check_plane)(struct drm_plane *plane,
649 : struct intel_crtc_state *crtc_state,
650 : struct intel_plane_state *state);
651 : void (*commit_plane)(struct drm_plane *plane,
652 : struct intel_plane_state *state);
653 : };
654 :
655 : struct intel_watermark_params {
656 : unsigned long fifo_size;
657 : unsigned long max_wm;
658 : unsigned long default_wm;
659 : unsigned long guard_size;
660 : unsigned long cacheline_size;
661 : };
662 :
663 : struct cxsr_latency {
664 : int is_desktop;
665 : int is_ddr3;
666 : unsigned long fsb_freq;
667 : unsigned long mem_freq;
668 : unsigned long display_sr;
669 : unsigned long display_hpll_disable;
670 : unsigned long cursor_sr;
671 : unsigned long cursor_hpll_disable;
672 : };
673 :
674 : #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
675 : #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
676 : #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
677 : #define to_intel_connector(x) container_of(x, struct intel_connector, base)
678 : #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
679 : #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
680 : #define to_intel_plane(x) container_of(x, struct intel_plane, base)
681 : #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
682 : #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
683 :
684 : struct intel_hdmi {
685 : u32 hdmi_reg;
686 : int ddc_bus;
687 : bool limited_color_range;
688 : bool color_range_auto;
689 : bool has_hdmi_sink;
690 : bool has_audio;
691 : enum hdmi_force_audio force_audio;
692 : bool rgb_quant_range_selectable;
693 : enum hdmi_picture_aspect aspect_ratio;
694 : struct intel_connector *attached_connector;
695 : void (*write_infoframe)(struct drm_encoder *encoder,
696 : enum hdmi_infoframe_type type,
697 : const void *frame, ssize_t len);
698 : void (*set_infoframes)(struct drm_encoder *encoder,
699 : bool enable,
700 : const struct drm_display_mode *adjusted_mode);
701 : bool (*infoframe_enabled)(struct drm_encoder *encoder);
702 : };
703 :
704 : struct intel_dp_mst_encoder;
705 : #define DP_MAX_DOWNSTREAM_PORTS 0x10
706 :
707 : /*
708 : * enum link_m_n_set:
709 : * When platform provides two set of M_N registers for dp, we can
710 : * program them and switch between them incase of DRRS.
711 : * But When only one such register is provided, we have to program the
712 : * required divider value on that registers itself based on the DRRS state.
713 : *
714 : * M1_N1 : Program dp_m_n on M1_N1 registers
715 : * dp_m2_n2 on M2_N2 registers (If supported)
716 : *
717 : * M2_N2 : Program dp_m2_n2 on M1_N1 registers
718 : * M2_N2 registers are not supported
719 : */
720 :
721 : enum link_m_n_set {
722 : /* Sets the m1_n1 and m2_n2 */
723 : M1_N1 = 0,
724 : M2_N2
725 : };
726 :
727 : struct sink_crc {
728 : bool started;
729 : u8 last_crc[6];
730 : int last_count;
731 : };
732 :
733 : struct intel_dp {
734 : uint32_t output_reg;
735 : uint32_t aux_ch_ctl_reg;
736 : uint32_t DP;
737 : int link_rate;
738 : uint8_t lane_count;
739 : bool has_audio;
740 : enum hdmi_force_audio force_audio;
741 : bool limited_color_range;
742 : bool color_range_auto;
743 : uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
744 : uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
745 : uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
746 : /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
747 : uint8_t num_sink_rates;
748 : int sink_rates[DP_MAX_SUPPORTED_RATES];
749 : struct sink_crc sink_crc;
750 : struct drm_dp_aux aux;
751 : uint8_t train_set[4];
752 : int panel_power_up_delay;
753 : int panel_power_down_delay;
754 : int panel_power_cycle_delay;
755 : int backlight_on_delay;
756 : int backlight_off_delay;
757 : struct delayed_work panel_vdd_work;
758 : bool want_panel_vdd;
759 : unsigned long last_power_cycle;
760 : unsigned long last_power_on;
761 : unsigned long last_backlight_off;
762 :
763 : struct notifier_block edp_notifier;
764 :
765 : /*
766 : * Pipe whose power sequencer is currently locked into
767 : * this port. Only relevant on VLV/CHV.
768 : */
769 : enum pipe pps_pipe;
770 : struct edp_power_seq pps_delays;
771 :
772 : bool can_mst; /* this port supports mst */
773 : bool is_mst;
774 : int active_mst_links;
775 : /* connector directly attached - won't be use for modeset in mst world */
776 : struct intel_connector *attached_connector;
777 :
778 : /* mst connector list */
779 : struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
780 : struct drm_dp_mst_topology_mgr mst_mgr;
781 :
782 : uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
783 : /*
784 : * This function returns the value we have to program the AUX_CTL
785 : * register with to kick off an AUX transaction.
786 : */
787 : uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
788 : bool has_aux_irq,
789 : int send_bytes,
790 : uint32_t aux_clock_divider);
791 :
792 : /* Displayport compliance testing */
793 : unsigned long compliance_test_type;
794 : unsigned long compliance_test_data;
795 : bool compliance_test_active;
796 : };
797 :
798 : struct intel_digital_port {
799 : struct intel_encoder base;
800 : enum port port;
801 : u32 saved_port_bits;
802 : struct intel_dp dp;
803 : struct intel_hdmi hdmi;
804 : enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
805 : bool release_cl2_override;
806 : };
807 :
808 : struct intel_dp_mst_encoder {
809 : struct intel_encoder base;
810 : enum pipe pipe;
811 : struct intel_digital_port *primary;
812 : void *port; /* store this opaque as its illegal to dereference it */
813 : };
814 :
815 : static inline enum dpio_channel
816 0 : vlv_dport_to_channel(struct intel_digital_port *dport)
817 : {
818 0 : switch (dport->port) {
819 : case PORT_B:
820 : case PORT_D:
821 0 : return DPIO_CH0;
822 : case PORT_C:
823 0 : return DPIO_CH1;
824 : default:
825 0 : BUG();
826 : }
827 0 : }
828 :
829 : static inline enum dpio_phy
830 0 : vlv_dport_to_phy(struct intel_digital_port *dport)
831 : {
832 0 : switch (dport->port) {
833 : case PORT_B:
834 : case PORT_C:
835 0 : return DPIO_PHY0;
836 : case PORT_D:
837 0 : return DPIO_PHY1;
838 : default:
839 0 : BUG();
840 : }
841 0 : }
842 :
843 : static inline enum dpio_channel
844 0 : vlv_pipe_to_channel(enum pipe pipe)
845 : {
846 0 : switch (pipe) {
847 : case PIPE_A:
848 : case PIPE_C:
849 0 : return DPIO_CH0;
850 : case PIPE_B:
851 0 : return DPIO_CH1;
852 : default:
853 0 : BUG();
854 : }
855 0 : }
856 :
857 : static inline struct drm_crtc *
858 0 : intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
859 : {
860 0 : struct drm_i915_private *dev_priv = dev->dev_private;
861 0 : return dev_priv->pipe_to_crtc_mapping[pipe];
862 : }
863 :
864 : static inline struct drm_crtc *
865 0 : intel_get_crtc_for_plane(struct drm_device *dev, int plane)
866 : {
867 0 : struct drm_i915_private *dev_priv = dev->dev_private;
868 0 : return dev_priv->plane_to_crtc_mapping[plane];
869 : }
870 :
871 : struct intel_unpin_work {
872 : struct work_struct work;
873 : struct drm_crtc *crtc;
874 : struct drm_framebuffer *old_fb;
875 : struct drm_i915_gem_object *pending_flip_obj;
876 : struct drm_pending_vblank_event *event;
877 : atomic_t pending;
878 : #define INTEL_FLIP_INACTIVE 0
879 : #define INTEL_FLIP_PENDING 1
880 : #define INTEL_FLIP_COMPLETE 2
881 : u32 flip_count;
882 : u32 gtt_offset;
883 : struct drm_i915_gem_request *flip_queued_req;
884 : u32 flip_queued_vblank;
885 : u32 flip_ready_vblank;
886 : bool enable_stall_check;
887 : };
888 :
889 : struct intel_load_detect_pipe {
890 : struct drm_framebuffer *release_fb;
891 : bool load_detect_temp;
892 : int dpms_mode;
893 : };
894 :
895 : static inline struct intel_encoder *
896 0 : intel_attached_encoder(struct drm_connector *connector)
897 : {
898 0 : return to_intel_connector(connector)->encoder;
899 : }
900 :
901 : static inline struct intel_digital_port *
902 0 : enc_to_dig_port(struct drm_encoder *encoder)
903 : {
904 0 : return container_of(encoder, struct intel_digital_port, base.base);
905 : }
906 :
907 : static inline struct intel_dp_mst_encoder *
908 0 : enc_to_mst(struct drm_encoder *encoder)
909 : {
910 0 : return container_of(encoder, struct intel_dp_mst_encoder, base.base);
911 : }
912 :
913 0 : static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
914 : {
915 0 : return &enc_to_dig_port(encoder)->dp;
916 : }
917 :
918 : static inline struct intel_digital_port *
919 0 : dp_to_dig_port(struct intel_dp *intel_dp)
920 : {
921 0 : return container_of(intel_dp, struct intel_digital_port, dp);
922 : }
923 :
924 : static inline struct intel_digital_port *
925 0 : hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
926 : {
927 0 : return container_of(intel_hdmi, struct intel_digital_port, hdmi);
928 : }
929 :
930 : /*
931 : * Returns the number of planes for this pipe, ie the number of sprites + 1
932 : * (primary plane). This doesn't count the cursor plane then.
933 : */
934 0 : static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
935 : {
936 0 : return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
937 : }
938 :
939 : /* intel_fifo_underrun.c */
940 : bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
941 : enum pipe pipe, bool enable);
942 : bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
943 : enum transcoder pch_transcoder,
944 : bool enable);
945 : void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
946 : enum pipe pipe);
947 : void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
948 : enum transcoder pch_transcoder);
949 : void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
950 :
951 : /* i915_irq.c */
952 : void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
953 : void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
954 : void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
955 : void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
956 : void gen6_reset_rps_interrupts(struct drm_device *dev);
957 : void gen6_enable_rps_interrupts(struct drm_device *dev);
958 : void gen6_disable_rps_interrupts(struct drm_device *dev);
959 : u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
960 : void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
961 : void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
962 0 : static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
963 : {
964 : /*
965 : * We only use drm_irq_uninstall() at unload and VT switch, so
966 : * this is the only thing we need to check.
967 : */
968 0 : return dev_priv->pm.irqs_enabled;
969 : }
970 :
971 : int intel_get_crtc_scanline(struct intel_crtc *crtc);
972 : void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
973 : unsigned int pipe_mask);
974 :
975 : /* intel_crt.c */
976 : void intel_crt_init(struct drm_device *dev);
977 :
978 :
979 : /* intel_ddi.c */
980 : void intel_prepare_ddi(struct drm_device *dev);
981 : void hsw_fdi_link_train(struct drm_crtc *crtc);
982 : void intel_ddi_init(struct drm_device *dev, enum port port);
983 : enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
984 : bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
985 : void intel_ddi_pll_init(struct drm_device *dev);
986 : void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
987 : void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
988 : enum transcoder cpu_transcoder);
989 : void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
990 : void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
991 : bool intel_ddi_pll_select(struct intel_crtc *crtc,
992 : struct intel_crtc_state *crtc_state);
993 : void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
994 : void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
995 : bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
996 : void intel_ddi_fdi_disable(struct drm_crtc *crtc);
997 : void intel_ddi_get_config(struct intel_encoder *encoder,
998 : struct intel_crtc_state *pipe_config);
999 : struct intel_encoder *
1000 : intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1001 :
1002 : void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1003 : void intel_ddi_clock_get(struct intel_encoder *encoder,
1004 : struct intel_crtc_state *pipe_config);
1005 : void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1006 : uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1007 :
1008 : /* intel_frontbuffer.c */
1009 : void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1010 : enum fb_op_origin origin);
1011 : void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1012 : unsigned frontbuffer_bits);
1013 : void intel_frontbuffer_flip_complete(struct drm_device *dev,
1014 : unsigned frontbuffer_bits);
1015 : void intel_frontbuffer_flip(struct drm_device *dev,
1016 : unsigned frontbuffer_bits);
1017 : unsigned int intel_fb_align_height(struct drm_device *dev,
1018 : unsigned int height,
1019 : uint32_t pixel_format,
1020 : uint64_t fb_format_modifier);
1021 : void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1022 : enum fb_op_origin origin);
1023 : u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
1024 : uint32_t pixel_format);
1025 :
1026 : /* intel_audio.c */
1027 : void intel_init_audio(struct drm_device *dev);
1028 : void intel_audio_codec_enable(struct intel_encoder *encoder);
1029 : void intel_audio_codec_disable(struct intel_encoder *encoder);
1030 : void i915_audio_component_init(struct drm_i915_private *dev_priv);
1031 : void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1032 :
1033 : /* intel_display.c */
1034 : extern const struct drm_plane_funcs intel_plane_funcs;
1035 : bool intel_has_pending_fb_unpin(struct drm_device *dev);
1036 : int intel_pch_rawclk(struct drm_device *dev);
1037 : int intel_hrawclk(struct drm_device *dev);
1038 : void intel_mark_busy(struct drm_device *dev);
1039 : void intel_mark_idle(struct drm_device *dev);
1040 : void intel_crtc_restore_mode(struct drm_crtc *crtc);
1041 : int intel_display_suspend(struct drm_device *dev);
1042 : void intel_encoder_destroy(struct drm_encoder *encoder);
1043 : int intel_connector_init(struct intel_connector *);
1044 : struct intel_connector *intel_connector_alloc(void);
1045 : bool intel_connector_get_hw_state(struct intel_connector *connector);
1046 : void intel_connector_attach_encoder(struct intel_connector *connector,
1047 : struct intel_encoder *encoder);
1048 : struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1049 : struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1050 : struct drm_crtc *crtc);
1051 : enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1052 : int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1053 : struct drm_file *file_priv);
1054 : enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1055 : enum pipe pipe);
1056 : bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1057 : static inline void
1058 0 : intel_wait_for_vblank(struct drm_device *dev, int pipe)
1059 : {
1060 0 : drm_wait_one_vblank(dev, pipe);
1061 0 : }
1062 : int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1063 : void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1064 : struct intel_digital_port *dport,
1065 : unsigned int expected_mask);
1066 : bool intel_get_load_detect_pipe(struct drm_connector *connector,
1067 : struct drm_display_mode *mode,
1068 : struct intel_load_detect_pipe *old,
1069 : struct drm_modeset_acquire_ctx *ctx);
1070 : void intel_release_load_detect_pipe(struct drm_connector *connector,
1071 : struct intel_load_detect_pipe *old,
1072 : struct drm_modeset_acquire_ctx *ctx);
1073 : int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1074 : struct drm_framebuffer *fb,
1075 : const struct drm_plane_state *plane_state,
1076 : struct intel_engine_cs *pipelined,
1077 : struct drm_i915_gem_request **pipelined_request);
1078 : struct drm_framebuffer *
1079 : __intel_framebuffer_create(struct drm_device *dev,
1080 : struct drm_mode_fb_cmd2 *mode_cmd,
1081 : struct drm_i915_gem_object *obj);
1082 : void intel_prepare_page_flip(struct drm_device *dev, int plane);
1083 : void intel_finish_page_flip(struct drm_device *dev, int pipe);
1084 : void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1085 : void intel_check_page_flip(struct drm_device *dev, int pipe);
1086 : int intel_prepare_plane_fb(struct drm_plane *plane,
1087 : const struct drm_plane_state *new_state);
1088 : void intel_cleanup_plane_fb(struct drm_plane *plane,
1089 : const struct drm_plane_state *old_state);
1090 : int intel_plane_atomic_get_property(struct drm_plane *plane,
1091 : const struct drm_plane_state *state,
1092 : struct drm_property *property,
1093 : uint64_t *val);
1094 : int intel_plane_atomic_set_property(struct drm_plane *plane,
1095 : struct drm_plane_state *state,
1096 : struct drm_property *property,
1097 : uint64_t val);
1098 : int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1099 : struct drm_plane_state *plane_state);
1100 :
1101 : unsigned int
1102 : intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1103 : uint64_t fb_format_modifier, unsigned int plane);
1104 :
1105 : static inline bool
1106 0 : intel_rotation_90_or_270(unsigned int rotation)
1107 : {
1108 0 : return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1109 : }
1110 :
1111 : void intel_create_rotation_property(struct drm_device *dev,
1112 : struct intel_plane *plane);
1113 :
1114 : /* shared dpll functions */
1115 : struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1116 : void assert_shared_dpll(struct drm_i915_private *dev_priv,
1117 : struct intel_shared_dpll *pll,
1118 : bool state);
1119 : #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1120 : #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1121 : struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1122 : struct intel_crtc_state *state);
1123 :
1124 : void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1125 : const struct dpll *dpll);
1126 : void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1127 :
1128 : /* modesetting asserts */
1129 : void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1130 : enum pipe pipe);
1131 : void assert_pll(struct drm_i915_private *dev_priv,
1132 : enum pipe pipe, bool state);
1133 : #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1134 : #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1135 : void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1136 : enum pipe pipe, bool state);
1137 : #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1138 : #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1139 : void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1140 : #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1141 : #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1142 : unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
1143 : int *x, int *y,
1144 : unsigned int tiling_mode,
1145 : unsigned int bpp,
1146 : unsigned int pitch);
1147 : void intel_prepare_reset(struct drm_device *dev);
1148 : void intel_finish_reset(struct drm_device *dev);
1149 : void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1150 : void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1151 : void broxton_init_cdclk(struct drm_device *dev);
1152 : void broxton_uninit_cdclk(struct drm_device *dev);
1153 : void broxton_ddi_phy_init(struct drm_device *dev);
1154 : void broxton_ddi_phy_uninit(struct drm_device *dev);
1155 : void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1156 : void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1157 : void skl_init_cdclk(struct drm_i915_private *dev_priv);
1158 : void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1159 : void intel_dp_get_m_n(struct intel_crtc *crtc,
1160 : struct intel_crtc_state *pipe_config);
1161 : void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1162 : int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1163 : void
1164 : ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1165 : int dotclock);
1166 : bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1167 : intel_clock_t *best_clock);
1168 : int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1169 :
1170 : bool intel_crtc_active(struct drm_crtc *crtc);
1171 : void hsw_enable_ips(struct intel_crtc *crtc);
1172 : void hsw_disable_ips(struct intel_crtc *crtc);
1173 : enum intel_display_power_domain
1174 : intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1175 : enum intel_display_power_domain
1176 : intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1177 : void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1178 : struct intel_crtc_state *pipe_config);
1179 : void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1180 : void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1181 :
1182 : int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1183 : int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1184 :
1185 : u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1186 : struct drm_i915_gem_object *obj,
1187 : unsigned int plane);
1188 :
1189 : u32 skl_plane_ctl_format(uint32_t pixel_format);
1190 : u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1191 : u32 skl_plane_ctl_rotation(unsigned int rotation);
1192 :
1193 : /* intel_csr.c */
1194 : void intel_csr_ucode_init(struct drm_device *dev);
1195 : enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1196 : void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1197 : enum csr_state state);
1198 : void intel_csr_load_program(struct drm_device *dev);
1199 : void intel_csr_ucode_fini(struct drm_device *dev);
1200 : void assert_csr_loaded(struct drm_i915_private *dev_priv);
1201 :
1202 : /* intel_dp.c */
1203 : bool intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1204 : bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1205 : struct intel_connector *intel_connector);
1206 : void intel_dp_set_link_params(struct intel_dp *intel_dp,
1207 : const struct intel_crtc_state *pipe_config);
1208 : void intel_dp_start_link_train(struct intel_dp *intel_dp);
1209 : void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1210 : void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1211 : void intel_dp_encoder_reset(struct drm_encoder *encoder);
1212 : void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1213 : void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1214 : int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1215 : bool intel_dp_compute_config(struct intel_encoder *encoder,
1216 : struct intel_crtc_state *pipe_config);
1217 : bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1218 : enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1219 : bool long_hpd);
1220 : void intel_edp_backlight_on(struct intel_dp *intel_dp);
1221 : void intel_edp_backlight_off(struct intel_dp *intel_dp);
1222 : void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1223 : void intel_edp_panel_on(struct intel_dp *intel_dp);
1224 : void intel_edp_panel_off(struct intel_dp *intel_dp);
1225 : void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1226 : void intel_dp_mst_suspend(struct drm_device *dev);
1227 : void intel_dp_mst_resume(struct drm_device *dev);
1228 : int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1229 : int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1230 : void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1231 : void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1232 : uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1233 : void intel_plane_destroy(struct drm_plane *plane);
1234 : void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1235 : void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1236 : void intel_edp_drrs_invalidate(struct drm_device *dev,
1237 : unsigned frontbuffer_bits);
1238 : void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1239 : void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1240 :
1241 : /* intel_dp_mst.c */
1242 : int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1243 : void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1244 : /* intel_dsi.c */
1245 : void intel_dsi_init(struct drm_device *dev);
1246 :
1247 :
1248 : /* intel_dvo.c */
1249 : void intel_dvo_init(struct drm_device *dev);
1250 :
1251 :
1252 : /* legacy fbdev emulation in intel_fbdev.c */
1253 : #ifdef CONFIG_DRM_FBDEV_EMULATION
1254 : extern int intel_fbdev_init(struct drm_device *dev);
1255 : extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1256 : extern void intel_fbdev_fini(struct drm_device *dev);
1257 : extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1258 : extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1259 : extern void intel_fbdev_restore_mode(struct drm_device *dev);
1260 : #else
1261 : static inline int intel_fbdev_init(struct drm_device *dev)
1262 : {
1263 : return 0;
1264 : }
1265 :
1266 : static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1267 : {
1268 : }
1269 :
1270 : static inline void intel_fbdev_fini(struct drm_device *dev)
1271 : {
1272 : }
1273 :
1274 : static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1275 : {
1276 : }
1277 :
1278 : static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1279 : {
1280 : }
1281 : #endif
1282 :
1283 : /* intel_fbc.c */
1284 : bool intel_fbc_enabled(struct drm_i915_private *dev_priv);
1285 : void intel_fbc_update(struct drm_i915_private *dev_priv);
1286 : void intel_fbc_init(struct drm_i915_private *dev_priv);
1287 : void intel_fbc_disable(struct drm_i915_private *dev_priv);
1288 : void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1289 : void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1290 : unsigned int frontbuffer_bits,
1291 : enum fb_op_origin origin);
1292 : void intel_fbc_flush(struct drm_i915_private *dev_priv,
1293 : unsigned int frontbuffer_bits, enum fb_op_origin origin);
1294 : const char *intel_no_fbc_reason_str(enum no_fbc_reason reason);
1295 : void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1296 :
1297 : /* intel_hdmi.c */
1298 : void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1299 : void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1300 : struct intel_connector *intel_connector);
1301 : struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1302 : bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1303 : struct intel_crtc_state *pipe_config);
1304 :
1305 :
1306 : /* intel_lvds.c */
1307 : void intel_lvds_init(struct drm_device *dev);
1308 : bool intel_is_dual_link_lvds(struct drm_device *dev);
1309 :
1310 :
1311 : /* intel_modes.c */
1312 : int intel_connector_update_modes(struct drm_connector *connector,
1313 : struct edid *edid);
1314 : int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1315 : void intel_attach_force_audio_property(struct drm_connector *connector);
1316 : void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1317 : void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1318 :
1319 :
1320 : /* intel_overlay.c */
1321 : void intel_setup_overlay(struct drm_device *dev);
1322 : void intel_cleanup_overlay(struct drm_device *dev);
1323 : int intel_overlay_switch_off(struct intel_overlay *overlay);
1324 : int intel_overlay_put_image(struct drm_device *dev, void *data,
1325 : struct drm_file *file_priv);
1326 : int intel_overlay_attrs(struct drm_device *dev, void *data,
1327 : struct drm_file *file_priv);
1328 : void intel_overlay_reset(struct drm_i915_private *dev_priv);
1329 :
1330 :
1331 : /* intel_panel.c */
1332 : int intel_panel_init(struct intel_panel *panel,
1333 : struct drm_display_mode *fixed_mode,
1334 : struct drm_display_mode *downclock_mode);
1335 : void intel_panel_fini(struct intel_panel *panel);
1336 : void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1337 : struct drm_display_mode *adjusted_mode);
1338 : void intel_pch_panel_fitting(struct intel_crtc *crtc,
1339 : struct intel_crtc_state *pipe_config,
1340 : int fitting_mode);
1341 : void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1342 : struct intel_crtc_state *pipe_config,
1343 : int fitting_mode);
1344 : void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1345 : u32 level, u32 max);
1346 : int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1347 : void intel_panel_enable_backlight(struct intel_connector *connector);
1348 : void intel_panel_disable_backlight(struct intel_connector *connector);
1349 : void intel_panel_destroy_backlight(struct drm_connector *connector);
1350 : enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1351 : extern struct drm_display_mode *intel_find_panel_downclock(
1352 : struct drm_device *dev,
1353 : struct drm_display_mode *fixed_mode,
1354 : struct drm_connector *connector);
1355 : void intel_backlight_register(struct drm_device *dev);
1356 : void intel_backlight_unregister(struct drm_device *dev);
1357 :
1358 :
1359 : /* intel_psr.c */
1360 : void intel_psr_enable(struct intel_dp *intel_dp);
1361 : void intel_psr_disable(struct intel_dp *intel_dp);
1362 : void intel_psr_invalidate(struct drm_device *dev,
1363 : unsigned frontbuffer_bits);
1364 : void intel_psr_flush(struct drm_device *dev,
1365 : unsigned frontbuffer_bits,
1366 : enum fb_op_origin origin);
1367 : void intel_psr_init(struct drm_device *dev);
1368 : void intel_psr_single_frame_update(struct drm_device *dev,
1369 : unsigned frontbuffer_bits);
1370 :
1371 : /* intel_runtime_pm.c */
1372 : int intel_power_domains_init(struct drm_i915_private *);
1373 : void intel_power_domains_fini(struct drm_i915_private *);
1374 : void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1375 : void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1376 :
1377 : bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1378 : enum intel_display_power_domain domain);
1379 : bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1380 : enum intel_display_power_domain domain);
1381 : void intel_display_power_get(struct drm_i915_private *dev_priv,
1382 : enum intel_display_power_domain domain);
1383 : void intel_display_power_put(struct drm_i915_private *dev_priv,
1384 : enum intel_display_power_domain domain);
1385 : void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1386 : void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1387 : void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1388 :
1389 : void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1390 :
1391 : void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1392 : bool override, unsigned int mask);
1393 : bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1394 : enum dpio_channel ch, bool override);
1395 :
1396 :
1397 : /* intel_pm.c */
1398 : void intel_init_clock_gating(struct drm_device *dev);
1399 : void intel_suspend_hw(struct drm_device *dev);
1400 : int ilk_wm_max_level(const struct drm_device *dev);
1401 : void intel_update_watermarks(struct drm_crtc *crtc);
1402 : void intel_update_sprite_watermarks(struct drm_plane *plane,
1403 : struct drm_crtc *crtc,
1404 : uint32_t sprite_width,
1405 : uint32_t sprite_height,
1406 : int pixel_size,
1407 : bool enabled, bool scaled);
1408 : void intel_init_pm(struct drm_device *dev);
1409 : void intel_pm_setup(struct drm_device *dev);
1410 : void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1411 : void intel_gpu_ips_teardown(void);
1412 : void intel_init_gt_powersave(struct drm_device *dev);
1413 : void intel_cleanup_gt_powersave(struct drm_device *dev);
1414 : void intel_enable_gt_powersave(struct drm_device *dev);
1415 : void intel_disable_gt_powersave(struct drm_device *dev);
1416 : void intel_suspend_gt_powersave(struct drm_device *dev);
1417 : void intel_reset_gt_powersave(struct drm_device *dev);
1418 : void gen6_update_ring_freq(struct drm_device *dev);
1419 : void gen6_rps_busy(struct drm_i915_private *dev_priv);
1420 : void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1421 : void gen6_rps_idle(struct drm_i915_private *dev_priv);
1422 : void gen6_rps_boost(struct drm_i915_private *dev_priv,
1423 : struct intel_rps_client *rps,
1424 : unsigned long submitted);
1425 : void intel_queue_rps_boost_for_request(struct drm_device *dev,
1426 : struct drm_i915_gem_request *req);
1427 : void vlv_wm_get_hw_state(struct drm_device *dev);
1428 : void ilk_wm_get_hw_state(struct drm_device *dev);
1429 : void skl_wm_get_hw_state(struct drm_device *dev);
1430 : void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1431 : struct skl_ddb_allocation *ddb /* out */);
1432 : uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1433 :
1434 : /* intel_sdvo.c */
1435 : bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1436 :
1437 :
1438 : /* intel_sprite.c */
1439 : int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1440 : int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1441 : struct drm_file *file_priv);
1442 : void intel_pipe_update_start(struct intel_crtc *crtc);
1443 : void intel_pipe_update_end(struct intel_crtc *crtc);
1444 :
1445 : /* intel_tv.c */
1446 : void intel_tv_init(struct drm_device *dev);
1447 :
1448 : /* intel_atomic.c */
1449 : int intel_connector_atomic_get_property(struct drm_connector *connector,
1450 : const struct drm_connector_state *state,
1451 : struct drm_property *property,
1452 : uint64_t *val);
1453 : struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1454 : void intel_crtc_destroy_state(struct drm_crtc *crtc,
1455 : struct drm_crtc_state *state);
1456 : struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1457 : void intel_atomic_state_clear(struct drm_atomic_state *);
1458 : struct intel_shared_dpll_config *
1459 : intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1460 :
1461 : static inline struct intel_crtc_state *
1462 0 : intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1463 : struct intel_crtc *crtc)
1464 : {
1465 : struct drm_crtc_state *crtc_state;
1466 0 : crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1467 0 : if (IS_ERR(crtc_state))
1468 0 : return ERR_CAST(crtc_state);
1469 :
1470 0 : return to_intel_crtc_state(crtc_state);
1471 0 : }
1472 : int intel_atomic_setup_scalers(struct drm_device *dev,
1473 : struct intel_crtc *intel_crtc,
1474 : struct intel_crtc_state *crtc_state);
1475 :
1476 : /* intel_atomic_plane.c */
1477 : struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1478 : struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1479 : void intel_plane_destroy_state(struct drm_plane *plane,
1480 : struct drm_plane_state *state);
1481 : extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1482 :
1483 : #endif /* __INTEL_DRV_H__ */
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