Line data Source code
1 : /*
2 : * Copyright © 2013 Intel Corporation
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice (including the next
12 : * paragraph) shall be included in all copies or substantial portions of the
13 : * Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 : * DEALINGS IN THE SOFTWARE.
22 : *
23 : * Author: Jani Nikula <jani.nikula@intel.com>
24 : */
25 :
26 : #include <dev/pci/drm/drmP.h>
27 : #include <dev/pci/drm/drm_atomic_helper.h>
28 : #include <dev/pci/drm/drm_crtc.h>
29 : #include <dev/pci/drm/drm_edid.h>
30 : #include <dev/pci/drm/i915_drm.h>
31 : #include <dev/pci/drm/drm_panel.h>
32 : #include <dev/pci/drm/drm_mipi_dsi.h>
33 : #ifdef __linux__
34 : #include <linux/slab.h>
35 : #include <linux/gpio/consumer.h>
36 : #endif
37 : #include "i915_drv.h"
38 : #include "intel_drv.h"
39 : #include "intel_dsi.h"
40 :
41 : static const struct {
42 : u16 panel_id;
43 : struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
44 : } intel_dsi_drivers[] = {
45 : {
46 : .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
47 : .init = vbt_panel_init,
48 : },
49 : };
50 :
51 0 : static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
52 : {
53 0 : struct drm_encoder *encoder = &intel_dsi->base.base;
54 0 : struct drm_device *dev = encoder->dev;
55 0 : struct drm_i915_private *dev_priv = dev->dev_private;
56 : u32 mask;
57 :
58 : mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
59 : LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
60 :
61 0 : if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
62 0 : DRM_ERROR("DPI FIFOs are not empty\n");
63 0 : }
64 :
65 0 : static void write_data(struct drm_i915_private *dev_priv, u32 reg,
66 : const u8 *data, u32 len)
67 : {
68 : u32 i, j;
69 :
70 0 : for (i = 0; i < len; i += 4) {
71 : u32 val = 0;
72 :
73 0 : for (j = 0; j < min_t(u32, len - i, 4); j++)
74 0 : val |= *data++ << 8 * j;
75 :
76 0 : I915_WRITE(reg, val);
77 : }
78 0 : }
79 :
80 0 : static void read_data(struct drm_i915_private *dev_priv, u32 reg,
81 : u8 *data, u32 len)
82 : {
83 : u32 i, j;
84 :
85 0 : for (i = 0; i < len; i += 4) {
86 0 : u32 val = I915_READ(reg);
87 :
88 0 : for (j = 0; j < min_t(u32, len - i, 4); j++)
89 0 : *data++ = val >> 8 * j;
90 : }
91 0 : }
92 :
93 0 : static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
94 : const struct mipi_dsi_msg *msg)
95 : {
96 0 : struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
97 0 : struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
98 0 : struct drm_i915_private *dev_priv = dev->dev_private;
99 0 : enum port port = intel_dsi_host->port;
100 0 : struct mipi_dsi_packet packet;
101 : ssize_t ret;
102 : const u8 *header, *data;
103 : u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
104 :
105 0 : ret = mipi_dsi_create_packet(&packet, msg);
106 0 : if (ret < 0)
107 0 : return ret;
108 :
109 0 : header = packet.header;
110 0 : data = packet.payload;
111 :
112 0 : if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
113 0 : data_reg = MIPI_LP_GEN_DATA(port);
114 : data_mask = LP_DATA_FIFO_FULL;
115 0 : ctrl_reg = MIPI_LP_GEN_CTRL(port);
116 : ctrl_mask = LP_CTRL_FIFO_FULL;
117 0 : } else {
118 0 : data_reg = MIPI_HS_GEN_DATA(port);
119 : data_mask = HS_DATA_FIFO_FULL;
120 0 : ctrl_reg = MIPI_HS_GEN_CTRL(port);
121 : ctrl_mask = HS_CTRL_FIFO_FULL;
122 : }
123 :
124 : /* note: this is never true for reads */
125 0 : if (packet.payload_length) {
126 :
127 0 : if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
128 0 : DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
129 :
130 0 : write_data(dev_priv, data_reg, packet.payload,
131 0 : packet.payload_length);
132 0 : }
133 :
134 0 : if (msg->rx_len) {
135 0 : I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
136 0 : }
137 :
138 0 : if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
139 0 : DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
140 0 : }
141 :
142 0 : I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
143 :
144 : /* ->rx_len is set only for reads */
145 0 : if (msg->rx_len) {
146 : data_mask = GEN_READ_DATA_AVAIL;
147 0 : if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
148 0 : DRM_ERROR("Timeout waiting for read data.\n");
149 :
150 0 : read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
151 0 : }
152 :
153 : /* XXX: fix for reads and writes */
154 0 : return 4 + packet.payload_length;
155 0 : }
156 :
157 0 : static int intel_dsi_host_attach(struct mipi_dsi_host *host,
158 : struct mipi_dsi_device *dsi)
159 : {
160 0 : return 0;
161 : }
162 :
163 0 : static int intel_dsi_host_detach(struct mipi_dsi_host *host,
164 : struct mipi_dsi_device *dsi)
165 : {
166 0 : return 0;
167 : }
168 :
169 : static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
170 : .attach = intel_dsi_host_attach,
171 : .detach = intel_dsi_host_detach,
172 : .transfer = intel_dsi_host_transfer,
173 : };
174 :
175 0 : static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
176 : enum port port)
177 : {
178 : struct intel_dsi_host *host;
179 : struct mipi_dsi_device *device;
180 :
181 0 : host = kzalloc(sizeof(*host), GFP_KERNEL);
182 0 : if (!host)
183 0 : return NULL;
184 :
185 0 : host->base.ops = &intel_dsi_host_ops;
186 0 : host->intel_dsi = intel_dsi;
187 0 : host->port = port;
188 :
189 : /*
190 : * We should call mipi_dsi_host_register(&host->base) here, but we don't
191 : * have a host->dev, and we don't have OF stuff either. So just use the
192 : * dsi framework as a library and hope for the best. Create the dsi
193 : * devices by ourselves here too. Need to be careful though, because we
194 : * don't initialize any of the driver model devices here.
195 : */
196 0 : device = kzalloc(sizeof(*device), GFP_KERNEL);
197 0 : if (!device) {
198 0 : kfree(host);
199 0 : return NULL;
200 : }
201 :
202 0 : device->host = &host->base;
203 0 : host->device = device;
204 :
205 0 : return host;
206 0 : }
207 :
208 : /*
209 : * send a video mode command
210 : *
211 : * XXX: commands with data in MIPI_DPI_DATA?
212 : */
213 0 : static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
214 : enum port port)
215 : {
216 0 : struct drm_encoder *encoder = &intel_dsi->base.base;
217 0 : struct drm_device *dev = encoder->dev;
218 0 : struct drm_i915_private *dev_priv = dev->dev_private;
219 : u32 mask;
220 :
221 : /* XXX: pipe, hs */
222 0 : if (hs)
223 0 : cmd &= ~DPI_LP_MODE;
224 : else
225 0 : cmd |= DPI_LP_MODE;
226 :
227 : /* clear bit */
228 0 : I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
229 :
230 : /* XXX: old code skips write if control unchanged */
231 0 : if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
232 0 : DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
233 :
234 0 : I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
235 :
236 : mask = SPL_PKT_SENT_INTERRUPT;
237 0 : if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
238 0 : DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
239 :
240 0 : return 0;
241 : }
242 :
243 0 : static void band_gap_reset(struct drm_i915_private *dev_priv)
244 : {
245 0 : mutex_lock(&dev_priv->sb_lock);
246 :
247 0 : vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
248 0 : vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
249 0 : vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
250 0 : udelay(150);
251 0 : vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
252 0 : vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
253 :
254 0 : mutex_unlock(&dev_priv->sb_lock);
255 0 : }
256 :
257 0 : static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
258 : {
259 0 : return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
260 : }
261 :
262 0 : static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
263 : {
264 0 : return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
265 : }
266 :
267 0 : static bool intel_dsi_compute_config(struct intel_encoder *encoder,
268 : struct intel_crtc_state *config)
269 : {
270 0 : struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
271 : base);
272 0 : struct intel_connector *intel_connector = intel_dsi->attached_connector;
273 0 : struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
274 0 : struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
275 :
276 : DRM_DEBUG_KMS("\n");
277 :
278 0 : if (fixed_mode)
279 0 : intel_fixed_panel_mode(fixed_mode, adjusted_mode);
280 :
281 : /* DSI uses short packets for sync events, so clear mode flags for DSI */
282 0 : adjusted_mode->flags = 0;
283 :
284 0 : return true;
285 : }
286 :
287 0 : static void bxt_dsi_device_ready(struct intel_encoder *encoder)
288 : {
289 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
290 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
291 : enum port port;
292 : u32 val;
293 :
294 : DRM_DEBUG_KMS("\n");
295 :
296 : /* Exit Low power state in 4 steps*/
297 0 : for_each_dsi_port(port, intel_dsi->ports) {
298 :
299 : /* 1. Enable MIPI PHY transparent latch */
300 0 : val = I915_READ(BXT_MIPI_PORT_CTRL(port));
301 0 : I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
302 0 : usleep_range(2000, 2500);
303 :
304 : /* 2. Enter ULPS */
305 0 : val = I915_READ(MIPI_DEVICE_READY(port));
306 0 : val &= ~ULPS_STATE_MASK;
307 0 : val |= (ULPS_STATE_ENTER | DEVICE_READY);
308 0 : I915_WRITE(MIPI_DEVICE_READY(port), val);
309 0 : usleep_range(2, 3);
310 :
311 : /* 3. Exit ULPS */
312 0 : val = I915_READ(MIPI_DEVICE_READY(port));
313 0 : val &= ~ULPS_STATE_MASK;
314 0 : val |= (ULPS_STATE_EXIT | DEVICE_READY);
315 0 : I915_WRITE(MIPI_DEVICE_READY(port), val);
316 0 : usleep_range(1000, 1500);
317 :
318 : /* Clear ULPS and set device ready */
319 0 : val = I915_READ(MIPI_DEVICE_READY(port));
320 0 : val &= ~ULPS_STATE_MASK;
321 0 : val |= DEVICE_READY;
322 0 : I915_WRITE(MIPI_DEVICE_READY(port), val);
323 0 : }
324 0 : }
325 :
326 0 : static void vlv_dsi_device_ready(struct intel_encoder *encoder)
327 : {
328 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
329 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
330 : enum port port;
331 : u32 val;
332 :
333 : DRM_DEBUG_KMS("\n");
334 :
335 0 : mutex_lock(&dev_priv->sb_lock);
336 : /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
337 : * needed everytime after power gate */
338 0 : vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
339 0 : mutex_unlock(&dev_priv->sb_lock);
340 :
341 : /* bandgap reset is needed after everytime we do power gate */
342 0 : band_gap_reset(dev_priv);
343 :
344 0 : for_each_dsi_port(port, intel_dsi->ports) {
345 :
346 0 : I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
347 0 : usleep_range(2500, 3000);
348 :
349 : /* Enable MIPI PHY transparent latch
350 : * Common bit for both MIPI Port A & MIPI Port C
351 : * No similar bit in MIPI Port C reg
352 : */
353 0 : val = I915_READ(MIPI_PORT_CTRL(PORT_A));
354 0 : I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
355 0 : usleep_range(1000, 1500);
356 :
357 0 : I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
358 0 : usleep_range(2500, 3000);
359 :
360 0 : I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
361 0 : usleep_range(2500, 3000);
362 0 : }
363 0 : }
364 :
365 0 : static void intel_dsi_device_ready(struct intel_encoder *encoder)
366 : {
367 0 : struct drm_device *dev = encoder->base.dev;
368 :
369 0 : if (IS_VALLEYVIEW(dev))
370 0 : vlv_dsi_device_ready(encoder);
371 0 : else if (IS_BROXTON(dev))
372 0 : bxt_dsi_device_ready(encoder);
373 0 : }
374 :
375 0 : static void intel_dsi_port_enable(struct intel_encoder *encoder)
376 : {
377 0 : struct drm_device *dev = encoder->base.dev;
378 0 : struct drm_i915_private *dev_priv = dev->dev_private;
379 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
380 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
381 : enum port port;
382 : u32 temp;
383 : u32 port_ctrl;
384 :
385 0 : if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
386 0 : temp = I915_READ(VLV_CHICKEN_3);
387 0 : temp &= ~PIXEL_OVERLAP_CNT_MASK |
388 0 : intel_dsi->pixel_overlap <<
389 : PIXEL_OVERLAP_CNT_SHIFT;
390 0 : I915_WRITE(VLV_CHICKEN_3, temp);
391 0 : }
392 :
393 0 : for_each_dsi_port(port, intel_dsi->ports) {
394 0 : port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
395 0 : MIPI_PORT_CTRL(port);
396 :
397 0 : temp = I915_READ(port_ctrl);
398 :
399 0 : temp &= ~LANE_CONFIGURATION_MASK;
400 0 : temp &= ~DUAL_LINK_MODE_MASK;
401 :
402 0 : if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) {
403 0 : temp |= (intel_dsi->dual_link - 1)
404 0 : << DUAL_LINK_MODE_SHIFT;
405 0 : temp |= intel_crtc->pipe ?
406 : LANE_CONFIGURATION_DUAL_LINK_B :
407 : LANE_CONFIGURATION_DUAL_LINK_A;
408 0 : }
409 : /* assert ip_tg_enable signal */
410 0 : I915_WRITE(port_ctrl, temp | DPI_ENABLE);
411 0 : POSTING_READ(port_ctrl);
412 0 : }
413 0 : }
414 :
415 0 : static void intel_dsi_port_disable(struct intel_encoder *encoder)
416 : {
417 0 : struct drm_device *dev = encoder->base.dev;
418 0 : struct drm_i915_private *dev_priv = dev->dev_private;
419 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
420 : enum port port;
421 : u32 temp;
422 : u32 port_ctrl;
423 :
424 0 : for_each_dsi_port(port, intel_dsi->ports) {
425 : /* de-assert ip_tg_enable signal */
426 0 : port_ctrl = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
427 0 : MIPI_PORT_CTRL(port);
428 0 : temp = I915_READ(port_ctrl);
429 0 : I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
430 0 : POSTING_READ(port_ctrl);
431 0 : }
432 0 : }
433 :
434 0 : static void intel_dsi_enable(struct intel_encoder *encoder)
435 : {
436 0 : struct drm_device *dev = encoder->base.dev;
437 0 : struct drm_i915_private *dev_priv = dev->dev_private;
438 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
439 : enum port port;
440 :
441 : DRM_DEBUG_KMS("\n");
442 :
443 0 : if (is_cmd_mode(intel_dsi)) {
444 0 : for_each_dsi_port(port, intel_dsi->ports)
445 0 : I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
446 : } else {
447 0 : drm_msleep(20); /* XXX */
448 0 : for_each_dsi_port(port, intel_dsi->ports)
449 0 : dpi_send_cmd(intel_dsi, TURN_ON, false, port);
450 0 : drm_msleep(100);
451 :
452 0 : drm_panel_enable(intel_dsi->panel);
453 :
454 0 : for_each_dsi_port(port, intel_dsi->ports)
455 0 : wait_for_dsi_fifo_empty(intel_dsi, port);
456 :
457 0 : intel_dsi_port_enable(encoder);
458 : }
459 :
460 0 : intel_panel_enable_backlight(intel_dsi->attached_connector);
461 0 : }
462 :
463 0 : static void intel_dsi_pre_enable(struct intel_encoder *encoder)
464 : {
465 0 : struct drm_device *dev = encoder->base.dev;
466 0 : struct drm_i915_private *dev_priv = dev->dev_private;
467 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
468 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
469 0 : enum pipe pipe = intel_crtc->pipe;
470 : enum port port;
471 : u32 tmp;
472 :
473 : DRM_DEBUG_KMS("\n");
474 :
475 : #ifdef notyet
476 : /* Panel Enable over CRC PMIC */
477 : if (intel_dsi->gpio_panel)
478 : gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
479 : #endif
480 :
481 0 : drm_msleep(intel_dsi->panel_on_delay);
482 :
483 0 : if (IS_VALLEYVIEW(dev)) {
484 : /*
485 : * Disable DPOunit clock gating, can stall pipe
486 : * and we need DPLL REFA always enabled
487 : */
488 0 : tmp = I915_READ(DPLL(pipe));
489 0 : tmp |= DPLL_REF_CLK_ENABLE_VLV;
490 0 : I915_WRITE(DPLL(pipe), tmp);
491 :
492 : /* update the hw state for DPLL */
493 0 : intel_crtc->config->dpll_hw_state.dpll =
494 : DPLL_INTEGRATED_REF_CLK_VLV |
495 : DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
496 :
497 0 : tmp = I915_READ(DSPCLK_GATE_D);
498 0 : tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
499 0 : I915_WRITE(DSPCLK_GATE_D, tmp);
500 0 : }
501 :
502 : /* put device in ready state */
503 0 : intel_dsi_device_ready(encoder);
504 :
505 0 : drm_panel_prepare(intel_dsi->panel);
506 :
507 0 : for_each_dsi_port(port, intel_dsi->ports)
508 0 : wait_for_dsi_fifo_empty(intel_dsi, port);
509 :
510 : /* Enable port in pre-enable phase itself because as per hw team
511 : * recommendation, port should be enabled befor plane & pipe */
512 0 : intel_dsi_enable(encoder);
513 0 : }
514 :
515 0 : static void intel_dsi_enable_nop(struct intel_encoder *encoder)
516 : {
517 : DRM_DEBUG_KMS("\n");
518 :
519 : /* for DSI port enable has to be done before pipe
520 : * and plane enable, so port enable is done in
521 : * pre_enable phase itself unlike other encoders
522 : */
523 0 : }
524 :
525 0 : static void intel_dsi_pre_disable(struct intel_encoder *encoder)
526 : {
527 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
528 : enum port port;
529 :
530 : DRM_DEBUG_KMS("\n");
531 :
532 0 : intel_panel_disable_backlight(intel_dsi->attached_connector);
533 :
534 0 : if (is_vid_mode(intel_dsi)) {
535 : /* Send Shutdown command to the panel in LP mode */
536 0 : for_each_dsi_port(port, intel_dsi->ports)
537 0 : dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
538 0 : drm_msleep(10);
539 0 : }
540 0 : }
541 :
542 0 : static void intel_dsi_disable(struct intel_encoder *encoder)
543 : {
544 0 : struct drm_device *dev = encoder->base.dev;
545 0 : struct drm_i915_private *dev_priv = dev->dev_private;
546 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
547 : enum port port;
548 : u32 temp;
549 :
550 : DRM_DEBUG_KMS("\n");
551 :
552 0 : if (is_vid_mode(intel_dsi)) {
553 0 : for_each_dsi_port(port, intel_dsi->ports)
554 0 : wait_for_dsi_fifo_empty(intel_dsi, port);
555 :
556 0 : intel_dsi_port_disable(encoder);
557 0 : drm_msleep(2);
558 0 : }
559 :
560 0 : for_each_dsi_port(port, intel_dsi->ports) {
561 : /* Panel commands can be sent when clock is in LP11 */
562 0 : I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
563 :
564 0 : intel_dsi_reset_clocks(encoder, port);
565 0 : I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
566 :
567 0 : temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
568 0 : temp &= ~VID_MODE_FORMAT_MASK;
569 0 : I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
570 :
571 0 : I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
572 0 : }
573 : /* if disable packets are sent before sending shutdown packet then in
574 : * some next enable sequence send turn on packet error is observed */
575 0 : drm_panel_disable(intel_dsi->panel);
576 :
577 0 : for_each_dsi_port(port, intel_dsi->ports)
578 0 : wait_for_dsi_fifo_empty(intel_dsi, port);
579 0 : }
580 :
581 0 : static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
582 : {
583 0 : struct drm_device *dev = encoder->base.dev;
584 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
585 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
586 : enum port port;
587 : u32 val;
588 : u32 port_ctrl = 0;
589 :
590 : DRM_DEBUG_KMS("\n");
591 0 : for_each_dsi_port(port, intel_dsi->ports) {
592 :
593 0 : I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
594 : ULPS_STATE_ENTER);
595 0 : usleep_range(2000, 2500);
596 :
597 0 : I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
598 : ULPS_STATE_EXIT);
599 0 : usleep_range(2000, 2500);
600 :
601 0 : I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
602 : ULPS_STATE_ENTER);
603 0 : usleep_range(2000, 2500);
604 :
605 0 : if (IS_BROXTON(dev))
606 0 : port_ctrl = BXT_MIPI_PORT_CTRL(port);
607 0 : else if (IS_VALLEYVIEW(dev))
608 : /* Common bit for both MIPI Port A & MIPI Port C */
609 0 : port_ctrl = MIPI_PORT_CTRL(PORT_A);
610 :
611 : /* Wait till Clock lanes are in LP-00 state for MIPI Port A
612 : * only. MIPI Port C has no similar bit for checking
613 : */
614 0 : if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
615 : == 0x00000), 30))
616 0 : DRM_ERROR("DSI LP not going Low\n");
617 :
618 : /* Disable MIPI PHY transparent latch */
619 0 : val = I915_READ(port_ctrl);
620 0 : I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
621 0 : usleep_range(1000, 1500);
622 :
623 0 : I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
624 0 : usleep_range(2000, 2500);
625 0 : }
626 :
627 0 : intel_disable_dsi_pll(encoder);
628 0 : }
629 :
630 0 : static void intel_dsi_post_disable(struct intel_encoder *encoder)
631 : {
632 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
633 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
634 : u32 val;
635 :
636 : DRM_DEBUG_KMS("\n");
637 :
638 0 : intel_dsi_disable(encoder);
639 :
640 0 : intel_dsi_clear_device_ready(encoder);
641 :
642 0 : val = I915_READ(DSPCLK_GATE_D);
643 0 : val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
644 0 : I915_WRITE(DSPCLK_GATE_D, val);
645 :
646 0 : drm_panel_unprepare(intel_dsi->panel);
647 :
648 0 : drm_msleep(intel_dsi->panel_off_delay);
649 0 : drm_msleep(intel_dsi->panel_pwr_cycle_delay);
650 :
651 : #ifdef notyet
652 : /* Panel Disable over CRC PMIC */
653 : if (intel_dsi->gpio_panel)
654 : gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
655 : #endif
656 0 : }
657 :
658 0 : static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
659 : enum pipe *pipe)
660 : {
661 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
662 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
663 0 : struct drm_device *dev = encoder->base.dev;
664 : enum intel_display_power_domain power_domain;
665 : u32 dpi_enabled, func, ctrl_reg;
666 : enum port port;
667 :
668 : DRM_DEBUG_KMS("\n");
669 :
670 0 : power_domain = intel_display_port_power_domain(encoder);
671 0 : if (!intel_display_power_is_enabled(dev_priv, power_domain))
672 0 : return false;
673 :
674 : /* XXX: this only works for one DSI output */
675 0 : for_each_dsi_port(port, intel_dsi->ports) {
676 0 : func = I915_READ(MIPI_DSI_FUNC_PRG(port));
677 0 : ctrl_reg = IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) :
678 0 : MIPI_PORT_CTRL(port);
679 0 : dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
680 :
681 : /* Due to some hardware limitations on BYT, MIPI Port C DPI
682 : * Enable bit does not get set. To check whether DSI Port C
683 : * was enabled in BIOS, check the Pipe B enable bit
684 : */
685 0 : if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
686 0 : (port == PORT_C))
687 0 : dpi_enabled = I915_READ(PIPECONF(PIPE_B)) &
688 : PIPECONF_ENABLE;
689 :
690 0 : if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) {
691 0 : if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) {
692 0 : *pipe = port == PORT_A ? PIPE_A : PIPE_B;
693 0 : return true;
694 : }
695 : }
696 : }
697 :
698 0 : return false;
699 0 : }
700 :
701 0 : static void intel_dsi_get_config(struct intel_encoder *encoder,
702 : struct intel_crtc_state *pipe_config)
703 : {
704 : u32 pclk = 0;
705 : DRM_DEBUG_KMS("\n");
706 :
707 : /*
708 : * DPLL_MD is not used in case of DSI, reading will get some default value
709 : * set dpll_md = 0
710 : */
711 0 : pipe_config->dpll_hw_state.dpll_md = 0;
712 :
713 0 : if (IS_BROXTON(encoder->base.dev))
714 0 : pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
715 0 : else if (IS_VALLEYVIEW(encoder->base.dev))
716 0 : pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
717 :
718 0 : if (!pclk)
719 0 : return;
720 :
721 0 : pipe_config->base.adjusted_mode.crtc_clock = pclk;
722 0 : pipe_config->port_clock = pclk;
723 0 : }
724 :
725 : static enum drm_mode_status
726 0 : intel_dsi_mode_valid(struct drm_connector *connector,
727 : struct drm_display_mode *mode)
728 : {
729 0 : struct intel_connector *intel_connector = to_intel_connector(connector);
730 0 : struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
731 0 : int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
732 :
733 : DRM_DEBUG_KMS("\n");
734 :
735 0 : if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
736 : DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
737 0 : return MODE_NO_DBLESCAN;
738 : }
739 :
740 0 : if (fixed_mode) {
741 0 : if (mode->hdisplay > fixed_mode->hdisplay)
742 0 : return MODE_PANEL;
743 0 : if (mode->vdisplay > fixed_mode->vdisplay)
744 0 : return MODE_PANEL;
745 0 : if (fixed_mode->clock > max_dotclk)
746 0 : return MODE_CLOCK_HIGH;
747 : }
748 :
749 0 : return MODE_OK;
750 0 : }
751 :
752 : /* return txclkesc cycles in terms of divider and duration in us */
753 0 : static u16 txclkesc(u32 divider, unsigned int us)
754 : {
755 0 : switch (divider) {
756 : case ESCAPE_CLOCK_DIVIDER_1:
757 : default:
758 0 : return 20 * us;
759 : case ESCAPE_CLOCK_DIVIDER_2:
760 0 : return 10 * us;
761 : case ESCAPE_CLOCK_DIVIDER_4:
762 0 : return 5 * us;
763 : }
764 0 : }
765 :
766 : /* return pixels in terms of txbyteclkhs */
767 0 : static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
768 : u16 burst_mode_ratio)
769 : {
770 0 : return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
771 : 8 * 100), lane_count);
772 : }
773 :
774 0 : static void set_dsi_timings(struct drm_encoder *encoder,
775 : const struct drm_display_mode *adjusted_mode)
776 : {
777 0 : struct drm_device *dev = encoder->dev;
778 0 : struct drm_i915_private *dev_priv = dev->dev_private;
779 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
780 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
781 : enum port port;
782 0 : unsigned int bpp = intel_crtc->config->pipe_bpp;
783 0 : unsigned int lane_count = intel_dsi->lane_count;
784 :
785 : u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
786 :
787 0 : hactive = adjusted_mode->crtc_hdisplay;
788 0 : hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
789 0 : hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
790 0 : hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
791 :
792 0 : if (intel_dsi->dual_link) {
793 0 : hactive /= 2;
794 0 : if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
795 0 : hactive += intel_dsi->pixel_overlap;
796 0 : hfp /= 2;
797 0 : hsync /= 2;
798 0 : hbp /= 2;
799 0 : }
800 :
801 0 : vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
802 0 : vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
803 0 : vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
804 :
805 : /* horizontal values are in terms of high speed byte clock */
806 0 : hactive = txbyteclkhs(hactive, bpp, lane_count,
807 0 : intel_dsi->burst_mode_ratio);
808 0 : hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
809 0 : hsync = txbyteclkhs(hsync, bpp, lane_count,
810 0 : intel_dsi->burst_mode_ratio);
811 0 : hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
812 :
813 0 : for_each_dsi_port(port, intel_dsi->ports) {
814 0 : if (IS_BROXTON(dev)) {
815 : /*
816 : * Program hdisplay and vdisplay on MIPI transcoder.
817 : * This is different from calculated hactive and
818 : * vactive, as they are calculated per channel basis,
819 : * whereas these values should be based on resolution.
820 : */
821 0 : I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
822 : adjusted_mode->crtc_hdisplay);
823 0 : I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
824 : adjusted_mode->crtc_vdisplay);
825 0 : I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
826 : adjusted_mode->crtc_vtotal);
827 0 : }
828 :
829 0 : I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
830 0 : I915_WRITE(MIPI_HFP_COUNT(port), hfp);
831 :
832 : /* meaningful for video mode non-burst sync pulse mode only,
833 : * can be zero for non-burst sync events and burst modes */
834 0 : I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
835 0 : I915_WRITE(MIPI_HBP_COUNT(port), hbp);
836 :
837 : /* vertical values are in terms of lines */
838 0 : I915_WRITE(MIPI_VFP_COUNT(port), vfp);
839 0 : I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
840 0 : I915_WRITE(MIPI_VBP_COUNT(port), vbp);
841 0 : }
842 0 : }
843 :
844 0 : static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
845 : {
846 0 : struct drm_encoder *encoder = &intel_encoder->base;
847 0 : struct drm_device *dev = encoder->dev;
848 0 : struct drm_i915_private *dev_priv = dev->dev_private;
849 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
850 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
851 0 : const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
852 : enum port port;
853 0 : unsigned int bpp = intel_crtc->config->pipe_bpp;
854 : u32 val, tmp;
855 : u16 mode_hdisplay;
856 :
857 : DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
858 :
859 0 : mode_hdisplay = adjusted_mode->crtc_hdisplay;
860 :
861 0 : if (intel_dsi->dual_link) {
862 0 : mode_hdisplay /= 2;
863 0 : if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
864 0 : mode_hdisplay += intel_dsi->pixel_overlap;
865 : }
866 :
867 0 : for_each_dsi_port(port, intel_dsi->ports) {
868 0 : if (IS_VALLEYVIEW(dev)) {
869 : /*
870 : * escape clock divider, 20MHz, shared for A and C.
871 : * device ready must be off when doing this! txclkesc?
872 : */
873 0 : tmp = I915_READ(MIPI_CTRL(PORT_A));
874 0 : tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
875 0 : I915_WRITE(MIPI_CTRL(PORT_A), tmp |
876 : ESCAPE_CLOCK_DIVIDER_1);
877 :
878 : /* read request priority is per pipe */
879 0 : tmp = I915_READ(MIPI_CTRL(port));
880 0 : tmp &= ~READ_REQUEST_PRIORITY_MASK;
881 0 : I915_WRITE(MIPI_CTRL(port), tmp |
882 : READ_REQUEST_PRIORITY_HIGH);
883 0 : } else if (IS_BROXTON(dev)) {
884 : /*
885 : * FIXME:
886 : * BXT can connect any PIPE to any MIPI port.
887 : * Select the pipe based on the MIPI port read from
888 : * VBT for now. Pick PIPE A for MIPI port A and C
889 : * for port C.
890 : */
891 0 : tmp = I915_READ(MIPI_CTRL(port));
892 0 : tmp &= ~BXT_PIPE_SELECT_MASK;
893 :
894 0 : if (port == PORT_A)
895 0 : tmp |= BXT_PIPE_SELECT_A;
896 0 : else if (port == PORT_C)
897 0 : tmp |= BXT_PIPE_SELECT_C;
898 :
899 0 : I915_WRITE(MIPI_CTRL(port), tmp);
900 0 : }
901 :
902 : /* XXX: why here, why like this? handling in irq handler?! */
903 0 : I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
904 0 : I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
905 :
906 0 : I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
907 :
908 0 : I915_WRITE(MIPI_DPI_RESOLUTION(port),
909 : adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
910 : mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
911 0 : }
912 :
913 0 : set_dsi_timings(encoder, adjusted_mode);
914 :
915 0 : val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
916 0 : if (is_cmd_mode(intel_dsi)) {
917 0 : val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
918 0 : val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
919 0 : } else {
920 0 : val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
921 :
922 : /* XXX: cross-check bpp vs. pixel format? */
923 0 : val |= intel_dsi->pixel_format;
924 : }
925 :
926 : tmp = 0;
927 0 : if (intel_dsi->eotp_pkt == 0)
928 0 : tmp |= EOT_DISABLE;
929 0 : if (intel_dsi->clock_stop)
930 0 : tmp |= CLOCKSTOP;
931 :
932 0 : for_each_dsi_port(port, intel_dsi->ports) {
933 0 : I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
934 :
935 : /* timeouts for recovery. one frame IIUC. if counter expires,
936 : * EOT and stop state. */
937 :
938 : /*
939 : * In burst mode, value greater than one DPI line Time in byte
940 : * clock (txbyteclkhs) To timeout this timer 1+ of the above
941 : * said value is recommended.
942 : *
943 : * In non-burst mode, Value greater than one DPI frame time in
944 : * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
945 : * said value is recommended.
946 : *
947 : * In DBI only mode, value greater than one DBI frame time in
948 : * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
949 : * said value is recommended.
950 : */
951 :
952 0 : if (is_vid_mode(intel_dsi) &&
953 0 : intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
954 0 : I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
955 : txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
956 : intel_dsi->lane_count,
957 : intel_dsi->burst_mode_ratio) + 1);
958 0 : } else {
959 0 : I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
960 : txbyteclkhs(adjusted_mode->crtc_vtotal *
961 : adjusted_mode->crtc_htotal,
962 : bpp, intel_dsi->lane_count,
963 : intel_dsi->burst_mode_ratio) + 1);
964 : }
965 0 : I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
966 0 : I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
967 : intel_dsi->turn_arnd_val);
968 0 : I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
969 : intel_dsi->rst_timer_val);
970 :
971 : /* dphy stuff */
972 :
973 : /* in terms of low power clock */
974 0 : I915_WRITE(MIPI_INIT_COUNT(port),
975 : txclkesc(intel_dsi->escape_clk_div, 100));
976 :
977 0 : if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
978 : /*
979 : * BXT spec says write MIPI_INIT_COUNT for
980 : * both the ports, even if only one is
981 : * getting used. So write the other port
982 : * if not in dual link mode.
983 : */
984 0 : I915_WRITE(MIPI_INIT_COUNT(port ==
985 : PORT_A ? PORT_C : PORT_A),
986 : intel_dsi->init_count);
987 0 : }
988 :
989 : /* recovery disables */
990 0 : I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
991 :
992 : /* in terms of low power clock */
993 0 : I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
994 :
995 : /* in terms of txbyteclkhs. actual high to low switch +
996 : * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
997 : *
998 : * XXX: write MIPI_STOP_STATE_STALL?
999 : */
1000 0 : I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1001 : intel_dsi->hs_to_lp_count);
1002 :
1003 : /* XXX: low power clock equivalence in terms of byte clock.
1004 : * the number of byte clocks occupied in one low power clock.
1005 : * based on txbyteclkhs and txclkesc.
1006 : * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1007 : * ) / 105.???
1008 : */
1009 0 : I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1010 :
1011 : /* the bw essential for transmitting 16 long packets containing
1012 : * 252 bytes meant for dcs write memory command is programmed in
1013 : * this register in terms of byte clocks. based on dsi transfer
1014 : * rate and the number of lanes configured the time taken to
1015 : * transmit 16 long packets in a dsi stream varies. */
1016 0 : I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1017 :
1018 0 : I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1019 : intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1020 : intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1021 :
1022 0 : if (is_vid_mode(intel_dsi))
1023 : /* Some panels might have resolution which is not a
1024 : * multiple of 64 like 1366 x 768. Enable RANDOM
1025 : * resolution support for such panels by default */
1026 0 : I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1027 : intel_dsi->video_frmt_cfg_bits |
1028 : intel_dsi->video_mode_format |
1029 : IP_TG_CONFIG |
1030 : RANDOM_DPI_DISPLAY_RESOLUTION);
1031 : }
1032 0 : }
1033 :
1034 0 : static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
1035 : {
1036 : DRM_DEBUG_KMS("\n");
1037 :
1038 0 : intel_dsi_prepare(encoder);
1039 0 : intel_enable_dsi_pll(encoder);
1040 :
1041 0 : }
1042 :
1043 : static enum drm_connector_status
1044 0 : intel_dsi_detect(struct drm_connector *connector, bool force)
1045 : {
1046 0 : return connector_status_connected;
1047 : }
1048 :
1049 0 : static int intel_dsi_get_modes(struct drm_connector *connector)
1050 : {
1051 0 : struct intel_connector *intel_connector = to_intel_connector(connector);
1052 : struct drm_display_mode *mode;
1053 :
1054 : DRM_DEBUG_KMS("\n");
1055 :
1056 0 : if (!intel_connector->panel.fixed_mode) {
1057 : DRM_DEBUG_KMS("no fixed mode\n");
1058 0 : return 0;
1059 : }
1060 :
1061 0 : mode = drm_mode_duplicate(connector->dev,
1062 : intel_connector->panel.fixed_mode);
1063 0 : if (!mode) {
1064 : DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1065 0 : return 0;
1066 : }
1067 :
1068 0 : drm_mode_probed_add(connector, mode);
1069 0 : return 1;
1070 0 : }
1071 :
1072 0 : static void intel_dsi_connector_destroy(struct drm_connector *connector)
1073 : {
1074 0 : struct intel_connector *intel_connector = to_intel_connector(connector);
1075 :
1076 : DRM_DEBUG_KMS("\n");
1077 0 : intel_panel_fini(&intel_connector->panel);
1078 0 : drm_connector_cleanup(connector);
1079 0 : kfree(connector);
1080 0 : }
1081 :
1082 0 : static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1083 : {
1084 0 : struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1085 :
1086 0 : if (intel_dsi->panel) {
1087 0 : drm_panel_detach(intel_dsi->panel);
1088 : /* XXX: Logically this call belongs in the panel driver. */
1089 0 : drm_panel_remove(intel_dsi->panel);
1090 0 : }
1091 :
1092 : #ifdef notyet
1093 : /* dispose of the gpios */
1094 : if (intel_dsi->gpio_panel)
1095 : gpiod_put(intel_dsi->gpio_panel);
1096 : #endif
1097 :
1098 0 : intel_encoder_destroy(encoder);
1099 0 : }
1100 :
1101 : static const struct drm_encoder_funcs intel_dsi_funcs = {
1102 : .destroy = intel_dsi_encoder_destroy,
1103 : };
1104 :
1105 : static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1106 : .get_modes = intel_dsi_get_modes,
1107 : .mode_valid = intel_dsi_mode_valid,
1108 : .best_encoder = intel_best_encoder,
1109 : };
1110 :
1111 : static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1112 : .dpms = drm_atomic_helper_connector_dpms,
1113 : .detect = intel_dsi_detect,
1114 : .destroy = intel_dsi_connector_destroy,
1115 : .fill_modes = drm_helper_probe_single_connector_modes,
1116 : .atomic_get_property = intel_connector_atomic_get_property,
1117 : .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1118 : .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1119 : };
1120 :
1121 0 : void intel_dsi_init(struct drm_device *dev)
1122 : {
1123 : struct intel_dsi *intel_dsi;
1124 : struct intel_encoder *intel_encoder;
1125 : struct drm_encoder *encoder;
1126 : struct intel_connector *intel_connector;
1127 : struct drm_connector *connector;
1128 : struct drm_display_mode *scan, *fixed_mode = NULL;
1129 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1130 : enum port port;
1131 : unsigned int i;
1132 :
1133 : DRM_DEBUG_KMS("\n");
1134 :
1135 : /* There is no detection method for MIPI so rely on VBT */
1136 0 : if (!dev_priv->vbt.has_mipi)
1137 0 : return;
1138 :
1139 0 : if (IS_VALLEYVIEW(dev)) {
1140 0 : dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1141 : } else {
1142 0 : DRM_ERROR("Unsupported Mipi device to reg base");
1143 0 : return;
1144 : }
1145 :
1146 0 : intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1147 0 : if (!intel_dsi)
1148 0 : return;
1149 :
1150 0 : intel_connector = intel_connector_alloc();
1151 0 : if (!intel_connector) {
1152 0 : kfree(intel_dsi);
1153 0 : return;
1154 : }
1155 :
1156 0 : intel_encoder = &intel_dsi->base;
1157 0 : encoder = &intel_encoder->base;
1158 0 : intel_dsi->attached_connector = intel_connector;
1159 :
1160 0 : connector = &intel_connector->base;
1161 :
1162 0 : drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
1163 :
1164 : /* XXX: very likely not all of these are needed */
1165 0 : intel_encoder->compute_config = intel_dsi_compute_config;
1166 0 : intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
1167 0 : intel_encoder->pre_enable = intel_dsi_pre_enable;
1168 0 : intel_encoder->enable = intel_dsi_enable_nop;
1169 0 : intel_encoder->disable = intel_dsi_pre_disable;
1170 0 : intel_encoder->post_disable = intel_dsi_post_disable;
1171 0 : intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1172 0 : intel_encoder->get_config = intel_dsi_get_config;
1173 :
1174 0 : intel_connector->get_hw_state = intel_connector_get_hw_state;
1175 0 : intel_connector->unregister = intel_connector_unregister;
1176 :
1177 : /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
1178 0 : if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
1179 0 : intel_encoder->crtc_mask = (1 << PIPE_A);
1180 0 : intel_dsi->ports = (1 << PORT_A);
1181 0 : } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
1182 0 : intel_encoder->crtc_mask = (1 << PIPE_B);
1183 0 : intel_dsi->ports = (1 << PORT_C);
1184 0 : }
1185 :
1186 0 : if (dev_priv->vbt.dsi.config->dual_link)
1187 0 : intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
1188 :
1189 : /* Create a DSI host (and a device) for each port. */
1190 0 : for_each_dsi_port(port, intel_dsi->ports) {
1191 : struct intel_dsi_host *host;
1192 :
1193 0 : host = intel_dsi_host_init(intel_dsi, port);
1194 0 : if (!host)
1195 0 : goto err;
1196 :
1197 0 : intel_dsi->dsi_hosts[port] = host;
1198 0 : }
1199 :
1200 0 : for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1201 0 : intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1202 0 : intel_dsi_drivers[i].panel_id);
1203 0 : if (intel_dsi->panel)
1204 : break;
1205 : }
1206 :
1207 0 : if (!intel_dsi->panel) {
1208 : DRM_DEBUG_KMS("no device found\n");
1209 : goto err;
1210 : }
1211 :
1212 : #ifdef notyet
1213 : /*
1214 : * In case of BYT with CRC PMIC, we need to use GPIO for
1215 : * Panel control.
1216 : */
1217 : if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) {
1218 : intel_dsi->gpio_panel =
1219 : gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1220 :
1221 : if (IS_ERR(intel_dsi->gpio_panel)) {
1222 : DRM_ERROR("Failed to own gpio for panel control\n");
1223 : intel_dsi->gpio_panel = NULL;
1224 : }
1225 : }
1226 : #endif
1227 :
1228 0 : intel_encoder->type = INTEL_OUTPUT_DSI;
1229 0 : intel_encoder->cloneable = 0;
1230 0 : drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1231 : DRM_MODE_CONNECTOR_DSI);
1232 :
1233 0 : drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1234 :
1235 0 : connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1236 0 : connector->interlace_allowed = false;
1237 0 : connector->doublescan_allowed = false;
1238 :
1239 0 : intel_connector_attach_encoder(intel_connector, intel_encoder);
1240 :
1241 0 : drm_connector_register(connector);
1242 :
1243 0 : drm_panel_attach(intel_dsi->panel, connector);
1244 :
1245 0 : mutex_lock(&dev->mode_config.mutex);
1246 0 : drm_panel_get_modes(intel_dsi->panel);
1247 0 : list_for_each_entry(scan, &connector->probed_modes, head) {
1248 0 : if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1249 0 : fixed_mode = drm_mode_duplicate(dev, scan);
1250 0 : break;
1251 : }
1252 : }
1253 0 : mutex_unlock(&dev->mode_config.mutex);
1254 :
1255 0 : if (!fixed_mode) {
1256 : DRM_DEBUG_KMS("no fixed mode\n");
1257 : goto err;
1258 : }
1259 :
1260 0 : intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1261 0 : intel_panel_setup_backlight(connector, INVALID_PIPE);
1262 :
1263 0 : return;
1264 :
1265 : err:
1266 0 : drm_encoder_cleanup(&intel_encoder->base);
1267 0 : kfree(intel_dsi);
1268 0 : kfree(intel_connector);
1269 0 : }
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