Line data Source code
1 : /*
2 : * Copyright © 2014 Intel Corporation
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice (including the next
12 : * paragraph) shall be included in all copies or substantial portions of the
13 : * Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 : * IN THE SOFTWARE.
22 : *
23 : * Authors:
24 : * Vinit Azad <vinit.azad@intel.com>
25 : * Ben Widawsky <ben@bwidawsk.net>
26 : * Dave Gordon <david.s.gordon@intel.com>
27 : * Alex Dai <yu.dai@intel.com>
28 : */
29 : #ifdef __linux__
30 : #include <linux/firmware.h>
31 : #endif
32 : #include "i915_drv.h"
33 : #include "intel_guc.h"
34 :
35 : #ifdef notyet
36 :
37 : /**
38 : * DOC: GuC
39 : *
40 : * intel_guc:
41 : * Top level structure of guc. It handles firmware loading and manages client
42 : * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
43 : * ExecList submission.
44 : *
45 : * Firmware versioning:
46 : * The firmware build process will generate a version header file with major and
47 : * minor version defined. The versions are built into CSS header of firmware.
48 : * i915 kernel driver set the minimal firmware version required per platform.
49 : * The firmware installation package will install (symbolic link) proper version
50 : * of firmware.
51 : *
52 : * GuC address space:
53 : * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
54 : * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
55 : * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
56 : * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
57 : *
58 : * Firmware log:
59 : * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
60 : * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
61 : * i915_guc_load_status will print out firmware loading status and scratch
62 : * registers value.
63 : *
64 : */
65 :
66 : #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
67 : MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
68 :
69 : #define I915_KBL_GUC_UCODE "i915/kbl_guc_ver9_14.bin"
70 : MODULE_FIRMWARE(I915_KBL_GUC_UCODE);
71 :
72 : /* User-friendly representation of an enum */
73 : const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
74 : {
75 : switch (status) {
76 : case GUC_FIRMWARE_FAIL:
77 : return "FAIL";
78 : case GUC_FIRMWARE_NONE:
79 : return "NONE";
80 : case GUC_FIRMWARE_PENDING:
81 : return "PENDING";
82 : case GUC_FIRMWARE_SUCCESS:
83 : return "SUCCESS";
84 : default:
85 : return "UNKNOWN!";
86 : }
87 : };
88 :
89 : static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
90 : {
91 : struct intel_engine_cs *ring;
92 : int i, irqs;
93 :
94 : /* tell all command streamers NOT to forward interrupts and vblank to GuC */
95 : irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
96 : irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
97 : for_each_ring(ring, dev_priv, i)
98 : I915_WRITE(RING_MODE_GEN7(ring), irqs);
99 :
100 : /* route all GT interrupts to the host */
101 : I915_WRITE(GUC_BCS_RCS_IER, 0);
102 : I915_WRITE(GUC_VCS2_VCS1_IER, 0);
103 : I915_WRITE(GUC_WD_VECS_IER, 0);
104 : }
105 :
106 : static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
107 : {
108 : struct intel_engine_cs *ring;
109 : int i, irqs;
110 :
111 : /* tell all command streamers to forward interrupts and vblank to GuC */
112 : irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
113 : irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
114 : for_each_ring(ring, dev_priv, i)
115 : I915_WRITE(RING_MODE_GEN7(ring), irqs);
116 :
117 : /* route USER_INTERRUPT to Host, all others are sent to GuC. */
118 : irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
119 : GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
120 : /* These three registers have the same bit definitions */
121 : I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
122 : I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
123 : I915_WRITE(GUC_WD_VECS_IER, ~irqs);
124 : }
125 :
126 : static u32 get_gttype(struct drm_i915_private *dev_priv)
127 : {
128 : /* XXX: GT type based on PCI device ID? field seems unused by fw */
129 : return 0;
130 : }
131 :
132 : static u32 get_core_family(struct drm_i915_private *dev_priv)
133 : {
134 : switch (INTEL_INFO(dev_priv)->gen) {
135 : case 9:
136 : return GFXCORE_FAMILY_GEN9;
137 :
138 : default:
139 : DRM_ERROR("GUC: unsupported core family\n");
140 : return GFXCORE_FAMILY_UNKNOWN;
141 : }
142 : }
143 :
144 : static void set_guc_init_params(struct drm_i915_private *dev_priv)
145 : {
146 : struct intel_guc *guc = &dev_priv->guc;
147 : u32 params[GUC_CTL_MAX_DWORDS];
148 : int i;
149 :
150 : memset(¶ms, 0, sizeof(params));
151 :
152 : params[GUC_CTL_DEVICE_INFO] |=
153 : (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
154 : (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
155 :
156 : /*
157 : * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
158 : * second. This ARAR is calculated by:
159 : * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
160 : */
161 : params[GUC_CTL_ARAT_HIGH] = 0;
162 : params[GUC_CTL_ARAT_LOW] = 100000000;
163 :
164 : params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
165 :
166 : params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
167 : GUC_CTL_VCS2_ENABLED;
168 :
169 : if (i915.guc_log_level >= 0) {
170 : params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
171 : params[GUC_CTL_DEBUG] =
172 : i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
173 : }
174 :
175 : /* If GuC submission is enabled, set up additional parameters here */
176 : if (i915.enable_guc_submission) {
177 : u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
178 : u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
179 :
180 : pgs >>= PAGE_SHIFT;
181 : params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
182 : (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
183 :
184 : params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
185 :
186 : /* Unmask this bit to enable the GuC's internal scheduler */
187 : params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
188 : }
189 :
190 : I915_WRITE(SOFT_SCRATCH(0), 0);
191 :
192 : for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
193 : I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
194 : }
195 :
196 : /*
197 : * Read the GuC status register (GUC_STATUS) and store it in the
198 : * specified location; then return a boolean indicating whether
199 : * the value matches either of two values representing completion
200 : * of the GuC boot process.
201 : *
202 : * This is used for polling the GuC status in a wait_for_atomic()
203 : * loop below.
204 : */
205 : static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
206 : u32 *status)
207 : {
208 : u32 val = I915_READ(GUC_STATUS);
209 : u32 uk_val = val & GS_UKERNEL_MASK;
210 : *status = val;
211 : return (uk_val == GS_UKERNEL_READY ||
212 : ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
213 : }
214 :
215 : /*
216 : * Transfer the firmware image to RAM for execution by the microcontroller.
217 : *
218 : * GuC Firmware layout:
219 : * +-------------------------------+ ----
220 : * | CSS header | 128B
221 : * | contains major/minor version |
222 : * +-------------------------------+ ----
223 : * | uCode |
224 : * +-------------------------------+ ----
225 : * | RSA signature | 256B
226 : * +-------------------------------+ ----
227 : *
228 : * Architecturally, the DMA engine is bidirectional, and can potentially even
229 : * transfer between GTT locations. This functionality is left out of the API
230 : * for now as there is no need for it.
231 : *
232 : * Note that GuC needs the CSS header plus uKernel code to be copied by the
233 : * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
234 : */
235 :
236 : #define UOS_CSS_HEADER_OFFSET 0
237 : #define UOS_VER_MINOR_OFFSET 0x44
238 : #define UOS_VER_MAJOR_OFFSET 0x46
239 : #define UOS_CSS_HEADER_SIZE 0x80
240 : #define UOS_RSA_SIG_SIZE 0x100
241 :
242 : static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
243 : {
244 : struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
245 : struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
246 : unsigned long offset;
247 : struct sg_table *sg = fw_obj->pages;
248 : u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)];
249 : int i, ret = 0;
250 :
251 : /* uCode size, also is where RSA signature starts */
252 : offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE;
253 : I915_WRITE(DMA_COPY_SIZE, ucode_size);
254 :
255 : /* Copy RSA signature from the fw image to HW for verification */
256 : sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
257 : for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
258 : I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
259 :
260 : /* Set the source address for the new blob */
261 : offset = i915_gem_obj_ggtt_offset(fw_obj);
262 : I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
263 : I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
264 :
265 : /*
266 : * Set the DMA destination. Current uCode expects the code to be
267 : * loaded at 8k; locations below this are used for the stack.
268 : */
269 : I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
270 : I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
271 :
272 : /* Finally start the DMA */
273 : I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
274 :
275 : /*
276 : * Spin-wait for the DMA to complete & the GuC to start up.
277 : * NB: Docs recommend not using the interrupt for completion.
278 : * Measurements indicate this should take no more than 20ms, so a
279 : * timeout here indicates that the GuC has failed and is unusable.
280 : * (Higher levels of the driver will attempt to fall back to
281 : * execlist mode if this happens.)
282 : */
283 : ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
284 :
285 : DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
286 : I915_READ(DMA_CTRL), status);
287 :
288 : if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
289 : DRM_ERROR("GuC firmware signature verification failed\n");
290 : ret = -ENOEXEC;
291 : }
292 :
293 : DRM_DEBUG_DRIVER("returning %d\n", ret);
294 :
295 : return ret;
296 : }
297 :
298 : /*
299 : * Load the GuC firmware blob into the MinuteIA.
300 : */
301 : static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
302 : {
303 : struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
304 : struct drm_device *dev = dev_priv->dev;
305 : int ret;
306 :
307 : ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
308 : if (ret) {
309 : DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
310 : return ret;
311 : }
312 :
313 : ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
314 : if (ret) {
315 : DRM_DEBUG_DRIVER("pin failed %d\n", ret);
316 : return ret;
317 : }
318 :
319 : /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
320 : I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
321 :
322 : intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
323 :
324 : /* init WOPCM */
325 : I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
326 : I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
327 :
328 : /* Enable MIA caching. GuC clock gating is disabled. */
329 : I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
330 :
331 : /* WaDisableMinuteIaClockGating:skl,bxt */
332 : if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
333 : IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
334 : I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
335 : ~GUC_ENABLE_MIA_CLOCK_GATING));
336 : }
337 :
338 : /* WaC6DisallowByGfxPause*/
339 : I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
340 :
341 : if (IS_BROXTON(dev))
342 : I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
343 : else
344 : I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
345 :
346 : if (IS_GEN9(dev)) {
347 : /* DOP Clock Gating Enable for GuC clocks */
348 : I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
349 : I915_READ(GEN7_MISCCPCTL)));
350 :
351 : /* allows for 5us before GT can go to RC6 */
352 : I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
353 : }
354 :
355 : set_guc_init_params(dev_priv);
356 :
357 : ret = guc_ucode_xfer_dma(dev_priv);
358 :
359 : intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
360 :
361 : /*
362 : * We keep the object pages for reuse during resume. But we can unpin it
363 : * now that DMA has completed, so it doesn't continue to take up space.
364 : */
365 : i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
366 :
367 : return ret;
368 : }
369 :
370 : /**
371 : * intel_guc_ucode_load() - load GuC uCode into the device
372 : * @dev: drm device
373 : *
374 : * Called from gem_init_hw() during driver loading and also after a GPU reset.
375 : *
376 : * The firmware image should have already been fetched into memory by the
377 : * earlier call to intel_guc_ucode_init(), so here we need only check that
378 : * is succeeded, and then transfer the image to the h/w.
379 : *
380 : * Return: non-zero code on error
381 : */
382 : int intel_guc_ucode_load(struct drm_device *dev)
383 : {
384 : struct drm_i915_private *dev_priv = dev->dev_private;
385 : struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
386 : int err = 0;
387 :
388 : DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
389 : intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
390 : intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
391 :
392 : direct_interrupts_to_host(dev_priv);
393 :
394 : if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
395 : return 0;
396 :
397 : if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
398 : guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
399 : return -ENOEXEC;
400 :
401 : guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
402 :
403 : DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
404 : intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
405 :
406 : switch (guc_fw->guc_fw_fetch_status) {
407 : case GUC_FIRMWARE_FAIL:
408 : /* something went wrong :( */
409 : err = -EIO;
410 : goto fail;
411 :
412 : case GUC_FIRMWARE_NONE:
413 : case GUC_FIRMWARE_PENDING:
414 : default:
415 : /* "can't happen" */
416 : WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
417 : guc_fw->guc_fw_path,
418 : intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
419 : guc_fw->guc_fw_fetch_status);
420 : err = -ENXIO;
421 : goto fail;
422 :
423 : case GUC_FIRMWARE_SUCCESS:
424 : break;
425 : }
426 :
427 : err = i915_guc_submission_init(dev);
428 : if (err)
429 : goto fail;
430 :
431 : err = guc_ucode_xfer(dev_priv);
432 : if (err)
433 : goto fail;
434 :
435 : guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
436 :
437 : DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
438 : intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
439 : intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
440 :
441 : if (i915.enable_guc_submission) {
442 : /* The execbuf_client will be recreated. Release it first. */
443 : i915_guc_submission_disable(dev);
444 :
445 : err = i915_guc_submission_enable(dev);
446 : if (err)
447 : goto fail;
448 : direct_interrupts_to_guc(dev_priv);
449 : }
450 :
451 : return 0;
452 :
453 : fail:
454 : if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
455 : guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
456 :
457 : direct_interrupts_to_host(dev_priv);
458 : i915_guc_submission_disable(dev);
459 :
460 : return err;
461 : }
462 :
463 : static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
464 : {
465 : struct drm_i915_gem_object *obj;
466 : const struct firmware *fw;
467 : const u8 *css_header;
468 : const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE;
469 : const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE
470 : - 0x8000; /* 32k reserved (8K stack + 24k context) */
471 : int err;
472 :
473 : DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
474 : intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
475 :
476 : err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
477 : if (err)
478 : goto fail;
479 : if (!fw)
480 : goto fail;
481 :
482 : DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
483 : guc_fw->guc_fw_path, fw);
484 : DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n",
485 : fw->size, minsize, maxsize);
486 :
487 : /* Check the size of the blob befoe examining buffer contents */
488 : if (fw->size < minsize || fw->size > maxsize)
489 : goto fail;
490 :
491 : /*
492 : * The GuC firmware image has the version number embedded at a well-known
493 : * offset within the firmware blob; note that major / minor version are
494 : * TWO bytes each (i.e. u16), although all pointers and offsets are defined
495 : * in terms of bytes (u8).
496 : */
497 : css_header = fw->data + UOS_CSS_HEADER_OFFSET;
498 : guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET);
499 : guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET);
500 :
501 : if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
502 : guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
503 : DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
504 : guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
505 : guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
506 : err = -ENOEXEC;
507 : goto fail;
508 : }
509 :
510 : DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
511 : guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
512 : guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
513 :
514 : mutex_lock(&dev->struct_mutex);
515 : obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
516 : mutex_unlock(&dev->struct_mutex);
517 : if (IS_ERR_OR_NULL(obj)) {
518 : err = obj ? PTR_ERR(obj) : -ENOMEM;
519 : goto fail;
520 : }
521 :
522 : guc_fw->guc_fw_obj = obj;
523 : guc_fw->guc_fw_size = fw->size;
524 :
525 : DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
526 : guc_fw->guc_fw_obj);
527 :
528 : release_firmware(fw);
529 : guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
530 : return;
531 :
532 : fail:
533 : DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
534 : err, fw, guc_fw->guc_fw_obj);
535 : DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
536 : guc_fw->guc_fw_path, err);
537 :
538 : obj = guc_fw->guc_fw_obj;
539 : if (obj)
540 : drm_gem_object_unreference(&obj->base);
541 : guc_fw->guc_fw_obj = NULL;
542 :
543 : release_firmware(fw); /* OK even if fw is NULL */
544 : guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
545 : }
546 :
547 : /**
548 : * intel_guc_ucode_init() - define parameters and fetch firmware
549 : * @dev: drm device
550 : *
551 : * Called early during driver load, but after GEM is initialised.
552 : *
553 : * The firmware will be transferred to the GuC's memory later,
554 : * when intel_guc_ucode_load() is called.
555 : */
556 : void intel_guc_ucode_init(struct drm_device *dev)
557 : {
558 : struct drm_i915_private *dev_priv = dev->dev_private;
559 : struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
560 : const char *fw_path;
561 :
562 : if (!HAS_GUC_SCHED(dev))
563 : i915.enable_guc_submission = false;
564 :
565 : if (!HAS_GUC_UCODE(dev)) {
566 : fw_path = NULL;
567 : } else if (IS_SKYLAKE(dev)) {
568 : fw_path = I915_SKL_GUC_UCODE;
569 : guc_fw->guc_fw_major_wanted = 4;
570 : guc_fw->guc_fw_minor_wanted = 3;
571 : } else if (IS_KABYLAKE(dev)) {
572 : fw_path = I915_KBL_GUC_UCODE;
573 : guc_fw->guc_fw_major_wanted = 9;
574 : guc_fw->guc_fw_minor_wanted = 14;
575 : } else {
576 : i915.enable_guc_submission = false;
577 : fw_path = ""; /* unknown device */
578 : }
579 :
580 : guc_fw->guc_dev = dev;
581 : guc_fw->guc_fw_path = fw_path;
582 : guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
583 : guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
584 :
585 : if (fw_path == NULL)
586 : return;
587 :
588 : if (*fw_path == '\0') {
589 : DRM_ERROR("No GuC firmware known for this platform\n");
590 : guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
591 : return;
592 : }
593 :
594 : guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
595 : DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
596 : guc_fw_fetch(dev, guc_fw);
597 : /* status must now be FAIL or SUCCESS */
598 : }
599 :
600 : /**
601 : * intel_guc_ucode_fini() - clean up all allocated resources
602 : * @dev: drm device
603 : */
604 : void intel_guc_ucode_fini(struct drm_device *dev)
605 : {
606 : struct drm_i915_private *dev_priv = dev->dev_private;
607 : struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
608 :
609 : direct_interrupts_to_host(dev_priv);
610 : i915_guc_submission_fini(dev);
611 :
612 : mutex_lock(&dev->struct_mutex);
613 : if (guc_fw->guc_fw_obj)
614 : drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
615 : guc_fw->guc_fw_obj = NULL;
616 : mutex_unlock(&dev->struct_mutex);
617 :
618 : guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
619 : }
620 :
621 : #else
622 :
623 : int
624 0 : intel_guc_ucode_load(struct drm_device *dev)
625 : {
626 0 : return -ENOEXEC;
627 : }
628 :
629 : void
630 0 : intel_guc_ucode_init(struct drm_device *dev)
631 : {
632 0 : }
633 :
634 : void
635 0 : intel_guc_ucode_fini(struct drm_device *dev)
636 : {
637 0 : }
638 :
639 : #endif
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