Line data Source code
1 : /*
2 : * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 : * Copyright © 2006-2009 Intel Corporation
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice (including the next
13 : * paragraph) shall be included in all copies or substantial portions of the
14 : * Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 : * DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors:
25 : * Eric Anholt <eric@anholt.net>
26 : * Jesse Barnes <jesse.barnes@intel.com>
27 : */
28 :
29 : #ifdef __linux__
30 : #include <linux/i2c.h>
31 : #include <linux/slab.h>
32 : #include <linux/delay.h>
33 : #include <linux/hdmi.h>
34 : #else
35 : #include <dev/pci/drm/linux_hdmi.h>
36 : #endif
37 : #include <dev/pci/drm/drmP.h>
38 : #include <dev/pci/drm/drm_atomic_helper.h>
39 : #include <dev/pci/drm/drm_crtc.h>
40 : #include <dev/pci/drm/drm_edid.h>
41 : #include "intel_drv.h"
42 : #include <dev/pci/drm/i915_drm.h>
43 : #include "i915_drv.h"
44 :
45 0 : static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
46 : {
47 0 : return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
48 : }
49 :
50 : static void
51 0 : assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
52 : {
53 0 : struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
54 0 : struct drm_i915_private *dev_priv = dev->dev_private;
55 : uint32_t enabled_bits;
56 :
57 0 : enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
58 :
59 0 : WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
60 : "HDMI port enabled, expecting disabled\n");
61 0 : }
62 :
63 0 : struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
64 : {
65 : struct intel_digital_port *intel_dig_port =
66 0 : container_of(encoder, struct intel_digital_port, base.base);
67 0 : return &intel_dig_port->hdmi;
68 : }
69 :
70 0 : static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
71 : {
72 0 : return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
73 : }
74 :
75 0 : static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
76 : {
77 0 : switch (type) {
78 : case HDMI_INFOFRAME_TYPE_AVI:
79 0 : return VIDEO_DIP_SELECT_AVI;
80 : case HDMI_INFOFRAME_TYPE_SPD:
81 0 : return VIDEO_DIP_SELECT_SPD;
82 : case HDMI_INFOFRAME_TYPE_VENDOR:
83 0 : return VIDEO_DIP_SELECT_VENDOR;
84 : default:
85 : DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
86 0 : return 0;
87 : }
88 0 : }
89 :
90 0 : static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
91 : {
92 0 : switch (type) {
93 : case HDMI_INFOFRAME_TYPE_AVI:
94 0 : return VIDEO_DIP_ENABLE_AVI;
95 : case HDMI_INFOFRAME_TYPE_SPD:
96 0 : return VIDEO_DIP_ENABLE_SPD;
97 : case HDMI_INFOFRAME_TYPE_VENDOR:
98 0 : return VIDEO_DIP_ENABLE_VENDOR;
99 : default:
100 : DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
101 0 : return 0;
102 : }
103 0 : }
104 :
105 0 : static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
106 : {
107 0 : switch (type) {
108 : case HDMI_INFOFRAME_TYPE_AVI:
109 0 : return VIDEO_DIP_ENABLE_AVI_HSW;
110 : case HDMI_INFOFRAME_TYPE_SPD:
111 0 : return VIDEO_DIP_ENABLE_SPD_HSW;
112 : case HDMI_INFOFRAME_TYPE_VENDOR:
113 0 : return VIDEO_DIP_ENABLE_VS_HSW;
114 : default:
115 : DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
116 0 : return 0;
117 : }
118 0 : }
119 :
120 0 : static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
121 : enum transcoder cpu_transcoder,
122 : enum hdmi_infoframe_type type,
123 : int i)
124 : {
125 0 : switch (type) {
126 : case HDMI_INFOFRAME_TYPE_AVI:
127 0 : return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
128 : case HDMI_INFOFRAME_TYPE_SPD:
129 0 : return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
130 : case HDMI_INFOFRAME_TYPE_VENDOR:
131 0 : return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
132 : default:
133 : DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
134 0 : return 0;
135 : }
136 0 : }
137 :
138 0 : static void g4x_write_infoframe(struct drm_encoder *encoder,
139 : enum hdmi_infoframe_type type,
140 : const void *frame, ssize_t len)
141 : {
142 0 : const uint32_t *data = frame;
143 0 : struct drm_device *dev = encoder->dev;
144 0 : struct drm_i915_private *dev_priv = dev->dev_private;
145 0 : u32 val = I915_READ(VIDEO_DIP_CTL);
146 : int i;
147 :
148 0 : WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
149 :
150 0 : val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
151 0 : val |= g4x_infoframe_index(type);
152 :
153 0 : val &= ~g4x_infoframe_enable(type);
154 :
155 0 : I915_WRITE(VIDEO_DIP_CTL, val);
156 :
157 0 : mmiowb();
158 0 : for (i = 0; i < len; i += 4) {
159 0 : I915_WRITE(VIDEO_DIP_DATA, *data);
160 0 : data++;
161 : }
162 : /* Write every possible data byte to force correct ECC calculation. */
163 0 : for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
164 0 : I915_WRITE(VIDEO_DIP_DATA, 0);
165 0 : mmiowb();
166 :
167 0 : val |= g4x_infoframe_enable(type);
168 0 : val &= ~VIDEO_DIP_FREQ_MASK;
169 0 : val |= VIDEO_DIP_FREQ_VSYNC;
170 :
171 0 : I915_WRITE(VIDEO_DIP_CTL, val);
172 0 : POSTING_READ(VIDEO_DIP_CTL);
173 0 : }
174 :
175 0 : static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
176 : {
177 0 : struct drm_device *dev = encoder->dev;
178 0 : struct drm_i915_private *dev_priv = dev->dev_private;
179 0 : struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
180 0 : u32 val = I915_READ(VIDEO_DIP_CTL);
181 :
182 0 : if ((val & VIDEO_DIP_ENABLE) == 0)
183 0 : return false;
184 :
185 0 : if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
186 0 : return false;
187 :
188 0 : return val & (VIDEO_DIP_ENABLE_AVI |
189 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
190 0 : }
191 :
192 0 : static void ibx_write_infoframe(struct drm_encoder *encoder,
193 : enum hdmi_infoframe_type type,
194 : const void *frame, ssize_t len)
195 : {
196 0 : const uint32_t *data = frame;
197 0 : struct drm_device *dev = encoder->dev;
198 0 : struct drm_i915_private *dev_priv = dev->dev_private;
199 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
200 0 : int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
201 0 : u32 val = I915_READ(reg);
202 :
203 0 : WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
204 :
205 0 : val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
206 0 : val |= g4x_infoframe_index(type);
207 :
208 0 : val &= ~g4x_infoframe_enable(type);
209 :
210 0 : I915_WRITE(reg, val);
211 :
212 0 : mmiowb();
213 0 : for (i = 0; i < len; i += 4) {
214 0 : I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
215 0 : data++;
216 : }
217 : /* Write every possible data byte to force correct ECC calculation. */
218 0 : for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
219 0 : I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
220 0 : mmiowb();
221 :
222 0 : val |= g4x_infoframe_enable(type);
223 0 : val &= ~VIDEO_DIP_FREQ_MASK;
224 0 : val |= VIDEO_DIP_FREQ_VSYNC;
225 :
226 0 : I915_WRITE(reg, val);
227 0 : POSTING_READ(reg);
228 0 : }
229 :
230 0 : static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
231 : {
232 0 : struct drm_device *dev = encoder->dev;
233 0 : struct drm_i915_private *dev_priv = dev->dev_private;
234 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
235 0 : struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
236 0 : int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
237 0 : u32 val = I915_READ(reg);
238 :
239 0 : if ((val & VIDEO_DIP_ENABLE) == 0)
240 0 : return false;
241 :
242 0 : if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
243 0 : return false;
244 :
245 0 : return val & (VIDEO_DIP_ENABLE_AVI |
246 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
247 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
248 0 : }
249 :
250 0 : static void cpt_write_infoframe(struct drm_encoder *encoder,
251 : enum hdmi_infoframe_type type,
252 : const void *frame, ssize_t len)
253 : {
254 0 : const uint32_t *data = frame;
255 0 : struct drm_device *dev = encoder->dev;
256 0 : struct drm_i915_private *dev_priv = dev->dev_private;
257 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
258 0 : int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
259 0 : u32 val = I915_READ(reg);
260 :
261 0 : WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
262 :
263 0 : val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
264 0 : val |= g4x_infoframe_index(type);
265 :
266 : /* The DIP control register spec says that we need to update the AVI
267 : * infoframe without clearing its enable bit */
268 0 : if (type != HDMI_INFOFRAME_TYPE_AVI)
269 0 : val &= ~g4x_infoframe_enable(type);
270 :
271 0 : I915_WRITE(reg, val);
272 :
273 0 : mmiowb();
274 0 : for (i = 0; i < len; i += 4) {
275 0 : I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
276 0 : data++;
277 : }
278 : /* Write every possible data byte to force correct ECC calculation. */
279 0 : for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
280 0 : I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
281 0 : mmiowb();
282 :
283 0 : val |= g4x_infoframe_enable(type);
284 0 : val &= ~VIDEO_DIP_FREQ_MASK;
285 0 : val |= VIDEO_DIP_FREQ_VSYNC;
286 :
287 0 : I915_WRITE(reg, val);
288 0 : POSTING_READ(reg);
289 0 : }
290 :
291 0 : static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
292 : {
293 0 : struct drm_device *dev = encoder->dev;
294 0 : struct drm_i915_private *dev_priv = dev->dev_private;
295 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
296 0 : int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
297 0 : u32 val = I915_READ(reg);
298 :
299 0 : if ((val & VIDEO_DIP_ENABLE) == 0)
300 0 : return false;
301 :
302 0 : return val & (VIDEO_DIP_ENABLE_AVI |
303 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
304 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
305 0 : }
306 :
307 0 : static void vlv_write_infoframe(struct drm_encoder *encoder,
308 : enum hdmi_infoframe_type type,
309 : const void *frame, ssize_t len)
310 : {
311 0 : const uint32_t *data = frame;
312 0 : struct drm_device *dev = encoder->dev;
313 0 : struct drm_i915_private *dev_priv = dev->dev_private;
314 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
315 0 : int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
316 0 : u32 val = I915_READ(reg);
317 :
318 0 : WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
319 :
320 0 : val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
321 0 : val |= g4x_infoframe_index(type);
322 :
323 0 : val &= ~g4x_infoframe_enable(type);
324 :
325 0 : I915_WRITE(reg, val);
326 :
327 0 : mmiowb();
328 0 : for (i = 0; i < len; i += 4) {
329 0 : I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
330 0 : data++;
331 : }
332 : /* Write every possible data byte to force correct ECC calculation. */
333 0 : for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
334 0 : I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
335 0 : mmiowb();
336 :
337 0 : val |= g4x_infoframe_enable(type);
338 0 : val &= ~VIDEO_DIP_FREQ_MASK;
339 0 : val |= VIDEO_DIP_FREQ_VSYNC;
340 :
341 0 : I915_WRITE(reg, val);
342 0 : POSTING_READ(reg);
343 0 : }
344 :
345 0 : static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
346 : {
347 0 : struct drm_device *dev = encoder->dev;
348 0 : struct drm_i915_private *dev_priv = dev->dev_private;
349 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
350 0 : struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
351 0 : int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
352 0 : u32 val = I915_READ(reg);
353 :
354 0 : if ((val & VIDEO_DIP_ENABLE) == 0)
355 0 : return false;
356 :
357 0 : if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
358 0 : return false;
359 :
360 0 : return val & (VIDEO_DIP_ENABLE_AVI |
361 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
362 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
363 0 : }
364 :
365 0 : static void hsw_write_infoframe(struct drm_encoder *encoder,
366 : enum hdmi_infoframe_type type,
367 : const void *frame, ssize_t len)
368 : {
369 0 : const uint32_t *data = frame;
370 0 : struct drm_device *dev = encoder->dev;
371 0 : struct drm_i915_private *dev_priv = dev->dev_private;
372 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
373 0 : enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
374 0 : u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
375 : u32 data_reg;
376 : int i;
377 0 : u32 val = I915_READ(ctl_reg);
378 :
379 0 : data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
380 0 : if (data_reg == 0)
381 0 : return;
382 :
383 0 : val &= ~hsw_infoframe_enable(type);
384 0 : I915_WRITE(ctl_reg, val);
385 :
386 0 : mmiowb();
387 0 : for (i = 0; i < len; i += 4) {
388 0 : I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
389 : type, i >> 2), *data);
390 0 : data++;
391 : }
392 : /* Write every possible data byte to force correct ECC calculation. */
393 0 : for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
394 0 : I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
395 : type, i >> 2), 0);
396 0 : mmiowb();
397 :
398 0 : val |= hsw_infoframe_enable(type);
399 0 : I915_WRITE(ctl_reg, val);
400 0 : POSTING_READ(ctl_reg);
401 0 : }
402 :
403 0 : static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
404 : {
405 0 : struct drm_device *dev = encoder->dev;
406 0 : struct drm_i915_private *dev_priv = dev->dev_private;
407 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
408 0 : u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
409 0 : u32 val = I915_READ(ctl_reg);
410 :
411 0 : return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
412 : VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
413 : VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
414 : }
415 :
416 : /*
417 : * The data we write to the DIP data buffer registers is 1 byte bigger than the
418 : * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
419 : * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
420 : * used for both technologies.
421 : *
422 : * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
423 : * DW1: DB3 | DB2 | DB1 | DB0
424 : * DW2: DB7 | DB6 | DB5 | DB4
425 : * DW3: ...
426 : *
427 : * (HB is Header Byte, DB is Data Byte)
428 : *
429 : * The hdmi pack() functions don't know about that hardware specific hole so we
430 : * trick them by giving an offset into the buffer and moving back the header
431 : * bytes by one.
432 : */
433 0 : static void intel_write_infoframe(struct drm_encoder *encoder,
434 : union hdmi_infoframe *frame)
435 : {
436 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
437 0 : uint8_t buffer[VIDEO_DIP_DATA_SIZE];
438 : ssize_t len;
439 :
440 : /* see comment above for the reason for this offset */
441 0 : len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
442 0 : if (len < 0)
443 0 : return;
444 :
445 : /* Insert the 'hole' (see big comment above) at position 3 */
446 0 : buffer[0] = buffer[1];
447 0 : buffer[1] = buffer[2];
448 0 : buffer[2] = buffer[3];
449 0 : buffer[3] = 0;
450 0 : len++;
451 :
452 0 : intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
453 0 : }
454 :
455 0 : static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
456 : const struct drm_display_mode *adjusted_mode)
457 : {
458 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
459 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
460 0 : union hdmi_infoframe frame;
461 : int ret;
462 :
463 0 : ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
464 : adjusted_mode);
465 0 : if (ret < 0) {
466 0 : DRM_ERROR("couldn't fill AVI infoframe\n");
467 0 : return;
468 : }
469 :
470 0 : if (intel_hdmi->rgb_quant_range_selectable) {
471 0 : if (intel_crtc->config->limited_color_range)
472 0 : frame.avi.quantization_range =
473 : HDMI_QUANTIZATION_RANGE_LIMITED;
474 : else
475 0 : frame.avi.quantization_range =
476 : HDMI_QUANTIZATION_RANGE_FULL;
477 : }
478 :
479 0 : intel_write_infoframe(encoder, &frame);
480 0 : }
481 :
482 0 : static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
483 : {
484 0 : union hdmi_infoframe frame;
485 : int ret;
486 :
487 0 : ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
488 0 : if (ret < 0) {
489 0 : DRM_ERROR("couldn't fill SPD infoframe\n");
490 0 : return;
491 : }
492 :
493 0 : frame.spd.sdi = HDMI_SPD_SDI_PC;
494 :
495 0 : intel_write_infoframe(encoder, &frame);
496 0 : }
497 :
498 : static void
499 0 : intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
500 : const struct drm_display_mode *adjusted_mode)
501 : {
502 0 : union hdmi_infoframe frame;
503 : int ret;
504 :
505 0 : ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
506 : adjusted_mode);
507 0 : if (ret < 0)
508 0 : return;
509 :
510 0 : intel_write_infoframe(encoder, &frame);
511 0 : }
512 :
513 0 : static void g4x_set_infoframes(struct drm_encoder *encoder,
514 : bool enable,
515 : const struct drm_display_mode *adjusted_mode)
516 : {
517 0 : struct drm_i915_private *dev_priv = encoder->dev->dev_private;
518 0 : struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
519 0 : struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
520 : u32 reg = VIDEO_DIP_CTL;
521 0 : u32 val = I915_READ(reg);
522 0 : u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
523 :
524 0 : assert_hdmi_port_disabled(intel_hdmi);
525 :
526 : /* If the registers were not initialized yet, they might be zeroes,
527 : * which means we're selecting the AVI DIP and we're setting its
528 : * frequency to once. This seems to really confuse the HW and make
529 : * things stop working (the register spec says the AVI always needs to
530 : * be sent every VSync). So here we avoid writing to the register more
531 : * than we need and also explicitly select the AVI DIP and explicitly
532 : * set its frequency to every VSync. Avoiding to write it twice seems to
533 : * be enough to solve the problem, but being defensive shouldn't hurt us
534 : * either. */
535 0 : val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
536 :
537 0 : if (!enable) {
538 0 : if (!(val & VIDEO_DIP_ENABLE))
539 0 : return;
540 0 : if (port != (val & VIDEO_DIP_PORT_MASK)) {
541 : DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
542 : (val & VIDEO_DIP_PORT_MASK) >> 29);
543 0 : return;
544 : }
545 0 : val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
546 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
547 0 : I915_WRITE(reg, val);
548 0 : POSTING_READ(reg);
549 0 : return;
550 : }
551 :
552 0 : if (port != (val & VIDEO_DIP_PORT_MASK)) {
553 0 : if (val & VIDEO_DIP_ENABLE) {
554 : DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
555 : (val & VIDEO_DIP_PORT_MASK) >> 29);
556 0 : return;
557 : }
558 0 : val &= ~VIDEO_DIP_PORT_MASK;
559 0 : val |= port;
560 0 : }
561 :
562 0 : val |= VIDEO_DIP_ENABLE;
563 0 : val &= ~(VIDEO_DIP_ENABLE_AVI |
564 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
565 :
566 0 : I915_WRITE(reg, val);
567 0 : POSTING_READ(reg);
568 :
569 0 : intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
570 0 : intel_hdmi_set_spd_infoframe(encoder);
571 0 : intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
572 0 : }
573 :
574 0 : static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
575 : {
576 0 : struct drm_device *dev = encoder->dev;
577 : struct drm_connector *connector;
578 :
579 0 : WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
580 :
581 : /*
582 : * HDMI cloning is only supported on g4x which doesn't
583 : * support deep color or GCP infoframes anyway so no
584 : * need to worry about multiple HDMI sinks here.
585 : */
586 0 : list_for_each_entry(connector, &dev->mode_config.connector_list, head)
587 0 : if (connector->encoder == encoder)
588 0 : return connector->display_info.bpc > 8;
589 :
590 0 : return false;
591 0 : }
592 :
593 : /*
594 : * Determine if default_phase=1 can be indicated in the GCP infoframe.
595 : *
596 : * From HDMI specification 1.4a:
597 : * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
598 : * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
599 : * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
600 : * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
601 : * phase of 0
602 : */
603 0 : static bool gcp_default_phase_possible(int pipe_bpp,
604 : const struct drm_display_mode *mode)
605 : {
606 : unsigned int pixels_per_group;
607 :
608 0 : switch (pipe_bpp) {
609 : case 30:
610 : /* 4 pixels in 5 clocks */
611 : pixels_per_group = 4;
612 0 : break;
613 : case 36:
614 : /* 2 pixels in 3 clocks */
615 : pixels_per_group = 2;
616 0 : break;
617 : case 48:
618 : /* 1 pixel in 2 clocks */
619 : pixels_per_group = 1;
620 0 : break;
621 : default:
622 : /* phase information not relevant for 8bpc */
623 0 : return false;
624 : }
625 :
626 0 : return mode->crtc_hdisplay % pixels_per_group == 0 &&
627 0 : mode->crtc_htotal % pixels_per_group == 0 &&
628 0 : mode->crtc_hblank_start % pixels_per_group == 0 &&
629 0 : mode->crtc_hblank_end % pixels_per_group == 0 &&
630 0 : mode->crtc_hsync_start % pixels_per_group == 0 &&
631 0 : mode->crtc_hsync_end % pixels_per_group == 0 &&
632 0 : ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
633 0 : mode->crtc_htotal/2 % pixels_per_group == 0);
634 0 : }
635 :
636 0 : static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
637 : {
638 0 : struct drm_i915_private *dev_priv = encoder->dev->dev_private;
639 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
640 : u32 reg, val = 0;
641 :
642 0 : if (HAS_DDI(dev_priv))
643 0 : reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
644 0 : else if (IS_VALLEYVIEW(dev_priv))
645 0 : reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
646 0 : else if (HAS_PCH_SPLIT(dev_priv->dev))
647 0 : reg = TVIDEO_DIP_GCP(crtc->pipe);
648 : else
649 0 : return false;
650 :
651 : /* Indicate color depth whenever the sink supports deep color */
652 0 : if (hdmi_sink_is_deep_color(encoder))
653 0 : val |= GCP_COLOR_INDICATION;
654 :
655 : /* Enable default_phase whenever the display mode is suitably aligned */
656 0 : if (gcp_default_phase_possible(crtc->config->pipe_bpp,
657 0 : &crtc->config->base.adjusted_mode))
658 0 : val |= GCP_DEFAULT_PHASE_ENABLE;
659 :
660 0 : I915_WRITE(reg, val);
661 :
662 0 : return val != 0;
663 0 : }
664 :
665 0 : static void ibx_set_infoframes(struct drm_encoder *encoder,
666 : bool enable,
667 : const struct drm_display_mode *adjusted_mode)
668 : {
669 0 : struct drm_i915_private *dev_priv = encoder->dev->dev_private;
670 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
671 0 : struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
672 0 : struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
673 0 : u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
674 0 : u32 val = I915_READ(reg);
675 0 : u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
676 :
677 0 : assert_hdmi_port_disabled(intel_hdmi);
678 :
679 : /* See the big comment in g4x_set_infoframes() */
680 0 : val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
681 :
682 0 : if (!enable) {
683 0 : if (!(val & VIDEO_DIP_ENABLE))
684 0 : return;
685 0 : val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
686 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
687 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
688 0 : I915_WRITE(reg, val);
689 0 : POSTING_READ(reg);
690 0 : return;
691 : }
692 :
693 0 : if (port != (val & VIDEO_DIP_PORT_MASK)) {
694 0 : WARN(val & VIDEO_DIP_ENABLE,
695 : "DIP already enabled on port %c\n",
696 : (val & VIDEO_DIP_PORT_MASK) >> 29);
697 0 : val &= ~VIDEO_DIP_PORT_MASK;
698 0 : val |= port;
699 0 : }
700 :
701 0 : val |= VIDEO_DIP_ENABLE;
702 0 : val &= ~(VIDEO_DIP_ENABLE_AVI |
703 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
704 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
705 :
706 0 : if (intel_hdmi_set_gcp_infoframe(encoder))
707 0 : val |= VIDEO_DIP_ENABLE_GCP;
708 :
709 0 : I915_WRITE(reg, val);
710 0 : POSTING_READ(reg);
711 :
712 0 : intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
713 0 : intel_hdmi_set_spd_infoframe(encoder);
714 0 : intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
715 0 : }
716 :
717 0 : static void cpt_set_infoframes(struct drm_encoder *encoder,
718 : bool enable,
719 : const struct drm_display_mode *adjusted_mode)
720 : {
721 0 : struct drm_i915_private *dev_priv = encoder->dev->dev_private;
722 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
723 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
724 0 : u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
725 0 : u32 val = I915_READ(reg);
726 :
727 0 : assert_hdmi_port_disabled(intel_hdmi);
728 :
729 : /* See the big comment in g4x_set_infoframes() */
730 0 : val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
731 :
732 0 : if (!enable) {
733 0 : if (!(val & VIDEO_DIP_ENABLE))
734 0 : return;
735 0 : val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
736 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
737 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
738 0 : I915_WRITE(reg, val);
739 0 : POSTING_READ(reg);
740 0 : return;
741 : }
742 :
743 : /* Set both together, unset both together: see the spec. */
744 0 : val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
745 0 : val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
746 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
747 :
748 0 : if (intel_hdmi_set_gcp_infoframe(encoder))
749 0 : val |= VIDEO_DIP_ENABLE_GCP;
750 :
751 0 : I915_WRITE(reg, val);
752 0 : POSTING_READ(reg);
753 :
754 0 : intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
755 0 : intel_hdmi_set_spd_infoframe(encoder);
756 0 : intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
757 0 : }
758 :
759 0 : static void vlv_set_infoframes(struct drm_encoder *encoder,
760 : bool enable,
761 : const struct drm_display_mode *adjusted_mode)
762 : {
763 0 : struct drm_i915_private *dev_priv = encoder->dev->dev_private;
764 0 : struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
765 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
766 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
767 0 : u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
768 0 : u32 val = I915_READ(reg);
769 0 : u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
770 :
771 0 : assert_hdmi_port_disabled(intel_hdmi);
772 :
773 : /* See the big comment in g4x_set_infoframes() */
774 0 : val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
775 :
776 0 : if (!enable) {
777 0 : if (!(val & VIDEO_DIP_ENABLE))
778 0 : return;
779 0 : val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
780 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
781 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
782 0 : I915_WRITE(reg, val);
783 0 : POSTING_READ(reg);
784 0 : return;
785 : }
786 :
787 0 : if (port != (val & VIDEO_DIP_PORT_MASK)) {
788 0 : WARN(val & VIDEO_DIP_ENABLE,
789 : "DIP already enabled on port %c\n",
790 : (val & VIDEO_DIP_PORT_MASK) >> 29);
791 0 : val &= ~VIDEO_DIP_PORT_MASK;
792 0 : val |= port;
793 0 : }
794 :
795 0 : val |= VIDEO_DIP_ENABLE;
796 0 : val &= ~(VIDEO_DIP_ENABLE_AVI |
797 : VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
798 : VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
799 :
800 0 : if (intel_hdmi_set_gcp_infoframe(encoder))
801 0 : val |= VIDEO_DIP_ENABLE_GCP;
802 :
803 0 : I915_WRITE(reg, val);
804 0 : POSTING_READ(reg);
805 :
806 0 : intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
807 0 : intel_hdmi_set_spd_infoframe(encoder);
808 0 : intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
809 0 : }
810 :
811 0 : static void hsw_set_infoframes(struct drm_encoder *encoder,
812 : bool enable,
813 : const struct drm_display_mode *adjusted_mode)
814 : {
815 0 : struct drm_i915_private *dev_priv = encoder->dev->dev_private;
816 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
817 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
818 0 : u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
819 0 : u32 val = I915_READ(reg);
820 :
821 0 : assert_hdmi_port_disabled(intel_hdmi);
822 :
823 0 : val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
824 : VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
825 : VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
826 :
827 0 : if (!enable) {
828 0 : I915_WRITE(reg, val);
829 0 : POSTING_READ(reg);
830 0 : return;
831 : }
832 :
833 0 : if (intel_hdmi_set_gcp_infoframe(encoder))
834 0 : val |= VIDEO_DIP_ENABLE_GCP_HSW;
835 :
836 0 : I915_WRITE(reg, val);
837 0 : POSTING_READ(reg);
838 :
839 0 : intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
840 0 : intel_hdmi_set_spd_infoframe(encoder);
841 0 : intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
842 0 : }
843 :
844 0 : static void intel_hdmi_prepare(struct intel_encoder *encoder)
845 : {
846 0 : struct drm_device *dev = encoder->base.dev;
847 0 : struct drm_i915_private *dev_priv = dev->dev_private;
848 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
849 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
850 0 : const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
851 : u32 hdmi_val;
852 :
853 : hdmi_val = SDVO_ENCODING_HDMI;
854 0 : if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
855 0 : hdmi_val |= HDMI_COLOR_RANGE_16_235;
856 0 : if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
857 0 : hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
858 0 : if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
859 0 : hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
860 :
861 0 : if (crtc->config->pipe_bpp > 24)
862 0 : hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
863 : else
864 : hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
865 :
866 0 : if (crtc->config->has_hdmi_sink)
867 0 : hdmi_val |= HDMI_MODE_SELECT_HDMI;
868 :
869 0 : if (HAS_PCH_CPT(dev))
870 0 : hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
871 0 : else if (IS_CHERRYVIEW(dev))
872 0 : hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
873 : else
874 0 : hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
875 :
876 0 : I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
877 0 : POSTING_READ(intel_hdmi->hdmi_reg);
878 0 : }
879 :
880 0 : static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
881 : enum pipe *pipe)
882 : {
883 0 : struct drm_device *dev = encoder->base.dev;
884 0 : struct drm_i915_private *dev_priv = dev->dev_private;
885 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
886 : enum intel_display_power_domain power_domain;
887 : u32 tmp;
888 :
889 0 : power_domain = intel_display_port_power_domain(encoder);
890 0 : if (!intel_display_power_is_enabled(dev_priv, power_domain))
891 0 : return false;
892 :
893 0 : tmp = I915_READ(intel_hdmi->hdmi_reg);
894 :
895 0 : if (!(tmp & SDVO_ENABLE))
896 0 : return false;
897 :
898 0 : if (HAS_PCH_CPT(dev))
899 0 : *pipe = PORT_TO_PIPE_CPT(tmp);
900 0 : else if (IS_CHERRYVIEW(dev))
901 0 : *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
902 : else
903 0 : *pipe = PORT_TO_PIPE(tmp);
904 :
905 0 : return true;
906 0 : }
907 :
908 0 : static void intel_hdmi_get_config(struct intel_encoder *encoder,
909 : struct intel_crtc_state *pipe_config)
910 : {
911 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
912 0 : struct drm_device *dev = encoder->base.dev;
913 0 : struct drm_i915_private *dev_priv = dev->dev_private;
914 : u32 tmp, flags = 0;
915 : int dotclock;
916 :
917 0 : tmp = I915_READ(intel_hdmi->hdmi_reg);
918 :
919 0 : if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
920 0 : flags |= DRM_MODE_FLAG_PHSYNC;
921 : else
922 : flags |= DRM_MODE_FLAG_NHSYNC;
923 :
924 0 : if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
925 0 : flags |= DRM_MODE_FLAG_PVSYNC;
926 : else
927 0 : flags |= DRM_MODE_FLAG_NVSYNC;
928 :
929 0 : if (tmp & HDMI_MODE_SELECT_HDMI)
930 0 : pipe_config->has_hdmi_sink = true;
931 :
932 0 : if (intel_hdmi->infoframe_enabled(&encoder->base))
933 0 : pipe_config->has_infoframe = true;
934 :
935 0 : if (tmp & SDVO_AUDIO_ENABLE)
936 0 : pipe_config->has_audio = true;
937 :
938 0 : if (!HAS_PCH_SPLIT(dev) &&
939 0 : tmp & HDMI_COLOR_RANGE_16_235)
940 0 : pipe_config->limited_color_range = true;
941 :
942 0 : pipe_config->base.adjusted_mode.flags |= flags;
943 :
944 0 : if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
945 0 : dotclock = pipe_config->port_clock * 2 / 3;
946 : else
947 : dotclock = pipe_config->port_clock;
948 :
949 0 : if (pipe_config->pixel_multiplier)
950 0 : dotclock /= pipe_config->pixel_multiplier;
951 :
952 0 : if (HAS_PCH_SPLIT(dev_priv->dev))
953 0 : ironlake_check_encoder_dotclock(pipe_config, dotclock);
954 :
955 0 : pipe_config->base.adjusted_mode.crtc_clock = dotclock;
956 0 : }
957 :
958 0 : static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
959 : {
960 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
961 :
962 0 : WARN_ON(!crtc->config->has_hdmi_sink);
963 : DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
964 : pipe_name(crtc->pipe));
965 0 : intel_audio_codec_enable(encoder);
966 0 : }
967 :
968 0 : static void g4x_enable_hdmi(struct intel_encoder *encoder)
969 : {
970 0 : struct drm_device *dev = encoder->base.dev;
971 0 : struct drm_i915_private *dev_priv = dev->dev_private;
972 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
973 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
974 : u32 temp;
975 :
976 0 : temp = I915_READ(intel_hdmi->hdmi_reg);
977 :
978 0 : temp |= SDVO_ENABLE;
979 0 : if (crtc->config->has_audio)
980 0 : temp |= SDVO_AUDIO_ENABLE;
981 :
982 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
983 0 : POSTING_READ(intel_hdmi->hdmi_reg);
984 :
985 0 : if (crtc->config->has_audio)
986 0 : intel_enable_hdmi_audio(encoder);
987 0 : }
988 :
989 0 : static void ibx_enable_hdmi(struct intel_encoder *encoder)
990 : {
991 0 : struct drm_device *dev = encoder->base.dev;
992 0 : struct drm_i915_private *dev_priv = dev->dev_private;
993 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
994 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
995 : u32 temp;
996 :
997 0 : temp = I915_READ(intel_hdmi->hdmi_reg);
998 :
999 0 : temp |= SDVO_ENABLE;
1000 0 : if (crtc->config->has_audio)
1001 0 : temp |= SDVO_AUDIO_ENABLE;
1002 :
1003 : /*
1004 : * HW workaround, need to write this twice for issue
1005 : * that may result in first write getting masked.
1006 : */
1007 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1008 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1009 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1010 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1011 :
1012 : /*
1013 : * HW workaround, need to toggle enable bit off and on
1014 : * for 12bpc with pixel repeat.
1015 : *
1016 : * FIXME: BSpec says this should be done at the end of
1017 : * of the modeset sequence, so not sure if this isn't too soon.
1018 : */
1019 0 : if (crtc->config->pipe_bpp > 24 &&
1020 0 : crtc->config->pixel_multiplier > 1) {
1021 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1022 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1023 :
1024 : /*
1025 : * HW workaround, need to write this twice for issue
1026 : * that may result in first write getting masked.
1027 : */
1028 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1029 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1030 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1031 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1032 0 : }
1033 :
1034 0 : if (crtc->config->has_audio)
1035 0 : intel_enable_hdmi_audio(encoder);
1036 0 : }
1037 :
1038 0 : static void cpt_enable_hdmi(struct intel_encoder *encoder)
1039 : {
1040 0 : struct drm_device *dev = encoder->base.dev;
1041 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1042 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1043 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1044 0 : enum pipe pipe = crtc->pipe;
1045 : u32 temp;
1046 :
1047 0 : temp = I915_READ(intel_hdmi->hdmi_reg);
1048 :
1049 0 : temp |= SDVO_ENABLE;
1050 0 : if (crtc->config->has_audio)
1051 0 : temp |= SDVO_AUDIO_ENABLE;
1052 :
1053 : /*
1054 : * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1055 : *
1056 : * The procedure for 12bpc is as follows:
1057 : * 1. disable HDMI clock gating
1058 : * 2. enable HDMI with 8bpc
1059 : * 3. enable HDMI with 12bpc
1060 : * 4. enable HDMI clock gating
1061 : */
1062 :
1063 0 : if (crtc->config->pipe_bpp > 24) {
1064 0 : I915_WRITE(TRANS_CHICKEN1(pipe),
1065 : I915_READ(TRANS_CHICKEN1(pipe)) |
1066 : TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1067 :
1068 0 : temp &= ~SDVO_COLOR_FORMAT_MASK;
1069 : temp |= SDVO_COLOR_FORMAT_8bpc;
1070 0 : }
1071 :
1072 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1073 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1074 :
1075 0 : if (crtc->config->pipe_bpp > 24) {
1076 0 : temp &= ~SDVO_COLOR_FORMAT_MASK;
1077 0 : temp |= HDMI_COLOR_FORMAT_12bpc;
1078 :
1079 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1080 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1081 :
1082 0 : I915_WRITE(TRANS_CHICKEN1(pipe),
1083 : I915_READ(TRANS_CHICKEN1(pipe)) &
1084 : ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1085 0 : }
1086 :
1087 0 : if (crtc->config->has_audio)
1088 0 : intel_enable_hdmi_audio(encoder);
1089 0 : }
1090 :
1091 0 : static void vlv_enable_hdmi(struct intel_encoder *encoder)
1092 : {
1093 0 : }
1094 :
1095 0 : static void intel_disable_hdmi(struct intel_encoder *encoder)
1096 : {
1097 0 : struct drm_device *dev = encoder->base.dev;
1098 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1099 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1100 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1101 : u32 temp;
1102 :
1103 0 : temp = I915_READ(intel_hdmi->hdmi_reg);
1104 :
1105 0 : temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1106 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1107 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1108 :
1109 : /*
1110 : * HW workaround for IBX, we need to move the port
1111 : * to transcoder A after disabling it to allow the
1112 : * matching DP port to be enabled on transcoder A.
1113 : */
1114 0 : if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1115 0 : temp &= ~SDVO_PIPE_B_SELECT;
1116 0 : temp |= SDVO_ENABLE;
1117 : /*
1118 : * HW workaround, need to write this twice for issue
1119 : * that may result in first write getting masked.
1120 : */
1121 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1122 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1123 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1124 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1125 :
1126 : temp &= ~SDVO_ENABLE;
1127 0 : I915_WRITE(intel_hdmi->hdmi_reg, temp);
1128 0 : POSTING_READ(intel_hdmi->hdmi_reg);
1129 0 : }
1130 :
1131 0 : intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1132 0 : }
1133 :
1134 0 : static void g4x_disable_hdmi(struct intel_encoder *encoder)
1135 : {
1136 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1137 :
1138 0 : if (crtc->config->has_audio)
1139 0 : intel_audio_codec_disable(encoder);
1140 :
1141 0 : intel_disable_hdmi(encoder);
1142 0 : }
1143 :
1144 0 : static void pch_disable_hdmi(struct intel_encoder *encoder)
1145 : {
1146 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1147 :
1148 0 : if (crtc->config->has_audio)
1149 0 : intel_audio_codec_disable(encoder);
1150 0 : }
1151 :
1152 0 : static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1153 : {
1154 0 : intel_disable_hdmi(encoder);
1155 0 : }
1156 :
1157 0 : static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1158 : {
1159 0 : struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1160 :
1161 0 : if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1162 0 : return 165000;
1163 0 : else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1164 0 : return 300000;
1165 : else
1166 0 : return 225000;
1167 0 : }
1168 :
1169 : static enum drm_mode_status
1170 0 : hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1171 : int clock, bool respect_dvi_limit)
1172 : {
1173 0 : struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1174 :
1175 0 : if (clock < 25000)
1176 0 : return MODE_CLOCK_LOW;
1177 0 : if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1178 0 : return MODE_CLOCK_HIGH;
1179 :
1180 : /* BXT DPLL can't generate 223-240 MHz */
1181 0 : if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1182 0 : return MODE_CLOCK_RANGE;
1183 :
1184 : /* CHV DPLL can't generate 216-240 MHz */
1185 0 : if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1186 0 : return MODE_CLOCK_RANGE;
1187 :
1188 0 : return MODE_OK;
1189 0 : }
1190 :
1191 : static enum drm_mode_status
1192 0 : intel_hdmi_mode_valid(struct drm_connector *connector,
1193 : struct drm_display_mode *mode)
1194 : {
1195 0 : struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1196 0 : struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1197 : enum drm_mode_status status;
1198 : int clock;
1199 :
1200 0 : if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1201 0 : return MODE_NO_DBLESCAN;
1202 :
1203 0 : clock = mode->clock;
1204 0 : if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1205 0 : clock *= 2;
1206 :
1207 : /* check if we can do 8bpc */
1208 0 : status = hdmi_port_clock_valid(hdmi, clock, true);
1209 :
1210 : /* if we can't do 8bpc we may still be able to do 12bpc */
1211 0 : if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1212 0 : status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1213 :
1214 0 : return status;
1215 0 : }
1216 :
1217 0 : static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1218 : {
1219 0 : struct drm_device *dev = crtc_state->base.crtc->dev;
1220 : struct drm_atomic_state *state;
1221 : struct intel_encoder *encoder;
1222 : struct drm_connector *connector;
1223 : struct drm_connector_state *connector_state;
1224 : int count = 0, count_hdmi = 0;
1225 : int i;
1226 :
1227 0 : if (HAS_GMCH_DISPLAY(dev))
1228 0 : return false;
1229 :
1230 0 : state = crtc_state->base.state;
1231 :
1232 0 : for_each_connector_in_state(state, connector, connector_state, i) {
1233 0 : if (connector_state->crtc != crtc_state->base.crtc)
1234 : continue;
1235 :
1236 0 : encoder = to_intel_encoder(connector_state->best_encoder);
1237 :
1238 0 : count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1239 0 : count++;
1240 0 : }
1241 :
1242 : /*
1243 : * HDMI 12bpc affects the clocks, so it's only possible
1244 : * when not cloning with other encoder types.
1245 : */
1246 0 : return count_hdmi > 0 && count_hdmi == count;
1247 0 : }
1248 :
1249 0 : bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1250 : struct intel_crtc_state *pipe_config)
1251 : {
1252 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1253 0 : struct drm_device *dev = encoder->base.dev;
1254 0 : struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1255 0 : int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1256 0 : int clock_12bpc = clock_8bpc * 3 / 2;
1257 : int desired_bpp;
1258 :
1259 0 : pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1260 :
1261 0 : if (pipe_config->has_hdmi_sink)
1262 0 : pipe_config->has_infoframe = true;
1263 :
1264 0 : if (intel_hdmi->color_range_auto) {
1265 : /* See CEA-861-E - 5.1 Default Encoding Parameters */
1266 0 : pipe_config->limited_color_range =
1267 0 : pipe_config->has_hdmi_sink &&
1268 0 : drm_match_cea_mode(adjusted_mode) > 1;
1269 0 : } else {
1270 0 : pipe_config->limited_color_range =
1271 0 : intel_hdmi->limited_color_range;
1272 : }
1273 :
1274 0 : if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1275 0 : pipe_config->pixel_multiplier = 2;
1276 0 : clock_8bpc *= 2;
1277 0 : clock_12bpc *= 2;
1278 0 : }
1279 :
1280 0 : if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1281 0 : pipe_config->has_pch_encoder = true;
1282 :
1283 0 : if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1284 0 : pipe_config->has_audio = true;
1285 :
1286 : /*
1287 : * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1288 : * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1289 : * outputs. We also need to check that the higher clock still fits
1290 : * within limits.
1291 : */
1292 0 : if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1293 0 : hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1294 0 : hdmi_12bpc_possible(pipe_config)) {
1295 : DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1296 : desired_bpp = 12*3;
1297 :
1298 : /* Need to adjust the port link by 1.5x for 12bpc. */
1299 0 : pipe_config->port_clock = clock_12bpc;
1300 0 : } else {
1301 : DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1302 : desired_bpp = 8*3;
1303 :
1304 0 : pipe_config->port_clock = clock_8bpc;
1305 : }
1306 :
1307 0 : if (!pipe_config->bw_constrained) {
1308 : DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1309 0 : pipe_config->pipe_bpp = desired_bpp;
1310 0 : }
1311 :
1312 0 : if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1313 0 : false) != MODE_OK) {
1314 : DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1315 0 : return false;
1316 : }
1317 :
1318 : /* Set user selected PAR to incoming mode's member */
1319 0 : adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1320 :
1321 0 : return true;
1322 0 : }
1323 :
1324 : static void
1325 0 : intel_hdmi_unset_edid(struct drm_connector *connector)
1326 : {
1327 0 : struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1328 :
1329 0 : intel_hdmi->has_hdmi_sink = false;
1330 0 : intel_hdmi->has_audio = false;
1331 0 : intel_hdmi->rgb_quant_range_selectable = false;
1332 :
1333 0 : kfree(to_intel_connector(connector)->detect_edid);
1334 0 : to_intel_connector(connector)->detect_edid = NULL;
1335 0 : }
1336 :
1337 : static bool
1338 0 : intel_hdmi_set_edid(struct drm_connector *connector)
1339 : {
1340 0 : struct drm_i915_private *dev_priv = to_i915(connector->dev);
1341 0 : struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1342 : struct edid *edid;
1343 : bool connected = false;
1344 :
1345 0 : intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1346 :
1347 0 : edid = drm_get_edid(connector,
1348 0 : intel_gmbus_get_adapter(dev_priv,
1349 0 : intel_hdmi->ddc_bus));
1350 :
1351 0 : intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1352 :
1353 0 : to_intel_connector(connector)->detect_edid = edid;
1354 0 : if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1355 0 : intel_hdmi->rgb_quant_range_selectable =
1356 0 : drm_rgb_quant_range_selectable(edid);
1357 :
1358 0 : intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1359 0 : if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1360 0 : intel_hdmi->has_audio =
1361 0 : intel_hdmi->force_audio == HDMI_AUDIO_ON;
1362 :
1363 0 : if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1364 0 : intel_hdmi->has_hdmi_sink =
1365 0 : drm_detect_hdmi_monitor(edid);
1366 :
1367 : connected = true;
1368 0 : }
1369 :
1370 0 : return connected;
1371 : }
1372 :
1373 : static enum drm_connector_status
1374 0 : intel_hdmi_detect(struct drm_connector *connector, bool force)
1375 : {
1376 : enum drm_connector_status status;
1377 0 : struct drm_i915_private *dev_priv = to_i915(connector->dev);
1378 :
1379 : DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1380 : connector->base.id, connector->name);
1381 :
1382 0 : intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1383 :
1384 0 : intel_hdmi_unset_edid(connector);
1385 :
1386 0 : if (intel_hdmi_set_edid(connector)) {
1387 0 : struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1388 :
1389 0 : hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1390 : status = connector_status_connected;
1391 0 : } else
1392 : status = connector_status_disconnected;
1393 :
1394 0 : intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1395 :
1396 0 : return status;
1397 : }
1398 :
1399 : static void
1400 0 : intel_hdmi_force(struct drm_connector *connector)
1401 : {
1402 0 : struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1403 :
1404 : DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1405 : connector->base.id, connector->name);
1406 :
1407 0 : intel_hdmi_unset_edid(connector);
1408 :
1409 0 : if (connector->status != connector_status_connected)
1410 0 : return;
1411 :
1412 0 : intel_hdmi_set_edid(connector);
1413 0 : hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1414 0 : }
1415 :
1416 0 : static int intel_hdmi_get_modes(struct drm_connector *connector)
1417 : {
1418 : struct edid *edid;
1419 :
1420 0 : edid = to_intel_connector(connector)->detect_edid;
1421 0 : if (edid == NULL)
1422 0 : return 0;
1423 :
1424 0 : return intel_connector_update_modes(connector, edid);
1425 0 : }
1426 :
1427 : static bool
1428 0 : intel_hdmi_detect_audio(struct drm_connector *connector)
1429 : {
1430 : bool has_audio = false;
1431 : struct edid *edid;
1432 :
1433 0 : edid = to_intel_connector(connector)->detect_edid;
1434 0 : if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1435 0 : has_audio = drm_detect_monitor_audio(edid);
1436 :
1437 0 : return has_audio;
1438 : }
1439 :
1440 : static int
1441 0 : intel_hdmi_set_property(struct drm_connector *connector,
1442 : struct drm_property *property,
1443 : uint64_t val)
1444 : {
1445 0 : struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1446 : struct intel_digital_port *intel_dig_port =
1447 0 : hdmi_to_dig_port(intel_hdmi);
1448 0 : struct drm_i915_private *dev_priv = connector->dev->dev_private;
1449 : int ret;
1450 :
1451 0 : ret = drm_object_property_set_value(&connector->base, property, val);
1452 0 : if (ret)
1453 0 : return ret;
1454 :
1455 0 : if (property == dev_priv->force_audio_property) {
1456 0 : enum hdmi_force_audio i = val;
1457 : bool has_audio;
1458 :
1459 0 : if (i == intel_hdmi->force_audio)
1460 0 : return 0;
1461 :
1462 0 : intel_hdmi->force_audio = i;
1463 :
1464 0 : if (i == HDMI_AUDIO_AUTO)
1465 0 : has_audio = intel_hdmi_detect_audio(connector);
1466 : else
1467 0 : has_audio = (i == HDMI_AUDIO_ON);
1468 :
1469 0 : if (i == HDMI_AUDIO_OFF_DVI)
1470 0 : intel_hdmi->has_hdmi_sink = 0;
1471 :
1472 0 : intel_hdmi->has_audio = has_audio;
1473 0 : goto done;
1474 : }
1475 :
1476 0 : if (property == dev_priv->broadcast_rgb_property) {
1477 0 : bool old_auto = intel_hdmi->color_range_auto;
1478 0 : bool old_range = intel_hdmi->limited_color_range;
1479 :
1480 0 : switch (val) {
1481 : case INTEL_BROADCAST_RGB_AUTO:
1482 0 : intel_hdmi->color_range_auto = true;
1483 0 : break;
1484 : case INTEL_BROADCAST_RGB_FULL:
1485 0 : intel_hdmi->color_range_auto = false;
1486 0 : intel_hdmi->limited_color_range = false;
1487 0 : break;
1488 : case INTEL_BROADCAST_RGB_LIMITED:
1489 0 : intel_hdmi->color_range_auto = false;
1490 0 : intel_hdmi->limited_color_range = true;
1491 0 : break;
1492 : default:
1493 0 : return -EINVAL;
1494 : }
1495 :
1496 0 : if (old_auto == intel_hdmi->color_range_auto &&
1497 0 : old_range == intel_hdmi->limited_color_range)
1498 0 : return 0;
1499 :
1500 0 : goto done;
1501 : }
1502 :
1503 0 : if (property == connector->dev->mode_config.aspect_ratio_property) {
1504 0 : switch (val) {
1505 : case DRM_MODE_PICTURE_ASPECT_NONE:
1506 0 : intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1507 0 : break;
1508 : case DRM_MODE_PICTURE_ASPECT_4_3:
1509 0 : intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1510 0 : break;
1511 : case DRM_MODE_PICTURE_ASPECT_16_9:
1512 0 : intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1513 0 : break;
1514 : default:
1515 0 : return -EINVAL;
1516 : }
1517 : goto done;
1518 : }
1519 :
1520 0 : return -EINVAL;
1521 :
1522 : done:
1523 0 : if (intel_dig_port->base.base.crtc)
1524 0 : intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1525 :
1526 0 : return 0;
1527 0 : }
1528 :
1529 0 : static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1530 : {
1531 0 : struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1532 0 : struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1533 0 : const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1534 :
1535 0 : intel_hdmi_prepare(encoder);
1536 :
1537 0 : intel_hdmi->set_infoframes(&encoder->base,
1538 0 : intel_crtc->config->has_hdmi_sink,
1539 : adjusted_mode);
1540 0 : }
1541 :
1542 0 : static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1543 : {
1544 0 : struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1545 0 : struct intel_hdmi *intel_hdmi = &dport->hdmi;
1546 0 : struct drm_device *dev = encoder->base.dev;
1547 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1548 : struct intel_crtc *intel_crtc =
1549 0 : to_intel_crtc(encoder->base.crtc);
1550 0 : const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1551 0 : enum dpio_channel port = vlv_dport_to_channel(dport);
1552 0 : int pipe = intel_crtc->pipe;
1553 : u32 val;
1554 :
1555 : /* Enable clock channels for this port */
1556 0 : mutex_lock(&dev_priv->sb_lock);
1557 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1558 : val = 0;
1559 0 : if (pipe)
1560 0 : val |= (1<<21);
1561 : else
1562 : val &= ~(1<<21);
1563 0 : val |= 0x001000c4;
1564 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1565 :
1566 : /* HDMI 1.0V-2dB */
1567 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1568 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1569 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1570 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1571 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1572 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1573 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1574 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1575 :
1576 : /* Program lane clock */
1577 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1578 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1579 0 : mutex_unlock(&dev_priv->sb_lock);
1580 :
1581 0 : intel_hdmi->set_infoframes(&encoder->base,
1582 0 : intel_crtc->config->has_hdmi_sink,
1583 : adjusted_mode);
1584 :
1585 0 : g4x_enable_hdmi(encoder);
1586 :
1587 0 : vlv_wait_port_ready(dev_priv, dport, 0x0);
1588 0 : }
1589 :
1590 0 : static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1591 : {
1592 0 : struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1593 0 : struct drm_device *dev = encoder->base.dev;
1594 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1595 : struct intel_crtc *intel_crtc =
1596 0 : to_intel_crtc(encoder->base.crtc);
1597 0 : enum dpio_channel port = vlv_dport_to_channel(dport);
1598 0 : int pipe = intel_crtc->pipe;
1599 :
1600 0 : intel_hdmi_prepare(encoder);
1601 :
1602 : /* Program Tx lane resets to default */
1603 0 : mutex_lock(&dev_priv->sb_lock);
1604 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1605 : DPIO_PCS_TX_LANE2_RESET |
1606 : DPIO_PCS_TX_LANE1_RESET);
1607 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1608 : DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1609 : DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1610 : (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1611 : DPIO_PCS_CLK_SOFT_RESET);
1612 :
1613 : /* Fix up inter-pair skew failure */
1614 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1615 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1616 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1617 :
1618 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1619 0 : vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1620 0 : mutex_unlock(&dev_priv->sb_lock);
1621 0 : }
1622 :
1623 0 : static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1624 : bool reset)
1625 : {
1626 0 : struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1627 0 : enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1628 0 : struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1629 0 : enum pipe pipe = crtc->pipe;
1630 : uint32_t val;
1631 :
1632 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1633 0 : if (reset)
1634 0 : val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1635 : else
1636 0 : val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1637 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1638 :
1639 0 : if (crtc->config->lane_count > 2) {
1640 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1641 0 : if (reset)
1642 0 : val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1643 : else
1644 0 : val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1645 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1646 0 : }
1647 :
1648 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1649 0 : val |= CHV_PCS_REQ_SOFTRESET_EN;
1650 0 : if (reset)
1651 0 : val &= ~DPIO_PCS_CLK_SOFT_RESET;
1652 : else
1653 0 : val |= DPIO_PCS_CLK_SOFT_RESET;
1654 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1655 :
1656 0 : if (crtc->config->lane_count > 2) {
1657 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1658 0 : val |= CHV_PCS_REQ_SOFTRESET_EN;
1659 0 : if (reset)
1660 0 : val &= ~DPIO_PCS_CLK_SOFT_RESET;
1661 : else
1662 0 : val |= DPIO_PCS_CLK_SOFT_RESET;
1663 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1664 0 : }
1665 0 : }
1666 :
1667 0 : static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1668 : {
1669 0 : struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1670 0 : struct drm_device *dev = encoder->base.dev;
1671 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1672 : struct intel_crtc *intel_crtc =
1673 0 : to_intel_crtc(encoder->base.crtc);
1674 0 : enum dpio_channel ch = vlv_dport_to_channel(dport);
1675 0 : enum pipe pipe = intel_crtc->pipe;
1676 : u32 val;
1677 :
1678 0 : intel_hdmi_prepare(encoder);
1679 :
1680 : /*
1681 : * Must trick the second common lane into life.
1682 : * Otherwise we can't even access the PLL.
1683 : */
1684 0 : if (ch == DPIO_CH0 && pipe == PIPE_B)
1685 0 : dport->release_cl2_override =
1686 0 : !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1687 :
1688 0 : chv_phy_powergate_lanes(encoder, true, 0x0);
1689 :
1690 0 : mutex_lock(&dev_priv->sb_lock);
1691 :
1692 : /* Assert data lane reset */
1693 0 : chv_data_lane_soft_reset(encoder, true);
1694 :
1695 : /* program left/right clock distribution */
1696 0 : if (pipe != PIPE_B) {
1697 0 : val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1698 0 : val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1699 0 : if (ch == DPIO_CH0)
1700 0 : val |= CHV_BUFLEFTENA1_FORCE;
1701 0 : if (ch == DPIO_CH1)
1702 0 : val |= CHV_BUFRIGHTENA1_FORCE;
1703 0 : vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1704 0 : } else {
1705 0 : val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1706 0 : val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1707 0 : if (ch == DPIO_CH0)
1708 0 : val |= CHV_BUFLEFTENA2_FORCE;
1709 0 : if (ch == DPIO_CH1)
1710 0 : val |= CHV_BUFRIGHTENA2_FORCE;
1711 0 : vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1712 : }
1713 :
1714 : /* program clock channel usage */
1715 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1716 0 : val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1717 0 : if (pipe != PIPE_B)
1718 0 : val &= ~CHV_PCS_USEDCLKCHANNEL;
1719 : else
1720 0 : val |= CHV_PCS_USEDCLKCHANNEL;
1721 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1722 :
1723 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1724 0 : val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1725 0 : if (pipe != PIPE_B)
1726 0 : val &= ~CHV_PCS_USEDCLKCHANNEL;
1727 : else
1728 0 : val |= CHV_PCS_USEDCLKCHANNEL;
1729 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1730 :
1731 : /*
1732 : * This a a bit weird since generally CL
1733 : * matches the pipe, but here we need to
1734 : * pick the CL based on the port.
1735 : */
1736 0 : val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1737 0 : if (pipe != PIPE_B)
1738 0 : val &= ~CHV_CMN_USEDCLKCHANNEL;
1739 : else
1740 0 : val |= CHV_CMN_USEDCLKCHANNEL;
1741 0 : vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1742 :
1743 0 : mutex_unlock(&dev_priv->sb_lock);
1744 0 : }
1745 :
1746 0 : static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1747 : {
1748 0 : struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1749 0 : enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1750 : u32 val;
1751 :
1752 0 : mutex_lock(&dev_priv->sb_lock);
1753 :
1754 : /* disable left/right clock distribution */
1755 0 : if (pipe != PIPE_B) {
1756 0 : val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1757 0 : val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1758 0 : vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1759 0 : } else {
1760 0 : val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1761 0 : val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1762 0 : vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1763 : }
1764 :
1765 0 : mutex_unlock(&dev_priv->sb_lock);
1766 :
1767 : /*
1768 : * Leave the power down bit cleared for at least one
1769 : * lane so that chv_powergate_phy_ch() will power
1770 : * on something when the channel is otherwise unused.
1771 : * When the port is off and the override is removed
1772 : * the lanes power down anyway, so otherwise it doesn't
1773 : * really matter what the state of power down bits is
1774 : * after this.
1775 : */
1776 0 : chv_phy_powergate_lanes(encoder, false, 0x0);
1777 0 : }
1778 :
1779 0 : static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1780 : {
1781 0 : struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1782 0 : struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1783 : struct intel_crtc *intel_crtc =
1784 0 : to_intel_crtc(encoder->base.crtc);
1785 0 : enum dpio_channel port = vlv_dport_to_channel(dport);
1786 0 : int pipe = intel_crtc->pipe;
1787 :
1788 : /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1789 0 : mutex_lock(&dev_priv->sb_lock);
1790 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1791 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1792 0 : mutex_unlock(&dev_priv->sb_lock);
1793 0 : }
1794 :
1795 0 : static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1796 : {
1797 0 : struct drm_device *dev = encoder->base.dev;
1798 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1799 :
1800 0 : mutex_lock(&dev_priv->sb_lock);
1801 :
1802 : /* Assert data lane reset */
1803 0 : chv_data_lane_soft_reset(encoder, true);
1804 :
1805 0 : mutex_unlock(&dev_priv->sb_lock);
1806 0 : }
1807 :
1808 0 : static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1809 : {
1810 0 : struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1811 0 : struct intel_hdmi *intel_hdmi = &dport->hdmi;
1812 0 : struct drm_device *dev = encoder->base.dev;
1813 0 : struct drm_i915_private *dev_priv = dev->dev_private;
1814 : struct intel_crtc *intel_crtc =
1815 0 : to_intel_crtc(encoder->base.crtc);
1816 0 : const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1817 0 : enum dpio_channel ch = vlv_dport_to_channel(dport);
1818 0 : int pipe = intel_crtc->pipe;
1819 : int data, i, stagger;
1820 : u32 val;
1821 :
1822 0 : mutex_lock(&dev_priv->sb_lock);
1823 :
1824 : /* allow hardware to manage TX FIFO reset source */
1825 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1826 0 : val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1827 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1828 :
1829 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1830 0 : val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1831 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1832 :
1833 : /* Program Tx latency optimal setting */
1834 0 : for (i = 0; i < 4; i++) {
1835 : /* Set the upar bit */
1836 0 : data = (i == 1) ? 0x0 : 0x1;
1837 0 : vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1838 0 : data << DPIO_UPAR_SHIFT);
1839 : }
1840 :
1841 : /* Data lane stagger programming */
1842 0 : if (intel_crtc->config->port_clock > 270000)
1843 0 : stagger = 0x18;
1844 0 : else if (intel_crtc->config->port_clock > 135000)
1845 0 : stagger = 0xd;
1846 0 : else if (intel_crtc->config->port_clock > 67500)
1847 0 : stagger = 0x7;
1848 0 : else if (intel_crtc->config->port_clock > 33750)
1849 0 : stagger = 0x4;
1850 : else
1851 : stagger = 0x2;
1852 :
1853 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1854 0 : val |= DPIO_TX2_STAGGER_MASK(0x1f);
1855 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1856 :
1857 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1858 0 : val |= DPIO_TX2_STAGGER_MASK(0x1f);
1859 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1860 :
1861 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1862 0 : DPIO_LANESTAGGER_STRAP(stagger) |
1863 0 : DPIO_LANESTAGGER_STRAP_OVRD |
1864 0 : DPIO_TX1_STAGGER_MASK(0x1f) |
1865 : DPIO_TX1_STAGGER_MULT(6) |
1866 : DPIO_TX2_STAGGER_MULT(0));
1867 :
1868 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1869 : DPIO_LANESTAGGER_STRAP(stagger) |
1870 : DPIO_LANESTAGGER_STRAP_OVRD |
1871 0 : DPIO_TX1_STAGGER_MASK(0x1f) |
1872 0 : DPIO_TX1_STAGGER_MULT(7) |
1873 : DPIO_TX2_STAGGER_MULT(5));
1874 :
1875 : /* Deassert data lane reset */
1876 0 : chv_data_lane_soft_reset(encoder, false);
1877 :
1878 : /* Clear calc init */
1879 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1880 0 : val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1881 0 : val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1882 : val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1883 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1884 :
1885 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1886 0 : val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1887 0 : val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1888 : val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1889 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1890 :
1891 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1892 0 : val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1893 : val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1894 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1895 :
1896 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1897 0 : val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1898 : val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1899 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1900 :
1901 : /* FIXME: Program the support xxx V-dB */
1902 : /* Use 800mV-0dB */
1903 0 : for (i = 0; i < 4; i++) {
1904 0 : val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1905 0 : val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1906 0 : val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1907 0 : vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1908 : }
1909 :
1910 0 : for (i = 0; i < 4; i++) {
1911 0 : val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1912 :
1913 0 : val &= ~DPIO_SWING_MARGIN000_MASK;
1914 0 : val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1915 :
1916 : /*
1917 : * Supposedly this value shouldn't matter when unique transition
1918 : * scale is disabled, but in fact it does matter. Let's just
1919 : * always program the same value and hope it's OK.
1920 : */
1921 0 : val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1922 0 : val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1923 :
1924 0 : vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1925 : }
1926 :
1927 : /*
1928 : * The document said it needs to set bit 27 for ch0 and bit 26
1929 : * for ch1. Might be a typo in the doc.
1930 : * For now, for this unique transition scale selection, set bit
1931 : * 27 for ch0 and ch1.
1932 : */
1933 0 : for (i = 0; i < 4; i++) {
1934 0 : val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1935 0 : val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1936 0 : vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1937 : }
1938 :
1939 : /* Start swing calculation */
1940 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1941 0 : val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1942 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1943 :
1944 0 : val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1945 0 : val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1946 0 : vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1947 :
1948 0 : mutex_unlock(&dev_priv->sb_lock);
1949 :
1950 0 : intel_hdmi->set_infoframes(&encoder->base,
1951 0 : intel_crtc->config->has_hdmi_sink,
1952 : adjusted_mode);
1953 :
1954 0 : g4x_enable_hdmi(encoder);
1955 :
1956 0 : vlv_wait_port_ready(dev_priv, dport, 0x0);
1957 :
1958 : /* Second common lane will stay alive on its own now */
1959 0 : if (dport->release_cl2_override) {
1960 0 : chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1961 0 : dport->release_cl2_override = false;
1962 0 : }
1963 0 : }
1964 :
1965 0 : static void intel_hdmi_destroy(struct drm_connector *connector)
1966 : {
1967 0 : kfree(to_intel_connector(connector)->detect_edid);
1968 0 : drm_connector_cleanup(connector);
1969 0 : kfree(connector);
1970 0 : }
1971 :
1972 : static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1973 : .dpms = drm_atomic_helper_connector_dpms,
1974 : .detect = intel_hdmi_detect,
1975 : .force = intel_hdmi_force,
1976 : .fill_modes = drm_helper_probe_single_connector_modes,
1977 : .set_property = intel_hdmi_set_property,
1978 : .atomic_get_property = intel_connector_atomic_get_property,
1979 : .destroy = intel_hdmi_destroy,
1980 : .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1981 : .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1982 : };
1983 :
1984 : static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1985 : .get_modes = intel_hdmi_get_modes,
1986 : .mode_valid = intel_hdmi_mode_valid,
1987 : .best_encoder = intel_best_encoder,
1988 : };
1989 :
1990 : static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1991 : .destroy = intel_encoder_destroy,
1992 : };
1993 :
1994 : static void
1995 0 : intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1996 : {
1997 0 : intel_attach_force_audio_property(connector);
1998 0 : intel_attach_broadcast_rgb_property(connector);
1999 0 : intel_hdmi->color_range_auto = true;
2000 0 : intel_attach_aspect_ratio_property(connector);
2001 0 : intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2002 0 : }
2003 :
2004 0 : static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2005 : enum port port)
2006 : {
2007 : const struct ddi_vbt_port_info *info =
2008 0 : &dev_priv->vbt.ddi_port_info[port];
2009 : u8 ddc_pin;
2010 :
2011 0 : if (info->alternate_ddc_pin) {
2012 : DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2013 : info->alternate_ddc_pin, port_name(port));
2014 0 : return info->alternate_ddc_pin;
2015 : }
2016 :
2017 0 : switch (port) {
2018 : case PORT_B:
2019 0 : if (IS_BROXTON(dev_priv))
2020 0 : ddc_pin = GMBUS_PIN_1_BXT;
2021 : else
2022 : ddc_pin = GMBUS_PIN_DPB;
2023 : break;
2024 : case PORT_C:
2025 0 : if (IS_BROXTON(dev_priv))
2026 0 : ddc_pin = GMBUS_PIN_2_BXT;
2027 : else
2028 : ddc_pin = GMBUS_PIN_DPC;
2029 : break;
2030 : case PORT_D:
2031 0 : if (IS_CHERRYVIEW(dev_priv))
2032 0 : ddc_pin = GMBUS_PIN_DPD_CHV;
2033 : else
2034 : ddc_pin = GMBUS_PIN_DPD;
2035 : break;
2036 : default:
2037 0 : MISSING_CASE(port);
2038 : ddc_pin = GMBUS_PIN_DPB;
2039 0 : break;
2040 : }
2041 :
2042 : DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2043 : ddc_pin, port_name(port));
2044 :
2045 0 : return ddc_pin;
2046 0 : }
2047 :
2048 0 : void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2049 : struct intel_connector *intel_connector)
2050 : {
2051 0 : struct drm_connector *connector = &intel_connector->base;
2052 0 : struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2053 0 : struct intel_encoder *intel_encoder = &intel_dig_port->base;
2054 0 : struct drm_device *dev = intel_encoder->base.dev;
2055 0 : struct drm_i915_private *dev_priv = dev->dev_private;
2056 0 : enum port port = intel_dig_port->port;
2057 :
2058 : DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2059 : port_name(port));
2060 :
2061 0 : drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2062 : DRM_MODE_CONNECTOR_HDMIA);
2063 0 : drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2064 :
2065 0 : connector->interlace_allowed = 1;
2066 0 : connector->doublescan_allowed = 0;
2067 0 : connector->stereo_allowed = 1;
2068 :
2069 0 : intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2070 :
2071 0 : switch (port) {
2072 : case PORT_B:
2073 : /*
2074 : * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2075 : * interrupts to check the external panel connection.
2076 : */
2077 0 : if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
2078 0 : intel_encoder->hpd_pin = HPD_PORT_A;
2079 : else
2080 0 : intel_encoder->hpd_pin = HPD_PORT_B;
2081 : break;
2082 : case PORT_C:
2083 0 : intel_encoder->hpd_pin = HPD_PORT_C;
2084 0 : break;
2085 : case PORT_D:
2086 0 : intel_encoder->hpd_pin = HPD_PORT_D;
2087 0 : break;
2088 : case PORT_E:
2089 0 : intel_encoder->hpd_pin = HPD_PORT_E;
2090 0 : break;
2091 : default:
2092 0 : MISSING_CASE(port);
2093 0 : return;
2094 : }
2095 :
2096 0 : if (IS_VALLEYVIEW(dev)) {
2097 0 : intel_hdmi->write_infoframe = vlv_write_infoframe;
2098 0 : intel_hdmi->set_infoframes = vlv_set_infoframes;
2099 0 : intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2100 0 : } else if (IS_G4X(dev)) {
2101 0 : intel_hdmi->write_infoframe = g4x_write_infoframe;
2102 0 : intel_hdmi->set_infoframes = g4x_set_infoframes;
2103 0 : intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2104 0 : } else if (HAS_DDI(dev)) {
2105 0 : intel_hdmi->write_infoframe = hsw_write_infoframe;
2106 0 : intel_hdmi->set_infoframes = hsw_set_infoframes;
2107 0 : intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2108 0 : } else if (HAS_PCH_IBX(dev)) {
2109 0 : intel_hdmi->write_infoframe = ibx_write_infoframe;
2110 0 : intel_hdmi->set_infoframes = ibx_set_infoframes;
2111 0 : intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2112 0 : } else {
2113 0 : intel_hdmi->write_infoframe = cpt_write_infoframe;
2114 0 : intel_hdmi->set_infoframes = cpt_set_infoframes;
2115 0 : intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2116 : }
2117 :
2118 0 : if (HAS_DDI(dev))
2119 0 : intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2120 : else
2121 0 : intel_connector->get_hw_state = intel_connector_get_hw_state;
2122 0 : intel_connector->unregister = intel_connector_unregister;
2123 :
2124 0 : intel_hdmi_add_properties(intel_hdmi, connector);
2125 :
2126 0 : intel_connector_attach_encoder(intel_connector, intel_encoder);
2127 0 : drm_connector_register(connector);
2128 0 : intel_hdmi->attached_connector = intel_connector;
2129 :
2130 : /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2131 : * 0xd. Failure to do so will result in spurious interrupts being
2132 : * generated on the port when a cable is not attached.
2133 : */
2134 0 : if (IS_G4X(dev) && !IS_GM45(dev)) {
2135 0 : u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2136 0 : I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2137 0 : }
2138 0 : }
2139 :
2140 0 : void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
2141 : {
2142 : struct intel_digital_port *intel_dig_port;
2143 : struct intel_encoder *intel_encoder;
2144 : struct intel_connector *intel_connector;
2145 :
2146 0 : intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2147 0 : if (!intel_dig_port)
2148 0 : return;
2149 :
2150 0 : intel_connector = intel_connector_alloc();
2151 0 : if (!intel_connector) {
2152 0 : kfree(intel_dig_port);
2153 0 : return;
2154 : }
2155 :
2156 0 : intel_encoder = &intel_dig_port->base;
2157 :
2158 0 : drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2159 : DRM_MODE_ENCODER_TMDS);
2160 :
2161 0 : intel_encoder->compute_config = intel_hdmi_compute_config;
2162 0 : if (HAS_PCH_SPLIT(dev)) {
2163 0 : intel_encoder->disable = pch_disable_hdmi;
2164 0 : intel_encoder->post_disable = pch_post_disable_hdmi;
2165 0 : } else {
2166 0 : intel_encoder->disable = g4x_disable_hdmi;
2167 : }
2168 0 : intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2169 0 : intel_encoder->get_config = intel_hdmi_get_config;
2170 0 : if (IS_CHERRYVIEW(dev)) {
2171 0 : intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2172 0 : intel_encoder->pre_enable = chv_hdmi_pre_enable;
2173 0 : intel_encoder->enable = vlv_enable_hdmi;
2174 0 : intel_encoder->post_disable = chv_hdmi_post_disable;
2175 0 : intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2176 0 : } else if (IS_VALLEYVIEW(dev)) {
2177 0 : intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2178 0 : intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2179 0 : intel_encoder->enable = vlv_enable_hdmi;
2180 0 : intel_encoder->post_disable = vlv_hdmi_post_disable;
2181 0 : } else {
2182 0 : intel_encoder->pre_enable = intel_hdmi_pre_enable;
2183 0 : if (HAS_PCH_CPT(dev))
2184 0 : intel_encoder->enable = cpt_enable_hdmi;
2185 0 : else if (HAS_PCH_IBX(dev))
2186 0 : intel_encoder->enable = ibx_enable_hdmi;
2187 : else
2188 0 : intel_encoder->enable = g4x_enable_hdmi;
2189 : }
2190 :
2191 0 : intel_encoder->type = INTEL_OUTPUT_HDMI;
2192 0 : if (IS_CHERRYVIEW(dev)) {
2193 0 : if (port == PORT_D)
2194 0 : intel_encoder->crtc_mask = 1 << 2;
2195 : else
2196 0 : intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2197 : } else {
2198 0 : intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2199 : }
2200 0 : intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2201 : /*
2202 : * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2203 : * to work on real hardware. And since g4x can send infoframes to
2204 : * only one port anyway, nothing is lost by allowing it.
2205 : */
2206 0 : if (IS_G4X(dev))
2207 0 : intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2208 :
2209 0 : intel_dig_port->port = port;
2210 0 : intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2211 0 : intel_dig_port->dp.output_reg = 0;
2212 :
2213 0 : intel_hdmi_init_connector(intel_dig_port, intel_connector);
2214 0 : }
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