Line data Source code
1 : /*
2 : * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 : * Copyright © 2006-2008,2010 Intel Corporation
4 : * Jesse Barnes <jesse.barnes@intel.com>
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice (including the next
14 : * paragraph) shall be included in all copies or substantial portions of the
15 : * Software.
16 : *
17 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 : * DEALINGS IN THE SOFTWARE.
24 : *
25 : * Authors:
26 : * Eric Anholt <eric@anholt.net>
27 : * Chris Wilson <chris@chris-wilson.co.uk>
28 : */
29 : #ifdef __linux__
30 : #include <linux/i2c.h>
31 : #include <linux/i2c-algo-bit.h>
32 : #include <linux/export.h>
33 : #endif
34 : #include <dev/pci/drm/drmP.h>
35 : #include "intel_drv.h"
36 : #include <dev/pci/drm/i915_drm.h>
37 : #include "i915_drv.h"
38 :
39 : #include <dev/i2c/i2cvar.h>
40 : #include <dev/i2c/i2c_bitbang.h>
41 :
42 : struct gmbus_pin {
43 : const char *name;
44 : int reg;
45 : };
46 :
47 : /* Map gmbus pin pairs to names and registers. */
48 : static const struct gmbus_pin gmbus_pins[] = {
49 : [GMBUS_PIN_SSC] = { "ssc", GPIOB },
50 : [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
51 : [GMBUS_PIN_PANEL] = { "panel", GPIOC },
52 : [GMBUS_PIN_DPC] = { "dpc", GPIOD },
53 : [GMBUS_PIN_DPB] = { "dpb", GPIOE },
54 : [GMBUS_PIN_DPD] = { "dpd", GPIOF },
55 : };
56 :
57 : static const struct gmbus_pin gmbus_pins_bdw[] = {
58 : [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
59 : [GMBUS_PIN_DPC] = { "dpc", GPIOD },
60 : [GMBUS_PIN_DPB] = { "dpb", GPIOE },
61 : [GMBUS_PIN_DPD] = { "dpd", GPIOF },
62 : };
63 :
64 : static const struct gmbus_pin gmbus_pins_skl[] = {
65 : [GMBUS_PIN_DPC] = { "dpc", GPIOD },
66 : [GMBUS_PIN_DPB] = { "dpb", GPIOE },
67 : [GMBUS_PIN_DPD] = { "dpd", GPIOF },
68 : };
69 :
70 : static const struct gmbus_pin gmbus_pins_bxt[] = {
71 : [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },
72 : [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },
73 : [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },
74 : };
75 :
76 : /* pin is expected to be valid */
77 0 : static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
78 : unsigned int pin)
79 : {
80 0 : if (IS_BROXTON(dev_priv))
81 0 : return &gmbus_pins_bxt[pin];
82 0 : else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
83 0 : return &gmbus_pins_skl[pin];
84 0 : else if (IS_BROADWELL(dev_priv))
85 0 : return &gmbus_pins_bdw[pin];
86 : else
87 0 : return &gmbus_pins[pin];
88 0 : }
89 :
90 0 : bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
91 : unsigned int pin)
92 : {
93 : unsigned int size;
94 :
95 0 : if (IS_BROXTON(dev_priv))
96 0 : size = ARRAY_SIZE(gmbus_pins_bxt);
97 0 : else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
98 0 : size = ARRAY_SIZE(gmbus_pins_skl);
99 0 : else if (IS_BROADWELL(dev_priv))
100 0 : size = ARRAY_SIZE(gmbus_pins_bdw);
101 : else
102 : size = ARRAY_SIZE(gmbus_pins);
103 :
104 0 : return pin < size && get_gmbus_pin(dev_priv, pin)->reg;
105 : }
106 :
107 : /* Intel GPIO access functions */
108 :
109 : #define I2C_RISEFALL_TIME 10
110 :
111 : static inline struct intel_gmbus *
112 0 : to_intel_gmbus(struct i2c_adapter *i2c)
113 : {
114 0 : return container_of(i2c, struct intel_gmbus, adapter);
115 : }
116 :
117 : void
118 0 : intel_i2c_reset(struct drm_device *dev)
119 : {
120 0 : struct drm_i915_private *dev_priv = dev->dev_private;
121 :
122 0 : I915_WRITE(GMBUS0, 0);
123 0 : I915_WRITE(GMBUS4, 0);
124 0 : }
125 :
126 0 : static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
127 : {
128 : u32 val;
129 :
130 : /* When using bit bashing for I2C, this bit needs to be set to 1 */
131 0 : if (!IS_PINEVIEW(dev_priv->dev))
132 0 : return;
133 :
134 0 : val = I915_READ(DSPCLK_GATE_D);
135 0 : if (enable)
136 0 : val |= DPCUNIT_CLOCK_GATE_DISABLE;
137 : else
138 0 : val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
139 0 : I915_WRITE(DSPCLK_GATE_D, val);
140 0 : }
141 :
142 0 : static u32 get_reserved(struct intel_gmbus *bus)
143 : {
144 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
145 0 : struct drm_device *dev = dev_priv->dev;
146 : u32 reserved = 0;
147 :
148 : /* On most chips, these bits must be preserved in software. */
149 0 : if (!IS_I830(dev) && !IS_845G(dev))
150 0 : reserved = I915_READ_NOTRACE(bus->gpio_reg) &
151 : (GPIO_DATA_PULLUP_DISABLE |
152 : GPIO_CLOCK_PULLUP_DISABLE);
153 :
154 0 : return reserved;
155 : }
156 :
157 0 : static int get_clock(void *data)
158 : {
159 0 : struct intel_gmbus *bus = data;
160 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
161 0 : u32 reserved = get_reserved(bus);
162 0 : I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
163 0 : I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
164 0 : return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
165 : }
166 :
167 0 : static int get_data(void *data)
168 : {
169 0 : struct intel_gmbus *bus = data;
170 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
171 0 : u32 reserved = get_reserved(bus);
172 0 : I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
173 0 : I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
174 0 : return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
175 : }
176 :
177 0 : static void set_clock(void *data, int state_high)
178 : {
179 0 : struct intel_gmbus *bus = data;
180 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
181 0 : u32 reserved = get_reserved(bus);
182 : u32 clock_bits;
183 :
184 0 : if (state_high)
185 0 : clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
186 : else
187 : clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
188 : GPIO_CLOCK_VAL_MASK;
189 :
190 0 : I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
191 0 : POSTING_READ(bus->gpio_reg);
192 0 : }
193 :
194 0 : static void set_data(void *data, int state_high)
195 : {
196 0 : struct intel_gmbus *bus = data;
197 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
198 0 : u32 reserved = get_reserved(bus);
199 : u32 data_bits;
200 :
201 0 : if (state_high)
202 0 : data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
203 : else
204 : data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
205 : GPIO_DATA_VAL_MASK;
206 :
207 0 : I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
208 0 : POSTING_READ(bus->gpio_reg);
209 0 : }
210 :
211 : static int
212 0 : intel_gpio_pre_xfer(struct i2c_adapter *adapter)
213 : {
214 0 : struct intel_gmbus *bus = container_of(adapter,
215 : struct intel_gmbus,
216 : adapter);
217 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
218 :
219 0 : intel_i2c_reset(dev_priv->dev);
220 0 : intel_i2c_quirk_set(dev_priv, true);
221 0 : set_data(bus, 1);
222 0 : set_clock(bus, 1);
223 0 : udelay(I2C_RISEFALL_TIME);
224 0 : return 0;
225 : }
226 :
227 : static void
228 0 : intel_gpio_post_xfer(struct i2c_adapter *adapter)
229 : {
230 0 : struct intel_gmbus *bus = container_of(adapter,
231 : struct intel_gmbus,
232 : adapter);
233 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
234 :
235 0 : set_data(bus, 1);
236 0 : set_clock(bus, 1);
237 0 : intel_i2c_quirk_set(dev_priv, false);
238 0 : }
239 :
240 : void intel_bb_set_bits(void *, uint32_t);
241 : void intel_bb_set_dir(void *, uint32_t);
242 : uint32_t intel_bb_read_bits(void *);
243 :
244 : int intel_acquire_bus(void *, int);
245 : void intel_release_bus(void *, int);
246 : int intel_send_start(void *, int);
247 : int intel_send_stop(void *, int);
248 : int intel_initiate_xfer(void *, i2c_addr_t, int);
249 : int intel_read_byte(void *, u_int8_t *, int);
250 : int intel_write_byte(void *, u_int8_t, int);
251 :
252 : #define INTEL_BB_SDA (1 << I2C_BIT_SDA)
253 : #define INTEL_BB_SCL (1 << I2C_BIT_SCL)
254 :
255 : struct i2c_bitbang_ops intel_bbops = {
256 : intel_bb_set_bits,
257 : intel_bb_set_dir,
258 : intel_bb_read_bits,
259 : { INTEL_BB_SDA, INTEL_BB_SCL, 0, 0 }
260 : };
261 :
262 : void
263 0 : intel_bb_set_bits(void *cookie, uint32_t bits)
264 : {
265 0 : set_clock(cookie, bits & INTEL_BB_SCL);
266 0 : set_data(cookie, bits & INTEL_BB_SDA);
267 0 : }
268 :
269 : void
270 0 : intel_bb_set_dir(void *cookie, uint32_t bits)
271 : {
272 0 : }
273 :
274 : uint32_t
275 0 : intel_bb_read_bits(void *cookie)
276 : {
277 : uint32_t bits = 0;
278 :
279 0 : if (get_clock(cookie))
280 0 : bits |= INTEL_BB_SCL;
281 0 : if (get_data(cookie))
282 0 : bits |= INTEL_BB_SDA;
283 :
284 0 : return bits;
285 : }
286 :
287 : int
288 0 : intel_acquire_bus(void *cookie, int flags)
289 : {
290 0 : struct intel_gmbus *bus = cookie;
291 :
292 0 : intel_gpio_pre_xfer(&bus->adapter);
293 0 : return (0);
294 : }
295 :
296 : void
297 0 : intel_release_bus(void *cookie, int flags)
298 : {
299 0 : struct intel_gmbus *bus = cookie;
300 :
301 0 : intel_gpio_post_xfer(&bus->adapter);
302 0 : }
303 :
304 : int
305 0 : intel_send_start(void *cookie, int flags)
306 : {
307 0 : return (i2c_bitbang_send_start(cookie, flags, &intel_bbops));
308 : }
309 :
310 : int
311 0 : intel_send_stop(void *cookie, int flags)
312 : {
313 0 : return (i2c_bitbang_send_stop(cookie, flags, &intel_bbops));
314 : }
315 :
316 : int
317 0 : intel_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
318 : {
319 0 : return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &intel_bbops));
320 : }
321 :
322 : int
323 0 : intel_read_byte(void *cookie, u_int8_t *bytep, int flags)
324 : {
325 0 : return (i2c_bitbang_read_byte(cookie, bytep, flags, &intel_bbops));
326 : }
327 :
328 : int
329 0 : intel_write_byte(void *cookie, u_int8_t byte, int flags)
330 : {
331 0 : return (i2c_bitbang_write_byte(cookie, byte, flags, &intel_bbops));
332 : }
333 :
334 : static void
335 0 : intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
336 : {
337 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
338 : struct i2c_algo_bit_data *algo;
339 :
340 0 : algo = &bus->bit_algo;
341 :
342 0 : bus->gpio_reg = dev_priv->gpio_mmio_base +
343 0 : get_gmbus_pin(dev_priv, pin)->reg;
344 :
345 0 : bus->adapter.algo_data = algo;
346 : #ifdef __linux__
347 : algo->setsda = set_data;
348 : algo->setscl = set_clock;
349 : algo->getsda = get_data;
350 : algo->getscl = get_clock;
351 : algo->pre_xfer = intel_gpio_pre_xfer;
352 : algo->post_xfer = intel_gpio_post_xfer;
353 : algo->udelay = I2C_RISEFALL_TIME;
354 : algo->timeout = usecs_to_jiffies(2200);
355 : algo->data = bus;
356 : #else
357 0 : algo->ic.ic_cookie = bus;
358 0 : algo->ic.ic_acquire_bus = intel_acquire_bus;
359 0 : algo->ic.ic_release_bus = intel_release_bus;
360 0 : algo->ic.ic_send_start = intel_send_start;
361 0 : algo->ic.ic_send_stop = intel_send_stop;
362 0 : algo->ic.ic_initiate_xfer = intel_initiate_xfer;
363 0 : algo->ic.ic_read_byte = intel_read_byte;
364 0 : algo->ic.ic_write_byte = intel_write_byte;
365 : #endif
366 0 : }
367 :
368 : static int
369 0 : gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
370 : u32 gmbus2_status,
371 : u32 gmbus4_irq_en)
372 : {
373 : int i;
374 : u32 gmbus2 = 0;
375 0 : DEFINE_WAIT(wait);
376 :
377 0 : if (!HAS_GMBUS_IRQ(dev_priv->dev) || cold)
378 0 : gmbus4_irq_en = 0;
379 :
380 : /* Important: The hw handles only the first bit, so set only one! Since
381 : * we also need to check for NAKs besides the hw ready/idle signal, we
382 : * need to wake up periodically and check that ourselves. */
383 0 : I915_WRITE(GMBUS4, gmbus4_irq_en);
384 :
385 0 : for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
386 0 : prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
387 : TASK_UNINTERRUPTIBLE);
388 :
389 0 : gmbus2 = I915_READ_NOTRACE(GMBUS2);
390 0 : if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
391 : break;
392 :
393 0 : schedule_timeout(1);
394 : }
395 0 : finish_wait(&dev_priv->gmbus_wait_queue, &wait);
396 :
397 0 : I915_WRITE(GMBUS4, 0);
398 :
399 0 : if (gmbus2 & GMBUS_SATOER)
400 0 : return -ENXIO;
401 0 : if (gmbus2 & gmbus2_status)
402 0 : return 0;
403 0 : return -ETIMEDOUT;
404 0 : }
405 :
406 : static int
407 0 : gmbus_wait_idle(struct drm_i915_private *dev_priv)
408 : {
409 : int ret;
410 :
411 : #define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
412 :
413 0 : if (!HAS_GMBUS_IRQ(dev_priv->dev) || cold)
414 0 : return wait_for(C, 10);
415 :
416 : /* Important: The hw handles only the first bit, so set only one! */
417 0 : I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
418 :
419 0 : ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
420 : msecs_to_jiffies_timeout(10));
421 :
422 0 : I915_WRITE(GMBUS4, 0);
423 :
424 0 : if (ret)
425 0 : return 0;
426 : else
427 0 : return -ETIMEDOUT;
428 : #undef C
429 0 : }
430 :
431 : static int
432 0 : gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
433 : unsigned short addr, u8 *buf, unsigned int len,
434 : u32 gmbus1_index)
435 : {
436 0 : I915_WRITE(GMBUS1,
437 : gmbus1_index |
438 : GMBUS_CYCLE_WAIT |
439 : (len << GMBUS_BYTE_COUNT_SHIFT) |
440 : (addr << GMBUS_SLAVE_ADDR_SHIFT) |
441 : GMBUS_SLAVE_READ | GMBUS_SW_RDY);
442 0 : while (len) {
443 : int ret;
444 : u32 val, loop = 0;
445 :
446 0 : ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
447 : GMBUS_HW_RDY_EN);
448 0 : if (ret)
449 0 : return ret;
450 :
451 0 : val = I915_READ(GMBUS3);
452 0 : do {
453 0 : *buf++ = val & 0xff;
454 0 : val >>= 8;
455 0 : } while (--len && ++loop < 4);
456 0 : }
457 :
458 0 : return 0;
459 0 : }
460 :
461 : static int
462 0 : gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
463 : u32 gmbus1_index)
464 : {
465 0 : u8 *buf = msg->buf;
466 0 : unsigned int rx_size = msg->len;
467 : unsigned int len;
468 : int ret;
469 :
470 0 : do {
471 0 : len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
472 :
473 0 : ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
474 : buf, len, gmbus1_index);
475 0 : if (ret)
476 0 : return ret;
477 :
478 0 : rx_size -= len;
479 0 : buf += len;
480 0 : } while (rx_size != 0);
481 :
482 0 : return 0;
483 0 : }
484 :
485 : static int
486 0 : gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
487 : unsigned short addr, u8 *buf, unsigned int len)
488 : {
489 : unsigned int chunk_size = len;
490 : u32 val, loop;
491 :
492 : val = loop = 0;
493 0 : while (len && loop < 4) {
494 0 : val |= *buf++ << (8 * loop++);
495 0 : len -= 1;
496 : }
497 :
498 0 : I915_WRITE(GMBUS3, val);
499 0 : I915_WRITE(GMBUS1,
500 : GMBUS_CYCLE_WAIT |
501 : (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
502 : (addr << GMBUS_SLAVE_ADDR_SHIFT) |
503 : GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
504 0 : while (len) {
505 : int ret;
506 :
507 : val = loop = 0;
508 0 : do {
509 0 : val |= *buf++ << (8 * loop);
510 0 : } while (--len && ++loop < 4);
511 :
512 0 : I915_WRITE(GMBUS3, val);
513 :
514 0 : ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
515 : GMBUS_HW_RDY_EN);
516 0 : if (ret)
517 0 : return ret;
518 0 : }
519 :
520 0 : return 0;
521 0 : }
522 :
523 : static int
524 0 : gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
525 : {
526 0 : u8 *buf = msg->buf;
527 0 : unsigned int tx_size = msg->len;
528 : unsigned int len;
529 : int ret;
530 :
531 0 : do {
532 0 : len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
533 :
534 0 : ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
535 0 : if (ret)
536 0 : return ret;
537 :
538 0 : buf += len;
539 0 : tx_size -= len;
540 0 : } while (tx_size != 0);
541 :
542 0 : return 0;
543 0 : }
544 :
545 : /*
546 : * The gmbus controller can combine a 1 or 2 byte write with a read that
547 : * immediately follows it by using an "INDEX" cycle.
548 : */
549 : static bool
550 0 : gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
551 : {
552 0 : return (i + 1 < num &&
553 0 : msgs[i].addr == msgs[i + 1].addr &&
554 0 : !(msgs[i].flags & I2C_M_RD) &&
555 0 : (msgs[i].len == 1 || msgs[i].len == 2) &&
556 0 : (msgs[i + 1].flags & I2C_M_RD));
557 : }
558 :
559 : static int
560 0 : gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
561 : {
562 : u32 gmbus1_index = 0;
563 : u32 gmbus5 = 0;
564 : int ret;
565 :
566 0 : if (msgs[0].len == 2)
567 0 : gmbus5 = GMBUS_2BYTE_INDEX_EN |
568 0 : msgs[0].buf[1] | (msgs[0].buf[0] << 8);
569 0 : if (msgs[0].len == 1)
570 0 : gmbus1_index = GMBUS_CYCLE_INDEX |
571 0 : (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
572 :
573 : /* GMBUS5 holds 16-bit index */
574 0 : if (gmbus5)
575 0 : I915_WRITE(GMBUS5, gmbus5);
576 :
577 0 : ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
578 :
579 : /* Clear GMBUS5 after each index transfer */
580 0 : if (gmbus5)
581 0 : I915_WRITE(GMBUS5, 0);
582 :
583 0 : return ret;
584 : }
585 :
586 : static int
587 0 : gmbus_xfer(struct i2c_adapter *adapter,
588 : struct i2c_msg *msgs,
589 : int num)
590 : {
591 0 : struct intel_gmbus *bus = container_of(adapter,
592 : struct intel_gmbus,
593 : adapter);
594 0 : struct drm_i915_private *dev_priv = bus->dev_priv;
595 : int i = 0, inc, try = 0;
596 : int ret = 0;
597 :
598 0 : intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
599 0 : mutex_lock(&dev_priv->gmbus_mutex);
600 :
601 0 : if (bus->force_bit) {
602 0 : ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
603 0 : goto out;
604 : }
605 :
606 : retry:
607 0 : I915_WRITE(GMBUS0, bus->reg0);
608 :
609 0 : for (; i < num; i += inc) {
610 : inc = 1;
611 0 : if (gmbus_is_index_read(msgs, i, num)) {
612 0 : ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
613 : inc = 2; /* an index read is two msgs */
614 0 : } else if (msgs[i].flags & I2C_M_RD) {
615 0 : ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
616 0 : } else {
617 0 : ret = gmbus_xfer_write(dev_priv, &msgs[i]);
618 : }
619 :
620 0 : if (ret == -ETIMEDOUT)
621 : goto timeout;
622 0 : if (ret == -ENXIO)
623 : goto clear_err;
624 :
625 0 : ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
626 : GMBUS_HW_WAIT_EN);
627 0 : if (ret == -ENXIO)
628 : goto clear_err;
629 0 : if (ret)
630 : goto timeout;
631 : }
632 :
633 : /* Generate a STOP condition on the bus. Note that gmbus can't generata
634 : * a STOP on the very first cycle. To simplify the code we
635 : * unconditionally generate the STOP condition with an additional gmbus
636 : * cycle. */
637 0 : I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
638 :
639 : /* Mark the GMBUS interface as disabled after waiting for idle.
640 : * We will re-enable it at the start of the next xfer,
641 : * till then let it sleep.
642 : */
643 0 : if (gmbus_wait_idle(dev_priv)) {
644 : DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
645 : adapter->name);
646 : ret = -ETIMEDOUT;
647 0 : }
648 0 : I915_WRITE(GMBUS0, 0);
649 0 : ret = ret ?: i;
650 0 : goto out;
651 :
652 : clear_err:
653 : /*
654 : * Wait for bus to IDLE before clearing NAK.
655 : * If we clear the NAK while bus is still active, then it will stay
656 : * active and the next transaction may fail.
657 : *
658 : * If no ACK is received during the address phase of a transaction, the
659 : * adapter must report -ENXIO. It is not clear what to return if no ACK
660 : * is received at other times. But we have to be careful to not return
661 : * spurious -ENXIO because that will prevent i2c and drm edid functions
662 : * from retrying. So return -ENXIO only when gmbus properly quiescents -
663 : * timing out seems to happen when there _is_ a ddc chip present, but
664 : * it's slow responding and only answers on the 2nd retry.
665 : */
666 : ret = -ENXIO;
667 0 : if (gmbus_wait_idle(dev_priv)) {
668 : DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
669 : adapter->name);
670 : ret = -ETIMEDOUT;
671 0 : }
672 :
673 : /* Toggle the Software Clear Interrupt bit. This has the effect
674 : * of resetting the GMBUS controller and so clearing the
675 : * BUS_ERROR raised by the slave's NAK.
676 : */
677 0 : I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT);
678 0 : I915_WRITE(GMBUS1, 0);
679 0 : I915_WRITE(GMBUS0, 0);
680 :
681 : DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
682 : adapter->name, msgs[i].addr,
683 : (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
684 :
685 : /*
686 : * Passive adapters sometimes NAK the first probe. Retry the first
687 : * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
688 : * has retries internally. See also the retry loop in
689 : * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
690 : */
691 0 : if (ret == -ENXIO && i == 0 && try++ == 0) {
692 : DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
693 : adapter->name);
694 0 : goto retry;
695 : }
696 :
697 : goto out;
698 :
699 : timeout:
700 : DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
701 : bus->adapter.name, bus->reg0 & 0xff);
702 0 : I915_WRITE(GMBUS0, 0);
703 :
704 : /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
705 0 : bus->force_bit = 1;
706 0 : ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
707 :
708 : out:
709 0 : mutex_unlock(&dev_priv->gmbus_mutex);
710 :
711 0 : intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
712 :
713 0 : return ret;
714 : }
715 :
716 0 : static u32 gmbus_func(struct i2c_adapter *adapter)
717 : {
718 0 : return i2c_bit_algo.functionality(adapter) &
719 : (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
720 : /* I2C_FUNC_10BIT_ADDR | */
721 : I2C_FUNC_SMBUS_READ_BLOCK_DATA |
722 : I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
723 : }
724 :
725 : static const struct i2c_algorithm gmbus_algorithm = {
726 : .master_xfer = gmbus_xfer,
727 : .functionality = gmbus_func
728 : };
729 :
730 : /**
731 : * intel_gmbus_setup - instantiate all Intel i2c GMBuses
732 : * @dev: DRM device
733 : */
734 0 : int intel_setup_gmbus(struct drm_device *dev)
735 : {
736 0 : struct drm_i915_private *dev_priv = dev->dev_private;
737 : struct intel_gmbus *bus;
738 : unsigned int pin;
739 : int ret;
740 :
741 0 : if (HAS_PCH_NOP(dev))
742 0 : return 0;
743 0 : else if (HAS_PCH_SPLIT(dev))
744 0 : dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
745 0 : else if (IS_VALLEYVIEW(dev))
746 0 : dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
747 : else
748 0 : dev_priv->gpio_mmio_base = 0;
749 :
750 0 : rw_init(&dev_priv->gmbus_mutex, "gmbus");
751 0 : init_waitqueue_head(&dev_priv->gmbus_wait_queue);
752 :
753 0 : for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
754 0 : if (!intel_gmbus_is_valid_pin(dev_priv, pin))
755 : continue;
756 :
757 0 : bus = &dev_priv->gmbus[pin];
758 :
759 : #ifdef notyet
760 : bus->adapter.owner = THIS_MODULE;
761 : bus->adapter.class = I2C_CLASS_DDC;
762 : #endif
763 0 : snprintf(bus->adapter.name,
764 : sizeof(bus->adapter.name),
765 : "i915 gmbus %s",
766 0 : get_gmbus_pin(dev_priv, pin)->name);
767 :
768 : #ifdef notyet
769 : bus->adapter.dev.parent = &dev->pdev->dev;
770 : #endif
771 0 : bus->dev_priv = dev_priv;
772 :
773 0 : bus->adapter.algo = &gmbus_algorithm;
774 :
775 : /* By default use a conservative clock rate */
776 0 : bus->reg0 = pin | GMBUS_RATE_100KHZ;
777 :
778 : /* gmbus seems to be broken on i830 */
779 0 : if (IS_I830(dev))
780 0 : bus->force_bit = 1;
781 :
782 0 : intel_gpio_setup(bus, pin);
783 :
784 : ret = i2c_add_adapter(&bus->adapter);
785 0 : if (ret)
786 : goto err;
787 : }
788 :
789 0 : intel_i2c_reset(dev_priv->dev);
790 :
791 0 : return 0;
792 :
793 : err:
794 0 : while (pin--) {
795 0 : if (!intel_gmbus_is_valid_pin(dev_priv, pin))
796 0 : continue;
797 :
798 0 : bus = &dev_priv->gmbus[pin];
799 : i2c_del_adapter(&bus->adapter);
800 : }
801 0 : return ret;
802 0 : }
803 :
804 0 : struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
805 : unsigned int pin)
806 : {
807 0 : if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
808 0 : return NULL;
809 :
810 0 : return &dev_priv->gmbus[pin].adapter;
811 0 : }
812 :
813 0 : void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
814 : {
815 0 : struct intel_gmbus *bus = to_intel_gmbus(adapter);
816 :
817 0 : bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
818 0 : }
819 :
820 0 : void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
821 : {
822 0 : struct intel_gmbus *bus = to_intel_gmbus(adapter);
823 :
824 0 : bus->force_bit += force_bit ? 1 : -1;
825 : DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
826 : force_bit ? "en" : "dis", adapter->name,
827 : bus->force_bit);
828 0 : }
829 :
830 0 : void intel_teardown_gmbus(struct drm_device *dev)
831 : {
832 0 : struct drm_i915_private *dev_priv = dev->dev_private;
833 : struct intel_gmbus *bus;
834 : unsigned int pin;
835 :
836 0 : for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
837 0 : if (!intel_gmbus_is_valid_pin(dev_priv, pin))
838 : continue;
839 :
840 0 : bus = &dev_priv->gmbus[pin];
841 : i2c_del_adapter(&bus->adapter);
842 0 : }
843 0 : }
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