Line data Source code
1 : /*
2 : * Copyright © 2012-2014 Intel Corporation
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice (including the next
12 : * paragraph) shall be included in all copies or substantial portions of the
13 : * Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 : * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 : * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 : * IN THE SOFTWARE.
22 : *
23 : * Authors:
24 : * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 : * Daniel Vetter <daniel.vetter@ffwll.ch>
26 : *
27 : */
28 :
29 : #ifdef __linux__
30 : #include <linux/pm_runtime.h>
31 : #include <linux/vgaarb.h>
32 : #endif
33 :
34 : #include "i915_drv.h"
35 : #include "intel_drv.h"
36 :
37 : /**
38 : * DOC: runtime pm
39 : *
40 : * The i915 driver supports dynamic enabling and disabling of entire hardware
41 : * blocks at runtime. This is especially important on the display side where
42 : * software is supposed to control many power gates manually on recent hardware,
43 : * since on the GT side a lot of the power management is done by the hardware.
44 : * But even there some manual control at the device level is required.
45 : *
46 : * Since i915 supports a diverse set of platforms with a unified codebase and
47 : * hardware engineers just love to shuffle functionality around between power
48 : * domains there's a sizeable amount of indirection required. This file provides
49 : * generic functions to the driver for grabbing and releasing references for
50 : * abstract power domains. It then maps those to the actual power wells
51 : * present for a given platform.
52 : */
53 :
54 : #define GEN9_ENABLE_DC5(dev) 0
55 : #define SKL_ENABLE_DC6(dev) (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
56 :
57 : #define for_each_power_well(i, power_well, domain_mask, power_domains) \
58 : for (i = 0; \
59 : i < (power_domains)->power_well_count && \
60 : ((power_well) = &(power_domains)->power_wells[i]); \
61 : i++) \
62 : if ((power_well)->domains & (domain_mask))
63 :
64 : #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
65 : for (i = (power_domains)->power_well_count - 1; \
66 : i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
67 : i--) \
68 : if ((power_well)->domains & (domain_mask))
69 :
70 : bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
71 : int power_well_id);
72 :
73 0 : static void intel_power_well_enable(struct drm_i915_private *dev_priv,
74 : struct i915_power_well *power_well)
75 : {
76 : DRM_DEBUG_KMS("enabling %s\n", power_well->name);
77 0 : power_well->ops->enable(dev_priv, power_well);
78 0 : power_well->hw_enabled = true;
79 0 : }
80 :
81 0 : static void intel_power_well_disable(struct drm_i915_private *dev_priv,
82 : struct i915_power_well *power_well)
83 : {
84 : DRM_DEBUG_KMS("disabling %s\n", power_well->name);
85 0 : power_well->hw_enabled = false;
86 0 : power_well->ops->disable(dev_priv, power_well);
87 0 : }
88 :
89 : /*
90 : * We should only use the power well if we explicitly asked the hardware to
91 : * enable it, so check if it's enabled and also check if we've requested it to
92 : * be enabled.
93 : */
94 0 : static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
95 : struct i915_power_well *power_well)
96 : {
97 0 : return I915_READ(HSW_PWR_WELL_DRIVER) ==
98 : (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
99 : }
100 :
101 : /**
102 : * __intel_display_power_is_enabled - unlocked check for a power domain
103 : * @dev_priv: i915 device instance
104 : * @domain: power domain to check
105 : *
106 : * This is the unlocked version of intel_display_power_is_enabled() and should
107 : * only be used from error capture and recovery code where deadlocks are
108 : * possible.
109 : *
110 : * Returns:
111 : * True when the power domain is enabled, false otherwise.
112 : */
113 0 : bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
114 : enum intel_display_power_domain domain)
115 : {
116 : struct i915_power_domains *power_domains;
117 : struct i915_power_well *power_well;
118 : bool is_enabled;
119 : int i;
120 :
121 0 : if (dev_priv->pm.suspended)
122 0 : return false;
123 :
124 0 : power_domains = &dev_priv->power_domains;
125 :
126 : is_enabled = true;
127 :
128 0 : for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
129 0 : if (power_well->always_on)
130 : continue;
131 :
132 0 : if (!power_well->hw_enabled) {
133 : is_enabled = false;
134 0 : break;
135 : }
136 : }
137 :
138 0 : return is_enabled;
139 0 : }
140 :
141 : /**
142 : * intel_display_power_is_enabled - check for a power domain
143 : * @dev_priv: i915 device instance
144 : * @domain: power domain to check
145 : *
146 : * This function can be used to check the hw power domain state. It is mostly
147 : * used in hardware state readout functions. Everywhere else code should rely
148 : * upon explicit power domain reference counting to ensure that the hardware
149 : * block is powered up before accessing it.
150 : *
151 : * Callers must hold the relevant modesetting locks to ensure that concurrent
152 : * threads can't disable the power well while the caller tries to read a few
153 : * registers.
154 : *
155 : * Returns:
156 : * True when the power domain is enabled, false otherwise.
157 : */
158 0 : bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
159 : enum intel_display_power_domain domain)
160 : {
161 : struct i915_power_domains *power_domains;
162 : bool ret;
163 :
164 0 : power_domains = &dev_priv->power_domains;
165 :
166 0 : mutex_lock(&power_domains->lock);
167 0 : ret = __intel_display_power_is_enabled(dev_priv, domain);
168 0 : mutex_unlock(&power_domains->lock);
169 :
170 0 : return ret;
171 : }
172 :
173 : /**
174 : * intel_display_set_init_power - set the initial power domain state
175 : * @dev_priv: i915 device instance
176 : * @enable: whether to enable or disable the initial power domain state
177 : *
178 : * For simplicity our driver load/unload and system suspend/resume code assumes
179 : * that all power domains are always enabled. This functions controls the state
180 : * of this little hack. While the initial power domain state is enabled runtime
181 : * pm is effectively disabled.
182 : */
183 0 : void intel_display_set_init_power(struct drm_i915_private *dev_priv,
184 : bool enable)
185 : {
186 0 : if (dev_priv->power_domains.init_power_on == enable)
187 : return;
188 :
189 0 : if (enable)
190 0 : intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
191 : else
192 0 : intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
193 :
194 0 : dev_priv->power_domains.init_power_on = enable;
195 0 : }
196 :
197 : /*
198 : * Starting with Haswell, we have a "Power Down Well" that can be turned off
199 : * when not needed anymore. We have 4 registers that can request the power well
200 : * to be enabled, and it will only be disabled if none of the registers is
201 : * requesting it to be enabled.
202 : */
203 0 : static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
204 : {
205 0 : struct drm_device *dev = dev_priv->dev;
206 :
207 : /*
208 : * After we re-enable the power well, if we touch VGA register 0x3d5
209 : * we'll get unclaimed register interrupts. This stops after we write
210 : * anything to the VGA MSR register. The vgacon module uses this
211 : * register all the time, so if we unbind our driver and, as a
212 : * consequence, bind vgacon, we'll get stuck in an infinite loop at
213 : * console_unlock(). So make here we touch the VGA MSR register, making
214 : * sure vgacon can keep working normally without triggering interrupts
215 : * and error messages.
216 : */
217 0 : vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
218 : #ifdef __linux__
219 : outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
220 : #else
221 0 : outb(VGA_MSR_WRITE, inb(VGA_MSR_READ));
222 : #endif
223 0 : vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
224 :
225 0 : if (IS_BROADWELL(dev))
226 0 : gen8_irq_power_well_post_enable(dev_priv,
227 : 1 << PIPE_C | 1 << PIPE_B);
228 0 : }
229 :
230 0 : static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
231 : struct i915_power_well *power_well)
232 : {
233 0 : struct drm_device *dev = dev_priv->dev;
234 :
235 : /*
236 : * After we re-enable the power well, if we touch VGA register 0x3d5
237 : * we'll get unclaimed register interrupts. This stops after we write
238 : * anything to the VGA MSR register. The vgacon module uses this
239 : * register all the time, so if we unbind our driver and, as a
240 : * consequence, bind vgacon, we'll get stuck in an infinite loop at
241 : * console_unlock(). So make here we touch the VGA MSR register, making
242 : * sure vgacon can keep working normally without triggering interrupts
243 : * and error messages.
244 : */
245 0 : if (power_well->data == SKL_DISP_PW_2) {
246 0 : vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
247 : #ifdef __linux__
248 : outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
249 : #else
250 0 : outb(VGA_MSR_WRITE, inb(VGA_MSR_READ));
251 : #endif
252 0 : vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
253 :
254 0 : gen8_irq_power_well_post_enable(dev_priv,
255 : 1 << PIPE_C | 1 << PIPE_B);
256 0 : }
257 :
258 0 : if (power_well->data == SKL_DISP_PW_1) {
259 0 : if (!dev_priv->power_domains.initializing)
260 0 : intel_prepare_ddi(dev);
261 0 : gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
262 0 : }
263 0 : }
264 :
265 0 : static void hsw_set_power_well(struct drm_i915_private *dev_priv,
266 : struct i915_power_well *power_well, bool enable)
267 : {
268 : bool is_enabled, enable_requested;
269 : uint32_t tmp;
270 :
271 0 : tmp = I915_READ(HSW_PWR_WELL_DRIVER);
272 0 : is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
273 0 : enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
274 :
275 0 : if (enable) {
276 0 : if (!enable_requested)
277 0 : I915_WRITE(HSW_PWR_WELL_DRIVER,
278 : HSW_PWR_WELL_ENABLE_REQUEST);
279 :
280 0 : if (!is_enabled) {
281 : DRM_DEBUG_KMS("Enabling power well\n");
282 0 : if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
283 : HSW_PWR_WELL_STATE_ENABLED), 20))
284 0 : DRM_ERROR("Timeout enabling power well\n");
285 0 : hsw_power_well_post_enable(dev_priv);
286 0 : }
287 :
288 : } else {
289 0 : if (enable_requested) {
290 0 : I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
291 0 : POSTING_READ(HSW_PWR_WELL_DRIVER);
292 : DRM_DEBUG_KMS("Requesting to disable the power well\n");
293 0 : }
294 : }
295 0 : }
296 :
297 : #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
298 : BIT(POWER_DOMAIN_TRANSCODER_A) | \
299 : BIT(POWER_DOMAIN_PIPE_B) | \
300 : BIT(POWER_DOMAIN_TRANSCODER_B) | \
301 : BIT(POWER_DOMAIN_PIPE_C) | \
302 : BIT(POWER_DOMAIN_TRANSCODER_C) | \
303 : BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
304 : BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
305 : BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
306 : BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
307 : BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
308 : BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
309 : BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
310 : BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
311 : BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
312 : BIT(POWER_DOMAIN_AUX_B) | \
313 : BIT(POWER_DOMAIN_AUX_C) | \
314 : BIT(POWER_DOMAIN_AUX_D) | \
315 : BIT(POWER_DOMAIN_AUDIO) | \
316 : BIT(POWER_DOMAIN_VGA) | \
317 : BIT(POWER_DOMAIN_INIT))
318 : #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
319 : SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
320 : BIT(POWER_DOMAIN_PLLS) | \
321 : BIT(POWER_DOMAIN_PIPE_A) | \
322 : BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
323 : BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
324 : BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
325 : BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
326 : BIT(POWER_DOMAIN_AUX_A) | \
327 : BIT(POWER_DOMAIN_INIT))
328 : #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
329 : BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
330 : BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
331 : BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
332 : BIT(POWER_DOMAIN_INIT))
333 : #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
334 : BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
335 : BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
336 : BIT(POWER_DOMAIN_INIT))
337 : #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
338 : BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
339 : BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
340 : BIT(POWER_DOMAIN_INIT))
341 : #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
342 : BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
343 : BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
344 : BIT(POWER_DOMAIN_INIT))
345 : #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \
346 : SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
347 : BIT(POWER_DOMAIN_PLLS) | \
348 : BIT(POWER_DOMAIN_INIT))
349 : #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
350 : (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
351 : SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
352 : SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \
353 : SKL_DISPLAY_DDI_B_POWER_DOMAINS | \
354 : SKL_DISPLAY_DDI_C_POWER_DOMAINS | \
355 : SKL_DISPLAY_DDI_D_POWER_DOMAINS | \
356 : SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \
357 : BIT(POWER_DOMAIN_INIT))
358 :
359 : #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
360 : BIT(POWER_DOMAIN_TRANSCODER_A) | \
361 : BIT(POWER_DOMAIN_PIPE_B) | \
362 : BIT(POWER_DOMAIN_TRANSCODER_B) | \
363 : BIT(POWER_DOMAIN_PIPE_C) | \
364 : BIT(POWER_DOMAIN_TRANSCODER_C) | \
365 : BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
366 : BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
367 : BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
368 : BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
369 : BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
370 : BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
371 : BIT(POWER_DOMAIN_AUX_B) | \
372 : BIT(POWER_DOMAIN_AUX_C) | \
373 : BIT(POWER_DOMAIN_AUDIO) | \
374 : BIT(POWER_DOMAIN_VGA) | \
375 : BIT(POWER_DOMAIN_GMBUS) | \
376 : BIT(POWER_DOMAIN_INIT))
377 : #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
378 : BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
379 : BIT(POWER_DOMAIN_PIPE_A) | \
380 : BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
381 : BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
382 : BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
383 : BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
384 : BIT(POWER_DOMAIN_AUX_A) | \
385 : BIT(POWER_DOMAIN_PLLS) | \
386 : BIT(POWER_DOMAIN_INIT))
387 : #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
388 : (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
389 : BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
390 : BIT(POWER_DOMAIN_INIT))
391 :
392 0 : static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
393 : {
394 0 : struct drm_device *dev = dev_priv->dev;
395 :
396 0 : WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
397 0 : WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
398 : "DC9 already programmed to be enabled.\n");
399 0 : WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
400 : "DC5 still not disabled to enable DC9.\n");
401 0 : WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
402 0 : WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
403 :
404 : /*
405 : * TODO: check for the following to verify the conditions to enter DC9
406 : * state are satisfied:
407 : * 1] Check relevant display engine registers to verify if mode set
408 : * disable sequence was followed.
409 : * 2] Check if display uninitialize sequence is initialized.
410 : */
411 0 : }
412 :
413 0 : static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
414 : {
415 0 : WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
416 0 : WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
417 : "DC9 already programmed to be disabled.\n");
418 0 : WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
419 : "DC5 still not disabled.\n");
420 :
421 : /*
422 : * TODO: check for the following to verify DC9 state was indeed
423 : * entered before programming to disable it:
424 : * 1] Check relevant display engine registers to verify if mode
425 : * set disable sequence was followed.
426 : * 2] Check if display uninitialize sequence is initialized.
427 : */
428 0 : }
429 :
430 0 : void bxt_enable_dc9(struct drm_i915_private *dev_priv)
431 : {
432 : uint32_t val;
433 :
434 0 : assert_can_enable_dc9(dev_priv);
435 :
436 : DRM_DEBUG_KMS("Enabling DC9\n");
437 :
438 0 : val = I915_READ(DC_STATE_EN);
439 0 : val |= DC_STATE_EN_DC9;
440 0 : I915_WRITE(DC_STATE_EN, val);
441 0 : POSTING_READ(DC_STATE_EN);
442 0 : }
443 :
444 0 : void bxt_disable_dc9(struct drm_i915_private *dev_priv)
445 : {
446 : uint32_t val;
447 :
448 0 : assert_can_disable_dc9(dev_priv);
449 :
450 : DRM_DEBUG_KMS("Disabling DC9\n");
451 :
452 0 : val = I915_READ(DC_STATE_EN);
453 0 : val &= ~DC_STATE_EN_DC9;
454 0 : I915_WRITE(DC_STATE_EN, val);
455 0 : POSTING_READ(DC_STATE_EN);
456 0 : }
457 :
458 0 : static void gen9_set_dc_state_debugmask_memory_up(
459 : struct drm_i915_private *dev_priv)
460 : {
461 : uint32_t val;
462 :
463 : /* The below bit doesn't need to be cleared ever afterwards */
464 0 : val = I915_READ(DC_STATE_DEBUG);
465 0 : if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
466 0 : val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
467 0 : I915_WRITE(DC_STATE_DEBUG, val);
468 0 : POSTING_READ(DC_STATE_DEBUG);
469 0 : }
470 0 : }
471 :
472 0 : static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
473 : {
474 0 : struct drm_device *dev = dev_priv->dev;
475 0 : bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
476 : SKL_DISP_PW_2);
477 :
478 0 : WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
479 : "Platform doesn't support DC5.\n");
480 0 : WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
481 0 : WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
482 :
483 0 : WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
484 : "DC5 already programmed to be enabled.\n");
485 0 : WARN_ONCE(dev_priv->pm.suspended,
486 : "DC5 cannot be enabled, if platform is runtime-suspended.\n");
487 :
488 0 : assert_csr_loaded(dev_priv);
489 0 : }
490 :
491 0 : static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
492 : {
493 0 : bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
494 : SKL_DISP_PW_2);
495 : /*
496 : * During initialization, the firmware may not be loaded yet.
497 : * We still want to make sure that the DC enabling flag is cleared.
498 : */
499 0 : if (dev_priv->power_domains.initializing)
500 0 : return;
501 :
502 0 : WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
503 0 : WARN_ONCE(dev_priv->pm.suspended,
504 : "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
505 0 : }
506 :
507 0 : static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
508 : {
509 : uint32_t val;
510 :
511 0 : assert_can_enable_dc5(dev_priv);
512 :
513 : DRM_DEBUG_KMS("Enabling DC5\n");
514 :
515 0 : gen9_set_dc_state_debugmask_memory_up(dev_priv);
516 :
517 0 : val = I915_READ(DC_STATE_EN);
518 0 : val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
519 0 : val |= DC_STATE_EN_UPTO_DC5;
520 0 : I915_WRITE(DC_STATE_EN, val);
521 0 : POSTING_READ(DC_STATE_EN);
522 0 : }
523 :
524 0 : static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
525 : {
526 : uint32_t val;
527 :
528 0 : assert_can_disable_dc5(dev_priv);
529 :
530 : DRM_DEBUG_KMS("Disabling DC5\n");
531 :
532 0 : val = I915_READ(DC_STATE_EN);
533 0 : val &= ~DC_STATE_EN_UPTO_DC5;
534 0 : I915_WRITE(DC_STATE_EN, val);
535 0 : POSTING_READ(DC_STATE_EN);
536 0 : }
537 :
538 0 : static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
539 : {
540 0 : struct drm_device *dev = dev_priv->dev;
541 :
542 0 : WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
543 : "Platform doesn't support DC6.\n");
544 0 : WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
545 0 : WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
546 : "Backlight is not disabled.\n");
547 0 : WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
548 : "DC6 already programmed to be enabled.\n");
549 :
550 0 : assert_csr_loaded(dev_priv);
551 0 : }
552 :
553 0 : static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
554 : {
555 : /*
556 : * During initialization, the firmware may not be loaded yet.
557 : * We still want to make sure that the DC enabling flag is cleared.
558 : */
559 0 : if (dev_priv->power_domains.initializing)
560 : return;
561 :
562 0 : assert_csr_loaded(dev_priv);
563 0 : WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
564 : "DC6 already programmed to be disabled.\n");
565 0 : }
566 :
567 0 : static void skl_enable_dc6(struct drm_i915_private *dev_priv)
568 : {
569 : uint32_t val;
570 :
571 0 : assert_can_enable_dc6(dev_priv);
572 :
573 : DRM_DEBUG_KMS("Enabling DC6\n");
574 :
575 0 : gen9_set_dc_state_debugmask_memory_up(dev_priv);
576 :
577 0 : val = I915_READ(DC_STATE_EN);
578 0 : val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
579 0 : val |= DC_STATE_EN_UPTO_DC6;
580 0 : I915_WRITE(DC_STATE_EN, val);
581 0 : POSTING_READ(DC_STATE_EN);
582 0 : }
583 :
584 0 : static void skl_disable_dc6(struct drm_i915_private *dev_priv)
585 : {
586 : uint32_t val;
587 :
588 0 : assert_can_disable_dc6(dev_priv);
589 :
590 : DRM_DEBUG_KMS("Disabling DC6\n");
591 :
592 0 : val = I915_READ(DC_STATE_EN);
593 0 : val &= ~DC_STATE_EN_UPTO_DC6;
594 0 : I915_WRITE(DC_STATE_EN, val);
595 0 : POSTING_READ(DC_STATE_EN);
596 0 : }
597 :
598 0 : static void skl_set_power_well(struct drm_i915_private *dev_priv,
599 : struct i915_power_well *power_well, bool enable)
600 : {
601 0 : struct drm_device *dev = dev_priv->dev;
602 : uint32_t tmp, fuse_status;
603 : uint32_t req_mask, state_mask;
604 : bool is_enabled, enable_requested, check_fuse_status = false;
605 :
606 0 : tmp = I915_READ(HSW_PWR_WELL_DRIVER);
607 0 : fuse_status = I915_READ(SKL_FUSE_STATUS);
608 :
609 0 : switch (power_well->data) {
610 : case SKL_DISP_PW_1:
611 0 : if (wait_for((I915_READ(SKL_FUSE_STATUS) &
612 : SKL_FUSE_PG0_DIST_STATUS), 1)) {
613 0 : DRM_ERROR("PG0 not enabled\n");
614 0 : return;
615 : }
616 : break;
617 : case SKL_DISP_PW_2:
618 0 : if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
619 0 : DRM_ERROR("PG1 in disabled state\n");
620 0 : return;
621 : }
622 : break;
623 : case SKL_DISP_PW_DDI_A_E:
624 : case SKL_DISP_PW_DDI_B:
625 : case SKL_DISP_PW_DDI_C:
626 : case SKL_DISP_PW_DDI_D:
627 : case SKL_DISP_PW_MISC_IO:
628 : break;
629 : default:
630 0 : WARN(1, "Unknown power well %lu\n", power_well->data);
631 0 : return;
632 : }
633 :
634 0 : req_mask = SKL_POWER_WELL_REQ(power_well->data);
635 0 : enable_requested = tmp & req_mask;
636 0 : state_mask = SKL_POWER_WELL_STATE(power_well->data);
637 0 : is_enabled = tmp & state_mask;
638 :
639 0 : if (enable) {
640 0 : if (!enable_requested) {
641 0 : WARN((tmp & state_mask) &&
642 : !I915_READ(HSW_PWR_WELL_BIOS),
643 : "Invalid for power well status to be enabled, unless done by the BIOS, \
644 : when request is to disable!\n");
645 0 : if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
646 0 : power_well->data == SKL_DISP_PW_2) {
647 0 : if (SKL_ENABLE_DC6(dev)) {
648 0 : skl_disable_dc6(dev_priv);
649 : /*
650 : * DDI buffer programming unnecessary during driver-load/resume
651 : * as it's already done during modeset initialization then.
652 : * It's also invalid here as encoder list is still uninitialized.
653 : */
654 0 : if (!dev_priv->power_domains.initializing)
655 0 : intel_prepare_ddi(dev);
656 : } else {
657 0 : gen9_disable_dc5(dev_priv);
658 : }
659 : }
660 0 : I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
661 0 : }
662 :
663 0 : if (!is_enabled) {
664 : DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
665 0 : if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
666 : state_mask), 1))
667 0 : DRM_ERROR("%s enable timeout\n",
668 : power_well->name);
669 : check_fuse_status = true;
670 0 : }
671 : } else {
672 0 : if (enable_requested) {
673 0 : if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
674 0 : (power_well->data == SKL_DISP_PW_1) &&
675 0 : (intel_csr_load_status_get(dev_priv) == FW_LOADED))
676 : DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
677 : else {
678 0 : I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
679 0 : POSTING_READ(HSW_PWR_WELL_DRIVER);
680 : DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
681 : }
682 :
683 0 : if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
684 0 : power_well->data == SKL_DISP_PW_2) {
685 : enum csr_state state;
686 : /* TODO: wait for a completion event or
687 : * similar here instead of busy
688 : * waiting using wait_for function.
689 : */
690 0 : wait_for((state = intel_csr_load_status_get(dev_priv)) !=
691 : FW_UNINITIALIZED, 1000);
692 0 : if (state != FW_LOADED)
693 : DRM_DEBUG("CSR firmware not ready (%d)\n",
694 : state);
695 : else
696 0 : if (SKL_ENABLE_DC6(dev))
697 0 : skl_enable_dc6(dev_priv);
698 : else
699 0 : gen9_enable_dc5(dev_priv);
700 0 : }
701 : }
702 : }
703 :
704 0 : if (check_fuse_status) {
705 0 : if (power_well->data == SKL_DISP_PW_1) {
706 0 : if (wait_for((I915_READ(SKL_FUSE_STATUS) &
707 : SKL_FUSE_PG1_DIST_STATUS), 1))
708 0 : DRM_ERROR("PG1 distributing status timeout\n");
709 0 : } else if (power_well->data == SKL_DISP_PW_2) {
710 0 : if (wait_for((I915_READ(SKL_FUSE_STATUS) &
711 : SKL_FUSE_PG2_DIST_STATUS), 1))
712 0 : DRM_ERROR("PG2 distributing status timeout\n");
713 : }
714 : }
715 :
716 0 : if (enable && !is_enabled)
717 0 : skl_power_well_post_enable(dev_priv, power_well);
718 0 : }
719 :
720 0 : static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
721 : struct i915_power_well *power_well)
722 : {
723 0 : hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
724 :
725 : /*
726 : * We're taking over the BIOS, so clear any requests made by it since
727 : * the driver is in charge now.
728 : */
729 0 : if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
730 0 : I915_WRITE(HSW_PWR_WELL_BIOS, 0);
731 0 : }
732 :
733 0 : static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
734 : struct i915_power_well *power_well)
735 : {
736 0 : hsw_set_power_well(dev_priv, power_well, true);
737 0 : }
738 :
739 0 : static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
740 : struct i915_power_well *power_well)
741 : {
742 0 : hsw_set_power_well(dev_priv, power_well, false);
743 0 : }
744 :
745 0 : static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
746 : struct i915_power_well *power_well)
747 : {
748 0 : uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
749 0 : SKL_POWER_WELL_STATE(power_well->data);
750 :
751 0 : return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
752 : }
753 :
754 0 : static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
755 : struct i915_power_well *power_well)
756 : {
757 0 : skl_set_power_well(dev_priv, power_well, power_well->count > 0);
758 :
759 : /* Clear any request made by BIOS as driver is taking over */
760 0 : I915_WRITE(HSW_PWR_WELL_BIOS, 0);
761 0 : }
762 :
763 0 : static void skl_power_well_enable(struct drm_i915_private *dev_priv,
764 : struct i915_power_well *power_well)
765 : {
766 0 : skl_set_power_well(dev_priv, power_well, true);
767 0 : }
768 :
769 0 : static void skl_power_well_disable(struct drm_i915_private *dev_priv,
770 : struct i915_power_well *power_well)
771 : {
772 0 : skl_set_power_well(dev_priv, power_well, false);
773 0 : }
774 :
775 0 : static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
776 : struct i915_power_well *power_well)
777 : {
778 0 : }
779 :
780 0 : static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
781 : struct i915_power_well *power_well)
782 : {
783 0 : return true;
784 : }
785 :
786 0 : static void vlv_set_power_well(struct drm_i915_private *dev_priv,
787 : struct i915_power_well *power_well, bool enable)
788 : {
789 0 : enum punit_power_well power_well_id = power_well->data;
790 : u32 mask;
791 : u32 state;
792 : u32 ctrl;
793 :
794 0 : mask = PUNIT_PWRGT_MASK(power_well_id);
795 0 : state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
796 : PUNIT_PWRGT_PWR_GATE(power_well_id);
797 :
798 0 : mutex_lock(&dev_priv->rps.hw_lock);
799 :
800 : #define COND \
801 : ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
802 :
803 0 : if (COND)
804 : goto out;
805 :
806 0 : ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
807 0 : ctrl &= ~mask;
808 0 : ctrl |= state;
809 0 : vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
810 :
811 0 : if (wait_for(COND, 100))
812 0 : DRM_ERROR("timeout setting power well state %08x (%08x)\n",
813 : state,
814 : vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
815 :
816 : #undef COND
817 :
818 : out:
819 0 : mutex_unlock(&dev_priv->rps.hw_lock);
820 0 : }
821 :
822 0 : static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
823 : struct i915_power_well *power_well)
824 : {
825 0 : vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
826 0 : }
827 :
828 0 : static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
829 : struct i915_power_well *power_well)
830 : {
831 0 : vlv_set_power_well(dev_priv, power_well, true);
832 0 : }
833 :
834 0 : static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
835 : struct i915_power_well *power_well)
836 : {
837 0 : vlv_set_power_well(dev_priv, power_well, false);
838 0 : }
839 :
840 0 : static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
841 : struct i915_power_well *power_well)
842 : {
843 0 : int power_well_id = power_well->data;
844 : bool enabled = false;
845 : u32 mask;
846 : u32 state;
847 : u32 ctrl;
848 :
849 0 : mask = PUNIT_PWRGT_MASK(power_well_id);
850 : ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
851 :
852 0 : mutex_lock(&dev_priv->rps.hw_lock);
853 :
854 0 : state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
855 : /*
856 : * We only ever set the power-on and power-gate states, anything
857 : * else is unexpected.
858 : */
859 0 : WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
860 : state != PUNIT_PWRGT_PWR_GATE(power_well_id));
861 0 : if (state == ctrl)
862 0 : enabled = true;
863 :
864 : /*
865 : * A transient state at this point would mean some unexpected party
866 : * is poking at the power controls too.
867 : */
868 0 : ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
869 0 : WARN_ON(ctrl != state);
870 :
871 0 : mutex_unlock(&dev_priv->rps.hw_lock);
872 :
873 0 : return enabled;
874 : }
875 :
876 0 : static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
877 : {
878 : enum pipe pipe;
879 :
880 : /*
881 : * Enable the CRI clock source so we can get at the
882 : * display and the reference clock for VGA
883 : * hotplug / manual detection. Supposedly DSI also
884 : * needs the ref clock up and running.
885 : *
886 : * CHV DPLL B/C have some issues if VGA mode is enabled.
887 : */
888 0 : for_each_pipe(dev_priv->dev, pipe) {
889 0 : u32 val = I915_READ(DPLL(pipe));
890 :
891 0 : val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
892 0 : if (pipe != PIPE_A)
893 0 : val |= DPLL_INTEGRATED_CRI_CLK_VLV;
894 :
895 0 : I915_WRITE(DPLL(pipe), val);
896 : }
897 :
898 0 : spin_lock_irq(&dev_priv->irq_lock);
899 0 : valleyview_enable_display_irqs(dev_priv);
900 0 : spin_unlock_irq(&dev_priv->irq_lock);
901 :
902 : /*
903 : * During driver initialization/resume we can avoid restoring the
904 : * part of the HW/SW state that will be inited anyway explicitly.
905 : */
906 0 : if (dev_priv->power_domains.initializing)
907 0 : return;
908 :
909 0 : intel_hpd_init(dev_priv);
910 :
911 0 : i915_redisable_vga_power_on(dev_priv->dev);
912 0 : }
913 :
914 0 : static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
915 : {
916 0 : spin_lock_irq(&dev_priv->irq_lock);
917 0 : valleyview_disable_display_irqs(dev_priv);
918 0 : spin_unlock_irq(&dev_priv->irq_lock);
919 :
920 0 : vlv_power_sequencer_reset(dev_priv);
921 0 : }
922 :
923 0 : static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
924 : struct i915_power_well *power_well)
925 : {
926 0 : WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
927 :
928 0 : vlv_set_power_well(dev_priv, power_well, true);
929 :
930 0 : vlv_display_power_well_init(dev_priv);
931 0 : }
932 :
933 0 : static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
934 : struct i915_power_well *power_well)
935 : {
936 0 : WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
937 :
938 0 : vlv_display_power_well_deinit(dev_priv);
939 :
940 0 : vlv_set_power_well(dev_priv, power_well, false);
941 0 : }
942 :
943 0 : static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
944 : struct i915_power_well *power_well)
945 : {
946 0 : WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
947 :
948 : /* since ref/cri clock was enabled */
949 0 : udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
950 :
951 0 : vlv_set_power_well(dev_priv, power_well, true);
952 :
953 : /*
954 : * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
955 : * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
956 : * a. GUnit 0x2110 bit[0] set to 1 (def 0)
957 : * b. The other bits such as sfr settings / modesel may all
958 : * be set to 0.
959 : *
960 : * This should only be done on init and resume from S3 with
961 : * both PLLs disabled, or we risk losing DPIO and PLL
962 : * synchronization.
963 : */
964 0 : I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
965 0 : }
966 :
967 0 : static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
968 : struct i915_power_well *power_well)
969 : {
970 : enum pipe pipe;
971 :
972 0 : WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
973 :
974 0 : for_each_pipe(dev_priv, pipe)
975 0 : assert_pll_disabled(dev_priv, pipe);
976 :
977 : /* Assert common reset */
978 0 : I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
979 :
980 0 : vlv_set_power_well(dev_priv, power_well, false);
981 0 : }
982 :
983 : #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
984 :
985 0 : static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
986 : int power_well_id)
987 : {
988 0 : struct i915_power_domains *power_domains = &dev_priv->power_domains;
989 : struct i915_power_well *power_well;
990 : int i;
991 :
992 0 : for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
993 0 : if (power_well->data == power_well_id)
994 0 : return power_well;
995 : }
996 :
997 0 : return NULL;
998 0 : }
999 :
1000 : #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1001 :
1002 0 : static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1003 : {
1004 : struct i915_power_well *cmn_bc =
1005 0 : lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1006 : struct i915_power_well *cmn_d =
1007 0 : lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1008 0 : u32 phy_control = dev_priv->chv_phy_control;
1009 : u32 phy_status = 0;
1010 : u32 phy_status_mask = 0xffffffff;
1011 : u32 tmp;
1012 :
1013 : /*
1014 : * The BIOS can leave the PHY is some weird state
1015 : * where it doesn't fully power down some parts.
1016 : * Disable the asserts until the PHY has been fully
1017 : * reset (ie. the power well has been disabled at
1018 : * least once).
1019 : */
1020 0 : if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1021 0 : phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1022 : PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1023 : PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1024 : PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1025 : PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1026 : PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1027 :
1028 0 : if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1029 0 : phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1030 : PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1031 : PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1032 :
1033 0 : if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1034 : phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1035 :
1036 : /* this assumes override is only used to enable lanes */
1037 0 : if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1038 0 : phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1039 :
1040 0 : if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1041 0 : phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1042 :
1043 : /* CL1 is on whenever anything is on in either channel */
1044 0 : if (BITS_SET(phy_control,
1045 : PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1046 : PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1047 0 : phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1048 :
1049 : /*
1050 : * The DPLLB check accounts for the pipe B + port A usage
1051 : * with CL2 powered up but all the lanes in the second channel
1052 : * powered down.
1053 : */
1054 0 : if (BITS_SET(phy_control,
1055 0 : PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1056 0 : (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1057 0 : phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1058 :
1059 0 : if (BITS_SET(phy_control,
1060 : PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1061 0 : phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1062 0 : if (BITS_SET(phy_control,
1063 : PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1064 0 : phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1065 :
1066 0 : if (BITS_SET(phy_control,
1067 : PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1068 0 : phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1069 0 : if (BITS_SET(phy_control,
1070 : PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1071 0 : phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1072 : }
1073 :
1074 0 : if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1075 0 : phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1076 :
1077 : /* this assumes override is only used to enable lanes */
1078 0 : if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1079 0 : phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1080 :
1081 0 : if (BITS_SET(phy_control,
1082 : PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1083 0 : phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1084 :
1085 0 : if (BITS_SET(phy_control,
1086 : PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1087 0 : phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1088 0 : if (BITS_SET(phy_control,
1089 : PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1090 0 : phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1091 : }
1092 :
1093 0 : phy_status &= phy_status_mask;
1094 :
1095 : /*
1096 : * The PHY may be busy with some initial calibration and whatnot,
1097 : * so the power state can take a while to actually change.
1098 : */
1099 0 : if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1100 0 : WARN(phy_status != tmp,
1101 : "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1102 : tmp, phy_status, dev_priv->chv_phy_control);
1103 0 : }
1104 :
1105 : #undef BITS_SET
1106 :
1107 0 : static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1108 : struct i915_power_well *power_well)
1109 : {
1110 : enum dpio_phy phy;
1111 : enum pipe pipe;
1112 : uint32_t tmp;
1113 :
1114 0 : WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1115 : power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1116 :
1117 0 : if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1118 : pipe = PIPE_A;
1119 : phy = DPIO_PHY0;
1120 0 : } else {
1121 : pipe = PIPE_C;
1122 : phy = DPIO_PHY1;
1123 : }
1124 :
1125 : /* since ref/cri clock was enabled */
1126 0 : udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1127 0 : vlv_set_power_well(dev_priv, power_well, true);
1128 :
1129 : /* Poll for phypwrgood signal */
1130 0 : if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1131 0 : DRM_ERROR("Display PHY %d is not power up\n", phy);
1132 :
1133 0 : mutex_lock(&dev_priv->sb_lock);
1134 :
1135 : /* Enable dynamic power down */
1136 0 : tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1137 0 : tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1138 : DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1139 0 : vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1140 :
1141 0 : if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1142 0 : tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1143 0 : tmp |= DPIO_DYNPWRDOWNEN_CH1;
1144 0 : vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1145 0 : } else {
1146 : /*
1147 : * Force the non-existing CL2 off. BXT does this
1148 : * too, so maybe it saves some power even though
1149 : * CL2 doesn't exist?
1150 : */
1151 0 : tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1152 0 : tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1153 0 : vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1154 : }
1155 :
1156 0 : mutex_unlock(&dev_priv->sb_lock);
1157 :
1158 0 : dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1159 0 : I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1160 :
1161 : DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1162 : phy, dev_priv->chv_phy_control);
1163 :
1164 0 : assert_chv_phy_status(dev_priv);
1165 0 : }
1166 :
1167 0 : static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1168 : struct i915_power_well *power_well)
1169 : {
1170 : enum dpio_phy phy;
1171 :
1172 0 : WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1173 : power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1174 :
1175 0 : if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1176 : phy = DPIO_PHY0;
1177 0 : assert_pll_disabled(dev_priv, PIPE_A);
1178 0 : assert_pll_disabled(dev_priv, PIPE_B);
1179 0 : } else {
1180 : phy = DPIO_PHY1;
1181 0 : assert_pll_disabled(dev_priv, PIPE_C);
1182 : }
1183 :
1184 0 : dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1185 0 : I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1186 :
1187 0 : vlv_set_power_well(dev_priv, power_well, false);
1188 :
1189 : DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1190 : phy, dev_priv->chv_phy_control);
1191 :
1192 : /* PHY is fully reset now, so we can enable the PHY state asserts */
1193 0 : dev_priv->chv_phy_assert[phy] = true;
1194 :
1195 0 : assert_chv_phy_status(dev_priv);
1196 0 : }
1197 :
1198 0 : static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1199 : enum dpio_channel ch, bool override, unsigned int mask)
1200 : {
1201 0 : enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1202 : u32 reg, val, expected, actual;
1203 :
1204 : /*
1205 : * The BIOS can leave the PHY is some weird state
1206 : * where it doesn't fully power down some parts.
1207 : * Disable the asserts until the PHY has been fully
1208 : * reset (ie. the power well has been disabled at
1209 : * least once).
1210 : */
1211 0 : if (!dev_priv->chv_phy_assert[phy])
1212 0 : return;
1213 :
1214 0 : if (ch == DPIO_CH0)
1215 0 : reg = _CHV_CMN_DW0_CH0;
1216 : else
1217 : reg = _CHV_CMN_DW6_CH1;
1218 :
1219 0 : mutex_lock(&dev_priv->sb_lock);
1220 0 : val = vlv_dpio_read(dev_priv, pipe, reg);
1221 0 : mutex_unlock(&dev_priv->sb_lock);
1222 :
1223 : /*
1224 : * This assumes !override is only used when the port is disabled.
1225 : * All lanes should power down even without the override when
1226 : * the port is disabled.
1227 : */
1228 0 : if (!override || mask == 0xf) {
1229 : expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1230 : /*
1231 : * If CH1 common lane is not active anymore
1232 : * (eg. for pipe B DPLL) the entire channel will
1233 : * shut down, which causes the common lane registers
1234 : * to read as 0. That means we can't actually check
1235 : * the lane power down status bits, but as the entire
1236 : * register reads as 0 it's a good indication that the
1237 : * channel is indeed entirely powered down.
1238 : */
1239 0 : if (ch == DPIO_CH1 && val == 0)
1240 : expected = 0;
1241 0 : } else if (mask != 0x0) {
1242 : expected = DPIO_ANYDL_POWERDOWN;
1243 0 : } else {
1244 : expected = 0;
1245 : }
1246 :
1247 0 : if (ch == DPIO_CH0)
1248 0 : actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1249 : else
1250 0 : actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1251 0 : actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1252 :
1253 0 : WARN(actual != expected,
1254 : "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1255 : !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1256 : !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1257 : reg, val);
1258 0 : }
1259 :
1260 0 : bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1261 : enum dpio_channel ch, bool override)
1262 : {
1263 0 : struct i915_power_domains *power_domains = &dev_priv->power_domains;
1264 : bool was_override;
1265 :
1266 0 : mutex_lock(&power_domains->lock);
1267 :
1268 0 : was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1269 :
1270 0 : if (override == was_override)
1271 : goto out;
1272 :
1273 0 : if (override)
1274 0 : dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1275 : else
1276 0 : dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1277 :
1278 0 : I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1279 :
1280 : DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1281 : phy, ch, dev_priv->chv_phy_control);
1282 :
1283 0 : assert_chv_phy_status(dev_priv);
1284 :
1285 : out:
1286 0 : mutex_unlock(&power_domains->lock);
1287 :
1288 0 : return was_override;
1289 : }
1290 :
1291 0 : void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1292 : bool override, unsigned int mask)
1293 : {
1294 0 : struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1295 0 : struct i915_power_domains *power_domains = &dev_priv->power_domains;
1296 0 : enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1297 0 : enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1298 :
1299 0 : mutex_lock(&power_domains->lock);
1300 :
1301 0 : dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1302 0 : dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1303 :
1304 0 : if (override)
1305 0 : dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1306 : else
1307 0 : dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1308 :
1309 0 : I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1310 :
1311 : DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1312 : phy, ch, mask, dev_priv->chv_phy_control);
1313 :
1314 0 : assert_chv_phy_status(dev_priv);
1315 :
1316 0 : assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1317 :
1318 0 : mutex_unlock(&power_domains->lock);
1319 0 : }
1320 :
1321 0 : static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1322 : struct i915_power_well *power_well)
1323 : {
1324 0 : enum pipe pipe = power_well->data;
1325 : bool enabled;
1326 : u32 state, ctrl;
1327 :
1328 0 : mutex_lock(&dev_priv->rps.hw_lock);
1329 :
1330 0 : state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1331 : /*
1332 : * We only ever set the power-on and power-gate states, anything
1333 : * else is unexpected.
1334 : */
1335 0 : WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1336 0 : enabled = state == DP_SSS_PWR_ON(pipe);
1337 :
1338 : /*
1339 : * A transient state at this point would mean some unexpected party
1340 : * is poking at the power controls too.
1341 : */
1342 0 : ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1343 0 : WARN_ON(ctrl << 16 != state);
1344 :
1345 0 : mutex_unlock(&dev_priv->rps.hw_lock);
1346 :
1347 0 : return enabled;
1348 : }
1349 :
1350 0 : static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1351 : struct i915_power_well *power_well,
1352 : bool enable)
1353 : {
1354 0 : enum pipe pipe = power_well->data;
1355 : u32 state;
1356 : u32 ctrl;
1357 :
1358 0 : state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1359 :
1360 0 : mutex_lock(&dev_priv->rps.hw_lock);
1361 :
1362 : #define COND \
1363 : ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1364 :
1365 0 : if (COND)
1366 : goto out;
1367 :
1368 0 : ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1369 0 : ctrl &= ~DP_SSC_MASK(pipe);
1370 0 : ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1371 0 : vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1372 :
1373 0 : if (wait_for(COND, 100))
1374 0 : DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1375 : state,
1376 : vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1377 :
1378 : #undef COND
1379 :
1380 : out:
1381 0 : mutex_unlock(&dev_priv->rps.hw_lock);
1382 0 : }
1383 :
1384 0 : static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1385 : struct i915_power_well *power_well)
1386 : {
1387 0 : WARN_ON_ONCE(power_well->data != PIPE_A);
1388 :
1389 0 : chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1390 0 : }
1391 :
1392 0 : static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1393 : struct i915_power_well *power_well)
1394 : {
1395 0 : WARN_ON_ONCE(power_well->data != PIPE_A);
1396 :
1397 0 : chv_set_pipe_power_well(dev_priv, power_well, true);
1398 :
1399 0 : vlv_display_power_well_init(dev_priv);
1400 0 : }
1401 :
1402 0 : static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1403 : struct i915_power_well *power_well)
1404 : {
1405 0 : WARN_ON_ONCE(power_well->data != PIPE_A);
1406 :
1407 0 : vlv_display_power_well_deinit(dev_priv);
1408 :
1409 0 : chv_set_pipe_power_well(dev_priv, power_well, false);
1410 0 : }
1411 :
1412 : /**
1413 : * intel_display_power_get - grab a power domain reference
1414 : * @dev_priv: i915 device instance
1415 : * @domain: power domain to reference
1416 : *
1417 : * This function grabs a power domain reference for @domain and ensures that the
1418 : * power domain and all its parents are powered up. Therefore users should only
1419 : * grab a reference to the innermost power domain they need.
1420 : *
1421 : * Any power domain reference obtained by this function must have a symmetric
1422 : * call to intel_display_power_put() to release the reference again.
1423 : */
1424 0 : void intel_display_power_get(struct drm_i915_private *dev_priv,
1425 : enum intel_display_power_domain domain)
1426 : {
1427 : struct i915_power_domains *power_domains;
1428 : struct i915_power_well *power_well;
1429 : int i;
1430 :
1431 0 : intel_runtime_pm_get(dev_priv);
1432 :
1433 0 : power_domains = &dev_priv->power_domains;
1434 :
1435 0 : mutex_lock(&power_domains->lock);
1436 :
1437 0 : for_each_power_well(i, power_well, BIT(domain), power_domains) {
1438 0 : if (!power_well->count++)
1439 0 : intel_power_well_enable(dev_priv, power_well);
1440 : }
1441 :
1442 0 : power_domains->domain_use_count[domain]++;
1443 :
1444 0 : mutex_unlock(&power_domains->lock);
1445 0 : }
1446 :
1447 : /**
1448 : * intel_display_power_put - release a power domain reference
1449 : * @dev_priv: i915 device instance
1450 : * @domain: power domain to reference
1451 : *
1452 : * This function drops the power domain reference obtained by
1453 : * intel_display_power_get() and might power down the corresponding hardware
1454 : * block right away if this is the last reference.
1455 : */
1456 0 : void intel_display_power_put(struct drm_i915_private *dev_priv,
1457 : enum intel_display_power_domain domain)
1458 : {
1459 : struct i915_power_domains *power_domains;
1460 : struct i915_power_well *power_well;
1461 : int i;
1462 :
1463 0 : power_domains = &dev_priv->power_domains;
1464 :
1465 0 : mutex_lock(&power_domains->lock);
1466 :
1467 0 : WARN_ON(!power_domains->domain_use_count[domain]);
1468 0 : power_domains->domain_use_count[domain]--;
1469 :
1470 0 : for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1471 0 : WARN_ON(!power_well->count);
1472 :
1473 0 : if (!--power_well->count && i915.disable_power_well)
1474 0 : intel_power_well_disable(dev_priv, power_well);
1475 : }
1476 :
1477 0 : mutex_unlock(&power_domains->lock);
1478 :
1479 0 : intel_runtime_pm_put(dev_priv);
1480 0 : }
1481 :
1482 : #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1483 : BIT(POWER_DOMAIN_PIPE_A) | \
1484 : BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1485 : BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
1486 : BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
1487 : BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1488 : BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1489 : BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1490 : BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1491 : BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1492 : BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1493 : BIT(POWER_DOMAIN_PORT_CRT) | \
1494 : BIT(POWER_DOMAIN_PLLS) | \
1495 : BIT(POWER_DOMAIN_AUX_A) | \
1496 : BIT(POWER_DOMAIN_AUX_B) | \
1497 : BIT(POWER_DOMAIN_AUX_C) | \
1498 : BIT(POWER_DOMAIN_AUX_D) | \
1499 : BIT(POWER_DOMAIN_GMBUS) | \
1500 : BIT(POWER_DOMAIN_INIT))
1501 : #define HSW_DISPLAY_POWER_DOMAINS ( \
1502 : (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1503 : BIT(POWER_DOMAIN_INIT))
1504 :
1505 : #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1506 : HSW_ALWAYS_ON_POWER_DOMAINS | \
1507 : BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1508 : #define BDW_DISPLAY_POWER_DOMAINS ( \
1509 : (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1510 : BIT(POWER_DOMAIN_INIT))
1511 :
1512 : #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1513 : #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1514 :
1515 : #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1516 : BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1517 : BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1518 : BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1519 : BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1520 : BIT(POWER_DOMAIN_PORT_CRT) | \
1521 : BIT(POWER_DOMAIN_AUX_B) | \
1522 : BIT(POWER_DOMAIN_AUX_C) | \
1523 : BIT(POWER_DOMAIN_INIT))
1524 :
1525 : #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1526 : BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1527 : BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1528 : BIT(POWER_DOMAIN_AUX_B) | \
1529 : BIT(POWER_DOMAIN_INIT))
1530 :
1531 : #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1532 : BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1533 : BIT(POWER_DOMAIN_AUX_B) | \
1534 : BIT(POWER_DOMAIN_INIT))
1535 :
1536 : #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1537 : BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1538 : BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1539 : BIT(POWER_DOMAIN_AUX_C) | \
1540 : BIT(POWER_DOMAIN_INIT))
1541 :
1542 : #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1543 : BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1544 : BIT(POWER_DOMAIN_AUX_C) | \
1545 : BIT(POWER_DOMAIN_INIT))
1546 :
1547 : #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1548 : BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
1549 : BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
1550 : BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
1551 : BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
1552 : BIT(POWER_DOMAIN_AUX_B) | \
1553 : BIT(POWER_DOMAIN_AUX_C) | \
1554 : BIT(POWER_DOMAIN_INIT))
1555 :
1556 : #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1557 : BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
1558 : BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
1559 : BIT(POWER_DOMAIN_AUX_D) | \
1560 : BIT(POWER_DOMAIN_INIT))
1561 :
1562 : static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1563 : .sync_hw = i9xx_always_on_power_well_noop,
1564 : .enable = i9xx_always_on_power_well_noop,
1565 : .disable = i9xx_always_on_power_well_noop,
1566 : .is_enabled = i9xx_always_on_power_well_enabled,
1567 : };
1568 :
1569 : static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1570 : .sync_hw = chv_pipe_power_well_sync_hw,
1571 : .enable = chv_pipe_power_well_enable,
1572 : .disable = chv_pipe_power_well_disable,
1573 : .is_enabled = chv_pipe_power_well_enabled,
1574 : };
1575 :
1576 : static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1577 : .sync_hw = vlv_power_well_sync_hw,
1578 : .enable = chv_dpio_cmn_power_well_enable,
1579 : .disable = chv_dpio_cmn_power_well_disable,
1580 : .is_enabled = vlv_power_well_enabled,
1581 : };
1582 :
1583 : static struct i915_power_well i9xx_always_on_power_well[] = {
1584 : {
1585 : .name = "always-on",
1586 : .always_on = 1,
1587 : .domains = POWER_DOMAIN_MASK,
1588 : .ops = &i9xx_always_on_power_well_ops,
1589 : },
1590 : };
1591 :
1592 : static const struct i915_power_well_ops hsw_power_well_ops = {
1593 : .sync_hw = hsw_power_well_sync_hw,
1594 : .enable = hsw_power_well_enable,
1595 : .disable = hsw_power_well_disable,
1596 : .is_enabled = hsw_power_well_enabled,
1597 : };
1598 :
1599 : static const struct i915_power_well_ops skl_power_well_ops = {
1600 : .sync_hw = skl_power_well_sync_hw,
1601 : .enable = skl_power_well_enable,
1602 : .disable = skl_power_well_disable,
1603 : .is_enabled = skl_power_well_enabled,
1604 : };
1605 :
1606 : static struct i915_power_well hsw_power_wells[] = {
1607 : {
1608 : .name = "always-on",
1609 : .always_on = 1,
1610 : .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1611 : .ops = &i9xx_always_on_power_well_ops,
1612 : },
1613 : {
1614 : .name = "display",
1615 : .domains = HSW_DISPLAY_POWER_DOMAINS,
1616 : .ops = &hsw_power_well_ops,
1617 : },
1618 : };
1619 :
1620 : static struct i915_power_well bdw_power_wells[] = {
1621 : {
1622 : .name = "always-on",
1623 : .always_on = 1,
1624 : .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1625 : .ops = &i9xx_always_on_power_well_ops,
1626 : },
1627 : {
1628 : .name = "display",
1629 : .domains = BDW_DISPLAY_POWER_DOMAINS,
1630 : .ops = &hsw_power_well_ops,
1631 : },
1632 : };
1633 :
1634 : static const struct i915_power_well_ops vlv_display_power_well_ops = {
1635 : .sync_hw = vlv_power_well_sync_hw,
1636 : .enable = vlv_display_power_well_enable,
1637 : .disable = vlv_display_power_well_disable,
1638 : .is_enabled = vlv_power_well_enabled,
1639 : };
1640 :
1641 : static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1642 : .sync_hw = vlv_power_well_sync_hw,
1643 : .enable = vlv_dpio_cmn_power_well_enable,
1644 : .disable = vlv_dpio_cmn_power_well_disable,
1645 : .is_enabled = vlv_power_well_enabled,
1646 : };
1647 :
1648 : static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1649 : .sync_hw = vlv_power_well_sync_hw,
1650 : .enable = vlv_power_well_enable,
1651 : .disable = vlv_power_well_disable,
1652 : .is_enabled = vlv_power_well_enabled,
1653 : };
1654 :
1655 : static struct i915_power_well vlv_power_wells[] = {
1656 : {
1657 : .name = "always-on",
1658 : .always_on = 1,
1659 : .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1660 : .ops = &i9xx_always_on_power_well_ops,
1661 : },
1662 : {
1663 : .name = "display",
1664 : .domains = VLV_DISPLAY_POWER_DOMAINS,
1665 : .data = PUNIT_POWER_WELL_DISP2D,
1666 : .ops = &vlv_display_power_well_ops,
1667 : },
1668 : {
1669 : .name = "dpio-tx-b-01",
1670 : .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1671 : VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1672 : VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1673 : VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1674 : .ops = &vlv_dpio_power_well_ops,
1675 : .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1676 : },
1677 : {
1678 : .name = "dpio-tx-b-23",
1679 : .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1680 : VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1681 : VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1682 : VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1683 : .ops = &vlv_dpio_power_well_ops,
1684 : .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1685 : },
1686 : {
1687 : .name = "dpio-tx-c-01",
1688 : .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1689 : VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1690 : VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1691 : VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1692 : .ops = &vlv_dpio_power_well_ops,
1693 : .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1694 : },
1695 : {
1696 : .name = "dpio-tx-c-23",
1697 : .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1698 : VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1699 : VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1700 : VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1701 : .ops = &vlv_dpio_power_well_ops,
1702 : .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1703 : },
1704 : {
1705 : .name = "dpio-common",
1706 : .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1707 : .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1708 : .ops = &vlv_dpio_cmn_power_well_ops,
1709 : },
1710 : };
1711 :
1712 : static struct i915_power_well chv_power_wells[] = {
1713 : {
1714 : .name = "always-on",
1715 : .always_on = 1,
1716 : .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1717 : .ops = &i9xx_always_on_power_well_ops,
1718 : },
1719 : {
1720 : .name = "display",
1721 : /*
1722 : * Pipe A power well is the new disp2d well. Pipe B and C
1723 : * power wells don't actually exist. Pipe A power well is
1724 : * required for any pipe to work.
1725 : */
1726 : .domains = VLV_DISPLAY_POWER_DOMAINS,
1727 : .data = PIPE_A,
1728 : .ops = &chv_pipe_power_well_ops,
1729 : },
1730 : {
1731 : .name = "dpio-common-bc",
1732 : .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1733 : .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1734 : .ops = &chv_dpio_cmn_power_well_ops,
1735 : },
1736 : {
1737 : .name = "dpio-common-d",
1738 : .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1739 : .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1740 : .ops = &chv_dpio_cmn_power_well_ops,
1741 : },
1742 : };
1743 :
1744 0 : bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1745 : int power_well_id)
1746 : {
1747 : struct i915_power_well *power_well;
1748 : bool ret;
1749 :
1750 0 : power_well = lookup_power_well(dev_priv, power_well_id);
1751 0 : ret = power_well->ops->is_enabled(dev_priv, power_well);
1752 :
1753 0 : return ret;
1754 : }
1755 :
1756 : static struct i915_power_well skl_power_wells[] = {
1757 : {
1758 : .name = "always-on",
1759 : .always_on = 1,
1760 : .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1761 : .ops = &i9xx_always_on_power_well_ops,
1762 : },
1763 : {
1764 : .name = "power well 1",
1765 : .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1766 : .ops = &skl_power_well_ops,
1767 : .data = SKL_DISP_PW_1,
1768 : },
1769 : {
1770 : .name = "MISC IO power well",
1771 : .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1772 : .ops = &skl_power_well_ops,
1773 : .data = SKL_DISP_PW_MISC_IO,
1774 : },
1775 : {
1776 : .name = "power well 2",
1777 : .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1778 : .ops = &skl_power_well_ops,
1779 : .data = SKL_DISP_PW_2,
1780 : },
1781 : {
1782 : .name = "DDI A/E power well",
1783 : .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1784 : .ops = &skl_power_well_ops,
1785 : .data = SKL_DISP_PW_DDI_A_E,
1786 : },
1787 : {
1788 : .name = "DDI B power well",
1789 : .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1790 : .ops = &skl_power_well_ops,
1791 : .data = SKL_DISP_PW_DDI_B,
1792 : },
1793 : {
1794 : .name = "DDI C power well",
1795 : .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1796 : .ops = &skl_power_well_ops,
1797 : .data = SKL_DISP_PW_DDI_C,
1798 : },
1799 : {
1800 : .name = "DDI D power well",
1801 : .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1802 : .ops = &skl_power_well_ops,
1803 : .data = SKL_DISP_PW_DDI_D,
1804 : },
1805 : };
1806 :
1807 : static struct i915_power_well bxt_power_wells[] = {
1808 : {
1809 : .name = "always-on",
1810 : .always_on = 1,
1811 : .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1812 : .ops = &i9xx_always_on_power_well_ops,
1813 : },
1814 : {
1815 : .name = "power well 1",
1816 : .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1817 : .ops = &skl_power_well_ops,
1818 : .data = SKL_DISP_PW_1,
1819 : },
1820 : {
1821 : .name = "power well 2",
1822 : .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1823 : .ops = &skl_power_well_ops,
1824 : .data = SKL_DISP_PW_2,
1825 : }
1826 : };
1827 :
1828 : static int
1829 0 : sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1830 : int disable_power_well)
1831 : {
1832 0 : if (disable_power_well >= 0)
1833 0 : return !!disable_power_well;
1834 :
1835 0 : if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1836 : DRM_DEBUG_KMS("Disabling display power well support\n");
1837 0 : return 0;
1838 : }
1839 :
1840 0 : return 1;
1841 0 : }
1842 :
1843 : #define set_power_wells(power_domains, __power_wells) ({ \
1844 : (power_domains)->power_wells = (__power_wells); \
1845 : (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1846 : })
1847 :
1848 : /**
1849 : * intel_power_domains_init - initializes the power domain structures
1850 : * @dev_priv: i915 device instance
1851 : *
1852 : * Initializes the power domain structures for @dev_priv depending upon the
1853 : * supported platform.
1854 : */
1855 0 : int intel_power_domains_init(struct drm_i915_private *dev_priv)
1856 : {
1857 0 : struct i915_power_domains *power_domains = &dev_priv->power_domains;
1858 :
1859 0 : i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
1860 0 : i915.disable_power_well);
1861 :
1862 : BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
1863 :
1864 0 : rw_init(&power_domains->lock, "pdl");
1865 :
1866 : /*
1867 : * The enabling order will be from lower to higher indexed wells,
1868 : * the disabling order is reversed.
1869 : */
1870 0 : if (IS_HASWELL(dev_priv->dev)) {
1871 0 : set_power_wells(power_domains, hsw_power_wells);
1872 0 : } else if (IS_BROADWELL(dev_priv->dev)) {
1873 0 : set_power_wells(power_domains, bdw_power_wells);
1874 0 : } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
1875 0 : set_power_wells(power_domains, skl_power_wells);
1876 0 : } else if (IS_BROXTON(dev_priv->dev)) {
1877 0 : set_power_wells(power_domains, bxt_power_wells);
1878 0 : } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1879 0 : set_power_wells(power_domains, chv_power_wells);
1880 0 : } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1881 0 : set_power_wells(power_domains, vlv_power_wells);
1882 0 : } else {
1883 0 : set_power_wells(power_domains, i9xx_always_on_power_well);
1884 : }
1885 :
1886 0 : return 0;
1887 : }
1888 :
1889 0 : static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1890 : {
1891 : #ifdef __linux__
1892 : struct drm_device *dev = dev_priv->dev;
1893 : struct device *device = &dev->pdev->dev;
1894 :
1895 : if (!HAS_RUNTIME_PM(dev))
1896 : return;
1897 :
1898 : if (!intel_enable_rc6(dev))
1899 : return;
1900 :
1901 : /* Make sure we're not suspended first. */
1902 : pm_runtime_get_sync(device);
1903 : #endif
1904 0 : }
1905 :
1906 : /**
1907 : * intel_power_domains_fini - finalizes the power domain structures
1908 : * @dev_priv: i915 device instance
1909 : *
1910 : * Finalizes the power domain structures for @dev_priv depending upon the
1911 : * supported platform. This function also disables runtime pm and ensures that
1912 : * the device stays powered up so that the driver can be reloaded.
1913 : */
1914 0 : void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1915 : {
1916 0 : intel_runtime_pm_disable(dev_priv);
1917 :
1918 : /* The i915.ko module is still not prepared to be loaded when
1919 : * the power well is not enabled, so just enable it in case
1920 : * we're going to unload/reload. */
1921 0 : intel_display_set_init_power(dev_priv, true);
1922 0 : }
1923 :
1924 0 : static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1925 : {
1926 0 : struct i915_power_domains *power_domains = &dev_priv->power_domains;
1927 : struct i915_power_well *power_well;
1928 : int i;
1929 :
1930 0 : mutex_lock(&power_domains->lock);
1931 0 : for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1932 0 : power_well->ops->sync_hw(dev_priv, power_well);
1933 0 : power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1934 : power_well);
1935 0 : }
1936 0 : mutex_unlock(&power_domains->lock);
1937 0 : }
1938 :
1939 0 : static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1940 : {
1941 : struct i915_power_well *cmn_bc =
1942 0 : lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1943 : struct i915_power_well *cmn_d =
1944 0 : lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1945 :
1946 : /*
1947 : * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1948 : * workaround never ever read DISPLAY_PHY_CONTROL, and
1949 : * instead maintain a shadow copy ourselves. Use the actual
1950 : * power well state and lane status to reconstruct the
1951 : * expected initial value.
1952 : */
1953 0 : dev_priv->chv_phy_control =
1954 : PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1955 : PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1956 : PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1957 : PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1958 : PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1959 :
1960 : /*
1961 : * If all lanes are disabled we leave the override disabled
1962 : * with all power down bits cleared to match the state we
1963 : * would use after disabling the port. Otherwise enable the
1964 : * override and set the lane powerdown bits accding to the
1965 : * current lane status.
1966 : */
1967 0 : if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1968 0 : uint32_t status = I915_READ(DPLL(PIPE_A));
1969 : unsigned int mask;
1970 :
1971 0 : mask = status & DPLL_PORTB_READY_MASK;
1972 0 : if (mask == 0xf)
1973 0 : mask = 0x0;
1974 : else
1975 0 : dev_priv->chv_phy_control |=
1976 : PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1977 :
1978 0 : dev_priv->chv_phy_control |=
1979 0 : PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1980 :
1981 0 : mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1982 0 : if (mask == 0xf)
1983 0 : mask = 0x0;
1984 : else
1985 0 : dev_priv->chv_phy_control |=
1986 : PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1987 :
1988 0 : dev_priv->chv_phy_control |=
1989 0 : PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1990 :
1991 0 : dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1992 :
1993 0 : dev_priv->chv_phy_assert[DPIO_PHY0] = false;
1994 0 : } else {
1995 0 : dev_priv->chv_phy_assert[DPIO_PHY0] = true;
1996 : }
1997 :
1998 0 : if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1999 0 : uint32_t status = I915_READ(DPIO_PHY_STATUS);
2000 : unsigned int mask;
2001 :
2002 0 : mask = status & DPLL_PORTD_READY_MASK;
2003 :
2004 0 : if (mask == 0xf)
2005 0 : mask = 0x0;
2006 : else
2007 0 : dev_priv->chv_phy_control |=
2008 : PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2009 :
2010 0 : dev_priv->chv_phy_control |=
2011 0 : PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2012 :
2013 0 : dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2014 :
2015 0 : dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2016 0 : } else {
2017 0 : dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2018 : }
2019 :
2020 0 : I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2021 :
2022 : DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2023 : dev_priv->chv_phy_control);
2024 0 : }
2025 :
2026 0 : static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2027 : {
2028 : struct i915_power_well *cmn =
2029 0 : lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2030 : struct i915_power_well *disp2d =
2031 0 : lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2032 :
2033 : /* If the display might be already active skip this */
2034 0 : if (cmn->ops->is_enabled(dev_priv, cmn) &&
2035 0 : disp2d->ops->is_enabled(dev_priv, disp2d) &&
2036 0 : I915_READ(DPIO_CTL) & DPIO_CMNRST)
2037 0 : return;
2038 :
2039 : DRM_DEBUG_KMS("toggling display PHY side reset\n");
2040 :
2041 : /* cmnlane needs DPLL registers */
2042 0 : disp2d->ops->enable(dev_priv, disp2d);
2043 :
2044 : /*
2045 : * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2046 : * Need to assert and de-assert PHY SB reset by gating the
2047 : * common lane power, then un-gating it.
2048 : * Simply ungating isn't enough to reset the PHY enough to get
2049 : * ports and lanes running.
2050 : */
2051 0 : cmn->ops->disable(dev_priv, cmn);
2052 0 : }
2053 :
2054 : /**
2055 : * intel_power_domains_init_hw - initialize hardware power domain state
2056 : * @dev_priv: i915 device instance
2057 : *
2058 : * This function initializes the hardware power domain state and enables all
2059 : * power domains using intel_display_set_init_power().
2060 : */
2061 0 : void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
2062 : {
2063 0 : struct drm_device *dev = dev_priv->dev;
2064 0 : struct i915_power_domains *power_domains = &dev_priv->power_domains;
2065 :
2066 0 : power_domains->initializing = true;
2067 :
2068 0 : if (IS_CHERRYVIEW(dev)) {
2069 0 : mutex_lock(&power_domains->lock);
2070 0 : chv_phy_control_init(dev_priv);
2071 0 : mutex_unlock(&power_domains->lock);
2072 0 : } else if (IS_VALLEYVIEW(dev)) {
2073 0 : mutex_lock(&power_domains->lock);
2074 0 : vlv_cmnlane_wa(dev_priv);
2075 0 : mutex_unlock(&power_domains->lock);
2076 0 : }
2077 :
2078 : /* For now, we need the power well to be always enabled. */
2079 0 : intel_display_set_init_power(dev_priv, true);
2080 0 : intel_power_domains_resume(dev_priv);
2081 0 : power_domains->initializing = false;
2082 0 : }
2083 :
2084 : /**
2085 : * intel_runtime_pm_get - grab a runtime pm reference
2086 : * @dev_priv: i915 device instance
2087 : *
2088 : * This function grabs a device-level runtime pm reference (mostly used for GEM
2089 : * code to ensure the GTT or GT is on) and ensures that it is powered up.
2090 : *
2091 : * Any runtime pm reference obtained by this function must have a symmetric
2092 : * call to intel_runtime_pm_put() to release the reference again.
2093 : */
2094 0 : void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2095 : {
2096 : #ifdef __linux__
2097 : struct drm_device *dev = dev_priv->dev;
2098 : struct device *device = &dev->pdev->dev;
2099 :
2100 : if (!HAS_RUNTIME_PM(dev))
2101 : return;
2102 :
2103 : pm_runtime_get_sync(device);
2104 : WARN(dev_priv->pm.suspended, "Device still suspended.\n");
2105 : #endif
2106 0 : }
2107 :
2108 : /**
2109 : * intel_runtime_pm_get_noresume - grab a runtime pm reference
2110 : * @dev_priv: i915 device instance
2111 : *
2112 : * This function grabs a device-level runtime pm reference (mostly used for GEM
2113 : * code to ensure the GTT or GT is on).
2114 : *
2115 : * It will _not_ power up the device but instead only check that it's powered
2116 : * on. Therefore it is only valid to call this functions from contexts where
2117 : * the device is known to be powered up and where trying to power it up would
2118 : * result in hilarity and deadlocks. That pretty much means only the system
2119 : * suspend/resume code where this is used to grab runtime pm references for
2120 : * delayed setup down in work items.
2121 : *
2122 : * Any runtime pm reference obtained by this function must have a symmetric
2123 : * call to intel_runtime_pm_put() to release the reference again.
2124 : */
2125 0 : void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2126 : {
2127 : #ifdef __linux__
2128 : struct drm_device *dev = dev_priv->dev;
2129 : struct device *device = &dev->pdev->dev;
2130 :
2131 : if (!HAS_RUNTIME_PM(dev))
2132 : return;
2133 :
2134 : WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
2135 : pm_runtime_get_noresume(device);
2136 : #endif
2137 0 : }
2138 :
2139 : /**
2140 : * intel_runtime_pm_put - release a runtime pm reference
2141 : * @dev_priv: i915 device instance
2142 : *
2143 : * This function drops the device-level runtime pm reference obtained by
2144 : * intel_runtime_pm_get() and might power down the corresponding
2145 : * hardware block right away if this is the last reference.
2146 : */
2147 0 : void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2148 : {
2149 : #ifdef __linux__
2150 : struct drm_device *dev = dev_priv->dev;
2151 : struct device *device = &dev->pdev->dev;
2152 :
2153 : if (!HAS_RUNTIME_PM(dev))
2154 : return;
2155 :
2156 : pm_runtime_mark_last_busy(device);
2157 : pm_runtime_put_autosuspend(device);
2158 : #endif
2159 0 : }
2160 :
2161 : /**
2162 : * intel_runtime_pm_enable - enable runtime pm
2163 : * @dev_priv: i915 device instance
2164 : *
2165 : * This function enables runtime pm at the end of the driver load sequence.
2166 : *
2167 : * Note that this function does currently not enable runtime pm for the
2168 : * subordinate display power domains. That is only done on the first modeset
2169 : * using intel_display_set_init_power().
2170 : */
2171 0 : void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2172 : {
2173 : #ifdef __linux__
2174 : struct drm_device *dev = dev_priv->dev;
2175 : struct device *device = &dev->pdev->dev;
2176 :
2177 : if (!HAS_RUNTIME_PM(dev))
2178 : return;
2179 :
2180 : /*
2181 : * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2182 : * requirement.
2183 : */
2184 : if (!intel_enable_rc6(dev)) {
2185 : DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2186 : return;
2187 : }
2188 :
2189 : pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2190 : pm_runtime_mark_last_busy(device);
2191 : pm_runtime_use_autosuspend(device);
2192 :
2193 : pm_runtime_put_autosuspend(device);
2194 : #endif
2195 0 : }
2196 :
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