Line data Source code
1 : /*
2 : * Copyright 2007-11 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: Dave Airlie
24 : * Alex Deucher
25 : */
26 : #include <dev/pci/drm/drmP.h>
27 : #include <dev/pci/drm/drm_crtc_helper.h>
28 : #include <dev/pci/drm/radeon_drm.h>
29 : #include "radeon.h"
30 : #include "radeon_audio.h"
31 : #include "atom.h"
32 :
33 : extern int atom_debug;
34 :
35 : static u8
36 0 : radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
37 : {
38 : u8 backlight_level;
39 : u32 bios_2_scratch;
40 :
41 0 : if (rdev->family >= CHIP_R600)
42 0 : bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
43 : else
44 0 : bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
45 :
46 0 : backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
47 : ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
48 :
49 0 : return backlight_level;
50 : }
51 :
52 : static void
53 0 : radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
54 : u8 backlight_level)
55 : {
56 : u32 bios_2_scratch;
57 :
58 0 : if (rdev->family >= CHIP_R600)
59 0 : bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
60 : else
61 0 : bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
62 :
63 0 : bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
64 0 : bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
65 : ATOM_S2_CURRENT_BL_LEVEL_MASK);
66 :
67 0 : if (rdev->family >= CHIP_R600)
68 0 : WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
69 : else
70 0 : WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
71 0 : }
72 :
73 : u8
74 0 : atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
75 : {
76 0 : struct drm_device *dev = radeon_encoder->base.dev;
77 0 : struct radeon_device *rdev = dev->dev_private;
78 :
79 0 : if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
80 0 : return 0;
81 :
82 0 : return radeon_atom_get_backlight_level_from_reg(rdev);
83 0 : }
84 :
85 : void
86 0 : atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
87 : {
88 0 : struct drm_encoder *encoder = &radeon_encoder->base;
89 0 : struct drm_device *dev = radeon_encoder->base.dev;
90 0 : struct radeon_device *rdev = dev->dev_private;
91 : struct radeon_encoder_atom_dig *dig;
92 0 : DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
93 : int index;
94 :
95 0 : if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
96 0 : return;
97 :
98 0 : if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
99 0 : radeon_encoder->enc_priv) {
100 0 : dig = radeon_encoder->enc_priv;
101 0 : dig->backlight_level = level;
102 0 : radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
103 :
104 0 : switch (radeon_encoder->encoder_id) {
105 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
106 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
107 : index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
108 0 : if (dig->backlight_level == 0) {
109 0 : args.ucAction = ATOM_LCD_BLOFF;
110 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
111 0 : } else {
112 0 : args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
113 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
114 0 : args.ucAction = ATOM_LCD_BLON;
115 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
116 : }
117 : break;
118 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
119 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
120 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
121 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
122 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
123 0 : if (dig->backlight_level == 0)
124 0 : atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125 : else {
126 0 : atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127 0 : atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
128 : }
129 : break;
130 : default:
131 : break;
132 : }
133 : }
134 0 : }
135 :
136 : #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137 :
138 0 : static u8 radeon_atom_bl_level(struct backlight_device *bd)
139 : {
140 : u8 level;
141 :
142 : /* Convert brightness to hardware level */
143 0 : if (bd->props.brightness < 0)
144 0 : level = 0;
145 0 : else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146 0 : level = RADEON_MAX_BL_LEVEL;
147 : else
148 0 : level = bd->props.brightness;
149 :
150 0 : return level;
151 : }
152 :
153 0 : static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154 : {
155 0 : struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156 0 : struct radeon_encoder *radeon_encoder = pdata->encoder;
157 :
158 0 : atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
159 :
160 0 : return 0;
161 : }
162 :
163 0 : static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164 : {
165 0 : struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166 0 : struct radeon_encoder *radeon_encoder = pdata->encoder;
167 0 : struct drm_device *dev = radeon_encoder->base.dev;
168 0 : struct radeon_device *rdev = dev->dev_private;
169 :
170 0 : return radeon_atom_get_backlight_level_from_reg(rdev);
171 : }
172 :
173 : static const struct backlight_ops radeon_atom_backlight_ops = {
174 : .get_brightness = radeon_atom_backlight_get_brightness,
175 : .update_status = radeon_atom_backlight_update_status,
176 : };
177 :
178 0 : void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179 : struct drm_connector *drm_connector)
180 : {
181 0 : struct drm_device *dev = radeon_encoder->base.dev;
182 0 : struct radeon_device *rdev = dev->dev_private;
183 : struct backlight_device *bd;
184 0 : struct backlight_properties props;
185 : struct radeon_backlight_privdata *pdata;
186 : struct radeon_encoder_atom_dig *dig;
187 0 : char bl_name[16];
188 :
189 : /* Mac laptops with multiple GPUs use the gmux driver for backlight
190 : * so don't register a backlight device
191 : */
192 0 : if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
193 0 : (rdev->pdev->device == 0x6741))
194 0 : return;
195 :
196 0 : if (!radeon_encoder->enc_priv)
197 0 : return;
198 :
199 0 : if (!rdev->is_atom_bios)
200 0 : return;
201 :
202 0 : if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
203 0 : return;
204 :
205 0 : pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
206 0 : if (!pdata) {
207 0 : DRM_ERROR("Memory allocation failed\n");
208 0 : goto error;
209 : }
210 :
211 0 : memset(&props, 0, sizeof(props));
212 0 : props.max_brightness = RADEON_MAX_BL_LEVEL;
213 0 : props.type = BACKLIGHT_RAW;
214 : #ifdef notyet
215 : snprintf(bl_name, sizeof(bl_name),
216 : "radeon_bl%d", dev->primary->index);
217 : #else
218 0 : snprintf(bl_name, sizeof(bl_name),
219 : "radeon_bl%d", 0);
220 : #endif
221 0 : bd = backlight_device_register(bl_name, drm_connector->kdev,
222 : pdata, &radeon_atom_backlight_ops, &props);
223 0 : if (IS_ERR(bd)) {
224 0 : DRM_ERROR("Backlight registration failed\n");
225 0 : goto error;
226 : }
227 :
228 0 : pdata->encoder = radeon_encoder;
229 :
230 0 : dig = radeon_encoder->enc_priv;
231 0 : dig->bl_dev = bd;
232 :
233 0 : bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
234 : /* Set a reasonable default here if the level is 0 otherwise
235 : * fbdev will attempt to turn the backlight on after console
236 : * unblanking and it will try and restore 0 which turns the backlight
237 : * off again.
238 : */
239 0 : if (bd->props.brightness == 0)
240 0 : bd->props.brightness = RADEON_MAX_BL_LEVEL;
241 0 : bd->props.power = FB_BLANK_UNBLANK;
242 0 : backlight_update_status(bd);
243 :
244 : DRM_INFO("radeon atom DIG backlight initialized\n");
245 0 : rdev->mode_info.bl_encoder = radeon_encoder;
246 :
247 0 : return;
248 :
249 : error:
250 0 : kfree(pdata);
251 0 : return;
252 0 : }
253 :
254 0 : static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
255 : {
256 0 : struct drm_device *dev = radeon_encoder->base.dev;
257 0 : struct radeon_device *rdev = dev->dev_private;
258 : struct backlight_device *bd = NULL;
259 : struct radeon_encoder_atom_dig *dig;
260 :
261 0 : if (!radeon_encoder->enc_priv)
262 0 : return;
263 :
264 0 : if (!rdev->is_atom_bios)
265 0 : return;
266 :
267 0 : if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
268 0 : return;
269 :
270 0 : dig = radeon_encoder->enc_priv;
271 0 : bd = dig->bl_dev;
272 0 : dig->bl_dev = NULL;
273 :
274 0 : if (bd) {
275 : struct radeon_legacy_backlight_privdata *pdata;
276 :
277 0 : pdata = bl_get_data(bd);
278 0 : backlight_device_unregister(bd);
279 0 : kfree(pdata);
280 :
281 : DRM_INFO("radeon atom LVDS backlight unloaded\n");
282 0 : }
283 0 : }
284 :
285 : #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
286 :
287 : void radeon_atom_backlight_init(struct radeon_encoder *encoder)
288 : {
289 : }
290 :
291 : static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
292 : {
293 : }
294 :
295 : #endif
296 :
297 : /* evil but including atombios.h is much worse */
298 : bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
299 : struct drm_display_mode *mode);
300 :
301 0 : static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
302 : const struct drm_display_mode *mode,
303 : struct drm_display_mode *adjusted_mode)
304 : {
305 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
306 0 : struct drm_device *dev = encoder->dev;
307 0 : struct radeon_device *rdev = dev->dev_private;
308 :
309 : /* set the active encoder to connector routing */
310 0 : radeon_encoder_set_active_device(encoder);
311 0 : drm_mode_set_crtcinfo(adjusted_mode, 0);
312 :
313 : /* hw bug */
314 0 : if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
315 0 : && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
316 0 : adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
317 :
318 : /* vertical FP must be at least 1 */
319 0 : if (mode->crtc_vsync_start == mode->crtc_vdisplay)
320 0 : adjusted_mode->crtc_vsync_start++;
321 :
322 : /* get the native mode for scaling */
323 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
324 0 : radeon_panel_mode_fixup(encoder, adjusted_mode);
325 0 : } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
326 0 : struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
327 0 : if (tv_dac) {
328 0 : if (tv_dac->tv_std == TV_STD_NTSC ||
329 0 : tv_dac->tv_std == TV_STD_NTSC_J ||
330 0 : tv_dac->tv_std == TV_STD_PAL_M)
331 0 : radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
332 : else
333 0 : radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
334 : }
335 0 : } else if (radeon_encoder->rmx_type != RMX_OFF) {
336 0 : radeon_panel_mode_fixup(encoder, adjusted_mode);
337 0 : }
338 :
339 0 : if (ASIC_IS_DCE3(rdev) &&
340 0 : ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
341 0 : (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
342 0 : struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
343 0 : radeon_dp_set_link_config(connector, adjusted_mode);
344 0 : }
345 :
346 0 : return true;
347 : }
348 :
349 : static void
350 0 : atombios_dac_setup(struct drm_encoder *encoder, int action)
351 : {
352 0 : struct drm_device *dev = encoder->dev;
353 0 : struct radeon_device *rdev = dev->dev_private;
354 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
355 0 : DAC_ENCODER_CONTROL_PS_ALLOCATION args;
356 : int index = 0;
357 0 : struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
358 :
359 0 : memset(&args, 0, sizeof(args));
360 :
361 0 : switch (radeon_encoder->encoder_id) {
362 : case ENCODER_OBJECT_ID_INTERNAL_DAC1:
363 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
364 : index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
365 0 : break;
366 : case ENCODER_OBJECT_ID_INTERNAL_DAC2:
367 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
368 : index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
369 0 : break;
370 : }
371 :
372 0 : args.ucAction = action;
373 :
374 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
375 0 : args.ucDacStandard = ATOM_DAC1_PS2;
376 0 : else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
377 0 : args.ucDacStandard = ATOM_DAC1_CV;
378 : else {
379 0 : switch (dac_info->tv_std) {
380 : case TV_STD_PAL:
381 : case TV_STD_PAL_M:
382 : case TV_STD_SCART_PAL:
383 : case TV_STD_SECAM:
384 : case TV_STD_PAL_CN:
385 0 : args.ucDacStandard = ATOM_DAC1_PAL;
386 0 : break;
387 : case TV_STD_NTSC:
388 : case TV_STD_NTSC_J:
389 : case TV_STD_PAL_60:
390 : default:
391 0 : args.ucDacStandard = ATOM_DAC1_NTSC;
392 0 : break;
393 : }
394 : }
395 0 : args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
396 :
397 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
398 :
399 0 : }
400 :
401 : static void
402 0 : atombios_tv_setup(struct drm_encoder *encoder, int action)
403 : {
404 0 : struct drm_device *dev = encoder->dev;
405 0 : struct radeon_device *rdev = dev->dev_private;
406 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
407 0 : TV_ENCODER_CONTROL_PS_ALLOCATION args;
408 : int index = 0;
409 0 : struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
410 :
411 0 : memset(&args, 0, sizeof(args));
412 :
413 : index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
414 :
415 0 : args.sTVEncoder.ucAction = action;
416 :
417 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
418 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
419 : else {
420 0 : switch (dac_info->tv_std) {
421 : case TV_STD_NTSC:
422 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
423 0 : break;
424 : case TV_STD_PAL:
425 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
426 0 : break;
427 : case TV_STD_PAL_M:
428 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
429 0 : break;
430 : case TV_STD_PAL_60:
431 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
432 0 : break;
433 : case TV_STD_NTSC_J:
434 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
435 0 : break;
436 : case TV_STD_SCART_PAL:
437 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
438 0 : break;
439 : case TV_STD_SECAM:
440 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
441 0 : break;
442 : case TV_STD_PAL_CN:
443 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
444 0 : break;
445 : default:
446 0 : args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
447 0 : break;
448 : }
449 : }
450 :
451 0 : args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
452 :
453 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
454 :
455 0 : }
456 :
457 0 : static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
458 : {
459 : int bpc = 8;
460 :
461 0 : if (encoder->crtc) {
462 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
463 0 : bpc = radeon_crtc->bpc;
464 0 : }
465 :
466 0 : switch (bpc) {
467 : case 0:
468 0 : return PANEL_BPC_UNDEFINE;
469 : case 6:
470 0 : return PANEL_6BIT_PER_COLOR;
471 : case 8:
472 : default:
473 0 : return PANEL_8BIT_PER_COLOR;
474 : case 10:
475 0 : return PANEL_10BIT_PER_COLOR;
476 : case 12:
477 0 : return PANEL_12BIT_PER_COLOR;
478 : case 16:
479 0 : return PANEL_16BIT_PER_COLOR;
480 : }
481 0 : }
482 :
483 : union dvo_encoder_control {
484 : ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
485 : DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
486 : DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
487 : DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
488 : };
489 :
490 : void
491 0 : atombios_dvo_setup(struct drm_encoder *encoder, int action)
492 : {
493 0 : struct drm_device *dev = encoder->dev;
494 0 : struct radeon_device *rdev = dev->dev_private;
495 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
496 0 : union dvo_encoder_control args;
497 : int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
498 0 : uint8_t frev, crev;
499 :
500 0 : memset(&args, 0, sizeof(args));
501 :
502 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
503 0 : return;
504 :
505 : /* some R4xx chips have the wrong frev */
506 0 : if (rdev->family <= CHIP_RV410)
507 0 : frev = 1;
508 :
509 0 : switch (frev) {
510 : case 1:
511 0 : switch (crev) {
512 : case 1:
513 : /* R4xx, R5xx */
514 0 : args.ext_tmds.sXTmdsEncoder.ucEnable = action;
515 :
516 0 : if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
517 0 : args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
518 :
519 0 : args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
520 0 : break;
521 : case 2:
522 : /* RS600/690/740 */
523 0 : args.dvo.sDVOEncoder.ucAction = action;
524 0 : args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
525 : /* DFP1, CRT1, TV1 depending on the type of port */
526 0 : args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
527 :
528 0 : if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
529 0 : args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
530 : break;
531 : case 3:
532 : /* R6xx */
533 0 : args.dvo_v3.ucAction = action;
534 0 : args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
535 0 : args.dvo_v3.ucDVOConfig = 0; /* XXX */
536 0 : break;
537 : case 4:
538 : /* DCE8 */
539 0 : args.dvo_v4.ucAction = action;
540 0 : args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
541 0 : args.dvo_v4.ucDVOConfig = 0; /* XXX */
542 0 : args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
543 0 : break;
544 : default:
545 0 : DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
546 0 : break;
547 : }
548 : break;
549 : default:
550 0 : DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
551 0 : break;
552 : }
553 :
554 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
555 0 : }
556 :
557 : union lvds_encoder_control {
558 : LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
559 : LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
560 : };
561 :
562 : void
563 0 : atombios_digital_setup(struct drm_encoder *encoder, int action)
564 : {
565 0 : struct drm_device *dev = encoder->dev;
566 0 : struct radeon_device *rdev = dev->dev_private;
567 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
568 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
569 0 : union lvds_encoder_control args;
570 : int index = 0;
571 : int hdmi_detected = 0;
572 0 : uint8_t frev, crev;
573 :
574 0 : if (!dig)
575 0 : return;
576 :
577 0 : if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
578 0 : hdmi_detected = 1;
579 :
580 0 : memset(&args, 0, sizeof(args));
581 :
582 0 : switch (radeon_encoder->encoder_id) {
583 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
584 : index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
585 0 : break;
586 : case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
587 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
588 : index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
589 0 : break;
590 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
591 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
592 0 : index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
593 : else
594 : index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
595 : break;
596 : }
597 :
598 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
599 0 : return;
600 :
601 0 : switch (frev) {
602 : case 1:
603 : case 2:
604 0 : switch (crev) {
605 : case 1:
606 0 : args.v1.ucMisc = 0;
607 0 : args.v1.ucAction = action;
608 0 : if (hdmi_detected)
609 0 : args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
610 0 : args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
611 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
612 0 : if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
613 0 : args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
614 0 : if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
615 0 : args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
616 : } else {
617 0 : if (dig->linkb)
618 0 : args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
619 0 : if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
620 0 : args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
621 : /*if (pScrn->rgbBits == 8) */
622 0 : args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
623 : }
624 : break;
625 : case 2:
626 : case 3:
627 0 : args.v2.ucMisc = 0;
628 0 : args.v2.ucAction = action;
629 0 : if (crev == 3) {
630 0 : if (dig->coherent_mode)
631 0 : args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
632 : }
633 0 : if (hdmi_detected)
634 0 : args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
635 0 : args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
636 0 : args.v2.ucTruncate = 0;
637 0 : args.v2.ucSpatial = 0;
638 0 : args.v2.ucTemporal = 0;
639 0 : args.v2.ucFRC = 0;
640 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
641 0 : if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
642 0 : args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
643 0 : if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
644 0 : args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
645 0 : if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
646 0 : args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
647 : }
648 0 : if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
649 0 : args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
650 0 : if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
651 0 : args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
652 0 : if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
653 0 : args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
654 : }
655 : } else {
656 0 : if (dig->linkb)
657 0 : args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
658 0 : if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
659 0 : args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
660 : }
661 : break;
662 : default:
663 0 : DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
664 0 : break;
665 : }
666 : break;
667 : default:
668 0 : DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
669 0 : break;
670 : }
671 :
672 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
673 0 : }
674 :
675 : int
676 0 : atombios_get_encoder_mode(struct drm_encoder *encoder)
677 : {
678 0 : struct drm_device *dev = encoder->dev;
679 0 : struct radeon_device *rdev = dev->dev_private;
680 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
681 : struct drm_connector *connector;
682 : struct radeon_connector *radeon_connector;
683 : struct radeon_connector_atom_dig *dig_connector;
684 : struct radeon_encoder_atom_dig *dig_enc;
685 :
686 0 : if (radeon_encoder_is_digital(encoder)) {
687 0 : dig_enc = radeon_encoder->enc_priv;
688 0 : if (dig_enc->active_mst_links)
689 0 : return ATOM_ENCODER_MODE_DP_MST;
690 : }
691 0 : if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
692 0 : return ATOM_ENCODER_MODE_DP_MST;
693 : /* dp bridges are always DP */
694 0 : if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
695 0 : return ATOM_ENCODER_MODE_DP;
696 :
697 : /* DVO is always DVO */
698 0 : if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
699 0 : (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
700 0 : return ATOM_ENCODER_MODE_DVO;
701 :
702 0 : connector = radeon_get_connector_for_encoder(encoder);
703 : /* if we don't have an active device yet, just use one of
704 : * the connectors tied to the encoder.
705 : */
706 0 : if (!connector)
707 0 : connector = radeon_get_connector_for_encoder_init(encoder);
708 0 : radeon_connector = to_radeon_connector(connector);
709 :
710 0 : switch (connector->connector_type) {
711 : case DRM_MODE_CONNECTOR_DVII:
712 : case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
713 0 : if (radeon_audio != 0) {
714 0 : if (radeon_connector->use_digital &&
715 0 : (radeon_connector->audio == RADEON_AUDIO_ENABLE))
716 0 : return ATOM_ENCODER_MODE_HDMI;
717 0 : else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
718 0 : (radeon_connector->audio == RADEON_AUDIO_AUTO))
719 0 : return ATOM_ENCODER_MODE_HDMI;
720 0 : else if (radeon_connector->use_digital)
721 0 : return ATOM_ENCODER_MODE_DVI;
722 : else
723 0 : return ATOM_ENCODER_MODE_CRT;
724 0 : } else if (radeon_connector->use_digital) {
725 0 : return ATOM_ENCODER_MODE_DVI;
726 : } else {
727 0 : return ATOM_ENCODER_MODE_CRT;
728 : }
729 : break;
730 : case DRM_MODE_CONNECTOR_DVID:
731 : case DRM_MODE_CONNECTOR_HDMIA:
732 : default:
733 0 : if (radeon_audio != 0) {
734 0 : if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
735 0 : return ATOM_ENCODER_MODE_HDMI;
736 0 : else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
737 0 : (radeon_connector->audio == RADEON_AUDIO_AUTO))
738 0 : return ATOM_ENCODER_MODE_HDMI;
739 : else
740 0 : return ATOM_ENCODER_MODE_DVI;
741 : } else {
742 0 : return ATOM_ENCODER_MODE_DVI;
743 : }
744 : break;
745 : case DRM_MODE_CONNECTOR_LVDS:
746 0 : return ATOM_ENCODER_MODE_LVDS;
747 : break;
748 : case DRM_MODE_CONNECTOR_DisplayPort:
749 0 : dig_connector = radeon_connector->con_priv;
750 0 : if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
751 0 : (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
752 0 : if (radeon_audio != 0 &&
753 0 : drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
754 0 : ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
755 0 : return ATOM_ENCODER_MODE_DP_AUDIO;
756 0 : return ATOM_ENCODER_MODE_DP;
757 0 : } else if (radeon_audio != 0) {
758 0 : if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
759 0 : return ATOM_ENCODER_MODE_HDMI;
760 0 : else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
761 0 : (radeon_connector->audio == RADEON_AUDIO_AUTO))
762 0 : return ATOM_ENCODER_MODE_HDMI;
763 : else
764 0 : return ATOM_ENCODER_MODE_DVI;
765 : } else {
766 0 : return ATOM_ENCODER_MODE_DVI;
767 : }
768 : break;
769 : case DRM_MODE_CONNECTOR_eDP:
770 0 : if (radeon_audio != 0 &&
771 0 : drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
772 0 : ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
773 0 : return ATOM_ENCODER_MODE_DP_AUDIO;
774 0 : return ATOM_ENCODER_MODE_DP;
775 : case DRM_MODE_CONNECTOR_DVIA:
776 : case DRM_MODE_CONNECTOR_VGA:
777 0 : return ATOM_ENCODER_MODE_CRT;
778 : break;
779 : case DRM_MODE_CONNECTOR_Composite:
780 : case DRM_MODE_CONNECTOR_SVIDEO:
781 : case DRM_MODE_CONNECTOR_9PinDIN:
782 : /* fix me */
783 0 : return ATOM_ENCODER_MODE_TV;
784 : /*return ATOM_ENCODER_MODE_CV;*/
785 : break;
786 : }
787 0 : }
788 :
789 : /*
790 : * DIG Encoder/Transmitter Setup
791 : *
792 : * DCE 3.0/3.1
793 : * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
794 : * Supports up to 3 digital outputs
795 : * - 2 DIG encoder blocks.
796 : * DIG1 can drive UNIPHY link A or link B
797 : * DIG2 can drive UNIPHY link B or LVTMA
798 : *
799 : * DCE 3.2
800 : * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
801 : * Supports up to 5 digital outputs
802 : * - 2 DIG encoder blocks.
803 : * DIG1/2 can drive UNIPHY0/1/2 link A or link B
804 : *
805 : * DCE 4.0/5.0/6.0
806 : * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
807 : * Supports up to 6 digital outputs
808 : * - 6 DIG encoder blocks.
809 : * - DIG to PHY mapping is hardcoded
810 : * DIG1 drives UNIPHY0 link A, A+B
811 : * DIG2 drives UNIPHY0 link B
812 : * DIG3 drives UNIPHY1 link A, A+B
813 : * DIG4 drives UNIPHY1 link B
814 : * DIG5 drives UNIPHY2 link A, A+B
815 : * DIG6 drives UNIPHY2 link B
816 : *
817 : * DCE 4.1
818 : * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
819 : * Supports up to 6 digital outputs
820 : * - 2 DIG encoder blocks.
821 : * llano
822 : * DIG1/2 can drive UNIPHY0/1/2 link A or link B
823 : * ontario
824 : * DIG1 drives UNIPHY0/1/2 link A
825 : * DIG2 drives UNIPHY0/1/2 link B
826 : *
827 : * Routing
828 : * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
829 : * Examples:
830 : * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
831 : * crtc1 -> dig1 -> UNIPHY0 link B -> DP
832 : * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
833 : * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
834 : */
835 :
836 : union dig_encoder_control {
837 : DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
838 : DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
839 : DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
840 : DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
841 : };
842 :
843 : void
844 0 : atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
845 : {
846 0 : struct drm_device *dev = encoder->dev;
847 0 : struct radeon_device *rdev = dev->dev_private;
848 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
849 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
850 0 : struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
851 0 : union dig_encoder_control args;
852 : int index = 0;
853 0 : uint8_t frev, crev;
854 : int dp_clock = 0;
855 : int dp_lane_count = 0;
856 : int hpd_id = RADEON_HPD_NONE;
857 :
858 0 : if (connector) {
859 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
860 : struct radeon_connector_atom_dig *dig_connector =
861 0 : radeon_connector->con_priv;
862 :
863 0 : dp_clock = dig_connector->dp_clock;
864 0 : dp_lane_count = dig_connector->dp_lane_count;
865 0 : hpd_id = radeon_connector->hpd.hpd;
866 0 : }
867 :
868 : /* no dig encoder assigned */
869 0 : if (dig->dig_encoder == -1)
870 0 : return;
871 :
872 0 : memset(&args, 0, sizeof(args));
873 :
874 0 : if (ASIC_IS_DCE4(rdev))
875 0 : index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
876 : else {
877 0 : if (dig->dig_encoder)
878 0 : index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
879 : else
880 : index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
881 : }
882 :
883 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
884 0 : return;
885 :
886 0 : switch (frev) {
887 : case 1:
888 0 : switch (crev) {
889 : case 1:
890 0 : args.v1.ucAction = action;
891 0 : args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
892 0 : if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
893 0 : args.v3.ucPanelMode = panel_mode;
894 : else
895 0 : args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
896 :
897 0 : if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
898 0 : args.v1.ucLaneNum = dp_lane_count;
899 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
900 0 : args.v1.ucLaneNum = 8;
901 : else
902 0 : args.v1.ucLaneNum = 4;
903 :
904 0 : switch (radeon_encoder->encoder_id) {
905 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
906 0 : args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
907 0 : break;
908 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
909 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
910 0 : args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
911 0 : break;
912 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
913 0 : args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
914 0 : break;
915 : }
916 0 : if (dig->linkb)
917 0 : args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
918 : else
919 : args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
920 :
921 0 : if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
922 0 : args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
923 :
924 : break;
925 : case 2:
926 : case 3:
927 0 : args.v3.ucAction = action;
928 0 : args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
929 0 : if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
930 0 : args.v3.ucPanelMode = panel_mode;
931 : else
932 0 : args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
933 :
934 0 : if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
935 0 : args.v3.ucLaneNum = dp_lane_count;
936 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
937 0 : args.v3.ucLaneNum = 8;
938 : else
939 0 : args.v3.ucLaneNum = 4;
940 :
941 0 : if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
942 0 : args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
943 0 : if (enc_override != -1)
944 0 : args.v3.acConfig.ucDigSel = enc_override;
945 : else
946 0 : args.v3.acConfig.ucDigSel = dig->dig_encoder;
947 0 : args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
948 0 : break;
949 : case 4:
950 0 : args.v4.ucAction = action;
951 0 : args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
952 0 : if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
953 0 : args.v4.ucPanelMode = panel_mode;
954 : else
955 0 : args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
956 :
957 0 : if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
958 0 : args.v4.ucLaneNum = dp_lane_count;
959 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
960 0 : args.v4.ucLaneNum = 8;
961 : else
962 0 : args.v4.ucLaneNum = 4;
963 :
964 0 : if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
965 0 : if (dp_clock == 540000)
966 0 : args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
967 0 : else if (dp_clock == 324000)
968 0 : args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
969 0 : else if (dp_clock == 270000)
970 0 : args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
971 : else
972 : args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
973 : }
974 :
975 0 : if (enc_override != -1)
976 0 : args.v4.acConfig.ucDigSel = enc_override;
977 : else
978 0 : args.v4.acConfig.ucDigSel = dig->dig_encoder;
979 0 : args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
980 0 : if (hpd_id == RADEON_HPD_NONE)
981 0 : args.v4.ucHPD_ID = 0;
982 : else
983 0 : args.v4.ucHPD_ID = hpd_id + 1;
984 : break;
985 : default:
986 0 : DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
987 0 : break;
988 : }
989 : break;
990 : default:
991 0 : DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
992 0 : break;
993 : }
994 :
995 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
996 :
997 0 : }
998 :
999 : void
1000 0 : atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
1001 : {
1002 0 : atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
1003 0 : }
1004 :
1005 : union dig_transmitter_control {
1006 : DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1007 : DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1008 : DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1009 : DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1010 : DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1011 : };
1012 :
1013 : void
1014 0 : atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1015 : {
1016 0 : struct drm_device *dev = encoder->dev;
1017 0 : struct radeon_device *rdev = dev->dev_private;
1018 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1019 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1020 : struct drm_connector *connector;
1021 0 : union dig_transmitter_control args;
1022 : int index = 0;
1023 0 : uint8_t frev, crev;
1024 : bool is_dp = false;
1025 : int pll_id = 0;
1026 : int dp_clock = 0;
1027 : int dp_lane_count = 0;
1028 : int connector_object_id = 0;
1029 : int igp_lane_info = 0;
1030 0 : int dig_encoder = dig->dig_encoder;
1031 : int hpd_id = RADEON_HPD_NONE;
1032 :
1033 0 : if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1034 0 : connector = radeon_get_connector_for_encoder_init(encoder);
1035 : /* just needed to avoid bailing in the encoder check. the encoder
1036 : * isn't used for init
1037 : */
1038 : dig_encoder = 0;
1039 0 : } else
1040 0 : connector = radeon_get_connector_for_encoder(encoder);
1041 :
1042 0 : if (connector) {
1043 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1044 : struct radeon_connector_atom_dig *dig_connector =
1045 0 : radeon_connector->con_priv;
1046 :
1047 0 : hpd_id = radeon_connector->hpd.hpd;
1048 0 : dp_clock = dig_connector->dp_clock;
1049 0 : dp_lane_count = dig_connector->dp_lane_count;
1050 : connector_object_id =
1051 0 : (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1052 0 : igp_lane_info = dig_connector->igp_lane_info;
1053 0 : }
1054 :
1055 0 : if (encoder->crtc) {
1056 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1057 0 : pll_id = radeon_crtc->pll_id;
1058 0 : }
1059 :
1060 : /* no dig encoder assigned */
1061 0 : if (dig_encoder == -1)
1062 0 : return;
1063 :
1064 0 : if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1065 0 : is_dp = true;
1066 :
1067 0 : memset(&args, 0, sizeof(args));
1068 :
1069 0 : switch (radeon_encoder->encoder_id) {
1070 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1071 : index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1072 0 : break;
1073 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1074 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1075 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1076 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1077 : index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1078 0 : break;
1079 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1080 : index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1081 0 : break;
1082 : }
1083 :
1084 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1085 0 : return;
1086 :
1087 0 : switch (frev) {
1088 : case 1:
1089 0 : switch (crev) {
1090 : case 1:
1091 0 : args.v1.ucAction = action;
1092 0 : if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1093 0 : args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1094 0 : } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1095 0 : args.v1.asMode.ucLaneSel = lane_num;
1096 0 : args.v1.asMode.ucLaneSet = lane_set;
1097 0 : } else {
1098 0 : if (is_dp)
1099 0 : args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1100 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1101 0 : args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1102 : else
1103 0 : args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1104 : }
1105 :
1106 0 : args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1107 :
1108 0 : if (dig_encoder)
1109 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1110 : else
1111 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1112 :
1113 0 : if ((rdev->flags & RADEON_IS_IGP) &&
1114 0 : (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1115 0 : if (is_dp ||
1116 0 : !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1117 0 : if (igp_lane_info & 0x1)
1118 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1119 0 : else if (igp_lane_info & 0x2)
1120 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1121 0 : else if (igp_lane_info & 0x4)
1122 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1123 0 : else if (igp_lane_info & 0x8)
1124 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1125 : } else {
1126 0 : if (igp_lane_info & 0x3)
1127 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1128 0 : else if (igp_lane_info & 0xc)
1129 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1130 : }
1131 : }
1132 :
1133 0 : if (dig->linkb)
1134 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1135 : else
1136 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1137 :
1138 0 : if (is_dp)
1139 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1140 0 : else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1141 0 : if (dig->coherent_mode)
1142 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1143 0 : if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1144 0 : args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1145 : }
1146 : break;
1147 : case 2:
1148 0 : args.v2.ucAction = action;
1149 0 : if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1150 0 : args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1151 0 : } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1152 0 : args.v2.asMode.ucLaneSel = lane_num;
1153 0 : args.v2.asMode.ucLaneSet = lane_set;
1154 0 : } else {
1155 0 : if (is_dp)
1156 0 : args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1157 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1158 0 : args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1159 : else
1160 0 : args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1161 : }
1162 :
1163 0 : args.v2.acConfig.ucEncoderSel = dig_encoder;
1164 0 : if (dig->linkb)
1165 0 : args.v2.acConfig.ucLinkSel = 1;
1166 :
1167 0 : switch (radeon_encoder->encoder_id) {
1168 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1169 0 : args.v2.acConfig.ucTransmitterSel = 0;
1170 0 : break;
1171 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1172 0 : args.v2.acConfig.ucTransmitterSel = 1;
1173 0 : break;
1174 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1175 0 : args.v2.acConfig.ucTransmitterSel = 2;
1176 0 : break;
1177 : }
1178 :
1179 0 : if (is_dp) {
1180 0 : args.v2.acConfig.fCoherentMode = 1;
1181 0 : args.v2.acConfig.fDPConnector = 1;
1182 0 : } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1183 0 : if (dig->coherent_mode)
1184 0 : args.v2.acConfig.fCoherentMode = 1;
1185 0 : if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1186 0 : args.v2.acConfig.fDualLinkConnector = 1;
1187 : }
1188 : break;
1189 : case 3:
1190 0 : args.v3.ucAction = action;
1191 0 : if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1192 0 : args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1193 0 : } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1194 0 : args.v3.asMode.ucLaneSel = lane_num;
1195 0 : args.v3.asMode.ucLaneSet = lane_set;
1196 0 : } else {
1197 0 : if (is_dp)
1198 0 : args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1199 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1200 0 : args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1201 : else
1202 0 : args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1203 : }
1204 :
1205 0 : if (is_dp)
1206 0 : args.v3.ucLaneNum = dp_lane_count;
1207 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1208 0 : args.v3.ucLaneNum = 8;
1209 : else
1210 0 : args.v3.ucLaneNum = 4;
1211 :
1212 0 : if (dig->linkb)
1213 0 : args.v3.acConfig.ucLinkSel = 1;
1214 0 : if (dig_encoder & 1)
1215 0 : args.v3.acConfig.ucEncoderSel = 1;
1216 :
1217 : /* Select the PLL for the PHY
1218 : * DP PHY should be clocked from external src if there is
1219 : * one.
1220 : */
1221 : /* On DCE4, if there is an external clock, it generates the DP ref clock */
1222 0 : if (is_dp && rdev->clock.dp_extclk)
1223 0 : args.v3.acConfig.ucRefClkSource = 2; /* external src */
1224 : else
1225 0 : args.v3.acConfig.ucRefClkSource = pll_id;
1226 :
1227 0 : switch (radeon_encoder->encoder_id) {
1228 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1229 0 : args.v3.acConfig.ucTransmitterSel = 0;
1230 0 : break;
1231 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1232 0 : args.v3.acConfig.ucTransmitterSel = 1;
1233 0 : break;
1234 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1235 0 : args.v3.acConfig.ucTransmitterSel = 2;
1236 0 : break;
1237 : }
1238 :
1239 0 : if (is_dp)
1240 0 : args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1241 0 : else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1242 0 : if (dig->coherent_mode)
1243 0 : args.v3.acConfig.fCoherentMode = 1;
1244 0 : if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1245 0 : args.v3.acConfig.fDualLinkConnector = 1;
1246 : }
1247 : break;
1248 : case 4:
1249 0 : args.v4.ucAction = action;
1250 0 : if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1251 0 : args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1252 0 : } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1253 0 : args.v4.asMode.ucLaneSel = lane_num;
1254 0 : args.v4.asMode.ucLaneSet = lane_set;
1255 0 : } else {
1256 0 : if (is_dp)
1257 0 : args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1258 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1259 0 : args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1260 : else
1261 0 : args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1262 : }
1263 :
1264 0 : if (is_dp)
1265 0 : args.v4.ucLaneNum = dp_lane_count;
1266 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1267 0 : args.v4.ucLaneNum = 8;
1268 : else
1269 0 : args.v4.ucLaneNum = 4;
1270 :
1271 0 : if (dig->linkb)
1272 0 : args.v4.acConfig.ucLinkSel = 1;
1273 0 : if (dig_encoder & 1)
1274 0 : args.v4.acConfig.ucEncoderSel = 1;
1275 :
1276 : /* Select the PLL for the PHY
1277 : * DP PHY should be clocked from external src if there is
1278 : * one.
1279 : */
1280 : /* On DCE5 DCPLL usually generates the DP ref clock */
1281 0 : if (is_dp) {
1282 0 : if (rdev->clock.dp_extclk)
1283 0 : args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1284 : else
1285 0 : args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1286 : } else
1287 0 : args.v4.acConfig.ucRefClkSource = pll_id;
1288 :
1289 0 : switch (radeon_encoder->encoder_id) {
1290 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1291 0 : args.v4.acConfig.ucTransmitterSel = 0;
1292 0 : break;
1293 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1294 0 : args.v4.acConfig.ucTransmitterSel = 1;
1295 0 : break;
1296 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1297 0 : args.v4.acConfig.ucTransmitterSel = 2;
1298 0 : break;
1299 : }
1300 :
1301 0 : if (is_dp)
1302 0 : args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1303 0 : else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1304 0 : if (dig->coherent_mode)
1305 0 : args.v4.acConfig.fCoherentMode = 1;
1306 0 : if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1307 0 : args.v4.acConfig.fDualLinkConnector = 1;
1308 : }
1309 : break;
1310 : case 5:
1311 0 : args.v5.ucAction = action;
1312 0 : if (is_dp)
1313 0 : args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1314 : else
1315 0 : args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1316 :
1317 0 : switch (radeon_encoder->encoder_id) {
1318 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1319 0 : if (dig->linkb)
1320 0 : args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1321 : else
1322 0 : args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1323 : break;
1324 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1325 0 : if (dig->linkb)
1326 0 : args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1327 : else
1328 0 : args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1329 : break;
1330 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1331 0 : if (dig->linkb)
1332 0 : args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1333 : else
1334 0 : args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1335 : break;
1336 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1337 0 : args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1338 0 : break;
1339 : }
1340 0 : if (is_dp)
1341 0 : args.v5.ucLaneNum = dp_lane_count;
1342 0 : else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1343 0 : args.v5.ucLaneNum = 8;
1344 : else
1345 0 : args.v5.ucLaneNum = 4;
1346 0 : args.v5.ucConnObjId = connector_object_id;
1347 0 : args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1348 :
1349 0 : if (is_dp && rdev->clock.dp_extclk)
1350 0 : args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1351 : else
1352 0 : args.v5.asConfig.ucPhyClkSrcId = pll_id;
1353 :
1354 0 : if (is_dp)
1355 0 : args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1356 0 : else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1357 0 : if (dig->coherent_mode)
1358 0 : args.v5.asConfig.ucCoherentMode = 1;
1359 : }
1360 0 : if (hpd_id == RADEON_HPD_NONE)
1361 0 : args.v5.asConfig.ucHPDSel = 0;
1362 : else
1363 0 : args.v5.asConfig.ucHPDSel = hpd_id + 1;
1364 0 : args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1365 0 : args.v5.ucDPLaneSet = lane_set;
1366 0 : break;
1367 : default:
1368 0 : DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1369 0 : break;
1370 : }
1371 : break;
1372 : default:
1373 0 : DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1374 0 : break;
1375 : }
1376 :
1377 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1378 0 : }
1379 :
1380 : void
1381 0 : atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1382 : {
1383 0 : atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1384 0 : }
1385 :
1386 : bool
1387 0 : atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1388 : {
1389 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1390 0 : struct drm_device *dev = radeon_connector->base.dev;
1391 0 : struct radeon_device *rdev = dev->dev_private;
1392 0 : union dig_transmitter_control args;
1393 : int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1394 0 : uint8_t frev, crev;
1395 :
1396 0 : if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1397 : goto done;
1398 :
1399 0 : if (!ASIC_IS_DCE4(rdev))
1400 : goto done;
1401 :
1402 0 : if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1403 0 : (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1404 : goto done;
1405 :
1406 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1407 : goto done;
1408 :
1409 0 : memset(&args, 0, sizeof(args));
1410 :
1411 0 : args.v1.ucAction = action;
1412 :
1413 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1414 :
1415 : /* wait for the panel to power up */
1416 0 : if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1417 : int i;
1418 :
1419 0 : for (i = 0; i < 300; i++) {
1420 0 : if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1421 0 : return true;
1422 0 : mdelay(1);
1423 : }
1424 0 : return false;
1425 : }
1426 : done:
1427 0 : return true;
1428 0 : }
1429 :
1430 : union external_encoder_control {
1431 : EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1432 : EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1433 : };
1434 :
1435 : static void
1436 0 : atombios_external_encoder_setup(struct drm_encoder *encoder,
1437 : struct drm_encoder *ext_encoder,
1438 : int action)
1439 : {
1440 0 : struct drm_device *dev = encoder->dev;
1441 0 : struct radeon_device *rdev = dev->dev_private;
1442 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1443 0 : struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1444 0 : union external_encoder_control args;
1445 : struct drm_connector *connector;
1446 : int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1447 0 : u8 frev, crev;
1448 : int dp_clock = 0;
1449 : int dp_lane_count = 0;
1450 : int connector_object_id = 0;
1451 0 : u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1452 :
1453 0 : if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1454 0 : connector = radeon_get_connector_for_encoder_init(encoder);
1455 : else
1456 0 : connector = radeon_get_connector_for_encoder(encoder);
1457 :
1458 0 : if (connector) {
1459 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1460 : struct radeon_connector_atom_dig *dig_connector =
1461 0 : radeon_connector->con_priv;
1462 :
1463 0 : dp_clock = dig_connector->dp_clock;
1464 0 : dp_lane_count = dig_connector->dp_lane_count;
1465 : connector_object_id =
1466 0 : (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1467 0 : }
1468 :
1469 0 : memset(&args, 0, sizeof(args));
1470 :
1471 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1472 0 : return;
1473 :
1474 0 : switch (frev) {
1475 : case 1:
1476 : /* no params on frev 1 */
1477 : break;
1478 : case 2:
1479 0 : switch (crev) {
1480 : case 1:
1481 : case 2:
1482 0 : args.v1.sDigEncoder.ucAction = action;
1483 0 : args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1484 0 : args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1485 :
1486 0 : if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1487 0 : if (dp_clock == 270000)
1488 0 : args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1489 0 : args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1490 0 : } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1491 0 : args.v1.sDigEncoder.ucLaneNum = 8;
1492 : else
1493 0 : args.v1.sDigEncoder.ucLaneNum = 4;
1494 : break;
1495 : case 3:
1496 0 : args.v3.sExtEncoder.ucAction = action;
1497 0 : if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1498 0 : args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1499 : else
1500 0 : args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1501 0 : args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1502 :
1503 0 : if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1504 0 : if (dp_clock == 270000)
1505 0 : args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1506 0 : else if (dp_clock == 540000)
1507 0 : args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1508 0 : args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1509 0 : } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1510 0 : args.v3.sExtEncoder.ucLaneNum = 8;
1511 : else
1512 0 : args.v3.sExtEncoder.ucLaneNum = 4;
1513 0 : switch (ext_enum) {
1514 : case GRAPH_OBJECT_ENUM_ID1:
1515 0 : args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1516 0 : break;
1517 : case GRAPH_OBJECT_ENUM_ID2:
1518 0 : args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1519 0 : break;
1520 : case GRAPH_OBJECT_ENUM_ID3:
1521 0 : args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1522 0 : break;
1523 : }
1524 0 : args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1525 0 : break;
1526 : default:
1527 0 : DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1528 0 : return;
1529 : }
1530 : break;
1531 : default:
1532 0 : DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1533 0 : return;
1534 : }
1535 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1536 0 : }
1537 :
1538 : static void
1539 0 : atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1540 : {
1541 0 : struct drm_device *dev = encoder->dev;
1542 0 : struct radeon_device *rdev = dev->dev_private;
1543 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1544 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1545 0 : ENABLE_YUV_PS_ALLOCATION args;
1546 : int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1547 : uint32_t temp, reg;
1548 :
1549 0 : memset(&args, 0, sizeof(args));
1550 :
1551 0 : if (rdev->family >= CHIP_R600)
1552 0 : reg = R600_BIOS_3_SCRATCH;
1553 : else
1554 : reg = RADEON_BIOS_3_SCRATCH;
1555 :
1556 : /* XXX: fix up scratch reg handling */
1557 0 : temp = RREG32(reg);
1558 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1559 0 : WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1560 : (radeon_crtc->crtc_id << 18)));
1561 0 : else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1562 0 : WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1563 : else
1564 0 : WREG32(reg, 0);
1565 :
1566 0 : if (enable)
1567 0 : args.ucEnable = ATOM_ENABLE;
1568 0 : args.ucCRTC = radeon_crtc->crtc_id;
1569 :
1570 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1571 :
1572 0 : WREG32(reg, temp);
1573 0 : }
1574 :
1575 : static void
1576 0 : radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1577 : {
1578 0 : struct drm_device *dev = encoder->dev;
1579 0 : struct radeon_device *rdev = dev->dev_private;
1580 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1581 0 : DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1582 : int index = 0;
1583 :
1584 0 : memset(&args, 0, sizeof(args));
1585 :
1586 0 : switch (radeon_encoder->encoder_id) {
1587 : case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1588 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1589 : index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1590 0 : break;
1591 : case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1592 : case ENCODER_OBJECT_ID_INTERNAL_DDI:
1593 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1594 : index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1595 0 : break;
1596 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1597 : index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1598 0 : break;
1599 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1600 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1601 0 : index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1602 : else
1603 : index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1604 : break;
1605 : case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1606 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1607 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1608 0 : index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1609 0 : else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1610 0 : index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1611 : else
1612 : index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1613 : break;
1614 : case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1615 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1616 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1617 0 : index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1618 0 : else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1619 0 : index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1620 : else
1621 : index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1622 : break;
1623 : default:
1624 0 : return;
1625 : }
1626 :
1627 0 : switch (mode) {
1628 : case DRM_MODE_DPMS_ON:
1629 0 : args.ucAction = ATOM_ENABLE;
1630 : /* workaround for DVOOutputControl on some RS690 systems */
1631 0 : if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1632 0 : u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1633 0 : WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1634 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1635 0 : WREG32(RADEON_BIOS_3_SCRATCH, reg);
1636 0 : } else
1637 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1638 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1639 0 : if (rdev->mode_info.bl_encoder) {
1640 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1641 :
1642 0 : atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1643 0 : } else {
1644 0 : args.ucAction = ATOM_LCD_BLON;
1645 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1646 : }
1647 : }
1648 : break;
1649 : case DRM_MODE_DPMS_STANDBY:
1650 : case DRM_MODE_DPMS_SUSPEND:
1651 : case DRM_MODE_DPMS_OFF:
1652 0 : args.ucAction = ATOM_DISABLE;
1653 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1654 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1655 0 : args.ucAction = ATOM_LCD_BLOFF;
1656 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1657 0 : }
1658 : break;
1659 : }
1660 0 : }
1661 :
1662 : static void
1663 0 : radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1664 : {
1665 0 : struct drm_device *dev = encoder->dev;
1666 0 : struct radeon_device *rdev = dev->dev_private;
1667 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1668 0 : struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1669 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1670 0 : struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1671 : struct radeon_connector *radeon_connector = NULL;
1672 : struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1673 : bool travis_quirk = false;
1674 :
1675 0 : if (connector) {
1676 0 : radeon_connector = to_radeon_connector(connector);
1677 0 : radeon_dig_connector = radeon_connector->con_priv;
1678 0 : if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1679 0 : ENCODER_OBJECT_ID_TRAVIS) &&
1680 0 : (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1681 0 : !ASIC_IS_DCE5(rdev))
1682 0 : travis_quirk = true;
1683 : }
1684 :
1685 0 : switch (mode) {
1686 : case DRM_MODE_DPMS_ON:
1687 0 : if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1688 0 : if (!connector)
1689 0 : dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1690 : else
1691 0 : dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1692 :
1693 : /* setup and enable the encoder */
1694 0 : atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1695 0 : atombios_dig_encoder_setup(encoder,
1696 : ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1697 0 : dig->panel_mode);
1698 0 : if (ext_encoder) {
1699 0 : if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1700 0 : atombios_external_encoder_setup(encoder, ext_encoder,
1701 : EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1702 : }
1703 0 : } else if (ASIC_IS_DCE4(rdev)) {
1704 : /* setup and enable the encoder */
1705 0 : atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1706 0 : } else {
1707 : /* setup and enable the encoder and transmitter */
1708 0 : atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1709 0 : atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1710 : }
1711 0 : if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1712 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1713 0 : atombios_set_edp_panel_power(connector,
1714 : ATOM_TRANSMITTER_ACTION_POWER_ON);
1715 0 : radeon_dig_connector->edp_on = true;
1716 0 : }
1717 : }
1718 : /* enable the transmitter */
1719 0 : atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1720 0 : if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1721 : /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1722 0 : radeon_dp_link_train(encoder, connector);
1723 0 : if (ASIC_IS_DCE4(rdev))
1724 0 : atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1725 : }
1726 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1727 0 : if (rdev->mode_info.bl_encoder)
1728 0 : atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1729 : else
1730 0 : atombios_dig_transmitter_setup(encoder,
1731 : ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1732 : }
1733 0 : if (ext_encoder)
1734 0 : atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1735 : break;
1736 : case DRM_MODE_DPMS_STANDBY:
1737 : case DRM_MODE_DPMS_SUSPEND:
1738 : case DRM_MODE_DPMS_OFF:
1739 :
1740 : /* don't power off encoders with active MST links */
1741 0 : if (dig->active_mst_links)
1742 0 : return;
1743 :
1744 0 : if (ASIC_IS_DCE4(rdev)) {
1745 0 : if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1746 0 : atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1747 : }
1748 0 : if (ext_encoder)
1749 0 : atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1750 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1751 0 : atombios_dig_transmitter_setup(encoder,
1752 : ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1753 :
1754 0 : if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1755 0 : connector && !travis_quirk)
1756 0 : radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1757 0 : if (ASIC_IS_DCE4(rdev)) {
1758 : /* disable the transmitter */
1759 : atombios_dig_transmitter_setup(encoder,
1760 : ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1761 : } else {
1762 : /* disable the encoder and transmitter */
1763 : atombios_dig_transmitter_setup(encoder,
1764 : ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1765 0 : atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1766 : }
1767 0 : if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1768 0 : if (travis_quirk)
1769 0 : radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1770 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1771 0 : atombios_set_edp_panel_power(connector,
1772 : ATOM_TRANSMITTER_ACTION_POWER_OFF);
1773 0 : radeon_dig_connector->edp_on = false;
1774 0 : }
1775 : }
1776 : break;
1777 : }
1778 0 : }
1779 :
1780 : static void
1781 0 : radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1782 : {
1783 0 : struct drm_device *dev = encoder->dev;
1784 0 : struct radeon_device *rdev = dev->dev_private;
1785 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1786 0 : int encoder_mode = atombios_get_encoder_mode(encoder);
1787 :
1788 : DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1789 : radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1790 : radeon_encoder->active_device);
1791 :
1792 0 : if ((radeon_audio != 0) &&
1793 0 : ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1794 0 : ENCODER_MODE_IS_DP(encoder_mode)))
1795 0 : radeon_audio_dpms(encoder, mode);
1796 :
1797 0 : switch (radeon_encoder->encoder_id) {
1798 : case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1799 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1800 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1801 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1802 : case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1803 : case ENCODER_OBJECT_ID_INTERNAL_DDI:
1804 : case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1805 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1806 0 : radeon_atom_encoder_dpms_avivo(encoder, mode);
1807 0 : break;
1808 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1809 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1810 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1811 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1812 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1813 0 : radeon_atom_encoder_dpms_dig(encoder, mode);
1814 0 : break;
1815 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1816 0 : if (ASIC_IS_DCE5(rdev)) {
1817 0 : switch (mode) {
1818 : case DRM_MODE_DPMS_ON:
1819 0 : atombios_dvo_setup(encoder, ATOM_ENABLE);
1820 0 : break;
1821 : case DRM_MODE_DPMS_STANDBY:
1822 : case DRM_MODE_DPMS_SUSPEND:
1823 : case DRM_MODE_DPMS_OFF:
1824 0 : atombios_dvo_setup(encoder, ATOM_DISABLE);
1825 0 : break;
1826 : }
1827 0 : } else if (ASIC_IS_DCE3(rdev))
1828 0 : radeon_atom_encoder_dpms_dig(encoder, mode);
1829 : else
1830 0 : radeon_atom_encoder_dpms_avivo(encoder, mode);
1831 : break;
1832 : case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1833 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1834 0 : if (ASIC_IS_DCE5(rdev)) {
1835 0 : switch (mode) {
1836 : case DRM_MODE_DPMS_ON:
1837 0 : atombios_dac_setup(encoder, ATOM_ENABLE);
1838 0 : break;
1839 : case DRM_MODE_DPMS_STANDBY:
1840 : case DRM_MODE_DPMS_SUSPEND:
1841 : case DRM_MODE_DPMS_OFF:
1842 0 : atombios_dac_setup(encoder, ATOM_DISABLE);
1843 0 : break;
1844 : }
1845 : } else
1846 0 : radeon_atom_encoder_dpms_avivo(encoder, mode);
1847 : break;
1848 : default:
1849 0 : return;
1850 : }
1851 :
1852 0 : radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1853 :
1854 0 : }
1855 :
1856 : union crtc_source_param {
1857 : SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1858 : SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1859 : };
1860 :
1861 : static void
1862 0 : atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1863 : {
1864 0 : struct drm_device *dev = encoder->dev;
1865 0 : struct radeon_device *rdev = dev->dev_private;
1866 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1867 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1868 0 : union crtc_source_param args;
1869 : int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1870 0 : uint8_t frev, crev;
1871 : struct radeon_encoder_atom_dig *dig;
1872 :
1873 0 : memset(&args, 0, sizeof(args));
1874 :
1875 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1876 0 : return;
1877 :
1878 0 : switch (frev) {
1879 : case 1:
1880 0 : switch (crev) {
1881 : case 1:
1882 : default:
1883 0 : if (ASIC_IS_AVIVO(rdev))
1884 0 : args.v1.ucCRTC = radeon_crtc->crtc_id;
1885 : else {
1886 0 : if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1887 0 : args.v1.ucCRTC = radeon_crtc->crtc_id;
1888 0 : } else {
1889 0 : args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1890 : }
1891 : }
1892 0 : switch (radeon_encoder->encoder_id) {
1893 : case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1894 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1895 0 : args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1896 0 : break;
1897 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1898 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1899 0 : if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1900 0 : args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1901 : else
1902 0 : args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1903 : break;
1904 : case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1905 : case ENCODER_OBJECT_ID_INTERNAL_DDI:
1906 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1907 0 : args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1908 0 : break;
1909 : case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1910 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1911 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1912 0 : args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1913 0 : else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1914 0 : args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1915 : else
1916 0 : args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1917 : break;
1918 : case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1919 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1920 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1921 0 : args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1922 0 : else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1923 0 : args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1924 : else
1925 0 : args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1926 : break;
1927 : }
1928 : break;
1929 : case 2:
1930 0 : args.v2.ucCRTC = radeon_crtc->crtc_id;
1931 0 : if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1932 0 : struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1933 :
1934 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1935 0 : args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1936 0 : else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1937 0 : args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1938 : else
1939 0 : args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1940 0 : } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1941 0 : args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1942 0 : } else {
1943 0 : args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1944 : }
1945 0 : switch (radeon_encoder->encoder_id) {
1946 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1947 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1948 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1949 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1950 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1951 0 : dig = radeon_encoder->enc_priv;
1952 0 : switch (dig->dig_encoder) {
1953 : case 0:
1954 0 : args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1955 0 : break;
1956 : case 1:
1957 0 : args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1958 0 : break;
1959 : case 2:
1960 0 : args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1961 0 : break;
1962 : case 3:
1963 0 : args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1964 0 : break;
1965 : case 4:
1966 0 : args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1967 0 : break;
1968 : case 5:
1969 0 : args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1970 0 : break;
1971 : case 6:
1972 0 : args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1973 0 : break;
1974 : }
1975 : break;
1976 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1977 0 : args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1978 0 : break;
1979 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1980 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1981 0 : args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1982 0 : else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1983 0 : args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1984 : else
1985 0 : args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1986 : break;
1987 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1988 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1989 0 : args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1990 0 : else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1991 0 : args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1992 : else
1993 0 : args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1994 : break;
1995 : }
1996 : break;
1997 : }
1998 : break;
1999 : default:
2000 0 : DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
2001 0 : return;
2002 : }
2003 :
2004 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2005 :
2006 : /* update scratch regs with new routing */
2007 0 : radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2008 0 : }
2009 :
2010 : void
2011 0 : atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2012 : {
2013 0 : struct drm_device *dev = encoder->dev;
2014 0 : struct radeon_device *rdev = dev->dev_private;
2015 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2016 : int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2017 0 : uint8_t frev, crev;
2018 0 : union crtc_source_param args;
2019 :
2020 0 : memset(&args, 0, sizeof(args));
2021 :
2022 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2023 0 : return;
2024 :
2025 0 : if (frev != 1 && crev != 2)
2026 0 : DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2027 :
2028 0 : args.v2.ucCRTC = radeon_crtc->crtc_id;
2029 0 : args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2030 :
2031 0 : switch (fe) {
2032 : case 0:
2033 0 : args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2034 0 : break;
2035 : case 1:
2036 0 : args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2037 0 : break;
2038 : case 2:
2039 0 : args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2040 0 : break;
2041 : case 3:
2042 0 : args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2043 0 : break;
2044 : case 4:
2045 0 : args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2046 0 : break;
2047 : case 5:
2048 0 : args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2049 0 : break;
2050 : case 6:
2051 0 : args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2052 0 : break;
2053 : }
2054 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2055 0 : }
2056 :
2057 : static void
2058 0 : atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2059 : struct drm_display_mode *mode)
2060 : {
2061 0 : struct drm_device *dev = encoder->dev;
2062 0 : struct radeon_device *rdev = dev->dev_private;
2063 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2064 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2065 :
2066 : /* Funky macbooks */
2067 0 : if ((dev->pdev->device == 0x71C5) &&
2068 0 : (dev->pdev->subsystem_vendor == 0x106b) &&
2069 0 : (dev->pdev->subsystem_device == 0x0080)) {
2070 0 : if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2071 0 : uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2072 :
2073 0 : lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2074 0 : lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2075 :
2076 0 : WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2077 0 : }
2078 : }
2079 :
2080 : /* set scaler clears this on some chips */
2081 0 : if (ASIC_IS_AVIVO(rdev) &&
2082 0 : (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2083 0 : if (ASIC_IS_DCE8(rdev)) {
2084 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2085 0 : WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2086 : CIK_INTERLEAVE_EN);
2087 : else
2088 0 : WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2089 0 : } else if (ASIC_IS_DCE4(rdev)) {
2090 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2091 0 : WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2092 : EVERGREEN_INTERLEAVE_EN);
2093 : else
2094 0 : WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2095 : } else {
2096 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2097 0 : WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2098 : AVIVO_D1MODE_INTERLEAVE_EN);
2099 : else
2100 0 : WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2101 : }
2102 : }
2103 0 : }
2104 :
2105 0 : void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2106 : {
2107 0 : if (enc_idx < 0)
2108 : return;
2109 0 : rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2110 0 : }
2111 :
2112 0 : int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2113 : {
2114 0 : struct drm_device *dev = encoder->dev;
2115 0 : struct radeon_device *rdev = dev->dev_private;
2116 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2117 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2118 : struct drm_encoder *test_encoder;
2119 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2120 : uint32_t dig_enc_in_use = 0;
2121 : int enc_idx = -1;
2122 :
2123 0 : if (fe_idx >= 0) {
2124 : enc_idx = fe_idx;
2125 0 : goto assigned;
2126 : }
2127 0 : if (ASIC_IS_DCE6(rdev)) {
2128 : /* DCE6 */
2129 0 : switch (radeon_encoder->encoder_id) {
2130 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2131 0 : if (dig->linkb)
2132 0 : enc_idx = 1;
2133 : else
2134 : enc_idx = 0;
2135 : break;
2136 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2137 0 : if (dig->linkb)
2138 0 : enc_idx = 3;
2139 : else
2140 : enc_idx = 2;
2141 : break;
2142 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2143 0 : if (dig->linkb)
2144 0 : enc_idx = 5;
2145 : else
2146 : enc_idx = 4;
2147 : break;
2148 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2149 : enc_idx = 6;
2150 0 : break;
2151 : }
2152 : goto assigned;
2153 0 : } else if (ASIC_IS_DCE4(rdev)) {
2154 : /* DCE4/5 */
2155 0 : if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2156 : /* ontario follows DCE4 */
2157 0 : if (rdev->family == CHIP_PALM) {
2158 0 : if (dig->linkb)
2159 0 : enc_idx = 1;
2160 : else
2161 : enc_idx = 0;
2162 : } else
2163 : /* llano follows DCE3.2 */
2164 0 : enc_idx = radeon_crtc->crtc_id;
2165 : } else {
2166 0 : switch (radeon_encoder->encoder_id) {
2167 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2168 0 : if (dig->linkb)
2169 0 : enc_idx = 1;
2170 : else
2171 : enc_idx = 0;
2172 : break;
2173 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2174 0 : if (dig->linkb)
2175 0 : enc_idx = 3;
2176 : else
2177 : enc_idx = 2;
2178 : break;
2179 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2180 0 : if (dig->linkb)
2181 0 : enc_idx = 5;
2182 : else
2183 : enc_idx = 4;
2184 : break;
2185 : }
2186 : }
2187 : goto assigned;
2188 : }
2189 :
2190 : /*
2191 : * On DCE32 any encoder can drive any block so usually just use crtc id,
2192 : * but Apple thinks different at least on iMac10,1, so there use linkb,
2193 : * otherwise the internal eDP panel will stay dark.
2194 : */
2195 0 : if (ASIC_IS_DCE32(rdev)) {
2196 0 : if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
2197 0 : enc_idx = (dig->linkb) ? 1 : 0;
2198 : else
2199 0 : enc_idx = radeon_crtc->crtc_id;
2200 :
2201 : goto assigned;
2202 : }
2203 :
2204 : /* on DCE3 - LVTMA can only be driven by DIGB */
2205 0 : list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2206 : struct radeon_encoder *radeon_test_encoder;
2207 :
2208 0 : if (encoder == test_encoder)
2209 0 : continue;
2210 :
2211 0 : if (!radeon_encoder_is_digital(test_encoder))
2212 0 : continue;
2213 :
2214 0 : radeon_test_encoder = to_radeon_encoder(test_encoder);
2215 0 : dig = radeon_test_encoder->enc_priv;
2216 :
2217 0 : if (dig->dig_encoder >= 0)
2218 0 : dig_enc_in_use |= (1 << dig->dig_encoder);
2219 0 : }
2220 :
2221 0 : if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2222 0 : if (dig_enc_in_use & 0x2)
2223 0 : DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2224 0 : return 1;
2225 : }
2226 0 : if (!(dig_enc_in_use & 1))
2227 0 : return 0;
2228 0 : return 1;
2229 :
2230 : assigned:
2231 0 : if (enc_idx == -1) {
2232 0 : DRM_ERROR("Got encoder index incorrect - returning 0\n");
2233 0 : return 0;
2234 : }
2235 0 : if (rdev->mode_info.active_encoders & (1 << enc_idx)) {
2236 0 : DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2237 0 : }
2238 0 : rdev->mode_info.active_encoders |= (1 << enc_idx);
2239 0 : return enc_idx;
2240 0 : }
2241 :
2242 : /* This only needs to be called once at startup */
2243 : void
2244 0 : radeon_atom_encoder_init(struct radeon_device *rdev)
2245 : {
2246 0 : struct drm_device *dev = rdev->ddev;
2247 : struct drm_encoder *encoder;
2248 :
2249 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2250 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2251 0 : struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2252 :
2253 0 : switch (radeon_encoder->encoder_id) {
2254 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2255 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2256 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2257 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2258 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2259 0 : atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2260 0 : break;
2261 : default:
2262 : break;
2263 : }
2264 :
2265 0 : if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2266 0 : atombios_external_encoder_setup(encoder, ext_encoder,
2267 : EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2268 : }
2269 0 : }
2270 :
2271 : static void
2272 0 : radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2273 : struct drm_display_mode *mode,
2274 : struct drm_display_mode *adjusted_mode)
2275 : {
2276 0 : struct drm_device *dev = encoder->dev;
2277 0 : struct radeon_device *rdev = dev->dev_private;
2278 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2279 0 : struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2280 : int encoder_mode;
2281 :
2282 0 : radeon_encoder->pixel_clock = adjusted_mode->clock;
2283 :
2284 : /* need to call this here rather than in prepare() since we need some crtc info */
2285 0 : radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2286 :
2287 0 : if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2288 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2289 0 : atombios_yuv_setup(encoder, true);
2290 : else
2291 0 : atombios_yuv_setup(encoder, false);
2292 : }
2293 :
2294 0 : switch (radeon_encoder->encoder_id) {
2295 : case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2296 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2297 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2298 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2299 0 : atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2300 0 : break;
2301 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2302 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2303 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2304 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2305 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2306 : /* handled in dpms */
2307 : break;
2308 : case ENCODER_OBJECT_ID_INTERNAL_DDI:
2309 : case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2310 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2311 0 : atombios_dvo_setup(encoder, ATOM_ENABLE);
2312 0 : break;
2313 : case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2314 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2315 : case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2316 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2317 0 : atombios_dac_setup(encoder, ATOM_ENABLE);
2318 0 : if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2319 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2320 0 : atombios_tv_setup(encoder, ATOM_ENABLE);
2321 : else
2322 0 : atombios_tv_setup(encoder, ATOM_DISABLE);
2323 : }
2324 : break;
2325 : }
2326 :
2327 0 : atombios_apply_encoder_quirks(encoder, adjusted_mode);
2328 :
2329 0 : encoder_mode = atombios_get_encoder_mode(encoder);
2330 0 : if (connector && (radeon_audio != 0) &&
2331 0 : ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2332 0 : ENCODER_MODE_IS_DP(encoder_mode)))
2333 0 : radeon_audio_mode_set(encoder, adjusted_mode);
2334 0 : }
2335 :
2336 : static bool
2337 0 : atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2338 : {
2339 0 : struct drm_device *dev = encoder->dev;
2340 0 : struct radeon_device *rdev = dev->dev_private;
2341 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2342 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2343 :
2344 0 : if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2345 : ATOM_DEVICE_CV_SUPPORT |
2346 : ATOM_DEVICE_CRT_SUPPORT)) {
2347 0 : DAC_LOAD_DETECTION_PS_ALLOCATION args;
2348 : int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2349 0 : uint8_t frev, crev;
2350 :
2351 0 : memset(&args, 0, sizeof(args));
2352 :
2353 0 : if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2354 0 : return false;
2355 :
2356 0 : args.sDacload.ucMisc = 0;
2357 :
2358 0 : if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2359 0 : (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2360 0 : args.sDacload.ucDacType = ATOM_DAC_A;
2361 : else
2362 0 : args.sDacload.ucDacType = ATOM_DAC_B;
2363 :
2364 0 : if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2365 0 : args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2366 0 : else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2367 0 : args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2368 0 : else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2369 0 : args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2370 0 : if (crev >= 3)
2371 0 : args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2372 0 : } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2373 0 : args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2374 0 : if (crev >= 3)
2375 0 : args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2376 : }
2377 :
2378 0 : atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2379 :
2380 0 : return true;
2381 0 : } else
2382 0 : return false;
2383 0 : }
2384 :
2385 : static enum drm_connector_status
2386 0 : radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2387 : {
2388 0 : struct drm_device *dev = encoder->dev;
2389 0 : struct radeon_device *rdev = dev->dev_private;
2390 : #ifdef DRMDEBUG
2391 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2392 : #endif
2393 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2394 : uint32_t bios_0_scratch;
2395 :
2396 0 : if (!atombios_dac_load_detect(encoder, connector)) {
2397 : DRM_DEBUG_KMS("detect returned false \n");
2398 0 : return connector_status_unknown;
2399 : }
2400 :
2401 0 : if (rdev->family >= CHIP_R600)
2402 0 : bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2403 : else
2404 0 : bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2405 :
2406 : DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2407 0 : if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2408 0 : if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2409 0 : return connector_status_connected;
2410 : }
2411 0 : if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2412 0 : if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2413 0 : return connector_status_connected;
2414 : }
2415 0 : if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2416 0 : if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2417 0 : return connector_status_connected;
2418 : }
2419 0 : if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2420 0 : if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2421 0 : return connector_status_connected; /* CTV */
2422 0 : else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2423 0 : return connector_status_connected; /* STV */
2424 : }
2425 0 : return connector_status_disconnected;
2426 0 : }
2427 :
2428 : static enum drm_connector_status
2429 0 : radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2430 : {
2431 0 : struct drm_device *dev = encoder->dev;
2432 0 : struct radeon_device *rdev = dev->dev_private;
2433 : #ifdef DRMDEBUG
2434 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2435 : #endif
2436 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2437 0 : struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2438 : u32 bios_0_scratch;
2439 :
2440 0 : if (!ASIC_IS_DCE4(rdev))
2441 0 : return connector_status_unknown;
2442 :
2443 0 : if (!ext_encoder)
2444 0 : return connector_status_unknown;
2445 :
2446 0 : if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2447 0 : return connector_status_unknown;
2448 :
2449 : /* load detect on the dp bridge */
2450 0 : atombios_external_encoder_setup(encoder, ext_encoder,
2451 : EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2452 :
2453 0 : bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2454 :
2455 : DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2456 0 : if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2457 0 : if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2458 0 : return connector_status_connected;
2459 : }
2460 0 : if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2461 0 : if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2462 0 : return connector_status_connected;
2463 : }
2464 0 : if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2465 0 : if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2466 0 : return connector_status_connected;
2467 : }
2468 0 : if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2469 0 : if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2470 0 : return connector_status_connected; /* CTV */
2471 0 : else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2472 0 : return connector_status_connected; /* STV */
2473 : }
2474 0 : return connector_status_disconnected;
2475 0 : }
2476 :
2477 : void
2478 0 : radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2479 : {
2480 0 : struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2481 :
2482 0 : if (ext_encoder)
2483 : /* ddc_setup on the dp bridge */
2484 0 : atombios_external_encoder_setup(encoder, ext_encoder,
2485 : EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2486 :
2487 0 : }
2488 :
2489 0 : static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2490 : {
2491 0 : struct radeon_device *rdev = encoder->dev->dev_private;
2492 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2493 0 : struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2494 :
2495 0 : if ((radeon_encoder->active_device &
2496 0 : (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2497 0 : (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2498 : ENCODER_OBJECT_ID_NONE)) {
2499 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2500 0 : if (dig) {
2501 0 : if (dig->dig_encoder >= 0)
2502 0 : radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2503 0 : dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2504 0 : if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2505 0 : if (rdev->family >= CHIP_R600)
2506 0 : dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2507 : else
2508 : /* RS600/690/740 have only 1 afmt block */
2509 0 : dig->afmt = rdev->mode_info.afmt[0];
2510 : }
2511 : }
2512 0 : }
2513 :
2514 0 : radeon_atom_output_lock(encoder, true);
2515 :
2516 0 : if (connector) {
2517 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2518 :
2519 : /* select the clock/data port if it uses a router */
2520 0 : if (radeon_connector->router.cd_valid)
2521 0 : radeon_router_select_cd_port(radeon_connector);
2522 :
2523 : /* turn eDP panel on for mode set */
2524 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2525 0 : atombios_set_edp_panel_power(connector,
2526 : ATOM_TRANSMITTER_ACTION_POWER_ON);
2527 0 : }
2528 :
2529 : /* this is needed for the pll/ss setup to work correctly in some cases */
2530 0 : atombios_set_encoder_crtc_source(encoder);
2531 : /* set up the FMT blocks */
2532 0 : if (ASIC_IS_DCE8(rdev))
2533 0 : dce8_program_fmt(encoder);
2534 0 : else if (ASIC_IS_DCE4(rdev))
2535 0 : dce4_program_fmt(encoder);
2536 0 : else if (ASIC_IS_DCE3(rdev))
2537 0 : dce3_program_fmt(encoder);
2538 0 : else if (ASIC_IS_AVIVO(rdev))
2539 0 : avivo_program_fmt(encoder);
2540 0 : }
2541 :
2542 0 : static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2543 : {
2544 : /* need to call this here as we need the crtc set up */
2545 0 : radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2546 0 : radeon_atom_output_lock(encoder, false);
2547 0 : }
2548 :
2549 0 : static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2550 : {
2551 0 : struct drm_device *dev = encoder->dev;
2552 0 : struct radeon_device *rdev = dev->dev_private;
2553 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2554 : struct radeon_encoder_atom_dig *dig;
2555 :
2556 : /* check for pre-DCE3 cards with shared encoders;
2557 : * can't really use the links individually, so don't disable
2558 : * the encoder if it's in use by another connector
2559 : */
2560 0 : if (!ASIC_IS_DCE3(rdev)) {
2561 : struct drm_encoder *other_encoder;
2562 : struct radeon_encoder *other_radeon_encoder;
2563 :
2564 0 : list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2565 0 : other_radeon_encoder = to_radeon_encoder(other_encoder);
2566 0 : if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2567 0 : drm_helper_encoder_in_use(other_encoder))
2568 0 : goto disable_done;
2569 : }
2570 0 : }
2571 :
2572 0 : radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2573 :
2574 0 : switch (radeon_encoder->encoder_id) {
2575 : case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2576 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2577 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2578 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2579 0 : atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2580 0 : break;
2581 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2582 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2583 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2584 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2585 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2586 : /* handled in dpms */
2587 : break;
2588 : case ENCODER_OBJECT_ID_INTERNAL_DDI:
2589 : case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2590 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2591 0 : atombios_dvo_setup(encoder, ATOM_DISABLE);
2592 0 : break;
2593 : case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2594 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2595 : case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2596 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2597 0 : atombios_dac_setup(encoder, ATOM_DISABLE);
2598 0 : if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2599 0 : atombios_tv_setup(encoder, ATOM_DISABLE);
2600 : break;
2601 : }
2602 :
2603 : disable_done:
2604 0 : if (radeon_encoder_is_digital(encoder)) {
2605 0 : if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2606 0 : if (rdev->asic->display.hdmi_enable)
2607 0 : radeon_hdmi_enable(rdev, encoder, false);
2608 : }
2609 0 : if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2610 0 : dig = radeon_encoder->enc_priv;
2611 0 : radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2612 0 : dig->dig_encoder = -1;
2613 0 : radeon_encoder->active_device = 0;
2614 0 : }
2615 : } else
2616 0 : radeon_encoder->active_device = 0;
2617 0 : }
2618 :
2619 : /* these are handled by the primary encoders */
2620 0 : static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2621 : {
2622 :
2623 0 : }
2624 :
2625 0 : static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2626 : {
2627 :
2628 0 : }
2629 :
2630 : static void
2631 0 : radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2632 : struct drm_display_mode *mode,
2633 : struct drm_display_mode *adjusted_mode)
2634 : {
2635 :
2636 0 : }
2637 :
2638 0 : static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2639 : {
2640 :
2641 0 : }
2642 :
2643 : static void
2644 0 : radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2645 : {
2646 :
2647 0 : }
2648 :
2649 0 : static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2650 : const struct drm_display_mode *mode,
2651 : struct drm_display_mode *adjusted_mode)
2652 : {
2653 0 : return true;
2654 : }
2655 :
2656 : static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2657 : .dpms = radeon_atom_ext_dpms,
2658 : .mode_fixup = radeon_atom_ext_mode_fixup,
2659 : .prepare = radeon_atom_ext_prepare,
2660 : .mode_set = radeon_atom_ext_mode_set,
2661 : .commit = radeon_atom_ext_commit,
2662 : .disable = radeon_atom_ext_disable,
2663 : /* no detect for TMDS/LVDS yet */
2664 : };
2665 :
2666 : static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2667 : .dpms = radeon_atom_encoder_dpms,
2668 : .mode_fixup = radeon_atom_mode_fixup,
2669 : .prepare = radeon_atom_encoder_prepare,
2670 : .mode_set = radeon_atom_encoder_mode_set,
2671 : .commit = radeon_atom_encoder_commit,
2672 : .disable = radeon_atom_encoder_disable,
2673 : .detect = radeon_atom_dig_detect,
2674 : };
2675 :
2676 : static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2677 : .dpms = radeon_atom_encoder_dpms,
2678 : .mode_fixup = radeon_atom_mode_fixup,
2679 : .prepare = radeon_atom_encoder_prepare,
2680 : .mode_set = radeon_atom_encoder_mode_set,
2681 : .commit = radeon_atom_encoder_commit,
2682 : .detect = radeon_atom_dac_detect,
2683 : };
2684 :
2685 0 : void radeon_enc_destroy(struct drm_encoder *encoder)
2686 : {
2687 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2688 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2689 0 : radeon_atom_backlight_exit(radeon_encoder);
2690 0 : kfree(radeon_encoder->enc_priv);
2691 0 : drm_encoder_cleanup(encoder);
2692 0 : kfree(radeon_encoder);
2693 0 : }
2694 :
2695 : static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2696 : .destroy = radeon_enc_destroy,
2697 : };
2698 :
2699 : static struct radeon_encoder_atom_dac *
2700 0 : radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2701 : {
2702 0 : struct drm_device *dev = radeon_encoder->base.dev;
2703 0 : struct radeon_device *rdev = dev->dev_private;
2704 0 : struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2705 :
2706 0 : if (!dac)
2707 0 : return NULL;
2708 :
2709 0 : dac->tv_std = radeon_atombios_get_tv_info(rdev);
2710 0 : return dac;
2711 0 : }
2712 :
2713 : static struct radeon_encoder_atom_dig *
2714 0 : radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2715 : {
2716 0 : int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2717 0 : struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2718 :
2719 0 : if (!dig)
2720 0 : return NULL;
2721 :
2722 : /* coherent mode by default */
2723 0 : dig->coherent_mode = true;
2724 0 : dig->dig_encoder = -1;
2725 :
2726 0 : if (encoder_enum == 2)
2727 0 : dig->linkb = true;
2728 : else
2729 0 : dig->linkb = false;
2730 :
2731 0 : return dig;
2732 0 : }
2733 :
2734 : void
2735 0 : radeon_add_atom_encoder(struct drm_device *dev,
2736 : uint32_t encoder_enum,
2737 : uint32_t supported_device,
2738 : u16 caps)
2739 : {
2740 0 : struct radeon_device *rdev = dev->dev_private;
2741 : struct drm_encoder *encoder;
2742 : struct radeon_encoder *radeon_encoder;
2743 :
2744 : /* see if we already added it */
2745 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2746 0 : radeon_encoder = to_radeon_encoder(encoder);
2747 0 : if (radeon_encoder->encoder_enum == encoder_enum) {
2748 0 : radeon_encoder->devices |= supported_device;
2749 0 : return;
2750 : }
2751 :
2752 : }
2753 :
2754 : /* add a new one */
2755 0 : radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2756 0 : if (!radeon_encoder)
2757 0 : return;
2758 :
2759 0 : encoder = &radeon_encoder->base;
2760 0 : switch (rdev->num_crtc) {
2761 : case 1:
2762 0 : encoder->possible_crtcs = 0x1;
2763 0 : break;
2764 : case 2:
2765 : default:
2766 0 : encoder->possible_crtcs = 0x3;
2767 0 : break;
2768 : case 4:
2769 0 : encoder->possible_crtcs = 0xf;
2770 0 : break;
2771 : case 6:
2772 0 : encoder->possible_crtcs = 0x3f;
2773 0 : break;
2774 : }
2775 :
2776 0 : radeon_encoder->enc_priv = NULL;
2777 :
2778 0 : radeon_encoder->encoder_enum = encoder_enum;
2779 0 : radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2780 0 : radeon_encoder->devices = supported_device;
2781 0 : radeon_encoder->rmx_type = RMX_OFF;
2782 0 : radeon_encoder->underscan_type = UNDERSCAN_OFF;
2783 0 : radeon_encoder->is_ext_encoder = false;
2784 0 : radeon_encoder->caps = caps;
2785 :
2786 0 : switch (radeon_encoder->encoder_id) {
2787 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2788 : case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2789 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2790 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2791 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2792 0 : radeon_encoder->rmx_type = RMX_FULL;
2793 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2794 0 : radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2795 0 : } else {
2796 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2797 0 : radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2798 : }
2799 0 : drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2800 0 : break;
2801 : case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2802 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2803 0 : radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2804 0 : drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2805 0 : break;
2806 : case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2807 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2808 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2809 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2810 0 : radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2811 0 : drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2812 0 : break;
2813 : case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2814 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2815 : case ENCODER_OBJECT_ID_INTERNAL_DDI:
2816 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2817 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2818 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2819 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2820 : case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2821 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2822 0 : radeon_encoder->rmx_type = RMX_FULL;
2823 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2824 0 : radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2825 0 : } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2826 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2827 0 : radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2828 0 : } else {
2829 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2830 0 : radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2831 : }
2832 0 : drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2833 0 : break;
2834 : case ENCODER_OBJECT_ID_SI170B:
2835 : case ENCODER_OBJECT_ID_CH7303:
2836 : case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2837 : case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2838 : case ENCODER_OBJECT_ID_TITFP513:
2839 : case ENCODER_OBJECT_ID_VT1623:
2840 : case ENCODER_OBJECT_ID_HDMI_SI1930:
2841 : case ENCODER_OBJECT_ID_TRAVIS:
2842 : case ENCODER_OBJECT_ID_NUTMEG:
2843 : /* these are handled by the primary encoders */
2844 0 : radeon_encoder->is_ext_encoder = true;
2845 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2846 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2847 0 : else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2848 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2849 : else
2850 0 : drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2851 0 : drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2852 0 : break;
2853 : }
2854 0 : }
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