Line data Source code
1 : /*
2 : * Copyright 2011 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: Alex Deucher
23 : */
24 :
25 : #include <dev/pci/drm/drmP.h>
26 : #include "radeon.h"
27 : #include "radeon_asic.h"
28 : #include "btcd.h"
29 : #include "r600_dpm.h"
30 : #include "cypress_dpm.h"
31 : #include "btc_dpm.h"
32 : #include "atom.h"
33 :
34 : #define MC_CG_ARB_FREQ_F0 0x0a
35 : #define MC_CG_ARB_FREQ_F1 0x0b
36 : #define MC_CG_ARB_FREQ_F2 0x0c
37 : #define MC_CG_ARB_FREQ_F3 0x0d
38 :
39 : #define MC_CG_SEQ_DRAMCONF_S0 0x05
40 : #define MC_CG_SEQ_DRAMCONF_S1 0x06
41 : #define MC_CG_SEQ_YCLK_SUSPEND 0x04
42 : #define MC_CG_SEQ_YCLK_RESUME 0x0a
43 :
44 : #define SMC_RAM_END 0x8000
45 :
46 : #ifndef BTC_MGCG_SEQUENCE
47 : #define BTC_MGCG_SEQUENCE 300
48 :
49 : struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
50 : struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
51 : struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
52 :
53 : extern int ni_mc_load_microcode(struct radeon_device *rdev);
54 :
55 : //********* BARTS **************//
56 : static const u32 barts_cgcg_cgls_default[] =
57 : {
58 : /* Register, Value, Mask bits */
59 : 0x000008f8, 0x00000010, 0xffffffff,
60 : 0x000008fc, 0x00000000, 0xffffffff,
61 : 0x000008f8, 0x00000011, 0xffffffff,
62 : 0x000008fc, 0x00000000, 0xffffffff,
63 : 0x000008f8, 0x00000012, 0xffffffff,
64 : 0x000008fc, 0x00000000, 0xffffffff,
65 : 0x000008f8, 0x00000013, 0xffffffff,
66 : 0x000008fc, 0x00000000, 0xffffffff,
67 : 0x000008f8, 0x00000014, 0xffffffff,
68 : 0x000008fc, 0x00000000, 0xffffffff,
69 : 0x000008f8, 0x00000015, 0xffffffff,
70 : 0x000008fc, 0x00000000, 0xffffffff,
71 : 0x000008f8, 0x00000016, 0xffffffff,
72 : 0x000008fc, 0x00000000, 0xffffffff,
73 : 0x000008f8, 0x00000017, 0xffffffff,
74 : 0x000008fc, 0x00000000, 0xffffffff,
75 : 0x000008f8, 0x00000018, 0xffffffff,
76 : 0x000008fc, 0x00000000, 0xffffffff,
77 : 0x000008f8, 0x00000019, 0xffffffff,
78 : 0x000008fc, 0x00000000, 0xffffffff,
79 : 0x000008f8, 0x0000001a, 0xffffffff,
80 : 0x000008fc, 0x00000000, 0xffffffff,
81 : 0x000008f8, 0x0000001b, 0xffffffff,
82 : 0x000008fc, 0x00000000, 0xffffffff,
83 : 0x000008f8, 0x00000020, 0xffffffff,
84 : 0x000008fc, 0x00000000, 0xffffffff,
85 : 0x000008f8, 0x00000021, 0xffffffff,
86 : 0x000008fc, 0x00000000, 0xffffffff,
87 : 0x000008f8, 0x00000022, 0xffffffff,
88 : 0x000008fc, 0x00000000, 0xffffffff,
89 : 0x000008f8, 0x00000023, 0xffffffff,
90 : 0x000008fc, 0x00000000, 0xffffffff,
91 : 0x000008f8, 0x00000024, 0xffffffff,
92 : 0x000008fc, 0x00000000, 0xffffffff,
93 : 0x000008f8, 0x00000025, 0xffffffff,
94 : 0x000008fc, 0x00000000, 0xffffffff,
95 : 0x000008f8, 0x00000026, 0xffffffff,
96 : 0x000008fc, 0x00000000, 0xffffffff,
97 : 0x000008f8, 0x00000027, 0xffffffff,
98 : 0x000008fc, 0x00000000, 0xffffffff,
99 : 0x000008f8, 0x00000028, 0xffffffff,
100 : 0x000008fc, 0x00000000, 0xffffffff,
101 : 0x000008f8, 0x00000029, 0xffffffff,
102 : 0x000008fc, 0x00000000, 0xffffffff,
103 : 0x000008f8, 0x0000002a, 0xffffffff,
104 : 0x000008fc, 0x00000000, 0xffffffff,
105 : 0x000008f8, 0x0000002b, 0xffffffff,
106 : 0x000008fc, 0x00000000, 0xffffffff
107 : };
108 : #define BARTS_CGCG_CGLS_DEFAULT_LENGTH sizeof(barts_cgcg_cgls_default) / (3 * sizeof(u32))
109 :
110 : static const u32 barts_cgcg_cgls_disable[] =
111 : {
112 : 0x000008f8, 0x00000010, 0xffffffff,
113 : 0x000008fc, 0xffffffff, 0xffffffff,
114 : 0x000008f8, 0x00000011, 0xffffffff,
115 : 0x000008fc, 0xffffffff, 0xffffffff,
116 : 0x000008f8, 0x00000012, 0xffffffff,
117 : 0x000008fc, 0xffffffff, 0xffffffff,
118 : 0x000008f8, 0x00000013, 0xffffffff,
119 : 0x000008fc, 0xffffffff, 0xffffffff,
120 : 0x000008f8, 0x00000014, 0xffffffff,
121 : 0x000008fc, 0xffffffff, 0xffffffff,
122 : 0x000008f8, 0x00000015, 0xffffffff,
123 : 0x000008fc, 0xffffffff, 0xffffffff,
124 : 0x000008f8, 0x00000016, 0xffffffff,
125 : 0x000008fc, 0xffffffff, 0xffffffff,
126 : 0x000008f8, 0x00000017, 0xffffffff,
127 : 0x000008fc, 0xffffffff, 0xffffffff,
128 : 0x000008f8, 0x00000018, 0xffffffff,
129 : 0x000008fc, 0xffffffff, 0xffffffff,
130 : 0x000008f8, 0x00000019, 0xffffffff,
131 : 0x000008fc, 0xffffffff, 0xffffffff,
132 : 0x000008f8, 0x0000001a, 0xffffffff,
133 : 0x000008fc, 0xffffffff, 0xffffffff,
134 : 0x000008f8, 0x0000001b, 0xffffffff,
135 : 0x000008fc, 0xffffffff, 0xffffffff,
136 : 0x000008f8, 0x00000020, 0xffffffff,
137 : 0x000008fc, 0x00000000, 0xffffffff,
138 : 0x000008f8, 0x00000021, 0xffffffff,
139 : 0x000008fc, 0x00000000, 0xffffffff,
140 : 0x000008f8, 0x00000022, 0xffffffff,
141 : 0x000008fc, 0x00000000, 0xffffffff,
142 : 0x000008f8, 0x00000023, 0xffffffff,
143 : 0x000008fc, 0x00000000, 0xffffffff,
144 : 0x000008f8, 0x00000024, 0xffffffff,
145 : 0x000008fc, 0x00000000, 0xffffffff,
146 : 0x000008f8, 0x00000025, 0xffffffff,
147 : 0x000008fc, 0x00000000, 0xffffffff,
148 : 0x000008f8, 0x00000026, 0xffffffff,
149 : 0x000008fc, 0x00000000, 0xffffffff,
150 : 0x000008f8, 0x00000027, 0xffffffff,
151 : 0x000008fc, 0x00000000, 0xffffffff,
152 : 0x000008f8, 0x00000028, 0xffffffff,
153 : 0x000008fc, 0x00000000, 0xffffffff,
154 : 0x000008f8, 0x00000029, 0xffffffff,
155 : 0x000008fc, 0x00000000, 0xffffffff,
156 : 0x000008f8, 0x0000002a, 0xffffffff,
157 : 0x000008fc, 0x00000000, 0xffffffff,
158 : 0x000008f8, 0x0000002b, 0xffffffff,
159 : 0x000008fc, 0x00000000, 0xffffffff,
160 : 0x00000644, 0x000f7912, 0x001f4180,
161 : 0x00000644, 0x000f3812, 0x001f4180
162 : };
163 : #define BARTS_CGCG_CGLS_DISABLE_LENGTH sizeof(barts_cgcg_cgls_disable) / (3 * sizeof(u32))
164 :
165 : static const u32 barts_cgcg_cgls_enable[] =
166 : {
167 : /* 0x0000c124, 0x84180000, 0x00180000, */
168 : 0x00000644, 0x000f7892, 0x001f4080,
169 : 0x000008f8, 0x00000010, 0xffffffff,
170 : 0x000008fc, 0x00000000, 0xffffffff,
171 : 0x000008f8, 0x00000011, 0xffffffff,
172 : 0x000008fc, 0x00000000, 0xffffffff,
173 : 0x000008f8, 0x00000012, 0xffffffff,
174 : 0x000008fc, 0x00000000, 0xffffffff,
175 : 0x000008f8, 0x00000013, 0xffffffff,
176 : 0x000008fc, 0x00000000, 0xffffffff,
177 : 0x000008f8, 0x00000014, 0xffffffff,
178 : 0x000008fc, 0x00000000, 0xffffffff,
179 : 0x000008f8, 0x00000015, 0xffffffff,
180 : 0x000008fc, 0x00000000, 0xffffffff,
181 : 0x000008f8, 0x00000016, 0xffffffff,
182 : 0x000008fc, 0x00000000, 0xffffffff,
183 : 0x000008f8, 0x00000017, 0xffffffff,
184 : 0x000008fc, 0x00000000, 0xffffffff,
185 : 0x000008f8, 0x00000018, 0xffffffff,
186 : 0x000008fc, 0x00000000, 0xffffffff,
187 : 0x000008f8, 0x00000019, 0xffffffff,
188 : 0x000008fc, 0x00000000, 0xffffffff,
189 : 0x000008f8, 0x0000001a, 0xffffffff,
190 : 0x000008fc, 0x00000000, 0xffffffff,
191 : 0x000008f8, 0x0000001b, 0xffffffff,
192 : 0x000008fc, 0x00000000, 0xffffffff,
193 : 0x000008f8, 0x00000020, 0xffffffff,
194 : 0x000008fc, 0xffffffff, 0xffffffff,
195 : 0x000008f8, 0x00000021, 0xffffffff,
196 : 0x000008fc, 0xffffffff, 0xffffffff,
197 : 0x000008f8, 0x00000022, 0xffffffff,
198 : 0x000008fc, 0xffffffff, 0xffffffff,
199 : 0x000008f8, 0x00000023, 0xffffffff,
200 : 0x000008fc, 0xffffffff, 0xffffffff,
201 : 0x000008f8, 0x00000024, 0xffffffff,
202 : 0x000008fc, 0xffffffff, 0xffffffff,
203 : 0x000008f8, 0x00000025, 0xffffffff,
204 : 0x000008fc, 0xffffffff, 0xffffffff,
205 : 0x000008f8, 0x00000026, 0xffffffff,
206 : 0x000008fc, 0xffffffff, 0xffffffff,
207 : 0x000008f8, 0x00000027, 0xffffffff,
208 : 0x000008fc, 0xffffffff, 0xffffffff,
209 : 0x000008f8, 0x00000028, 0xffffffff,
210 : 0x000008fc, 0xffffffff, 0xffffffff,
211 : 0x000008f8, 0x00000029, 0xffffffff,
212 : 0x000008fc, 0xffffffff, 0xffffffff,
213 : 0x000008f8, 0x0000002a, 0xffffffff,
214 : 0x000008fc, 0xffffffff, 0xffffffff,
215 : 0x000008f8, 0x0000002b, 0xffffffff,
216 : 0x000008fc, 0xffffffff, 0xffffffff
217 : };
218 : #define BARTS_CGCG_CGLS_ENABLE_LENGTH sizeof(barts_cgcg_cgls_enable) / (3 * sizeof(u32))
219 :
220 : static const u32 barts_mgcg_default[] =
221 : {
222 : 0x0000802c, 0xc0000000, 0xffffffff,
223 : 0x00005448, 0x00000100, 0xffffffff,
224 : 0x000055e4, 0x00600100, 0xffffffff,
225 : 0x0000160c, 0x00000100, 0xffffffff,
226 : 0x0000c164, 0x00000100, 0xffffffff,
227 : 0x00008a18, 0x00000100, 0xffffffff,
228 : 0x0000897c, 0x06000100, 0xffffffff,
229 : 0x00008b28, 0x00000100, 0xffffffff,
230 : 0x00009144, 0x00000100, 0xffffffff,
231 : 0x00009a60, 0x00000100, 0xffffffff,
232 : 0x00009868, 0x00000100, 0xffffffff,
233 : 0x00008d58, 0x00000100, 0xffffffff,
234 : 0x00009510, 0x00000100, 0xffffffff,
235 : 0x0000949c, 0x00000100, 0xffffffff,
236 : 0x00009654, 0x00000100, 0xffffffff,
237 : 0x00009030, 0x00000100, 0xffffffff,
238 : 0x00009034, 0x00000100, 0xffffffff,
239 : 0x00009038, 0x00000100, 0xffffffff,
240 : 0x0000903c, 0x00000100, 0xffffffff,
241 : 0x00009040, 0x00000100, 0xffffffff,
242 : 0x0000a200, 0x00000100, 0xffffffff,
243 : 0x0000a204, 0x00000100, 0xffffffff,
244 : 0x0000a208, 0x00000100, 0xffffffff,
245 : 0x0000a20c, 0x00000100, 0xffffffff,
246 : 0x0000977c, 0x00000100, 0xffffffff,
247 : 0x00003f80, 0x00000100, 0xffffffff,
248 : 0x0000a210, 0x00000100, 0xffffffff,
249 : 0x0000a214, 0x00000100, 0xffffffff,
250 : 0x000004d8, 0x00000100, 0xffffffff,
251 : 0x00009784, 0x00000100, 0xffffffff,
252 : 0x00009698, 0x00000100, 0xffffffff,
253 : 0x000004d4, 0x00000200, 0xffffffff,
254 : 0x000004d0, 0x00000000, 0xffffffff,
255 : 0x000030cc, 0x00000100, 0xffffffff,
256 : 0x0000d0c0, 0xff000100, 0xffffffff,
257 : 0x0000802c, 0x40000000, 0xffffffff,
258 : 0x0000915c, 0x00010000, 0xffffffff,
259 : 0x00009160, 0x00030002, 0xffffffff,
260 : 0x00009164, 0x00050004, 0xffffffff,
261 : 0x00009168, 0x00070006, 0xffffffff,
262 : 0x00009178, 0x00070000, 0xffffffff,
263 : 0x0000917c, 0x00030002, 0xffffffff,
264 : 0x00009180, 0x00050004, 0xffffffff,
265 : 0x0000918c, 0x00010006, 0xffffffff,
266 : 0x00009190, 0x00090008, 0xffffffff,
267 : 0x00009194, 0x00070000, 0xffffffff,
268 : 0x00009198, 0x00030002, 0xffffffff,
269 : 0x0000919c, 0x00050004, 0xffffffff,
270 : 0x000091a8, 0x00010006, 0xffffffff,
271 : 0x000091ac, 0x00090008, 0xffffffff,
272 : 0x000091b0, 0x00070000, 0xffffffff,
273 : 0x000091b4, 0x00030002, 0xffffffff,
274 : 0x000091b8, 0x00050004, 0xffffffff,
275 : 0x000091c4, 0x00010006, 0xffffffff,
276 : 0x000091c8, 0x00090008, 0xffffffff,
277 : 0x000091cc, 0x00070000, 0xffffffff,
278 : 0x000091d0, 0x00030002, 0xffffffff,
279 : 0x000091d4, 0x00050004, 0xffffffff,
280 : 0x000091e0, 0x00010006, 0xffffffff,
281 : 0x000091e4, 0x00090008, 0xffffffff,
282 : 0x000091e8, 0x00000000, 0xffffffff,
283 : 0x000091ec, 0x00070000, 0xffffffff,
284 : 0x000091f0, 0x00030002, 0xffffffff,
285 : 0x000091f4, 0x00050004, 0xffffffff,
286 : 0x00009200, 0x00010006, 0xffffffff,
287 : 0x00009204, 0x00090008, 0xffffffff,
288 : 0x00009208, 0x00070000, 0xffffffff,
289 : 0x0000920c, 0x00030002, 0xffffffff,
290 : 0x00009210, 0x00050004, 0xffffffff,
291 : 0x0000921c, 0x00010006, 0xffffffff,
292 : 0x00009220, 0x00090008, 0xffffffff,
293 : 0x00009224, 0x00070000, 0xffffffff,
294 : 0x00009228, 0x00030002, 0xffffffff,
295 : 0x0000922c, 0x00050004, 0xffffffff,
296 : 0x00009238, 0x00010006, 0xffffffff,
297 : 0x0000923c, 0x00090008, 0xffffffff,
298 : 0x00009294, 0x00000000, 0xffffffff,
299 : 0x0000802c, 0x40010000, 0xffffffff,
300 : 0x0000915c, 0x00010000, 0xffffffff,
301 : 0x00009160, 0x00030002, 0xffffffff,
302 : 0x00009164, 0x00050004, 0xffffffff,
303 : 0x00009168, 0x00070006, 0xffffffff,
304 : 0x00009178, 0x00070000, 0xffffffff,
305 : 0x0000917c, 0x00030002, 0xffffffff,
306 : 0x00009180, 0x00050004, 0xffffffff,
307 : 0x0000918c, 0x00010006, 0xffffffff,
308 : 0x00009190, 0x00090008, 0xffffffff,
309 : 0x00009194, 0x00070000, 0xffffffff,
310 : 0x00009198, 0x00030002, 0xffffffff,
311 : 0x0000919c, 0x00050004, 0xffffffff,
312 : 0x000091a8, 0x00010006, 0xffffffff,
313 : 0x000091ac, 0x00090008, 0xffffffff,
314 : 0x000091b0, 0x00070000, 0xffffffff,
315 : 0x000091b4, 0x00030002, 0xffffffff,
316 : 0x000091b8, 0x00050004, 0xffffffff,
317 : 0x000091c4, 0x00010006, 0xffffffff,
318 : 0x000091c8, 0x00090008, 0xffffffff,
319 : 0x000091cc, 0x00070000, 0xffffffff,
320 : 0x000091d0, 0x00030002, 0xffffffff,
321 : 0x000091d4, 0x00050004, 0xffffffff,
322 : 0x000091e0, 0x00010006, 0xffffffff,
323 : 0x000091e4, 0x00090008, 0xffffffff,
324 : 0x000091e8, 0x00000000, 0xffffffff,
325 : 0x000091ec, 0x00070000, 0xffffffff,
326 : 0x000091f0, 0x00030002, 0xffffffff,
327 : 0x000091f4, 0x00050004, 0xffffffff,
328 : 0x00009200, 0x00010006, 0xffffffff,
329 : 0x00009204, 0x00090008, 0xffffffff,
330 : 0x00009208, 0x00070000, 0xffffffff,
331 : 0x0000920c, 0x00030002, 0xffffffff,
332 : 0x00009210, 0x00050004, 0xffffffff,
333 : 0x0000921c, 0x00010006, 0xffffffff,
334 : 0x00009220, 0x00090008, 0xffffffff,
335 : 0x00009224, 0x00070000, 0xffffffff,
336 : 0x00009228, 0x00030002, 0xffffffff,
337 : 0x0000922c, 0x00050004, 0xffffffff,
338 : 0x00009238, 0x00010006, 0xffffffff,
339 : 0x0000923c, 0x00090008, 0xffffffff,
340 : 0x00009294, 0x00000000, 0xffffffff,
341 : 0x0000802c, 0xc0000000, 0xffffffff,
342 : 0x000008f8, 0x00000010, 0xffffffff,
343 : 0x000008fc, 0x00000000, 0xffffffff,
344 : 0x000008f8, 0x00000011, 0xffffffff,
345 : 0x000008fc, 0x00000000, 0xffffffff,
346 : 0x000008f8, 0x00000012, 0xffffffff,
347 : 0x000008fc, 0x00000000, 0xffffffff,
348 : 0x000008f8, 0x00000013, 0xffffffff,
349 : 0x000008fc, 0x00000000, 0xffffffff,
350 : 0x000008f8, 0x00000014, 0xffffffff,
351 : 0x000008fc, 0x00000000, 0xffffffff,
352 : 0x000008f8, 0x00000015, 0xffffffff,
353 : 0x000008fc, 0x00000000, 0xffffffff,
354 : 0x000008f8, 0x00000016, 0xffffffff,
355 : 0x000008fc, 0x00000000, 0xffffffff,
356 : 0x000008f8, 0x00000017, 0xffffffff,
357 : 0x000008fc, 0x00000000, 0xffffffff,
358 : 0x000008f8, 0x00000018, 0xffffffff,
359 : 0x000008fc, 0x00000000, 0xffffffff,
360 : 0x000008f8, 0x00000019, 0xffffffff,
361 : 0x000008fc, 0x00000000, 0xffffffff,
362 : 0x000008f8, 0x0000001a, 0xffffffff,
363 : 0x000008fc, 0x00000000, 0xffffffff,
364 : 0x000008f8, 0x0000001b, 0xffffffff,
365 : 0x000008fc, 0x00000000, 0xffffffff
366 : };
367 : #define BARTS_MGCG_DEFAULT_LENGTH sizeof(barts_mgcg_default) / (3 * sizeof(u32))
368 :
369 : static const u32 barts_mgcg_disable[] =
370 : {
371 : 0x0000802c, 0xc0000000, 0xffffffff,
372 : 0x000008f8, 0x00000000, 0xffffffff,
373 : 0x000008fc, 0xffffffff, 0xffffffff,
374 : 0x000008f8, 0x00000001, 0xffffffff,
375 : 0x000008fc, 0xffffffff, 0xffffffff,
376 : 0x000008f8, 0x00000002, 0xffffffff,
377 : 0x000008fc, 0xffffffff, 0xffffffff,
378 : 0x000008f8, 0x00000003, 0xffffffff,
379 : 0x000008fc, 0xffffffff, 0xffffffff,
380 : 0x00009150, 0x00600000, 0xffffffff
381 : };
382 : #define BARTS_MGCG_DISABLE_LENGTH sizeof(barts_mgcg_disable) / (3 * sizeof(u32))
383 :
384 : static const u32 barts_mgcg_enable[] =
385 : {
386 : 0x0000802c, 0xc0000000, 0xffffffff,
387 : 0x000008f8, 0x00000000, 0xffffffff,
388 : 0x000008fc, 0x00000000, 0xffffffff,
389 : 0x000008f8, 0x00000001, 0xffffffff,
390 : 0x000008fc, 0x00000000, 0xffffffff,
391 : 0x000008f8, 0x00000002, 0xffffffff,
392 : 0x000008fc, 0x00000000, 0xffffffff,
393 : 0x000008f8, 0x00000003, 0xffffffff,
394 : 0x000008fc, 0x00000000, 0xffffffff,
395 : 0x00009150, 0x81944000, 0xffffffff
396 : };
397 : #define BARTS_MGCG_ENABLE_LENGTH sizeof(barts_mgcg_enable) / (3 * sizeof(u32))
398 :
399 : //********* CAICOS **************//
400 : static const u32 caicos_cgcg_cgls_default[] =
401 : {
402 : 0x000008f8, 0x00000010, 0xffffffff,
403 : 0x000008fc, 0x00000000, 0xffffffff,
404 : 0x000008f8, 0x00000011, 0xffffffff,
405 : 0x000008fc, 0x00000000, 0xffffffff,
406 : 0x000008f8, 0x00000012, 0xffffffff,
407 : 0x000008fc, 0x00000000, 0xffffffff,
408 : 0x000008f8, 0x00000013, 0xffffffff,
409 : 0x000008fc, 0x00000000, 0xffffffff,
410 : 0x000008f8, 0x00000014, 0xffffffff,
411 : 0x000008fc, 0x00000000, 0xffffffff,
412 : 0x000008f8, 0x00000015, 0xffffffff,
413 : 0x000008fc, 0x00000000, 0xffffffff,
414 : 0x000008f8, 0x00000016, 0xffffffff,
415 : 0x000008fc, 0x00000000, 0xffffffff,
416 : 0x000008f8, 0x00000017, 0xffffffff,
417 : 0x000008fc, 0x00000000, 0xffffffff,
418 : 0x000008f8, 0x00000018, 0xffffffff,
419 : 0x000008fc, 0x00000000, 0xffffffff,
420 : 0x000008f8, 0x00000019, 0xffffffff,
421 : 0x000008fc, 0x00000000, 0xffffffff,
422 : 0x000008f8, 0x0000001a, 0xffffffff,
423 : 0x000008fc, 0x00000000, 0xffffffff,
424 : 0x000008f8, 0x0000001b, 0xffffffff,
425 : 0x000008fc, 0x00000000, 0xffffffff,
426 : 0x000008f8, 0x00000020, 0xffffffff,
427 : 0x000008fc, 0x00000000, 0xffffffff,
428 : 0x000008f8, 0x00000021, 0xffffffff,
429 : 0x000008fc, 0x00000000, 0xffffffff,
430 : 0x000008f8, 0x00000022, 0xffffffff,
431 : 0x000008fc, 0x00000000, 0xffffffff,
432 : 0x000008f8, 0x00000023, 0xffffffff,
433 : 0x000008fc, 0x00000000, 0xffffffff,
434 : 0x000008f8, 0x00000024, 0xffffffff,
435 : 0x000008fc, 0x00000000, 0xffffffff,
436 : 0x000008f8, 0x00000025, 0xffffffff,
437 : 0x000008fc, 0x00000000, 0xffffffff,
438 : 0x000008f8, 0x00000026, 0xffffffff,
439 : 0x000008fc, 0x00000000, 0xffffffff,
440 : 0x000008f8, 0x00000027, 0xffffffff,
441 : 0x000008fc, 0x00000000, 0xffffffff,
442 : 0x000008f8, 0x00000028, 0xffffffff,
443 : 0x000008fc, 0x00000000, 0xffffffff,
444 : 0x000008f8, 0x00000029, 0xffffffff,
445 : 0x000008fc, 0x00000000, 0xffffffff,
446 : 0x000008f8, 0x0000002a, 0xffffffff,
447 : 0x000008fc, 0x00000000, 0xffffffff,
448 : 0x000008f8, 0x0000002b, 0xffffffff,
449 : 0x000008fc, 0x00000000, 0xffffffff
450 : };
451 : #define CAICOS_CGCG_CGLS_DEFAULT_LENGTH sizeof(caicos_cgcg_cgls_default) / (3 * sizeof(u32))
452 :
453 : static const u32 caicos_cgcg_cgls_disable[] =
454 : {
455 : 0x000008f8, 0x00000010, 0xffffffff,
456 : 0x000008fc, 0xffffffff, 0xffffffff,
457 : 0x000008f8, 0x00000011, 0xffffffff,
458 : 0x000008fc, 0xffffffff, 0xffffffff,
459 : 0x000008f8, 0x00000012, 0xffffffff,
460 : 0x000008fc, 0xffffffff, 0xffffffff,
461 : 0x000008f8, 0x00000013, 0xffffffff,
462 : 0x000008fc, 0xffffffff, 0xffffffff,
463 : 0x000008f8, 0x00000014, 0xffffffff,
464 : 0x000008fc, 0xffffffff, 0xffffffff,
465 : 0x000008f8, 0x00000015, 0xffffffff,
466 : 0x000008fc, 0xffffffff, 0xffffffff,
467 : 0x000008f8, 0x00000016, 0xffffffff,
468 : 0x000008fc, 0xffffffff, 0xffffffff,
469 : 0x000008f8, 0x00000017, 0xffffffff,
470 : 0x000008fc, 0xffffffff, 0xffffffff,
471 : 0x000008f8, 0x00000018, 0xffffffff,
472 : 0x000008fc, 0xffffffff, 0xffffffff,
473 : 0x000008f8, 0x00000019, 0xffffffff,
474 : 0x000008fc, 0xffffffff, 0xffffffff,
475 : 0x000008f8, 0x0000001a, 0xffffffff,
476 : 0x000008fc, 0xffffffff, 0xffffffff,
477 : 0x000008f8, 0x0000001b, 0xffffffff,
478 : 0x000008fc, 0xffffffff, 0xffffffff,
479 : 0x000008f8, 0x00000020, 0xffffffff,
480 : 0x000008fc, 0x00000000, 0xffffffff,
481 : 0x000008f8, 0x00000021, 0xffffffff,
482 : 0x000008fc, 0x00000000, 0xffffffff,
483 : 0x000008f8, 0x00000022, 0xffffffff,
484 : 0x000008fc, 0x00000000, 0xffffffff,
485 : 0x000008f8, 0x00000023, 0xffffffff,
486 : 0x000008fc, 0x00000000, 0xffffffff,
487 : 0x000008f8, 0x00000024, 0xffffffff,
488 : 0x000008fc, 0x00000000, 0xffffffff,
489 : 0x000008f8, 0x00000025, 0xffffffff,
490 : 0x000008fc, 0x00000000, 0xffffffff,
491 : 0x000008f8, 0x00000026, 0xffffffff,
492 : 0x000008fc, 0x00000000, 0xffffffff,
493 : 0x000008f8, 0x00000027, 0xffffffff,
494 : 0x000008fc, 0x00000000, 0xffffffff,
495 : 0x000008f8, 0x00000028, 0xffffffff,
496 : 0x000008fc, 0x00000000, 0xffffffff,
497 : 0x000008f8, 0x00000029, 0xffffffff,
498 : 0x000008fc, 0x00000000, 0xffffffff,
499 : 0x000008f8, 0x0000002a, 0xffffffff,
500 : 0x000008fc, 0x00000000, 0xffffffff,
501 : 0x000008f8, 0x0000002b, 0xffffffff,
502 : 0x000008fc, 0x00000000, 0xffffffff,
503 : 0x00000644, 0x000f7912, 0x001f4180,
504 : 0x00000644, 0x000f3812, 0x001f4180
505 : };
506 : #define CAICOS_CGCG_CGLS_DISABLE_LENGTH sizeof(caicos_cgcg_cgls_disable) / (3 * sizeof(u32))
507 :
508 : static const u32 caicos_cgcg_cgls_enable[] =
509 : {
510 : /* 0x0000c124, 0x84180000, 0x00180000, */
511 : 0x00000644, 0x000f7892, 0x001f4080,
512 : 0x000008f8, 0x00000010, 0xffffffff,
513 : 0x000008fc, 0x00000000, 0xffffffff,
514 : 0x000008f8, 0x00000011, 0xffffffff,
515 : 0x000008fc, 0x00000000, 0xffffffff,
516 : 0x000008f8, 0x00000012, 0xffffffff,
517 : 0x000008fc, 0x00000000, 0xffffffff,
518 : 0x000008f8, 0x00000013, 0xffffffff,
519 : 0x000008fc, 0x00000000, 0xffffffff,
520 : 0x000008f8, 0x00000014, 0xffffffff,
521 : 0x000008fc, 0x00000000, 0xffffffff,
522 : 0x000008f8, 0x00000015, 0xffffffff,
523 : 0x000008fc, 0x00000000, 0xffffffff,
524 : 0x000008f8, 0x00000016, 0xffffffff,
525 : 0x000008fc, 0x00000000, 0xffffffff,
526 : 0x000008f8, 0x00000017, 0xffffffff,
527 : 0x000008fc, 0x00000000, 0xffffffff,
528 : 0x000008f8, 0x00000018, 0xffffffff,
529 : 0x000008fc, 0x00000000, 0xffffffff,
530 : 0x000008f8, 0x00000019, 0xffffffff,
531 : 0x000008fc, 0x00000000, 0xffffffff,
532 : 0x000008f8, 0x0000001a, 0xffffffff,
533 : 0x000008fc, 0x00000000, 0xffffffff,
534 : 0x000008f8, 0x0000001b, 0xffffffff,
535 : 0x000008fc, 0x00000000, 0xffffffff,
536 : 0x000008f8, 0x00000020, 0xffffffff,
537 : 0x000008fc, 0xffffffff, 0xffffffff,
538 : 0x000008f8, 0x00000021, 0xffffffff,
539 : 0x000008fc, 0xffffffff, 0xffffffff,
540 : 0x000008f8, 0x00000022, 0xffffffff,
541 : 0x000008fc, 0xffffffff, 0xffffffff,
542 : 0x000008f8, 0x00000023, 0xffffffff,
543 : 0x000008fc, 0xffffffff, 0xffffffff,
544 : 0x000008f8, 0x00000024, 0xffffffff,
545 : 0x000008fc, 0xffffffff, 0xffffffff,
546 : 0x000008f8, 0x00000025, 0xffffffff,
547 : 0x000008fc, 0xffffffff, 0xffffffff,
548 : 0x000008f8, 0x00000026, 0xffffffff,
549 : 0x000008fc, 0xffffffff, 0xffffffff,
550 : 0x000008f8, 0x00000027, 0xffffffff,
551 : 0x000008fc, 0xffffffff, 0xffffffff,
552 : 0x000008f8, 0x00000028, 0xffffffff,
553 : 0x000008fc, 0xffffffff, 0xffffffff,
554 : 0x000008f8, 0x00000029, 0xffffffff,
555 : 0x000008fc, 0xffffffff, 0xffffffff,
556 : 0x000008f8, 0x0000002a, 0xffffffff,
557 : 0x000008fc, 0xffffffff, 0xffffffff,
558 : 0x000008f8, 0x0000002b, 0xffffffff,
559 : 0x000008fc, 0xffffffff, 0xffffffff
560 : };
561 : #define CAICOS_CGCG_CGLS_ENABLE_LENGTH sizeof(caicos_cgcg_cgls_enable) / (3 * sizeof(u32))
562 :
563 : static const u32 caicos_mgcg_default[] =
564 : {
565 : 0x0000802c, 0xc0000000, 0xffffffff,
566 : 0x00005448, 0x00000100, 0xffffffff,
567 : 0x000055e4, 0x00600100, 0xffffffff,
568 : 0x0000160c, 0x00000100, 0xffffffff,
569 : 0x0000c164, 0x00000100, 0xffffffff,
570 : 0x00008a18, 0x00000100, 0xffffffff,
571 : 0x0000897c, 0x06000100, 0xffffffff,
572 : 0x00008b28, 0x00000100, 0xffffffff,
573 : 0x00009144, 0x00000100, 0xffffffff,
574 : 0x00009a60, 0x00000100, 0xffffffff,
575 : 0x00009868, 0x00000100, 0xffffffff,
576 : 0x00008d58, 0x00000100, 0xffffffff,
577 : 0x00009510, 0x00000100, 0xffffffff,
578 : 0x0000949c, 0x00000100, 0xffffffff,
579 : 0x00009654, 0x00000100, 0xffffffff,
580 : 0x00009030, 0x00000100, 0xffffffff,
581 : 0x00009034, 0x00000100, 0xffffffff,
582 : 0x00009038, 0x00000100, 0xffffffff,
583 : 0x0000903c, 0x00000100, 0xffffffff,
584 : 0x00009040, 0x00000100, 0xffffffff,
585 : 0x0000a200, 0x00000100, 0xffffffff,
586 : 0x0000a204, 0x00000100, 0xffffffff,
587 : 0x0000a208, 0x00000100, 0xffffffff,
588 : 0x0000a20c, 0x00000100, 0xffffffff,
589 : 0x0000977c, 0x00000100, 0xffffffff,
590 : 0x00003f80, 0x00000100, 0xffffffff,
591 : 0x0000a210, 0x00000100, 0xffffffff,
592 : 0x0000a214, 0x00000100, 0xffffffff,
593 : 0x000004d8, 0x00000100, 0xffffffff,
594 : 0x00009784, 0x00000100, 0xffffffff,
595 : 0x00009698, 0x00000100, 0xffffffff,
596 : 0x000004d4, 0x00000200, 0xffffffff,
597 : 0x000004d0, 0x00000000, 0xffffffff,
598 : 0x000030cc, 0x00000100, 0xffffffff,
599 : 0x0000d0c0, 0xff000100, 0xffffffff,
600 : 0x0000915c, 0x00010000, 0xffffffff,
601 : 0x00009160, 0x00030002, 0xffffffff,
602 : 0x00009164, 0x00050004, 0xffffffff,
603 : 0x00009168, 0x00070006, 0xffffffff,
604 : 0x00009178, 0x00070000, 0xffffffff,
605 : 0x0000917c, 0x00030002, 0xffffffff,
606 : 0x00009180, 0x00050004, 0xffffffff,
607 : 0x0000918c, 0x00010006, 0xffffffff,
608 : 0x00009190, 0x00090008, 0xffffffff,
609 : 0x00009194, 0x00070000, 0xffffffff,
610 : 0x00009198, 0x00030002, 0xffffffff,
611 : 0x0000919c, 0x00050004, 0xffffffff,
612 : 0x000091a8, 0x00010006, 0xffffffff,
613 : 0x000091ac, 0x00090008, 0xffffffff,
614 : 0x000091e8, 0x00000000, 0xffffffff,
615 : 0x00009294, 0x00000000, 0xffffffff,
616 : 0x000008f8, 0x00000010, 0xffffffff,
617 : 0x000008fc, 0x00000000, 0xffffffff,
618 : 0x000008f8, 0x00000011, 0xffffffff,
619 : 0x000008fc, 0x00000000, 0xffffffff,
620 : 0x000008f8, 0x00000012, 0xffffffff,
621 : 0x000008fc, 0x00000000, 0xffffffff,
622 : 0x000008f8, 0x00000013, 0xffffffff,
623 : 0x000008fc, 0x00000000, 0xffffffff,
624 : 0x000008f8, 0x00000014, 0xffffffff,
625 : 0x000008fc, 0x00000000, 0xffffffff,
626 : 0x000008f8, 0x00000015, 0xffffffff,
627 : 0x000008fc, 0x00000000, 0xffffffff,
628 : 0x000008f8, 0x00000016, 0xffffffff,
629 : 0x000008fc, 0x00000000, 0xffffffff,
630 : 0x000008f8, 0x00000017, 0xffffffff,
631 : 0x000008fc, 0x00000000, 0xffffffff,
632 : 0x000008f8, 0x00000018, 0xffffffff,
633 : 0x000008fc, 0x00000000, 0xffffffff,
634 : 0x000008f8, 0x00000019, 0xffffffff,
635 : 0x000008fc, 0x00000000, 0xffffffff,
636 : 0x000008f8, 0x0000001a, 0xffffffff,
637 : 0x000008fc, 0x00000000, 0xffffffff,
638 : 0x000008f8, 0x0000001b, 0xffffffff,
639 : 0x000008fc, 0x00000000, 0xffffffff
640 : };
641 : #define CAICOS_MGCG_DEFAULT_LENGTH sizeof(caicos_mgcg_default) / (3 * sizeof(u32))
642 :
643 : static const u32 caicos_mgcg_disable[] =
644 : {
645 : 0x0000802c, 0xc0000000, 0xffffffff,
646 : 0x000008f8, 0x00000000, 0xffffffff,
647 : 0x000008fc, 0xffffffff, 0xffffffff,
648 : 0x000008f8, 0x00000001, 0xffffffff,
649 : 0x000008fc, 0xffffffff, 0xffffffff,
650 : 0x000008f8, 0x00000002, 0xffffffff,
651 : 0x000008fc, 0xffffffff, 0xffffffff,
652 : 0x000008f8, 0x00000003, 0xffffffff,
653 : 0x000008fc, 0xffffffff, 0xffffffff,
654 : 0x00009150, 0x00600000, 0xffffffff
655 : };
656 : #define CAICOS_MGCG_DISABLE_LENGTH sizeof(caicos_mgcg_disable) / (3 * sizeof(u32))
657 :
658 : static const u32 caicos_mgcg_enable[] =
659 : {
660 : 0x0000802c, 0xc0000000, 0xffffffff,
661 : 0x000008f8, 0x00000000, 0xffffffff,
662 : 0x000008fc, 0x00000000, 0xffffffff,
663 : 0x000008f8, 0x00000001, 0xffffffff,
664 : 0x000008fc, 0x00000000, 0xffffffff,
665 : 0x000008f8, 0x00000002, 0xffffffff,
666 : 0x000008fc, 0x00000000, 0xffffffff,
667 : 0x000008f8, 0x00000003, 0xffffffff,
668 : 0x000008fc, 0x00000000, 0xffffffff,
669 : 0x00009150, 0x46944040, 0xffffffff
670 : };
671 : #define CAICOS_MGCG_ENABLE_LENGTH sizeof(caicos_mgcg_enable) / (3 * sizeof(u32))
672 :
673 : //********* TURKS **************//
674 : static const u32 turks_cgcg_cgls_default[] =
675 : {
676 : 0x000008f8, 0x00000010, 0xffffffff,
677 : 0x000008fc, 0x00000000, 0xffffffff,
678 : 0x000008f8, 0x00000011, 0xffffffff,
679 : 0x000008fc, 0x00000000, 0xffffffff,
680 : 0x000008f8, 0x00000012, 0xffffffff,
681 : 0x000008fc, 0x00000000, 0xffffffff,
682 : 0x000008f8, 0x00000013, 0xffffffff,
683 : 0x000008fc, 0x00000000, 0xffffffff,
684 : 0x000008f8, 0x00000014, 0xffffffff,
685 : 0x000008fc, 0x00000000, 0xffffffff,
686 : 0x000008f8, 0x00000015, 0xffffffff,
687 : 0x000008fc, 0x00000000, 0xffffffff,
688 : 0x000008f8, 0x00000016, 0xffffffff,
689 : 0x000008fc, 0x00000000, 0xffffffff,
690 : 0x000008f8, 0x00000017, 0xffffffff,
691 : 0x000008fc, 0x00000000, 0xffffffff,
692 : 0x000008f8, 0x00000018, 0xffffffff,
693 : 0x000008fc, 0x00000000, 0xffffffff,
694 : 0x000008f8, 0x00000019, 0xffffffff,
695 : 0x000008fc, 0x00000000, 0xffffffff,
696 : 0x000008f8, 0x0000001a, 0xffffffff,
697 : 0x000008fc, 0x00000000, 0xffffffff,
698 : 0x000008f8, 0x0000001b, 0xffffffff,
699 : 0x000008fc, 0x00000000, 0xffffffff,
700 : 0x000008f8, 0x00000020, 0xffffffff,
701 : 0x000008fc, 0x00000000, 0xffffffff,
702 : 0x000008f8, 0x00000021, 0xffffffff,
703 : 0x000008fc, 0x00000000, 0xffffffff,
704 : 0x000008f8, 0x00000022, 0xffffffff,
705 : 0x000008fc, 0x00000000, 0xffffffff,
706 : 0x000008f8, 0x00000023, 0xffffffff,
707 : 0x000008fc, 0x00000000, 0xffffffff,
708 : 0x000008f8, 0x00000024, 0xffffffff,
709 : 0x000008fc, 0x00000000, 0xffffffff,
710 : 0x000008f8, 0x00000025, 0xffffffff,
711 : 0x000008fc, 0x00000000, 0xffffffff,
712 : 0x000008f8, 0x00000026, 0xffffffff,
713 : 0x000008fc, 0x00000000, 0xffffffff,
714 : 0x000008f8, 0x00000027, 0xffffffff,
715 : 0x000008fc, 0x00000000, 0xffffffff,
716 : 0x000008f8, 0x00000028, 0xffffffff,
717 : 0x000008fc, 0x00000000, 0xffffffff,
718 : 0x000008f8, 0x00000029, 0xffffffff,
719 : 0x000008fc, 0x00000000, 0xffffffff,
720 : 0x000008f8, 0x0000002a, 0xffffffff,
721 : 0x000008fc, 0x00000000, 0xffffffff,
722 : 0x000008f8, 0x0000002b, 0xffffffff,
723 : 0x000008fc, 0x00000000, 0xffffffff
724 : };
725 : #define TURKS_CGCG_CGLS_DEFAULT_LENGTH sizeof(turks_cgcg_cgls_default) / (3 * sizeof(u32))
726 :
727 : static const u32 turks_cgcg_cgls_disable[] =
728 : {
729 : 0x000008f8, 0x00000010, 0xffffffff,
730 : 0x000008fc, 0xffffffff, 0xffffffff,
731 : 0x000008f8, 0x00000011, 0xffffffff,
732 : 0x000008fc, 0xffffffff, 0xffffffff,
733 : 0x000008f8, 0x00000012, 0xffffffff,
734 : 0x000008fc, 0xffffffff, 0xffffffff,
735 : 0x000008f8, 0x00000013, 0xffffffff,
736 : 0x000008fc, 0xffffffff, 0xffffffff,
737 : 0x000008f8, 0x00000014, 0xffffffff,
738 : 0x000008fc, 0xffffffff, 0xffffffff,
739 : 0x000008f8, 0x00000015, 0xffffffff,
740 : 0x000008fc, 0xffffffff, 0xffffffff,
741 : 0x000008f8, 0x00000016, 0xffffffff,
742 : 0x000008fc, 0xffffffff, 0xffffffff,
743 : 0x000008f8, 0x00000017, 0xffffffff,
744 : 0x000008fc, 0xffffffff, 0xffffffff,
745 : 0x000008f8, 0x00000018, 0xffffffff,
746 : 0x000008fc, 0xffffffff, 0xffffffff,
747 : 0x000008f8, 0x00000019, 0xffffffff,
748 : 0x000008fc, 0xffffffff, 0xffffffff,
749 : 0x000008f8, 0x0000001a, 0xffffffff,
750 : 0x000008fc, 0xffffffff, 0xffffffff,
751 : 0x000008f8, 0x0000001b, 0xffffffff,
752 : 0x000008fc, 0xffffffff, 0xffffffff,
753 : 0x000008f8, 0x00000020, 0xffffffff,
754 : 0x000008fc, 0x00000000, 0xffffffff,
755 : 0x000008f8, 0x00000021, 0xffffffff,
756 : 0x000008fc, 0x00000000, 0xffffffff,
757 : 0x000008f8, 0x00000022, 0xffffffff,
758 : 0x000008fc, 0x00000000, 0xffffffff,
759 : 0x000008f8, 0x00000023, 0xffffffff,
760 : 0x000008fc, 0x00000000, 0xffffffff,
761 : 0x000008f8, 0x00000024, 0xffffffff,
762 : 0x000008fc, 0x00000000, 0xffffffff,
763 : 0x000008f8, 0x00000025, 0xffffffff,
764 : 0x000008fc, 0x00000000, 0xffffffff,
765 : 0x000008f8, 0x00000026, 0xffffffff,
766 : 0x000008fc, 0x00000000, 0xffffffff,
767 : 0x000008f8, 0x00000027, 0xffffffff,
768 : 0x000008fc, 0x00000000, 0xffffffff,
769 : 0x000008f8, 0x00000028, 0xffffffff,
770 : 0x000008fc, 0x00000000, 0xffffffff,
771 : 0x000008f8, 0x00000029, 0xffffffff,
772 : 0x000008fc, 0x00000000, 0xffffffff,
773 : 0x000008f8, 0x0000002a, 0xffffffff,
774 : 0x000008fc, 0x00000000, 0xffffffff,
775 : 0x000008f8, 0x0000002b, 0xffffffff,
776 : 0x000008fc, 0x00000000, 0xffffffff,
777 : 0x00000644, 0x000f7912, 0x001f4180,
778 : 0x00000644, 0x000f3812, 0x001f4180
779 : };
780 : #define TURKS_CGCG_CGLS_DISABLE_LENGTH sizeof(turks_cgcg_cgls_disable) / (3 * sizeof(u32))
781 :
782 : static const u32 turks_cgcg_cgls_enable[] =
783 : {
784 : /* 0x0000c124, 0x84180000, 0x00180000, */
785 : 0x00000644, 0x000f7892, 0x001f4080,
786 : 0x000008f8, 0x00000010, 0xffffffff,
787 : 0x000008fc, 0x00000000, 0xffffffff,
788 : 0x000008f8, 0x00000011, 0xffffffff,
789 : 0x000008fc, 0x00000000, 0xffffffff,
790 : 0x000008f8, 0x00000012, 0xffffffff,
791 : 0x000008fc, 0x00000000, 0xffffffff,
792 : 0x000008f8, 0x00000013, 0xffffffff,
793 : 0x000008fc, 0x00000000, 0xffffffff,
794 : 0x000008f8, 0x00000014, 0xffffffff,
795 : 0x000008fc, 0x00000000, 0xffffffff,
796 : 0x000008f8, 0x00000015, 0xffffffff,
797 : 0x000008fc, 0x00000000, 0xffffffff,
798 : 0x000008f8, 0x00000016, 0xffffffff,
799 : 0x000008fc, 0x00000000, 0xffffffff,
800 : 0x000008f8, 0x00000017, 0xffffffff,
801 : 0x000008fc, 0x00000000, 0xffffffff,
802 : 0x000008f8, 0x00000018, 0xffffffff,
803 : 0x000008fc, 0x00000000, 0xffffffff,
804 : 0x000008f8, 0x00000019, 0xffffffff,
805 : 0x000008fc, 0x00000000, 0xffffffff,
806 : 0x000008f8, 0x0000001a, 0xffffffff,
807 : 0x000008fc, 0x00000000, 0xffffffff,
808 : 0x000008f8, 0x0000001b, 0xffffffff,
809 : 0x000008fc, 0x00000000, 0xffffffff,
810 : 0x000008f8, 0x00000020, 0xffffffff,
811 : 0x000008fc, 0xffffffff, 0xffffffff,
812 : 0x000008f8, 0x00000021, 0xffffffff,
813 : 0x000008fc, 0xffffffff, 0xffffffff,
814 : 0x000008f8, 0x00000022, 0xffffffff,
815 : 0x000008fc, 0xffffffff, 0xffffffff,
816 : 0x000008f8, 0x00000023, 0xffffffff,
817 : 0x000008fc, 0xffffffff, 0xffffffff,
818 : 0x000008f8, 0x00000024, 0xffffffff,
819 : 0x000008fc, 0xffffffff, 0xffffffff,
820 : 0x000008f8, 0x00000025, 0xffffffff,
821 : 0x000008fc, 0xffffffff, 0xffffffff,
822 : 0x000008f8, 0x00000026, 0xffffffff,
823 : 0x000008fc, 0xffffffff, 0xffffffff,
824 : 0x000008f8, 0x00000027, 0xffffffff,
825 : 0x000008fc, 0xffffffff, 0xffffffff,
826 : 0x000008f8, 0x00000028, 0xffffffff,
827 : 0x000008fc, 0xffffffff, 0xffffffff,
828 : 0x000008f8, 0x00000029, 0xffffffff,
829 : 0x000008fc, 0xffffffff, 0xffffffff,
830 : 0x000008f8, 0x0000002a, 0xffffffff,
831 : 0x000008fc, 0xffffffff, 0xffffffff,
832 : 0x000008f8, 0x0000002b, 0xffffffff,
833 : 0x000008fc, 0xffffffff, 0xffffffff
834 : };
835 : #define TURKS_CGCG_CGLS_ENABLE_LENGTH sizeof(turks_cgcg_cgls_enable) / (3 * sizeof(u32))
836 :
837 : // These are the sequences for turks_mgcg_shls
838 : static const u32 turks_mgcg_default[] =
839 : {
840 : 0x0000802c, 0xc0000000, 0xffffffff,
841 : 0x00005448, 0x00000100, 0xffffffff,
842 : 0x000055e4, 0x00600100, 0xffffffff,
843 : 0x0000160c, 0x00000100, 0xffffffff,
844 : 0x0000c164, 0x00000100, 0xffffffff,
845 : 0x00008a18, 0x00000100, 0xffffffff,
846 : 0x0000897c, 0x06000100, 0xffffffff,
847 : 0x00008b28, 0x00000100, 0xffffffff,
848 : 0x00009144, 0x00000100, 0xffffffff,
849 : 0x00009a60, 0x00000100, 0xffffffff,
850 : 0x00009868, 0x00000100, 0xffffffff,
851 : 0x00008d58, 0x00000100, 0xffffffff,
852 : 0x00009510, 0x00000100, 0xffffffff,
853 : 0x0000949c, 0x00000100, 0xffffffff,
854 : 0x00009654, 0x00000100, 0xffffffff,
855 : 0x00009030, 0x00000100, 0xffffffff,
856 : 0x00009034, 0x00000100, 0xffffffff,
857 : 0x00009038, 0x00000100, 0xffffffff,
858 : 0x0000903c, 0x00000100, 0xffffffff,
859 : 0x00009040, 0x00000100, 0xffffffff,
860 : 0x0000a200, 0x00000100, 0xffffffff,
861 : 0x0000a204, 0x00000100, 0xffffffff,
862 : 0x0000a208, 0x00000100, 0xffffffff,
863 : 0x0000a20c, 0x00000100, 0xffffffff,
864 : 0x0000977c, 0x00000100, 0xffffffff,
865 : 0x00003f80, 0x00000100, 0xffffffff,
866 : 0x0000a210, 0x00000100, 0xffffffff,
867 : 0x0000a214, 0x00000100, 0xffffffff,
868 : 0x000004d8, 0x00000100, 0xffffffff,
869 : 0x00009784, 0x00000100, 0xffffffff,
870 : 0x00009698, 0x00000100, 0xffffffff,
871 : 0x000004d4, 0x00000200, 0xffffffff,
872 : 0x000004d0, 0x00000000, 0xffffffff,
873 : 0x000030cc, 0x00000100, 0xffffffff,
874 : 0x0000d0c0, 0x00000100, 0xffffffff,
875 : 0x0000915c, 0x00010000, 0xffffffff,
876 : 0x00009160, 0x00030002, 0xffffffff,
877 : 0x00009164, 0x00050004, 0xffffffff,
878 : 0x00009168, 0x00070006, 0xffffffff,
879 : 0x00009178, 0x00070000, 0xffffffff,
880 : 0x0000917c, 0x00030002, 0xffffffff,
881 : 0x00009180, 0x00050004, 0xffffffff,
882 : 0x0000918c, 0x00010006, 0xffffffff,
883 : 0x00009190, 0x00090008, 0xffffffff,
884 : 0x00009194, 0x00070000, 0xffffffff,
885 : 0x00009198, 0x00030002, 0xffffffff,
886 : 0x0000919c, 0x00050004, 0xffffffff,
887 : 0x000091a8, 0x00010006, 0xffffffff,
888 : 0x000091ac, 0x00090008, 0xffffffff,
889 : 0x000091b0, 0x00070000, 0xffffffff,
890 : 0x000091b4, 0x00030002, 0xffffffff,
891 : 0x000091b8, 0x00050004, 0xffffffff,
892 : 0x000091c4, 0x00010006, 0xffffffff,
893 : 0x000091c8, 0x00090008, 0xffffffff,
894 : 0x000091cc, 0x00070000, 0xffffffff,
895 : 0x000091d0, 0x00030002, 0xffffffff,
896 : 0x000091d4, 0x00050004, 0xffffffff,
897 : 0x000091e0, 0x00010006, 0xffffffff,
898 : 0x000091e4, 0x00090008, 0xffffffff,
899 : 0x000091e8, 0x00000000, 0xffffffff,
900 : 0x000091ec, 0x00070000, 0xffffffff,
901 : 0x000091f0, 0x00030002, 0xffffffff,
902 : 0x000091f4, 0x00050004, 0xffffffff,
903 : 0x00009200, 0x00010006, 0xffffffff,
904 : 0x00009204, 0x00090008, 0xffffffff,
905 : 0x00009208, 0x00070000, 0xffffffff,
906 : 0x0000920c, 0x00030002, 0xffffffff,
907 : 0x00009210, 0x00050004, 0xffffffff,
908 : 0x0000921c, 0x00010006, 0xffffffff,
909 : 0x00009220, 0x00090008, 0xffffffff,
910 : 0x00009294, 0x00000000, 0xffffffff,
911 : 0x000008f8, 0x00000010, 0xffffffff,
912 : 0x000008fc, 0x00000000, 0xffffffff,
913 : 0x000008f8, 0x00000011, 0xffffffff,
914 : 0x000008fc, 0x00000000, 0xffffffff,
915 : 0x000008f8, 0x00000012, 0xffffffff,
916 : 0x000008fc, 0x00000000, 0xffffffff,
917 : 0x000008f8, 0x00000013, 0xffffffff,
918 : 0x000008fc, 0x00000000, 0xffffffff,
919 : 0x000008f8, 0x00000014, 0xffffffff,
920 : 0x000008fc, 0x00000000, 0xffffffff,
921 : 0x000008f8, 0x00000015, 0xffffffff,
922 : 0x000008fc, 0x00000000, 0xffffffff,
923 : 0x000008f8, 0x00000016, 0xffffffff,
924 : 0x000008fc, 0x00000000, 0xffffffff,
925 : 0x000008f8, 0x00000017, 0xffffffff,
926 : 0x000008fc, 0x00000000, 0xffffffff,
927 : 0x000008f8, 0x00000018, 0xffffffff,
928 : 0x000008fc, 0x00000000, 0xffffffff,
929 : 0x000008f8, 0x00000019, 0xffffffff,
930 : 0x000008fc, 0x00000000, 0xffffffff,
931 : 0x000008f8, 0x0000001a, 0xffffffff,
932 : 0x000008fc, 0x00000000, 0xffffffff,
933 : 0x000008f8, 0x0000001b, 0xffffffff,
934 : 0x000008fc, 0x00000000, 0xffffffff
935 : };
936 : #define TURKS_MGCG_DEFAULT_LENGTH sizeof(turks_mgcg_default) / (3 * sizeof(u32))
937 :
938 : static const u32 turks_mgcg_disable[] =
939 : {
940 : 0x0000802c, 0xc0000000, 0xffffffff,
941 : 0x000008f8, 0x00000000, 0xffffffff,
942 : 0x000008fc, 0xffffffff, 0xffffffff,
943 : 0x000008f8, 0x00000001, 0xffffffff,
944 : 0x000008fc, 0xffffffff, 0xffffffff,
945 : 0x000008f8, 0x00000002, 0xffffffff,
946 : 0x000008fc, 0xffffffff, 0xffffffff,
947 : 0x000008f8, 0x00000003, 0xffffffff,
948 : 0x000008fc, 0xffffffff, 0xffffffff,
949 : 0x00009150, 0x00600000, 0xffffffff
950 : };
951 : #define TURKS_MGCG_DISABLE_LENGTH sizeof(turks_mgcg_disable) / (3 * sizeof(u32))
952 :
953 : static const u32 turks_mgcg_enable[] =
954 : {
955 : 0x0000802c, 0xc0000000, 0xffffffff,
956 : 0x000008f8, 0x00000000, 0xffffffff,
957 : 0x000008fc, 0x00000000, 0xffffffff,
958 : 0x000008f8, 0x00000001, 0xffffffff,
959 : 0x000008fc, 0x00000000, 0xffffffff,
960 : 0x000008f8, 0x00000002, 0xffffffff,
961 : 0x000008fc, 0x00000000, 0xffffffff,
962 : 0x000008f8, 0x00000003, 0xffffffff,
963 : 0x000008fc, 0x00000000, 0xffffffff,
964 : 0x00009150, 0x6e944000, 0xffffffff
965 : };
966 : #define TURKS_MGCG_ENABLE_LENGTH sizeof(turks_mgcg_enable) / (3 * sizeof(u32))
967 :
968 : #endif
969 :
970 : #ifndef BTC_SYSLS_SEQUENCE
971 : #define BTC_SYSLS_SEQUENCE 100
972 :
973 :
974 : //********* BARTS **************//
975 : static const u32 barts_sysls_default[] =
976 : {
977 : /* Register, Value, Mask bits */
978 : 0x000055e8, 0x00000000, 0xffffffff,
979 : 0x0000d0bc, 0x00000000, 0xffffffff,
980 : 0x000015c0, 0x000c1401, 0xffffffff,
981 : 0x0000264c, 0x000c0400, 0xffffffff,
982 : 0x00002648, 0x000c0400, 0xffffffff,
983 : 0x00002650, 0x000c0400, 0xffffffff,
984 : 0x000020b8, 0x000c0400, 0xffffffff,
985 : 0x000020bc, 0x000c0400, 0xffffffff,
986 : 0x000020c0, 0x000c0c80, 0xffffffff,
987 : 0x0000f4a0, 0x000000c0, 0xffffffff,
988 : 0x0000f4a4, 0x00680fff, 0xffffffff,
989 : 0x000004c8, 0x00000001, 0xffffffff,
990 : 0x000064ec, 0x00000000, 0xffffffff,
991 : 0x00000c7c, 0x00000000, 0xffffffff,
992 : 0x00006dfc, 0x00000000, 0xffffffff
993 : };
994 : #define BARTS_SYSLS_DEFAULT_LENGTH sizeof(barts_sysls_default) / (3 * sizeof(u32))
995 :
996 : static const u32 barts_sysls_disable[] =
997 : {
998 : 0x000055e8, 0x00000000, 0xffffffff,
999 : 0x0000d0bc, 0x00000000, 0xffffffff,
1000 : 0x000015c0, 0x00041401, 0xffffffff,
1001 : 0x0000264c, 0x00040400, 0xffffffff,
1002 : 0x00002648, 0x00040400, 0xffffffff,
1003 : 0x00002650, 0x00040400, 0xffffffff,
1004 : 0x000020b8, 0x00040400, 0xffffffff,
1005 : 0x000020bc, 0x00040400, 0xffffffff,
1006 : 0x000020c0, 0x00040c80, 0xffffffff,
1007 : 0x0000f4a0, 0x000000c0, 0xffffffff,
1008 : 0x0000f4a4, 0x00680000, 0xffffffff,
1009 : 0x000004c8, 0x00000001, 0xffffffff,
1010 : 0x000064ec, 0x00007ffd, 0xffffffff,
1011 : 0x00000c7c, 0x0000ff00, 0xffffffff,
1012 : 0x00006dfc, 0x0000007f, 0xffffffff
1013 : };
1014 : #define BARTS_SYSLS_DISABLE_LENGTH sizeof(barts_sysls_disable) / (3 * sizeof(u32))
1015 :
1016 : static const u32 barts_sysls_enable[] =
1017 : {
1018 : 0x000055e8, 0x00000001, 0xffffffff,
1019 : 0x0000d0bc, 0x00000100, 0xffffffff,
1020 : 0x000015c0, 0x000c1401, 0xffffffff,
1021 : 0x0000264c, 0x000c0400, 0xffffffff,
1022 : 0x00002648, 0x000c0400, 0xffffffff,
1023 : 0x00002650, 0x000c0400, 0xffffffff,
1024 : 0x000020b8, 0x000c0400, 0xffffffff,
1025 : 0x000020bc, 0x000c0400, 0xffffffff,
1026 : 0x000020c0, 0x000c0c80, 0xffffffff,
1027 : 0x0000f4a0, 0x000000c0, 0xffffffff,
1028 : 0x0000f4a4, 0x00680fff, 0xffffffff,
1029 : 0x000004c8, 0x00000000, 0xffffffff,
1030 : 0x000064ec, 0x00000000, 0xffffffff,
1031 : 0x00000c7c, 0x00000000, 0xffffffff,
1032 : 0x00006dfc, 0x00000000, 0xffffffff
1033 : };
1034 : #define BARTS_SYSLS_ENABLE_LENGTH sizeof(barts_sysls_enable) / (3 * sizeof(u32))
1035 :
1036 : //********* CAICOS **************//
1037 : static const u32 caicos_sysls_default[] =
1038 : {
1039 : 0x000055e8, 0x00000000, 0xffffffff,
1040 : 0x0000d0bc, 0x00000000, 0xffffffff,
1041 : 0x000015c0, 0x000c1401, 0xffffffff,
1042 : 0x0000264c, 0x000c0400, 0xffffffff,
1043 : 0x00002648, 0x000c0400, 0xffffffff,
1044 : 0x00002650, 0x000c0400, 0xffffffff,
1045 : 0x000020b8, 0x000c0400, 0xffffffff,
1046 : 0x000020bc, 0x000c0400, 0xffffffff,
1047 : 0x0000f4a0, 0x000000c0, 0xffffffff,
1048 : 0x0000f4a4, 0x00680fff, 0xffffffff,
1049 : 0x000004c8, 0x00000001, 0xffffffff,
1050 : 0x000064ec, 0x00000000, 0xffffffff,
1051 : 0x00000c7c, 0x00000000, 0xffffffff,
1052 : 0x00006dfc, 0x00000000, 0xffffffff
1053 : };
1054 : #define CAICOS_SYSLS_DEFAULT_LENGTH sizeof(caicos_sysls_default) / (3 * sizeof(u32))
1055 :
1056 : static const u32 caicos_sysls_disable[] =
1057 : {
1058 : 0x000055e8, 0x00000000, 0xffffffff,
1059 : 0x0000d0bc, 0x00000000, 0xffffffff,
1060 : 0x000015c0, 0x00041401, 0xffffffff,
1061 : 0x0000264c, 0x00040400, 0xffffffff,
1062 : 0x00002648, 0x00040400, 0xffffffff,
1063 : 0x00002650, 0x00040400, 0xffffffff,
1064 : 0x000020b8, 0x00040400, 0xffffffff,
1065 : 0x000020bc, 0x00040400, 0xffffffff,
1066 : 0x0000f4a0, 0x000000c0, 0xffffffff,
1067 : 0x0000f4a4, 0x00680000, 0xffffffff,
1068 : 0x000004c8, 0x00000001, 0xffffffff,
1069 : 0x000064ec, 0x00007ffd, 0xffffffff,
1070 : 0x00000c7c, 0x0000ff00, 0xffffffff,
1071 : 0x00006dfc, 0x0000007f, 0xffffffff
1072 : };
1073 : #define CAICOS_SYSLS_DISABLE_LENGTH sizeof(caicos_sysls_disable) / (3 * sizeof(u32))
1074 :
1075 : static const u32 caicos_sysls_enable[] =
1076 : {
1077 : 0x000055e8, 0x00000001, 0xffffffff,
1078 : 0x0000d0bc, 0x00000100, 0xffffffff,
1079 : 0x000015c0, 0x000c1401, 0xffffffff,
1080 : 0x0000264c, 0x000c0400, 0xffffffff,
1081 : 0x00002648, 0x000c0400, 0xffffffff,
1082 : 0x00002650, 0x000c0400, 0xffffffff,
1083 : 0x000020b8, 0x000c0400, 0xffffffff,
1084 : 0x000020bc, 0x000c0400, 0xffffffff,
1085 : 0x0000f4a0, 0x000000c0, 0xffffffff,
1086 : 0x0000f4a4, 0x00680fff, 0xffffffff,
1087 : 0x000064ec, 0x00000000, 0xffffffff,
1088 : 0x00000c7c, 0x00000000, 0xffffffff,
1089 : 0x00006dfc, 0x00000000, 0xffffffff,
1090 : 0x000004c8, 0x00000000, 0xffffffff
1091 : };
1092 : #define CAICOS_SYSLS_ENABLE_LENGTH sizeof(caicos_sysls_enable) / (3 * sizeof(u32))
1093 :
1094 : //********* TURKS **************//
1095 : static const u32 turks_sysls_default[] =
1096 : {
1097 : 0x000055e8, 0x00000000, 0xffffffff,
1098 : 0x0000d0bc, 0x00000000, 0xffffffff,
1099 : 0x000015c0, 0x000c1401, 0xffffffff,
1100 : 0x0000264c, 0x000c0400, 0xffffffff,
1101 : 0x00002648, 0x000c0400, 0xffffffff,
1102 : 0x00002650, 0x000c0400, 0xffffffff,
1103 : 0x000020b8, 0x000c0400, 0xffffffff,
1104 : 0x000020bc, 0x000c0400, 0xffffffff,
1105 : 0x000020c0, 0x000c0c80, 0xffffffff,
1106 : 0x0000f4a0, 0x000000c0, 0xffffffff,
1107 : 0x0000f4a4, 0x00680fff, 0xffffffff,
1108 : 0x000004c8, 0x00000001, 0xffffffff,
1109 : 0x000064ec, 0x00000000, 0xffffffff,
1110 : 0x00000c7c, 0x00000000, 0xffffffff,
1111 : 0x00006dfc, 0x00000000, 0xffffffff
1112 : };
1113 : #define TURKS_SYSLS_DEFAULT_LENGTH sizeof(turks_sysls_default) / (3 * sizeof(u32))
1114 :
1115 : static const u32 turks_sysls_disable[] =
1116 : {
1117 : 0x000055e8, 0x00000000, 0xffffffff,
1118 : 0x0000d0bc, 0x00000000, 0xffffffff,
1119 : 0x000015c0, 0x00041401, 0xffffffff,
1120 : 0x0000264c, 0x00040400, 0xffffffff,
1121 : 0x00002648, 0x00040400, 0xffffffff,
1122 : 0x00002650, 0x00040400, 0xffffffff,
1123 : 0x000020b8, 0x00040400, 0xffffffff,
1124 : 0x000020bc, 0x00040400, 0xffffffff,
1125 : 0x000020c0, 0x00040c80, 0xffffffff,
1126 : 0x0000f4a0, 0x000000c0, 0xffffffff,
1127 : 0x0000f4a4, 0x00680000, 0xffffffff,
1128 : 0x000004c8, 0x00000001, 0xffffffff,
1129 : 0x000064ec, 0x00007ffd, 0xffffffff,
1130 : 0x00000c7c, 0x0000ff00, 0xffffffff,
1131 : 0x00006dfc, 0x0000007f, 0xffffffff
1132 : };
1133 : #define TURKS_SYSLS_DISABLE_LENGTH sizeof(turks_sysls_disable) / (3 * sizeof(u32))
1134 :
1135 : static const u32 turks_sysls_enable[] =
1136 : {
1137 : 0x000055e8, 0x00000001, 0xffffffff,
1138 : 0x0000d0bc, 0x00000100, 0xffffffff,
1139 : 0x000015c0, 0x000c1401, 0xffffffff,
1140 : 0x0000264c, 0x000c0400, 0xffffffff,
1141 : 0x00002648, 0x000c0400, 0xffffffff,
1142 : 0x00002650, 0x000c0400, 0xffffffff,
1143 : 0x000020b8, 0x000c0400, 0xffffffff,
1144 : 0x000020bc, 0x000c0400, 0xffffffff,
1145 : 0x000020c0, 0x000c0c80, 0xffffffff,
1146 : 0x0000f4a0, 0x000000c0, 0xffffffff,
1147 : 0x0000f4a4, 0x00680fff, 0xffffffff,
1148 : 0x000004c8, 0x00000000, 0xffffffff,
1149 : 0x000064ec, 0x00000000, 0xffffffff,
1150 : 0x00000c7c, 0x00000000, 0xffffffff,
1151 : 0x00006dfc, 0x00000000, 0xffffffff
1152 : };
1153 : #define TURKS_SYSLS_ENABLE_LENGTH sizeof(turks_sysls_enable) / (3 * sizeof(u32))
1154 :
1155 : #endif
1156 :
1157 : u32 btc_valid_sclk[40] =
1158 : {
1159 : 5000, 10000, 15000, 20000, 25000, 30000, 35000, 40000, 45000, 50000,
1160 : 55000, 60000, 65000, 70000, 75000, 80000, 85000, 90000, 95000, 100000,
1161 : 105000, 110000, 11500, 120000, 125000, 130000, 135000, 140000, 145000, 150000,
1162 : 155000, 160000, 165000, 170000, 175000, 180000, 185000, 190000, 195000, 200000
1163 : };
1164 :
1165 : static const struct radeon_blacklist_clocks btc_blacklist_clocks[] =
1166 : {
1167 : { 10000, 30000, RADEON_SCLK_UP },
1168 : { 15000, 30000, RADEON_SCLK_UP },
1169 : { 20000, 30000, RADEON_SCLK_UP },
1170 : { 25000, 30000, RADEON_SCLK_UP }
1171 : };
1172 :
1173 0 : void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
1174 : u32 *max_clock)
1175 : {
1176 : u32 i, clock = 0;
1177 :
1178 0 : if ((table == NULL) || (table->count == 0)) {
1179 0 : *max_clock = clock;
1180 0 : return;
1181 : }
1182 :
1183 0 : for (i = 0; i < table->count; i++) {
1184 0 : if (clock < table->entries[i].clk)
1185 0 : clock = table->entries[i].clk;
1186 : }
1187 0 : *max_clock = clock;
1188 0 : }
1189 :
1190 0 : void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,
1191 : u32 clock, u16 max_voltage, u16 *voltage)
1192 : {
1193 : u32 i;
1194 :
1195 0 : if ((table == NULL) || (table->count == 0))
1196 0 : return;
1197 :
1198 0 : for (i= 0; i < table->count; i++) {
1199 0 : if (clock <= table->entries[i].clk) {
1200 0 : if (*voltage < table->entries[i].v)
1201 0 : *voltage = (u16)((table->entries[i].v < max_voltage) ?
1202 : table->entries[i].v : max_voltage);
1203 0 : return;
1204 : }
1205 : }
1206 :
1207 0 : *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
1208 0 : }
1209 :
1210 0 : static u32 btc_find_valid_clock(struct radeon_clock_array *clocks,
1211 : u32 max_clock, u32 requested_clock)
1212 : {
1213 : unsigned int i;
1214 :
1215 0 : if ((clocks == NULL) || (clocks->count == 0))
1216 0 : return (requested_clock < max_clock) ? requested_clock : max_clock;
1217 :
1218 0 : for (i = 0; i < clocks->count; i++) {
1219 0 : if (clocks->values[i] >= requested_clock)
1220 0 : return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
1221 : }
1222 :
1223 0 : return (clocks->values[clocks->count - 1] < max_clock) ?
1224 : clocks->values[clocks->count - 1] : max_clock;
1225 0 : }
1226 :
1227 0 : static u32 btc_get_valid_mclk(struct radeon_device *rdev,
1228 : u32 max_mclk, u32 requested_mclk)
1229 : {
1230 0 : return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values,
1231 : max_mclk, requested_mclk);
1232 : }
1233 :
1234 0 : static u32 btc_get_valid_sclk(struct radeon_device *rdev,
1235 : u32 max_sclk, u32 requested_sclk)
1236 : {
1237 0 : return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values,
1238 : max_sclk, requested_sclk);
1239 : }
1240 :
1241 0 : void btc_skip_blacklist_clocks(struct radeon_device *rdev,
1242 : const u32 max_sclk, const u32 max_mclk,
1243 : u32 *sclk, u32 *mclk)
1244 : {
1245 : int i, num_blacklist_clocks;
1246 :
1247 0 : if ((sclk == NULL) || (mclk == NULL))
1248 0 : return;
1249 :
1250 : num_blacklist_clocks = ARRAY_SIZE(btc_blacklist_clocks);
1251 :
1252 0 : for (i = 0; i < num_blacklist_clocks; i++) {
1253 0 : if ((btc_blacklist_clocks[i].sclk == *sclk) &&
1254 0 : (btc_blacklist_clocks[i].mclk == *mclk))
1255 : break;
1256 : }
1257 :
1258 0 : if (i < num_blacklist_clocks) {
1259 0 : if (btc_blacklist_clocks[i].action == RADEON_SCLK_UP) {
1260 0 : *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1);
1261 :
1262 0 : if (*sclk < max_sclk)
1263 0 : btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk);
1264 : }
1265 : }
1266 0 : }
1267 :
1268 0 : void btc_adjust_clock_combinations(struct radeon_device *rdev,
1269 : const struct radeon_clock_and_voltage_limits *max_limits,
1270 : struct rv7xx_pl *pl)
1271 : {
1272 :
1273 0 : if ((pl->mclk == 0) || (pl->sclk == 0))
1274 : return;
1275 :
1276 0 : if (pl->mclk == pl->sclk)
1277 : return;
1278 :
1279 0 : if (pl->mclk > pl->sclk) {
1280 0 : if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
1281 0 : pl->sclk = btc_get_valid_sclk(rdev,
1282 0 : max_limits->sclk,
1283 0 : (pl->mclk +
1284 0 : (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
1285 : rdev->pm.dpm.dyn_state.mclk_sclk_ratio);
1286 : } else {
1287 0 : if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta)
1288 0 : pl->mclk = btc_get_valid_mclk(rdev,
1289 0 : max_limits->mclk,
1290 0 : pl->sclk -
1291 : rdev->pm.dpm.dyn_state.sclk_mclk_delta);
1292 : }
1293 0 : }
1294 :
1295 0 : static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
1296 : {
1297 : unsigned int i;
1298 :
1299 0 : for (i = 0; i < table->count; i++) {
1300 0 : if (voltage <= table->entries[i].value)
1301 0 : return table->entries[i].value;
1302 : }
1303 :
1304 0 : return table->entries[table->count - 1].value;
1305 0 : }
1306 :
1307 0 : void btc_apply_voltage_delta_rules(struct radeon_device *rdev,
1308 : u16 max_vddc, u16 max_vddci,
1309 : u16 *vddc, u16 *vddci)
1310 : {
1311 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1312 : u16 new_voltage;
1313 :
1314 0 : if ((0 == *vddc) || (0 == *vddci))
1315 0 : return;
1316 :
1317 0 : if (*vddc > *vddci) {
1318 0 : if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1319 0 : new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
1320 0 : (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1321 0 : *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
1322 0 : }
1323 : } else {
1324 0 : if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1325 0 : new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
1326 0 : (*vddci - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1327 0 : *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
1328 0 : }
1329 : }
1330 0 : }
1331 :
1332 0 : static void btc_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
1333 : bool enable)
1334 : {
1335 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1336 : u32 tmp, bif;
1337 :
1338 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
1339 0 : if (enable) {
1340 0 : if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1341 0 : (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1342 0 : if (!pi->boot_in_gen2) {
1343 0 : bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
1344 0 : bif |= CG_CLIENT_REQ(0xd);
1345 0 : WREG32(CG_BIF_REQ_AND_RSP, bif);
1346 :
1347 0 : tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
1348 0 : tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
1349 0 : tmp |= LC_GEN2_EN_STRAP;
1350 :
1351 0 : tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1352 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
1353 0 : udelay(10);
1354 0 : tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1355 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
1356 0 : }
1357 : }
1358 : } else {
1359 0 : if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
1360 0 : (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1361 0 : if (!pi->boot_in_gen2) {
1362 0 : bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
1363 0 : bif |= CG_CLIENT_REQ(0xd);
1364 0 : WREG32(CG_BIF_REQ_AND_RSP, bif);
1365 :
1366 0 : tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
1367 0 : tmp &= ~LC_GEN2_EN_STRAP;
1368 0 : }
1369 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
1370 0 : }
1371 : }
1372 0 : }
1373 :
1374 0 : static void btc_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1375 : bool enable)
1376 : {
1377 0 : btc_enable_bif_dynamic_pcie_gen2(rdev, enable);
1378 :
1379 0 : if (enable)
1380 0 : WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
1381 : else
1382 0 : WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
1383 0 : }
1384 :
1385 0 : static int btc_disable_ulv(struct radeon_device *rdev)
1386 : {
1387 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1388 :
1389 0 : if (eg_pi->ulv.supported) {
1390 0 : if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) != PPSMC_Result_OK)
1391 0 : return -EINVAL;
1392 : }
1393 0 : return 0;
1394 0 : }
1395 :
1396 0 : static int btc_populate_ulv_state(struct radeon_device *rdev,
1397 : RV770_SMC_STATETABLE *table)
1398 : {
1399 : int ret = -EINVAL;
1400 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1401 0 : struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl;
1402 :
1403 0 : if (ulv_pl->vddc) {
1404 0 : ret = cypress_convert_power_level_to_smc(rdev,
1405 : ulv_pl,
1406 0 : &table->ULVState.levels[0],
1407 : PPSMC_DISPLAY_WATERMARK_LOW);
1408 0 : if (ret == 0) {
1409 0 : table->ULVState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
1410 0 : table->ULVState.levels[0].ACIndex = 1;
1411 :
1412 0 : table->ULVState.levels[1] = table->ULVState.levels[0];
1413 0 : table->ULVState.levels[2] = table->ULVState.levels[0];
1414 :
1415 0 : table->ULVState.flags |= PPSMC_SWSTATE_FLAG_DC;
1416 :
1417 0 : WREG32(CG_ULV_CONTROL, BTC_CGULVCONTROL_DFLT);
1418 0 : WREG32(CG_ULV_PARAMETER, BTC_CGULVPARAMETER_DFLT);
1419 0 : }
1420 : }
1421 :
1422 0 : return ret;
1423 : }
1424 :
1425 0 : static int btc_populate_smc_acpi_state(struct radeon_device *rdev,
1426 : RV770_SMC_STATETABLE *table)
1427 : {
1428 0 : int ret = cypress_populate_smc_acpi_state(rdev, table);
1429 :
1430 0 : if (ret == 0) {
1431 0 : table->ACPIState.levels[0].ACIndex = 0;
1432 0 : table->ACPIState.levels[1].ACIndex = 0;
1433 0 : table->ACPIState.levels[2].ACIndex = 0;
1434 0 : }
1435 :
1436 0 : return ret;
1437 : }
1438 :
1439 0 : void btc_program_mgcg_hw_sequence(struct radeon_device *rdev,
1440 : const u32 *sequence, u32 count)
1441 : {
1442 0 : u32 i, length = count * 3;
1443 : u32 tmp;
1444 :
1445 0 : for (i = 0; i < length; i+=3) {
1446 0 : tmp = RREG32(sequence[i]);
1447 0 : tmp &= ~sequence[i+2];
1448 0 : tmp |= sequence[i+1] & sequence[i+2];
1449 0 : WREG32(sequence[i], tmp);
1450 : }
1451 0 : }
1452 :
1453 0 : static void btc_cg_clock_gating_default(struct radeon_device *rdev)
1454 : {
1455 : u32 count;
1456 : const u32 *p = NULL;
1457 :
1458 0 : if (rdev->family == CHIP_BARTS) {
1459 : p = (const u32 *)&barts_cgcg_cgls_default;
1460 : count = BARTS_CGCG_CGLS_DEFAULT_LENGTH;
1461 0 : } else if (rdev->family == CHIP_TURKS) {
1462 : p = (const u32 *)&turks_cgcg_cgls_default;
1463 : count = TURKS_CGCG_CGLS_DEFAULT_LENGTH;
1464 0 : } else if (rdev->family == CHIP_CAICOS) {
1465 : p = (const u32 *)&caicos_cgcg_cgls_default;
1466 : count = CAICOS_CGCG_CGLS_DEFAULT_LENGTH;
1467 : } else
1468 0 : return;
1469 :
1470 0 : btc_program_mgcg_hw_sequence(rdev, p, count);
1471 0 : }
1472 :
1473 0 : static void btc_cg_clock_gating_enable(struct radeon_device *rdev,
1474 : bool enable)
1475 : {
1476 : u32 count;
1477 : const u32 *p = NULL;
1478 :
1479 0 : if (enable) {
1480 0 : if (rdev->family == CHIP_BARTS) {
1481 : p = (const u32 *)&barts_cgcg_cgls_enable;
1482 : count = BARTS_CGCG_CGLS_ENABLE_LENGTH;
1483 0 : } else if (rdev->family == CHIP_TURKS) {
1484 : p = (const u32 *)&turks_cgcg_cgls_enable;
1485 : count = TURKS_CGCG_CGLS_ENABLE_LENGTH;
1486 0 : } else if (rdev->family == CHIP_CAICOS) {
1487 : p = (const u32 *)&caicos_cgcg_cgls_enable;
1488 : count = CAICOS_CGCG_CGLS_ENABLE_LENGTH;
1489 : } else
1490 0 : return;
1491 : } else {
1492 0 : if (rdev->family == CHIP_BARTS) {
1493 : p = (const u32 *)&barts_cgcg_cgls_disable;
1494 : count = BARTS_CGCG_CGLS_DISABLE_LENGTH;
1495 0 : } else if (rdev->family == CHIP_TURKS) {
1496 : p = (const u32 *)&turks_cgcg_cgls_disable;
1497 : count = TURKS_CGCG_CGLS_DISABLE_LENGTH;
1498 0 : } else if (rdev->family == CHIP_CAICOS) {
1499 : p = (const u32 *)&caicos_cgcg_cgls_disable;
1500 : count = CAICOS_CGCG_CGLS_DISABLE_LENGTH;
1501 : } else
1502 0 : return;
1503 : }
1504 :
1505 0 : btc_program_mgcg_hw_sequence(rdev, p, count);
1506 0 : }
1507 :
1508 0 : static void btc_mg_clock_gating_default(struct radeon_device *rdev)
1509 : {
1510 : u32 count;
1511 : const u32 *p = NULL;
1512 :
1513 0 : if (rdev->family == CHIP_BARTS) {
1514 : p = (const u32 *)&barts_mgcg_default;
1515 : count = BARTS_MGCG_DEFAULT_LENGTH;
1516 0 : } else if (rdev->family == CHIP_TURKS) {
1517 : p = (const u32 *)&turks_mgcg_default;
1518 : count = TURKS_MGCG_DEFAULT_LENGTH;
1519 0 : } else if (rdev->family == CHIP_CAICOS) {
1520 : p = (const u32 *)&caicos_mgcg_default;
1521 : count = CAICOS_MGCG_DEFAULT_LENGTH;
1522 : } else
1523 0 : return;
1524 :
1525 0 : btc_program_mgcg_hw_sequence(rdev, p, count);
1526 0 : }
1527 :
1528 0 : static void btc_mg_clock_gating_enable(struct radeon_device *rdev,
1529 : bool enable)
1530 : {
1531 : u32 count;
1532 : const u32 *p = NULL;
1533 :
1534 0 : if (enable) {
1535 0 : if (rdev->family == CHIP_BARTS) {
1536 : p = (const u32 *)&barts_mgcg_enable;
1537 : count = BARTS_MGCG_ENABLE_LENGTH;
1538 0 : } else if (rdev->family == CHIP_TURKS) {
1539 : p = (const u32 *)&turks_mgcg_enable;
1540 : count = TURKS_MGCG_ENABLE_LENGTH;
1541 0 : } else if (rdev->family == CHIP_CAICOS) {
1542 : p = (const u32 *)&caicos_mgcg_enable;
1543 : count = CAICOS_MGCG_ENABLE_LENGTH;
1544 : } else
1545 0 : return;
1546 : } else {
1547 0 : if (rdev->family == CHIP_BARTS) {
1548 : p = (const u32 *)&barts_mgcg_disable[0];
1549 : count = BARTS_MGCG_DISABLE_LENGTH;
1550 0 : } else if (rdev->family == CHIP_TURKS) {
1551 : p = (const u32 *)&turks_mgcg_disable[0];
1552 : count = TURKS_MGCG_DISABLE_LENGTH;
1553 0 : } else if (rdev->family == CHIP_CAICOS) {
1554 : p = (const u32 *)&caicos_mgcg_disable[0];
1555 : count = CAICOS_MGCG_DISABLE_LENGTH;
1556 : } else
1557 0 : return;
1558 : }
1559 :
1560 0 : btc_program_mgcg_hw_sequence(rdev, p, count);
1561 0 : }
1562 :
1563 0 : static void btc_ls_clock_gating_default(struct radeon_device *rdev)
1564 : {
1565 : u32 count;
1566 : const u32 *p = NULL;
1567 :
1568 0 : if (rdev->family == CHIP_BARTS) {
1569 : p = (const u32 *)&barts_sysls_default;
1570 : count = BARTS_SYSLS_DEFAULT_LENGTH;
1571 0 : } else if (rdev->family == CHIP_TURKS) {
1572 : p = (const u32 *)&turks_sysls_default;
1573 : count = TURKS_SYSLS_DEFAULT_LENGTH;
1574 0 : } else if (rdev->family == CHIP_CAICOS) {
1575 : p = (const u32 *)&caicos_sysls_default;
1576 : count = CAICOS_SYSLS_DEFAULT_LENGTH;
1577 : } else
1578 0 : return;
1579 :
1580 0 : btc_program_mgcg_hw_sequence(rdev, p, count);
1581 0 : }
1582 :
1583 0 : static void btc_ls_clock_gating_enable(struct radeon_device *rdev,
1584 : bool enable)
1585 : {
1586 : u32 count;
1587 : const u32 *p = NULL;
1588 :
1589 0 : if (enable) {
1590 0 : if (rdev->family == CHIP_BARTS) {
1591 : p = (const u32 *)&barts_sysls_enable;
1592 : count = BARTS_SYSLS_ENABLE_LENGTH;
1593 0 : } else if (rdev->family == CHIP_TURKS) {
1594 : p = (const u32 *)&turks_sysls_enable;
1595 : count = TURKS_SYSLS_ENABLE_LENGTH;
1596 0 : } else if (rdev->family == CHIP_CAICOS) {
1597 : p = (const u32 *)&caicos_sysls_enable;
1598 : count = CAICOS_SYSLS_ENABLE_LENGTH;
1599 : } else
1600 0 : return;
1601 : } else {
1602 0 : if (rdev->family == CHIP_BARTS) {
1603 : p = (const u32 *)&barts_sysls_disable;
1604 : count = BARTS_SYSLS_DISABLE_LENGTH;
1605 0 : } else if (rdev->family == CHIP_TURKS) {
1606 : p = (const u32 *)&turks_sysls_disable;
1607 : count = TURKS_SYSLS_DISABLE_LENGTH;
1608 0 : } else if (rdev->family == CHIP_CAICOS) {
1609 : p = (const u32 *)&caicos_sysls_disable;
1610 : count = CAICOS_SYSLS_DISABLE_LENGTH;
1611 : } else
1612 0 : return;
1613 : }
1614 :
1615 0 : btc_program_mgcg_hw_sequence(rdev, p, count);
1616 0 : }
1617 :
1618 0 : bool btc_dpm_enabled(struct radeon_device *rdev)
1619 : {
1620 0 : if (rv770_is_smc_running(rdev))
1621 0 : return true;
1622 : else
1623 0 : return false;
1624 0 : }
1625 :
1626 0 : static int btc_init_smc_table(struct radeon_device *rdev,
1627 : struct radeon_ps *radeon_boot_state)
1628 : {
1629 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1630 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1631 0 : RV770_SMC_STATETABLE *table = &pi->smc_statetable;
1632 : int ret;
1633 :
1634 0 : memset(table, 0, sizeof(RV770_SMC_STATETABLE));
1635 :
1636 0 : cypress_populate_smc_voltage_tables(rdev, table);
1637 :
1638 0 : switch (rdev->pm.int_thermal_type) {
1639 : case THERMAL_TYPE_EVERGREEN:
1640 : case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1641 0 : table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1642 0 : break;
1643 : case THERMAL_TYPE_NONE:
1644 0 : table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1645 0 : break;
1646 : default:
1647 0 : table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1648 0 : break;
1649 : }
1650 :
1651 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1652 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1653 :
1654 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1655 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1656 :
1657 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1658 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1659 :
1660 0 : if (pi->mem_gddr5)
1661 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1662 :
1663 0 : ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
1664 0 : if (ret)
1665 0 : return ret;
1666 :
1667 0 : if (eg_pi->sclk_deep_sleep)
1668 0 : WREG32_P(SCLK_PSKIP_CNTL, PSKIP_ON_ALLOW_STOP_HI(32),
1669 : ~PSKIP_ON_ALLOW_STOP_HI_MASK);
1670 :
1671 0 : ret = btc_populate_smc_acpi_state(rdev, table);
1672 0 : if (ret)
1673 0 : return ret;
1674 :
1675 0 : if (eg_pi->ulv.supported) {
1676 0 : ret = btc_populate_ulv_state(rdev, table);
1677 0 : if (ret)
1678 0 : eg_pi->ulv.supported = false;
1679 : }
1680 :
1681 0 : table->driverState = table->initialState;
1682 :
1683 0 : return rv770_copy_bytes_to_smc(rdev,
1684 0 : pi->state_table_start,
1685 : (u8 *)table,
1686 : sizeof(RV770_SMC_STATETABLE),
1687 0 : pi->sram_end);
1688 0 : }
1689 :
1690 0 : static void btc_set_at_for_uvd(struct radeon_device *rdev,
1691 : struct radeon_ps *radeon_new_state)
1692 : {
1693 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1694 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1695 : int idx = 0;
1696 :
1697 0 : if (r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2))
1698 0 : idx = 1;
1699 :
1700 0 : if ((idx == 1) && !eg_pi->smu_uvd_hs) {
1701 0 : pi->rlp = 10;
1702 0 : pi->rmp = 100;
1703 0 : pi->lhp = 100;
1704 0 : pi->lmp = 10;
1705 0 : } else {
1706 0 : pi->rlp = eg_pi->ats[idx].rlp;
1707 0 : pi->rmp = eg_pi->ats[idx].rmp;
1708 0 : pi->lhp = eg_pi->ats[idx].lhp;
1709 0 : pi->lmp = eg_pi->ats[idx].lmp;
1710 : }
1711 :
1712 0 : }
1713 :
1714 0 : void btc_notify_uvd_to_smc(struct radeon_device *rdev,
1715 : struct radeon_ps *radeon_new_state)
1716 : {
1717 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1718 :
1719 0 : if (r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {
1720 0 : rv770_write_smc_soft_register(rdev,
1721 : RV770_SMC_SOFT_REGISTER_uvd_enabled, 1);
1722 0 : eg_pi->uvd_enabled = true;
1723 0 : } else {
1724 0 : rv770_write_smc_soft_register(rdev,
1725 : RV770_SMC_SOFT_REGISTER_uvd_enabled, 0);
1726 0 : eg_pi->uvd_enabled = false;
1727 : }
1728 0 : }
1729 :
1730 0 : int btc_reset_to_default(struct radeon_device *rdev)
1731 : {
1732 0 : if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) != PPSMC_Result_OK)
1733 0 : return -EINVAL;
1734 :
1735 0 : return 0;
1736 0 : }
1737 :
1738 0 : static void btc_stop_smc(struct radeon_device *rdev)
1739 : {
1740 : int i;
1741 :
1742 0 : for (i = 0; i < rdev->usec_timeout; i++) {
1743 0 : if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1)
1744 : break;
1745 0 : udelay(1);
1746 : }
1747 0 : udelay(100);
1748 :
1749 0 : r7xx_stop_smc(rdev);
1750 0 : }
1751 :
1752 0 : void btc_read_arb_registers(struct radeon_device *rdev)
1753 : {
1754 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1755 : struct evergreen_arb_registers *arb_registers =
1756 0 : &eg_pi->bootup_arb_registers;
1757 :
1758 0 : arb_registers->mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
1759 0 : arb_registers->mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
1760 0 : arb_registers->mc_arb_rfsh_rate = RREG32(MC_ARB_RFSH_RATE);
1761 0 : arb_registers->mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
1762 0 : }
1763 :
1764 :
1765 0 : static void btc_set_arb0_registers(struct radeon_device *rdev,
1766 : struct evergreen_arb_registers *arb_registers)
1767 : {
1768 : u32 val;
1769 :
1770 0 : WREG32(MC_ARB_DRAM_TIMING, arb_registers->mc_arb_dram_timing);
1771 0 : WREG32(MC_ARB_DRAM_TIMING2, arb_registers->mc_arb_dram_timing2);
1772 :
1773 0 : val = (arb_registers->mc_arb_rfsh_rate & POWERMODE0_MASK) >>
1774 : POWERMODE0_SHIFT;
1775 0 : WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);
1776 :
1777 0 : val = (arb_registers->mc_arb_burst_time & STATE0_MASK) >>
1778 : STATE0_SHIFT;
1779 0 : WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);
1780 0 : }
1781 :
1782 0 : static void btc_set_boot_state_timing(struct radeon_device *rdev)
1783 : {
1784 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1785 :
1786 0 : if (eg_pi->ulv.supported)
1787 0 : btc_set_arb0_registers(rdev, &eg_pi->bootup_arb_registers);
1788 0 : }
1789 :
1790 0 : static bool btc_is_state_ulv_compatible(struct radeon_device *rdev,
1791 : struct radeon_ps *radeon_state)
1792 : {
1793 0 : struct rv7xx_ps *state = rv770_get_ps(radeon_state);
1794 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1795 0 : struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl;
1796 :
1797 0 : if (state->low.mclk != ulv_pl->mclk)
1798 0 : return false;
1799 :
1800 0 : if (state->low.vddci != ulv_pl->vddci)
1801 0 : return false;
1802 :
1803 : /* XXX check minclocks, etc. */
1804 :
1805 0 : return true;
1806 0 : }
1807 :
1808 :
1809 0 : static int btc_set_ulv_dram_timing(struct radeon_device *rdev)
1810 : {
1811 : u32 val;
1812 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1813 0 : struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl;
1814 :
1815 0 : radeon_atom_set_engine_dram_timings(rdev,
1816 0 : ulv_pl->sclk,
1817 0 : ulv_pl->mclk);
1818 :
1819 0 : val = rv770_calculate_memory_refresh_rate(rdev, ulv_pl->sclk);
1820 0 : WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK);
1821 :
1822 0 : val = cypress_calculate_burst_time(rdev, ulv_pl->sclk, ulv_pl->mclk);
1823 0 : WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK);
1824 :
1825 0 : return 0;
1826 : }
1827 :
1828 0 : static int btc_enable_ulv(struct radeon_device *rdev)
1829 : {
1830 0 : if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) != PPSMC_Result_OK)
1831 0 : return -EINVAL;
1832 :
1833 0 : return 0;
1834 0 : }
1835 :
1836 0 : static int btc_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
1837 : struct radeon_ps *radeon_new_state)
1838 : {
1839 : int ret = 0;
1840 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1841 :
1842 0 : if (eg_pi->ulv.supported) {
1843 0 : if (btc_is_state_ulv_compatible(rdev, radeon_new_state)) {
1844 : // Set ARB[0] to reflect the DRAM timing needed for ULV.
1845 0 : ret = btc_set_ulv_dram_timing(rdev);
1846 0 : if (ret == 0)
1847 0 : ret = btc_enable_ulv(rdev);
1848 : }
1849 : }
1850 :
1851 0 : return ret;
1852 : }
1853 :
1854 0 : static bool btc_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
1855 : {
1856 : bool result = true;
1857 :
1858 0 : switch (in_reg) {
1859 : case MC_SEQ_RAS_TIMING >> 2:
1860 0 : *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
1861 0 : break;
1862 : case MC_SEQ_CAS_TIMING >> 2:
1863 0 : *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
1864 0 : break;
1865 : case MC_SEQ_MISC_TIMING >> 2:
1866 0 : *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
1867 0 : break;
1868 : case MC_SEQ_MISC_TIMING2 >> 2:
1869 0 : *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
1870 0 : break;
1871 : case MC_SEQ_RD_CTL_D0 >> 2:
1872 0 : *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
1873 0 : break;
1874 : case MC_SEQ_RD_CTL_D1 >> 2:
1875 0 : *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
1876 0 : break;
1877 : case MC_SEQ_WR_CTL_D0 >> 2:
1878 0 : *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
1879 0 : break;
1880 : case MC_SEQ_WR_CTL_D1 >> 2:
1881 0 : *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
1882 0 : break;
1883 : case MC_PMG_CMD_EMRS >> 2:
1884 0 : *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1885 0 : break;
1886 : case MC_PMG_CMD_MRS >> 2:
1887 0 : *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1888 0 : break;
1889 : case MC_PMG_CMD_MRS1 >> 2:
1890 0 : *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1891 0 : break;
1892 : default:
1893 : result = false;
1894 0 : break;
1895 : }
1896 :
1897 0 : return result;
1898 : }
1899 :
1900 0 : static void btc_set_valid_flag(struct evergreen_mc_reg_table *table)
1901 : {
1902 : u8 i, j;
1903 :
1904 0 : for (i = 0; i < table->last; i++) {
1905 0 : for (j = 1; j < table->num_entries; j++) {
1906 0 : if (table->mc_reg_table_entry[j-1].mc_data[i] !=
1907 0 : table->mc_reg_table_entry[j].mc_data[i]) {
1908 0 : table->valid_flag |= (1 << i);
1909 0 : break;
1910 : }
1911 : }
1912 : }
1913 0 : }
1914 :
1915 0 : static int btc_set_mc_special_registers(struct radeon_device *rdev,
1916 : struct evergreen_mc_reg_table *table)
1917 : {
1918 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1919 : u8 i, j, k;
1920 : u32 tmp;
1921 :
1922 0 : for (i = 0, j = table->last; i < table->last; i++) {
1923 0 : switch (table->mc_reg_address[i].s1) {
1924 : case MC_SEQ_MISC1 >> 2:
1925 0 : tmp = RREG32(MC_PMG_CMD_EMRS);
1926 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
1927 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
1928 0 : for (k = 0; k < table->num_entries; k++) {
1929 0 : table->mc_reg_table_entry[k].mc_data[j] =
1930 0 : ((tmp & 0xffff0000)) |
1931 0 : ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
1932 : }
1933 0 : j++;
1934 :
1935 0 : if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1936 0 : return -EINVAL;
1937 :
1938 0 : tmp = RREG32(MC_PMG_CMD_MRS);
1939 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
1940 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
1941 0 : for (k = 0; k < table->num_entries; k++) {
1942 0 : table->mc_reg_table_entry[k].mc_data[j] =
1943 0 : (tmp & 0xffff0000) |
1944 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
1945 0 : if (!pi->mem_gddr5)
1946 0 : table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
1947 : }
1948 0 : j++;
1949 :
1950 0 : if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1951 0 : return -EINVAL;
1952 : break;
1953 : case MC_SEQ_RESERVE_M >> 2:
1954 0 : tmp = RREG32(MC_PMG_CMD_MRS1);
1955 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
1956 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
1957 0 : for (k = 0; k < table->num_entries; k++) {
1958 0 : table->mc_reg_table_entry[k].mc_data[j] =
1959 0 : (tmp & 0xffff0000) |
1960 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
1961 : }
1962 0 : j++;
1963 :
1964 0 : if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1965 0 : return -EINVAL;
1966 : break;
1967 : default:
1968 : break;
1969 : }
1970 : }
1971 :
1972 0 : table->last = j;
1973 :
1974 0 : return 0;
1975 0 : }
1976 :
1977 0 : static void btc_set_s0_mc_reg_index(struct evergreen_mc_reg_table *table)
1978 : {
1979 : u32 i;
1980 0 : u16 address;
1981 :
1982 0 : for (i = 0; i < table->last; i++) {
1983 0 : table->mc_reg_address[i].s0 =
1984 0 : btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
1985 0 : address : table->mc_reg_address[i].s1;
1986 : }
1987 0 : }
1988 :
1989 0 : static int btc_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
1990 : struct evergreen_mc_reg_table *eg_table)
1991 : {
1992 : u8 i, j;
1993 :
1994 0 : if (table->last > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1995 0 : return -EINVAL;
1996 :
1997 0 : if (table->num_entries > MAX_AC_TIMING_ENTRIES)
1998 0 : return -EINVAL;
1999 :
2000 0 : for (i = 0; i < table->last; i++)
2001 0 : eg_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2002 0 : eg_table->last = table->last;
2003 :
2004 0 : for (i = 0; i < table->num_entries; i++) {
2005 0 : eg_table->mc_reg_table_entry[i].mclk_max =
2006 0 : table->mc_reg_table_entry[i].mclk_max;
2007 0 : for(j = 0; j < table->last; j++)
2008 0 : eg_table->mc_reg_table_entry[i].mc_data[j] =
2009 0 : table->mc_reg_table_entry[i].mc_data[j];
2010 : }
2011 0 : eg_table->num_entries = table->num_entries;
2012 :
2013 0 : return 0;
2014 0 : }
2015 :
2016 0 : static int btc_initialize_mc_reg_table(struct radeon_device *rdev)
2017 : {
2018 : int ret;
2019 : struct atom_mc_reg_table *table;
2020 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2021 0 : struct evergreen_mc_reg_table *eg_table = &eg_pi->mc_reg_table;
2022 0 : u8 module_index = rv770_get_memory_module_index(rdev);
2023 :
2024 0 : table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
2025 0 : if (!table)
2026 0 : return -ENOMEM;
2027 :
2028 : /* Program additional LP registers that are no longer programmed by VBIOS */
2029 0 : WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
2030 0 : WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
2031 0 : WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
2032 0 : WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
2033 0 : WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
2034 0 : WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
2035 0 : WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
2036 0 : WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
2037 0 : WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
2038 0 : WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
2039 0 : WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
2040 :
2041 0 : ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2042 :
2043 0 : if (ret)
2044 : goto init_mc_done;
2045 :
2046 0 : ret = btc_copy_vbios_mc_reg_table(table, eg_table);
2047 :
2048 0 : if (ret)
2049 : goto init_mc_done;
2050 :
2051 0 : btc_set_s0_mc_reg_index(eg_table);
2052 0 : ret = btc_set_mc_special_registers(rdev, eg_table);
2053 :
2054 0 : if (ret)
2055 : goto init_mc_done;
2056 :
2057 0 : btc_set_valid_flag(eg_table);
2058 :
2059 : init_mc_done:
2060 0 : kfree(table);
2061 :
2062 0 : return ret;
2063 0 : }
2064 :
2065 0 : static void btc_init_stutter_mode(struct radeon_device *rdev)
2066 : {
2067 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2068 : u32 tmp;
2069 :
2070 0 : if (pi->mclk_stutter_mode_threshold) {
2071 0 : if (pi->mem_gddr5) {
2072 0 : tmp = RREG32(MC_PMG_AUTO_CFG);
2073 0 : if ((0x200 & tmp) == 0) {
2074 0 : tmp = (tmp & 0xfffffc0b) | 0x204;
2075 0 : WREG32(MC_PMG_AUTO_CFG, tmp);
2076 0 : }
2077 : }
2078 : }
2079 0 : }
2080 :
2081 0 : bool btc_dpm_vblank_too_short(struct radeon_device *rdev)
2082 : {
2083 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2084 0 : u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2085 0 : u32 switch_limit = pi->mem_gddr5 ? 450 : 100;
2086 :
2087 0 : if (vblank_time < switch_limit)
2088 0 : return true;
2089 : else
2090 0 : return false;
2091 :
2092 0 : }
2093 :
2094 0 : static void btc_apply_state_adjust_rules(struct radeon_device *rdev,
2095 : struct radeon_ps *rps)
2096 : {
2097 0 : struct rv7xx_ps *ps = rv770_get_ps(rps);
2098 : struct radeon_clock_and_voltage_limits *max_limits;
2099 : bool disable_mclk_switching;
2100 : u32 mclk, sclk;
2101 : u16 vddc, vddci;
2102 :
2103 0 : if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2104 0 : btc_dpm_vblank_too_short(rdev))
2105 0 : disable_mclk_switching = true;
2106 : else
2107 : disable_mclk_switching = false;
2108 :
2109 0 : if (rdev->pm.dpm.ac_power)
2110 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2111 : else
2112 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2113 :
2114 0 : if (rdev->pm.dpm.ac_power == false) {
2115 0 : if (ps->high.mclk > max_limits->mclk)
2116 0 : ps->high.mclk = max_limits->mclk;
2117 0 : if (ps->high.sclk > max_limits->sclk)
2118 0 : ps->high.sclk = max_limits->sclk;
2119 0 : if (ps->high.vddc > max_limits->vddc)
2120 0 : ps->high.vddc = max_limits->vddc;
2121 0 : if (ps->high.vddci > max_limits->vddci)
2122 0 : ps->high.vddci = max_limits->vddci;
2123 :
2124 0 : if (ps->medium.mclk > max_limits->mclk)
2125 0 : ps->medium.mclk = max_limits->mclk;
2126 0 : if (ps->medium.sclk > max_limits->sclk)
2127 0 : ps->medium.sclk = max_limits->sclk;
2128 0 : if (ps->medium.vddc > max_limits->vddc)
2129 0 : ps->medium.vddc = max_limits->vddc;
2130 0 : if (ps->medium.vddci > max_limits->vddci)
2131 0 : ps->medium.vddci = max_limits->vddci;
2132 :
2133 0 : if (ps->low.mclk > max_limits->mclk)
2134 0 : ps->low.mclk = max_limits->mclk;
2135 0 : if (ps->low.sclk > max_limits->sclk)
2136 0 : ps->low.sclk = max_limits->sclk;
2137 0 : if (ps->low.vddc > max_limits->vddc)
2138 0 : ps->low.vddc = max_limits->vddc;
2139 0 : if (ps->low.vddci > max_limits->vddci)
2140 0 : ps->low.vddci = max_limits->vddci;
2141 : }
2142 :
2143 : /* XXX validate the min clocks required for display */
2144 :
2145 0 : if (disable_mclk_switching) {
2146 : sclk = ps->low.sclk;
2147 0 : mclk = ps->high.mclk;
2148 0 : vddc = ps->low.vddc;
2149 0 : vddci = ps->high.vddci;
2150 0 : } else {
2151 : sclk = ps->low.sclk;
2152 0 : mclk = ps->low.mclk;
2153 0 : vddc = ps->low.vddc;
2154 0 : vddci = ps->low.vddci;
2155 : }
2156 :
2157 : /* adjusted low state */
2158 0 : ps->low.sclk = sclk;
2159 0 : ps->low.mclk = mclk;
2160 0 : ps->low.vddc = vddc;
2161 0 : ps->low.vddci = vddci;
2162 :
2163 0 : btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2164 : &ps->low.sclk, &ps->low.mclk);
2165 :
2166 : /* adjusted medium, high states */
2167 0 : if (ps->medium.sclk < ps->low.sclk)
2168 0 : ps->medium.sclk = ps->low.sclk;
2169 0 : if (ps->medium.vddc < ps->low.vddc)
2170 0 : ps->medium.vddc = ps->low.vddc;
2171 0 : if (ps->high.sclk < ps->medium.sclk)
2172 0 : ps->high.sclk = ps->medium.sclk;
2173 0 : if (ps->high.vddc < ps->medium.vddc)
2174 0 : ps->high.vddc = ps->medium.vddc;
2175 :
2176 0 : if (disable_mclk_switching) {
2177 0 : mclk = ps->low.mclk;
2178 0 : if (mclk < ps->medium.mclk)
2179 0 : mclk = ps->medium.mclk;
2180 0 : if (mclk < ps->high.mclk)
2181 0 : mclk = ps->high.mclk;
2182 0 : ps->low.mclk = mclk;
2183 0 : ps->low.vddci = vddci;
2184 0 : ps->medium.mclk = mclk;
2185 0 : ps->medium.vddci = vddci;
2186 0 : ps->high.mclk = mclk;
2187 0 : ps->high.vddci = vddci;
2188 0 : } else {
2189 0 : if (ps->medium.mclk < ps->low.mclk)
2190 0 : ps->medium.mclk = ps->low.mclk;
2191 0 : if (ps->medium.vddci < ps->low.vddci)
2192 0 : ps->medium.vddci = ps->low.vddci;
2193 0 : if (ps->high.mclk < ps->medium.mclk)
2194 0 : ps->high.mclk = ps->medium.mclk;
2195 0 : if (ps->high.vddci < ps->medium.vddci)
2196 0 : ps->high.vddci = ps->medium.vddci;
2197 : }
2198 :
2199 0 : btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2200 0 : &ps->medium.sclk, &ps->medium.mclk);
2201 0 : btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
2202 0 : &ps->high.sclk, &ps->high.mclk);
2203 :
2204 0 : btc_adjust_clock_combinations(rdev, max_limits, &ps->low);
2205 0 : btc_adjust_clock_combinations(rdev, max_limits, &ps->medium);
2206 0 : btc_adjust_clock_combinations(rdev, max_limits, &ps->high);
2207 :
2208 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2209 0 : ps->low.sclk, max_limits->vddc, &ps->low.vddc);
2210 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2211 0 : ps->low.mclk, max_limits->vddci, &ps->low.vddci);
2212 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2213 0 : ps->low.mclk, max_limits->vddc, &ps->low.vddc);
2214 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2215 0 : rdev->clock.current_dispclk, max_limits->vddc, &ps->low.vddc);
2216 :
2217 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2218 0 : ps->medium.sclk, max_limits->vddc, &ps->medium.vddc);
2219 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2220 0 : ps->medium.mclk, max_limits->vddci, &ps->medium.vddci);
2221 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2222 0 : ps->medium.mclk, max_limits->vddc, &ps->medium.vddc);
2223 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2224 0 : rdev->clock.current_dispclk, max_limits->vddc, &ps->medium.vddc);
2225 :
2226 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2227 0 : ps->high.sclk, max_limits->vddc, &ps->high.vddc);
2228 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2229 0 : ps->high.mclk, max_limits->vddci, &ps->high.vddci);
2230 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2231 0 : ps->high.mclk, max_limits->vddc, &ps->high.vddc);
2232 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2233 0 : rdev->clock.current_dispclk, max_limits->vddc, &ps->high.vddc);
2234 :
2235 0 : btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2236 : &ps->low.vddc, &ps->low.vddci);
2237 0 : btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2238 : &ps->medium.vddc, &ps->medium.vddci);
2239 0 : btc_apply_voltage_delta_rules(rdev, max_limits->vddc, max_limits->vddci,
2240 : &ps->high.vddc, &ps->high.vddci);
2241 :
2242 0 : if ((ps->high.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) &&
2243 0 : (ps->medium.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) &&
2244 0 : (ps->low.vddc <= rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc))
2245 0 : ps->dc_compatible = true;
2246 : else
2247 0 : ps->dc_compatible = false;
2248 :
2249 0 : if (ps->low.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2250 0 : ps->low.flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
2251 0 : if (ps->medium.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2252 0 : ps->medium.flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
2253 0 : if (ps->high.vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
2254 0 : ps->high.flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
2255 0 : }
2256 :
2257 0 : static void btc_update_current_ps(struct radeon_device *rdev,
2258 : struct radeon_ps *rps)
2259 : {
2260 0 : struct rv7xx_ps *new_ps = rv770_get_ps(rps);
2261 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2262 :
2263 0 : eg_pi->current_rps = *rps;
2264 0 : eg_pi->current_ps = *new_ps;
2265 0 : eg_pi->current_rps.ps_priv = &eg_pi->current_ps;
2266 0 : }
2267 :
2268 0 : static void btc_update_requested_ps(struct radeon_device *rdev,
2269 : struct radeon_ps *rps)
2270 : {
2271 0 : struct rv7xx_ps *new_ps = rv770_get_ps(rps);
2272 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2273 :
2274 0 : eg_pi->requested_rps = *rps;
2275 0 : eg_pi->requested_ps = *new_ps;
2276 0 : eg_pi->requested_rps.ps_priv = &eg_pi->requested_ps;
2277 0 : }
2278 :
2279 : #if 0
2280 : void btc_dpm_reset_asic(struct radeon_device *rdev)
2281 : {
2282 : rv770_restrict_performance_levels_before_switch(rdev);
2283 : btc_disable_ulv(rdev);
2284 : btc_set_boot_state_timing(rdev);
2285 : rv770_set_boot_state(rdev);
2286 : }
2287 : #endif
2288 :
2289 0 : int btc_dpm_pre_set_power_state(struct radeon_device *rdev)
2290 : {
2291 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2292 0 : struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
2293 : struct radeon_ps *new_ps = &requested_ps;
2294 :
2295 0 : btc_update_requested_ps(rdev, new_ps);
2296 :
2297 0 : btc_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
2298 :
2299 0 : return 0;
2300 0 : }
2301 :
2302 0 : int btc_dpm_set_power_state(struct radeon_device *rdev)
2303 : {
2304 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2305 0 : struct radeon_ps *new_ps = &eg_pi->requested_rps;
2306 0 : struct radeon_ps *old_ps = &eg_pi->current_rps;
2307 : int ret;
2308 :
2309 0 : ret = btc_disable_ulv(rdev);
2310 0 : btc_set_boot_state_timing(rdev);
2311 0 : ret = rv770_restrict_performance_levels_before_switch(rdev);
2312 0 : if (ret) {
2313 0 : DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n");
2314 0 : return ret;
2315 : }
2316 0 : if (eg_pi->pcie_performance_request)
2317 0 : cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps);
2318 :
2319 0 : rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
2320 0 : ret = rv770_halt_smc(rdev);
2321 0 : if (ret) {
2322 0 : DRM_ERROR("rv770_halt_smc failed\n");
2323 0 : return ret;
2324 : }
2325 0 : btc_set_at_for_uvd(rdev, new_ps);
2326 0 : if (eg_pi->smu_uvd_hs)
2327 0 : btc_notify_uvd_to_smc(rdev, new_ps);
2328 0 : ret = cypress_upload_sw_state(rdev, new_ps);
2329 0 : if (ret) {
2330 0 : DRM_ERROR("cypress_upload_sw_state failed\n");
2331 0 : return ret;
2332 : }
2333 0 : if (eg_pi->dynamic_ac_timing) {
2334 0 : ret = cypress_upload_mc_reg_table(rdev, new_ps);
2335 0 : if (ret) {
2336 0 : DRM_ERROR("cypress_upload_mc_reg_table failed\n");
2337 0 : return ret;
2338 : }
2339 : }
2340 :
2341 0 : cypress_program_memory_timing_parameters(rdev, new_ps);
2342 :
2343 0 : ret = rv770_resume_smc(rdev);
2344 0 : if (ret) {
2345 0 : DRM_ERROR("rv770_resume_smc failed\n");
2346 0 : return ret;
2347 : }
2348 0 : ret = rv770_set_sw_state(rdev);
2349 0 : if (ret) {
2350 0 : DRM_ERROR("rv770_set_sw_state failed\n");
2351 0 : return ret;
2352 : }
2353 0 : rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2354 :
2355 0 : if (eg_pi->pcie_performance_request)
2356 0 : cypress_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
2357 :
2358 0 : ret = btc_set_power_state_conditionally_enable_ulv(rdev, new_ps);
2359 0 : if (ret) {
2360 0 : DRM_ERROR("btc_set_power_state_conditionally_enable_ulv failed\n");
2361 0 : return ret;
2362 : }
2363 :
2364 0 : return 0;
2365 0 : }
2366 :
2367 0 : void btc_dpm_post_set_power_state(struct radeon_device *rdev)
2368 : {
2369 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2370 0 : struct radeon_ps *new_ps = &eg_pi->requested_rps;
2371 :
2372 0 : btc_update_current_ps(rdev, new_ps);
2373 0 : }
2374 :
2375 0 : int btc_dpm_enable(struct radeon_device *rdev)
2376 : {
2377 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2378 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2379 0 : struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
2380 : int ret;
2381 :
2382 0 : if (pi->gfx_clock_gating)
2383 0 : btc_cg_clock_gating_default(rdev);
2384 :
2385 0 : if (btc_dpm_enabled(rdev))
2386 0 : return -EINVAL;
2387 :
2388 0 : if (pi->mg_clock_gating)
2389 0 : btc_mg_clock_gating_default(rdev);
2390 :
2391 0 : if (eg_pi->ls_clock_gating)
2392 0 : btc_ls_clock_gating_default(rdev);
2393 :
2394 0 : if (pi->voltage_control) {
2395 0 : rv770_enable_voltage_control(rdev, true);
2396 0 : ret = cypress_construct_voltage_tables(rdev);
2397 0 : if (ret) {
2398 0 : DRM_ERROR("cypress_construct_voltage_tables failed\n");
2399 0 : return ret;
2400 : }
2401 : }
2402 :
2403 0 : if (pi->mvdd_control) {
2404 0 : ret = cypress_get_mvdd_configuration(rdev);
2405 0 : if (ret) {
2406 0 : DRM_ERROR("cypress_get_mvdd_configuration failed\n");
2407 0 : return ret;
2408 : }
2409 : }
2410 :
2411 0 : if (eg_pi->dynamic_ac_timing) {
2412 0 : ret = btc_initialize_mc_reg_table(rdev);
2413 0 : if (ret)
2414 0 : eg_pi->dynamic_ac_timing = false;
2415 : }
2416 :
2417 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
2418 0 : rv770_enable_backbias(rdev, true);
2419 :
2420 0 : if (pi->dynamic_ss)
2421 0 : cypress_enable_spread_spectrum(rdev, true);
2422 :
2423 0 : if (pi->thermal_protection)
2424 0 : rv770_enable_thermal_protection(rdev, true);
2425 :
2426 0 : rv770_setup_bsp(rdev);
2427 0 : rv770_program_git(rdev);
2428 0 : rv770_program_tp(rdev);
2429 0 : rv770_program_tpp(rdev);
2430 0 : rv770_program_sstp(rdev);
2431 0 : rv770_program_engine_speed_parameters(rdev);
2432 0 : cypress_enable_display_gap(rdev);
2433 0 : rv770_program_vc(rdev);
2434 :
2435 0 : if (pi->dynamic_pcie_gen2)
2436 0 : btc_enable_dynamic_pcie_gen2(rdev, true);
2437 :
2438 0 : ret = rv770_upload_firmware(rdev);
2439 0 : if (ret) {
2440 0 : DRM_ERROR("rv770_upload_firmware failed\n");
2441 0 : return ret;
2442 : }
2443 0 : ret = cypress_get_table_locations(rdev);
2444 0 : if (ret) {
2445 0 : DRM_ERROR("cypress_get_table_locations failed\n");
2446 0 : return ret;
2447 : }
2448 0 : ret = btc_init_smc_table(rdev, boot_ps);
2449 0 : if (ret)
2450 0 : return ret;
2451 :
2452 0 : if (eg_pi->dynamic_ac_timing) {
2453 0 : ret = cypress_populate_mc_reg_table(rdev, boot_ps);
2454 0 : if (ret) {
2455 0 : DRM_ERROR("cypress_populate_mc_reg_table failed\n");
2456 0 : return ret;
2457 : }
2458 : }
2459 :
2460 0 : cypress_program_response_times(rdev);
2461 0 : r7xx_start_smc(rdev);
2462 0 : ret = cypress_notify_smc_display_change(rdev, false);
2463 0 : if (ret) {
2464 0 : DRM_ERROR("cypress_notify_smc_display_change failed\n");
2465 0 : return ret;
2466 : }
2467 0 : cypress_enable_sclk_control(rdev, true);
2468 :
2469 0 : if (eg_pi->memory_transition)
2470 0 : cypress_enable_mclk_control(rdev, true);
2471 :
2472 0 : cypress_start_dpm(rdev);
2473 :
2474 0 : if (pi->gfx_clock_gating)
2475 0 : btc_cg_clock_gating_enable(rdev, true);
2476 :
2477 0 : if (pi->mg_clock_gating)
2478 0 : btc_mg_clock_gating_enable(rdev, true);
2479 :
2480 0 : if (eg_pi->ls_clock_gating)
2481 0 : btc_ls_clock_gating_enable(rdev, true);
2482 :
2483 0 : rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
2484 :
2485 0 : btc_init_stutter_mode(rdev);
2486 :
2487 0 : btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
2488 :
2489 0 : return 0;
2490 0 : };
2491 :
2492 0 : void btc_dpm_disable(struct radeon_device *rdev)
2493 : {
2494 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2495 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2496 :
2497 0 : if (!btc_dpm_enabled(rdev))
2498 0 : return;
2499 :
2500 0 : rv770_clear_vc(rdev);
2501 :
2502 0 : if (pi->thermal_protection)
2503 0 : rv770_enable_thermal_protection(rdev, false);
2504 :
2505 0 : if (pi->dynamic_pcie_gen2)
2506 0 : btc_enable_dynamic_pcie_gen2(rdev, false);
2507 :
2508 0 : if (rdev->irq.installed &&
2509 0 : r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
2510 0 : rdev->irq.dpm_thermal = false;
2511 0 : radeon_irq_set(rdev);
2512 0 : }
2513 :
2514 0 : if (pi->gfx_clock_gating)
2515 0 : btc_cg_clock_gating_enable(rdev, false);
2516 :
2517 0 : if (pi->mg_clock_gating)
2518 0 : btc_mg_clock_gating_enable(rdev, false);
2519 :
2520 0 : if (eg_pi->ls_clock_gating)
2521 0 : btc_ls_clock_gating_enable(rdev, false);
2522 :
2523 0 : rv770_stop_dpm(rdev);
2524 0 : btc_reset_to_default(rdev);
2525 0 : btc_stop_smc(rdev);
2526 0 : cypress_enable_spread_spectrum(rdev, false);
2527 :
2528 0 : btc_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
2529 0 : }
2530 :
2531 0 : void btc_dpm_setup_asic(struct radeon_device *rdev)
2532 : {
2533 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2534 : int r;
2535 :
2536 0 : r = ni_mc_load_microcode(rdev);
2537 0 : if (r)
2538 0 : DRM_ERROR("Failed to load MC firmware!\n");
2539 0 : rv770_get_memory_type(rdev);
2540 0 : rv740_read_clock_registers(rdev);
2541 0 : btc_read_arb_registers(rdev);
2542 0 : rv770_read_voltage_smio_registers(rdev);
2543 :
2544 0 : if (eg_pi->pcie_performance_request)
2545 0 : cypress_advertise_gen2_capability(rdev);
2546 :
2547 0 : rv770_get_pcie_gen2_status(rdev);
2548 0 : rv770_enable_acpi_pm(rdev);
2549 0 : }
2550 :
2551 0 : int btc_dpm_init(struct radeon_device *rdev)
2552 : {
2553 : struct rv7xx_power_info *pi;
2554 : struct evergreen_power_info *eg_pi;
2555 0 : struct atom_clock_dividers dividers;
2556 : int ret;
2557 :
2558 0 : eg_pi = kzalloc(sizeof(struct evergreen_power_info), GFP_KERNEL);
2559 0 : if (eg_pi == NULL)
2560 0 : return -ENOMEM;
2561 0 : rdev->pm.dpm.priv = eg_pi;
2562 0 : pi = &eg_pi->rv7xx;
2563 :
2564 0 : rv770_get_max_vddc(rdev);
2565 :
2566 0 : eg_pi->ulv.supported = false;
2567 0 : pi->acpi_vddc = 0;
2568 0 : eg_pi->acpi_vddci = 0;
2569 0 : pi->min_vddc_in_table = 0;
2570 0 : pi->max_vddc_in_table = 0;
2571 :
2572 0 : ret = r600_get_platform_caps(rdev);
2573 0 : if (ret)
2574 0 : return ret;
2575 :
2576 0 : ret = rv7xx_parse_power_table(rdev);
2577 0 : if (ret)
2578 0 : return ret;
2579 0 : ret = r600_parse_extended_power_table(rdev);
2580 0 : if (ret)
2581 0 : return ret;
2582 :
2583 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
2584 0 : kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
2585 0 : if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
2586 0 : r600_free_extended_power_table(rdev);
2587 0 : return -ENOMEM;
2588 : }
2589 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
2590 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
2591 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
2592 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
2593 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 800;
2594 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
2595 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 800;
2596 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
2597 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 800;
2598 :
2599 0 : if (rdev->pm.dpm.voltage_response_time == 0)
2600 0 : rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2601 0 : if (rdev->pm.dpm.backbias_response_time == 0)
2602 0 : rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2603 :
2604 0 : ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2605 : 0, false, ÷rs);
2606 0 : if (ret)
2607 0 : pi->ref_div = dividers.ref_div + 1;
2608 : else
2609 0 : pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
2610 :
2611 0 : pi->mclk_strobe_mode_threshold = 40000;
2612 0 : pi->mclk_edc_enable_threshold = 40000;
2613 0 : eg_pi->mclk_edc_wr_enable_threshold = 40000;
2614 :
2615 0 : pi->rlp = RV770_RLP_DFLT;
2616 0 : pi->rmp = RV770_RMP_DFLT;
2617 0 : pi->lhp = RV770_LHP_DFLT;
2618 0 : pi->lmp = RV770_LMP_DFLT;
2619 :
2620 0 : eg_pi->ats[0].rlp = RV770_RLP_DFLT;
2621 0 : eg_pi->ats[0].rmp = RV770_RMP_DFLT;
2622 0 : eg_pi->ats[0].lhp = RV770_LHP_DFLT;
2623 0 : eg_pi->ats[0].lmp = RV770_LMP_DFLT;
2624 :
2625 0 : eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT;
2626 0 : eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT;
2627 0 : eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT;
2628 0 : eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT;
2629 :
2630 0 : eg_pi->smu_uvd_hs = true;
2631 :
2632 0 : pi->voltage_control =
2633 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
2634 :
2635 0 : pi->mvdd_control =
2636 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2637 :
2638 0 : eg_pi->vddci_control =
2639 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
2640 :
2641 0 : rv770_get_engine_memory_ss(rdev);
2642 :
2643 0 : pi->asi = RV770_ASI_DFLT;
2644 0 : pi->pasi = CYPRESS_HASI_DFLT;
2645 0 : pi->vrc = CYPRESS_VRC_DFLT;
2646 :
2647 0 : pi->power_gating = false;
2648 :
2649 0 : pi->gfx_clock_gating = true;
2650 :
2651 0 : pi->mg_clock_gating = true;
2652 0 : pi->mgcgtssm = true;
2653 0 : eg_pi->ls_clock_gating = false;
2654 0 : eg_pi->sclk_deep_sleep = false;
2655 :
2656 0 : pi->dynamic_pcie_gen2 = true;
2657 :
2658 0 : if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
2659 0 : pi->thermal_protection = true;
2660 : else
2661 0 : pi->thermal_protection = false;
2662 :
2663 0 : pi->display_gap = true;
2664 :
2665 0 : if (rdev->flags & RADEON_IS_MOBILITY)
2666 0 : pi->dcodt = true;
2667 : else
2668 0 : pi->dcodt = false;
2669 :
2670 0 : pi->ulps = true;
2671 :
2672 0 : eg_pi->dynamic_ac_timing = true;
2673 0 : eg_pi->abm = true;
2674 0 : eg_pi->mcls = true;
2675 0 : eg_pi->light_sleep = true;
2676 0 : eg_pi->memory_transition = true;
2677 : #if defined(CONFIG_ACPI)
2678 : eg_pi->pcie_performance_request =
2679 : radeon_acpi_is_pcie_performance_request_supported(rdev);
2680 : #else
2681 0 : eg_pi->pcie_performance_request = false;
2682 : #endif
2683 :
2684 0 : if (rdev->family == CHIP_BARTS)
2685 0 : eg_pi->dll_default_on = true;
2686 : else
2687 0 : eg_pi->dll_default_on = false;
2688 :
2689 0 : eg_pi->sclk_deep_sleep = false;
2690 0 : if (ASIC_IS_LOMBOK(rdev))
2691 0 : pi->mclk_stutter_mode_threshold = 30000;
2692 : else
2693 0 : pi->mclk_stutter_mode_threshold = 0;
2694 :
2695 0 : pi->sram_end = SMC_RAM_END;
2696 :
2697 0 : rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
2698 0 : rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
2699 0 : rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;
2700 0 : rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);
2701 0 : rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;
2702 0 : rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
2703 0 : rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
2704 :
2705 0 : if (rdev->family == CHIP_TURKS)
2706 0 : rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
2707 : else
2708 0 : rdev->pm.dpm.dyn_state.sclk_mclk_delta = 10000;
2709 :
2710 : /* make sure dc limits are valid */
2711 0 : if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
2712 0 : (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
2713 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
2714 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2715 :
2716 0 : return 0;
2717 0 : }
2718 :
2719 0 : void btc_dpm_fini(struct radeon_device *rdev)
2720 : {
2721 : int i;
2722 :
2723 0 : for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2724 0 : kfree(rdev->pm.dpm.ps[i].ps_priv);
2725 : }
2726 0 : kfree(rdev->pm.dpm.ps);
2727 0 : kfree(rdev->pm.dpm.priv);
2728 0 : kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
2729 0 : r600_free_extended_power_table(rdev);
2730 0 : }
2731 :
2732 0 : void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2733 : struct seq_file *m)
2734 : {
2735 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2736 0 : struct radeon_ps *rps = &eg_pi->current_rps;
2737 0 : struct rv7xx_ps *ps = rv770_get_ps(rps);
2738 : struct rv7xx_pl *pl;
2739 : u32 current_index =
2740 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2741 : CURRENT_PROFILE_INDEX_SHIFT;
2742 :
2743 0 : if (current_index > 2) {
2744 0 : seq_printf(m, "invalid dpm profile %d\n", current_index);
2745 0 : } else {
2746 0 : if (current_index == 0)
2747 0 : pl = &ps->low;
2748 0 : else if (current_index == 1)
2749 0 : pl = &ps->medium;
2750 : else /* current_index == 2 */
2751 0 : pl = &ps->high;
2752 0 : seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2753 0 : seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
2754 0 : current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
2755 : }
2756 0 : }
2757 :
2758 0 : u32 btc_dpm_get_current_sclk(struct radeon_device *rdev)
2759 : {
2760 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2761 0 : struct radeon_ps *rps = &eg_pi->current_rps;
2762 0 : struct rv7xx_ps *ps = rv770_get_ps(rps);
2763 : struct rv7xx_pl *pl;
2764 : u32 current_index =
2765 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2766 : CURRENT_PROFILE_INDEX_SHIFT;
2767 :
2768 0 : if (current_index > 2) {
2769 0 : return 0;
2770 : } else {
2771 0 : if (current_index == 0)
2772 0 : pl = &ps->low;
2773 0 : else if (current_index == 1)
2774 0 : pl = &ps->medium;
2775 : else /* current_index == 2 */
2776 0 : pl = &ps->high;
2777 0 : return pl->sclk;
2778 : }
2779 0 : }
2780 :
2781 0 : u32 btc_dpm_get_current_mclk(struct radeon_device *rdev)
2782 : {
2783 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2784 0 : struct radeon_ps *rps = &eg_pi->current_rps;
2785 0 : struct rv7xx_ps *ps = rv770_get_ps(rps);
2786 : struct rv7xx_pl *pl;
2787 : u32 current_index =
2788 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2789 : CURRENT_PROFILE_INDEX_SHIFT;
2790 :
2791 0 : if (current_index > 2) {
2792 0 : return 0;
2793 : } else {
2794 0 : if (current_index == 0)
2795 0 : pl = &ps->low;
2796 0 : else if (current_index == 1)
2797 0 : pl = &ps->medium;
2798 : else /* current_index == 2 */
2799 0 : pl = &ps->high;
2800 0 : return pl->mclk;
2801 : }
2802 0 : }
2803 :
2804 0 : u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low)
2805 : {
2806 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2807 0 : struct rv7xx_ps *requested_state = rv770_get_ps(&eg_pi->requested_rps);
2808 :
2809 0 : if (low)
2810 0 : return requested_state->low.sclk;
2811 : else
2812 0 : return requested_state->high.sclk;
2813 0 : }
2814 :
2815 0 : u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low)
2816 : {
2817 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2818 0 : struct rv7xx_ps *requested_state = rv770_get_ps(&eg_pi->requested_rps);
2819 :
2820 0 : if (low)
2821 0 : return requested_state->low.mclk;
2822 : else
2823 0 : return requested_state->high.mclk;
2824 0 : }
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