Line data Source code
1 : /*
2 : * Copyright 2012 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: Alex Deucher
23 : */
24 : #include <dev/pci/drm/drmP.h>
25 : #include "radeon.h"
26 : #include "radeon_asic.h"
27 : #include "radeon_audio.h"
28 : #include "cikd.h"
29 : #include "atom.h"
30 : #include "cik_blit_shaders.h"
31 : #include "radeon_ucode.h"
32 : #include "clearstate_ci.h"
33 : #include "radeon_kfd.h"
34 :
35 : MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
36 : MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
37 : MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
38 : MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
39 : MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
40 : MODULE_FIRMWARE("radeon/BONAIRE_mc2.bin");
41 : MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
42 : MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
43 : MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
44 :
45 : MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
46 : MODULE_FIRMWARE("radeon/bonaire_me.bin");
47 : MODULE_FIRMWARE("radeon/bonaire_ce.bin");
48 : MODULE_FIRMWARE("radeon/bonaire_mec.bin");
49 : MODULE_FIRMWARE("radeon/bonaire_mc.bin");
50 : MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
51 : MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
52 : MODULE_FIRMWARE("radeon/bonaire_smc.bin");
53 :
54 : MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
55 : MODULE_FIRMWARE("radeon/HAWAII_me.bin");
56 : MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
57 : MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
58 : MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
59 : MODULE_FIRMWARE("radeon/HAWAII_mc2.bin");
60 : MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
61 : MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
62 : MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
63 :
64 : MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
65 : MODULE_FIRMWARE("radeon/hawaii_me.bin");
66 : MODULE_FIRMWARE("radeon/hawaii_ce.bin");
67 : MODULE_FIRMWARE("radeon/hawaii_mec.bin");
68 : MODULE_FIRMWARE("radeon/hawaii_mc.bin");
69 : MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
70 : MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
71 : MODULE_FIRMWARE("radeon/hawaii_smc.bin");
72 :
73 : MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
74 : MODULE_FIRMWARE("radeon/KAVERI_me.bin");
75 : MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
76 : MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
77 : MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
78 : MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
79 :
80 : MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
81 : MODULE_FIRMWARE("radeon/kaveri_me.bin");
82 : MODULE_FIRMWARE("radeon/kaveri_ce.bin");
83 : MODULE_FIRMWARE("radeon/kaveri_mec.bin");
84 : MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
85 : MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
86 : MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
87 :
88 : MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
89 : MODULE_FIRMWARE("radeon/KABINI_me.bin");
90 : MODULE_FIRMWARE("radeon/KABINI_ce.bin");
91 : MODULE_FIRMWARE("radeon/KABINI_mec.bin");
92 : MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
93 : MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
94 :
95 : MODULE_FIRMWARE("radeon/kabini_pfp.bin");
96 : MODULE_FIRMWARE("radeon/kabini_me.bin");
97 : MODULE_FIRMWARE("radeon/kabini_ce.bin");
98 : MODULE_FIRMWARE("radeon/kabini_mec.bin");
99 : MODULE_FIRMWARE("radeon/kabini_rlc.bin");
100 : MODULE_FIRMWARE("radeon/kabini_sdma.bin");
101 :
102 : MODULE_FIRMWARE("radeon/MULLINS_pfp.bin");
103 : MODULE_FIRMWARE("radeon/MULLINS_me.bin");
104 : MODULE_FIRMWARE("radeon/MULLINS_ce.bin");
105 : MODULE_FIRMWARE("radeon/MULLINS_mec.bin");
106 : MODULE_FIRMWARE("radeon/MULLINS_rlc.bin");
107 : MODULE_FIRMWARE("radeon/MULLINS_sdma.bin");
108 :
109 : MODULE_FIRMWARE("radeon/mullins_pfp.bin");
110 : MODULE_FIRMWARE("radeon/mullins_me.bin");
111 : MODULE_FIRMWARE("radeon/mullins_ce.bin");
112 : MODULE_FIRMWARE("radeon/mullins_mec.bin");
113 : MODULE_FIRMWARE("radeon/mullins_rlc.bin");
114 : MODULE_FIRMWARE("radeon/mullins_sdma.bin");
115 :
116 : extern int r600_ih_ring_alloc(struct radeon_device *rdev);
117 : extern void r600_ih_ring_fini(struct radeon_device *rdev);
118 : extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
119 : extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
120 : extern bool evergreen_is_display_hung(struct radeon_device *rdev);
121 : extern void sumo_rlc_fini(struct radeon_device *rdev);
122 : extern int sumo_rlc_init(struct radeon_device *rdev);
123 : extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
124 : extern void si_rlc_reset(struct radeon_device *rdev);
125 : extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
126 : static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
127 : extern int cik_sdma_resume(struct radeon_device *rdev);
128 : extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
129 : extern void cik_sdma_fini(struct radeon_device *rdev);
130 : extern void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable);
131 : static void cik_rlc_stop(struct radeon_device *rdev);
132 : static void cik_pcie_gen3_enable(struct radeon_device *rdev);
133 : static void cik_program_aspm(struct radeon_device *rdev);
134 : static void cik_init_pg(struct radeon_device *rdev);
135 : static void cik_init_cg(struct radeon_device *rdev);
136 : static void cik_fini_pg(struct radeon_device *rdev);
137 : static void cik_fini_cg(struct radeon_device *rdev);
138 : static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
139 : bool enable);
140 :
141 : /**
142 : * cik_get_allowed_info_register - fetch the register for the info ioctl
143 : *
144 : * @rdev: radeon_device pointer
145 : * @reg: register offset in bytes
146 : * @val: register value
147 : *
148 : * Returns 0 for success or -EINVAL for an invalid register
149 : *
150 : */
151 0 : int cik_get_allowed_info_register(struct radeon_device *rdev,
152 : u32 reg, u32 *val)
153 : {
154 0 : switch (reg) {
155 : case GRBM_STATUS:
156 : case GRBM_STATUS2:
157 : case GRBM_STATUS_SE0:
158 : case GRBM_STATUS_SE1:
159 : case GRBM_STATUS_SE2:
160 : case GRBM_STATUS_SE3:
161 : case SRBM_STATUS:
162 : case SRBM_STATUS2:
163 : case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):
164 : case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):
165 : case UVD_STATUS:
166 : /* TODO VCE */
167 0 : *val = RREG32(reg);
168 0 : return 0;
169 : default:
170 0 : return -EINVAL;
171 : }
172 0 : }
173 :
174 : /*
175 : * Indirect registers accessor
176 : */
177 0 : u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
178 : {
179 : unsigned long flags;
180 : u32 r;
181 :
182 0 : spin_lock_irqsave(&rdev->didt_idx_lock, flags);
183 0 : WREG32(CIK_DIDT_IND_INDEX, (reg));
184 0 : r = RREG32(CIK_DIDT_IND_DATA);
185 0 : spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
186 0 : return r;
187 : }
188 :
189 0 : void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
190 : {
191 : unsigned long flags;
192 :
193 0 : spin_lock_irqsave(&rdev->didt_idx_lock, flags);
194 0 : WREG32(CIK_DIDT_IND_INDEX, (reg));
195 0 : WREG32(CIK_DIDT_IND_DATA, (v));
196 0 : spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
197 0 : }
198 :
199 : /* get temperature in millidegrees */
200 0 : int ci_get_temp(struct radeon_device *rdev)
201 : {
202 : u32 temp;
203 : int actual_temp = 0;
204 :
205 0 : temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
206 : CTF_TEMP_SHIFT;
207 :
208 0 : if (temp & 0x200)
209 0 : actual_temp = 255;
210 : else
211 0 : actual_temp = temp & 0x1ff;
212 :
213 0 : actual_temp = actual_temp * 1000;
214 :
215 0 : return actual_temp;
216 : }
217 :
218 : /* get temperature in millidegrees */
219 0 : int kv_get_temp(struct radeon_device *rdev)
220 : {
221 : u32 temp;
222 : int actual_temp = 0;
223 :
224 0 : temp = RREG32_SMC(0xC0300E0C);
225 :
226 0 : if (temp)
227 0 : actual_temp = (temp / 8) - 49;
228 : else
229 : actual_temp = 0;
230 :
231 0 : actual_temp = actual_temp * 1000;
232 :
233 0 : return actual_temp;
234 : }
235 :
236 : /*
237 : * Indirect registers accessor
238 : */
239 0 : u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
240 : {
241 : unsigned long flags;
242 : u32 r;
243 :
244 0 : spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
245 0 : WREG32(PCIE_INDEX, reg);
246 0 : (void)RREG32(PCIE_INDEX);
247 0 : r = RREG32(PCIE_DATA);
248 0 : spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
249 0 : return r;
250 : }
251 :
252 0 : void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
253 : {
254 : unsigned long flags;
255 :
256 0 : spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
257 0 : WREG32(PCIE_INDEX, reg);
258 0 : (void)RREG32(PCIE_INDEX);
259 0 : WREG32(PCIE_DATA, v);
260 0 : (void)RREG32(PCIE_DATA);
261 0 : spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
262 0 : }
263 :
264 : static const u32 spectre_rlc_save_restore_register_list[] =
265 : {
266 : (0x0e00 << 16) | (0xc12c >> 2),
267 : 0x00000000,
268 : (0x0e00 << 16) | (0xc140 >> 2),
269 : 0x00000000,
270 : (0x0e00 << 16) | (0xc150 >> 2),
271 : 0x00000000,
272 : (0x0e00 << 16) | (0xc15c >> 2),
273 : 0x00000000,
274 : (0x0e00 << 16) | (0xc168 >> 2),
275 : 0x00000000,
276 : (0x0e00 << 16) | (0xc170 >> 2),
277 : 0x00000000,
278 : (0x0e00 << 16) | (0xc178 >> 2),
279 : 0x00000000,
280 : (0x0e00 << 16) | (0xc204 >> 2),
281 : 0x00000000,
282 : (0x0e00 << 16) | (0xc2b4 >> 2),
283 : 0x00000000,
284 : (0x0e00 << 16) | (0xc2b8 >> 2),
285 : 0x00000000,
286 : (0x0e00 << 16) | (0xc2bc >> 2),
287 : 0x00000000,
288 : (0x0e00 << 16) | (0xc2c0 >> 2),
289 : 0x00000000,
290 : (0x0e00 << 16) | (0x8228 >> 2),
291 : 0x00000000,
292 : (0x0e00 << 16) | (0x829c >> 2),
293 : 0x00000000,
294 : (0x0e00 << 16) | (0x869c >> 2),
295 : 0x00000000,
296 : (0x0600 << 16) | (0x98f4 >> 2),
297 : 0x00000000,
298 : (0x0e00 << 16) | (0x98f8 >> 2),
299 : 0x00000000,
300 : (0x0e00 << 16) | (0x9900 >> 2),
301 : 0x00000000,
302 : (0x0e00 << 16) | (0xc260 >> 2),
303 : 0x00000000,
304 : (0x0e00 << 16) | (0x90e8 >> 2),
305 : 0x00000000,
306 : (0x0e00 << 16) | (0x3c000 >> 2),
307 : 0x00000000,
308 : (0x0e00 << 16) | (0x3c00c >> 2),
309 : 0x00000000,
310 : (0x0e00 << 16) | (0x8c1c >> 2),
311 : 0x00000000,
312 : (0x0e00 << 16) | (0x9700 >> 2),
313 : 0x00000000,
314 : (0x0e00 << 16) | (0xcd20 >> 2),
315 : 0x00000000,
316 : (0x4e00 << 16) | (0xcd20 >> 2),
317 : 0x00000000,
318 : (0x5e00 << 16) | (0xcd20 >> 2),
319 : 0x00000000,
320 : (0x6e00 << 16) | (0xcd20 >> 2),
321 : 0x00000000,
322 : (0x7e00 << 16) | (0xcd20 >> 2),
323 : 0x00000000,
324 : (0x8e00 << 16) | (0xcd20 >> 2),
325 : 0x00000000,
326 : (0x9e00 << 16) | (0xcd20 >> 2),
327 : 0x00000000,
328 : (0xae00 << 16) | (0xcd20 >> 2),
329 : 0x00000000,
330 : (0xbe00 << 16) | (0xcd20 >> 2),
331 : 0x00000000,
332 : (0x0e00 << 16) | (0x89bc >> 2),
333 : 0x00000000,
334 : (0x0e00 << 16) | (0x8900 >> 2),
335 : 0x00000000,
336 : 0x3,
337 : (0x0e00 << 16) | (0xc130 >> 2),
338 : 0x00000000,
339 : (0x0e00 << 16) | (0xc134 >> 2),
340 : 0x00000000,
341 : (0x0e00 << 16) | (0xc1fc >> 2),
342 : 0x00000000,
343 : (0x0e00 << 16) | (0xc208 >> 2),
344 : 0x00000000,
345 : (0x0e00 << 16) | (0xc264 >> 2),
346 : 0x00000000,
347 : (0x0e00 << 16) | (0xc268 >> 2),
348 : 0x00000000,
349 : (0x0e00 << 16) | (0xc26c >> 2),
350 : 0x00000000,
351 : (0x0e00 << 16) | (0xc270 >> 2),
352 : 0x00000000,
353 : (0x0e00 << 16) | (0xc274 >> 2),
354 : 0x00000000,
355 : (0x0e00 << 16) | (0xc278 >> 2),
356 : 0x00000000,
357 : (0x0e00 << 16) | (0xc27c >> 2),
358 : 0x00000000,
359 : (0x0e00 << 16) | (0xc280 >> 2),
360 : 0x00000000,
361 : (0x0e00 << 16) | (0xc284 >> 2),
362 : 0x00000000,
363 : (0x0e00 << 16) | (0xc288 >> 2),
364 : 0x00000000,
365 : (0x0e00 << 16) | (0xc28c >> 2),
366 : 0x00000000,
367 : (0x0e00 << 16) | (0xc290 >> 2),
368 : 0x00000000,
369 : (0x0e00 << 16) | (0xc294 >> 2),
370 : 0x00000000,
371 : (0x0e00 << 16) | (0xc298 >> 2),
372 : 0x00000000,
373 : (0x0e00 << 16) | (0xc29c >> 2),
374 : 0x00000000,
375 : (0x0e00 << 16) | (0xc2a0 >> 2),
376 : 0x00000000,
377 : (0x0e00 << 16) | (0xc2a4 >> 2),
378 : 0x00000000,
379 : (0x0e00 << 16) | (0xc2a8 >> 2),
380 : 0x00000000,
381 : (0x0e00 << 16) | (0xc2ac >> 2),
382 : 0x00000000,
383 : (0x0e00 << 16) | (0xc2b0 >> 2),
384 : 0x00000000,
385 : (0x0e00 << 16) | (0x301d0 >> 2),
386 : 0x00000000,
387 : (0x0e00 << 16) | (0x30238 >> 2),
388 : 0x00000000,
389 : (0x0e00 << 16) | (0x30250 >> 2),
390 : 0x00000000,
391 : (0x0e00 << 16) | (0x30254 >> 2),
392 : 0x00000000,
393 : (0x0e00 << 16) | (0x30258 >> 2),
394 : 0x00000000,
395 : (0x0e00 << 16) | (0x3025c >> 2),
396 : 0x00000000,
397 : (0x4e00 << 16) | (0xc900 >> 2),
398 : 0x00000000,
399 : (0x5e00 << 16) | (0xc900 >> 2),
400 : 0x00000000,
401 : (0x6e00 << 16) | (0xc900 >> 2),
402 : 0x00000000,
403 : (0x7e00 << 16) | (0xc900 >> 2),
404 : 0x00000000,
405 : (0x8e00 << 16) | (0xc900 >> 2),
406 : 0x00000000,
407 : (0x9e00 << 16) | (0xc900 >> 2),
408 : 0x00000000,
409 : (0xae00 << 16) | (0xc900 >> 2),
410 : 0x00000000,
411 : (0xbe00 << 16) | (0xc900 >> 2),
412 : 0x00000000,
413 : (0x4e00 << 16) | (0xc904 >> 2),
414 : 0x00000000,
415 : (0x5e00 << 16) | (0xc904 >> 2),
416 : 0x00000000,
417 : (0x6e00 << 16) | (0xc904 >> 2),
418 : 0x00000000,
419 : (0x7e00 << 16) | (0xc904 >> 2),
420 : 0x00000000,
421 : (0x8e00 << 16) | (0xc904 >> 2),
422 : 0x00000000,
423 : (0x9e00 << 16) | (0xc904 >> 2),
424 : 0x00000000,
425 : (0xae00 << 16) | (0xc904 >> 2),
426 : 0x00000000,
427 : (0xbe00 << 16) | (0xc904 >> 2),
428 : 0x00000000,
429 : (0x4e00 << 16) | (0xc908 >> 2),
430 : 0x00000000,
431 : (0x5e00 << 16) | (0xc908 >> 2),
432 : 0x00000000,
433 : (0x6e00 << 16) | (0xc908 >> 2),
434 : 0x00000000,
435 : (0x7e00 << 16) | (0xc908 >> 2),
436 : 0x00000000,
437 : (0x8e00 << 16) | (0xc908 >> 2),
438 : 0x00000000,
439 : (0x9e00 << 16) | (0xc908 >> 2),
440 : 0x00000000,
441 : (0xae00 << 16) | (0xc908 >> 2),
442 : 0x00000000,
443 : (0xbe00 << 16) | (0xc908 >> 2),
444 : 0x00000000,
445 : (0x4e00 << 16) | (0xc90c >> 2),
446 : 0x00000000,
447 : (0x5e00 << 16) | (0xc90c >> 2),
448 : 0x00000000,
449 : (0x6e00 << 16) | (0xc90c >> 2),
450 : 0x00000000,
451 : (0x7e00 << 16) | (0xc90c >> 2),
452 : 0x00000000,
453 : (0x8e00 << 16) | (0xc90c >> 2),
454 : 0x00000000,
455 : (0x9e00 << 16) | (0xc90c >> 2),
456 : 0x00000000,
457 : (0xae00 << 16) | (0xc90c >> 2),
458 : 0x00000000,
459 : (0xbe00 << 16) | (0xc90c >> 2),
460 : 0x00000000,
461 : (0x4e00 << 16) | (0xc910 >> 2),
462 : 0x00000000,
463 : (0x5e00 << 16) | (0xc910 >> 2),
464 : 0x00000000,
465 : (0x6e00 << 16) | (0xc910 >> 2),
466 : 0x00000000,
467 : (0x7e00 << 16) | (0xc910 >> 2),
468 : 0x00000000,
469 : (0x8e00 << 16) | (0xc910 >> 2),
470 : 0x00000000,
471 : (0x9e00 << 16) | (0xc910 >> 2),
472 : 0x00000000,
473 : (0xae00 << 16) | (0xc910 >> 2),
474 : 0x00000000,
475 : (0xbe00 << 16) | (0xc910 >> 2),
476 : 0x00000000,
477 : (0x0e00 << 16) | (0xc99c >> 2),
478 : 0x00000000,
479 : (0x0e00 << 16) | (0x9834 >> 2),
480 : 0x00000000,
481 : (0x0000 << 16) | (0x30f00 >> 2),
482 : 0x00000000,
483 : (0x0001 << 16) | (0x30f00 >> 2),
484 : 0x00000000,
485 : (0x0000 << 16) | (0x30f04 >> 2),
486 : 0x00000000,
487 : (0x0001 << 16) | (0x30f04 >> 2),
488 : 0x00000000,
489 : (0x0000 << 16) | (0x30f08 >> 2),
490 : 0x00000000,
491 : (0x0001 << 16) | (0x30f08 >> 2),
492 : 0x00000000,
493 : (0x0000 << 16) | (0x30f0c >> 2),
494 : 0x00000000,
495 : (0x0001 << 16) | (0x30f0c >> 2),
496 : 0x00000000,
497 : (0x0600 << 16) | (0x9b7c >> 2),
498 : 0x00000000,
499 : (0x0e00 << 16) | (0x8a14 >> 2),
500 : 0x00000000,
501 : (0x0e00 << 16) | (0x8a18 >> 2),
502 : 0x00000000,
503 : (0x0600 << 16) | (0x30a00 >> 2),
504 : 0x00000000,
505 : (0x0e00 << 16) | (0x8bf0 >> 2),
506 : 0x00000000,
507 : (0x0e00 << 16) | (0x8bcc >> 2),
508 : 0x00000000,
509 : (0x0e00 << 16) | (0x8b24 >> 2),
510 : 0x00000000,
511 : (0x0e00 << 16) | (0x30a04 >> 2),
512 : 0x00000000,
513 : (0x0600 << 16) | (0x30a10 >> 2),
514 : 0x00000000,
515 : (0x0600 << 16) | (0x30a14 >> 2),
516 : 0x00000000,
517 : (0x0600 << 16) | (0x30a18 >> 2),
518 : 0x00000000,
519 : (0x0600 << 16) | (0x30a2c >> 2),
520 : 0x00000000,
521 : (0x0e00 << 16) | (0xc700 >> 2),
522 : 0x00000000,
523 : (0x0e00 << 16) | (0xc704 >> 2),
524 : 0x00000000,
525 : (0x0e00 << 16) | (0xc708 >> 2),
526 : 0x00000000,
527 : (0x0e00 << 16) | (0xc768 >> 2),
528 : 0x00000000,
529 : (0x0400 << 16) | (0xc770 >> 2),
530 : 0x00000000,
531 : (0x0400 << 16) | (0xc774 >> 2),
532 : 0x00000000,
533 : (0x0400 << 16) | (0xc778 >> 2),
534 : 0x00000000,
535 : (0x0400 << 16) | (0xc77c >> 2),
536 : 0x00000000,
537 : (0x0400 << 16) | (0xc780 >> 2),
538 : 0x00000000,
539 : (0x0400 << 16) | (0xc784 >> 2),
540 : 0x00000000,
541 : (0x0400 << 16) | (0xc788 >> 2),
542 : 0x00000000,
543 : (0x0400 << 16) | (0xc78c >> 2),
544 : 0x00000000,
545 : (0x0400 << 16) | (0xc798 >> 2),
546 : 0x00000000,
547 : (0x0400 << 16) | (0xc79c >> 2),
548 : 0x00000000,
549 : (0x0400 << 16) | (0xc7a0 >> 2),
550 : 0x00000000,
551 : (0x0400 << 16) | (0xc7a4 >> 2),
552 : 0x00000000,
553 : (0x0400 << 16) | (0xc7a8 >> 2),
554 : 0x00000000,
555 : (0x0400 << 16) | (0xc7ac >> 2),
556 : 0x00000000,
557 : (0x0400 << 16) | (0xc7b0 >> 2),
558 : 0x00000000,
559 : (0x0400 << 16) | (0xc7b4 >> 2),
560 : 0x00000000,
561 : (0x0e00 << 16) | (0x9100 >> 2),
562 : 0x00000000,
563 : (0x0e00 << 16) | (0x3c010 >> 2),
564 : 0x00000000,
565 : (0x0e00 << 16) | (0x92a8 >> 2),
566 : 0x00000000,
567 : (0x0e00 << 16) | (0x92ac >> 2),
568 : 0x00000000,
569 : (0x0e00 << 16) | (0x92b4 >> 2),
570 : 0x00000000,
571 : (0x0e00 << 16) | (0x92b8 >> 2),
572 : 0x00000000,
573 : (0x0e00 << 16) | (0x92bc >> 2),
574 : 0x00000000,
575 : (0x0e00 << 16) | (0x92c0 >> 2),
576 : 0x00000000,
577 : (0x0e00 << 16) | (0x92c4 >> 2),
578 : 0x00000000,
579 : (0x0e00 << 16) | (0x92c8 >> 2),
580 : 0x00000000,
581 : (0x0e00 << 16) | (0x92cc >> 2),
582 : 0x00000000,
583 : (0x0e00 << 16) | (0x92d0 >> 2),
584 : 0x00000000,
585 : (0x0e00 << 16) | (0x8c00 >> 2),
586 : 0x00000000,
587 : (0x0e00 << 16) | (0x8c04 >> 2),
588 : 0x00000000,
589 : (0x0e00 << 16) | (0x8c20 >> 2),
590 : 0x00000000,
591 : (0x0e00 << 16) | (0x8c38 >> 2),
592 : 0x00000000,
593 : (0x0e00 << 16) | (0x8c3c >> 2),
594 : 0x00000000,
595 : (0x0e00 << 16) | (0xae00 >> 2),
596 : 0x00000000,
597 : (0x0e00 << 16) | (0x9604 >> 2),
598 : 0x00000000,
599 : (0x0e00 << 16) | (0xac08 >> 2),
600 : 0x00000000,
601 : (0x0e00 << 16) | (0xac0c >> 2),
602 : 0x00000000,
603 : (0x0e00 << 16) | (0xac10 >> 2),
604 : 0x00000000,
605 : (0x0e00 << 16) | (0xac14 >> 2),
606 : 0x00000000,
607 : (0x0e00 << 16) | (0xac58 >> 2),
608 : 0x00000000,
609 : (0x0e00 << 16) | (0xac68 >> 2),
610 : 0x00000000,
611 : (0x0e00 << 16) | (0xac6c >> 2),
612 : 0x00000000,
613 : (0x0e00 << 16) | (0xac70 >> 2),
614 : 0x00000000,
615 : (0x0e00 << 16) | (0xac74 >> 2),
616 : 0x00000000,
617 : (0x0e00 << 16) | (0xac78 >> 2),
618 : 0x00000000,
619 : (0x0e00 << 16) | (0xac7c >> 2),
620 : 0x00000000,
621 : (0x0e00 << 16) | (0xac80 >> 2),
622 : 0x00000000,
623 : (0x0e00 << 16) | (0xac84 >> 2),
624 : 0x00000000,
625 : (0x0e00 << 16) | (0xac88 >> 2),
626 : 0x00000000,
627 : (0x0e00 << 16) | (0xac8c >> 2),
628 : 0x00000000,
629 : (0x0e00 << 16) | (0x970c >> 2),
630 : 0x00000000,
631 : (0x0e00 << 16) | (0x9714 >> 2),
632 : 0x00000000,
633 : (0x0e00 << 16) | (0x9718 >> 2),
634 : 0x00000000,
635 : (0x0e00 << 16) | (0x971c >> 2),
636 : 0x00000000,
637 : (0x0e00 << 16) | (0x31068 >> 2),
638 : 0x00000000,
639 : (0x4e00 << 16) | (0x31068 >> 2),
640 : 0x00000000,
641 : (0x5e00 << 16) | (0x31068 >> 2),
642 : 0x00000000,
643 : (0x6e00 << 16) | (0x31068 >> 2),
644 : 0x00000000,
645 : (0x7e00 << 16) | (0x31068 >> 2),
646 : 0x00000000,
647 : (0x8e00 << 16) | (0x31068 >> 2),
648 : 0x00000000,
649 : (0x9e00 << 16) | (0x31068 >> 2),
650 : 0x00000000,
651 : (0xae00 << 16) | (0x31068 >> 2),
652 : 0x00000000,
653 : (0xbe00 << 16) | (0x31068 >> 2),
654 : 0x00000000,
655 : (0x0e00 << 16) | (0xcd10 >> 2),
656 : 0x00000000,
657 : (0x0e00 << 16) | (0xcd14 >> 2),
658 : 0x00000000,
659 : (0x0e00 << 16) | (0x88b0 >> 2),
660 : 0x00000000,
661 : (0x0e00 << 16) | (0x88b4 >> 2),
662 : 0x00000000,
663 : (0x0e00 << 16) | (0x88b8 >> 2),
664 : 0x00000000,
665 : (0x0e00 << 16) | (0x88bc >> 2),
666 : 0x00000000,
667 : (0x0400 << 16) | (0x89c0 >> 2),
668 : 0x00000000,
669 : (0x0e00 << 16) | (0x88c4 >> 2),
670 : 0x00000000,
671 : (0x0e00 << 16) | (0x88c8 >> 2),
672 : 0x00000000,
673 : (0x0e00 << 16) | (0x88d0 >> 2),
674 : 0x00000000,
675 : (0x0e00 << 16) | (0x88d4 >> 2),
676 : 0x00000000,
677 : (0x0e00 << 16) | (0x88d8 >> 2),
678 : 0x00000000,
679 : (0x0e00 << 16) | (0x8980 >> 2),
680 : 0x00000000,
681 : (0x0e00 << 16) | (0x30938 >> 2),
682 : 0x00000000,
683 : (0x0e00 << 16) | (0x3093c >> 2),
684 : 0x00000000,
685 : (0x0e00 << 16) | (0x30940 >> 2),
686 : 0x00000000,
687 : (0x0e00 << 16) | (0x89a0 >> 2),
688 : 0x00000000,
689 : (0x0e00 << 16) | (0x30900 >> 2),
690 : 0x00000000,
691 : (0x0e00 << 16) | (0x30904 >> 2),
692 : 0x00000000,
693 : (0x0e00 << 16) | (0x89b4 >> 2),
694 : 0x00000000,
695 : (0x0e00 << 16) | (0x3c210 >> 2),
696 : 0x00000000,
697 : (0x0e00 << 16) | (0x3c214 >> 2),
698 : 0x00000000,
699 : (0x0e00 << 16) | (0x3c218 >> 2),
700 : 0x00000000,
701 : (0x0e00 << 16) | (0x8904 >> 2),
702 : 0x00000000,
703 : 0x5,
704 : (0x0e00 << 16) | (0x8c28 >> 2),
705 : (0x0e00 << 16) | (0x8c2c >> 2),
706 : (0x0e00 << 16) | (0x8c30 >> 2),
707 : (0x0e00 << 16) | (0x8c34 >> 2),
708 : (0x0e00 << 16) | (0x9600 >> 2),
709 : };
710 :
711 : static const u32 kalindi_rlc_save_restore_register_list[] =
712 : {
713 : (0x0e00 << 16) | (0xc12c >> 2),
714 : 0x00000000,
715 : (0x0e00 << 16) | (0xc140 >> 2),
716 : 0x00000000,
717 : (0x0e00 << 16) | (0xc150 >> 2),
718 : 0x00000000,
719 : (0x0e00 << 16) | (0xc15c >> 2),
720 : 0x00000000,
721 : (0x0e00 << 16) | (0xc168 >> 2),
722 : 0x00000000,
723 : (0x0e00 << 16) | (0xc170 >> 2),
724 : 0x00000000,
725 : (0x0e00 << 16) | (0xc204 >> 2),
726 : 0x00000000,
727 : (0x0e00 << 16) | (0xc2b4 >> 2),
728 : 0x00000000,
729 : (0x0e00 << 16) | (0xc2b8 >> 2),
730 : 0x00000000,
731 : (0x0e00 << 16) | (0xc2bc >> 2),
732 : 0x00000000,
733 : (0x0e00 << 16) | (0xc2c0 >> 2),
734 : 0x00000000,
735 : (0x0e00 << 16) | (0x8228 >> 2),
736 : 0x00000000,
737 : (0x0e00 << 16) | (0x829c >> 2),
738 : 0x00000000,
739 : (0x0e00 << 16) | (0x869c >> 2),
740 : 0x00000000,
741 : (0x0600 << 16) | (0x98f4 >> 2),
742 : 0x00000000,
743 : (0x0e00 << 16) | (0x98f8 >> 2),
744 : 0x00000000,
745 : (0x0e00 << 16) | (0x9900 >> 2),
746 : 0x00000000,
747 : (0x0e00 << 16) | (0xc260 >> 2),
748 : 0x00000000,
749 : (0x0e00 << 16) | (0x90e8 >> 2),
750 : 0x00000000,
751 : (0x0e00 << 16) | (0x3c000 >> 2),
752 : 0x00000000,
753 : (0x0e00 << 16) | (0x3c00c >> 2),
754 : 0x00000000,
755 : (0x0e00 << 16) | (0x8c1c >> 2),
756 : 0x00000000,
757 : (0x0e00 << 16) | (0x9700 >> 2),
758 : 0x00000000,
759 : (0x0e00 << 16) | (0xcd20 >> 2),
760 : 0x00000000,
761 : (0x4e00 << 16) | (0xcd20 >> 2),
762 : 0x00000000,
763 : (0x5e00 << 16) | (0xcd20 >> 2),
764 : 0x00000000,
765 : (0x6e00 << 16) | (0xcd20 >> 2),
766 : 0x00000000,
767 : (0x7e00 << 16) | (0xcd20 >> 2),
768 : 0x00000000,
769 : (0x0e00 << 16) | (0x89bc >> 2),
770 : 0x00000000,
771 : (0x0e00 << 16) | (0x8900 >> 2),
772 : 0x00000000,
773 : 0x3,
774 : (0x0e00 << 16) | (0xc130 >> 2),
775 : 0x00000000,
776 : (0x0e00 << 16) | (0xc134 >> 2),
777 : 0x00000000,
778 : (0x0e00 << 16) | (0xc1fc >> 2),
779 : 0x00000000,
780 : (0x0e00 << 16) | (0xc208 >> 2),
781 : 0x00000000,
782 : (0x0e00 << 16) | (0xc264 >> 2),
783 : 0x00000000,
784 : (0x0e00 << 16) | (0xc268 >> 2),
785 : 0x00000000,
786 : (0x0e00 << 16) | (0xc26c >> 2),
787 : 0x00000000,
788 : (0x0e00 << 16) | (0xc270 >> 2),
789 : 0x00000000,
790 : (0x0e00 << 16) | (0xc274 >> 2),
791 : 0x00000000,
792 : (0x0e00 << 16) | (0xc28c >> 2),
793 : 0x00000000,
794 : (0x0e00 << 16) | (0xc290 >> 2),
795 : 0x00000000,
796 : (0x0e00 << 16) | (0xc294 >> 2),
797 : 0x00000000,
798 : (0x0e00 << 16) | (0xc298 >> 2),
799 : 0x00000000,
800 : (0x0e00 << 16) | (0xc2a0 >> 2),
801 : 0x00000000,
802 : (0x0e00 << 16) | (0xc2a4 >> 2),
803 : 0x00000000,
804 : (0x0e00 << 16) | (0xc2a8 >> 2),
805 : 0x00000000,
806 : (0x0e00 << 16) | (0xc2ac >> 2),
807 : 0x00000000,
808 : (0x0e00 << 16) | (0x301d0 >> 2),
809 : 0x00000000,
810 : (0x0e00 << 16) | (0x30238 >> 2),
811 : 0x00000000,
812 : (0x0e00 << 16) | (0x30250 >> 2),
813 : 0x00000000,
814 : (0x0e00 << 16) | (0x30254 >> 2),
815 : 0x00000000,
816 : (0x0e00 << 16) | (0x30258 >> 2),
817 : 0x00000000,
818 : (0x0e00 << 16) | (0x3025c >> 2),
819 : 0x00000000,
820 : (0x4e00 << 16) | (0xc900 >> 2),
821 : 0x00000000,
822 : (0x5e00 << 16) | (0xc900 >> 2),
823 : 0x00000000,
824 : (0x6e00 << 16) | (0xc900 >> 2),
825 : 0x00000000,
826 : (0x7e00 << 16) | (0xc900 >> 2),
827 : 0x00000000,
828 : (0x4e00 << 16) | (0xc904 >> 2),
829 : 0x00000000,
830 : (0x5e00 << 16) | (0xc904 >> 2),
831 : 0x00000000,
832 : (0x6e00 << 16) | (0xc904 >> 2),
833 : 0x00000000,
834 : (0x7e00 << 16) | (0xc904 >> 2),
835 : 0x00000000,
836 : (0x4e00 << 16) | (0xc908 >> 2),
837 : 0x00000000,
838 : (0x5e00 << 16) | (0xc908 >> 2),
839 : 0x00000000,
840 : (0x6e00 << 16) | (0xc908 >> 2),
841 : 0x00000000,
842 : (0x7e00 << 16) | (0xc908 >> 2),
843 : 0x00000000,
844 : (0x4e00 << 16) | (0xc90c >> 2),
845 : 0x00000000,
846 : (0x5e00 << 16) | (0xc90c >> 2),
847 : 0x00000000,
848 : (0x6e00 << 16) | (0xc90c >> 2),
849 : 0x00000000,
850 : (0x7e00 << 16) | (0xc90c >> 2),
851 : 0x00000000,
852 : (0x4e00 << 16) | (0xc910 >> 2),
853 : 0x00000000,
854 : (0x5e00 << 16) | (0xc910 >> 2),
855 : 0x00000000,
856 : (0x6e00 << 16) | (0xc910 >> 2),
857 : 0x00000000,
858 : (0x7e00 << 16) | (0xc910 >> 2),
859 : 0x00000000,
860 : (0x0e00 << 16) | (0xc99c >> 2),
861 : 0x00000000,
862 : (0x0e00 << 16) | (0x9834 >> 2),
863 : 0x00000000,
864 : (0x0000 << 16) | (0x30f00 >> 2),
865 : 0x00000000,
866 : (0x0000 << 16) | (0x30f04 >> 2),
867 : 0x00000000,
868 : (0x0000 << 16) | (0x30f08 >> 2),
869 : 0x00000000,
870 : (0x0000 << 16) | (0x30f0c >> 2),
871 : 0x00000000,
872 : (0x0600 << 16) | (0x9b7c >> 2),
873 : 0x00000000,
874 : (0x0e00 << 16) | (0x8a14 >> 2),
875 : 0x00000000,
876 : (0x0e00 << 16) | (0x8a18 >> 2),
877 : 0x00000000,
878 : (0x0600 << 16) | (0x30a00 >> 2),
879 : 0x00000000,
880 : (0x0e00 << 16) | (0x8bf0 >> 2),
881 : 0x00000000,
882 : (0x0e00 << 16) | (0x8bcc >> 2),
883 : 0x00000000,
884 : (0x0e00 << 16) | (0x8b24 >> 2),
885 : 0x00000000,
886 : (0x0e00 << 16) | (0x30a04 >> 2),
887 : 0x00000000,
888 : (0x0600 << 16) | (0x30a10 >> 2),
889 : 0x00000000,
890 : (0x0600 << 16) | (0x30a14 >> 2),
891 : 0x00000000,
892 : (0x0600 << 16) | (0x30a18 >> 2),
893 : 0x00000000,
894 : (0x0600 << 16) | (0x30a2c >> 2),
895 : 0x00000000,
896 : (0x0e00 << 16) | (0xc700 >> 2),
897 : 0x00000000,
898 : (0x0e00 << 16) | (0xc704 >> 2),
899 : 0x00000000,
900 : (0x0e00 << 16) | (0xc708 >> 2),
901 : 0x00000000,
902 : (0x0e00 << 16) | (0xc768 >> 2),
903 : 0x00000000,
904 : (0x0400 << 16) | (0xc770 >> 2),
905 : 0x00000000,
906 : (0x0400 << 16) | (0xc774 >> 2),
907 : 0x00000000,
908 : (0x0400 << 16) | (0xc798 >> 2),
909 : 0x00000000,
910 : (0x0400 << 16) | (0xc79c >> 2),
911 : 0x00000000,
912 : (0x0e00 << 16) | (0x9100 >> 2),
913 : 0x00000000,
914 : (0x0e00 << 16) | (0x3c010 >> 2),
915 : 0x00000000,
916 : (0x0e00 << 16) | (0x8c00 >> 2),
917 : 0x00000000,
918 : (0x0e00 << 16) | (0x8c04 >> 2),
919 : 0x00000000,
920 : (0x0e00 << 16) | (0x8c20 >> 2),
921 : 0x00000000,
922 : (0x0e00 << 16) | (0x8c38 >> 2),
923 : 0x00000000,
924 : (0x0e00 << 16) | (0x8c3c >> 2),
925 : 0x00000000,
926 : (0x0e00 << 16) | (0xae00 >> 2),
927 : 0x00000000,
928 : (0x0e00 << 16) | (0x9604 >> 2),
929 : 0x00000000,
930 : (0x0e00 << 16) | (0xac08 >> 2),
931 : 0x00000000,
932 : (0x0e00 << 16) | (0xac0c >> 2),
933 : 0x00000000,
934 : (0x0e00 << 16) | (0xac10 >> 2),
935 : 0x00000000,
936 : (0x0e00 << 16) | (0xac14 >> 2),
937 : 0x00000000,
938 : (0x0e00 << 16) | (0xac58 >> 2),
939 : 0x00000000,
940 : (0x0e00 << 16) | (0xac68 >> 2),
941 : 0x00000000,
942 : (0x0e00 << 16) | (0xac6c >> 2),
943 : 0x00000000,
944 : (0x0e00 << 16) | (0xac70 >> 2),
945 : 0x00000000,
946 : (0x0e00 << 16) | (0xac74 >> 2),
947 : 0x00000000,
948 : (0x0e00 << 16) | (0xac78 >> 2),
949 : 0x00000000,
950 : (0x0e00 << 16) | (0xac7c >> 2),
951 : 0x00000000,
952 : (0x0e00 << 16) | (0xac80 >> 2),
953 : 0x00000000,
954 : (0x0e00 << 16) | (0xac84 >> 2),
955 : 0x00000000,
956 : (0x0e00 << 16) | (0xac88 >> 2),
957 : 0x00000000,
958 : (0x0e00 << 16) | (0xac8c >> 2),
959 : 0x00000000,
960 : (0x0e00 << 16) | (0x970c >> 2),
961 : 0x00000000,
962 : (0x0e00 << 16) | (0x9714 >> 2),
963 : 0x00000000,
964 : (0x0e00 << 16) | (0x9718 >> 2),
965 : 0x00000000,
966 : (0x0e00 << 16) | (0x971c >> 2),
967 : 0x00000000,
968 : (0x0e00 << 16) | (0x31068 >> 2),
969 : 0x00000000,
970 : (0x4e00 << 16) | (0x31068 >> 2),
971 : 0x00000000,
972 : (0x5e00 << 16) | (0x31068 >> 2),
973 : 0x00000000,
974 : (0x6e00 << 16) | (0x31068 >> 2),
975 : 0x00000000,
976 : (0x7e00 << 16) | (0x31068 >> 2),
977 : 0x00000000,
978 : (0x0e00 << 16) | (0xcd10 >> 2),
979 : 0x00000000,
980 : (0x0e00 << 16) | (0xcd14 >> 2),
981 : 0x00000000,
982 : (0x0e00 << 16) | (0x88b0 >> 2),
983 : 0x00000000,
984 : (0x0e00 << 16) | (0x88b4 >> 2),
985 : 0x00000000,
986 : (0x0e00 << 16) | (0x88b8 >> 2),
987 : 0x00000000,
988 : (0x0e00 << 16) | (0x88bc >> 2),
989 : 0x00000000,
990 : (0x0400 << 16) | (0x89c0 >> 2),
991 : 0x00000000,
992 : (0x0e00 << 16) | (0x88c4 >> 2),
993 : 0x00000000,
994 : (0x0e00 << 16) | (0x88c8 >> 2),
995 : 0x00000000,
996 : (0x0e00 << 16) | (0x88d0 >> 2),
997 : 0x00000000,
998 : (0x0e00 << 16) | (0x88d4 >> 2),
999 : 0x00000000,
1000 : (0x0e00 << 16) | (0x88d8 >> 2),
1001 : 0x00000000,
1002 : (0x0e00 << 16) | (0x8980 >> 2),
1003 : 0x00000000,
1004 : (0x0e00 << 16) | (0x30938 >> 2),
1005 : 0x00000000,
1006 : (0x0e00 << 16) | (0x3093c >> 2),
1007 : 0x00000000,
1008 : (0x0e00 << 16) | (0x30940 >> 2),
1009 : 0x00000000,
1010 : (0x0e00 << 16) | (0x89a0 >> 2),
1011 : 0x00000000,
1012 : (0x0e00 << 16) | (0x30900 >> 2),
1013 : 0x00000000,
1014 : (0x0e00 << 16) | (0x30904 >> 2),
1015 : 0x00000000,
1016 : (0x0e00 << 16) | (0x89b4 >> 2),
1017 : 0x00000000,
1018 : (0x0e00 << 16) | (0x3e1fc >> 2),
1019 : 0x00000000,
1020 : (0x0e00 << 16) | (0x3c210 >> 2),
1021 : 0x00000000,
1022 : (0x0e00 << 16) | (0x3c214 >> 2),
1023 : 0x00000000,
1024 : (0x0e00 << 16) | (0x3c218 >> 2),
1025 : 0x00000000,
1026 : (0x0e00 << 16) | (0x8904 >> 2),
1027 : 0x00000000,
1028 : 0x5,
1029 : (0x0e00 << 16) | (0x8c28 >> 2),
1030 : (0x0e00 << 16) | (0x8c2c >> 2),
1031 : (0x0e00 << 16) | (0x8c30 >> 2),
1032 : (0x0e00 << 16) | (0x8c34 >> 2),
1033 : (0x0e00 << 16) | (0x9600 >> 2),
1034 : };
1035 :
1036 : static const u32 bonaire_golden_spm_registers[] =
1037 : {
1038 : 0x30800, 0xe0ffffff, 0xe0000000
1039 : };
1040 :
1041 : static const u32 bonaire_golden_common_registers[] =
1042 : {
1043 : 0xc770, 0xffffffff, 0x00000800,
1044 : 0xc774, 0xffffffff, 0x00000800,
1045 : 0xc798, 0xffffffff, 0x00007fbf,
1046 : 0xc79c, 0xffffffff, 0x00007faf
1047 : };
1048 :
1049 : static const u32 bonaire_golden_registers[] =
1050 : {
1051 : 0x3354, 0x00000333, 0x00000333,
1052 : 0x3350, 0x000c0fc0, 0x00040200,
1053 : 0x9a10, 0x00010000, 0x00058208,
1054 : 0x3c000, 0xffff1fff, 0x00140000,
1055 : 0x3c200, 0xfdfc0fff, 0x00000100,
1056 : 0x3c234, 0x40000000, 0x40000200,
1057 : 0x9830, 0xffffffff, 0x00000000,
1058 : 0x9834, 0xf00fffff, 0x00000400,
1059 : 0x9838, 0x0002021c, 0x00020200,
1060 : 0xc78, 0x00000080, 0x00000000,
1061 : 0x5bb0, 0x000000f0, 0x00000070,
1062 : 0x5bc0, 0xf0311fff, 0x80300000,
1063 : 0x98f8, 0x73773777, 0x12010001,
1064 : 0x350c, 0x00810000, 0x408af000,
1065 : 0x7030, 0x31000111, 0x00000011,
1066 : 0x2f48, 0x73773777, 0x12010001,
1067 : 0x220c, 0x00007fb6, 0x0021a1b1,
1068 : 0x2210, 0x00007fb6, 0x002021b1,
1069 : 0x2180, 0x00007fb6, 0x00002191,
1070 : 0x2218, 0x00007fb6, 0x002121b1,
1071 : 0x221c, 0x00007fb6, 0x002021b1,
1072 : 0x21dc, 0x00007fb6, 0x00002191,
1073 : 0x21e0, 0x00007fb6, 0x00002191,
1074 : 0x3628, 0x0000003f, 0x0000000a,
1075 : 0x362c, 0x0000003f, 0x0000000a,
1076 : 0x2ae4, 0x00073ffe, 0x000022a2,
1077 : 0x240c, 0x000007ff, 0x00000000,
1078 : 0x8a14, 0xf000003f, 0x00000007,
1079 : 0x8bf0, 0x00002001, 0x00000001,
1080 : 0x8b24, 0xffffffff, 0x00ffffff,
1081 : 0x30a04, 0x0000ff0f, 0x00000000,
1082 : 0x28a4c, 0x07ffffff, 0x06000000,
1083 : 0x4d8, 0x00000fff, 0x00000100,
1084 : 0x3e78, 0x00000001, 0x00000002,
1085 : 0x9100, 0x03000000, 0x0362c688,
1086 : 0x8c00, 0x000000ff, 0x00000001,
1087 : 0xe40, 0x00001fff, 0x00001fff,
1088 : 0x9060, 0x0000007f, 0x00000020,
1089 : 0x9508, 0x00010000, 0x00010000,
1090 : 0xac14, 0x000003ff, 0x000000f3,
1091 : 0xac0c, 0xffffffff, 0x00001032
1092 : };
1093 :
1094 : static const u32 bonaire_mgcg_cgcg_init[] =
1095 : {
1096 : 0xc420, 0xffffffff, 0xfffffffc,
1097 : 0x30800, 0xffffffff, 0xe0000000,
1098 : 0x3c2a0, 0xffffffff, 0x00000100,
1099 : 0x3c208, 0xffffffff, 0x00000100,
1100 : 0x3c2c0, 0xffffffff, 0xc0000100,
1101 : 0x3c2c8, 0xffffffff, 0xc0000100,
1102 : 0x3c2c4, 0xffffffff, 0xc0000100,
1103 : 0x55e4, 0xffffffff, 0x00600100,
1104 : 0x3c280, 0xffffffff, 0x00000100,
1105 : 0x3c214, 0xffffffff, 0x06000100,
1106 : 0x3c220, 0xffffffff, 0x00000100,
1107 : 0x3c218, 0xffffffff, 0x06000100,
1108 : 0x3c204, 0xffffffff, 0x00000100,
1109 : 0x3c2e0, 0xffffffff, 0x00000100,
1110 : 0x3c224, 0xffffffff, 0x00000100,
1111 : 0x3c200, 0xffffffff, 0x00000100,
1112 : 0x3c230, 0xffffffff, 0x00000100,
1113 : 0x3c234, 0xffffffff, 0x00000100,
1114 : 0x3c250, 0xffffffff, 0x00000100,
1115 : 0x3c254, 0xffffffff, 0x00000100,
1116 : 0x3c258, 0xffffffff, 0x00000100,
1117 : 0x3c25c, 0xffffffff, 0x00000100,
1118 : 0x3c260, 0xffffffff, 0x00000100,
1119 : 0x3c27c, 0xffffffff, 0x00000100,
1120 : 0x3c278, 0xffffffff, 0x00000100,
1121 : 0x3c210, 0xffffffff, 0x06000100,
1122 : 0x3c290, 0xffffffff, 0x00000100,
1123 : 0x3c274, 0xffffffff, 0x00000100,
1124 : 0x3c2b4, 0xffffffff, 0x00000100,
1125 : 0x3c2b0, 0xffffffff, 0x00000100,
1126 : 0x3c270, 0xffffffff, 0x00000100,
1127 : 0x30800, 0xffffffff, 0xe0000000,
1128 : 0x3c020, 0xffffffff, 0x00010000,
1129 : 0x3c024, 0xffffffff, 0x00030002,
1130 : 0x3c028, 0xffffffff, 0x00040007,
1131 : 0x3c02c, 0xffffffff, 0x00060005,
1132 : 0x3c030, 0xffffffff, 0x00090008,
1133 : 0x3c034, 0xffffffff, 0x00010000,
1134 : 0x3c038, 0xffffffff, 0x00030002,
1135 : 0x3c03c, 0xffffffff, 0x00040007,
1136 : 0x3c040, 0xffffffff, 0x00060005,
1137 : 0x3c044, 0xffffffff, 0x00090008,
1138 : 0x3c048, 0xffffffff, 0x00010000,
1139 : 0x3c04c, 0xffffffff, 0x00030002,
1140 : 0x3c050, 0xffffffff, 0x00040007,
1141 : 0x3c054, 0xffffffff, 0x00060005,
1142 : 0x3c058, 0xffffffff, 0x00090008,
1143 : 0x3c05c, 0xffffffff, 0x00010000,
1144 : 0x3c060, 0xffffffff, 0x00030002,
1145 : 0x3c064, 0xffffffff, 0x00040007,
1146 : 0x3c068, 0xffffffff, 0x00060005,
1147 : 0x3c06c, 0xffffffff, 0x00090008,
1148 : 0x3c070, 0xffffffff, 0x00010000,
1149 : 0x3c074, 0xffffffff, 0x00030002,
1150 : 0x3c078, 0xffffffff, 0x00040007,
1151 : 0x3c07c, 0xffffffff, 0x00060005,
1152 : 0x3c080, 0xffffffff, 0x00090008,
1153 : 0x3c084, 0xffffffff, 0x00010000,
1154 : 0x3c088, 0xffffffff, 0x00030002,
1155 : 0x3c08c, 0xffffffff, 0x00040007,
1156 : 0x3c090, 0xffffffff, 0x00060005,
1157 : 0x3c094, 0xffffffff, 0x00090008,
1158 : 0x3c098, 0xffffffff, 0x00010000,
1159 : 0x3c09c, 0xffffffff, 0x00030002,
1160 : 0x3c0a0, 0xffffffff, 0x00040007,
1161 : 0x3c0a4, 0xffffffff, 0x00060005,
1162 : 0x3c0a8, 0xffffffff, 0x00090008,
1163 : 0x3c000, 0xffffffff, 0x96e00200,
1164 : 0x8708, 0xffffffff, 0x00900100,
1165 : 0xc424, 0xffffffff, 0x0020003f,
1166 : 0x38, 0xffffffff, 0x0140001c,
1167 : 0x3c, 0x000f0000, 0x000f0000,
1168 : 0x220, 0xffffffff, 0xC060000C,
1169 : 0x224, 0xc0000fff, 0x00000100,
1170 : 0xf90, 0xffffffff, 0x00000100,
1171 : 0xf98, 0x00000101, 0x00000000,
1172 : 0x20a8, 0xffffffff, 0x00000104,
1173 : 0x55e4, 0xff000fff, 0x00000100,
1174 : 0x30cc, 0xc0000fff, 0x00000104,
1175 : 0xc1e4, 0x00000001, 0x00000001,
1176 : 0xd00c, 0xff000ff0, 0x00000100,
1177 : 0xd80c, 0xff000ff0, 0x00000100
1178 : };
1179 :
1180 : static const u32 spectre_golden_spm_registers[] =
1181 : {
1182 : 0x30800, 0xe0ffffff, 0xe0000000
1183 : };
1184 :
1185 : static const u32 spectre_golden_common_registers[] =
1186 : {
1187 : 0xc770, 0xffffffff, 0x00000800,
1188 : 0xc774, 0xffffffff, 0x00000800,
1189 : 0xc798, 0xffffffff, 0x00007fbf,
1190 : 0xc79c, 0xffffffff, 0x00007faf
1191 : };
1192 :
1193 : static const u32 spectre_golden_registers[] =
1194 : {
1195 : 0x3c000, 0xffff1fff, 0x96940200,
1196 : 0x3c00c, 0xffff0001, 0xff000000,
1197 : 0x3c200, 0xfffc0fff, 0x00000100,
1198 : 0x6ed8, 0x00010101, 0x00010000,
1199 : 0x9834, 0xf00fffff, 0x00000400,
1200 : 0x9838, 0xfffffffc, 0x00020200,
1201 : 0x5bb0, 0x000000f0, 0x00000070,
1202 : 0x5bc0, 0xf0311fff, 0x80300000,
1203 : 0x98f8, 0x73773777, 0x12010001,
1204 : 0x9b7c, 0x00ff0000, 0x00fc0000,
1205 : 0x2f48, 0x73773777, 0x12010001,
1206 : 0x8a14, 0xf000003f, 0x00000007,
1207 : 0x8b24, 0xffffffff, 0x00ffffff,
1208 : 0x28350, 0x3f3f3fff, 0x00000082,
1209 : 0x28354, 0x0000003f, 0x00000000,
1210 : 0x3e78, 0x00000001, 0x00000002,
1211 : 0x913c, 0xffff03df, 0x00000004,
1212 : 0xc768, 0x00000008, 0x00000008,
1213 : 0x8c00, 0x000008ff, 0x00000800,
1214 : 0x9508, 0x00010000, 0x00010000,
1215 : 0xac0c, 0xffffffff, 0x54763210,
1216 : 0x214f8, 0x01ff01ff, 0x00000002,
1217 : 0x21498, 0x007ff800, 0x00200000,
1218 : 0x2015c, 0xffffffff, 0x00000f40,
1219 : 0x30934, 0xffffffff, 0x00000001
1220 : };
1221 :
1222 : static const u32 spectre_mgcg_cgcg_init[] =
1223 : {
1224 : 0xc420, 0xffffffff, 0xfffffffc,
1225 : 0x30800, 0xffffffff, 0xe0000000,
1226 : 0x3c2a0, 0xffffffff, 0x00000100,
1227 : 0x3c208, 0xffffffff, 0x00000100,
1228 : 0x3c2c0, 0xffffffff, 0x00000100,
1229 : 0x3c2c8, 0xffffffff, 0x00000100,
1230 : 0x3c2c4, 0xffffffff, 0x00000100,
1231 : 0x55e4, 0xffffffff, 0x00600100,
1232 : 0x3c280, 0xffffffff, 0x00000100,
1233 : 0x3c214, 0xffffffff, 0x06000100,
1234 : 0x3c220, 0xffffffff, 0x00000100,
1235 : 0x3c218, 0xffffffff, 0x06000100,
1236 : 0x3c204, 0xffffffff, 0x00000100,
1237 : 0x3c2e0, 0xffffffff, 0x00000100,
1238 : 0x3c224, 0xffffffff, 0x00000100,
1239 : 0x3c200, 0xffffffff, 0x00000100,
1240 : 0x3c230, 0xffffffff, 0x00000100,
1241 : 0x3c234, 0xffffffff, 0x00000100,
1242 : 0x3c250, 0xffffffff, 0x00000100,
1243 : 0x3c254, 0xffffffff, 0x00000100,
1244 : 0x3c258, 0xffffffff, 0x00000100,
1245 : 0x3c25c, 0xffffffff, 0x00000100,
1246 : 0x3c260, 0xffffffff, 0x00000100,
1247 : 0x3c27c, 0xffffffff, 0x00000100,
1248 : 0x3c278, 0xffffffff, 0x00000100,
1249 : 0x3c210, 0xffffffff, 0x06000100,
1250 : 0x3c290, 0xffffffff, 0x00000100,
1251 : 0x3c274, 0xffffffff, 0x00000100,
1252 : 0x3c2b4, 0xffffffff, 0x00000100,
1253 : 0x3c2b0, 0xffffffff, 0x00000100,
1254 : 0x3c270, 0xffffffff, 0x00000100,
1255 : 0x30800, 0xffffffff, 0xe0000000,
1256 : 0x3c020, 0xffffffff, 0x00010000,
1257 : 0x3c024, 0xffffffff, 0x00030002,
1258 : 0x3c028, 0xffffffff, 0x00040007,
1259 : 0x3c02c, 0xffffffff, 0x00060005,
1260 : 0x3c030, 0xffffffff, 0x00090008,
1261 : 0x3c034, 0xffffffff, 0x00010000,
1262 : 0x3c038, 0xffffffff, 0x00030002,
1263 : 0x3c03c, 0xffffffff, 0x00040007,
1264 : 0x3c040, 0xffffffff, 0x00060005,
1265 : 0x3c044, 0xffffffff, 0x00090008,
1266 : 0x3c048, 0xffffffff, 0x00010000,
1267 : 0x3c04c, 0xffffffff, 0x00030002,
1268 : 0x3c050, 0xffffffff, 0x00040007,
1269 : 0x3c054, 0xffffffff, 0x00060005,
1270 : 0x3c058, 0xffffffff, 0x00090008,
1271 : 0x3c05c, 0xffffffff, 0x00010000,
1272 : 0x3c060, 0xffffffff, 0x00030002,
1273 : 0x3c064, 0xffffffff, 0x00040007,
1274 : 0x3c068, 0xffffffff, 0x00060005,
1275 : 0x3c06c, 0xffffffff, 0x00090008,
1276 : 0x3c070, 0xffffffff, 0x00010000,
1277 : 0x3c074, 0xffffffff, 0x00030002,
1278 : 0x3c078, 0xffffffff, 0x00040007,
1279 : 0x3c07c, 0xffffffff, 0x00060005,
1280 : 0x3c080, 0xffffffff, 0x00090008,
1281 : 0x3c084, 0xffffffff, 0x00010000,
1282 : 0x3c088, 0xffffffff, 0x00030002,
1283 : 0x3c08c, 0xffffffff, 0x00040007,
1284 : 0x3c090, 0xffffffff, 0x00060005,
1285 : 0x3c094, 0xffffffff, 0x00090008,
1286 : 0x3c098, 0xffffffff, 0x00010000,
1287 : 0x3c09c, 0xffffffff, 0x00030002,
1288 : 0x3c0a0, 0xffffffff, 0x00040007,
1289 : 0x3c0a4, 0xffffffff, 0x00060005,
1290 : 0x3c0a8, 0xffffffff, 0x00090008,
1291 : 0x3c0ac, 0xffffffff, 0x00010000,
1292 : 0x3c0b0, 0xffffffff, 0x00030002,
1293 : 0x3c0b4, 0xffffffff, 0x00040007,
1294 : 0x3c0b8, 0xffffffff, 0x00060005,
1295 : 0x3c0bc, 0xffffffff, 0x00090008,
1296 : 0x3c000, 0xffffffff, 0x96e00200,
1297 : 0x8708, 0xffffffff, 0x00900100,
1298 : 0xc424, 0xffffffff, 0x0020003f,
1299 : 0x38, 0xffffffff, 0x0140001c,
1300 : 0x3c, 0x000f0000, 0x000f0000,
1301 : 0x220, 0xffffffff, 0xC060000C,
1302 : 0x224, 0xc0000fff, 0x00000100,
1303 : 0xf90, 0xffffffff, 0x00000100,
1304 : 0xf98, 0x00000101, 0x00000000,
1305 : 0x20a8, 0xffffffff, 0x00000104,
1306 : 0x55e4, 0xff000fff, 0x00000100,
1307 : 0x30cc, 0xc0000fff, 0x00000104,
1308 : 0xc1e4, 0x00000001, 0x00000001,
1309 : 0xd00c, 0xff000ff0, 0x00000100,
1310 : 0xd80c, 0xff000ff0, 0x00000100
1311 : };
1312 :
1313 : static const u32 kalindi_golden_spm_registers[] =
1314 : {
1315 : 0x30800, 0xe0ffffff, 0xe0000000
1316 : };
1317 :
1318 : static const u32 kalindi_golden_common_registers[] =
1319 : {
1320 : 0xc770, 0xffffffff, 0x00000800,
1321 : 0xc774, 0xffffffff, 0x00000800,
1322 : 0xc798, 0xffffffff, 0x00007fbf,
1323 : 0xc79c, 0xffffffff, 0x00007faf
1324 : };
1325 :
1326 : static const u32 kalindi_golden_registers[] =
1327 : {
1328 : 0x3c000, 0xffffdfff, 0x6e944040,
1329 : 0x55e4, 0xff607fff, 0xfc000100,
1330 : 0x3c220, 0xff000fff, 0x00000100,
1331 : 0x3c224, 0xff000fff, 0x00000100,
1332 : 0x3c200, 0xfffc0fff, 0x00000100,
1333 : 0x6ed8, 0x00010101, 0x00010000,
1334 : 0x9830, 0xffffffff, 0x00000000,
1335 : 0x9834, 0xf00fffff, 0x00000400,
1336 : 0x5bb0, 0x000000f0, 0x00000070,
1337 : 0x5bc0, 0xf0311fff, 0x80300000,
1338 : 0x98f8, 0x73773777, 0x12010001,
1339 : 0x98fc, 0xffffffff, 0x00000010,
1340 : 0x9b7c, 0x00ff0000, 0x00fc0000,
1341 : 0x8030, 0x00001f0f, 0x0000100a,
1342 : 0x2f48, 0x73773777, 0x12010001,
1343 : 0x2408, 0x000fffff, 0x000c007f,
1344 : 0x8a14, 0xf000003f, 0x00000007,
1345 : 0x8b24, 0x3fff3fff, 0x00ffcfff,
1346 : 0x30a04, 0x0000ff0f, 0x00000000,
1347 : 0x28a4c, 0x07ffffff, 0x06000000,
1348 : 0x4d8, 0x00000fff, 0x00000100,
1349 : 0x3e78, 0x00000001, 0x00000002,
1350 : 0xc768, 0x00000008, 0x00000008,
1351 : 0x8c00, 0x000000ff, 0x00000003,
1352 : 0x214f8, 0x01ff01ff, 0x00000002,
1353 : 0x21498, 0x007ff800, 0x00200000,
1354 : 0x2015c, 0xffffffff, 0x00000f40,
1355 : 0x88c4, 0x001f3ae3, 0x00000082,
1356 : 0x88d4, 0x0000001f, 0x00000010,
1357 : 0x30934, 0xffffffff, 0x00000000
1358 : };
1359 :
1360 : static const u32 kalindi_mgcg_cgcg_init[] =
1361 : {
1362 : 0xc420, 0xffffffff, 0xfffffffc,
1363 : 0x30800, 0xffffffff, 0xe0000000,
1364 : 0x3c2a0, 0xffffffff, 0x00000100,
1365 : 0x3c208, 0xffffffff, 0x00000100,
1366 : 0x3c2c0, 0xffffffff, 0x00000100,
1367 : 0x3c2c8, 0xffffffff, 0x00000100,
1368 : 0x3c2c4, 0xffffffff, 0x00000100,
1369 : 0x55e4, 0xffffffff, 0x00600100,
1370 : 0x3c280, 0xffffffff, 0x00000100,
1371 : 0x3c214, 0xffffffff, 0x06000100,
1372 : 0x3c220, 0xffffffff, 0x00000100,
1373 : 0x3c218, 0xffffffff, 0x06000100,
1374 : 0x3c204, 0xffffffff, 0x00000100,
1375 : 0x3c2e0, 0xffffffff, 0x00000100,
1376 : 0x3c224, 0xffffffff, 0x00000100,
1377 : 0x3c200, 0xffffffff, 0x00000100,
1378 : 0x3c230, 0xffffffff, 0x00000100,
1379 : 0x3c234, 0xffffffff, 0x00000100,
1380 : 0x3c250, 0xffffffff, 0x00000100,
1381 : 0x3c254, 0xffffffff, 0x00000100,
1382 : 0x3c258, 0xffffffff, 0x00000100,
1383 : 0x3c25c, 0xffffffff, 0x00000100,
1384 : 0x3c260, 0xffffffff, 0x00000100,
1385 : 0x3c27c, 0xffffffff, 0x00000100,
1386 : 0x3c278, 0xffffffff, 0x00000100,
1387 : 0x3c210, 0xffffffff, 0x06000100,
1388 : 0x3c290, 0xffffffff, 0x00000100,
1389 : 0x3c274, 0xffffffff, 0x00000100,
1390 : 0x3c2b4, 0xffffffff, 0x00000100,
1391 : 0x3c2b0, 0xffffffff, 0x00000100,
1392 : 0x3c270, 0xffffffff, 0x00000100,
1393 : 0x30800, 0xffffffff, 0xe0000000,
1394 : 0x3c020, 0xffffffff, 0x00010000,
1395 : 0x3c024, 0xffffffff, 0x00030002,
1396 : 0x3c028, 0xffffffff, 0x00040007,
1397 : 0x3c02c, 0xffffffff, 0x00060005,
1398 : 0x3c030, 0xffffffff, 0x00090008,
1399 : 0x3c034, 0xffffffff, 0x00010000,
1400 : 0x3c038, 0xffffffff, 0x00030002,
1401 : 0x3c03c, 0xffffffff, 0x00040007,
1402 : 0x3c040, 0xffffffff, 0x00060005,
1403 : 0x3c044, 0xffffffff, 0x00090008,
1404 : 0x3c000, 0xffffffff, 0x96e00200,
1405 : 0x8708, 0xffffffff, 0x00900100,
1406 : 0xc424, 0xffffffff, 0x0020003f,
1407 : 0x38, 0xffffffff, 0x0140001c,
1408 : 0x3c, 0x000f0000, 0x000f0000,
1409 : 0x220, 0xffffffff, 0xC060000C,
1410 : 0x224, 0xc0000fff, 0x00000100,
1411 : 0x20a8, 0xffffffff, 0x00000104,
1412 : 0x55e4, 0xff000fff, 0x00000100,
1413 : 0x30cc, 0xc0000fff, 0x00000104,
1414 : 0xc1e4, 0x00000001, 0x00000001,
1415 : 0xd00c, 0xff000ff0, 0x00000100,
1416 : 0xd80c, 0xff000ff0, 0x00000100
1417 : };
1418 :
1419 : static const u32 hawaii_golden_spm_registers[] =
1420 : {
1421 : 0x30800, 0xe0ffffff, 0xe0000000
1422 : };
1423 :
1424 : static const u32 hawaii_golden_common_registers[] =
1425 : {
1426 : 0x30800, 0xffffffff, 0xe0000000,
1427 : 0x28350, 0xffffffff, 0x3a00161a,
1428 : 0x28354, 0xffffffff, 0x0000002e,
1429 : 0x9a10, 0xffffffff, 0x00018208,
1430 : 0x98f8, 0xffffffff, 0x12011003
1431 : };
1432 :
1433 : static const u32 hawaii_golden_registers[] =
1434 : {
1435 : 0x3354, 0x00000333, 0x00000333,
1436 : 0x9a10, 0x00010000, 0x00058208,
1437 : 0x9830, 0xffffffff, 0x00000000,
1438 : 0x9834, 0xf00fffff, 0x00000400,
1439 : 0x9838, 0x0002021c, 0x00020200,
1440 : 0xc78, 0x00000080, 0x00000000,
1441 : 0x5bb0, 0x000000f0, 0x00000070,
1442 : 0x5bc0, 0xf0311fff, 0x80300000,
1443 : 0x350c, 0x00810000, 0x408af000,
1444 : 0x7030, 0x31000111, 0x00000011,
1445 : 0x2f48, 0x73773777, 0x12010001,
1446 : 0x2120, 0x0000007f, 0x0000001b,
1447 : 0x21dc, 0x00007fb6, 0x00002191,
1448 : 0x3628, 0x0000003f, 0x0000000a,
1449 : 0x362c, 0x0000003f, 0x0000000a,
1450 : 0x2ae4, 0x00073ffe, 0x000022a2,
1451 : 0x240c, 0x000007ff, 0x00000000,
1452 : 0x8bf0, 0x00002001, 0x00000001,
1453 : 0x8b24, 0xffffffff, 0x00ffffff,
1454 : 0x30a04, 0x0000ff0f, 0x00000000,
1455 : 0x28a4c, 0x07ffffff, 0x06000000,
1456 : 0x3e78, 0x00000001, 0x00000002,
1457 : 0xc768, 0x00000008, 0x00000008,
1458 : 0xc770, 0x00000f00, 0x00000800,
1459 : 0xc774, 0x00000f00, 0x00000800,
1460 : 0xc798, 0x00ffffff, 0x00ff7fbf,
1461 : 0xc79c, 0x00ffffff, 0x00ff7faf,
1462 : 0x8c00, 0x000000ff, 0x00000800,
1463 : 0xe40, 0x00001fff, 0x00001fff,
1464 : 0x9060, 0x0000007f, 0x00000020,
1465 : 0x9508, 0x00010000, 0x00010000,
1466 : 0xae00, 0x00100000, 0x000ff07c,
1467 : 0xac14, 0x000003ff, 0x0000000f,
1468 : 0xac10, 0xffffffff, 0x7564fdec,
1469 : 0xac0c, 0xffffffff, 0x3120b9a8,
1470 : 0xac08, 0x20000000, 0x0f9c0000
1471 : };
1472 :
1473 : static const u32 hawaii_mgcg_cgcg_init[] =
1474 : {
1475 : 0xc420, 0xffffffff, 0xfffffffd,
1476 : 0x30800, 0xffffffff, 0xe0000000,
1477 : 0x3c2a0, 0xffffffff, 0x00000100,
1478 : 0x3c208, 0xffffffff, 0x00000100,
1479 : 0x3c2c0, 0xffffffff, 0x00000100,
1480 : 0x3c2c8, 0xffffffff, 0x00000100,
1481 : 0x3c2c4, 0xffffffff, 0x00000100,
1482 : 0x55e4, 0xffffffff, 0x00200100,
1483 : 0x3c280, 0xffffffff, 0x00000100,
1484 : 0x3c214, 0xffffffff, 0x06000100,
1485 : 0x3c220, 0xffffffff, 0x00000100,
1486 : 0x3c218, 0xffffffff, 0x06000100,
1487 : 0x3c204, 0xffffffff, 0x00000100,
1488 : 0x3c2e0, 0xffffffff, 0x00000100,
1489 : 0x3c224, 0xffffffff, 0x00000100,
1490 : 0x3c200, 0xffffffff, 0x00000100,
1491 : 0x3c230, 0xffffffff, 0x00000100,
1492 : 0x3c234, 0xffffffff, 0x00000100,
1493 : 0x3c250, 0xffffffff, 0x00000100,
1494 : 0x3c254, 0xffffffff, 0x00000100,
1495 : 0x3c258, 0xffffffff, 0x00000100,
1496 : 0x3c25c, 0xffffffff, 0x00000100,
1497 : 0x3c260, 0xffffffff, 0x00000100,
1498 : 0x3c27c, 0xffffffff, 0x00000100,
1499 : 0x3c278, 0xffffffff, 0x00000100,
1500 : 0x3c210, 0xffffffff, 0x06000100,
1501 : 0x3c290, 0xffffffff, 0x00000100,
1502 : 0x3c274, 0xffffffff, 0x00000100,
1503 : 0x3c2b4, 0xffffffff, 0x00000100,
1504 : 0x3c2b0, 0xffffffff, 0x00000100,
1505 : 0x3c270, 0xffffffff, 0x00000100,
1506 : 0x30800, 0xffffffff, 0xe0000000,
1507 : 0x3c020, 0xffffffff, 0x00010000,
1508 : 0x3c024, 0xffffffff, 0x00030002,
1509 : 0x3c028, 0xffffffff, 0x00040007,
1510 : 0x3c02c, 0xffffffff, 0x00060005,
1511 : 0x3c030, 0xffffffff, 0x00090008,
1512 : 0x3c034, 0xffffffff, 0x00010000,
1513 : 0x3c038, 0xffffffff, 0x00030002,
1514 : 0x3c03c, 0xffffffff, 0x00040007,
1515 : 0x3c040, 0xffffffff, 0x00060005,
1516 : 0x3c044, 0xffffffff, 0x00090008,
1517 : 0x3c048, 0xffffffff, 0x00010000,
1518 : 0x3c04c, 0xffffffff, 0x00030002,
1519 : 0x3c050, 0xffffffff, 0x00040007,
1520 : 0x3c054, 0xffffffff, 0x00060005,
1521 : 0x3c058, 0xffffffff, 0x00090008,
1522 : 0x3c05c, 0xffffffff, 0x00010000,
1523 : 0x3c060, 0xffffffff, 0x00030002,
1524 : 0x3c064, 0xffffffff, 0x00040007,
1525 : 0x3c068, 0xffffffff, 0x00060005,
1526 : 0x3c06c, 0xffffffff, 0x00090008,
1527 : 0x3c070, 0xffffffff, 0x00010000,
1528 : 0x3c074, 0xffffffff, 0x00030002,
1529 : 0x3c078, 0xffffffff, 0x00040007,
1530 : 0x3c07c, 0xffffffff, 0x00060005,
1531 : 0x3c080, 0xffffffff, 0x00090008,
1532 : 0x3c084, 0xffffffff, 0x00010000,
1533 : 0x3c088, 0xffffffff, 0x00030002,
1534 : 0x3c08c, 0xffffffff, 0x00040007,
1535 : 0x3c090, 0xffffffff, 0x00060005,
1536 : 0x3c094, 0xffffffff, 0x00090008,
1537 : 0x3c098, 0xffffffff, 0x00010000,
1538 : 0x3c09c, 0xffffffff, 0x00030002,
1539 : 0x3c0a0, 0xffffffff, 0x00040007,
1540 : 0x3c0a4, 0xffffffff, 0x00060005,
1541 : 0x3c0a8, 0xffffffff, 0x00090008,
1542 : 0x3c0ac, 0xffffffff, 0x00010000,
1543 : 0x3c0b0, 0xffffffff, 0x00030002,
1544 : 0x3c0b4, 0xffffffff, 0x00040007,
1545 : 0x3c0b8, 0xffffffff, 0x00060005,
1546 : 0x3c0bc, 0xffffffff, 0x00090008,
1547 : 0x3c0c0, 0xffffffff, 0x00010000,
1548 : 0x3c0c4, 0xffffffff, 0x00030002,
1549 : 0x3c0c8, 0xffffffff, 0x00040007,
1550 : 0x3c0cc, 0xffffffff, 0x00060005,
1551 : 0x3c0d0, 0xffffffff, 0x00090008,
1552 : 0x3c0d4, 0xffffffff, 0x00010000,
1553 : 0x3c0d8, 0xffffffff, 0x00030002,
1554 : 0x3c0dc, 0xffffffff, 0x00040007,
1555 : 0x3c0e0, 0xffffffff, 0x00060005,
1556 : 0x3c0e4, 0xffffffff, 0x00090008,
1557 : 0x3c0e8, 0xffffffff, 0x00010000,
1558 : 0x3c0ec, 0xffffffff, 0x00030002,
1559 : 0x3c0f0, 0xffffffff, 0x00040007,
1560 : 0x3c0f4, 0xffffffff, 0x00060005,
1561 : 0x3c0f8, 0xffffffff, 0x00090008,
1562 : 0xc318, 0xffffffff, 0x00020200,
1563 : 0x3350, 0xffffffff, 0x00000200,
1564 : 0x15c0, 0xffffffff, 0x00000400,
1565 : 0x55e8, 0xffffffff, 0x00000000,
1566 : 0x2f50, 0xffffffff, 0x00000902,
1567 : 0x3c000, 0xffffffff, 0x96940200,
1568 : 0x8708, 0xffffffff, 0x00900100,
1569 : 0xc424, 0xffffffff, 0x0020003f,
1570 : 0x38, 0xffffffff, 0x0140001c,
1571 : 0x3c, 0x000f0000, 0x000f0000,
1572 : 0x220, 0xffffffff, 0xc060000c,
1573 : 0x224, 0xc0000fff, 0x00000100,
1574 : 0xf90, 0xffffffff, 0x00000100,
1575 : 0xf98, 0x00000101, 0x00000000,
1576 : 0x20a8, 0xffffffff, 0x00000104,
1577 : 0x55e4, 0xff000fff, 0x00000100,
1578 : 0x30cc, 0xc0000fff, 0x00000104,
1579 : 0xc1e4, 0x00000001, 0x00000001,
1580 : 0xd00c, 0xff000ff0, 0x00000100,
1581 : 0xd80c, 0xff000ff0, 0x00000100
1582 : };
1583 :
1584 : static const u32 godavari_golden_registers[] =
1585 : {
1586 : 0x55e4, 0xff607fff, 0xfc000100,
1587 : 0x6ed8, 0x00010101, 0x00010000,
1588 : 0x9830, 0xffffffff, 0x00000000,
1589 : 0x98302, 0xf00fffff, 0x00000400,
1590 : 0x6130, 0xffffffff, 0x00010000,
1591 : 0x5bb0, 0x000000f0, 0x00000070,
1592 : 0x5bc0, 0xf0311fff, 0x80300000,
1593 : 0x98f8, 0x73773777, 0x12010001,
1594 : 0x98fc, 0xffffffff, 0x00000010,
1595 : 0x8030, 0x00001f0f, 0x0000100a,
1596 : 0x2f48, 0x73773777, 0x12010001,
1597 : 0x2408, 0x000fffff, 0x000c007f,
1598 : 0x8a14, 0xf000003f, 0x00000007,
1599 : 0x8b24, 0xffffffff, 0x00ff0fff,
1600 : 0x30a04, 0x0000ff0f, 0x00000000,
1601 : 0x28a4c, 0x07ffffff, 0x06000000,
1602 : 0x4d8, 0x00000fff, 0x00000100,
1603 : 0xd014, 0x00010000, 0x00810001,
1604 : 0xd814, 0x00010000, 0x00810001,
1605 : 0x3e78, 0x00000001, 0x00000002,
1606 : 0xc768, 0x00000008, 0x00000008,
1607 : 0xc770, 0x00000f00, 0x00000800,
1608 : 0xc774, 0x00000f00, 0x00000800,
1609 : 0xc798, 0x00ffffff, 0x00ff7fbf,
1610 : 0xc79c, 0x00ffffff, 0x00ff7faf,
1611 : 0x8c00, 0x000000ff, 0x00000001,
1612 : 0x214f8, 0x01ff01ff, 0x00000002,
1613 : 0x21498, 0x007ff800, 0x00200000,
1614 : 0x2015c, 0xffffffff, 0x00000f40,
1615 : 0x88c4, 0x001f3ae3, 0x00000082,
1616 : 0x88d4, 0x0000001f, 0x00000010,
1617 : 0x30934, 0xffffffff, 0x00000000
1618 : };
1619 :
1620 :
1621 0 : static void cik_init_golden_registers(struct radeon_device *rdev)
1622 : {
1623 : /* Some of the registers might be dependent on GRBM_GFX_INDEX */
1624 0 : mutex_lock(&rdev->grbm_idx_mutex);
1625 0 : switch (rdev->family) {
1626 : case CHIP_BONAIRE:
1627 0 : radeon_program_register_sequence(rdev,
1628 : bonaire_mgcg_cgcg_init,
1629 : (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1630 0 : radeon_program_register_sequence(rdev,
1631 : bonaire_golden_registers,
1632 : (const u32)ARRAY_SIZE(bonaire_golden_registers));
1633 0 : radeon_program_register_sequence(rdev,
1634 : bonaire_golden_common_registers,
1635 : (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
1636 0 : radeon_program_register_sequence(rdev,
1637 : bonaire_golden_spm_registers,
1638 : (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
1639 0 : break;
1640 : case CHIP_KABINI:
1641 0 : radeon_program_register_sequence(rdev,
1642 : kalindi_mgcg_cgcg_init,
1643 : (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1644 0 : radeon_program_register_sequence(rdev,
1645 : kalindi_golden_registers,
1646 : (const u32)ARRAY_SIZE(kalindi_golden_registers));
1647 0 : radeon_program_register_sequence(rdev,
1648 : kalindi_golden_common_registers,
1649 : (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1650 0 : radeon_program_register_sequence(rdev,
1651 : kalindi_golden_spm_registers,
1652 : (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1653 0 : break;
1654 : case CHIP_MULLINS:
1655 0 : radeon_program_register_sequence(rdev,
1656 : kalindi_mgcg_cgcg_init,
1657 : (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1658 0 : radeon_program_register_sequence(rdev,
1659 : godavari_golden_registers,
1660 : (const u32)ARRAY_SIZE(godavari_golden_registers));
1661 0 : radeon_program_register_sequence(rdev,
1662 : kalindi_golden_common_registers,
1663 : (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1664 0 : radeon_program_register_sequence(rdev,
1665 : kalindi_golden_spm_registers,
1666 : (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1667 0 : break;
1668 : case CHIP_KAVERI:
1669 0 : radeon_program_register_sequence(rdev,
1670 : spectre_mgcg_cgcg_init,
1671 : (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
1672 0 : radeon_program_register_sequence(rdev,
1673 : spectre_golden_registers,
1674 : (const u32)ARRAY_SIZE(spectre_golden_registers));
1675 0 : radeon_program_register_sequence(rdev,
1676 : spectre_golden_common_registers,
1677 : (const u32)ARRAY_SIZE(spectre_golden_common_registers));
1678 0 : radeon_program_register_sequence(rdev,
1679 : spectre_golden_spm_registers,
1680 : (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
1681 0 : break;
1682 : case CHIP_HAWAII:
1683 0 : radeon_program_register_sequence(rdev,
1684 : hawaii_mgcg_cgcg_init,
1685 : (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
1686 0 : radeon_program_register_sequence(rdev,
1687 : hawaii_golden_registers,
1688 : (const u32)ARRAY_SIZE(hawaii_golden_registers));
1689 0 : radeon_program_register_sequence(rdev,
1690 : hawaii_golden_common_registers,
1691 : (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1692 0 : radeon_program_register_sequence(rdev,
1693 : hawaii_golden_spm_registers,
1694 : (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1695 0 : break;
1696 : default:
1697 : break;
1698 : }
1699 0 : mutex_unlock(&rdev->grbm_idx_mutex);
1700 0 : }
1701 :
1702 : /**
1703 : * cik_get_xclk - get the xclk
1704 : *
1705 : * @rdev: radeon_device pointer
1706 : *
1707 : * Returns the reference clock used by the gfx engine
1708 : * (CIK).
1709 : */
1710 0 : u32 cik_get_xclk(struct radeon_device *rdev)
1711 : {
1712 0 : u32 reference_clock = rdev->clock.spll.reference_freq;
1713 :
1714 0 : if (rdev->flags & RADEON_IS_IGP) {
1715 0 : if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1716 0 : return reference_clock / 2;
1717 : } else {
1718 0 : if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
1719 0 : return reference_clock / 4;
1720 : }
1721 0 : return reference_clock;
1722 0 : }
1723 :
1724 : /**
1725 : * cik_mm_rdoorbell - read a doorbell dword
1726 : *
1727 : * @rdev: radeon_device pointer
1728 : * @index: doorbell index
1729 : *
1730 : * Returns the value in the doorbell aperture at the
1731 : * requested doorbell index (CIK).
1732 : */
1733 0 : u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)
1734 : {
1735 0 : if (index < rdev->doorbell.num_doorbells) {
1736 0 : return bus_space_read_4(rdev->memt, rdev->doorbell.bsh, index);
1737 : } else {
1738 0 : DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
1739 0 : return 0;
1740 : }
1741 0 : }
1742 :
1743 : /**
1744 : * cik_mm_wdoorbell - write a doorbell dword
1745 : *
1746 : * @rdev: radeon_device pointer
1747 : * @index: doorbell index
1748 : * @v: value to write
1749 : *
1750 : * Writes @v to the doorbell aperture at the
1751 : * requested doorbell index (CIK).
1752 : */
1753 0 : void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
1754 : {
1755 0 : if (index < rdev->doorbell.num_doorbells) {
1756 0 : bus_space_write_4(rdev->memt, rdev->doorbell.bsh, index, v);
1757 0 : } else {
1758 0 : DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
1759 : }
1760 0 : }
1761 :
1762 : #define BONAIRE_IO_MC_REGS_SIZE 36
1763 :
1764 : static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
1765 : {
1766 : {0x00000070, 0x04400000},
1767 : {0x00000071, 0x80c01803},
1768 : {0x00000072, 0x00004004},
1769 : {0x00000073, 0x00000100},
1770 : {0x00000074, 0x00ff0000},
1771 : {0x00000075, 0x34000000},
1772 : {0x00000076, 0x08000014},
1773 : {0x00000077, 0x00cc08ec},
1774 : {0x00000078, 0x00000400},
1775 : {0x00000079, 0x00000000},
1776 : {0x0000007a, 0x04090000},
1777 : {0x0000007c, 0x00000000},
1778 : {0x0000007e, 0x4408a8e8},
1779 : {0x0000007f, 0x00000304},
1780 : {0x00000080, 0x00000000},
1781 : {0x00000082, 0x00000001},
1782 : {0x00000083, 0x00000002},
1783 : {0x00000084, 0xf3e4f400},
1784 : {0x00000085, 0x052024e3},
1785 : {0x00000087, 0x00000000},
1786 : {0x00000088, 0x01000000},
1787 : {0x0000008a, 0x1c0a0000},
1788 : {0x0000008b, 0xff010000},
1789 : {0x0000008d, 0xffffefff},
1790 : {0x0000008e, 0xfff3efff},
1791 : {0x0000008f, 0xfff3efbf},
1792 : {0x00000092, 0xf7ffffff},
1793 : {0x00000093, 0xffffff7f},
1794 : {0x00000095, 0x00101101},
1795 : {0x00000096, 0x00000fff},
1796 : {0x00000097, 0x00116fff},
1797 : {0x00000098, 0x60010000},
1798 : {0x00000099, 0x10010000},
1799 : {0x0000009a, 0x00006000},
1800 : {0x0000009b, 0x00001000},
1801 : {0x0000009f, 0x00b48000}
1802 : };
1803 :
1804 : #define HAWAII_IO_MC_REGS_SIZE 22
1805 :
1806 : static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
1807 : {
1808 : {0x0000007d, 0x40000000},
1809 : {0x0000007e, 0x40180304},
1810 : {0x0000007f, 0x0000ff00},
1811 : {0x00000081, 0x00000000},
1812 : {0x00000083, 0x00000800},
1813 : {0x00000086, 0x00000000},
1814 : {0x00000087, 0x00000100},
1815 : {0x00000088, 0x00020100},
1816 : {0x00000089, 0x00000000},
1817 : {0x0000008b, 0x00040000},
1818 : {0x0000008c, 0x00000100},
1819 : {0x0000008e, 0xff010000},
1820 : {0x00000090, 0xffffefff},
1821 : {0x00000091, 0xfff3efff},
1822 : {0x00000092, 0xfff3efbf},
1823 : {0x00000093, 0xf7ffffff},
1824 : {0x00000094, 0xffffff7f},
1825 : {0x00000095, 0x00000fff},
1826 : {0x00000096, 0x00116fff},
1827 : {0x00000097, 0x60010000},
1828 : {0x00000098, 0x10010000},
1829 : {0x0000009f, 0x00c79000}
1830 : };
1831 :
1832 :
1833 : /**
1834 : * cik_srbm_select - select specific register instances
1835 : *
1836 : * @rdev: radeon_device pointer
1837 : * @me: selected ME (micro engine)
1838 : * @pipe: pipe
1839 : * @queue: queue
1840 : * @vmid: VMID
1841 : *
1842 : * Switches the currently active registers instances. Some
1843 : * registers are instanced per VMID, others are instanced per
1844 : * me/pipe/queue combination.
1845 : */
1846 0 : static void cik_srbm_select(struct radeon_device *rdev,
1847 : u32 me, u32 pipe, u32 queue, u32 vmid)
1848 : {
1849 0 : u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
1850 0 : MEID(me & 0x3) |
1851 0 : VMID(vmid & 0xf) |
1852 0 : QUEUEID(queue & 0x7));
1853 0 : WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
1854 0 : }
1855 :
1856 : /* ucode loading */
1857 : /**
1858 : * ci_mc_load_microcode - load MC ucode into the hw
1859 : *
1860 : * @rdev: radeon_device pointer
1861 : *
1862 : * Load the GDDR MC ucode into the hw (CIK).
1863 : * Returns 0 on success, error on failure.
1864 : */
1865 0 : int ci_mc_load_microcode(struct radeon_device *rdev)
1866 : {
1867 : const __be32 *fw_data = NULL;
1868 : const __le32 *new_fw_data = NULL;
1869 : u32 running, blackout = 0, tmp;
1870 : u32 *io_mc_regs = NULL;
1871 : const __le32 *new_io_mc_regs = NULL;
1872 : int i, regs_size, ucode_size;
1873 :
1874 0 : if (!rdev->mc_fw)
1875 0 : return -EINVAL;
1876 :
1877 0 : if (rdev->new_fw) {
1878 : const struct mc_firmware_header_v1_0 *hdr =
1879 0 : (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1880 :
1881 0 : radeon_ucode_print_mc_hdr(&hdr->header);
1882 :
1883 0 : regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1884 0 : new_io_mc_regs = (const __le32 *)
1885 0 : (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1886 0 : ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1887 0 : new_fw_data = (const __le32 *)
1888 0 : (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1889 0 : } else {
1890 0 : ucode_size = rdev->mc_fw->size / 4;
1891 :
1892 0 : switch (rdev->family) {
1893 : case CHIP_BONAIRE:
1894 : io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1895 : regs_size = BONAIRE_IO_MC_REGS_SIZE;
1896 0 : break;
1897 : case CHIP_HAWAII:
1898 : io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1899 : regs_size = HAWAII_IO_MC_REGS_SIZE;
1900 0 : break;
1901 : default:
1902 0 : return -EINVAL;
1903 : }
1904 0 : fw_data = (const __be32 *)rdev->mc_fw->data;
1905 : }
1906 :
1907 0 : running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1908 :
1909 0 : if (running == 0) {
1910 0 : if (running) {
1911 0 : blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1912 0 : WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1913 0 : }
1914 :
1915 : /* reset the engine and set to writable */
1916 0 : WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1917 0 : WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1918 :
1919 : /* load mc io regs */
1920 0 : for (i = 0; i < regs_size; i++) {
1921 0 : if (rdev->new_fw) {
1922 0 : WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1923 0 : WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1924 0 : } else {
1925 0 : WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1926 0 : WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1927 : }
1928 : }
1929 :
1930 0 : tmp = RREG32(MC_SEQ_MISC0);
1931 0 : if ((rdev->pdev->device == 0x6649) && ((tmp & 0xff00) == 0x5600)) {
1932 0 : WREG32(MC_SEQ_IO_DEBUG_INDEX, 5);
1933 0 : WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023);
1934 0 : WREG32(MC_SEQ_IO_DEBUG_INDEX, 9);
1935 0 : WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0);
1936 0 : }
1937 :
1938 : /* load the MC ucode */
1939 0 : for (i = 0; i < ucode_size; i++) {
1940 0 : if (rdev->new_fw)
1941 0 : WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1942 : else
1943 0 : WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1944 : }
1945 :
1946 : /* put the engine back into the active state */
1947 0 : WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1948 0 : WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1949 0 : WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1950 :
1951 : /* wait for training to complete */
1952 0 : for (i = 0; i < rdev->usec_timeout; i++) {
1953 0 : if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1954 : break;
1955 0 : udelay(1);
1956 : }
1957 0 : for (i = 0; i < rdev->usec_timeout; i++) {
1958 0 : if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1959 : break;
1960 0 : udelay(1);
1961 : }
1962 :
1963 0 : if (running)
1964 0 : WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
1965 : }
1966 :
1967 0 : return 0;
1968 0 : }
1969 :
1970 : /**
1971 : * cik_init_microcode - load ucode images from disk
1972 : *
1973 : * @rdev: radeon_device pointer
1974 : *
1975 : * Use the firmware interface to load the ucode images into
1976 : * the driver (not loaded into hw).
1977 : * Returns 0 on success, error on failure.
1978 : */
1979 0 : static int cik_init_microcode(struct radeon_device *rdev)
1980 : {
1981 : const char *chip_name;
1982 : const char *new_chip_name;
1983 : size_t pfp_req_size, me_req_size, ce_req_size,
1984 : mec_req_size, rlc_req_size, mc_req_size = 0,
1985 : sdma_req_size, smc_req_size = 0, mc2_req_size = 0;
1986 0 : char fw_name[30];
1987 : int new_fw = 0;
1988 : int err;
1989 : int num_fw;
1990 :
1991 : DRM_DEBUG("\n");
1992 :
1993 0 : switch (rdev->family) {
1994 : case CHIP_BONAIRE:
1995 : chip_name = "BONAIRE";
1996 : new_chip_name = "bonaire";
1997 : pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1998 : me_req_size = CIK_ME_UCODE_SIZE * 4;
1999 : ce_req_size = CIK_CE_UCODE_SIZE * 4;
2000 : mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2001 : rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
2002 : mc_req_size = BONAIRE_MC_UCODE_SIZE * 4;
2003 : mc2_req_size = BONAIRE_MC2_UCODE_SIZE * 4;
2004 : sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2005 : smc_req_size = roundup2(BONAIRE_SMC_UCODE_SIZE, 4);
2006 : num_fw = 8;
2007 0 : break;
2008 : case CHIP_HAWAII:
2009 : chip_name = "HAWAII";
2010 : new_chip_name = "hawaii";
2011 : pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2012 : me_req_size = CIK_ME_UCODE_SIZE * 4;
2013 : ce_req_size = CIK_CE_UCODE_SIZE * 4;
2014 : mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2015 : rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
2016 : mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
2017 : mc2_req_size = HAWAII_MC2_UCODE_SIZE * 4;
2018 : sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2019 : smc_req_size = roundup2(HAWAII_SMC_UCODE_SIZE, 4);
2020 : num_fw = 8;
2021 0 : break;
2022 : case CHIP_KAVERI:
2023 : chip_name = "KAVERI";
2024 : new_chip_name = "kaveri";
2025 : pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2026 : me_req_size = CIK_ME_UCODE_SIZE * 4;
2027 : ce_req_size = CIK_CE_UCODE_SIZE * 4;
2028 : mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2029 : rlc_req_size = KV_RLC_UCODE_SIZE * 4;
2030 : sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2031 : num_fw = 7;
2032 0 : break;
2033 : case CHIP_KABINI:
2034 : chip_name = "KABINI";
2035 : new_chip_name = "kabini";
2036 : pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2037 : me_req_size = CIK_ME_UCODE_SIZE * 4;
2038 : ce_req_size = CIK_CE_UCODE_SIZE * 4;
2039 : mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2040 : rlc_req_size = KB_RLC_UCODE_SIZE * 4;
2041 : sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2042 : num_fw = 6;
2043 0 : break;
2044 : case CHIP_MULLINS:
2045 : chip_name = "MULLINS";
2046 : new_chip_name = "mullins";
2047 : pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
2048 : me_req_size = CIK_ME_UCODE_SIZE * 4;
2049 : ce_req_size = CIK_CE_UCODE_SIZE * 4;
2050 : mec_req_size = CIK_MEC_UCODE_SIZE * 4;
2051 : rlc_req_size = ML_RLC_UCODE_SIZE * 4;
2052 : sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
2053 : num_fw = 6;
2054 0 : break;
2055 0 : default: BUG();
2056 : }
2057 :
2058 : DRM_INFO("Loading %s Microcode\n", new_chip_name);
2059 :
2060 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
2061 0 : err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2062 0 : if (err) {
2063 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2064 0 : err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2065 0 : if (err)
2066 : goto out;
2067 0 : if (rdev->pfp_fw->size != pfp_req_size) {
2068 0 : printk(KERN_ERR
2069 : "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2070 : rdev->pfp_fw->size, fw_name);
2071 : err = -EINVAL;
2072 0 : goto out;
2073 : }
2074 : } else {
2075 0 : err = radeon_ucode_validate(rdev->pfp_fw);
2076 0 : if (err) {
2077 0 : printk(KERN_ERR
2078 : "cik_fw: validation failed for firmware \"%s\"\n",
2079 : fw_name);
2080 0 : goto out;
2081 : } else {
2082 : new_fw++;
2083 : }
2084 : }
2085 :
2086 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
2087 0 : err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2088 0 : if (err) {
2089 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2090 0 : err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2091 0 : if (err)
2092 : goto out;
2093 0 : if (rdev->me_fw->size != me_req_size) {
2094 0 : printk(KERN_ERR
2095 : "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2096 : rdev->me_fw->size, fw_name);
2097 : err = -EINVAL;
2098 0 : }
2099 : } else {
2100 0 : err = radeon_ucode_validate(rdev->me_fw);
2101 0 : if (err) {
2102 0 : printk(KERN_ERR
2103 : "cik_fw: validation failed for firmware \"%s\"\n",
2104 : fw_name);
2105 0 : goto out;
2106 : } else {
2107 0 : new_fw++;
2108 : }
2109 : }
2110 :
2111 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
2112 0 : err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
2113 0 : if (err) {
2114 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
2115 0 : err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
2116 0 : if (err)
2117 : goto out;
2118 0 : if (rdev->ce_fw->size != ce_req_size) {
2119 0 : printk(KERN_ERR
2120 : "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2121 : rdev->ce_fw->size, fw_name);
2122 : err = -EINVAL;
2123 0 : }
2124 : } else {
2125 0 : err = radeon_ucode_validate(rdev->ce_fw);
2126 0 : if (err) {
2127 0 : printk(KERN_ERR
2128 : "cik_fw: validation failed for firmware \"%s\"\n",
2129 : fw_name);
2130 0 : goto out;
2131 : } else {
2132 0 : new_fw++;
2133 : }
2134 : }
2135 :
2136 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", new_chip_name);
2137 0 : err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
2138 0 : if (err) {
2139 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
2140 0 : err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
2141 0 : if (err)
2142 : goto out;
2143 0 : if (rdev->mec_fw->size != mec_req_size) {
2144 0 : printk(KERN_ERR
2145 : "cik_cp: Bogus length %zu in firmware \"%s\"\n",
2146 : rdev->mec_fw->size, fw_name);
2147 : err = -EINVAL;
2148 0 : }
2149 : } else {
2150 0 : err = radeon_ucode_validate(rdev->mec_fw);
2151 0 : if (err) {
2152 0 : printk(KERN_ERR
2153 : "cik_fw: validation failed for firmware \"%s\"\n",
2154 : fw_name);
2155 0 : goto out;
2156 : } else {
2157 0 : new_fw++;
2158 : }
2159 : }
2160 :
2161 0 : if (rdev->family == CHIP_KAVERI) {
2162 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", new_chip_name);
2163 0 : err = request_firmware(&rdev->mec2_fw, fw_name, rdev->dev);
2164 0 : if (err) {
2165 : goto out;
2166 : } else {
2167 0 : err = radeon_ucode_validate(rdev->mec2_fw);
2168 0 : if (err) {
2169 : goto out;
2170 : } else {
2171 0 : new_fw++;
2172 : }
2173 : }
2174 0 : }
2175 :
2176 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
2177 0 : err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2178 0 : if (err) {
2179 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
2180 0 : err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2181 0 : if (err)
2182 : goto out;
2183 0 : if (rdev->rlc_fw->size != rlc_req_size) {
2184 0 : printk(KERN_ERR
2185 : "cik_rlc: Bogus length %zu in firmware \"%s\"\n",
2186 : rdev->rlc_fw->size, fw_name);
2187 : err = -EINVAL;
2188 0 : }
2189 : } else {
2190 0 : err = radeon_ucode_validate(rdev->rlc_fw);
2191 0 : if (err) {
2192 0 : printk(KERN_ERR
2193 : "cik_fw: validation failed for firmware \"%s\"\n",
2194 : fw_name);
2195 0 : goto out;
2196 : } else {
2197 0 : new_fw++;
2198 : }
2199 : }
2200 :
2201 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", new_chip_name);
2202 0 : err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
2203 0 : if (err) {
2204 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
2205 0 : err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
2206 0 : if (err)
2207 : goto out;
2208 0 : if (rdev->sdma_fw->size != sdma_req_size) {
2209 0 : printk(KERN_ERR
2210 : "cik_sdma: Bogus length %zu in firmware \"%s\"\n",
2211 : rdev->sdma_fw->size, fw_name);
2212 : err = -EINVAL;
2213 0 : }
2214 : } else {
2215 0 : err = radeon_ucode_validate(rdev->sdma_fw);
2216 0 : if (err) {
2217 0 : printk(KERN_ERR
2218 : "cik_fw: validation failed for firmware \"%s\"\n",
2219 : fw_name);
2220 0 : goto out;
2221 : } else {
2222 0 : new_fw++;
2223 : }
2224 : }
2225 :
2226 : /* No SMC, MC ucode on APUs */
2227 0 : if (!(rdev->flags & RADEON_IS_IGP)) {
2228 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
2229 0 : err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2230 0 : if (err) {
2231 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
2232 0 : err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2233 0 : if (err) {
2234 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
2235 0 : err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
2236 0 : if (err)
2237 : goto out;
2238 : }
2239 0 : if ((rdev->mc_fw->size != mc_req_size) &&
2240 0 : (rdev->mc_fw->size != mc2_req_size)){
2241 0 : printk(KERN_ERR
2242 : "cik_mc: Bogus length %zu in firmware \"%s\"\n",
2243 : rdev->mc_fw->size, fw_name);
2244 : err = -EINVAL;
2245 0 : }
2246 : DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
2247 : } else {
2248 0 : err = radeon_ucode_validate(rdev->mc_fw);
2249 0 : if (err) {
2250 0 : printk(KERN_ERR
2251 : "cik_fw: validation failed for firmware \"%s\"\n",
2252 : fw_name);
2253 0 : goto out;
2254 : } else {
2255 0 : new_fw++;
2256 : }
2257 : }
2258 :
2259 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
2260 0 : err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2261 0 : if (err) {
2262 0 : snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
2263 0 : err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2264 0 : if (err) {
2265 0 : printk(KERN_ERR
2266 : "smc: error loading firmware \"%s\"\n",
2267 : fw_name);
2268 0 : release_firmware(rdev->smc_fw);
2269 0 : rdev->smc_fw = NULL;
2270 : err = 0;
2271 0 : } else if (rdev->smc_fw->size != smc_req_size) {
2272 0 : printk(KERN_ERR
2273 : "cik_smc: Bogus length %zu in firmware \"%s\"\n",
2274 : rdev->smc_fw->size, fw_name);
2275 : err = -EINVAL;
2276 0 : }
2277 : } else {
2278 0 : err = radeon_ucode_validate(rdev->smc_fw);
2279 0 : if (err) {
2280 0 : printk(KERN_ERR
2281 : "cik_fw: validation failed for firmware \"%s\"\n",
2282 : fw_name);
2283 0 : goto out;
2284 : } else {
2285 0 : new_fw++;
2286 : }
2287 : }
2288 : }
2289 :
2290 0 : if (new_fw == 0) {
2291 0 : rdev->new_fw = false;
2292 0 : } else if (new_fw < num_fw) {
2293 0 : printk(KERN_ERR "ci_fw: mixing new and old firmware!\n");
2294 : err = -EINVAL;
2295 0 : } else {
2296 0 : rdev->new_fw = true;
2297 : }
2298 :
2299 : out:
2300 0 : if (err) {
2301 0 : if (err != -EINVAL)
2302 0 : printk(KERN_ERR
2303 : "cik_cp: Failed to load firmware \"%s\"\n",
2304 : fw_name);
2305 0 : release_firmware(rdev->pfp_fw);
2306 0 : rdev->pfp_fw = NULL;
2307 0 : release_firmware(rdev->me_fw);
2308 0 : rdev->me_fw = NULL;
2309 0 : release_firmware(rdev->ce_fw);
2310 0 : rdev->ce_fw = NULL;
2311 0 : release_firmware(rdev->mec_fw);
2312 0 : rdev->mec_fw = NULL;
2313 0 : release_firmware(rdev->mec2_fw);
2314 0 : rdev->mec2_fw = NULL;
2315 0 : release_firmware(rdev->rlc_fw);
2316 0 : rdev->rlc_fw = NULL;
2317 0 : release_firmware(rdev->sdma_fw);
2318 0 : rdev->sdma_fw = NULL;
2319 0 : release_firmware(rdev->mc_fw);
2320 0 : rdev->mc_fw = NULL;
2321 0 : release_firmware(rdev->smc_fw);
2322 0 : rdev->smc_fw = NULL;
2323 0 : }
2324 0 : return err;
2325 0 : }
2326 :
2327 : /*
2328 : * Core functions
2329 : */
2330 : /**
2331 : * cik_tiling_mode_table_init - init the hw tiling table
2332 : *
2333 : * @rdev: radeon_device pointer
2334 : *
2335 : * Starting with SI, the tiling setup is done globally in a
2336 : * set of 32 tiling modes. Rather than selecting each set of
2337 : * parameters per surface as on older asics, we just select
2338 : * which index in the tiling table we want to use, and the
2339 : * surface uses those parameters (CIK).
2340 : */
2341 0 : static void cik_tiling_mode_table_init(struct radeon_device *rdev)
2342 : {
2343 : const u32 num_tile_mode_states = 32;
2344 : const u32 num_secondary_tile_mode_states = 16;
2345 : u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
2346 : u32 num_pipe_configs;
2347 0 : u32 num_rbs = rdev->config.cik.max_backends_per_se *
2348 0 : rdev->config.cik.max_shader_engines;
2349 :
2350 0 : switch (rdev->config.cik.mem_row_size_in_kb) {
2351 : case 1:
2352 : split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2353 0 : break;
2354 : case 2:
2355 : default:
2356 : split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2357 0 : break;
2358 : case 4:
2359 : split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2360 0 : break;
2361 : }
2362 :
2363 0 : num_pipe_configs = rdev->config.cik.max_tile_pipes;
2364 0 : if (num_pipe_configs > 8)
2365 : num_pipe_configs = 16;
2366 :
2367 0 : if (num_pipe_configs == 16) {
2368 0 : for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2369 0 : switch (reg_offset) {
2370 : case 0:
2371 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2372 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2373 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2374 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2375 0 : break;
2376 : case 1:
2377 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2378 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2379 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2380 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2381 0 : break;
2382 : case 2:
2383 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2384 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2385 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2386 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2387 0 : break;
2388 : case 3:
2389 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2390 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2391 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2392 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2393 0 : break;
2394 : case 4:
2395 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2396 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2397 0 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2398 0 : TILE_SPLIT(split_equal_to_row_size));
2399 0 : break;
2400 : case 5:
2401 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2402 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2403 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2404 0 : break;
2405 : case 6:
2406 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2407 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2408 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2409 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2410 0 : break;
2411 : case 7:
2412 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2413 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2414 0 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2415 0 : TILE_SPLIT(split_equal_to_row_size));
2416 0 : break;
2417 : case 8:
2418 : gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2419 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2420 0 : break;
2421 : case 9:
2422 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2423 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2424 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2425 0 : break;
2426 : case 10:
2427 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2428 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2429 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2430 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2431 0 : break;
2432 : case 11:
2433 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2434 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2435 : PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2436 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2437 0 : break;
2438 : case 12:
2439 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2440 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2441 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2442 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2443 0 : break;
2444 : case 13:
2445 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2446 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2447 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2448 0 : break;
2449 : case 14:
2450 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2451 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2452 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2453 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2454 0 : break;
2455 : case 16:
2456 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2457 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2458 : PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2459 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2460 0 : break;
2461 : case 17:
2462 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2463 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2464 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2465 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2466 0 : break;
2467 : case 27:
2468 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2469 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2470 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2471 0 : break;
2472 : case 28:
2473 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2474 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2475 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2476 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2477 0 : break;
2478 : case 29:
2479 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2480 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2481 : PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2482 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2483 0 : break;
2484 : case 30:
2485 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2486 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2487 : PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2488 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2489 0 : break;
2490 : default:
2491 : gb_tile_moden = 0;
2492 0 : break;
2493 : }
2494 0 : rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2495 0 : WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2496 : }
2497 0 : for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2498 0 : switch (reg_offset) {
2499 : case 0:
2500 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2501 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2502 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2503 : NUM_BANKS(ADDR_SURF_16_BANK));
2504 0 : break;
2505 : case 1:
2506 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2507 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2508 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2509 : NUM_BANKS(ADDR_SURF_16_BANK));
2510 0 : break;
2511 : case 2:
2512 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2513 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2514 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2515 : NUM_BANKS(ADDR_SURF_16_BANK));
2516 0 : break;
2517 : case 3:
2518 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2519 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2520 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2521 : NUM_BANKS(ADDR_SURF_16_BANK));
2522 0 : break;
2523 : case 4:
2524 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2525 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2526 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2527 : NUM_BANKS(ADDR_SURF_8_BANK));
2528 0 : break;
2529 : case 5:
2530 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2531 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2532 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2533 : NUM_BANKS(ADDR_SURF_4_BANK));
2534 0 : break;
2535 : case 6:
2536 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2537 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2538 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2539 : NUM_BANKS(ADDR_SURF_2_BANK));
2540 0 : break;
2541 : case 8:
2542 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2543 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2544 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2545 : NUM_BANKS(ADDR_SURF_16_BANK));
2546 0 : break;
2547 : case 9:
2548 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2549 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2550 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2551 : NUM_BANKS(ADDR_SURF_16_BANK));
2552 0 : break;
2553 : case 10:
2554 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2555 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2556 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2557 : NUM_BANKS(ADDR_SURF_16_BANK));
2558 0 : break;
2559 : case 11:
2560 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2561 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2562 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2563 : NUM_BANKS(ADDR_SURF_8_BANK));
2564 0 : break;
2565 : case 12:
2566 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2567 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2568 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2569 : NUM_BANKS(ADDR_SURF_4_BANK));
2570 0 : break;
2571 : case 13:
2572 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2573 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2574 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2575 : NUM_BANKS(ADDR_SURF_2_BANK));
2576 0 : break;
2577 : case 14:
2578 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2579 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2580 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2581 : NUM_BANKS(ADDR_SURF_2_BANK));
2582 0 : break;
2583 : default:
2584 : gb_tile_moden = 0;
2585 0 : break;
2586 : }
2587 0 : rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2588 0 : WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2589 : }
2590 0 : } else if (num_pipe_configs == 8) {
2591 0 : for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2592 0 : switch (reg_offset) {
2593 : case 0:
2594 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2595 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2596 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2597 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2598 0 : break;
2599 : case 1:
2600 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2601 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2602 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2603 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2604 0 : break;
2605 : case 2:
2606 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2607 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2608 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2609 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2610 0 : break;
2611 : case 3:
2612 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2613 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2614 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2615 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2616 0 : break;
2617 : case 4:
2618 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2619 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2620 0 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2621 0 : TILE_SPLIT(split_equal_to_row_size));
2622 0 : break;
2623 : case 5:
2624 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2625 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2626 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2627 0 : break;
2628 : case 6:
2629 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2630 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2631 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2632 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2633 0 : break;
2634 : case 7:
2635 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2636 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2637 0 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2638 0 : TILE_SPLIT(split_equal_to_row_size));
2639 0 : break;
2640 : case 8:
2641 : gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2642 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2643 0 : break;
2644 : case 9:
2645 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2646 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2647 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2648 0 : break;
2649 : case 10:
2650 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2651 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2652 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2653 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2654 0 : break;
2655 : case 11:
2656 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2657 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2658 : PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2659 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2660 0 : break;
2661 : case 12:
2662 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2663 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2664 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2665 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2666 0 : break;
2667 : case 13:
2668 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2669 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2670 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2671 0 : break;
2672 : case 14:
2673 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2674 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2675 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2676 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2677 0 : break;
2678 : case 16:
2679 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2680 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2681 : PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2682 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2683 0 : break;
2684 : case 17:
2685 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2686 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2687 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2688 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2689 0 : break;
2690 : case 27:
2691 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2692 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2693 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2694 0 : break;
2695 : case 28:
2696 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2697 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2698 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2699 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2700 0 : break;
2701 : case 29:
2702 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2703 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2704 : PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2705 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2706 0 : break;
2707 : case 30:
2708 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2709 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2710 : PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2711 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2712 0 : break;
2713 : default:
2714 : gb_tile_moden = 0;
2715 0 : break;
2716 : }
2717 0 : rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2718 0 : WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2719 : }
2720 0 : for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2721 0 : switch (reg_offset) {
2722 : case 0:
2723 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2724 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2725 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2726 : NUM_BANKS(ADDR_SURF_16_BANK));
2727 0 : break;
2728 : case 1:
2729 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2730 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2731 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2732 : NUM_BANKS(ADDR_SURF_16_BANK));
2733 0 : break;
2734 : case 2:
2735 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2736 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2737 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2738 : NUM_BANKS(ADDR_SURF_16_BANK));
2739 0 : break;
2740 : case 3:
2741 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2742 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2743 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2744 : NUM_BANKS(ADDR_SURF_16_BANK));
2745 0 : break;
2746 : case 4:
2747 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2748 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2749 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2750 : NUM_BANKS(ADDR_SURF_8_BANK));
2751 0 : break;
2752 : case 5:
2753 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2754 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2755 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2756 : NUM_BANKS(ADDR_SURF_4_BANK));
2757 0 : break;
2758 : case 6:
2759 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2760 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2761 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2762 : NUM_BANKS(ADDR_SURF_2_BANK));
2763 0 : break;
2764 : case 8:
2765 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2766 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2767 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2768 : NUM_BANKS(ADDR_SURF_16_BANK));
2769 0 : break;
2770 : case 9:
2771 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2772 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2773 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2774 : NUM_BANKS(ADDR_SURF_16_BANK));
2775 0 : break;
2776 : case 10:
2777 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2778 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2779 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2780 : NUM_BANKS(ADDR_SURF_16_BANK));
2781 0 : break;
2782 : case 11:
2783 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2784 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2785 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2786 : NUM_BANKS(ADDR_SURF_16_BANK));
2787 0 : break;
2788 : case 12:
2789 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2790 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2791 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2792 : NUM_BANKS(ADDR_SURF_8_BANK));
2793 0 : break;
2794 : case 13:
2795 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2796 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2797 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2798 : NUM_BANKS(ADDR_SURF_4_BANK));
2799 0 : break;
2800 : case 14:
2801 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2802 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2803 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2804 : NUM_BANKS(ADDR_SURF_2_BANK));
2805 0 : break;
2806 : default:
2807 : gb_tile_moden = 0;
2808 0 : break;
2809 : }
2810 0 : rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2811 0 : WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2812 : }
2813 0 : } else if (num_pipe_configs == 4) {
2814 0 : if (num_rbs == 4) {
2815 0 : for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2816 0 : switch (reg_offset) {
2817 : case 0:
2818 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2819 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2820 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2821 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2822 0 : break;
2823 : case 1:
2824 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2825 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2826 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2827 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2828 0 : break;
2829 : case 2:
2830 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2831 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2832 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2833 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2834 0 : break;
2835 : case 3:
2836 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2837 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2838 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2839 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2840 0 : break;
2841 : case 4:
2842 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2843 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2844 0 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2845 0 : TILE_SPLIT(split_equal_to_row_size));
2846 0 : break;
2847 : case 5:
2848 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2849 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2850 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2851 0 : break;
2852 : case 6:
2853 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2854 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2855 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2856 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2857 0 : break;
2858 : case 7:
2859 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2860 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2861 0 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2862 0 : TILE_SPLIT(split_equal_to_row_size));
2863 0 : break;
2864 : case 8:
2865 : gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2866 : PIPE_CONFIG(ADDR_SURF_P4_16x16));
2867 0 : break;
2868 : case 9:
2869 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2870 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2871 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2872 0 : break;
2873 : case 10:
2874 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2875 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2876 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2877 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2878 0 : break;
2879 : case 11:
2880 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2881 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2882 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2883 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2884 0 : break;
2885 : case 12:
2886 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2887 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2888 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2889 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2890 0 : break;
2891 : case 13:
2892 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2893 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2894 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2895 0 : break;
2896 : case 14:
2897 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2898 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2899 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2900 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2901 0 : break;
2902 : case 16:
2903 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2904 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2905 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2906 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2907 0 : break;
2908 : case 17:
2909 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2910 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2911 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2912 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2913 0 : break;
2914 : case 27:
2915 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2916 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2917 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2918 0 : break;
2919 : case 28:
2920 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2921 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2922 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2923 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2924 0 : break;
2925 : case 29:
2926 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2927 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2928 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2929 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2930 0 : break;
2931 : case 30:
2932 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2933 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2934 : PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2935 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2936 0 : break;
2937 : default:
2938 : gb_tile_moden = 0;
2939 0 : break;
2940 : }
2941 0 : rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2942 0 : WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2943 : }
2944 0 : } else if (num_rbs < 4) {
2945 0 : for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2946 0 : switch (reg_offset) {
2947 : case 0:
2948 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2949 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2950 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2951 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2952 0 : break;
2953 : case 1:
2954 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2955 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2956 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2957 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2958 0 : break;
2959 : case 2:
2960 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2961 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2962 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2963 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2964 0 : break;
2965 : case 3:
2966 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2967 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2968 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2969 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2970 0 : break;
2971 : case 4:
2972 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2973 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2974 0 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2975 0 : TILE_SPLIT(split_equal_to_row_size));
2976 0 : break;
2977 : case 5:
2978 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2979 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2980 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2981 0 : break;
2982 : case 6:
2983 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2984 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2985 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2986 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2987 0 : break;
2988 : case 7:
2989 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2990 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2991 0 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2992 0 : TILE_SPLIT(split_equal_to_row_size));
2993 0 : break;
2994 : case 8:
2995 : gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2996 : PIPE_CONFIG(ADDR_SURF_P4_8x16));
2997 0 : break;
2998 : case 9:
2999 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3000 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3001 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
3002 0 : break;
3003 : case 10:
3004 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3005 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3006 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3007 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3008 0 : break;
3009 : case 11:
3010 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3011 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3012 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3013 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3014 0 : break;
3015 : case 12:
3016 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3017 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3018 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3019 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3020 0 : break;
3021 : case 13:
3022 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3023 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3024 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
3025 0 : break;
3026 : case 14:
3027 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3028 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3029 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3030 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3031 0 : break;
3032 : case 16:
3033 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3034 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3035 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3036 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3037 0 : break;
3038 : case 17:
3039 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3040 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3041 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3042 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3043 0 : break;
3044 : case 27:
3045 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3046 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3047 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
3048 0 : break;
3049 : case 28:
3050 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3051 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3052 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3053 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3054 0 : break;
3055 : case 29:
3056 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3057 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3058 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3059 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3060 0 : break;
3061 : case 30:
3062 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3063 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3064 : PIPE_CONFIG(ADDR_SURF_P4_8x16) |
3065 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3066 0 : break;
3067 : default:
3068 : gb_tile_moden = 0;
3069 0 : break;
3070 : }
3071 0 : rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
3072 0 : WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
3073 : }
3074 : }
3075 0 : for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
3076 0 : switch (reg_offset) {
3077 : case 0:
3078 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3079 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3080 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3081 : NUM_BANKS(ADDR_SURF_16_BANK));
3082 0 : break;
3083 : case 1:
3084 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3085 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3086 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3087 : NUM_BANKS(ADDR_SURF_16_BANK));
3088 0 : break;
3089 : case 2:
3090 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3091 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3092 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3093 : NUM_BANKS(ADDR_SURF_16_BANK));
3094 0 : break;
3095 : case 3:
3096 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3097 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3098 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3099 : NUM_BANKS(ADDR_SURF_16_BANK));
3100 0 : break;
3101 : case 4:
3102 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3103 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3104 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3105 : NUM_BANKS(ADDR_SURF_16_BANK));
3106 0 : break;
3107 : case 5:
3108 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3109 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3110 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3111 : NUM_BANKS(ADDR_SURF_8_BANK));
3112 0 : break;
3113 : case 6:
3114 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3115 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3116 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3117 : NUM_BANKS(ADDR_SURF_4_BANK));
3118 0 : break;
3119 : case 8:
3120 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3121 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3122 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3123 : NUM_BANKS(ADDR_SURF_16_BANK));
3124 0 : break;
3125 : case 9:
3126 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3127 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3128 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3129 : NUM_BANKS(ADDR_SURF_16_BANK));
3130 0 : break;
3131 : case 10:
3132 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3133 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3134 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3135 : NUM_BANKS(ADDR_SURF_16_BANK));
3136 0 : break;
3137 : case 11:
3138 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3139 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3140 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3141 : NUM_BANKS(ADDR_SURF_16_BANK));
3142 0 : break;
3143 : case 12:
3144 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3145 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3146 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3147 : NUM_BANKS(ADDR_SURF_16_BANK));
3148 0 : break;
3149 : case 13:
3150 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3151 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3152 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3153 : NUM_BANKS(ADDR_SURF_8_BANK));
3154 0 : break;
3155 : case 14:
3156 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3157 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3158 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3159 : NUM_BANKS(ADDR_SURF_4_BANK));
3160 0 : break;
3161 : default:
3162 : gb_tile_moden = 0;
3163 0 : break;
3164 : }
3165 0 : rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
3166 0 : WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
3167 : }
3168 0 : } else if (num_pipe_configs == 2) {
3169 0 : for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
3170 0 : switch (reg_offset) {
3171 : case 0:
3172 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3173 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3174 : PIPE_CONFIG(ADDR_SURF_P2) |
3175 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
3176 0 : break;
3177 : case 1:
3178 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3179 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3180 : PIPE_CONFIG(ADDR_SURF_P2) |
3181 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
3182 0 : break;
3183 : case 2:
3184 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3185 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3186 : PIPE_CONFIG(ADDR_SURF_P2) |
3187 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
3188 0 : break;
3189 : case 3:
3190 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3191 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3192 : PIPE_CONFIG(ADDR_SURF_P2) |
3193 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
3194 0 : break;
3195 : case 4:
3196 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3197 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3198 0 : PIPE_CONFIG(ADDR_SURF_P2) |
3199 0 : TILE_SPLIT(split_equal_to_row_size));
3200 0 : break;
3201 : case 5:
3202 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3203 : PIPE_CONFIG(ADDR_SURF_P2) |
3204 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3205 0 : break;
3206 : case 6:
3207 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3208 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3209 : PIPE_CONFIG(ADDR_SURF_P2) |
3210 : TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
3211 0 : break;
3212 : case 7:
3213 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3214 : MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
3215 0 : PIPE_CONFIG(ADDR_SURF_P2) |
3216 0 : TILE_SPLIT(split_equal_to_row_size));
3217 0 : break;
3218 : case 8:
3219 : gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3220 : PIPE_CONFIG(ADDR_SURF_P2);
3221 0 : break;
3222 : case 9:
3223 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3224 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3225 : PIPE_CONFIG(ADDR_SURF_P2));
3226 0 : break;
3227 : case 10:
3228 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3229 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3230 : PIPE_CONFIG(ADDR_SURF_P2) |
3231 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3232 0 : break;
3233 : case 11:
3234 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3235 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3236 : PIPE_CONFIG(ADDR_SURF_P2) |
3237 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3238 0 : break;
3239 : case 12:
3240 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3241 : MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3242 : PIPE_CONFIG(ADDR_SURF_P2) |
3243 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3244 0 : break;
3245 : case 13:
3246 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3247 : PIPE_CONFIG(ADDR_SURF_P2) |
3248 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
3249 0 : break;
3250 : case 14:
3251 : gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3252 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3253 : PIPE_CONFIG(ADDR_SURF_P2) |
3254 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3255 0 : break;
3256 : case 16:
3257 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3258 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3259 : PIPE_CONFIG(ADDR_SURF_P2) |
3260 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3261 0 : break;
3262 : case 17:
3263 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3264 : MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3265 : PIPE_CONFIG(ADDR_SURF_P2) |
3266 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3267 0 : break;
3268 : case 27:
3269 : gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3270 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3271 : PIPE_CONFIG(ADDR_SURF_P2));
3272 0 : break;
3273 : case 28:
3274 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3275 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3276 : PIPE_CONFIG(ADDR_SURF_P2) |
3277 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3278 0 : break;
3279 : case 29:
3280 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3281 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3282 : PIPE_CONFIG(ADDR_SURF_P2) |
3283 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3284 0 : break;
3285 : case 30:
3286 : gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
3287 : MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3288 : PIPE_CONFIG(ADDR_SURF_P2) |
3289 : SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3290 0 : break;
3291 : default:
3292 : gb_tile_moden = 0;
3293 0 : break;
3294 : }
3295 0 : rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
3296 0 : WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
3297 : }
3298 0 : for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
3299 0 : switch (reg_offset) {
3300 : case 0:
3301 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3302 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3303 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3304 : NUM_BANKS(ADDR_SURF_16_BANK));
3305 0 : break;
3306 : case 1:
3307 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3308 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3309 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3310 : NUM_BANKS(ADDR_SURF_16_BANK));
3311 0 : break;
3312 : case 2:
3313 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3314 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3315 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3316 : NUM_BANKS(ADDR_SURF_16_BANK));
3317 0 : break;
3318 : case 3:
3319 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3320 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3321 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3322 : NUM_BANKS(ADDR_SURF_16_BANK));
3323 0 : break;
3324 : case 4:
3325 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3326 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3327 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3328 : NUM_BANKS(ADDR_SURF_16_BANK));
3329 0 : break;
3330 : case 5:
3331 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3332 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3333 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3334 : NUM_BANKS(ADDR_SURF_16_BANK));
3335 0 : break;
3336 : case 6:
3337 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3338 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3339 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3340 : NUM_BANKS(ADDR_SURF_8_BANK));
3341 0 : break;
3342 : case 8:
3343 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3344 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3345 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3346 : NUM_BANKS(ADDR_SURF_16_BANK));
3347 0 : break;
3348 : case 9:
3349 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3350 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3351 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3352 : NUM_BANKS(ADDR_SURF_16_BANK));
3353 0 : break;
3354 : case 10:
3355 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3356 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3357 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3358 : NUM_BANKS(ADDR_SURF_16_BANK));
3359 0 : break;
3360 : case 11:
3361 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3362 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3363 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3364 : NUM_BANKS(ADDR_SURF_16_BANK));
3365 0 : break;
3366 : case 12:
3367 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3368 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3369 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3370 : NUM_BANKS(ADDR_SURF_16_BANK));
3371 0 : break;
3372 : case 13:
3373 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3374 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3375 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3376 : NUM_BANKS(ADDR_SURF_16_BANK));
3377 0 : break;
3378 : case 14:
3379 : gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3380 : BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3381 : MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3382 : NUM_BANKS(ADDR_SURF_8_BANK));
3383 0 : break;
3384 : default:
3385 : gb_tile_moden = 0;
3386 0 : break;
3387 : }
3388 0 : rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
3389 0 : WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
3390 : }
3391 : } else
3392 0 : DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
3393 0 : }
3394 :
3395 : /**
3396 : * cik_select_se_sh - select which SE, SH to address
3397 : *
3398 : * @rdev: radeon_device pointer
3399 : * @se_num: shader engine to address
3400 : * @sh_num: sh block to address
3401 : *
3402 : * Select which SE, SH combinations to address. Certain
3403 : * registers are instanced per SE or SH. 0xffffffff means
3404 : * broadcast to all SEs or SHs (CIK).
3405 : */
3406 0 : static void cik_select_se_sh(struct radeon_device *rdev,
3407 : u32 se_num, u32 sh_num)
3408 : {
3409 : u32 data = INSTANCE_BROADCAST_WRITES;
3410 :
3411 0 : if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
3412 0 : data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
3413 0 : else if (se_num == 0xffffffff)
3414 0 : data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
3415 0 : else if (sh_num == 0xffffffff)
3416 0 : data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
3417 : else
3418 0 : data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3419 0 : WREG32(GRBM_GFX_INDEX, data);
3420 0 : }
3421 :
3422 : /**
3423 : * cik_create_bitmask - create a bitmask
3424 : *
3425 : * @bit_width: length of the mask
3426 : *
3427 : * create a variable length bit mask (CIK).
3428 : * Returns the bitmask.
3429 : */
3430 0 : static u32 cik_create_bitmask(u32 bit_width)
3431 : {
3432 : u32 i, mask = 0;
3433 :
3434 0 : for (i = 0; i < bit_width; i++) {
3435 0 : mask <<= 1;
3436 0 : mask |= 1;
3437 : }
3438 0 : return mask;
3439 : }
3440 :
3441 : /**
3442 : * cik_get_rb_disabled - computes the mask of disabled RBs
3443 : *
3444 : * @rdev: radeon_device pointer
3445 : * @max_rb_num: max RBs (render backends) for the asic
3446 : * @se_num: number of SEs (shader engines) for the asic
3447 : * @sh_per_se: number of SH blocks per SE for the asic
3448 : *
3449 : * Calculates the bitmask of disabled RBs (CIK).
3450 : * Returns the disabled RB bitmask.
3451 : */
3452 0 : static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3453 : u32 max_rb_num_per_se,
3454 : u32 sh_per_se)
3455 : {
3456 : u32 data, mask;
3457 :
3458 0 : data = RREG32(CC_RB_BACKEND_DISABLE);
3459 0 : if (data & 1)
3460 0 : data &= BACKEND_DISABLE_MASK;
3461 : else
3462 : data = 0;
3463 0 : data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3464 :
3465 0 : data >>= BACKEND_DISABLE_SHIFT;
3466 :
3467 0 : mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
3468 :
3469 0 : return data & mask;
3470 : }
3471 :
3472 : /**
3473 : * cik_setup_rb - setup the RBs on the asic
3474 : *
3475 : * @rdev: radeon_device pointer
3476 : * @se_num: number of SEs (shader engines) for the asic
3477 : * @sh_per_se: number of SH blocks per SE for the asic
3478 : * @max_rb_num: max RBs (render backends) for the asic
3479 : *
3480 : * Configures per-SE/SH RB registers (CIK).
3481 : */
3482 0 : static void cik_setup_rb(struct radeon_device *rdev,
3483 : u32 se_num, u32 sh_per_se,
3484 : u32 max_rb_num_per_se)
3485 : {
3486 : int i, j;
3487 : u32 data, mask;
3488 : u32 disabled_rbs = 0;
3489 : u32 enabled_rbs = 0;
3490 :
3491 0 : mutex_lock(&rdev->grbm_idx_mutex);
3492 0 : for (i = 0; i < se_num; i++) {
3493 0 : for (j = 0; j < sh_per_se; j++) {
3494 0 : cik_select_se_sh(rdev, i, j);
3495 0 : data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3496 0 : if (rdev->family == CHIP_HAWAII)
3497 0 : disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3498 : else
3499 0 : disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
3500 : }
3501 : }
3502 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3503 0 : mutex_unlock(&rdev->grbm_idx_mutex);
3504 :
3505 : mask = 1;
3506 0 : for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3507 0 : if (!(disabled_rbs & mask))
3508 0 : enabled_rbs |= mask;
3509 0 : mask <<= 1;
3510 : }
3511 :
3512 0 : rdev->config.cik.backend_enable_mask = enabled_rbs;
3513 :
3514 0 : mutex_lock(&rdev->grbm_idx_mutex);
3515 0 : for (i = 0; i < se_num; i++) {
3516 0 : cik_select_se_sh(rdev, i, 0xffffffff);
3517 : data = 0;
3518 0 : for (j = 0; j < sh_per_se; j++) {
3519 0 : switch (enabled_rbs & 3) {
3520 : case 0:
3521 0 : if (j == 0)
3522 0 : data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
3523 : else
3524 : data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
3525 : break;
3526 : case 1:
3527 0 : data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3528 0 : break;
3529 : case 2:
3530 0 : data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3531 0 : break;
3532 : case 3:
3533 : default:
3534 0 : data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3535 0 : break;
3536 : }
3537 0 : enabled_rbs >>= 2;
3538 : }
3539 0 : WREG32(PA_SC_RASTER_CONFIG, data);
3540 : }
3541 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3542 0 : mutex_unlock(&rdev->grbm_idx_mutex);
3543 0 : }
3544 :
3545 : /**
3546 : * cik_gpu_init - setup the 3D engine
3547 : *
3548 : * @rdev: radeon_device pointer
3549 : *
3550 : * Configures the 3D engine and tiling configuration
3551 : * registers so that the 3D engine is usable.
3552 : */
3553 0 : static void cik_gpu_init(struct radeon_device *rdev)
3554 : {
3555 0 : u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
3556 : u32 mc_shared_chmap, mc_arb_ramcfg;
3557 : u32 hdp_host_path_cntl;
3558 : u32 tmp;
3559 : int i, j;
3560 :
3561 0 : switch (rdev->family) {
3562 : case CHIP_BONAIRE:
3563 0 : rdev->config.cik.max_shader_engines = 2;
3564 0 : rdev->config.cik.max_tile_pipes = 4;
3565 0 : rdev->config.cik.max_cu_per_sh = 7;
3566 0 : rdev->config.cik.max_sh_per_se = 1;
3567 0 : rdev->config.cik.max_backends_per_se = 2;
3568 0 : rdev->config.cik.max_texture_channel_caches = 4;
3569 0 : rdev->config.cik.max_gprs = 256;
3570 0 : rdev->config.cik.max_gs_threads = 32;
3571 0 : rdev->config.cik.max_hw_contexts = 8;
3572 :
3573 0 : rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3574 0 : rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3575 0 : rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3576 0 : rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3577 : gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3578 0 : break;
3579 : case CHIP_HAWAII:
3580 0 : rdev->config.cik.max_shader_engines = 4;
3581 0 : rdev->config.cik.max_tile_pipes = 16;
3582 0 : rdev->config.cik.max_cu_per_sh = 11;
3583 0 : rdev->config.cik.max_sh_per_se = 1;
3584 0 : rdev->config.cik.max_backends_per_se = 4;
3585 0 : rdev->config.cik.max_texture_channel_caches = 16;
3586 0 : rdev->config.cik.max_gprs = 256;
3587 0 : rdev->config.cik.max_gs_threads = 32;
3588 0 : rdev->config.cik.max_hw_contexts = 8;
3589 :
3590 0 : rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3591 0 : rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3592 0 : rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3593 0 : rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3594 : gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
3595 0 : break;
3596 : case CHIP_KAVERI:
3597 0 : rdev->config.cik.max_shader_engines = 1;
3598 0 : rdev->config.cik.max_tile_pipes = 4;
3599 0 : rdev->config.cik.max_cu_per_sh = 8;
3600 0 : rdev->config.cik.max_backends_per_se = 2;
3601 0 : rdev->config.cik.max_sh_per_se = 1;
3602 0 : rdev->config.cik.max_texture_channel_caches = 4;
3603 0 : rdev->config.cik.max_gprs = 256;
3604 0 : rdev->config.cik.max_gs_threads = 16;
3605 0 : rdev->config.cik.max_hw_contexts = 8;
3606 :
3607 0 : rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3608 0 : rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3609 0 : rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3610 0 : rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3611 : gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3612 0 : break;
3613 : case CHIP_KABINI:
3614 : case CHIP_MULLINS:
3615 : default:
3616 0 : rdev->config.cik.max_shader_engines = 1;
3617 0 : rdev->config.cik.max_tile_pipes = 2;
3618 0 : rdev->config.cik.max_cu_per_sh = 2;
3619 0 : rdev->config.cik.max_sh_per_se = 1;
3620 0 : rdev->config.cik.max_backends_per_se = 1;
3621 0 : rdev->config.cik.max_texture_channel_caches = 2;
3622 0 : rdev->config.cik.max_gprs = 256;
3623 0 : rdev->config.cik.max_gs_threads = 16;
3624 0 : rdev->config.cik.max_hw_contexts = 8;
3625 :
3626 0 : rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3627 0 : rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3628 0 : rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3629 0 : rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3630 : gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3631 0 : break;
3632 : }
3633 :
3634 : /* Initialize HDP */
3635 0 : for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3636 0 : WREG32((0x2c14 + j), 0x00000000);
3637 0 : WREG32((0x2c18 + j), 0x00000000);
3638 0 : WREG32((0x2c1c + j), 0x00000000);
3639 0 : WREG32((0x2c20 + j), 0x00000000);
3640 0 : WREG32((0x2c24 + j), 0x00000000);
3641 : }
3642 :
3643 0 : WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3644 0 : WREG32(SRBM_INT_CNTL, 0x1);
3645 0 : WREG32(SRBM_INT_ACK, 0x1);
3646 :
3647 0 : WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3648 :
3649 0 : mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3650 0 : mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3651 :
3652 0 : rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
3653 0 : rdev->config.cik.mem_max_burst_length_bytes = 256;
3654 0 : tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3655 0 : rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3656 0 : if (rdev->config.cik.mem_row_size_in_kb > 4)
3657 0 : rdev->config.cik.mem_row_size_in_kb = 4;
3658 : /* XXX use MC settings? */
3659 0 : rdev->config.cik.shader_engine_tile_size = 32;
3660 0 : rdev->config.cik.num_gpus = 1;
3661 0 : rdev->config.cik.multi_gpu_tile_size = 64;
3662 :
3663 : /* fix up row size */
3664 0 : gb_addr_config &= ~ROW_SIZE_MASK;
3665 0 : switch (rdev->config.cik.mem_row_size_in_kb) {
3666 : case 1:
3667 : default:
3668 : gb_addr_config |= ROW_SIZE(0);
3669 0 : break;
3670 : case 2:
3671 0 : gb_addr_config |= ROW_SIZE(1);
3672 0 : break;
3673 : case 4:
3674 0 : gb_addr_config |= ROW_SIZE(2);
3675 0 : break;
3676 : }
3677 :
3678 : /* setup tiling info dword. gb_addr_config is not adequate since it does
3679 : * not have bank info, so create a custom tiling dword.
3680 : * bits 3:0 num_pipes
3681 : * bits 7:4 num_banks
3682 : * bits 11:8 group_size
3683 : * bits 15:12 row_size
3684 : */
3685 0 : rdev->config.cik.tile_config = 0;
3686 0 : switch (rdev->config.cik.num_tile_pipes) {
3687 : case 1:
3688 0 : rdev->config.cik.tile_config |= (0 << 0);
3689 0 : break;
3690 : case 2:
3691 0 : rdev->config.cik.tile_config |= (1 << 0);
3692 0 : break;
3693 : case 4:
3694 0 : rdev->config.cik.tile_config |= (2 << 0);
3695 0 : break;
3696 : case 8:
3697 : default:
3698 : /* XXX what about 12? */
3699 0 : rdev->config.cik.tile_config |= (3 << 0);
3700 0 : break;
3701 : }
3702 0 : rdev->config.cik.tile_config |=
3703 0 : ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
3704 0 : rdev->config.cik.tile_config |=
3705 0 : ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3706 0 : rdev->config.cik.tile_config |=
3707 0 : ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3708 :
3709 0 : WREG32(GB_ADDR_CONFIG, gb_addr_config);
3710 0 : WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3711 0 : WREG32(DMIF_ADDR_CALC, gb_addr_config);
3712 0 : WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
3713 0 : WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
3714 0 : WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3715 0 : WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3716 0 : WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3717 :
3718 0 : cik_tiling_mode_table_init(rdev);
3719 :
3720 0 : cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
3721 0 : rdev->config.cik.max_sh_per_se,
3722 0 : rdev->config.cik.max_backends_per_se);
3723 :
3724 0 : rdev->config.cik.active_cus = 0;
3725 0 : for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
3726 0 : for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
3727 0 : rdev->config.cik.active_cus +=
3728 0 : hweight32(cik_get_cu_active_bitmap(rdev, i, j));
3729 : }
3730 : }
3731 :
3732 : /* set HW defaults for 3D engine */
3733 0 : WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3734 :
3735 0 : mutex_lock(&rdev->grbm_idx_mutex);
3736 : /*
3737 : * making sure that the following register writes will be broadcasted
3738 : * to all the shaders
3739 : */
3740 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3741 0 : WREG32(SX_DEBUG_1, 0x20);
3742 :
3743 0 : WREG32(TA_CNTL_AUX, 0x00010000);
3744 :
3745 0 : tmp = RREG32(SPI_CONFIG_CNTL);
3746 0 : tmp |= 0x03000000;
3747 0 : WREG32(SPI_CONFIG_CNTL, tmp);
3748 :
3749 0 : WREG32(SQ_CONFIG, 1);
3750 :
3751 0 : WREG32(DB_DEBUG, 0);
3752 :
3753 0 : tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3754 0 : tmp |= 0x00000400;
3755 0 : WREG32(DB_DEBUG2, tmp);
3756 :
3757 0 : tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3758 0 : tmp |= 0x00020200;
3759 0 : WREG32(DB_DEBUG3, tmp);
3760 :
3761 0 : tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3762 0 : tmp |= 0x00018208;
3763 0 : WREG32(CB_HW_CONTROL, tmp);
3764 :
3765 0 : WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3766 :
3767 0 : WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
3768 : SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
3769 : SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
3770 : SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
3771 :
3772 0 : WREG32(VGT_NUM_INSTANCES, 1);
3773 :
3774 0 : WREG32(CP_PERFMON_CNTL, 0);
3775 :
3776 0 : WREG32(SQ_CONFIG, 0);
3777 :
3778 0 : WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3779 : FORCE_EOV_MAX_REZ_CNT(255)));
3780 :
3781 0 : WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3782 : AUTO_INVLD_EN(ES_AND_GS_AUTO));
3783 :
3784 0 : WREG32(VGT_GS_VERTEX_REUSE, 16);
3785 0 : WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3786 :
3787 0 : tmp = RREG32(HDP_MISC_CNTL);
3788 0 : tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3789 0 : WREG32(HDP_MISC_CNTL, tmp);
3790 :
3791 0 : hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3792 0 : WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3793 :
3794 0 : WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3795 0 : WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
3796 0 : mutex_unlock(&rdev->grbm_idx_mutex);
3797 :
3798 0 : udelay(50);
3799 0 : }
3800 :
3801 : /*
3802 : * GPU scratch registers helpers function.
3803 : */
3804 : /**
3805 : * cik_scratch_init - setup driver info for CP scratch regs
3806 : *
3807 : * @rdev: radeon_device pointer
3808 : *
3809 : * Set up the number and offset of the CP scratch registers.
3810 : * NOTE: use of CP scratch registers is a legacy inferface and
3811 : * is not used by default on newer asics (r6xx+). On newer asics,
3812 : * memory buffers are used for fences rather than scratch regs.
3813 : */
3814 0 : static void cik_scratch_init(struct radeon_device *rdev)
3815 : {
3816 : int i;
3817 :
3818 0 : rdev->scratch.num_reg = 7;
3819 0 : rdev->scratch.reg_base = SCRATCH_REG0;
3820 0 : for (i = 0; i < rdev->scratch.num_reg; i++) {
3821 0 : rdev->scratch.free[i] = true;
3822 0 : rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3823 : }
3824 0 : }
3825 :
3826 : /**
3827 : * cik_ring_test - basic gfx ring test
3828 : *
3829 : * @rdev: radeon_device pointer
3830 : * @ring: radeon_ring structure holding ring information
3831 : *
3832 : * Allocate a scratch register and write to it using the gfx ring (CIK).
3833 : * Provides a basic gfx ring test to verify that the ring is working.
3834 : * Used by cik_cp_gfx_resume();
3835 : * Returns 0 on success, error on failure.
3836 : */
3837 0 : int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3838 : {
3839 0 : uint32_t scratch;
3840 : uint32_t tmp = 0;
3841 : unsigned i;
3842 : int r;
3843 :
3844 0 : r = radeon_scratch_get(rdev, &scratch);
3845 0 : if (r) {
3846 0 : DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3847 0 : return r;
3848 : }
3849 0 : WREG32(scratch, 0xCAFEDEAD);
3850 0 : r = radeon_ring_lock(rdev, ring, 3);
3851 0 : if (r) {
3852 0 : DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3853 0 : radeon_scratch_free(rdev, scratch);
3854 0 : return r;
3855 : }
3856 0 : radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3857 0 : radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3858 0 : radeon_ring_write(ring, 0xDEADBEEF);
3859 0 : radeon_ring_unlock_commit(rdev, ring, false);
3860 :
3861 0 : for (i = 0; i < rdev->usec_timeout; i++) {
3862 0 : tmp = RREG32(scratch);
3863 0 : if (tmp == 0xDEADBEEF)
3864 : break;
3865 0 : DRM_UDELAY(1);
3866 : }
3867 0 : if (i < rdev->usec_timeout) {
3868 : DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3869 : } else {
3870 0 : DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
3871 : ring->idx, scratch, tmp);
3872 : r = -EINVAL;
3873 : }
3874 0 : radeon_scratch_free(rdev, scratch);
3875 0 : return r;
3876 0 : }
3877 :
3878 : /**
3879 : * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
3880 : *
3881 : * @rdev: radeon_device pointer
3882 : * @ridx: radeon ring index
3883 : *
3884 : * Emits an hdp flush on the cp.
3885 : */
3886 0 : static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
3887 : int ridx)
3888 : {
3889 0 : struct radeon_ring *ring = &rdev->ring[ridx];
3890 : u32 ref_and_mask;
3891 :
3892 0 : switch (ring->idx) {
3893 : case CAYMAN_RING_TYPE_CP1_INDEX:
3894 : case CAYMAN_RING_TYPE_CP2_INDEX:
3895 : default:
3896 0 : switch (ring->me) {
3897 : case 0:
3898 0 : ref_and_mask = CP2 << ring->pipe;
3899 0 : break;
3900 : case 1:
3901 0 : ref_and_mask = CP6 << ring->pipe;
3902 0 : break;
3903 : default:
3904 0 : return;
3905 : }
3906 : break;
3907 : case RADEON_RING_TYPE_GFX_INDEX:
3908 : ref_and_mask = CP0;
3909 0 : break;
3910 : }
3911 :
3912 0 : radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3913 0 : radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3914 : WAIT_REG_MEM_FUNCTION(3) | /* == */
3915 : WAIT_REG_MEM_ENGINE(1))); /* pfp */
3916 0 : radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
3917 0 : radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
3918 0 : radeon_ring_write(ring, ref_and_mask);
3919 0 : radeon_ring_write(ring, ref_and_mask);
3920 0 : radeon_ring_write(ring, 0x20); /* poll interval */
3921 0 : }
3922 :
3923 : /**
3924 : * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
3925 : *
3926 : * @rdev: radeon_device pointer
3927 : * @fence: radeon fence object
3928 : *
3929 : * Emits a fence sequnce number on the gfx ring and flushes
3930 : * GPU caches.
3931 : */
3932 0 : void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
3933 : struct radeon_fence *fence)
3934 : {
3935 0 : struct radeon_ring *ring = &rdev->ring[fence->ring];
3936 0 : u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3937 :
3938 : /* Workaround for cache flush problems. First send a dummy EOP
3939 : * event down the pipe with seq one below.
3940 : */
3941 0 : radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3942 0 : radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3943 : EOP_TC_ACTION_EN |
3944 : EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3945 : EVENT_INDEX(5)));
3946 0 : radeon_ring_write(ring, addr & 0xfffffffc);
3947 0 : radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3948 : DATA_SEL(1) | INT_SEL(0));
3949 0 : radeon_ring_write(ring, fence->seq - 1);
3950 0 : radeon_ring_write(ring, 0);
3951 :
3952 : /* Then send the real EOP event down the pipe. */
3953 0 : radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3954 0 : radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3955 : EOP_TC_ACTION_EN |
3956 : EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3957 : EVENT_INDEX(5)));
3958 0 : radeon_ring_write(ring, addr & 0xfffffffc);
3959 0 : radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
3960 0 : radeon_ring_write(ring, fence->seq);
3961 0 : radeon_ring_write(ring, 0);
3962 0 : }
3963 :
3964 : /**
3965 : * cik_fence_compute_ring_emit - emit a fence on the compute ring
3966 : *
3967 : * @rdev: radeon_device pointer
3968 : * @fence: radeon fence object
3969 : *
3970 : * Emits a fence sequnce number on the compute ring and flushes
3971 : * GPU caches.
3972 : */
3973 0 : void cik_fence_compute_ring_emit(struct radeon_device *rdev,
3974 : struct radeon_fence *fence)
3975 : {
3976 0 : struct radeon_ring *ring = &rdev->ring[fence->ring];
3977 0 : u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3978 :
3979 : /* RELEASE_MEM - flush caches, send int */
3980 0 : radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3981 0 : radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3982 : EOP_TC_ACTION_EN |
3983 : EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3984 : EVENT_INDEX(5)));
3985 0 : radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));
3986 0 : radeon_ring_write(ring, addr & 0xfffffffc);
3987 0 : radeon_ring_write(ring, upper_32_bits(addr));
3988 0 : radeon_ring_write(ring, fence->seq);
3989 0 : radeon_ring_write(ring, 0);
3990 0 : }
3991 :
3992 : /**
3993 : * cik_semaphore_ring_emit - emit a semaphore on the CP ring
3994 : *
3995 : * @rdev: radeon_device pointer
3996 : * @ring: radeon ring buffer object
3997 : * @semaphore: radeon semaphore object
3998 : * @emit_wait: Is this a sempahore wait?
3999 : *
4000 : * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
4001 : * from running ahead of semaphore waits.
4002 : */
4003 0 : bool cik_semaphore_ring_emit(struct radeon_device *rdev,
4004 : struct radeon_ring *ring,
4005 : struct radeon_semaphore *semaphore,
4006 : bool emit_wait)
4007 : {
4008 0 : uint64_t addr = semaphore->gpu_addr;
4009 0 : unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
4010 :
4011 0 : radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
4012 0 : radeon_ring_write(ring, lower_32_bits(addr));
4013 0 : radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
4014 :
4015 0 : if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
4016 : /* Prevent the PFP from running ahead of the semaphore wait */
4017 0 : radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4018 0 : radeon_ring_write(ring, 0x0);
4019 0 : }
4020 :
4021 0 : return true;
4022 : }
4023 :
4024 : /**
4025 : * cik_copy_cpdma - copy pages using the CP DMA engine
4026 : *
4027 : * @rdev: radeon_device pointer
4028 : * @src_offset: src GPU address
4029 : * @dst_offset: dst GPU address
4030 : * @num_gpu_pages: number of GPU pages to xfer
4031 : * @resv: reservation object to sync to
4032 : *
4033 : * Copy GPU paging using the CP DMA engine (CIK+).
4034 : * Used by the radeon ttm implementation to move pages if
4035 : * registered as the asic copy callback.
4036 : */
4037 0 : struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
4038 : uint64_t src_offset, uint64_t dst_offset,
4039 : unsigned num_gpu_pages,
4040 : struct reservation_object *resv)
4041 : {
4042 0 : struct radeon_fence *fence;
4043 0 : struct radeon_sync sync;
4044 0 : int ring_index = rdev->asic->copy.blit_ring_index;
4045 0 : struct radeon_ring *ring = &rdev->ring[ring_index];
4046 : u32 size_in_bytes, cur_size_in_bytes, control;
4047 : int i, num_loops;
4048 : int r = 0;
4049 :
4050 0 : radeon_sync_create(&sync);
4051 :
4052 0 : size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
4053 0 : num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
4054 0 : r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);
4055 0 : if (r) {
4056 0 : DRM_ERROR("radeon: moving bo (%d).\n", r);
4057 0 : radeon_sync_free(rdev, &sync, NULL);
4058 0 : return ERR_PTR(r);
4059 : }
4060 :
4061 0 : radeon_sync_resv(rdev, &sync, resv, false);
4062 0 : radeon_sync_rings(rdev, &sync, ring->idx);
4063 :
4064 0 : for (i = 0; i < num_loops; i++) {
4065 : cur_size_in_bytes = size_in_bytes;
4066 0 : if (cur_size_in_bytes > 0x1fffff)
4067 : cur_size_in_bytes = 0x1fffff;
4068 0 : size_in_bytes -= cur_size_in_bytes;
4069 : control = 0;
4070 0 : if (size_in_bytes == 0)
4071 0 : control |= PACKET3_DMA_DATA_CP_SYNC;
4072 0 : radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
4073 0 : radeon_ring_write(ring, control);
4074 0 : radeon_ring_write(ring, lower_32_bits(src_offset));
4075 0 : radeon_ring_write(ring, upper_32_bits(src_offset));
4076 0 : radeon_ring_write(ring, lower_32_bits(dst_offset));
4077 0 : radeon_ring_write(ring, upper_32_bits(dst_offset));
4078 0 : radeon_ring_write(ring, cur_size_in_bytes);
4079 0 : src_offset += cur_size_in_bytes;
4080 0 : dst_offset += cur_size_in_bytes;
4081 : }
4082 :
4083 0 : r = radeon_fence_emit(rdev, &fence, ring->idx);
4084 0 : if (r) {
4085 0 : radeon_ring_unlock_undo(rdev, ring);
4086 0 : radeon_sync_free(rdev, &sync, NULL);
4087 0 : return ERR_PTR(r);
4088 : }
4089 :
4090 0 : radeon_ring_unlock_commit(rdev, ring, false);
4091 0 : radeon_sync_free(rdev, &sync, fence);
4092 :
4093 0 : return fence;
4094 0 : }
4095 :
4096 : /*
4097 : * IB stuff
4098 : */
4099 : /**
4100 : * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
4101 : *
4102 : * @rdev: radeon_device pointer
4103 : * @ib: radeon indirect buffer object
4104 : *
4105 : * Emits an DE (drawing engine) or CE (constant engine) IB
4106 : * on the gfx ring. IBs are usually generated by userspace
4107 : * acceleration drivers and submitted to the kernel for
4108 : * sheduling on the ring. This function schedules the IB
4109 : * on the gfx ring for execution by the GPU.
4110 : */
4111 0 : void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
4112 : {
4113 0 : struct radeon_ring *ring = &rdev->ring[ib->ring];
4114 0 : unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
4115 : u32 header, control = INDIRECT_BUFFER_VALID;
4116 :
4117 0 : if (ib->is_const_ib) {
4118 : /* set switch buffer packet before const IB */
4119 0 : radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4120 0 : radeon_ring_write(ring, 0);
4121 :
4122 : header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4123 0 : } else {
4124 : u32 next_rptr;
4125 0 : if (ring->rptr_save_reg) {
4126 0 : next_rptr = ring->wptr + 3 + 4;
4127 0 : radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
4128 0 : radeon_ring_write(ring, ((ring->rptr_save_reg -
4129 0 : PACKET3_SET_UCONFIG_REG_START) >> 2));
4130 0 : radeon_ring_write(ring, next_rptr);
4131 0 : } else if (rdev->wb.enabled) {
4132 0 : next_rptr = ring->wptr + 5 + 4;
4133 0 : radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4134 0 : radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
4135 0 : radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4136 0 : radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
4137 0 : radeon_ring_write(ring, next_rptr);
4138 0 : }
4139 :
4140 : header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4141 : }
4142 :
4143 0 : control |= ib->length_dw | (vm_id << 24);
4144 :
4145 0 : radeon_ring_write(ring, header);
4146 0 : radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));
4147 0 : radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4148 0 : radeon_ring_write(ring, control);
4149 0 : }
4150 :
4151 : /**
4152 : * cik_ib_test - basic gfx ring IB test
4153 : *
4154 : * @rdev: radeon_device pointer
4155 : * @ring: radeon_ring structure holding ring information
4156 : *
4157 : * Allocate an IB and execute it on the gfx ring (CIK).
4158 : * Provides a basic gfx ring test to verify that IBs are working.
4159 : * Returns 0 on success, error on failure.
4160 : */
4161 0 : int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
4162 : {
4163 0 : struct radeon_ib ib;
4164 0 : uint32_t scratch;
4165 : uint32_t tmp = 0;
4166 : unsigned i;
4167 : int r;
4168 :
4169 0 : r = radeon_scratch_get(rdev, &scratch);
4170 0 : if (r) {
4171 0 : DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
4172 0 : return r;
4173 : }
4174 0 : WREG32(scratch, 0xCAFEDEAD);
4175 0 : r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
4176 0 : if (r) {
4177 0 : DRM_ERROR("radeon: failed to get ib (%d).\n", r);
4178 0 : radeon_scratch_free(rdev, scratch);
4179 0 : return r;
4180 : }
4181 0 : ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
4182 0 : ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
4183 0 : ib.ptr[2] = 0xDEADBEEF;
4184 0 : ib.length_dw = 3;
4185 0 : r = radeon_ib_schedule(rdev, &ib, NULL, false);
4186 0 : if (r) {
4187 0 : radeon_scratch_free(rdev, scratch);
4188 0 : radeon_ib_free(rdev, &ib);
4189 0 : DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
4190 0 : return r;
4191 : }
4192 0 : r = radeon_fence_wait(ib.fence, false);
4193 0 : if (r) {
4194 0 : DRM_ERROR("radeon: fence wait failed (%d).\n", r);
4195 0 : radeon_scratch_free(rdev, scratch);
4196 0 : radeon_ib_free(rdev, &ib);
4197 0 : return r;
4198 : }
4199 0 : for (i = 0; i < rdev->usec_timeout; i++) {
4200 0 : tmp = RREG32(scratch);
4201 0 : if (tmp == 0xDEADBEEF)
4202 : break;
4203 0 : DRM_UDELAY(1);
4204 : }
4205 0 : if (i < rdev->usec_timeout) {
4206 : DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
4207 : } else {
4208 0 : DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
4209 : scratch, tmp);
4210 : r = -EINVAL;
4211 : }
4212 0 : radeon_scratch_free(rdev, scratch);
4213 0 : radeon_ib_free(rdev, &ib);
4214 0 : return r;
4215 0 : }
4216 :
4217 : /*
4218 : * CP.
4219 : * On CIK, gfx and compute now have independant command processors.
4220 : *
4221 : * GFX
4222 : * Gfx consists of a single ring and can process both gfx jobs and
4223 : * compute jobs. The gfx CP consists of three microengines (ME):
4224 : * PFP - Pre-Fetch Parser
4225 : * ME - Micro Engine
4226 : * CE - Constant Engine
4227 : * The PFP and ME make up what is considered the Drawing Engine (DE).
4228 : * The CE is an asynchronous engine used for updating buffer desciptors
4229 : * used by the DE so that they can be loaded into cache in parallel
4230 : * while the DE is processing state update packets.
4231 : *
4232 : * Compute
4233 : * The compute CP consists of two microengines (ME):
4234 : * MEC1 - Compute MicroEngine 1
4235 : * MEC2 - Compute MicroEngine 2
4236 : * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
4237 : * The queues are exposed to userspace and are programmed directly
4238 : * by the compute runtime.
4239 : */
4240 : /**
4241 : * cik_cp_gfx_enable - enable/disable the gfx CP MEs
4242 : *
4243 : * @rdev: radeon_device pointer
4244 : * @enable: enable or disable the MEs
4245 : *
4246 : * Halts or unhalts the gfx MEs.
4247 : */
4248 0 : static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
4249 : {
4250 0 : if (enable)
4251 0 : WREG32(CP_ME_CNTL, 0);
4252 : else {
4253 0 : if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
4254 0 : radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
4255 0 : WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
4256 0 : rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4257 : }
4258 0 : udelay(50);
4259 0 : }
4260 :
4261 : /**
4262 : * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
4263 : *
4264 : * @rdev: radeon_device pointer
4265 : *
4266 : * Loads the gfx PFP, ME, and CE ucode.
4267 : * Returns 0 for success, -EINVAL if the ucode is not available.
4268 : */
4269 0 : static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
4270 : {
4271 : int i;
4272 :
4273 0 : if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
4274 0 : return -EINVAL;
4275 :
4276 0 : cik_cp_gfx_enable(rdev, false);
4277 :
4278 0 : if (rdev->new_fw) {
4279 : const struct gfx_firmware_header_v1_0 *pfp_hdr =
4280 0 : (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
4281 : const struct gfx_firmware_header_v1_0 *ce_hdr =
4282 0 : (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
4283 : const struct gfx_firmware_header_v1_0 *me_hdr =
4284 0 : (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
4285 : const __le32 *fw_data;
4286 : u32 fw_size;
4287 :
4288 0 : radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
4289 0 : radeon_ucode_print_gfx_hdr(&ce_hdr->header);
4290 0 : radeon_ucode_print_gfx_hdr(&me_hdr->header);
4291 :
4292 : /* PFP */
4293 0 : fw_data = (const __le32 *)
4294 0 : (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
4295 0 : fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
4296 0 : WREG32(CP_PFP_UCODE_ADDR, 0);
4297 0 : for (i = 0; i < fw_size; i++)
4298 0 : WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
4299 0 : WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version));
4300 :
4301 : /* CE */
4302 0 : fw_data = (const __le32 *)
4303 0 : (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
4304 0 : fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
4305 0 : WREG32(CP_CE_UCODE_ADDR, 0);
4306 0 : for (i = 0; i < fw_size; i++)
4307 0 : WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
4308 0 : WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version));
4309 :
4310 : /* ME */
4311 0 : fw_data = (const __be32 *)
4312 0 : (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
4313 0 : fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
4314 0 : WREG32(CP_ME_RAM_WADDR, 0);
4315 0 : for (i = 0; i < fw_size; i++)
4316 0 : WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
4317 0 : WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version));
4318 0 : WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version));
4319 0 : } else {
4320 : const __be32 *fw_data;
4321 :
4322 : /* PFP */
4323 0 : fw_data = (const __be32 *)rdev->pfp_fw->data;
4324 0 : WREG32(CP_PFP_UCODE_ADDR, 0);
4325 0 : for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
4326 0 : WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
4327 0 : WREG32(CP_PFP_UCODE_ADDR, 0);
4328 :
4329 : /* CE */
4330 0 : fw_data = (const __be32 *)rdev->ce_fw->data;
4331 0 : WREG32(CP_CE_UCODE_ADDR, 0);
4332 0 : for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
4333 0 : WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
4334 0 : WREG32(CP_CE_UCODE_ADDR, 0);
4335 :
4336 : /* ME */
4337 0 : fw_data = (const __be32 *)rdev->me_fw->data;
4338 0 : WREG32(CP_ME_RAM_WADDR, 0);
4339 0 : for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
4340 0 : WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
4341 0 : WREG32(CP_ME_RAM_WADDR, 0);
4342 : }
4343 :
4344 0 : return 0;
4345 0 : }
4346 :
4347 : /**
4348 : * cik_cp_gfx_start - start the gfx ring
4349 : *
4350 : * @rdev: radeon_device pointer
4351 : *
4352 : * Enables the ring and loads the clear state context and other
4353 : * packets required to init the ring.
4354 : * Returns 0 for success, error for failure.
4355 : */
4356 0 : static int cik_cp_gfx_start(struct radeon_device *rdev)
4357 : {
4358 0 : struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4359 : int r, i;
4360 :
4361 : /* init the CP */
4362 0 : WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
4363 0 : WREG32(CP_ENDIAN_SWAP, 0);
4364 0 : WREG32(CP_DEVICE_ID, 1);
4365 :
4366 0 : cik_cp_gfx_enable(rdev, true);
4367 :
4368 0 : r = radeon_ring_lock(rdev, ring, cik_default_size + 17);
4369 0 : if (r) {
4370 0 : DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
4371 0 : return r;
4372 : }
4373 :
4374 : /* init the CE partitions. CE only used for gfx on CIK */
4375 0 : radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4376 0 : radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4377 0 : radeon_ring_write(ring, 0x8000);
4378 0 : radeon_ring_write(ring, 0x8000);
4379 :
4380 : /* setup clear context state */
4381 0 : radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4382 0 : radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4383 :
4384 0 : radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4385 0 : radeon_ring_write(ring, 0x80000000);
4386 0 : radeon_ring_write(ring, 0x80000000);
4387 :
4388 0 : for (i = 0; i < cik_default_size; i++)
4389 0 : radeon_ring_write(ring, cik_default_state[i]);
4390 :
4391 0 : radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4392 0 : radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4393 :
4394 : /* set clear context state */
4395 0 : radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4396 0 : radeon_ring_write(ring, 0);
4397 :
4398 0 : radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4399 0 : radeon_ring_write(ring, 0x00000316);
4400 0 : radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
4401 0 : radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
4402 :
4403 0 : radeon_ring_unlock_commit(rdev, ring, false);
4404 :
4405 0 : return 0;
4406 0 : }
4407 :
4408 : /**
4409 : * cik_cp_gfx_fini - stop the gfx ring
4410 : *
4411 : * @rdev: radeon_device pointer
4412 : *
4413 : * Stop the gfx ring and tear down the driver ring
4414 : * info.
4415 : */
4416 0 : static void cik_cp_gfx_fini(struct radeon_device *rdev)
4417 : {
4418 0 : cik_cp_gfx_enable(rdev, false);
4419 0 : radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4420 0 : }
4421 :
4422 : /**
4423 : * cik_cp_gfx_resume - setup the gfx ring buffer registers
4424 : *
4425 : * @rdev: radeon_device pointer
4426 : *
4427 : * Program the location and size of the gfx ring buffer
4428 : * and test it to make sure it's working.
4429 : * Returns 0 for success, error for failure.
4430 : */
4431 0 : static int cik_cp_gfx_resume(struct radeon_device *rdev)
4432 : {
4433 : struct radeon_ring *ring;
4434 : u32 tmp;
4435 : u32 rb_bufsz;
4436 : u64 rb_addr;
4437 : int r;
4438 :
4439 0 : WREG32(CP_SEM_WAIT_TIMER, 0x0);
4440 0 : if (rdev->family != CHIP_HAWAII)
4441 0 : WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
4442 :
4443 : /* Set the write pointer delay */
4444 0 : WREG32(CP_RB_WPTR_DELAY, 0);
4445 :
4446 : /* set the RB to use vmid 0 */
4447 0 : WREG32(CP_RB_VMID, 0);
4448 :
4449 0 : WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
4450 :
4451 : /* ring 0 - compute and gfx */
4452 : /* Set ring buffer size */
4453 0 : ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4454 0 : rb_bufsz = order_base_2(ring->ring_size / 8);
4455 0 : tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
4456 : #ifdef __BIG_ENDIAN
4457 : tmp |= BUF_SWAP_32BIT;
4458 : #endif
4459 0 : WREG32(CP_RB0_CNTL, tmp);
4460 :
4461 : /* Initialize the ring buffer's read and write pointers */
4462 0 : WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
4463 0 : ring->wptr = 0;
4464 0 : WREG32(CP_RB0_WPTR, ring->wptr);
4465 :
4466 : /* set the wb address wether it's enabled or not */
4467 0 : WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
4468 0 : WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
4469 :
4470 : /* scratch register shadowing is no longer supported */
4471 0 : WREG32(SCRATCH_UMSK, 0);
4472 :
4473 0 : if (!rdev->wb.enabled)
4474 0 : tmp |= RB_NO_UPDATE;
4475 :
4476 0 : mdelay(1);
4477 0 : WREG32(CP_RB0_CNTL, tmp);
4478 :
4479 0 : rb_addr = ring->gpu_addr >> 8;
4480 0 : WREG32(CP_RB0_BASE, rb_addr);
4481 0 : WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
4482 :
4483 : /* start the ring */
4484 0 : cik_cp_gfx_start(rdev);
4485 0 : rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
4486 0 : r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4487 0 : if (r) {
4488 0 : rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4489 0 : return r;
4490 : }
4491 :
4492 0 : if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
4493 0 : radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
4494 :
4495 0 : return 0;
4496 0 : }
4497 :
4498 0 : u32 cik_gfx_get_rptr(struct radeon_device *rdev,
4499 : struct radeon_ring *ring)
4500 : {
4501 : u32 rptr;
4502 :
4503 0 : if (rdev->wb.enabled)
4504 0 : rptr = rdev->wb.wb[ring->rptr_offs/4];
4505 : else
4506 0 : rptr = RREG32(CP_RB0_RPTR);
4507 :
4508 0 : return rptr;
4509 : }
4510 :
4511 0 : u32 cik_gfx_get_wptr(struct radeon_device *rdev,
4512 : struct radeon_ring *ring)
4513 : {
4514 : u32 wptr;
4515 :
4516 0 : wptr = RREG32(CP_RB0_WPTR);
4517 :
4518 0 : return wptr;
4519 : }
4520 :
4521 0 : void cik_gfx_set_wptr(struct radeon_device *rdev,
4522 : struct radeon_ring *ring)
4523 : {
4524 0 : WREG32(CP_RB0_WPTR, ring->wptr);
4525 0 : (void)RREG32(CP_RB0_WPTR);
4526 0 : }
4527 :
4528 0 : u32 cik_compute_get_rptr(struct radeon_device *rdev,
4529 : struct radeon_ring *ring)
4530 : {
4531 : u32 rptr;
4532 :
4533 0 : if (rdev->wb.enabled) {
4534 0 : rptr = rdev->wb.wb[ring->rptr_offs/4];
4535 0 : } else {
4536 0 : mutex_lock(&rdev->srbm_mutex);
4537 0 : cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4538 0 : rptr = RREG32(CP_HQD_PQ_RPTR);
4539 0 : cik_srbm_select(rdev, 0, 0, 0, 0);
4540 0 : mutex_unlock(&rdev->srbm_mutex);
4541 : }
4542 :
4543 0 : return rptr;
4544 : }
4545 :
4546 0 : u32 cik_compute_get_wptr(struct radeon_device *rdev,
4547 : struct radeon_ring *ring)
4548 : {
4549 : u32 wptr;
4550 :
4551 0 : if (rdev->wb.enabled) {
4552 : /* XXX check if swapping is necessary on BE */
4553 0 : wptr = rdev->wb.wb[ring->wptr_offs/4];
4554 0 : } else {
4555 0 : mutex_lock(&rdev->srbm_mutex);
4556 0 : cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4557 0 : wptr = RREG32(CP_HQD_PQ_WPTR);
4558 0 : cik_srbm_select(rdev, 0, 0, 0, 0);
4559 0 : mutex_unlock(&rdev->srbm_mutex);
4560 : }
4561 :
4562 0 : return wptr;
4563 : }
4564 :
4565 0 : void cik_compute_set_wptr(struct radeon_device *rdev,
4566 : struct radeon_ring *ring)
4567 : {
4568 : /* XXX check if swapping is necessary on BE */
4569 0 : rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
4570 0 : WDOORBELL32(ring->doorbell_index, ring->wptr);
4571 0 : }
4572 :
4573 0 : static void cik_compute_stop(struct radeon_device *rdev,
4574 : struct radeon_ring *ring)
4575 : {
4576 : u32 j, tmp;
4577 :
4578 0 : cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4579 : /* Disable wptr polling. */
4580 0 : tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4581 0 : tmp &= ~WPTR_POLL_EN;
4582 0 : WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4583 : /* Disable HQD. */
4584 0 : if (RREG32(CP_HQD_ACTIVE) & 1) {
4585 0 : WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
4586 0 : for (j = 0; j < rdev->usec_timeout; j++) {
4587 0 : if (!(RREG32(CP_HQD_ACTIVE) & 1))
4588 : break;
4589 0 : udelay(1);
4590 : }
4591 0 : WREG32(CP_HQD_DEQUEUE_REQUEST, 0);
4592 0 : WREG32(CP_HQD_PQ_RPTR, 0);
4593 0 : WREG32(CP_HQD_PQ_WPTR, 0);
4594 0 : }
4595 0 : cik_srbm_select(rdev, 0, 0, 0, 0);
4596 0 : }
4597 :
4598 : /**
4599 : * cik_cp_compute_enable - enable/disable the compute CP MEs
4600 : *
4601 : * @rdev: radeon_device pointer
4602 : * @enable: enable or disable the MEs
4603 : *
4604 : * Halts or unhalts the compute MEs.
4605 : */
4606 0 : static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
4607 : {
4608 0 : if (enable)
4609 0 : WREG32(CP_MEC_CNTL, 0);
4610 : else {
4611 : /*
4612 : * To make hibernation reliable we need to clear compute ring
4613 : * configuration before halting the compute ring.
4614 : */
4615 0 : mutex_lock(&rdev->srbm_mutex);
4616 0 : cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
4617 0 : cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
4618 0 : mutex_unlock(&rdev->srbm_mutex);
4619 :
4620 0 : WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
4621 0 : rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
4622 0 : rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
4623 : }
4624 0 : udelay(50);
4625 0 : }
4626 :
4627 : /**
4628 : * cik_cp_compute_load_microcode - load the compute CP ME ucode
4629 : *
4630 : * @rdev: radeon_device pointer
4631 : *
4632 : * Loads the compute MEC1&2 ucode.
4633 : * Returns 0 for success, -EINVAL if the ucode is not available.
4634 : */
4635 0 : static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4636 : {
4637 : int i;
4638 :
4639 0 : if (!rdev->mec_fw)
4640 0 : return -EINVAL;
4641 :
4642 0 : cik_cp_compute_enable(rdev, false);
4643 :
4644 0 : if (rdev->new_fw) {
4645 : const struct gfx_firmware_header_v1_0 *mec_hdr =
4646 0 : (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
4647 : const __le32 *fw_data;
4648 : u32 fw_size;
4649 :
4650 0 : radeon_ucode_print_gfx_hdr(&mec_hdr->header);
4651 :
4652 : /* MEC1 */
4653 0 : fw_data = (const __le32 *)
4654 0 : (rdev->mec_fw->data + le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4655 0 : fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
4656 0 : WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4657 0 : for (i = 0; i < fw_size; i++)
4658 0 : WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
4659 0 : WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version));
4660 :
4661 : /* MEC2 */
4662 0 : if (rdev->family == CHIP_KAVERI) {
4663 : const struct gfx_firmware_header_v1_0 *mec2_hdr =
4664 0 : (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
4665 :
4666 0 : fw_data = (const __le32 *)
4667 0 : (rdev->mec2_fw->data +
4668 0 : le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
4669 0 : fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
4670 0 : WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4671 0 : for (i = 0; i < fw_size; i++)
4672 0 : WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
4673 0 : WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version));
4674 0 : }
4675 0 : } else {
4676 : const __be32 *fw_data;
4677 :
4678 : /* MEC1 */
4679 0 : fw_data = (const __be32 *)rdev->mec_fw->data;
4680 0 : WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4681 0 : for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4682 0 : WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
4683 0 : WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4684 :
4685 0 : if (rdev->family == CHIP_KAVERI) {
4686 : /* MEC2 */
4687 0 : fw_data = (const __be32 *)rdev->mec_fw->data;
4688 0 : WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4689 0 : for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4690 0 : WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
4691 0 : WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4692 0 : }
4693 : }
4694 :
4695 0 : return 0;
4696 0 : }
4697 :
4698 : /**
4699 : * cik_cp_compute_start - start the compute queues
4700 : *
4701 : * @rdev: radeon_device pointer
4702 : *
4703 : * Enable the compute queues.
4704 : * Returns 0 for success, error for failure.
4705 : */
4706 0 : static int cik_cp_compute_start(struct radeon_device *rdev)
4707 : {
4708 0 : cik_cp_compute_enable(rdev, true);
4709 :
4710 0 : return 0;
4711 : }
4712 :
4713 : /**
4714 : * cik_cp_compute_fini - stop the compute queues
4715 : *
4716 : * @rdev: radeon_device pointer
4717 : *
4718 : * Stop the compute queues and tear down the driver queue
4719 : * info.
4720 : */
4721 0 : static void cik_cp_compute_fini(struct radeon_device *rdev)
4722 : {
4723 : int i, idx, r;
4724 :
4725 0 : cik_cp_compute_enable(rdev, false);
4726 :
4727 0 : for (i = 0; i < 2; i++) {
4728 0 : if (i == 0)
4729 0 : idx = CAYMAN_RING_TYPE_CP1_INDEX;
4730 : else
4731 : idx = CAYMAN_RING_TYPE_CP2_INDEX;
4732 :
4733 0 : if (rdev->ring[idx].mqd_obj) {
4734 0 : r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
4735 0 : if (unlikely(r != 0))
4736 0 : dev_warn(rdev->dev, "(%d) reserve MQD bo failed\n", r);
4737 :
4738 0 : radeon_bo_unpin(rdev->ring[idx].mqd_obj);
4739 0 : radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
4740 :
4741 0 : radeon_bo_unref(&rdev->ring[idx].mqd_obj);
4742 0 : rdev->ring[idx].mqd_obj = NULL;
4743 0 : }
4744 : }
4745 0 : }
4746 :
4747 0 : static void cik_mec_fini(struct radeon_device *rdev)
4748 : {
4749 : int r;
4750 :
4751 0 : if (rdev->mec.hpd_eop_obj) {
4752 0 : r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4753 0 : if (unlikely(r != 0))
4754 0 : dev_warn(rdev->dev, "(%d) reserve HPD EOP bo failed\n", r);
4755 0 : radeon_bo_unpin(rdev->mec.hpd_eop_obj);
4756 0 : radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4757 :
4758 0 : radeon_bo_unref(&rdev->mec.hpd_eop_obj);
4759 0 : rdev->mec.hpd_eop_obj = NULL;
4760 0 : }
4761 0 : }
4762 :
4763 : #define MEC_HPD_SIZE 2048
4764 :
4765 0 : static int cik_mec_init(struct radeon_device *rdev)
4766 : {
4767 : int r;
4768 0 : u32 *hpd;
4769 :
4770 : /*
4771 : * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
4772 : * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
4773 : * Nonetheless, we assign only 1 pipe because all other pipes will
4774 : * be handled by KFD
4775 : */
4776 0 : rdev->mec.num_mec = 1;
4777 0 : rdev->mec.num_pipe = 1;
4778 0 : rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8;
4779 :
4780 0 : if (rdev->mec.hpd_eop_obj == NULL) {
4781 0 : r = radeon_bo_create(rdev,
4782 0 : rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2,
4783 : PAGE_SIZE, true,
4784 : RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
4785 : &rdev->mec.hpd_eop_obj);
4786 0 : if (r) {
4787 0 : dev_warn(rdev->dev, "(%d) create HDP EOP bo failed\n", r);
4788 0 : return r;
4789 : }
4790 : }
4791 :
4792 0 : r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4793 0 : if (unlikely(r != 0)) {
4794 0 : cik_mec_fini(rdev);
4795 0 : return r;
4796 : }
4797 0 : r = radeon_bo_pin(rdev->mec.hpd_eop_obj, RADEON_GEM_DOMAIN_GTT,
4798 0 : &rdev->mec.hpd_eop_gpu_addr);
4799 0 : if (r) {
4800 0 : dev_warn(rdev->dev, "(%d) pin HDP EOP bo failed\n", r);
4801 0 : cik_mec_fini(rdev);
4802 0 : return r;
4803 : }
4804 0 : r = radeon_bo_kmap(rdev->mec.hpd_eop_obj, (void **)&hpd);
4805 0 : if (r) {
4806 0 : dev_warn(rdev->dev, "(%d) map HDP EOP bo failed\n", r);
4807 0 : cik_mec_fini(rdev);
4808 0 : return r;
4809 : }
4810 :
4811 : /* clear memory. Not sure if this is required or not */
4812 0 : memset(hpd, 0, rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2);
4813 :
4814 0 : radeon_bo_kunmap(rdev->mec.hpd_eop_obj);
4815 0 : radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4816 :
4817 0 : return 0;
4818 0 : }
4819 :
4820 : struct hqd_registers
4821 : {
4822 : u32 cp_mqd_base_addr;
4823 : u32 cp_mqd_base_addr_hi;
4824 : u32 cp_hqd_active;
4825 : u32 cp_hqd_vmid;
4826 : u32 cp_hqd_persistent_state;
4827 : u32 cp_hqd_pipe_priority;
4828 : u32 cp_hqd_queue_priority;
4829 : u32 cp_hqd_quantum;
4830 : u32 cp_hqd_pq_base;
4831 : u32 cp_hqd_pq_base_hi;
4832 : u32 cp_hqd_pq_rptr;
4833 : u32 cp_hqd_pq_rptr_report_addr;
4834 : u32 cp_hqd_pq_rptr_report_addr_hi;
4835 : u32 cp_hqd_pq_wptr_poll_addr;
4836 : u32 cp_hqd_pq_wptr_poll_addr_hi;
4837 : u32 cp_hqd_pq_doorbell_control;
4838 : u32 cp_hqd_pq_wptr;
4839 : u32 cp_hqd_pq_control;
4840 : u32 cp_hqd_ib_base_addr;
4841 : u32 cp_hqd_ib_base_addr_hi;
4842 : u32 cp_hqd_ib_rptr;
4843 : u32 cp_hqd_ib_control;
4844 : u32 cp_hqd_iq_timer;
4845 : u32 cp_hqd_iq_rptr;
4846 : u32 cp_hqd_dequeue_request;
4847 : u32 cp_hqd_dma_offload;
4848 : u32 cp_hqd_sema_cmd;
4849 : u32 cp_hqd_msg_type;
4850 : u32 cp_hqd_atomic0_preop_lo;
4851 : u32 cp_hqd_atomic0_preop_hi;
4852 : u32 cp_hqd_atomic1_preop_lo;
4853 : u32 cp_hqd_atomic1_preop_hi;
4854 : u32 cp_hqd_hq_scheduler0;
4855 : u32 cp_hqd_hq_scheduler1;
4856 : u32 cp_mqd_control;
4857 : };
4858 :
4859 : struct bonaire_mqd
4860 : {
4861 : u32 header;
4862 : u32 dispatch_initiator;
4863 : u32 dimensions[3];
4864 : u32 start_idx[3];
4865 : u32 num_threads[3];
4866 : u32 pipeline_stat_enable;
4867 : u32 perf_counter_enable;
4868 : u32 pgm[2];
4869 : u32 tba[2];
4870 : u32 tma[2];
4871 : u32 pgm_rsrc[2];
4872 : u32 vmid;
4873 : u32 resource_limits;
4874 : u32 static_thread_mgmt01[2];
4875 : u32 tmp_ring_size;
4876 : u32 static_thread_mgmt23[2];
4877 : u32 restart[3];
4878 : u32 thread_trace_enable;
4879 : u32 reserved1;
4880 : u32 user_data[16];
4881 : u32 vgtcs_invoke_count[2];
4882 : struct hqd_registers queue_state;
4883 : u32 dequeue_cntr;
4884 : u32 interrupt_queue[64];
4885 : };
4886 :
4887 : /**
4888 : * cik_cp_compute_resume - setup the compute queue registers
4889 : *
4890 : * @rdev: radeon_device pointer
4891 : *
4892 : * Program the compute queues and test them to make sure they
4893 : * are working.
4894 : * Returns 0 for success, error for failure.
4895 : */
4896 0 : static int cik_cp_compute_resume(struct radeon_device *rdev)
4897 : {
4898 : int r, i, j, idx;
4899 : u32 tmp;
4900 : bool use_doorbell = true;
4901 : u64 hqd_gpu_addr;
4902 0 : u64 mqd_gpu_addr;
4903 : u64 eop_gpu_addr;
4904 : u64 wb_gpu_addr;
4905 0 : u32 *buf;
4906 : struct bonaire_mqd *mqd;
4907 :
4908 0 : r = cik_cp_compute_start(rdev);
4909 0 : if (r)
4910 0 : return r;
4911 :
4912 : /* fix up chicken bits */
4913 0 : tmp = RREG32(CP_CPF_DEBUG);
4914 0 : tmp |= (1 << 23);
4915 0 : WREG32(CP_CPF_DEBUG, tmp);
4916 :
4917 : /* init the pipes */
4918 0 : mutex_lock(&rdev->srbm_mutex);
4919 :
4920 0 : eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr;
4921 :
4922 0 : cik_srbm_select(rdev, 0, 0, 0, 0);
4923 :
4924 : /* write the EOP addr */
4925 0 : WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
4926 0 : WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
4927 :
4928 : /* set the VMID assigned */
4929 0 : WREG32(CP_HPD_EOP_VMID, 0);
4930 :
4931 : /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4932 0 : tmp = RREG32(CP_HPD_EOP_CONTROL);
4933 0 : tmp &= ~EOP_SIZE_MASK;
4934 0 : tmp |= order_base_2(MEC_HPD_SIZE / 8);
4935 0 : WREG32(CP_HPD_EOP_CONTROL, tmp);
4936 :
4937 0 : mutex_unlock(&rdev->srbm_mutex);
4938 :
4939 : /* init the queues. Just two for now. */
4940 0 : for (i = 0; i < 2; i++) {
4941 0 : if (i == 0)
4942 0 : idx = CAYMAN_RING_TYPE_CP1_INDEX;
4943 : else
4944 : idx = CAYMAN_RING_TYPE_CP2_INDEX;
4945 :
4946 0 : if (rdev->ring[idx].mqd_obj == NULL) {
4947 0 : r = radeon_bo_create(rdev,
4948 : sizeof(struct bonaire_mqd),
4949 : PAGE_SIZE, true,
4950 : RADEON_GEM_DOMAIN_GTT, 0, NULL,
4951 : NULL, &rdev->ring[idx].mqd_obj);
4952 0 : if (r) {
4953 0 : dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r);
4954 0 : return r;
4955 : }
4956 : }
4957 :
4958 0 : r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
4959 0 : if (unlikely(r != 0)) {
4960 0 : cik_cp_compute_fini(rdev);
4961 0 : return r;
4962 : }
4963 0 : r = radeon_bo_pin(rdev->ring[idx].mqd_obj, RADEON_GEM_DOMAIN_GTT,
4964 : &mqd_gpu_addr);
4965 0 : if (r) {
4966 0 : dev_warn(rdev->dev, "(%d) pin MQD bo failed\n", r);
4967 0 : cik_cp_compute_fini(rdev);
4968 0 : return r;
4969 : }
4970 0 : r = radeon_bo_kmap(rdev->ring[idx].mqd_obj, (void **)&buf);
4971 0 : if (r) {
4972 0 : dev_warn(rdev->dev, "(%d) map MQD bo failed\n", r);
4973 0 : cik_cp_compute_fini(rdev);
4974 0 : return r;
4975 : }
4976 :
4977 : /* init the mqd struct */
4978 0 : memset(buf, 0, sizeof(struct bonaire_mqd));
4979 :
4980 0 : mqd = (struct bonaire_mqd *)buf;
4981 0 : mqd->header = 0xC0310800;
4982 0 : mqd->static_thread_mgmt01[0] = 0xffffffff;
4983 0 : mqd->static_thread_mgmt01[1] = 0xffffffff;
4984 0 : mqd->static_thread_mgmt23[0] = 0xffffffff;
4985 0 : mqd->static_thread_mgmt23[1] = 0xffffffff;
4986 :
4987 0 : mutex_lock(&rdev->srbm_mutex);
4988 0 : cik_srbm_select(rdev, rdev->ring[idx].me,
4989 0 : rdev->ring[idx].pipe,
4990 0 : rdev->ring[idx].queue, 0);
4991 :
4992 : /* disable wptr polling */
4993 0 : tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4994 0 : tmp &= ~WPTR_POLL_EN;
4995 0 : WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4996 :
4997 : /* enable doorbell? */
4998 0 : mqd->queue_state.cp_hqd_pq_doorbell_control =
4999 0 : RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
5000 0 : if (use_doorbell)
5001 0 : mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
5002 : else
5003 0 : mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;
5004 0 : WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
5005 : mqd->queue_state.cp_hqd_pq_doorbell_control);
5006 :
5007 : /* disable the queue if it's active */
5008 0 : mqd->queue_state.cp_hqd_dequeue_request = 0;
5009 0 : mqd->queue_state.cp_hqd_pq_rptr = 0;
5010 0 : mqd->queue_state.cp_hqd_pq_wptr= 0;
5011 0 : if (RREG32(CP_HQD_ACTIVE) & 1) {
5012 0 : WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
5013 0 : for (j = 0; j < rdev->usec_timeout; j++) {
5014 0 : if (!(RREG32(CP_HQD_ACTIVE) & 1))
5015 : break;
5016 0 : udelay(1);
5017 : }
5018 0 : WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
5019 0 : WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
5020 0 : WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
5021 0 : }
5022 :
5023 : /* set the pointer to the MQD */
5024 0 : mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
5025 0 : mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
5026 0 : WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
5027 0 : WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
5028 : /* set MQD vmid to 0 */
5029 0 : mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
5030 0 : mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
5031 0 : WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
5032 :
5033 : /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
5034 0 : hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8;
5035 0 : mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
5036 0 : mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
5037 0 : WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
5038 0 : WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
5039 :
5040 : /* set up the HQD, this is similar to CP_RB0_CNTL */
5041 0 : mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
5042 0 : mqd->queue_state.cp_hqd_pq_control &=
5043 : ~(QUEUE_SIZE_MASK | RPTR_BLOCK_SIZE_MASK);
5044 :
5045 0 : mqd->queue_state.cp_hqd_pq_control |=
5046 0 : order_base_2(rdev->ring[idx].ring_size / 8);
5047 0 : mqd->queue_state.cp_hqd_pq_control |=
5048 0 : (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8);
5049 : #ifdef __BIG_ENDIAN
5050 : mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
5051 : #endif
5052 0 : mqd->queue_state.cp_hqd_pq_control &=
5053 : ~(UNORD_DISPATCH | ROQ_PQ_IB_FLIP | PQ_VOLATILE);
5054 0 : mqd->queue_state.cp_hqd_pq_control |=
5055 : PRIV_STATE | KMD_QUEUE; /* assuming kernel queue control */
5056 0 : WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
5057 :
5058 : /* only used if CP_PQ_WPTR_POLL_CNTL.WPTR_POLL_EN=1 */
5059 0 : if (i == 0)
5060 0 : wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;
5061 : else
5062 0 : wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;
5063 0 : mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
5064 0 : mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
5065 0 : WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
5066 0 : WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI,
5067 : mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
5068 :
5069 : /* set the wb address wether it's enabled or not */
5070 0 : if (i == 0)
5071 0 : wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;
5072 : else
5073 0 : wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;
5074 0 : mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
5075 0 : mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
5076 0 : upper_32_bits(wb_gpu_addr) & 0xffff;
5077 0 : WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR,
5078 : mqd->queue_state.cp_hqd_pq_rptr_report_addr);
5079 0 : WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
5080 : mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
5081 :
5082 : /* enable the doorbell if requested */
5083 0 : if (use_doorbell) {
5084 : mqd->queue_state.cp_hqd_pq_doorbell_control =
5085 0 : RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
5086 0 : mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;
5087 0 : mqd->queue_state.cp_hqd_pq_doorbell_control |=
5088 0 : DOORBELL_OFFSET(rdev->ring[idx].doorbell_index);
5089 0 : mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
5090 0 : mqd->queue_state.cp_hqd_pq_doorbell_control &=
5091 : ~(DOORBELL_SOURCE | DOORBELL_HIT);
5092 :
5093 0 : } else {
5094 0 : mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
5095 : }
5096 0 : WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
5097 : mqd->queue_state.cp_hqd_pq_doorbell_control);
5098 :
5099 : /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5100 0 : rdev->ring[idx].wptr = 0;
5101 0 : mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
5102 0 : WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
5103 0 : mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
5104 :
5105 : /* set the vmid for the queue */
5106 0 : mqd->queue_state.cp_hqd_vmid = 0;
5107 0 : WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
5108 :
5109 : /* activate the queue */
5110 0 : mqd->queue_state.cp_hqd_active = 1;
5111 0 : WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
5112 :
5113 0 : cik_srbm_select(rdev, 0, 0, 0, 0);
5114 0 : mutex_unlock(&rdev->srbm_mutex);
5115 :
5116 0 : radeon_bo_kunmap(rdev->ring[idx].mqd_obj);
5117 0 : radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
5118 :
5119 0 : rdev->ring[idx].ready = true;
5120 0 : r = radeon_ring_test(rdev, idx, &rdev->ring[idx]);
5121 0 : if (r)
5122 0 : rdev->ring[idx].ready = false;
5123 : }
5124 :
5125 0 : return 0;
5126 0 : }
5127 :
5128 0 : static void cik_cp_enable(struct radeon_device *rdev, bool enable)
5129 : {
5130 0 : cik_cp_gfx_enable(rdev, enable);
5131 0 : cik_cp_compute_enable(rdev, enable);
5132 0 : }
5133 :
5134 0 : static int cik_cp_load_microcode(struct radeon_device *rdev)
5135 : {
5136 : int r;
5137 :
5138 0 : r = cik_cp_gfx_load_microcode(rdev);
5139 0 : if (r)
5140 0 : return r;
5141 0 : r = cik_cp_compute_load_microcode(rdev);
5142 0 : if (r)
5143 0 : return r;
5144 :
5145 0 : return 0;
5146 0 : }
5147 :
5148 0 : static void cik_cp_fini(struct radeon_device *rdev)
5149 : {
5150 0 : cik_cp_gfx_fini(rdev);
5151 0 : cik_cp_compute_fini(rdev);
5152 0 : }
5153 :
5154 0 : static int cik_cp_resume(struct radeon_device *rdev)
5155 : {
5156 : int r;
5157 :
5158 0 : cik_enable_gui_idle_interrupt(rdev, false);
5159 :
5160 0 : r = cik_cp_load_microcode(rdev);
5161 0 : if (r)
5162 0 : return r;
5163 :
5164 0 : r = cik_cp_gfx_resume(rdev);
5165 0 : if (r)
5166 0 : return r;
5167 0 : r = cik_cp_compute_resume(rdev);
5168 0 : if (r)
5169 0 : return r;
5170 :
5171 0 : cik_enable_gui_idle_interrupt(rdev, true);
5172 :
5173 0 : return 0;
5174 0 : }
5175 :
5176 0 : static void cik_print_gpu_status_regs(struct radeon_device *rdev)
5177 : {
5178 : dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
5179 : RREG32(GRBM_STATUS));
5180 : dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
5181 : RREG32(GRBM_STATUS2));
5182 : dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
5183 : RREG32(GRBM_STATUS_SE0));
5184 : dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
5185 : RREG32(GRBM_STATUS_SE1));
5186 : dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
5187 : RREG32(GRBM_STATUS_SE2));
5188 : dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
5189 : RREG32(GRBM_STATUS_SE3));
5190 : dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
5191 : RREG32(SRBM_STATUS));
5192 : dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
5193 : RREG32(SRBM_STATUS2));
5194 : dev_info(rdev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
5195 : RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
5196 : dev_info(rdev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
5197 : RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
5198 : dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));
5199 : dev_info(rdev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
5200 : RREG32(CP_STALLED_STAT1));
5201 : dev_info(rdev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
5202 : RREG32(CP_STALLED_STAT2));
5203 : dev_info(rdev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
5204 : RREG32(CP_STALLED_STAT3));
5205 : dev_info(rdev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
5206 : RREG32(CP_CPF_BUSY_STAT));
5207 : dev_info(rdev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
5208 : RREG32(CP_CPF_STALLED_STAT1));
5209 : dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));
5210 : dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));
5211 : dev_info(rdev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
5212 : RREG32(CP_CPC_STALLED_STAT1));
5213 : dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));
5214 0 : }
5215 :
5216 : /**
5217 : * cik_gpu_check_soft_reset - check which blocks are busy
5218 : *
5219 : * @rdev: radeon_device pointer
5220 : *
5221 : * Check which blocks are busy and return the relevant reset
5222 : * mask to be used by cik_gpu_soft_reset().
5223 : * Returns a mask of the blocks to be reset.
5224 : */
5225 0 : u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)
5226 : {
5227 : u32 reset_mask = 0;
5228 : u32 tmp;
5229 :
5230 : /* GRBM_STATUS */
5231 0 : tmp = RREG32(GRBM_STATUS);
5232 0 : if (tmp & (PA_BUSY | SC_BUSY |
5233 : BCI_BUSY | SX_BUSY |
5234 : TA_BUSY | VGT_BUSY |
5235 : DB_BUSY | CB_BUSY |
5236 : GDS_BUSY | SPI_BUSY |
5237 : IA_BUSY | IA_BUSY_NO_DMA))
5238 0 : reset_mask |= RADEON_RESET_GFX;
5239 :
5240 0 : if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
5241 0 : reset_mask |= RADEON_RESET_CP;
5242 :
5243 : /* GRBM_STATUS2 */
5244 0 : tmp = RREG32(GRBM_STATUS2);
5245 0 : if (tmp & RLC_BUSY)
5246 0 : reset_mask |= RADEON_RESET_RLC;
5247 :
5248 : /* SDMA0_STATUS_REG */
5249 0 : tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
5250 0 : if (!(tmp & SDMA_IDLE))
5251 0 : reset_mask |= RADEON_RESET_DMA;
5252 :
5253 : /* SDMA1_STATUS_REG */
5254 0 : tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
5255 0 : if (!(tmp & SDMA_IDLE))
5256 0 : reset_mask |= RADEON_RESET_DMA1;
5257 :
5258 : /* SRBM_STATUS2 */
5259 0 : tmp = RREG32(SRBM_STATUS2);
5260 0 : if (tmp & SDMA_BUSY)
5261 0 : reset_mask |= RADEON_RESET_DMA;
5262 :
5263 0 : if (tmp & SDMA1_BUSY)
5264 0 : reset_mask |= RADEON_RESET_DMA1;
5265 :
5266 : /* SRBM_STATUS */
5267 0 : tmp = RREG32(SRBM_STATUS);
5268 :
5269 0 : if (tmp & IH_BUSY)
5270 0 : reset_mask |= RADEON_RESET_IH;
5271 :
5272 0 : if (tmp & SEM_BUSY)
5273 0 : reset_mask |= RADEON_RESET_SEM;
5274 :
5275 0 : if (tmp & GRBM_RQ_PENDING)
5276 0 : reset_mask |= RADEON_RESET_GRBM;
5277 :
5278 0 : if (tmp & VMC_BUSY)
5279 0 : reset_mask |= RADEON_RESET_VMC;
5280 :
5281 0 : if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
5282 : MCC_BUSY | MCD_BUSY))
5283 0 : reset_mask |= RADEON_RESET_MC;
5284 :
5285 0 : if (evergreen_is_display_hung(rdev))
5286 0 : reset_mask |= RADEON_RESET_DISPLAY;
5287 :
5288 : /* Skip MC reset as it's mostly likely not hung, just busy */
5289 0 : if (reset_mask & RADEON_RESET_MC) {
5290 : DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
5291 0 : reset_mask &= ~RADEON_RESET_MC;
5292 0 : }
5293 :
5294 0 : return reset_mask;
5295 : }
5296 :
5297 : /**
5298 : * cik_gpu_soft_reset - soft reset GPU
5299 : *
5300 : * @rdev: radeon_device pointer
5301 : * @reset_mask: mask of which blocks to reset
5302 : *
5303 : * Soft reset the blocks specified in @reset_mask.
5304 : */
5305 0 : static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
5306 : {
5307 0 : struct evergreen_mc_save save;
5308 : u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5309 : u32 tmp;
5310 :
5311 0 : if (reset_mask == 0)
5312 0 : return;
5313 :
5314 : dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
5315 :
5316 0 : cik_print_gpu_status_regs(rdev);
5317 : dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
5318 : RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
5319 : dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
5320 : RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
5321 :
5322 : /* disable CG/PG */
5323 0 : cik_fini_pg(rdev);
5324 0 : cik_fini_cg(rdev);
5325 :
5326 : /* stop the rlc */
5327 0 : cik_rlc_stop(rdev);
5328 :
5329 : /* Disable GFX parsing/prefetching */
5330 0 : WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
5331 :
5332 : /* Disable MEC parsing/prefetching */
5333 0 : WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
5334 :
5335 0 : if (reset_mask & RADEON_RESET_DMA) {
5336 : /* sdma0 */
5337 0 : tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5338 0 : tmp |= SDMA_HALT;
5339 0 : WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
5340 0 : }
5341 0 : if (reset_mask & RADEON_RESET_DMA1) {
5342 : /* sdma1 */
5343 0 : tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5344 0 : tmp |= SDMA_HALT;
5345 0 : WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5346 0 : }
5347 :
5348 0 : evergreen_mc_stop(rdev, &save);
5349 0 : if (evergreen_mc_wait_for_idle(rdev)) {
5350 0 : dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5351 0 : }
5352 :
5353 0 : if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP))
5354 0 : grbm_soft_reset = SOFT_RESET_CP | SOFT_RESET_GFX;
5355 :
5356 0 : if (reset_mask & RADEON_RESET_CP) {
5357 0 : grbm_soft_reset |= SOFT_RESET_CP;
5358 :
5359 : srbm_soft_reset |= SOFT_RESET_GRBM;
5360 0 : }
5361 :
5362 0 : if (reset_mask & RADEON_RESET_DMA)
5363 0 : srbm_soft_reset |= SOFT_RESET_SDMA;
5364 :
5365 0 : if (reset_mask & RADEON_RESET_DMA1)
5366 0 : srbm_soft_reset |= SOFT_RESET_SDMA1;
5367 :
5368 0 : if (reset_mask & RADEON_RESET_DISPLAY)
5369 0 : srbm_soft_reset |= SOFT_RESET_DC;
5370 :
5371 0 : if (reset_mask & RADEON_RESET_RLC)
5372 0 : grbm_soft_reset |= SOFT_RESET_RLC;
5373 :
5374 0 : if (reset_mask & RADEON_RESET_SEM)
5375 0 : srbm_soft_reset |= SOFT_RESET_SEM;
5376 :
5377 0 : if (reset_mask & RADEON_RESET_IH)
5378 0 : srbm_soft_reset |= SOFT_RESET_IH;
5379 :
5380 0 : if (reset_mask & RADEON_RESET_GRBM)
5381 0 : srbm_soft_reset |= SOFT_RESET_GRBM;
5382 :
5383 0 : if (reset_mask & RADEON_RESET_VMC)
5384 0 : srbm_soft_reset |= SOFT_RESET_VMC;
5385 :
5386 0 : if (!(rdev->flags & RADEON_IS_IGP)) {
5387 0 : if (reset_mask & RADEON_RESET_MC)
5388 0 : srbm_soft_reset |= SOFT_RESET_MC;
5389 : }
5390 :
5391 0 : if (grbm_soft_reset) {
5392 0 : tmp = RREG32(GRBM_SOFT_RESET);
5393 0 : tmp |= grbm_soft_reset;
5394 : dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5395 0 : WREG32(GRBM_SOFT_RESET, tmp);
5396 0 : tmp = RREG32(GRBM_SOFT_RESET);
5397 :
5398 0 : udelay(50);
5399 :
5400 0 : tmp &= ~grbm_soft_reset;
5401 0 : WREG32(GRBM_SOFT_RESET, tmp);
5402 0 : tmp = RREG32(GRBM_SOFT_RESET);
5403 0 : }
5404 :
5405 0 : if (srbm_soft_reset) {
5406 0 : tmp = RREG32(SRBM_SOFT_RESET);
5407 0 : tmp |= srbm_soft_reset;
5408 : dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5409 0 : WREG32(SRBM_SOFT_RESET, tmp);
5410 0 : tmp = RREG32(SRBM_SOFT_RESET);
5411 :
5412 0 : udelay(50);
5413 :
5414 0 : tmp &= ~srbm_soft_reset;
5415 0 : WREG32(SRBM_SOFT_RESET, tmp);
5416 0 : tmp = RREG32(SRBM_SOFT_RESET);
5417 0 : }
5418 :
5419 : /* Wait a little for things to settle down */
5420 0 : udelay(50);
5421 :
5422 0 : evergreen_mc_resume(rdev, &save);
5423 0 : udelay(50);
5424 :
5425 0 : cik_print_gpu_status_regs(rdev);
5426 0 : }
5427 :
5428 : struct kv_reset_save_regs {
5429 : u32 gmcon_reng_execute;
5430 : u32 gmcon_misc;
5431 : u32 gmcon_misc3;
5432 : };
5433 :
5434 0 : static void kv_save_regs_for_reset(struct radeon_device *rdev,
5435 : struct kv_reset_save_regs *save)
5436 : {
5437 0 : save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
5438 0 : save->gmcon_misc = RREG32(GMCON_MISC);
5439 0 : save->gmcon_misc3 = RREG32(GMCON_MISC3);
5440 :
5441 0 : WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
5442 0 : WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
5443 : STCTRL_STUTTER_EN));
5444 0 : }
5445 :
5446 0 : static void kv_restore_regs_for_reset(struct radeon_device *rdev,
5447 : struct kv_reset_save_regs *save)
5448 : {
5449 : int i;
5450 :
5451 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5452 0 : WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
5453 :
5454 0 : for (i = 0; i < 5; i++)
5455 : WREG32(GMCON_PGFSM_WRITE, 0);
5456 :
5457 : WREG32(GMCON_PGFSM_WRITE, 0);
5458 0 : WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
5459 :
5460 0 : for (i = 0; i < 5; i++)
5461 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5462 :
5463 0 : WREG32(GMCON_PGFSM_WRITE, 0x210000);
5464 0 : WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
5465 :
5466 0 : for (i = 0; i < 5; i++)
5467 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5468 :
5469 0 : WREG32(GMCON_PGFSM_WRITE, 0x21003);
5470 0 : WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
5471 :
5472 0 : for (i = 0; i < 5; i++)
5473 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5474 :
5475 0 : WREG32(GMCON_PGFSM_WRITE, 0x2b00);
5476 0 : WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
5477 :
5478 0 : for (i = 0; i < 5; i++)
5479 : WREG32(GMCON_PGFSM_WRITE, 0);
5480 :
5481 : WREG32(GMCON_PGFSM_WRITE, 0);
5482 0 : WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
5483 :
5484 0 : for (i = 0; i < 5; i++)
5485 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5486 :
5487 0 : WREG32(GMCON_PGFSM_WRITE, 0x420000);
5488 0 : WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
5489 :
5490 0 : for (i = 0; i < 5; i++)
5491 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5492 :
5493 0 : WREG32(GMCON_PGFSM_WRITE, 0x120202);
5494 0 : WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
5495 :
5496 0 : for (i = 0; i < 5; i++)
5497 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5498 :
5499 0 : WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
5500 0 : WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
5501 :
5502 0 : for (i = 0; i < 5; i++)
5503 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5504 :
5505 0 : WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
5506 0 : WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
5507 :
5508 0 : for (i = 0; i < 5; i++)
5509 0 : WREG32(GMCON_PGFSM_WRITE, 0);
5510 :
5511 0 : WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
5512 0 : WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
5513 :
5514 0 : WREG32(GMCON_MISC3, save->gmcon_misc3);
5515 0 : WREG32(GMCON_MISC, save->gmcon_misc);
5516 0 : WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
5517 0 : }
5518 :
5519 0 : static void cik_gpu_pci_config_reset(struct radeon_device *rdev)
5520 : {
5521 0 : struct evergreen_mc_save save;
5522 0 : struct kv_reset_save_regs kv_save = { 0 };
5523 : u32 tmp, i;
5524 :
5525 : dev_info(rdev->dev, "GPU pci config reset\n");
5526 :
5527 : /* disable dpm? */
5528 :
5529 : /* disable cg/pg */
5530 0 : cik_fini_pg(rdev);
5531 0 : cik_fini_cg(rdev);
5532 :
5533 : /* Disable GFX parsing/prefetching */
5534 0 : WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
5535 :
5536 : /* Disable MEC parsing/prefetching */
5537 0 : WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
5538 :
5539 : /* sdma0 */
5540 0 : tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5541 0 : tmp |= SDMA_HALT;
5542 0 : WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
5543 : /* sdma1 */
5544 0 : tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5545 0 : tmp |= SDMA_HALT;
5546 0 : WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5547 : /* XXX other engines? */
5548 :
5549 : /* halt the rlc, disable cp internal ints */
5550 0 : cik_rlc_stop(rdev);
5551 :
5552 0 : udelay(50);
5553 :
5554 : /* disable mem access */
5555 0 : evergreen_mc_stop(rdev, &save);
5556 0 : if (evergreen_mc_wait_for_idle(rdev)) {
5557 0 : dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
5558 0 : }
5559 :
5560 0 : if (rdev->flags & RADEON_IS_IGP)
5561 0 : kv_save_regs_for_reset(rdev, &kv_save);
5562 :
5563 : /* disable BM */
5564 : pci_clear_master(rdev->pdev);
5565 : /* reset */
5566 0 : radeon_pci_config_reset(rdev);
5567 :
5568 0 : udelay(100);
5569 :
5570 : /* wait for asic to come out of reset */
5571 0 : for (i = 0; i < rdev->usec_timeout; i++) {
5572 0 : if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
5573 : break;
5574 0 : udelay(1);
5575 : }
5576 :
5577 : /* does asic init need to be run first??? */
5578 0 : if (rdev->flags & RADEON_IS_IGP)
5579 0 : kv_restore_regs_for_reset(rdev, &kv_save);
5580 0 : }
5581 :
5582 : /**
5583 : * cik_asic_reset - soft reset GPU
5584 : *
5585 : * @rdev: radeon_device pointer
5586 : *
5587 : * Look up which blocks are hung and attempt
5588 : * to reset them.
5589 : * Returns 0 for success.
5590 : */
5591 0 : int cik_asic_reset(struct radeon_device *rdev)
5592 : {
5593 : u32 reset_mask;
5594 :
5595 0 : reset_mask = cik_gpu_check_soft_reset(rdev);
5596 :
5597 0 : if (reset_mask)
5598 0 : r600_set_bios_scratch_engine_hung(rdev, true);
5599 :
5600 : /* try soft reset */
5601 0 : cik_gpu_soft_reset(rdev, reset_mask);
5602 :
5603 0 : reset_mask = cik_gpu_check_soft_reset(rdev);
5604 :
5605 : /* try pci config reset */
5606 0 : if (reset_mask && radeon_hard_reset)
5607 0 : cik_gpu_pci_config_reset(rdev);
5608 :
5609 0 : reset_mask = cik_gpu_check_soft_reset(rdev);
5610 :
5611 0 : if (!reset_mask)
5612 0 : r600_set_bios_scratch_engine_hung(rdev, false);
5613 :
5614 0 : return 0;
5615 : }
5616 :
5617 : /**
5618 : * cik_gfx_is_lockup - check if the 3D engine is locked up
5619 : *
5620 : * @rdev: radeon_device pointer
5621 : * @ring: radeon_ring structure holding ring information
5622 : *
5623 : * Check if the 3D engine is locked up (CIK).
5624 : * Returns true if the engine is locked, false if not.
5625 : */
5626 0 : bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
5627 : {
5628 0 : u32 reset_mask = cik_gpu_check_soft_reset(rdev);
5629 :
5630 0 : if (!(reset_mask & (RADEON_RESET_GFX |
5631 : RADEON_RESET_COMPUTE |
5632 : RADEON_RESET_CP))) {
5633 0 : radeon_ring_lockup_update(rdev, ring);
5634 0 : return false;
5635 : }
5636 0 : return radeon_ring_test_lockup(rdev, ring);
5637 0 : }
5638 :
5639 : /* MC */
5640 : /**
5641 : * cik_mc_program - program the GPU memory controller
5642 : *
5643 : * @rdev: radeon_device pointer
5644 : *
5645 : * Set the location of vram, gart, and AGP in the GPU's
5646 : * physical address space (CIK).
5647 : */
5648 0 : static void cik_mc_program(struct radeon_device *rdev)
5649 : {
5650 0 : struct evergreen_mc_save save;
5651 : u32 tmp;
5652 : int i, j;
5653 :
5654 : /* Initialize HDP */
5655 0 : for (i = 0, j = 0; i < 32; i++, j += 0x18) {
5656 0 : WREG32((0x2c14 + j), 0x00000000);
5657 0 : WREG32((0x2c18 + j), 0x00000000);
5658 0 : WREG32((0x2c1c + j), 0x00000000);
5659 0 : WREG32((0x2c20 + j), 0x00000000);
5660 0 : WREG32((0x2c24 + j), 0x00000000);
5661 : }
5662 0 : WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
5663 :
5664 0 : evergreen_mc_stop(rdev, &save);
5665 0 : if (radeon_mc_wait_for_idle(rdev)) {
5666 0 : dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5667 0 : }
5668 : /* Lockout access through VGA aperture*/
5669 0 : WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
5670 : /* Update configuration */
5671 0 : WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
5672 : rdev->mc.vram_start >> 12);
5673 0 : WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
5674 : rdev->mc.vram_end >> 12);
5675 0 : WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
5676 : rdev->vram_scratch.gpu_addr >> 12);
5677 0 : tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
5678 0 : tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
5679 0 : WREG32(MC_VM_FB_LOCATION, tmp);
5680 : /* XXX double check these! */
5681 0 : WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
5682 0 : WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
5683 0 : WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
5684 0 : WREG32(MC_VM_AGP_BASE, 0);
5685 0 : WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
5686 0 : WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
5687 0 : if (radeon_mc_wait_for_idle(rdev)) {
5688 0 : dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5689 0 : }
5690 0 : evergreen_mc_resume(rdev, &save);
5691 : /* we need to own VRAM, so turn off the VGA renderer here
5692 : * to stop it overwriting our objects */
5693 0 : rv515_vga_render_disable(rdev);
5694 0 : }
5695 :
5696 : /**
5697 : * cik_mc_init - initialize the memory controller driver params
5698 : *
5699 : * @rdev: radeon_device pointer
5700 : *
5701 : * Look up the amount of vram, vram width, and decide how to place
5702 : * vram and gart within the GPU's physical address space (CIK).
5703 : * Returns 0 for success.
5704 : */
5705 0 : static int cik_mc_init(struct radeon_device *rdev)
5706 : {
5707 : u32 tmp;
5708 : int chansize, numchan;
5709 :
5710 : /* Get VRAM informations */
5711 0 : rdev->mc.vram_is_ddr = true;
5712 0 : tmp = RREG32(MC_ARB_RAMCFG);
5713 0 : if (tmp & CHANSIZE_MASK) {
5714 : chansize = 64;
5715 0 : } else {
5716 : chansize = 32;
5717 : }
5718 0 : tmp = RREG32(MC_SHARED_CHMAP);
5719 0 : switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
5720 : case 0:
5721 : default:
5722 : numchan = 1;
5723 0 : break;
5724 : case 1:
5725 : numchan = 2;
5726 0 : break;
5727 : case 2:
5728 : numchan = 4;
5729 0 : break;
5730 : case 3:
5731 : numchan = 8;
5732 0 : break;
5733 : case 4:
5734 : numchan = 3;
5735 0 : break;
5736 : case 5:
5737 : numchan = 6;
5738 0 : break;
5739 : case 6:
5740 : numchan = 10;
5741 0 : break;
5742 : case 7:
5743 : numchan = 12;
5744 0 : break;
5745 : case 8:
5746 : numchan = 16;
5747 0 : break;
5748 : }
5749 0 : rdev->mc.vram_width = numchan * chansize;
5750 : /* Could aper size report 0 ? */
5751 0 : rdev->mc.aper_base = rdev->fb_aper_offset;
5752 0 : rdev->mc.aper_size = rdev->fb_aper_size;
5753 : /* size in MB on si */
5754 0 : rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5755 0 : rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5756 0 : rdev->mc.visible_vram_size = rdev->mc.aper_size;
5757 0 : si_vram_gtt_location(rdev, &rdev->mc);
5758 0 : radeon_update_bandwidth_info(rdev);
5759 :
5760 0 : return 0;
5761 : }
5762 :
5763 : /*
5764 : * GART
5765 : * VMID 0 is the physical GPU addresses as used by the kernel.
5766 : * VMIDs 1-15 are used for userspace clients and are handled
5767 : * by the radeon vm/hsa code.
5768 : */
5769 : /**
5770 : * cik_pcie_gart_tlb_flush - gart tlb flush callback
5771 : *
5772 : * @rdev: radeon_device pointer
5773 : *
5774 : * Flush the TLB for the VMID 0 page table (CIK).
5775 : */
5776 0 : void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
5777 : {
5778 : /* flush hdp cache */
5779 0 : WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
5780 :
5781 : /* bits 0-15 are the VM contexts0-15 */
5782 0 : WREG32(VM_INVALIDATE_REQUEST, 0x1);
5783 0 : }
5784 :
5785 0 : static void cik_pcie_init_compute_vmid(struct radeon_device *rdev)
5786 : {
5787 : int i;
5788 : uint32_t sh_mem_bases, sh_mem_config;
5789 :
5790 : sh_mem_bases = 0x6000 | 0x6000 << 16;
5791 : sh_mem_config = ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED);
5792 : sh_mem_config |= DEFAULT_MTYPE(MTYPE_NONCACHED);
5793 :
5794 0 : mutex_lock(&rdev->srbm_mutex);
5795 0 : for (i = 8; i < 16; i++) {
5796 0 : cik_srbm_select(rdev, 0, 0, 0, i);
5797 : /* CP and shaders */
5798 0 : WREG32(SH_MEM_CONFIG, sh_mem_config);
5799 0 : WREG32(SH_MEM_APE1_BASE, 1);
5800 0 : WREG32(SH_MEM_APE1_LIMIT, 0);
5801 0 : WREG32(SH_MEM_BASES, sh_mem_bases);
5802 : }
5803 0 : cik_srbm_select(rdev, 0, 0, 0, 0);
5804 0 : mutex_unlock(&rdev->srbm_mutex);
5805 0 : }
5806 :
5807 : /**
5808 : * cik_pcie_gart_enable - gart enable
5809 : *
5810 : * @rdev: radeon_device pointer
5811 : *
5812 : * This sets up the TLBs, programs the page tables for VMID0,
5813 : * sets up the hw for VMIDs 1-15 which are allocated on
5814 : * demand, and sets up the global locations for the LDS, GDS,
5815 : * and GPUVM for FSA64 clients (CIK).
5816 : * Returns 0 for success, errors for failure.
5817 : */
5818 0 : static int cik_pcie_gart_enable(struct radeon_device *rdev)
5819 : {
5820 : int r, i;
5821 :
5822 0 : if (rdev->gart.robj == NULL) {
5823 0 : dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
5824 0 : return -EINVAL;
5825 : }
5826 0 : r = radeon_gart_table_vram_pin(rdev);
5827 0 : if (r)
5828 0 : return r;
5829 : /* Setup TLB control */
5830 0 : WREG32(MC_VM_MX_L1_TLB_CNTL,
5831 : (0xA << 7) |
5832 : ENABLE_L1_TLB |
5833 : ENABLE_L1_FRAGMENT_PROCESSING |
5834 : SYSTEM_ACCESS_MODE_NOT_IN_SYS |
5835 : ENABLE_ADVANCED_DRIVER_MODEL |
5836 : SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
5837 : /* Setup L2 cache */
5838 0 : WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
5839 : ENABLE_L2_FRAGMENT_PROCESSING |
5840 : ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
5841 : ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
5842 : EFFECTIVE_L2_QUEUE_SIZE(7) |
5843 : CONTEXT1_IDENTITY_ACCESS_MODE(1));
5844 0 : WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
5845 0 : WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5846 : BANK_SELECT(4) |
5847 : L2_CACHE_BIGK_FRAGMENT_SIZE(4));
5848 : /* setup context0 */
5849 0 : WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
5850 0 : WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
5851 0 : WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
5852 0 : WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
5853 : (u32)(rdev->dummy_page.addr >> 12));
5854 0 : WREG32(VM_CONTEXT0_CNTL2, 0);
5855 0 : WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
5856 : RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
5857 :
5858 0 : WREG32(0x15D4, 0);
5859 0 : WREG32(0x15D8, 0);
5860 0 : WREG32(0x15DC, 0);
5861 :
5862 : /* restore context1-15 */
5863 : /* set vm size, must be a multiple of 4 */
5864 0 : WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
5865 0 : WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
5866 0 : for (i = 1; i < 16; i++) {
5867 0 : if (i < 8)
5868 0 : WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
5869 : rdev->vm_manager.saved_table_addr[i]);
5870 : else
5871 0 : WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
5872 : rdev->vm_manager.saved_table_addr[i]);
5873 : }
5874 :
5875 : /* enable context1-15 */
5876 0 : WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
5877 : (u32)(rdev->dummy_page.addr >> 12));
5878 0 : WREG32(VM_CONTEXT1_CNTL2, 4);
5879 0 : WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
5880 : PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
5881 : RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5882 : RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
5883 : DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5884 : DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
5885 : PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
5886 : PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
5887 : VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
5888 : VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
5889 : READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
5890 : READ_PROTECTION_FAULT_ENABLE_DEFAULT |
5891 : WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5892 : WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
5893 :
5894 0 : if (rdev->family == CHIP_KAVERI) {
5895 0 : u32 tmp = RREG32(CHUB_CONTROL);
5896 0 : tmp &= ~BYPASS_VM;
5897 0 : WREG32(CHUB_CONTROL, tmp);
5898 0 : }
5899 :
5900 : /* XXX SH_MEM regs */
5901 : /* where to put LDS, scratch, GPUVM in FSA64 space */
5902 0 : mutex_lock(&rdev->srbm_mutex);
5903 0 : for (i = 0; i < 16; i++) {
5904 0 : cik_srbm_select(rdev, 0, 0, 0, i);
5905 : /* CP and shaders */
5906 0 : WREG32(SH_MEM_CONFIG, 0);
5907 0 : WREG32(SH_MEM_APE1_BASE, 1);
5908 0 : WREG32(SH_MEM_APE1_LIMIT, 0);
5909 0 : WREG32(SH_MEM_BASES, 0);
5910 : /* SDMA GFX */
5911 0 : WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);
5912 0 : WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);
5913 0 : WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);
5914 0 : WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
5915 : /* XXX SDMA RLC - todo */
5916 : }
5917 0 : cik_srbm_select(rdev, 0, 0, 0, 0);
5918 0 : mutex_unlock(&rdev->srbm_mutex);
5919 :
5920 0 : cik_pcie_init_compute_vmid(rdev);
5921 :
5922 0 : cik_pcie_gart_tlb_flush(rdev);
5923 : DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
5924 : (unsigned)(rdev->mc.gtt_size >> 20),
5925 : (unsigned long long)rdev->gart.table_addr);
5926 0 : rdev->gart.ready = true;
5927 0 : return 0;
5928 0 : }
5929 :
5930 : /**
5931 : * cik_pcie_gart_disable - gart disable
5932 : *
5933 : * @rdev: radeon_device pointer
5934 : *
5935 : * This disables all VM page table (CIK).
5936 : */
5937 0 : static void cik_pcie_gart_disable(struct radeon_device *rdev)
5938 : {
5939 : unsigned i;
5940 :
5941 0 : for (i = 1; i < 16; ++i) {
5942 : uint32_t reg;
5943 0 : if (i < 8)
5944 0 : reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
5945 : else
5946 0 : reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
5947 0 : rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
5948 : }
5949 :
5950 : /* Disable all tables */
5951 0 : WREG32(VM_CONTEXT0_CNTL, 0);
5952 0 : WREG32(VM_CONTEXT1_CNTL, 0);
5953 : /* Setup TLB control */
5954 0 : WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
5955 : SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
5956 : /* Setup L2 cache */
5957 0 : WREG32(VM_L2_CNTL,
5958 : ENABLE_L2_FRAGMENT_PROCESSING |
5959 : ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
5960 : ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
5961 : EFFECTIVE_L2_QUEUE_SIZE(7) |
5962 : CONTEXT1_IDENTITY_ACCESS_MODE(1));
5963 0 : WREG32(VM_L2_CNTL2, 0);
5964 0 : WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5965 : L2_CACHE_BIGK_FRAGMENT_SIZE(6));
5966 0 : radeon_gart_table_vram_unpin(rdev);
5967 0 : }
5968 :
5969 : /**
5970 : * cik_pcie_gart_fini - vm fini callback
5971 : *
5972 : * @rdev: radeon_device pointer
5973 : *
5974 : * Tears down the driver GART/VM setup (CIK).
5975 : */
5976 0 : static void cik_pcie_gart_fini(struct radeon_device *rdev)
5977 : {
5978 0 : cik_pcie_gart_disable(rdev);
5979 0 : radeon_gart_table_vram_free(rdev);
5980 0 : radeon_gart_fini(rdev);
5981 0 : }
5982 :
5983 : /* vm parser */
5984 : /**
5985 : * cik_ib_parse - vm ib_parse callback
5986 : *
5987 : * @rdev: radeon_device pointer
5988 : * @ib: indirect buffer pointer
5989 : *
5990 : * CIK uses hw IB checking so this is a nop (CIK).
5991 : */
5992 0 : int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
5993 : {
5994 0 : return 0;
5995 : }
5996 :
5997 : /*
5998 : * vm
5999 : * VMID 0 is the physical GPU addresses as used by the kernel.
6000 : * VMIDs 1-15 are used for userspace clients and are handled
6001 : * by the radeon vm/hsa code.
6002 : */
6003 : /**
6004 : * cik_vm_init - cik vm init callback
6005 : *
6006 : * @rdev: radeon_device pointer
6007 : *
6008 : * Inits cik specific vm parameters (number of VMs, base of vram for
6009 : * VMIDs 1-15) (CIK).
6010 : * Returns 0 for success.
6011 : */
6012 0 : int cik_vm_init(struct radeon_device *rdev)
6013 : {
6014 : /*
6015 : * number of VMs
6016 : * VMID 0 is reserved for System
6017 : * radeon graphics/compute will use VMIDs 1-7
6018 : * amdkfd will use VMIDs 8-15
6019 : */
6020 0 : rdev->vm_manager.nvm = RADEON_NUM_OF_VMIDS;
6021 : /* base offset of vram pages */
6022 0 : if (rdev->flags & RADEON_IS_IGP) {
6023 0 : u64 tmp = RREG32(MC_VM_FB_OFFSET);
6024 0 : tmp <<= 22;
6025 0 : rdev->vm_manager.vram_base_offset = tmp;
6026 0 : } else
6027 0 : rdev->vm_manager.vram_base_offset = 0;
6028 :
6029 0 : return 0;
6030 : }
6031 :
6032 : /**
6033 : * cik_vm_fini - cik vm fini callback
6034 : *
6035 : * @rdev: radeon_device pointer
6036 : *
6037 : * Tear down any asic specific VM setup (CIK).
6038 : */
6039 0 : void cik_vm_fini(struct radeon_device *rdev)
6040 : {
6041 0 : }
6042 :
6043 : /**
6044 : * cik_vm_decode_fault - print human readable fault info
6045 : *
6046 : * @rdev: radeon_device pointer
6047 : * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
6048 : * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
6049 : *
6050 : * Print human readable fault information (CIK).
6051 : */
6052 0 : static void cik_vm_decode_fault(struct radeon_device *rdev,
6053 : u32 status, u32 addr, u32 mc_client)
6054 : {
6055 : u32 mc_id;
6056 0 : u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
6057 0 : u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
6058 0 : char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
6059 0 : (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
6060 :
6061 0 : if (rdev->family == CHIP_HAWAII)
6062 0 : mc_id = (status & HAWAII_MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
6063 : else
6064 0 : mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
6065 :
6066 0 : printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
6067 : protections, vmid, addr,
6068 : (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
6069 : block, mc_client, mc_id);
6070 0 : }
6071 :
6072 : /**
6073 : * cik_vm_flush - cik vm flush using the CP
6074 : *
6075 : * @rdev: radeon_device pointer
6076 : *
6077 : * Update the page table base and flush the VM TLB
6078 : * using the CP (CIK).
6079 : */
6080 0 : void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
6081 : unsigned vm_id, uint64_t pd_addr)
6082 : {
6083 0 : int usepfp = (ring->idx == RADEON_RING_TYPE_GFX_INDEX);
6084 :
6085 0 : radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6086 0 : radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
6087 : WRITE_DATA_DST_SEL(0)));
6088 0 : if (vm_id < 8) {
6089 0 : radeon_ring_write(ring,
6090 0 : (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
6091 0 : } else {
6092 0 : radeon_ring_write(ring,
6093 0 : (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
6094 : }
6095 0 : radeon_ring_write(ring, 0);
6096 0 : radeon_ring_write(ring, pd_addr >> 12);
6097 :
6098 : /* update SH_MEM_* regs */
6099 0 : radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6100 0 : radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
6101 : WRITE_DATA_DST_SEL(0)));
6102 0 : radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
6103 0 : radeon_ring_write(ring, 0);
6104 0 : radeon_ring_write(ring, VMID(vm_id));
6105 :
6106 0 : radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
6107 0 : radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
6108 : WRITE_DATA_DST_SEL(0)));
6109 0 : radeon_ring_write(ring, SH_MEM_BASES >> 2);
6110 0 : radeon_ring_write(ring, 0);
6111 :
6112 0 : radeon_ring_write(ring, 0); /* SH_MEM_BASES */
6113 0 : radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */
6114 0 : radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
6115 0 : radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
6116 :
6117 0 : radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6118 0 : radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
6119 : WRITE_DATA_DST_SEL(0)));
6120 0 : radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
6121 0 : radeon_ring_write(ring, 0);
6122 0 : radeon_ring_write(ring, VMID(0));
6123 :
6124 : /* HDP flush */
6125 0 : cik_hdp_flush_cp_ring_emit(rdev, ring->idx);
6126 :
6127 : /* bits 0-15 are the VM contexts0-15 */
6128 0 : radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6129 0 : radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
6130 : WRITE_DATA_DST_SEL(0)));
6131 0 : radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
6132 0 : radeon_ring_write(ring, 0);
6133 0 : radeon_ring_write(ring, 1 << vm_id);
6134 :
6135 : /* wait for the invalidate to complete */
6136 0 : radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6137 0 : radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6138 : WAIT_REG_MEM_FUNCTION(0) | /* always */
6139 : WAIT_REG_MEM_ENGINE(0))); /* me */
6140 0 : radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
6141 0 : radeon_ring_write(ring, 0);
6142 0 : radeon_ring_write(ring, 0); /* ref */
6143 0 : radeon_ring_write(ring, 0); /* mask */
6144 0 : radeon_ring_write(ring, 0x20); /* poll interval */
6145 :
6146 : /* compute doesn't have PFP */
6147 0 : if (usepfp) {
6148 : /* sync PFP to ME, otherwise we might get invalid PFP reads */
6149 0 : radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6150 0 : radeon_ring_write(ring, 0x0);
6151 0 : }
6152 0 : }
6153 :
6154 : /*
6155 : * RLC
6156 : * The RLC is a multi-purpose microengine that handles a
6157 : * variety of functions, the most important of which is
6158 : * the interrupt controller.
6159 : */
6160 0 : static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
6161 : bool enable)
6162 : {
6163 0 : u32 tmp = RREG32(CP_INT_CNTL_RING0);
6164 :
6165 0 : if (enable)
6166 0 : tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6167 : else
6168 0 : tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6169 0 : WREG32(CP_INT_CNTL_RING0, tmp);
6170 0 : }
6171 :
6172 0 : static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
6173 : {
6174 : u32 tmp;
6175 :
6176 0 : tmp = RREG32(RLC_LB_CNTL);
6177 0 : if (enable)
6178 0 : tmp |= LOAD_BALANCE_ENABLE;
6179 : else
6180 0 : tmp &= ~LOAD_BALANCE_ENABLE;
6181 0 : WREG32(RLC_LB_CNTL, tmp);
6182 0 : }
6183 :
6184 0 : static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
6185 : {
6186 : u32 i, j, k;
6187 : u32 mask;
6188 :
6189 0 : mutex_lock(&rdev->grbm_idx_mutex);
6190 0 : for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
6191 0 : for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
6192 0 : cik_select_se_sh(rdev, i, j);
6193 0 : for (k = 0; k < rdev->usec_timeout; k++) {
6194 0 : if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
6195 : break;
6196 0 : udelay(1);
6197 : }
6198 : }
6199 : }
6200 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6201 0 : mutex_unlock(&rdev->grbm_idx_mutex);
6202 :
6203 : mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
6204 0 : for (k = 0; k < rdev->usec_timeout; k++) {
6205 0 : if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
6206 : break;
6207 0 : udelay(1);
6208 : }
6209 0 : }
6210 :
6211 0 : static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)
6212 : {
6213 : u32 tmp;
6214 :
6215 0 : tmp = RREG32(RLC_CNTL);
6216 0 : if (tmp != rlc)
6217 0 : WREG32(RLC_CNTL, rlc);
6218 0 : }
6219 :
6220 0 : static u32 cik_halt_rlc(struct radeon_device *rdev)
6221 : {
6222 : u32 data, orig;
6223 :
6224 0 : orig = data = RREG32(RLC_CNTL);
6225 :
6226 0 : if (data & RLC_ENABLE) {
6227 : u32 i;
6228 :
6229 0 : data &= ~RLC_ENABLE;
6230 0 : WREG32(RLC_CNTL, data);
6231 :
6232 0 : for (i = 0; i < rdev->usec_timeout; i++) {
6233 0 : if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
6234 : break;
6235 0 : udelay(1);
6236 : }
6237 :
6238 0 : cik_wait_for_rlc_serdes(rdev);
6239 0 : }
6240 :
6241 0 : return orig;
6242 : }
6243 :
6244 0 : void cik_enter_rlc_safe_mode(struct radeon_device *rdev)
6245 : {
6246 : u32 tmp, i, mask;
6247 :
6248 : tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
6249 0 : WREG32(RLC_GPR_REG2, tmp);
6250 :
6251 : mask = GFX_POWER_STATUS | GFX_CLOCK_STATUS;
6252 0 : for (i = 0; i < rdev->usec_timeout; i++) {
6253 0 : if ((RREG32(RLC_GPM_STAT) & mask) == mask)
6254 : break;
6255 0 : udelay(1);
6256 : }
6257 :
6258 0 : for (i = 0; i < rdev->usec_timeout; i++) {
6259 0 : if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
6260 : break;
6261 0 : udelay(1);
6262 : }
6263 0 : }
6264 :
6265 0 : void cik_exit_rlc_safe_mode(struct radeon_device *rdev)
6266 : {
6267 : u32 tmp;
6268 :
6269 : tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
6270 0 : WREG32(RLC_GPR_REG2, tmp);
6271 0 : }
6272 :
6273 : /**
6274 : * cik_rlc_stop - stop the RLC ME
6275 : *
6276 : * @rdev: radeon_device pointer
6277 : *
6278 : * Halt the RLC ME (MicroEngine) (CIK).
6279 : */
6280 0 : static void cik_rlc_stop(struct radeon_device *rdev)
6281 : {
6282 0 : WREG32(RLC_CNTL, 0);
6283 :
6284 0 : cik_enable_gui_idle_interrupt(rdev, false);
6285 :
6286 0 : cik_wait_for_rlc_serdes(rdev);
6287 0 : }
6288 :
6289 : /**
6290 : * cik_rlc_start - start the RLC ME
6291 : *
6292 : * @rdev: radeon_device pointer
6293 : *
6294 : * Unhalt the RLC ME (MicroEngine) (CIK).
6295 : */
6296 0 : static void cik_rlc_start(struct radeon_device *rdev)
6297 : {
6298 0 : WREG32(RLC_CNTL, RLC_ENABLE);
6299 :
6300 0 : cik_enable_gui_idle_interrupt(rdev, true);
6301 :
6302 0 : udelay(50);
6303 0 : }
6304 :
6305 : /**
6306 : * cik_rlc_resume - setup the RLC hw
6307 : *
6308 : * @rdev: radeon_device pointer
6309 : *
6310 : * Initialize the RLC registers, load the ucode,
6311 : * and start the RLC (CIK).
6312 : * Returns 0 for success, -EINVAL if the ucode is not available.
6313 : */
6314 0 : static int cik_rlc_resume(struct radeon_device *rdev)
6315 : {
6316 : u32 i, size, tmp;
6317 :
6318 0 : if (!rdev->rlc_fw)
6319 0 : return -EINVAL;
6320 :
6321 0 : cik_rlc_stop(rdev);
6322 :
6323 : /* disable CG */
6324 0 : tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
6325 0 : WREG32(RLC_CGCG_CGLS_CTRL, tmp);
6326 :
6327 0 : si_rlc_reset(rdev);
6328 :
6329 0 : cik_init_pg(rdev);
6330 :
6331 0 : cik_init_cg(rdev);
6332 :
6333 0 : WREG32(RLC_LB_CNTR_INIT, 0);
6334 0 : WREG32(RLC_LB_CNTR_MAX, 0x00008000);
6335 :
6336 0 : mutex_lock(&rdev->grbm_idx_mutex);
6337 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6338 0 : WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
6339 0 : WREG32(RLC_LB_PARAMS, 0x00600408);
6340 0 : WREG32(RLC_LB_CNTL, 0x80000004);
6341 0 : mutex_unlock(&rdev->grbm_idx_mutex);
6342 :
6343 0 : WREG32(RLC_MC_CNTL, 0);
6344 0 : WREG32(RLC_UCODE_CNTL, 0);
6345 :
6346 0 : if (rdev->new_fw) {
6347 : const struct rlc_firmware_header_v1_0 *hdr =
6348 0 : (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
6349 0 : const __le32 *fw_data = (const __le32 *)
6350 0 : (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6351 :
6352 0 : radeon_ucode_print_rlc_hdr(&hdr->header);
6353 :
6354 0 : size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
6355 0 : WREG32(RLC_GPM_UCODE_ADDR, 0);
6356 0 : for (i = 0; i < size; i++)
6357 0 : WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
6358 0 : WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version));
6359 0 : } else {
6360 : const __be32 *fw_data;
6361 :
6362 0 : switch (rdev->family) {
6363 : case CHIP_BONAIRE:
6364 : case CHIP_HAWAII:
6365 : default:
6366 : size = BONAIRE_RLC_UCODE_SIZE;
6367 0 : break;
6368 : case CHIP_KAVERI:
6369 : size = KV_RLC_UCODE_SIZE;
6370 0 : break;
6371 : case CHIP_KABINI:
6372 : size = KB_RLC_UCODE_SIZE;
6373 0 : break;
6374 : case CHIP_MULLINS:
6375 : size = ML_RLC_UCODE_SIZE;
6376 0 : break;
6377 : }
6378 :
6379 0 : fw_data = (const __be32 *)rdev->rlc_fw->data;
6380 0 : WREG32(RLC_GPM_UCODE_ADDR, 0);
6381 0 : for (i = 0; i < size; i++)
6382 0 : WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
6383 0 : WREG32(RLC_GPM_UCODE_ADDR, 0);
6384 : }
6385 :
6386 : /* XXX - find out what chips support lbpw */
6387 0 : cik_enable_lbpw(rdev, false);
6388 :
6389 0 : if (rdev->family == CHIP_BONAIRE)
6390 0 : WREG32(RLC_DRIVER_DMA_STATUS, 0);
6391 :
6392 0 : cik_rlc_start(rdev);
6393 :
6394 0 : return 0;
6395 0 : }
6396 :
6397 0 : static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
6398 : {
6399 : u32 data, orig, tmp, tmp2;
6400 :
6401 0 : orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
6402 :
6403 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
6404 0 : cik_enable_gui_idle_interrupt(rdev, true);
6405 :
6406 0 : tmp = cik_halt_rlc(rdev);
6407 :
6408 0 : mutex_lock(&rdev->grbm_idx_mutex);
6409 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6410 0 : WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6411 0 : WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6412 : tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
6413 0 : WREG32(RLC_SERDES_WR_CTRL, tmp2);
6414 0 : mutex_unlock(&rdev->grbm_idx_mutex);
6415 :
6416 0 : cik_update_rlc(rdev, tmp);
6417 :
6418 0 : data |= CGCG_EN | CGLS_EN;
6419 0 : } else {
6420 0 : cik_enable_gui_idle_interrupt(rdev, false);
6421 :
6422 0 : RREG32(CB_CGTT_SCLK_CTRL);
6423 0 : RREG32(CB_CGTT_SCLK_CTRL);
6424 0 : RREG32(CB_CGTT_SCLK_CTRL);
6425 0 : RREG32(CB_CGTT_SCLK_CTRL);
6426 :
6427 0 : data &= ~(CGCG_EN | CGLS_EN);
6428 : }
6429 :
6430 0 : if (orig != data)
6431 0 : WREG32(RLC_CGCG_CGLS_CTRL, data);
6432 :
6433 0 : }
6434 :
6435 0 : static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
6436 : {
6437 : u32 data, orig, tmp = 0;
6438 :
6439 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
6440 0 : if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) {
6441 0 : if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
6442 0 : orig = data = RREG32(CP_MEM_SLP_CNTL);
6443 0 : data |= CP_MEM_LS_EN;
6444 0 : if (orig != data)
6445 0 : WREG32(CP_MEM_SLP_CNTL, data);
6446 : }
6447 : }
6448 :
6449 0 : orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6450 0 : data |= 0x00000001;
6451 0 : data &= 0xfffffffd;
6452 0 : if (orig != data)
6453 0 : WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
6454 :
6455 0 : tmp = cik_halt_rlc(rdev);
6456 :
6457 0 : mutex_lock(&rdev->grbm_idx_mutex);
6458 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6459 0 : WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6460 0 : WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6461 : data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
6462 0 : WREG32(RLC_SERDES_WR_CTRL, data);
6463 0 : mutex_unlock(&rdev->grbm_idx_mutex);
6464 :
6465 0 : cik_update_rlc(rdev, tmp);
6466 :
6467 0 : if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS) {
6468 0 : orig = data = RREG32(CGTS_SM_CTRL_REG);
6469 0 : data &= ~SM_MODE_MASK;
6470 0 : data |= SM_MODE(0x2);
6471 0 : data |= SM_MODE_ENABLE;
6472 0 : data &= ~CGTS_OVERRIDE;
6473 0 : if ((rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) &&
6474 0 : (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS_LS))
6475 0 : data &= ~CGTS_LS_OVERRIDE;
6476 0 : data &= ~ON_MONITOR_ADD_MASK;
6477 0 : data |= ON_MONITOR_ADD_EN;
6478 0 : data |= ON_MONITOR_ADD(0x96);
6479 0 : if (orig != data)
6480 0 : WREG32(CGTS_SM_CTRL_REG, data);
6481 : }
6482 : } else {
6483 0 : orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6484 0 : data |= 0x00000003;
6485 0 : if (orig != data)
6486 0 : WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
6487 :
6488 0 : data = RREG32(RLC_MEM_SLP_CNTL);
6489 0 : if (data & RLC_MEM_LS_EN) {
6490 0 : data &= ~RLC_MEM_LS_EN;
6491 0 : WREG32(RLC_MEM_SLP_CNTL, data);
6492 0 : }
6493 :
6494 0 : data = RREG32(CP_MEM_SLP_CNTL);
6495 0 : if (data & CP_MEM_LS_EN) {
6496 0 : data &= ~CP_MEM_LS_EN;
6497 0 : WREG32(CP_MEM_SLP_CNTL, data);
6498 0 : }
6499 :
6500 0 : orig = data = RREG32(CGTS_SM_CTRL_REG);
6501 0 : data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
6502 0 : if (orig != data)
6503 0 : WREG32(CGTS_SM_CTRL_REG, data);
6504 :
6505 0 : tmp = cik_halt_rlc(rdev);
6506 :
6507 0 : mutex_lock(&rdev->grbm_idx_mutex);
6508 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6509 0 : WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
6510 0 : WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
6511 : data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
6512 0 : WREG32(RLC_SERDES_WR_CTRL, data);
6513 0 : mutex_unlock(&rdev->grbm_idx_mutex);
6514 :
6515 0 : cik_update_rlc(rdev, tmp);
6516 : }
6517 0 : }
6518 :
6519 : static const u32 mc_cg_registers[] =
6520 : {
6521 : MC_HUB_MISC_HUB_CG,
6522 : MC_HUB_MISC_SIP_CG,
6523 : MC_HUB_MISC_VM_CG,
6524 : MC_XPB_CLK_GAT,
6525 : ATC_MISC_CG,
6526 : MC_CITF_MISC_WR_CG,
6527 : MC_CITF_MISC_RD_CG,
6528 : MC_CITF_MISC_VM_CG,
6529 : VM_L2_CG,
6530 : };
6531 :
6532 0 : static void cik_enable_mc_ls(struct radeon_device *rdev,
6533 : bool enable)
6534 : {
6535 : int i;
6536 : u32 orig, data;
6537 :
6538 0 : for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
6539 0 : orig = data = RREG32(mc_cg_registers[i]);
6540 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
6541 0 : data |= MC_LS_ENABLE;
6542 : else
6543 0 : data &= ~MC_LS_ENABLE;
6544 0 : if (data != orig)
6545 0 : WREG32(mc_cg_registers[i], data);
6546 : }
6547 0 : }
6548 :
6549 0 : static void cik_enable_mc_mgcg(struct radeon_device *rdev,
6550 : bool enable)
6551 : {
6552 : int i;
6553 : u32 orig, data;
6554 :
6555 0 : for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
6556 0 : orig = data = RREG32(mc_cg_registers[i]);
6557 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
6558 0 : data |= MC_CG_ENABLE;
6559 : else
6560 0 : data &= ~MC_CG_ENABLE;
6561 0 : if (data != orig)
6562 0 : WREG32(mc_cg_registers[i], data);
6563 : }
6564 0 : }
6565 :
6566 0 : static void cik_enable_sdma_mgcg(struct radeon_device *rdev,
6567 : bool enable)
6568 : {
6569 : u32 orig, data;
6570 :
6571 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
6572 0 : WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
6573 0 : WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
6574 0 : } else {
6575 0 : orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
6576 0 : data |= 0xff000000;
6577 0 : if (data != orig)
6578 0 : WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
6579 :
6580 0 : orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
6581 0 : data |= 0xff000000;
6582 0 : if (data != orig)
6583 0 : WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
6584 : }
6585 0 : }
6586 :
6587 0 : static void cik_enable_sdma_mgls(struct radeon_device *rdev,
6588 : bool enable)
6589 : {
6590 : u32 orig, data;
6591 :
6592 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_LS)) {
6593 0 : orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6594 0 : data |= 0x100;
6595 0 : if (orig != data)
6596 0 : WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6597 :
6598 0 : orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6599 0 : data |= 0x100;
6600 0 : if (orig != data)
6601 0 : WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6602 : } else {
6603 0 : orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6604 0 : data &= ~0x100;
6605 0 : if (orig != data)
6606 0 : WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6607 :
6608 0 : orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6609 0 : data &= ~0x100;
6610 0 : if (orig != data)
6611 0 : WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6612 : }
6613 0 : }
6614 :
6615 0 : static void cik_enable_uvd_mgcg(struct radeon_device *rdev,
6616 : bool enable)
6617 : {
6618 : u32 orig, data;
6619 :
6620 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
6621 0 : data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6622 : data = 0xfff;
6623 0 : WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6624 :
6625 0 : orig = data = RREG32(UVD_CGC_CTRL);
6626 0 : data |= DCM;
6627 0 : if (orig != data)
6628 0 : WREG32(UVD_CGC_CTRL, data);
6629 : } else {
6630 0 : data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6631 0 : data &= ~0xfff;
6632 0 : WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6633 :
6634 0 : orig = data = RREG32(UVD_CGC_CTRL);
6635 0 : data &= ~DCM;
6636 0 : if (orig != data)
6637 0 : WREG32(UVD_CGC_CTRL, data);
6638 : }
6639 0 : }
6640 :
6641 0 : static void cik_enable_bif_mgls(struct radeon_device *rdev,
6642 : bool enable)
6643 : {
6644 : u32 orig, data;
6645 :
6646 0 : orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
6647 :
6648 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
6649 0 : data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
6650 : REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
6651 : else
6652 0 : data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
6653 : REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
6654 :
6655 0 : if (orig != data)
6656 0 : WREG32_PCIE_PORT(PCIE_CNTL2, data);
6657 0 : }
6658 :
6659 0 : static void cik_enable_hdp_mgcg(struct radeon_device *rdev,
6660 : bool enable)
6661 : {
6662 : u32 orig, data;
6663 :
6664 0 : orig = data = RREG32(HDP_HOST_PATH_CNTL);
6665 :
6666 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
6667 0 : data &= ~CLOCK_GATING_DIS;
6668 : else
6669 0 : data |= CLOCK_GATING_DIS;
6670 :
6671 0 : if (orig != data)
6672 0 : WREG32(HDP_HOST_PATH_CNTL, data);
6673 0 : }
6674 :
6675 0 : static void cik_enable_hdp_ls(struct radeon_device *rdev,
6676 : bool enable)
6677 : {
6678 : u32 orig, data;
6679 :
6680 0 : orig = data = RREG32(HDP_MEM_POWER_LS);
6681 :
6682 0 : if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
6683 0 : data |= HDP_LS_ENABLE;
6684 : else
6685 0 : data &= ~HDP_LS_ENABLE;
6686 :
6687 0 : if (orig != data)
6688 0 : WREG32(HDP_MEM_POWER_LS, data);
6689 0 : }
6690 :
6691 0 : void cik_update_cg(struct radeon_device *rdev,
6692 : u32 block, bool enable)
6693 : {
6694 :
6695 0 : if (block & RADEON_CG_BLOCK_GFX) {
6696 0 : cik_enable_gui_idle_interrupt(rdev, false);
6697 : /* order matters! */
6698 0 : if (enable) {
6699 0 : cik_enable_mgcg(rdev, true);
6700 0 : cik_enable_cgcg(rdev, true);
6701 0 : } else {
6702 0 : cik_enable_cgcg(rdev, false);
6703 0 : cik_enable_mgcg(rdev, false);
6704 : }
6705 0 : cik_enable_gui_idle_interrupt(rdev, true);
6706 0 : }
6707 :
6708 0 : if (block & RADEON_CG_BLOCK_MC) {
6709 0 : if (!(rdev->flags & RADEON_IS_IGP)) {
6710 0 : cik_enable_mc_mgcg(rdev, enable);
6711 0 : cik_enable_mc_ls(rdev, enable);
6712 0 : }
6713 : }
6714 :
6715 0 : if (block & RADEON_CG_BLOCK_SDMA) {
6716 0 : cik_enable_sdma_mgcg(rdev, enable);
6717 0 : cik_enable_sdma_mgls(rdev, enable);
6718 0 : }
6719 :
6720 0 : if (block & RADEON_CG_BLOCK_BIF) {
6721 0 : cik_enable_bif_mgls(rdev, enable);
6722 0 : }
6723 :
6724 0 : if (block & RADEON_CG_BLOCK_UVD) {
6725 0 : if (rdev->has_uvd)
6726 0 : cik_enable_uvd_mgcg(rdev, enable);
6727 : }
6728 :
6729 0 : if (block & RADEON_CG_BLOCK_HDP) {
6730 0 : cik_enable_hdp_mgcg(rdev, enable);
6731 0 : cik_enable_hdp_ls(rdev, enable);
6732 0 : }
6733 :
6734 0 : if (block & RADEON_CG_BLOCK_VCE) {
6735 0 : vce_v2_0_enable_mgcg(rdev, enable);
6736 0 : }
6737 0 : }
6738 :
6739 0 : static void cik_init_cg(struct radeon_device *rdev)
6740 : {
6741 :
6742 0 : cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, true);
6743 :
6744 0 : if (rdev->has_uvd)
6745 0 : si_init_uvd_internal_cg(rdev);
6746 :
6747 0 : cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
6748 : RADEON_CG_BLOCK_SDMA |
6749 : RADEON_CG_BLOCK_BIF |
6750 : RADEON_CG_BLOCK_UVD |
6751 : RADEON_CG_BLOCK_HDP), true);
6752 0 : }
6753 :
6754 0 : static void cik_fini_cg(struct radeon_device *rdev)
6755 : {
6756 0 : cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
6757 : RADEON_CG_BLOCK_SDMA |
6758 : RADEON_CG_BLOCK_BIF |
6759 : RADEON_CG_BLOCK_UVD |
6760 : RADEON_CG_BLOCK_HDP), false);
6761 :
6762 0 : cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, false);
6763 0 : }
6764 :
6765 0 : static void cik_enable_sck_slowdown_on_pu(struct radeon_device *rdev,
6766 : bool enable)
6767 : {
6768 : u32 data, orig;
6769 :
6770 0 : orig = data = RREG32(RLC_PG_CNTL);
6771 0 : if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6772 0 : data |= SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6773 : else
6774 0 : data &= ~SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6775 0 : if (orig != data)
6776 0 : WREG32(RLC_PG_CNTL, data);
6777 0 : }
6778 :
6779 0 : static void cik_enable_sck_slowdown_on_pd(struct radeon_device *rdev,
6780 : bool enable)
6781 : {
6782 : u32 data, orig;
6783 :
6784 0 : orig = data = RREG32(RLC_PG_CNTL);
6785 0 : if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6786 0 : data |= SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6787 : else
6788 0 : data &= ~SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6789 0 : if (orig != data)
6790 0 : WREG32(RLC_PG_CNTL, data);
6791 0 : }
6792 :
6793 0 : static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
6794 : {
6795 : u32 data, orig;
6796 :
6797 0 : orig = data = RREG32(RLC_PG_CNTL);
6798 0 : if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_CP))
6799 0 : data &= ~DISABLE_CP_PG;
6800 : else
6801 0 : data |= DISABLE_CP_PG;
6802 0 : if (orig != data)
6803 0 : WREG32(RLC_PG_CNTL, data);
6804 0 : }
6805 :
6806 0 : static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
6807 : {
6808 : u32 data, orig;
6809 :
6810 0 : orig = data = RREG32(RLC_PG_CNTL);
6811 0 : if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GDS))
6812 0 : data &= ~DISABLE_GDS_PG;
6813 : else
6814 0 : data |= DISABLE_GDS_PG;
6815 0 : if (orig != data)
6816 0 : WREG32(RLC_PG_CNTL, data);
6817 0 : }
6818 :
6819 : #define CP_ME_TABLE_SIZE 96
6820 : #define CP_ME_TABLE_OFFSET 2048
6821 : #define CP_MEC_TABLE_OFFSET 4096
6822 :
6823 0 : void cik_init_cp_pg_table(struct radeon_device *rdev)
6824 : {
6825 : volatile u32 *dst_ptr;
6826 : int me, i, max_me = 4;
6827 : u32 bo_offset = 0;
6828 : u32 table_offset, table_size;
6829 :
6830 0 : if (rdev->family == CHIP_KAVERI)
6831 0 : max_me = 5;
6832 :
6833 0 : if (rdev->rlc.cp_table_ptr == NULL)
6834 0 : return;
6835 :
6836 : /* write the cp table buffer */
6837 : dst_ptr = rdev->rlc.cp_table_ptr;
6838 0 : for (me = 0; me < max_me; me++) {
6839 0 : if (rdev->new_fw) {
6840 : const __le32 *fw_data;
6841 : const struct gfx_firmware_header_v1_0 *hdr;
6842 :
6843 0 : if (me == 0) {
6844 0 : hdr = (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
6845 0 : fw_data = (const __le32 *)
6846 0 : (rdev->ce_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6847 0 : table_offset = le32_to_cpu(hdr->jt_offset);
6848 0 : table_size = le32_to_cpu(hdr->jt_size);
6849 0 : } else if (me == 1) {
6850 0 : hdr = (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
6851 0 : fw_data = (const __le32 *)
6852 0 : (rdev->pfp_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6853 0 : table_offset = le32_to_cpu(hdr->jt_offset);
6854 0 : table_size = le32_to_cpu(hdr->jt_size);
6855 0 : } else if (me == 2) {
6856 0 : hdr = (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
6857 0 : fw_data = (const __le32 *)
6858 0 : (rdev->me_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6859 0 : table_offset = le32_to_cpu(hdr->jt_offset);
6860 0 : table_size = le32_to_cpu(hdr->jt_size);
6861 0 : } else if (me == 3) {
6862 0 : hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec_fw->data;
6863 0 : fw_data = (const __le32 *)
6864 0 : (rdev->mec_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6865 0 : table_offset = le32_to_cpu(hdr->jt_offset);
6866 0 : table_size = le32_to_cpu(hdr->jt_size);
6867 0 : } else {
6868 0 : hdr = (const struct gfx_firmware_header_v1_0 *)rdev->mec2_fw->data;
6869 0 : fw_data = (const __le32 *)
6870 0 : (rdev->mec2_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
6871 0 : table_offset = le32_to_cpu(hdr->jt_offset);
6872 0 : table_size = le32_to_cpu(hdr->jt_size);
6873 : }
6874 :
6875 0 : for (i = 0; i < table_size; i ++) {
6876 0 : dst_ptr[bo_offset + i] =
6877 0 : cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
6878 : }
6879 0 : bo_offset += table_size;
6880 0 : } else {
6881 : const __be32 *fw_data;
6882 : table_size = CP_ME_TABLE_SIZE;
6883 :
6884 0 : if (me == 0) {
6885 0 : fw_data = (const __be32 *)rdev->ce_fw->data;
6886 : table_offset = CP_ME_TABLE_OFFSET;
6887 0 : } else if (me == 1) {
6888 0 : fw_data = (const __be32 *)rdev->pfp_fw->data;
6889 : table_offset = CP_ME_TABLE_OFFSET;
6890 0 : } else if (me == 2) {
6891 0 : fw_data = (const __be32 *)rdev->me_fw->data;
6892 : table_offset = CP_ME_TABLE_OFFSET;
6893 0 : } else {
6894 0 : fw_data = (const __be32 *)rdev->mec_fw->data;
6895 : table_offset = CP_MEC_TABLE_OFFSET;
6896 : }
6897 :
6898 0 : for (i = 0; i < table_size; i ++) {
6899 0 : dst_ptr[bo_offset + i] =
6900 0 : cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));
6901 : }
6902 0 : bo_offset += table_size;
6903 : }
6904 : }
6905 0 : }
6906 :
6907 0 : static void cik_enable_gfx_cgpg(struct radeon_device *rdev,
6908 : bool enable)
6909 : {
6910 : u32 data, orig;
6911 :
6912 0 : if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
6913 0 : orig = data = RREG32(RLC_PG_CNTL);
6914 0 : data |= GFX_PG_ENABLE;
6915 0 : if (orig != data)
6916 0 : WREG32(RLC_PG_CNTL, data);
6917 :
6918 0 : orig = data = RREG32(RLC_AUTO_PG_CTRL);
6919 0 : data |= AUTO_PG_EN;
6920 0 : if (orig != data)
6921 0 : WREG32(RLC_AUTO_PG_CTRL, data);
6922 : } else {
6923 0 : orig = data = RREG32(RLC_PG_CNTL);
6924 0 : data &= ~GFX_PG_ENABLE;
6925 0 : if (orig != data)
6926 0 : WREG32(RLC_PG_CNTL, data);
6927 :
6928 0 : orig = data = RREG32(RLC_AUTO_PG_CTRL);
6929 0 : data &= ~AUTO_PG_EN;
6930 0 : if (orig != data)
6931 0 : WREG32(RLC_AUTO_PG_CTRL, data);
6932 :
6933 0 : data = RREG32(DB_RENDER_CONTROL);
6934 : }
6935 0 : }
6936 :
6937 0 : static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
6938 : {
6939 : u32 mask = 0, tmp, tmp1;
6940 : int i;
6941 :
6942 0 : mutex_lock(&rdev->grbm_idx_mutex);
6943 0 : cik_select_se_sh(rdev, se, sh);
6944 0 : tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6945 0 : tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
6946 0 : cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6947 0 : mutex_unlock(&rdev->grbm_idx_mutex);
6948 :
6949 0 : tmp &= 0xffff0000;
6950 :
6951 0 : tmp |= tmp1;
6952 0 : tmp >>= 16;
6953 :
6954 0 : for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
6955 0 : mask <<= 1;
6956 0 : mask |= 1;
6957 : }
6958 :
6959 0 : return (~tmp) & mask;
6960 : }
6961 :
6962 0 : static void cik_init_ao_cu_mask(struct radeon_device *rdev)
6963 : {
6964 : u32 i, j, k, active_cu_number = 0;
6965 : u32 mask, counter, cu_bitmap;
6966 : u32 tmp = 0;
6967 :
6968 0 : for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
6969 0 : for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
6970 : mask = 1;
6971 : cu_bitmap = 0;
6972 : counter = 0;
6973 0 : for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
6974 0 : if (cik_get_cu_active_bitmap(rdev, i, j) & mask) {
6975 0 : if (counter < 2)
6976 0 : cu_bitmap |= mask;
6977 0 : counter ++;
6978 0 : }
6979 0 : mask <<= 1;
6980 : }
6981 :
6982 0 : active_cu_number += counter;
6983 0 : tmp |= (cu_bitmap << (i * 16 + j * 8));
6984 : }
6985 : }
6986 :
6987 0 : WREG32(RLC_PG_AO_CU_MASK, tmp);
6988 :
6989 0 : tmp = RREG32(RLC_MAX_PG_CU);
6990 0 : tmp &= ~MAX_PU_CU_MASK;
6991 0 : tmp |= MAX_PU_CU(active_cu_number);
6992 0 : WREG32(RLC_MAX_PG_CU, tmp);
6993 0 : }
6994 :
6995 0 : static void cik_enable_gfx_static_mgpg(struct radeon_device *rdev,
6996 : bool enable)
6997 : {
6998 : u32 data, orig;
6999 :
7000 0 : orig = data = RREG32(RLC_PG_CNTL);
7001 0 : if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_SMG))
7002 0 : data |= STATIC_PER_CU_PG_ENABLE;
7003 : else
7004 0 : data &= ~STATIC_PER_CU_PG_ENABLE;
7005 0 : if (orig != data)
7006 0 : WREG32(RLC_PG_CNTL, data);
7007 0 : }
7008 :
7009 0 : static void cik_enable_gfx_dynamic_mgpg(struct radeon_device *rdev,
7010 : bool enable)
7011 : {
7012 : u32 data, orig;
7013 :
7014 0 : orig = data = RREG32(RLC_PG_CNTL);
7015 0 : if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_DMG))
7016 0 : data |= DYN_PER_CU_PG_ENABLE;
7017 : else
7018 0 : data &= ~DYN_PER_CU_PG_ENABLE;
7019 0 : if (orig != data)
7020 0 : WREG32(RLC_PG_CNTL, data);
7021 0 : }
7022 :
7023 : #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
7024 : #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
7025 :
7026 0 : static void cik_init_gfx_cgpg(struct radeon_device *rdev)
7027 : {
7028 : u32 data, orig;
7029 : u32 i;
7030 :
7031 0 : if (rdev->rlc.cs_data) {
7032 : WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
7033 0 : WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
7034 0 : WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
7035 0 : WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
7036 0 : } else {
7037 : WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
7038 0 : for (i = 0; i < 3; i++)
7039 0 : WREG32(RLC_GPM_SCRATCH_DATA, 0);
7040 : }
7041 0 : if (rdev->rlc.reg_list) {
7042 0 : WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
7043 0 : for (i = 0; i < rdev->rlc.reg_list_size; i++)
7044 0 : WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);
7045 : }
7046 :
7047 0 : orig = data = RREG32(RLC_PG_CNTL);
7048 0 : data |= GFX_PG_SRC;
7049 0 : if (orig != data)
7050 0 : WREG32(RLC_PG_CNTL, data);
7051 :
7052 0 : WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
7053 0 : WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);
7054 :
7055 0 : data = RREG32(CP_RB_WPTR_POLL_CNTL);
7056 0 : data &= ~IDLE_POLL_COUNT_MASK;
7057 0 : data |= IDLE_POLL_COUNT(0x60);
7058 0 : WREG32(CP_RB_WPTR_POLL_CNTL, data);
7059 :
7060 : data = 0x10101010;
7061 0 : WREG32(RLC_PG_DELAY, data);
7062 :
7063 0 : data = RREG32(RLC_PG_DELAY_2);
7064 0 : data &= ~0xff;
7065 0 : data |= 0x3;
7066 0 : WREG32(RLC_PG_DELAY_2, data);
7067 :
7068 0 : data = RREG32(RLC_AUTO_PG_CTRL);
7069 0 : data &= ~GRBM_REG_SGIT_MASK;
7070 0 : data |= GRBM_REG_SGIT(0x700);
7071 0 : WREG32(RLC_AUTO_PG_CTRL, data);
7072 :
7073 0 : }
7074 :
7075 0 : static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
7076 : {
7077 0 : cik_enable_gfx_cgpg(rdev, enable);
7078 0 : cik_enable_gfx_static_mgpg(rdev, enable);
7079 0 : cik_enable_gfx_dynamic_mgpg(rdev, enable);
7080 0 : }
7081 :
7082 0 : u32 cik_get_csb_size(struct radeon_device *rdev)
7083 : {
7084 : u32 count = 0;
7085 : const struct cs_section_def *sect = NULL;
7086 : const struct cs_extent_def *ext = NULL;
7087 :
7088 0 : if (rdev->rlc.cs_data == NULL)
7089 0 : return 0;
7090 :
7091 : /* begin clear state */
7092 : count += 2;
7093 : /* context control state */
7094 : count += 3;
7095 :
7096 0 : for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
7097 0 : for (ext = sect->section; ext->extent != NULL; ++ext) {
7098 0 : if (sect->id == SECT_CONTEXT)
7099 0 : count += 2 + ext->reg_count;
7100 : else
7101 0 : return 0;
7102 : }
7103 : }
7104 : /* pa_sc_raster_config/pa_sc_raster_config1 */
7105 0 : count += 4;
7106 : /* end clear state */
7107 0 : count += 2;
7108 : /* clear state */
7109 0 : count += 2;
7110 :
7111 0 : return count;
7112 0 : }
7113 :
7114 0 : void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
7115 : {
7116 : u32 count = 0, i;
7117 : const struct cs_section_def *sect = NULL;
7118 : const struct cs_extent_def *ext = NULL;
7119 :
7120 0 : if (rdev->rlc.cs_data == NULL)
7121 0 : return;
7122 0 : if (buffer == NULL)
7123 0 : return;
7124 :
7125 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
7126 0 : buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
7127 :
7128 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7129 0 : buffer[count++] = cpu_to_le32(0x80000000);
7130 0 : buffer[count++] = cpu_to_le32(0x80000000);
7131 :
7132 0 : for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
7133 0 : for (ext = sect->section; ext->extent != NULL; ++ext) {
7134 0 : if (sect->id == SECT_CONTEXT) {
7135 0 : buffer[count++] =
7136 0 : cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
7137 0 : buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
7138 0 : for (i = 0; i < ext->reg_count; i++)
7139 0 : buffer[count++] = cpu_to_le32(ext->extent[i]);
7140 : } else {
7141 0 : return;
7142 : }
7143 : }
7144 : }
7145 :
7146 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
7147 0 : buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
7148 0 : switch (rdev->family) {
7149 : case CHIP_BONAIRE:
7150 0 : buffer[count++] = cpu_to_le32(0x16000012);
7151 0 : buffer[count++] = cpu_to_le32(0x00000000);
7152 0 : break;
7153 : case CHIP_KAVERI:
7154 0 : buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
7155 0 : buffer[count++] = cpu_to_le32(0x00000000);
7156 0 : break;
7157 : case CHIP_KABINI:
7158 : case CHIP_MULLINS:
7159 0 : buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
7160 0 : buffer[count++] = cpu_to_le32(0x00000000);
7161 0 : break;
7162 : case CHIP_HAWAII:
7163 0 : buffer[count++] = cpu_to_le32(0x3a00161a);
7164 0 : buffer[count++] = cpu_to_le32(0x0000002e);
7165 0 : break;
7166 : default:
7167 0 : buffer[count++] = cpu_to_le32(0x00000000);
7168 0 : buffer[count++] = cpu_to_le32(0x00000000);
7169 0 : break;
7170 : }
7171 :
7172 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
7173 0 : buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
7174 :
7175 0 : buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
7176 0 : buffer[count++] = cpu_to_le32(0);
7177 0 : }
7178 :
7179 0 : static void cik_init_pg(struct radeon_device *rdev)
7180 : {
7181 0 : if (rdev->pg_flags) {
7182 0 : cik_enable_sck_slowdown_on_pu(rdev, true);
7183 0 : cik_enable_sck_slowdown_on_pd(rdev, true);
7184 0 : if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
7185 0 : cik_init_gfx_cgpg(rdev);
7186 0 : cik_enable_cp_pg(rdev, true);
7187 0 : cik_enable_gds_pg(rdev, true);
7188 0 : }
7189 0 : cik_init_ao_cu_mask(rdev);
7190 0 : cik_update_gfx_pg(rdev, true);
7191 0 : }
7192 0 : }
7193 :
7194 0 : static void cik_fini_pg(struct radeon_device *rdev)
7195 : {
7196 0 : if (rdev->pg_flags) {
7197 0 : cik_update_gfx_pg(rdev, false);
7198 0 : if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
7199 0 : cik_enable_cp_pg(rdev, false);
7200 0 : cik_enable_gds_pg(rdev, false);
7201 0 : }
7202 : }
7203 0 : }
7204 :
7205 : /*
7206 : * Interrupts
7207 : * Starting with r6xx, interrupts are handled via a ring buffer.
7208 : * Ring buffers are areas of GPU accessible memory that the GPU
7209 : * writes interrupt vectors into and the host reads vectors out of.
7210 : * There is a rptr (read pointer) that determines where the
7211 : * host is currently reading, and a wptr (write pointer)
7212 : * which determines where the GPU has written. When the
7213 : * pointers are equal, the ring is idle. When the GPU
7214 : * writes vectors to the ring buffer, it increments the
7215 : * wptr. When there is an interrupt, the host then starts
7216 : * fetching commands and processing them until the pointers are
7217 : * equal again at which point it updates the rptr.
7218 : */
7219 :
7220 : /**
7221 : * cik_enable_interrupts - Enable the interrupt ring buffer
7222 : *
7223 : * @rdev: radeon_device pointer
7224 : *
7225 : * Enable the interrupt ring buffer (CIK).
7226 : */
7227 0 : static void cik_enable_interrupts(struct radeon_device *rdev)
7228 : {
7229 0 : u32 ih_cntl = RREG32(IH_CNTL);
7230 0 : u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
7231 :
7232 0 : ih_cntl |= ENABLE_INTR;
7233 0 : ih_rb_cntl |= IH_RB_ENABLE;
7234 0 : WREG32(IH_CNTL, ih_cntl);
7235 0 : WREG32(IH_RB_CNTL, ih_rb_cntl);
7236 0 : rdev->ih.enabled = true;
7237 0 : }
7238 :
7239 : /**
7240 : * cik_disable_interrupts - Disable the interrupt ring buffer
7241 : *
7242 : * @rdev: radeon_device pointer
7243 : *
7244 : * Disable the interrupt ring buffer (CIK).
7245 : */
7246 0 : static void cik_disable_interrupts(struct radeon_device *rdev)
7247 : {
7248 0 : u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
7249 0 : u32 ih_cntl = RREG32(IH_CNTL);
7250 :
7251 0 : ih_rb_cntl &= ~IH_RB_ENABLE;
7252 0 : ih_cntl &= ~ENABLE_INTR;
7253 0 : WREG32(IH_RB_CNTL, ih_rb_cntl);
7254 0 : WREG32(IH_CNTL, ih_cntl);
7255 : /* set rptr, wptr to 0 */
7256 0 : WREG32(IH_RB_RPTR, 0);
7257 0 : WREG32(IH_RB_WPTR, 0);
7258 0 : rdev->ih.enabled = false;
7259 0 : rdev->ih.rptr = 0;
7260 0 : }
7261 :
7262 : /**
7263 : * cik_disable_interrupt_state - Disable all interrupt sources
7264 : *
7265 : * @rdev: radeon_device pointer
7266 : *
7267 : * Clear all interrupt enable bits used by the driver (CIK).
7268 : */
7269 0 : static void cik_disable_interrupt_state(struct radeon_device *rdev)
7270 : {
7271 : u32 tmp;
7272 :
7273 : /* gfx ring */
7274 0 : tmp = RREG32(CP_INT_CNTL_RING0) &
7275 : (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
7276 0 : WREG32(CP_INT_CNTL_RING0, tmp);
7277 : /* sdma */
7278 0 : tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
7279 0 : WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
7280 0 : tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
7281 0 : WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
7282 : /* compute queues */
7283 0 : WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
7284 0 : WREG32(CP_ME1_PIPE1_INT_CNTL, 0);
7285 0 : WREG32(CP_ME1_PIPE2_INT_CNTL, 0);
7286 0 : WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
7287 0 : WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
7288 0 : WREG32(CP_ME2_PIPE1_INT_CNTL, 0);
7289 0 : WREG32(CP_ME2_PIPE2_INT_CNTL, 0);
7290 0 : WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
7291 : /* grbm */
7292 0 : WREG32(GRBM_INT_CNTL, 0);
7293 : /* SRBM */
7294 0 : WREG32(SRBM_INT_CNTL, 0);
7295 : /* vline/vblank, etc. */
7296 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
7297 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
7298 0 : if (rdev->num_crtc >= 4) {
7299 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
7300 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
7301 0 : }
7302 0 : if (rdev->num_crtc >= 6) {
7303 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
7304 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
7305 0 : }
7306 : /* pflip */
7307 0 : if (rdev->num_crtc >= 2) {
7308 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
7309 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
7310 0 : }
7311 0 : if (rdev->num_crtc >= 4) {
7312 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
7313 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
7314 0 : }
7315 0 : if (rdev->num_crtc >= 6) {
7316 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
7317 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
7318 0 : }
7319 :
7320 : /* dac hotplug */
7321 0 : WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
7322 :
7323 : /* digital hotplug */
7324 0 : tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
7325 0 : WREG32(DC_HPD1_INT_CONTROL, tmp);
7326 0 : tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
7327 0 : WREG32(DC_HPD2_INT_CONTROL, tmp);
7328 0 : tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
7329 0 : WREG32(DC_HPD3_INT_CONTROL, tmp);
7330 0 : tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
7331 0 : WREG32(DC_HPD4_INT_CONTROL, tmp);
7332 0 : tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
7333 0 : WREG32(DC_HPD5_INT_CONTROL, tmp);
7334 0 : tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
7335 0 : WREG32(DC_HPD6_INT_CONTROL, tmp);
7336 :
7337 0 : }
7338 :
7339 : /**
7340 : * cik_irq_init - init and enable the interrupt ring
7341 : *
7342 : * @rdev: radeon_device pointer
7343 : *
7344 : * Allocate a ring buffer for the interrupt controller,
7345 : * enable the RLC, disable interrupts, enable the IH
7346 : * ring buffer and enable it (CIK).
7347 : * Called at device load and reume.
7348 : * Returns 0 for success, errors for failure.
7349 : */
7350 0 : static int cik_irq_init(struct radeon_device *rdev)
7351 : {
7352 : int ret = 0;
7353 : int rb_bufsz;
7354 : u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
7355 :
7356 : /* allocate ring */
7357 0 : ret = r600_ih_ring_alloc(rdev);
7358 0 : if (ret)
7359 0 : return ret;
7360 :
7361 : /* disable irqs */
7362 0 : cik_disable_interrupts(rdev);
7363 :
7364 : /* init rlc */
7365 0 : ret = cik_rlc_resume(rdev);
7366 0 : if (ret) {
7367 0 : r600_ih_ring_fini(rdev);
7368 0 : return ret;
7369 : }
7370 :
7371 : /* setup interrupt control */
7372 : /* XXX this should actually be a bus address, not an MC address. same on older asics */
7373 0 : WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
7374 0 : interrupt_cntl = RREG32(INTERRUPT_CNTL);
7375 : /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
7376 : * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
7377 : */
7378 0 : interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
7379 : /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
7380 0 : interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
7381 0 : WREG32(INTERRUPT_CNTL, interrupt_cntl);
7382 :
7383 0 : WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
7384 0 : rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
7385 :
7386 : ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
7387 0 : IH_WPTR_OVERFLOW_CLEAR |
7388 0 : (rb_bufsz << 1));
7389 :
7390 0 : if (rdev->wb.enabled)
7391 0 : ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
7392 :
7393 : /* set the writeback address whether it's enabled or not */
7394 0 : WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
7395 0 : WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
7396 :
7397 0 : WREG32(IH_RB_CNTL, ih_rb_cntl);
7398 :
7399 : /* set rptr, wptr to 0 */
7400 0 : WREG32(IH_RB_RPTR, 0);
7401 0 : WREG32(IH_RB_WPTR, 0);
7402 :
7403 : /* Default settings for IH_CNTL (disabled at first) */
7404 : ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
7405 : /* RPTR_REARM only works if msi's are enabled */
7406 0 : if (rdev->msi_enabled)
7407 0 : ih_cntl |= RPTR_REARM;
7408 0 : WREG32(IH_CNTL, ih_cntl);
7409 :
7410 : /* force the active interrupt state to all disabled */
7411 0 : cik_disable_interrupt_state(rdev);
7412 :
7413 : pci_set_master(rdev->pdev);
7414 :
7415 : /* enable irqs */
7416 0 : cik_enable_interrupts(rdev);
7417 :
7418 0 : return ret;
7419 0 : }
7420 :
7421 : /**
7422 : * cik_irq_set - enable/disable interrupt sources
7423 : *
7424 : * @rdev: radeon_device pointer
7425 : *
7426 : * Enable interrupt sources on the GPU (vblanks, hpd,
7427 : * etc.) (CIK).
7428 : * Returns 0 for success, errors for failure.
7429 : */
7430 0 : int cik_irq_set(struct radeon_device *rdev)
7431 : {
7432 : u32 cp_int_cntl;
7433 : u32 cp_m1p0;
7434 : u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
7435 : u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
7436 : u32 grbm_int_cntl = 0;
7437 : u32 dma_cntl, dma_cntl1;
7438 :
7439 0 : if (!rdev->irq.installed) {
7440 0 : WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
7441 0 : return -EINVAL;
7442 : }
7443 : /* don't enable anything if the ih is disabled */
7444 0 : if (!rdev->ih.enabled) {
7445 0 : cik_disable_interrupts(rdev);
7446 : /* force the active interrupt state to all disabled */
7447 0 : cik_disable_interrupt_state(rdev);
7448 0 : return 0;
7449 : }
7450 :
7451 0 : cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
7452 : (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
7453 0 : cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
7454 :
7455 0 : hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7456 0 : hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7457 0 : hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7458 0 : hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7459 0 : hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7460 0 : hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7461 :
7462 0 : dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
7463 0 : dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
7464 :
7465 0 : cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7466 :
7467 : /* enable CP interrupts on all rings */
7468 0 : if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7469 : DRM_DEBUG("cik_irq_set: sw int gfx\n");
7470 0 : cp_int_cntl |= TIME_STAMP_INT_ENABLE;
7471 0 : }
7472 0 : if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
7473 0 : struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7474 : DRM_DEBUG("si_irq_set: sw int cp1\n");
7475 0 : if (ring->me == 1) {
7476 0 : switch (ring->pipe) {
7477 : case 0:
7478 0 : cp_m1p0 |= TIME_STAMP_INT_ENABLE;
7479 0 : break;
7480 : default:
7481 : DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
7482 : break;
7483 : }
7484 : } else {
7485 : DRM_DEBUG("si_irq_set: sw int cp1 invalid me %d\n", ring->me);
7486 : }
7487 0 : }
7488 0 : if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
7489 0 : struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7490 : DRM_DEBUG("si_irq_set: sw int cp2\n");
7491 0 : if (ring->me == 1) {
7492 0 : switch (ring->pipe) {
7493 : case 0:
7494 0 : cp_m1p0 |= TIME_STAMP_INT_ENABLE;
7495 0 : break;
7496 : default:
7497 : DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
7498 : break;
7499 : }
7500 : } else {
7501 : DRM_DEBUG("si_irq_set: sw int cp2 invalid me %d\n", ring->me);
7502 : }
7503 0 : }
7504 :
7505 0 : if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
7506 : DRM_DEBUG("cik_irq_set: sw int dma\n");
7507 0 : dma_cntl |= TRAP_ENABLE;
7508 0 : }
7509 :
7510 0 : if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
7511 : DRM_DEBUG("cik_irq_set: sw int dma1\n");
7512 0 : dma_cntl1 |= TRAP_ENABLE;
7513 0 : }
7514 :
7515 0 : if (rdev->irq.crtc_vblank_int[0] ||
7516 0 : atomic_read(&rdev->irq.pflip[0])) {
7517 : DRM_DEBUG("cik_irq_set: vblank 0\n");
7518 : crtc1 |= VBLANK_INTERRUPT_MASK;
7519 0 : }
7520 0 : if (rdev->irq.crtc_vblank_int[1] ||
7521 0 : atomic_read(&rdev->irq.pflip[1])) {
7522 : DRM_DEBUG("cik_irq_set: vblank 1\n");
7523 : crtc2 |= VBLANK_INTERRUPT_MASK;
7524 0 : }
7525 0 : if (rdev->irq.crtc_vblank_int[2] ||
7526 0 : atomic_read(&rdev->irq.pflip[2])) {
7527 : DRM_DEBUG("cik_irq_set: vblank 2\n");
7528 : crtc3 |= VBLANK_INTERRUPT_MASK;
7529 0 : }
7530 0 : if (rdev->irq.crtc_vblank_int[3] ||
7531 0 : atomic_read(&rdev->irq.pflip[3])) {
7532 : DRM_DEBUG("cik_irq_set: vblank 3\n");
7533 : crtc4 |= VBLANK_INTERRUPT_MASK;
7534 0 : }
7535 0 : if (rdev->irq.crtc_vblank_int[4] ||
7536 0 : atomic_read(&rdev->irq.pflip[4])) {
7537 : DRM_DEBUG("cik_irq_set: vblank 4\n");
7538 : crtc5 |= VBLANK_INTERRUPT_MASK;
7539 0 : }
7540 0 : if (rdev->irq.crtc_vblank_int[5] ||
7541 0 : atomic_read(&rdev->irq.pflip[5])) {
7542 : DRM_DEBUG("cik_irq_set: vblank 5\n");
7543 : crtc6 |= VBLANK_INTERRUPT_MASK;
7544 0 : }
7545 0 : if (rdev->irq.hpd[0]) {
7546 : DRM_DEBUG("cik_irq_set: hpd 1\n");
7547 0 : hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7548 0 : }
7549 0 : if (rdev->irq.hpd[1]) {
7550 : DRM_DEBUG("cik_irq_set: hpd 2\n");
7551 0 : hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7552 0 : }
7553 0 : if (rdev->irq.hpd[2]) {
7554 : DRM_DEBUG("cik_irq_set: hpd 3\n");
7555 0 : hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7556 0 : }
7557 0 : if (rdev->irq.hpd[3]) {
7558 : DRM_DEBUG("cik_irq_set: hpd 4\n");
7559 0 : hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7560 0 : }
7561 0 : if (rdev->irq.hpd[4]) {
7562 : DRM_DEBUG("cik_irq_set: hpd 5\n");
7563 0 : hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7564 0 : }
7565 0 : if (rdev->irq.hpd[5]) {
7566 : DRM_DEBUG("cik_irq_set: hpd 6\n");
7567 0 : hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
7568 0 : }
7569 :
7570 0 : WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
7571 :
7572 0 : WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
7573 0 : WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
7574 :
7575 0 : WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);
7576 :
7577 0 : WREG32(GRBM_INT_CNTL, grbm_int_cntl);
7578 :
7579 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
7580 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
7581 0 : if (rdev->num_crtc >= 4) {
7582 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
7583 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
7584 0 : }
7585 0 : if (rdev->num_crtc >= 6) {
7586 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
7587 0 : WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
7588 0 : }
7589 :
7590 0 : if (rdev->num_crtc >= 2) {
7591 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
7592 : GRPH_PFLIP_INT_MASK);
7593 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
7594 : GRPH_PFLIP_INT_MASK);
7595 0 : }
7596 0 : if (rdev->num_crtc >= 4) {
7597 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
7598 : GRPH_PFLIP_INT_MASK);
7599 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
7600 : GRPH_PFLIP_INT_MASK);
7601 0 : }
7602 0 : if (rdev->num_crtc >= 6) {
7603 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
7604 : GRPH_PFLIP_INT_MASK);
7605 0 : WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
7606 : GRPH_PFLIP_INT_MASK);
7607 0 : }
7608 :
7609 0 : WREG32(DC_HPD1_INT_CONTROL, hpd1);
7610 0 : WREG32(DC_HPD2_INT_CONTROL, hpd2);
7611 0 : WREG32(DC_HPD3_INT_CONTROL, hpd3);
7612 0 : WREG32(DC_HPD4_INT_CONTROL, hpd4);
7613 0 : WREG32(DC_HPD5_INT_CONTROL, hpd5);
7614 0 : WREG32(DC_HPD6_INT_CONTROL, hpd6);
7615 :
7616 : /* posting read */
7617 0 : RREG32(SRBM_STATUS);
7618 :
7619 0 : return 0;
7620 0 : }
7621 :
7622 : /**
7623 : * cik_irq_ack - ack interrupt sources
7624 : *
7625 : * @rdev: radeon_device pointer
7626 : *
7627 : * Ack interrupt sources on the GPU (vblanks, hpd,
7628 : * etc.) (CIK). Certain interrupts sources are sw
7629 : * generated and do not require an explicit ack.
7630 : */
7631 0 : static inline void cik_irq_ack(struct radeon_device *rdev)
7632 : {
7633 : u32 tmp;
7634 :
7635 0 : rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
7636 0 : rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
7637 0 : rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
7638 0 : rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
7639 0 : rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
7640 0 : rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
7641 0 : rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
7642 :
7643 0 : rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
7644 : EVERGREEN_CRTC0_REGISTER_OFFSET);
7645 0 : rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
7646 : EVERGREEN_CRTC1_REGISTER_OFFSET);
7647 0 : if (rdev->num_crtc >= 4) {
7648 0 : rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
7649 : EVERGREEN_CRTC2_REGISTER_OFFSET);
7650 0 : rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
7651 : EVERGREEN_CRTC3_REGISTER_OFFSET);
7652 0 : }
7653 0 : if (rdev->num_crtc >= 6) {
7654 0 : rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
7655 : EVERGREEN_CRTC4_REGISTER_OFFSET);
7656 0 : rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
7657 : EVERGREEN_CRTC5_REGISTER_OFFSET);
7658 0 : }
7659 :
7660 0 : if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
7661 0 : WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
7662 : GRPH_PFLIP_INT_CLEAR);
7663 0 : if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
7664 0 : WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
7665 : GRPH_PFLIP_INT_CLEAR);
7666 0 : if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
7667 0 : WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
7668 0 : if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
7669 0 : WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
7670 0 : if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
7671 0 : WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
7672 0 : if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)
7673 0 : WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
7674 :
7675 0 : if (rdev->num_crtc >= 4) {
7676 0 : if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
7677 0 : WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
7678 : GRPH_PFLIP_INT_CLEAR);
7679 0 : if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
7680 0 : WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
7681 : GRPH_PFLIP_INT_CLEAR);
7682 0 : if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
7683 0 : WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
7684 0 : if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
7685 0 : WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
7686 0 : if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
7687 0 : WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
7688 0 : if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
7689 0 : WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
7690 : }
7691 :
7692 0 : if (rdev->num_crtc >= 6) {
7693 0 : if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
7694 0 : WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
7695 : GRPH_PFLIP_INT_CLEAR);
7696 0 : if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
7697 0 : WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
7698 : GRPH_PFLIP_INT_CLEAR);
7699 0 : if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
7700 0 : WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
7701 0 : if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
7702 0 : WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
7703 0 : if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
7704 0 : WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
7705 0 : if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
7706 0 : WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
7707 : }
7708 :
7709 0 : if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
7710 0 : tmp = RREG32(DC_HPD1_INT_CONTROL);
7711 0 : tmp |= DC_HPDx_INT_ACK;
7712 0 : WREG32(DC_HPD1_INT_CONTROL, tmp);
7713 0 : }
7714 0 : if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
7715 0 : tmp = RREG32(DC_HPD2_INT_CONTROL);
7716 0 : tmp |= DC_HPDx_INT_ACK;
7717 0 : WREG32(DC_HPD2_INT_CONTROL, tmp);
7718 0 : }
7719 0 : if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
7720 0 : tmp = RREG32(DC_HPD3_INT_CONTROL);
7721 0 : tmp |= DC_HPDx_INT_ACK;
7722 0 : WREG32(DC_HPD3_INT_CONTROL, tmp);
7723 0 : }
7724 0 : if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
7725 0 : tmp = RREG32(DC_HPD4_INT_CONTROL);
7726 0 : tmp |= DC_HPDx_INT_ACK;
7727 0 : WREG32(DC_HPD4_INT_CONTROL, tmp);
7728 0 : }
7729 0 : if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
7730 0 : tmp = RREG32(DC_HPD5_INT_CONTROL);
7731 0 : tmp |= DC_HPDx_INT_ACK;
7732 0 : WREG32(DC_HPD5_INT_CONTROL, tmp);
7733 0 : }
7734 0 : if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
7735 0 : tmp = RREG32(DC_HPD6_INT_CONTROL);
7736 0 : tmp |= DC_HPDx_INT_ACK;
7737 0 : WREG32(DC_HPD6_INT_CONTROL, tmp);
7738 0 : }
7739 0 : if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {
7740 0 : tmp = RREG32(DC_HPD1_INT_CONTROL);
7741 0 : tmp |= DC_HPDx_RX_INT_ACK;
7742 0 : WREG32(DC_HPD1_INT_CONTROL, tmp);
7743 0 : }
7744 0 : if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) {
7745 0 : tmp = RREG32(DC_HPD2_INT_CONTROL);
7746 0 : tmp |= DC_HPDx_RX_INT_ACK;
7747 0 : WREG32(DC_HPD2_INT_CONTROL, tmp);
7748 0 : }
7749 0 : if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {
7750 0 : tmp = RREG32(DC_HPD3_INT_CONTROL);
7751 0 : tmp |= DC_HPDx_RX_INT_ACK;
7752 0 : WREG32(DC_HPD3_INT_CONTROL, tmp);
7753 0 : }
7754 0 : if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {
7755 0 : tmp = RREG32(DC_HPD4_INT_CONTROL);
7756 0 : tmp |= DC_HPDx_RX_INT_ACK;
7757 0 : WREG32(DC_HPD4_INT_CONTROL, tmp);
7758 0 : }
7759 0 : if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {
7760 0 : tmp = RREG32(DC_HPD5_INT_CONTROL);
7761 0 : tmp |= DC_HPDx_RX_INT_ACK;
7762 0 : WREG32(DC_HPD5_INT_CONTROL, tmp);
7763 0 : }
7764 0 : if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
7765 0 : tmp = RREG32(DC_HPD6_INT_CONTROL);
7766 0 : tmp |= DC_HPDx_RX_INT_ACK;
7767 0 : WREG32(DC_HPD6_INT_CONTROL, tmp);
7768 0 : }
7769 0 : }
7770 :
7771 : /**
7772 : * cik_irq_disable - disable interrupts
7773 : *
7774 : * @rdev: radeon_device pointer
7775 : *
7776 : * Disable interrupts on the hw (CIK).
7777 : */
7778 0 : static void cik_irq_disable(struct radeon_device *rdev)
7779 : {
7780 0 : cik_disable_interrupts(rdev);
7781 : /* Wait and acknowledge irq */
7782 0 : mdelay(1);
7783 0 : cik_irq_ack(rdev);
7784 0 : cik_disable_interrupt_state(rdev);
7785 0 : }
7786 :
7787 : /**
7788 : * cik_irq_disable - disable interrupts for suspend
7789 : *
7790 : * @rdev: radeon_device pointer
7791 : *
7792 : * Disable interrupts and stop the RLC (CIK).
7793 : * Used for suspend.
7794 : */
7795 0 : static void cik_irq_suspend(struct radeon_device *rdev)
7796 : {
7797 0 : cik_irq_disable(rdev);
7798 0 : cik_rlc_stop(rdev);
7799 0 : }
7800 :
7801 : /**
7802 : * cik_irq_fini - tear down interrupt support
7803 : *
7804 : * @rdev: radeon_device pointer
7805 : *
7806 : * Disable interrupts on the hw and free the IH ring
7807 : * buffer (CIK).
7808 : * Used for driver unload.
7809 : */
7810 0 : static void cik_irq_fini(struct radeon_device *rdev)
7811 : {
7812 0 : cik_irq_suspend(rdev);
7813 0 : r600_ih_ring_fini(rdev);
7814 0 : }
7815 :
7816 : /**
7817 : * cik_get_ih_wptr - get the IH ring buffer wptr
7818 : *
7819 : * @rdev: radeon_device pointer
7820 : *
7821 : * Get the IH ring buffer wptr from either the register
7822 : * or the writeback memory buffer (CIK). Also check for
7823 : * ring buffer overflow and deal with it.
7824 : * Used by cik_irq_process().
7825 : * Returns the value of the wptr.
7826 : */
7827 0 : static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)
7828 : {
7829 : u32 wptr, tmp;
7830 :
7831 0 : if (rdev->wb.enabled)
7832 0 : wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
7833 : else
7834 0 : wptr = RREG32(IH_RB_WPTR);
7835 :
7836 0 : if (wptr & RB_OVERFLOW) {
7837 0 : wptr &= ~RB_OVERFLOW;
7838 : /* When a ring buffer overflow happen start parsing interrupt
7839 : * from the last not overwritten vector (wptr + 16). Hopefully
7840 : * this should allow us to catchup.
7841 : */
7842 0 : dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
7843 : wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
7844 0 : rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
7845 0 : tmp = RREG32(IH_RB_CNTL);
7846 0 : tmp |= IH_WPTR_OVERFLOW_CLEAR;
7847 0 : WREG32(IH_RB_CNTL, tmp);
7848 0 : }
7849 0 : return (wptr & rdev->ih.ptr_mask);
7850 : }
7851 :
7852 : /* CIK IV Ring
7853 : * Each IV ring entry is 128 bits:
7854 : * [7:0] - interrupt source id
7855 : * [31:8] - reserved
7856 : * [59:32] - interrupt source data
7857 : * [63:60] - reserved
7858 : * [71:64] - RINGID
7859 : * CP:
7860 : * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
7861 : * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
7862 : * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
7863 : * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
7864 : * PIPE_ID - ME0 0=3D
7865 : * - ME1&2 compute dispatcher (4 pipes each)
7866 : * SDMA:
7867 : * INSTANCE_ID [1:0], QUEUE_ID[1:0]
7868 : * INSTANCE_ID - 0 = sdma0, 1 = sdma1
7869 : * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
7870 : * [79:72] - VMID
7871 : * [95:80] - PASID
7872 : * [127:96] - reserved
7873 : */
7874 : /**
7875 : * cik_irq_process - interrupt handler
7876 : *
7877 : * @rdev: radeon_device pointer
7878 : *
7879 : * Interrupt hander (CIK). Walk the IH ring,
7880 : * ack interrupts and schedule work to handle
7881 : * interrupt events.
7882 : * Returns irq process return code.
7883 : */
7884 0 : int cik_irq_process(struct radeon_device *rdev)
7885 : {
7886 0 : struct radeon_ring *cp1_ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7887 0 : struct radeon_ring *cp2_ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7888 : u32 wptr;
7889 : u32 rptr;
7890 : u32 src_id, src_data, ring_id;
7891 : u8 me_id, pipe_id, queue_id;
7892 : u32 ring_index;
7893 : bool queue_hotplug = false;
7894 : bool queue_dp = false;
7895 : bool queue_reset = false;
7896 : u32 addr, status, mc_client;
7897 : bool queue_thermal = false;
7898 :
7899 0 : if (!rdev->ih.enabled || rdev->shutdown)
7900 0 : return IRQ_NONE;
7901 :
7902 0 : wptr = cik_get_ih_wptr(rdev);
7903 :
7904 0 : if (wptr == rdev->ih.rptr)
7905 0 : return IRQ_NONE;
7906 : restart_ih:
7907 : /* is somebody else already processing irqs? */
7908 0 : if (atomic_xchg(&rdev->ih.lock, 1))
7909 0 : return IRQ_NONE;
7910 :
7911 0 : rptr = rdev->ih.rptr;
7912 : DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
7913 :
7914 : /* Order reading of wptr vs. reading of IH ring data */
7915 0 : rmb();
7916 :
7917 : /* display interrupts */
7918 0 : cik_irq_ack(rdev);
7919 :
7920 0 : while (rptr != wptr) {
7921 : /* wptr/rptr are in bytes! */
7922 0 : ring_index = rptr / 4;
7923 :
7924 : #ifdef notyet
7925 : radeon_kfd_interrupt(rdev,
7926 : (const void *) &rdev->ih.ring[ring_index]);
7927 : #endif
7928 :
7929 0 : src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
7930 0 : src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
7931 0 : ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
7932 :
7933 0 : switch (src_id) {
7934 : case 1: /* D1 vblank/vline */
7935 0 : switch (src_data) {
7936 : case 0: /* D1 vblank */
7937 0 : if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))
7938 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7939 :
7940 0 : if (rdev->irq.crtc_vblank_int[0]) {
7941 0 : drm_handle_vblank(rdev->ddev, 0);
7942 0 : rdev->pm.vblank_sync = true;
7943 0 : wake_up(&rdev->irq.vblank_queue);
7944 0 : }
7945 0 : if (atomic_read(&rdev->irq.pflip[0]))
7946 0 : radeon_crtc_handle_vblank(rdev, 0);
7947 0 : rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
7948 : DRM_DEBUG("IH: D1 vblank\n");
7949 :
7950 0 : break;
7951 : case 1: /* D1 vline */
7952 0 : if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))
7953 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7954 :
7955 0 : rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
7956 : DRM_DEBUG("IH: D1 vline\n");
7957 :
7958 0 : break;
7959 : default:
7960 : DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7961 : break;
7962 : }
7963 : break;
7964 : case 2: /* D2 vblank/vline */
7965 0 : switch (src_data) {
7966 : case 0: /* D2 vblank */
7967 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
7968 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7969 :
7970 0 : if (rdev->irq.crtc_vblank_int[1]) {
7971 0 : drm_handle_vblank(rdev->ddev, 1);
7972 0 : rdev->pm.vblank_sync = true;
7973 0 : wake_up(&rdev->irq.vblank_queue);
7974 0 : }
7975 0 : if (atomic_read(&rdev->irq.pflip[1]))
7976 0 : radeon_crtc_handle_vblank(rdev, 1);
7977 0 : rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
7978 : DRM_DEBUG("IH: D2 vblank\n");
7979 :
7980 0 : break;
7981 : case 1: /* D2 vline */
7982 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT))
7983 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7984 :
7985 0 : rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
7986 : DRM_DEBUG("IH: D2 vline\n");
7987 :
7988 0 : break;
7989 : default:
7990 : DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7991 : break;
7992 : }
7993 : break;
7994 : case 3: /* D3 vblank/vline */
7995 0 : switch (src_data) {
7996 : case 0: /* D3 vblank */
7997 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
7998 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
7999 :
8000 0 : if (rdev->irq.crtc_vblank_int[2]) {
8001 0 : drm_handle_vblank(rdev->ddev, 2);
8002 0 : rdev->pm.vblank_sync = true;
8003 0 : wake_up(&rdev->irq.vblank_queue);
8004 0 : }
8005 0 : if (atomic_read(&rdev->irq.pflip[2]))
8006 0 : radeon_crtc_handle_vblank(rdev, 2);
8007 0 : rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
8008 : DRM_DEBUG("IH: D3 vblank\n");
8009 :
8010 0 : break;
8011 : case 1: /* D3 vline */
8012 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
8013 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8014 :
8015 0 : rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
8016 : DRM_DEBUG("IH: D3 vline\n");
8017 :
8018 0 : break;
8019 : default:
8020 : DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
8021 : break;
8022 : }
8023 : break;
8024 : case 4: /* D4 vblank/vline */
8025 0 : switch (src_data) {
8026 : case 0: /* D4 vblank */
8027 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
8028 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8029 :
8030 0 : if (rdev->irq.crtc_vblank_int[3]) {
8031 0 : drm_handle_vblank(rdev->ddev, 3);
8032 0 : rdev->pm.vblank_sync = true;
8033 0 : wake_up(&rdev->irq.vblank_queue);
8034 0 : }
8035 0 : if (atomic_read(&rdev->irq.pflip[3]))
8036 0 : radeon_crtc_handle_vblank(rdev, 3);
8037 0 : rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
8038 : DRM_DEBUG("IH: D4 vblank\n");
8039 :
8040 0 : break;
8041 : case 1: /* D4 vline */
8042 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
8043 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8044 :
8045 0 : rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
8046 : DRM_DEBUG("IH: D4 vline\n");
8047 :
8048 0 : break;
8049 : default:
8050 : DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
8051 : break;
8052 : }
8053 : break;
8054 : case 5: /* D5 vblank/vline */
8055 0 : switch (src_data) {
8056 : case 0: /* D5 vblank */
8057 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
8058 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8059 :
8060 0 : if (rdev->irq.crtc_vblank_int[4]) {
8061 0 : drm_handle_vblank(rdev->ddev, 4);
8062 0 : rdev->pm.vblank_sync = true;
8063 0 : wake_up(&rdev->irq.vblank_queue);
8064 0 : }
8065 0 : if (atomic_read(&rdev->irq.pflip[4]))
8066 0 : radeon_crtc_handle_vblank(rdev, 4);
8067 0 : rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
8068 : DRM_DEBUG("IH: D5 vblank\n");
8069 :
8070 0 : break;
8071 : case 1: /* D5 vline */
8072 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
8073 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8074 :
8075 0 : rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
8076 : DRM_DEBUG("IH: D5 vline\n");
8077 :
8078 0 : break;
8079 : default:
8080 : DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
8081 : break;
8082 : }
8083 : break;
8084 : case 6: /* D6 vblank/vline */
8085 0 : switch (src_data) {
8086 : case 0: /* D6 vblank */
8087 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
8088 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8089 :
8090 0 : if (rdev->irq.crtc_vblank_int[5]) {
8091 0 : drm_handle_vblank(rdev->ddev, 5);
8092 0 : rdev->pm.vblank_sync = true;
8093 0 : wake_up(&rdev->irq.vblank_queue);
8094 0 : }
8095 0 : if (atomic_read(&rdev->irq.pflip[5]))
8096 0 : radeon_crtc_handle_vblank(rdev, 5);
8097 0 : rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
8098 : DRM_DEBUG("IH: D6 vblank\n");
8099 :
8100 0 : break;
8101 : case 1: /* D6 vline */
8102 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
8103 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8104 :
8105 0 : rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
8106 : DRM_DEBUG("IH: D6 vline\n");
8107 :
8108 0 : break;
8109 : default:
8110 : DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
8111 : break;
8112 : }
8113 : break;
8114 : case 8: /* D1 page flip */
8115 : case 10: /* D2 page flip */
8116 : case 12: /* D3 page flip */
8117 : case 14: /* D4 page flip */
8118 : case 16: /* D5 page flip */
8119 : case 18: /* D6 page flip */
8120 : DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
8121 0 : if (radeon_use_pflipirq > 0)
8122 0 : radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
8123 : break;
8124 : case 42: /* HPD hotplug */
8125 0 : switch (src_data) {
8126 : case 0:
8127 0 : if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))
8128 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8129 :
8130 0 : rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
8131 : queue_hotplug = true;
8132 : DRM_DEBUG("IH: HPD1\n");
8133 :
8134 0 : break;
8135 : case 1:
8136 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT))
8137 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8138 :
8139 0 : rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;
8140 : queue_hotplug = true;
8141 : DRM_DEBUG("IH: HPD2\n");
8142 :
8143 0 : break;
8144 : case 2:
8145 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT))
8146 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8147 :
8148 0 : rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
8149 : queue_hotplug = true;
8150 : DRM_DEBUG("IH: HPD3\n");
8151 :
8152 0 : break;
8153 : case 3:
8154 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT))
8155 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8156 :
8157 0 : rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
8158 : queue_hotplug = true;
8159 : DRM_DEBUG("IH: HPD4\n");
8160 :
8161 0 : break;
8162 : case 4:
8163 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT))
8164 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8165 :
8166 0 : rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
8167 : queue_hotplug = true;
8168 : DRM_DEBUG("IH: HPD5\n");
8169 :
8170 0 : break;
8171 : case 5:
8172 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT))
8173 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8174 :
8175 0 : rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
8176 : queue_hotplug = true;
8177 : DRM_DEBUG("IH: HPD6\n");
8178 :
8179 0 : break;
8180 : case 6:
8181 0 : if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))
8182 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8183 :
8184 0 : rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;
8185 : queue_dp = true;
8186 : DRM_DEBUG("IH: HPD_RX 1\n");
8187 :
8188 0 : break;
8189 : case 7:
8190 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT))
8191 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8192 :
8193 0 : rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
8194 : queue_dp = true;
8195 : DRM_DEBUG("IH: HPD_RX 2\n");
8196 :
8197 0 : break;
8198 : case 8:
8199 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
8200 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8201 :
8202 0 : rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
8203 : queue_dp = true;
8204 : DRM_DEBUG("IH: HPD_RX 3\n");
8205 :
8206 0 : break;
8207 : case 9:
8208 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
8209 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8210 :
8211 0 : rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
8212 : queue_dp = true;
8213 : DRM_DEBUG("IH: HPD_RX 4\n");
8214 :
8215 0 : break;
8216 : case 10:
8217 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
8218 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8219 :
8220 0 : rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
8221 : queue_dp = true;
8222 : DRM_DEBUG("IH: HPD_RX 5\n");
8223 :
8224 0 : break;
8225 : case 11:
8226 0 : if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
8227 : DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
8228 :
8229 0 : rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
8230 : queue_dp = true;
8231 : DRM_DEBUG("IH: HPD_RX 6\n");
8232 :
8233 0 : break;
8234 : default:
8235 : DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
8236 : break;
8237 : }
8238 : break;
8239 : case 96:
8240 0 : DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
8241 0 : WREG32(SRBM_INT_ACK, 0x1);
8242 0 : break;
8243 : case 124: /* UVD */
8244 : DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
8245 0 : radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
8246 0 : break;
8247 : case 146:
8248 : case 147:
8249 0 : addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
8250 0 : status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
8251 0 : mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
8252 : /* reset addr and status */
8253 0 : WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
8254 0 : if (addr == 0x0 && status == 0x0)
8255 : break;
8256 0 : dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
8257 0 : dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
8258 : addr);
8259 0 : dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
8260 : status);
8261 0 : cik_vm_decode_fault(rdev, status, addr, mc_client);
8262 0 : break;
8263 : case 167: /* VCE */
8264 : DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
8265 0 : switch (src_data) {
8266 : case 0:
8267 0 : radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
8268 0 : break;
8269 : case 1:
8270 0 : radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
8271 0 : break;
8272 : default:
8273 0 : DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
8274 0 : break;
8275 : }
8276 : break;
8277 : case 176: /* GFX RB CP_INT */
8278 : case 177: /* GFX IB CP_INT */
8279 0 : radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
8280 0 : break;
8281 : case 181: /* CP EOP event */
8282 : DRM_DEBUG("IH: CP EOP\n");
8283 : /* XXX check the bitfield order! */
8284 0 : me_id = (ring_id & 0x60) >> 5;
8285 0 : pipe_id = (ring_id & 0x18) >> 3;
8286 0 : queue_id = (ring_id & 0x7) >> 0;
8287 0 : switch (me_id) {
8288 : case 0:
8289 0 : radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
8290 0 : break;
8291 : case 1:
8292 : case 2:
8293 0 : if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))
8294 0 : radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
8295 0 : if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))
8296 0 : radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
8297 : break;
8298 : }
8299 : break;
8300 : case 184: /* CP Privileged reg access */
8301 0 : DRM_ERROR("Illegal register access in command stream\n");
8302 : /* XXX check the bitfield order! */
8303 0 : me_id = (ring_id & 0x60) >> 5;
8304 0 : pipe_id = (ring_id & 0x18) >> 3;
8305 0 : queue_id = (ring_id & 0x7) >> 0;
8306 0 : switch (me_id) {
8307 : case 0:
8308 : /* This results in a full GPU reset, but all we need to do is soft
8309 : * reset the CP for gfx
8310 : */
8311 : queue_reset = true;
8312 0 : break;
8313 : case 1:
8314 : /* XXX compute */
8315 : queue_reset = true;
8316 0 : break;
8317 : case 2:
8318 : /* XXX compute */
8319 : queue_reset = true;
8320 0 : break;
8321 : }
8322 : break;
8323 : case 185: /* CP Privileged inst */
8324 0 : DRM_ERROR("Illegal instruction in command stream\n");
8325 : /* XXX check the bitfield order! */
8326 0 : me_id = (ring_id & 0x60) >> 5;
8327 0 : pipe_id = (ring_id & 0x18) >> 3;
8328 0 : queue_id = (ring_id & 0x7) >> 0;
8329 0 : switch (me_id) {
8330 : case 0:
8331 : /* This results in a full GPU reset, but all we need to do is soft
8332 : * reset the CP for gfx
8333 : */
8334 : queue_reset = true;
8335 0 : break;
8336 : case 1:
8337 : /* XXX compute */
8338 : queue_reset = true;
8339 0 : break;
8340 : case 2:
8341 : /* XXX compute */
8342 : queue_reset = true;
8343 0 : break;
8344 : }
8345 : break;
8346 : case 224: /* SDMA trap event */
8347 : /* XXX check the bitfield order! */
8348 0 : me_id = (ring_id & 0x3) >> 0;
8349 0 : queue_id = (ring_id & 0xc) >> 2;
8350 : DRM_DEBUG("IH: SDMA trap\n");
8351 0 : switch (me_id) {
8352 : case 0:
8353 0 : switch (queue_id) {
8354 : case 0:
8355 0 : radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
8356 0 : break;
8357 : case 1:
8358 : /* XXX compute */
8359 : break;
8360 : case 2:
8361 : /* XXX compute */
8362 : break;
8363 : }
8364 : break;
8365 : case 1:
8366 0 : switch (queue_id) {
8367 : case 0:
8368 0 : radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
8369 0 : break;
8370 : case 1:
8371 : /* XXX compute */
8372 : break;
8373 : case 2:
8374 : /* XXX compute */
8375 : break;
8376 : }
8377 : break;
8378 : }
8379 : break;
8380 : case 230: /* thermal low to high */
8381 : DRM_DEBUG("IH: thermal low to high\n");
8382 0 : rdev->pm.dpm.thermal.high_to_low = false;
8383 : queue_thermal = true;
8384 0 : break;
8385 : case 231: /* thermal high to low */
8386 : DRM_DEBUG("IH: thermal high to low\n");
8387 0 : rdev->pm.dpm.thermal.high_to_low = true;
8388 : queue_thermal = true;
8389 0 : break;
8390 : case 233: /* GUI IDLE */
8391 : DRM_DEBUG("IH: GUI idle\n");
8392 : break;
8393 : case 241: /* SDMA Privileged inst */
8394 : case 247: /* SDMA Privileged inst */
8395 0 : DRM_ERROR("Illegal instruction in SDMA command stream\n");
8396 : /* XXX check the bitfield order! */
8397 0 : me_id = (ring_id & 0x3) >> 0;
8398 0 : queue_id = (ring_id & 0xc) >> 2;
8399 0 : switch (me_id) {
8400 : case 0:
8401 0 : switch (queue_id) {
8402 : case 0:
8403 : queue_reset = true;
8404 0 : break;
8405 : case 1:
8406 : /* XXX compute */
8407 : queue_reset = true;
8408 0 : break;
8409 : case 2:
8410 : /* XXX compute */
8411 : queue_reset = true;
8412 0 : break;
8413 : }
8414 : break;
8415 : case 1:
8416 0 : switch (queue_id) {
8417 : case 0:
8418 : queue_reset = true;
8419 0 : break;
8420 : case 1:
8421 : /* XXX compute */
8422 : queue_reset = true;
8423 0 : break;
8424 : case 2:
8425 : /* XXX compute */
8426 : queue_reset = true;
8427 0 : break;
8428 : }
8429 : break;
8430 : }
8431 : break;
8432 : default:
8433 : DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
8434 : break;
8435 : }
8436 :
8437 : /* wptr/rptr are in bytes! */
8438 0 : rptr += 16;
8439 0 : rptr &= rdev->ih.ptr_mask;
8440 0 : WREG32(IH_RB_RPTR, rptr);
8441 : }
8442 0 : if (queue_dp)
8443 0 : schedule_work(&rdev->dp_work);
8444 0 : if (queue_hotplug)
8445 0 : schedule_delayed_work(&rdev->hotplug_work, 0);
8446 0 : if (queue_reset) {
8447 0 : rdev->needs_reset = true;
8448 0 : wake_up_all(&rdev->fence_queue);
8449 0 : }
8450 0 : if (queue_thermal)
8451 0 : schedule_work(&rdev->pm.dpm.thermal.work);
8452 0 : rdev->ih.rptr = rptr;
8453 0 : atomic_set(&rdev->ih.lock, 0);
8454 :
8455 : /* make sure wptr hasn't changed while processing */
8456 0 : wptr = cik_get_ih_wptr(rdev);
8457 0 : if (wptr != rptr)
8458 0 : goto restart_ih;
8459 :
8460 0 : return IRQ_HANDLED;
8461 0 : }
8462 :
8463 : /*
8464 : * startup/shutdown callbacks
8465 : */
8466 : /**
8467 : * cik_startup - program the asic to a functional state
8468 : *
8469 : * @rdev: radeon_device pointer
8470 : *
8471 : * Programs the asic to a functional state (CIK).
8472 : * Called by cik_init() and cik_resume().
8473 : * Returns 0 for success, error for failure.
8474 : */
8475 0 : static int cik_startup(struct radeon_device *rdev)
8476 : {
8477 : struct radeon_ring *ring;
8478 : u32 nop;
8479 : int r;
8480 :
8481 : /* enable pcie gen2/3 link */
8482 0 : cik_pcie_gen3_enable(rdev);
8483 : /* enable aspm */
8484 0 : cik_program_aspm(rdev);
8485 :
8486 : /* scratch needs to be initialized before MC */
8487 0 : r = r600_vram_scratch_init(rdev);
8488 0 : if (r)
8489 0 : return r;
8490 :
8491 0 : cik_mc_program(rdev);
8492 :
8493 0 : if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
8494 0 : r = ci_mc_load_microcode(rdev);
8495 0 : if (r) {
8496 0 : DRM_ERROR("Failed to load MC firmware!\n");
8497 0 : return r;
8498 : }
8499 : }
8500 :
8501 0 : r = cik_pcie_gart_enable(rdev);
8502 0 : if (r)
8503 0 : return r;
8504 0 : cik_gpu_init(rdev);
8505 :
8506 : /* allocate rlc buffers */
8507 0 : if (rdev->flags & RADEON_IS_IGP) {
8508 0 : if (rdev->family == CHIP_KAVERI) {
8509 0 : rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;
8510 0 : rdev->rlc.reg_list_size =
8511 : (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
8512 0 : } else {
8513 0 : rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;
8514 0 : rdev->rlc.reg_list_size =
8515 : (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
8516 : }
8517 : }
8518 0 : rdev->rlc.cs_data = ci_cs_data;
8519 0 : rdev->rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
8520 0 : r = sumo_rlc_init(rdev);
8521 0 : if (r) {
8522 0 : DRM_ERROR("Failed to init rlc BOs!\n");
8523 0 : return r;
8524 : }
8525 :
8526 : /* allocate wb buffer */
8527 0 : r = radeon_wb_init(rdev);
8528 0 : if (r)
8529 0 : return r;
8530 :
8531 : /* allocate mec buffers */
8532 0 : r = cik_mec_init(rdev);
8533 0 : if (r) {
8534 0 : DRM_ERROR("Failed to init MEC BOs!\n");
8535 0 : return r;
8536 : }
8537 :
8538 0 : r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
8539 0 : if (r) {
8540 0 : dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
8541 0 : return r;
8542 : }
8543 :
8544 0 : r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
8545 0 : if (r) {
8546 0 : dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
8547 0 : return r;
8548 : }
8549 :
8550 0 : r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
8551 0 : if (r) {
8552 0 : dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
8553 0 : return r;
8554 : }
8555 :
8556 0 : r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
8557 0 : if (r) {
8558 0 : dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
8559 0 : return r;
8560 : }
8561 :
8562 0 : r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
8563 0 : if (r) {
8564 0 : dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
8565 0 : return r;
8566 : }
8567 :
8568 0 : r = radeon_uvd_resume(rdev);
8569 0 : if (!r) {
8570 0 : r = uvd_v4_2_resume(rdev);
8571 0 : if (!r) {
8572 0 : r = radeon_fence_driver_start_ring(rdev,
8573 : R600_RING_TYPE_UVD_INDEX);
8574 0 : if (r)
8575 0 : dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
8576 : }
8577 : }
8578 0 : if (r)
8579 0 : rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
8580 :
8581 0 : r = radeon_vce_resume(rdev);
8582 0 : if (!r) {
8583 0 : r = vce_v2_0_resume(rdev);
8584 0 : if (!r)
8585 0 : r = radeon_fence_driver_start_ring(rdev,
8586 : TN_RING_TYPE_VCE1_INDEX);
8587 0 : if (!r)
8588 0 : r = radeon_fence_driver_start_ring(rdev,
8589 : TN_RING_TYPE_VCE2_INDEX);
8590 : }
8591 0 : if (r) {
8592 0 : dev_err(rdev->dev, "VCE init error (%d).\n", r);
8593 0 : rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
8594 0 : rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
8595 0 : }
8596 :
8597 : /* Enable IRQ */
8598 0 : if (!rdev->irq.installed) {
8599 0 : r = radeon_irq_kms_init(rdev);
8600 0 : if (r)
8601 0 : return r;
8602 : }
8603 :
8604 0 : r = cik_irq_init(rdev);
8605 0 : if (r) {
8606 0 : DRM_ERROR("radeon: IH init failed (%d).\n", r);
8607 0 : radeon_irq_kms_fini(rdev);
8608 0 : return r;
8609 : }
8610 0 : cik_irq_set(rdev);
8611 :
8612 0 : if (rdev->family == CHIP_HAWAII) {
8613 0 : if (rdev->new_fw)
8614 0 : nop = PACKET3(PACKET3_NOP, 0x3FFF);
8615 : else
8616 : nop = RADEON_CP_PACKET2;
8617 : } else {
8618 : nop = PACKET3(PACKET3_NOP, 0x3FFF);
8619 : }
8620 :
8621 0 : ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
8622 0 : r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
8623 : nop);
8624 0 : if (r)
8625 0 : return r;
8626 :
8627 : /* set up the compute queues */
8628 : /* type-2 packets are deprecated on MEC, use type-3 instead */
8629 0 : ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
8630 0 : r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
8631 : nop);
8632 0 : if (r)
8633 0 : return r;
8634 0 : ring->me = 1; /* first MEC */
8635 0 : ring->pipe = 0; /* first pipe */
8636 0 : ring->queue = 0; /* first queue */
8637 0 : ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET;
8638 :
8639 : /* type-2 packets are deprecated on MEC, use type-3 instead */
8640 0 : ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
8641 0 : r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
8642 : nop);
8643 0 : if (r)
8644 0 : return r;
8645 : /* dGPU only have 1 MEC */
8646 0 : ring->me = 1; /* first MEC */
8647 0 : ring->pipe = 0; /* first pipe */
8648 0 : ring->queue = 1; /* second queue */
8649 0 : ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET;
8650 :
8651 0 : ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
8652 0 : r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
8653 : SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
8654 0 : if (r)
8655 0 : return r;
8656 :
8657 0 : ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
8658 0 : r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
8659 : SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
8660 0 : if (r)
8661 0 : return r;
8662 :
8663 0 : r = cik_cp_resume(rdev);
8664 0 : if (r)
8665 0 : return r;
8666 :
8667 0 : r = cik_sdma_resume(rdev);
8668 0 : if (r)
8669 0 : return r;
8670 :
8671 0 : ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
8672 0 : if (ring->ring_size) {
8673 0 : r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
8674 : RADEON_CP_PACKET2);
8675 0 : if (!r)
8676 0 : r = uvd_v1_0_init(rdev);
8677 0 : if (r)
8678 0 : DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
8679 : }
8680 :
8681 : r = -ENOENT;
8682 :
8683 0 : ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
8684 0 : if (ring->ring_size)
8685 0 : r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
8686 : VCE_CMD_NO_OP);
8687 :
8688 0 : ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
8689 0 : if (ring->ring_size)
8690 0 : r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
8691 : VCE_CMD_NO_OP);
8692 :
8693 0 : if (!r)
8694 0 : r = vce_v1_0_init(rdev);
8695 0 : else if (r != -ENOENT)
8696 0 : DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
8697 :
8698 0 : r = radeon_ib_pool_init(rdev);
8699 0 : if (r) {
8700 0 : dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
8701 0 : return r;
8702 : }
8703 :
8704 0 : r = radeon_vm_manager_init(rdev);
8705 0 : if (r) {
8706 0 : dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
8707 0 : return r;
8708 : }
8709 :
8710 0 : r = radeon_audio_init(rdev);
8711 0 : if (r)
8712 0 : return r;
8713 :
8714 : #ifdef notyet
8715 : r = radeon_kfd_resume(rdev);
8716 : if (r)
8717 : return r;
8718 : #endif
8719 :
8720 0 : return 0;
8721 0 : }
8722 :
8723 : /**
8724 : * cik_resume - resume the asic to a functional state
8725 : *
8726 : * @rdev: radeon_device pointer
8727 : *
8728 : * Programs the asic to a functional state (CIK).
8729 : * Called at resume.
8730 : * Returns 0 for success, error for failure.
8731 : */
8732 0 : int cik_resume(struct radeon_device *rdev)
8733 : {
8734 : int r;
8735 :
8736 : /* post card */
8737 0 : atom_asic_init(rdev->mode_info.atom_context);
8738 :
8739 : /* init golden registers */
8740 0 : cik_init_golden_registers(rdev);
8741 :
8742 0 : if (rdev->pm.pm_method == PM_METHOD_DPM)
8743 0 : radeon_pm_resume(rdev);
8744 :
8745 0 : rdev->accel_working = true;
8746 0 : r = cik_startup(rdev);
8747 0 : if (r) {
8748 0 : DRM_ERROR("cik startup failed on resume\n");
8749 0 : rdev->accel_working = false;
8750 0 : return r;
8751 : }
8752 :
8753 0 : return r;
8754 :
8755 0 : }
8756 :
8757 : /**
8758 : * cik_suspend - suspend the asic
8759 : *
8760 : * @rdev: radeon_device pointer
8761 : *
8762 : * Bring the chip into a state suitable for suspend (CIK).
8763 : * Called at suspend.
8764 : * Returns 0 for success.
8765 : */
8766 0 : int cik_suspend(struct radeon_device *rdev)
8767 : {
8768 : #ifdef notyet
8769 : radeon_kfd_suspend(rdev);
8770 : #endif
8771 0 : radeon_pm_suspend(rdev);
8772 0 : radeon_audio_fini(rdev);
8773 0 : radeon_vm_manager_fini(rdev);
8774 0 : cik_cp_enable(rdev, false);
8775 0 : cik_sdma_enable(rdev, false);
8776 0 : uvd_v1_0_fini(rdev);
8777 0 : radeon_uvd_suspend(rdev);
8778 0 : radeon_vce_suspend(rdev);
8779 0 : cik_fini_pg(rdev);
8780 0 : cik_fini_cg(rdev);
8781 0 : cik_irq_suspend(rdev);
8782 0 : radeon_wb_disable(rdev);
8783 0 : cik_pcie_gart_disable(rdev);
8784 0 : return 0;
8785 : }
8786 :
8787 : /* Plan is to move initialization in that function and use
8788 : * helper function so that radeon_device_init pretty much
8789 : * do nothing more than calling asic specific function. This
8790 : * should also allow to remove a bunch of callback function
8791 : * like vram_info.
8792 : */
8793 : /**
8794 : * cik_init - asic specific driver and hw init
8795 : *
8796 : * @rdev: radeon_device pointer
8797 : *
8798 : * Setup asic specific driver variables and program the hw
8799 : * to a functional state (CIK).
8800 : * Called at driver startup.
8801 : * Returns 0 for success, errors for failure.
8802 : */
8803 0 : int cik_init(struct radeon_device *rdev)
8804 : {
8805 : struct radeon_ring *ring;
8806 : int r;
8807 :
8808 : /* Read BIOS */
8809 0 : if (!radeon_get_bios(rdev)) {
8810 0 : if (ASIC_IS_AVIVO(rdev))
8811 0 : return -EINVAL;
8812 : }
8813 : /* Must be an ATOMBIOS */
8814 0 : if (!rdev->is_atom_bios) {
8815 0 : dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
8816 0 : return -EINVAL;
8817 : }
8818 0 : r = radeon_atombios_init(rdev);
8819 0 : if (r)
8820 0 : return r;
8821 :
8822 : /* Post card if necessary */
8823 0 : if (!radeon_card_posted(rdev)) {
8824 0 : if (!rdev->bios) {
8825 0 : dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
8826 0 : return -EINVAL;
8827 : }
8828 : DRM_INFO("GPU not posted. posting now...\n");
8829 0 : atom_asic_init(rdev->mode_info.atom_context);
8830 0 : }
8831 : /* init golden registers */
8832 0 : cik_init_golden_registers(rdev);
8833 : /* Initialize scratch registers */
8834 0 : cik_scratch_init(rdev);
8835 : /* Initialize surface registers */
8836 0 : radeon_surface_init(rdev);
8837 : /* Initialize clocks */
8838 0 : radeon_get_clock_info(rdev->ddev);
8839 :
8840 : /* Fence driver */
8841 0 : r = radeon_fence_driver_init(rdev);
8842 0 : if (r)
8843 0 : return r;
8844 :
8845 : /* initialize memory controller */
8846 0 : r = cik_mc_init(rdev);
8847 0 : if (r)
8848 0 : return r;
8849 : /* Memory manager */
8850 0 : r = radeon_bo_init(rdev);
8851 0 : if (r)
8852 0 : return r;
8853 :
8854 0 : if (rdev->flags & RADEON_IS_IGP) {
8855 0 : if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8856 0 : !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
8857 0 : r = cik_init_microcode(rdev);
8858 0 : if (r) {
8859 0 : DRM_ERROR("Failed to load firmware!\n");
8860 0 : return r;
8861 : }
8862 : }
8863 : } else {
8864 0 : if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8865 0 : !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
8866 0 : !rdev->mc_fw) {
8867 0 : r = cik_init_microcode(rdev);
8868 0 : if (r) {
8869 0 : DRM_ERROR("Failed to load firmware!\n");
8870 0 : return r;
8871 : }
8872 : }
8873 : }
8874 :
8875 : /* Initialize power management */
8876 0 : radeon_pm_init(rdev);
8877 :
8878 0 : ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
8879 0 : ring->ring_obj = NULL;
8880 0 : r600_ring_init(rdev, ring, 1024 * 1024);
8881 :
8882 0 : ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
8883 0 : ring->ring_obj = NULL;
8884 0 : r600_ring_init(rdev, ring, 1024 * 1024);
8885 0 : r = radeon_doorbell_get(rdev, &ring->doorbell_index);
8886 0 : if (r)
8887 0 : return r;
8888 :
8889 0 : ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
8890 0 : ring->ring_obj = NULL;
8891 0 : r600_ring_init(rdev, ring, 1024 * 1024);
8892 0 : r = radeon_doorbell_get(rdev, &ring->doorbell_index);
8893 0 : if (r)
8894 0 : return r;
8895 :
8896 0 : ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
8897 0 : ring->ring_obj = NULL;
8898 0 : r600_ring_init(rdev, ring, 256 * 1024);
8899 :
8900 0 : ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
8901 0 : ring->ring_obj = NULL;
8902 0 : r600_ring_init(rdev, ring, 256 * 1024);
8903 :
8904 0 : r = radeon_uvd_init(rdev);
8905 0 : if (!r) {
8906 0 : ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
8907 0 : ring->ring_obj = NULL;
8908 0 : r600_ring_init(rdev, ring, 4096);
8909 0 : }
8910 :
8911 0 : r = radeon_vce_init(rdev);
8912 0 : if (!r) {
8913 0 : ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
8914 0 : ring->ring_obj = NULL;
8915 0 : r600_ring_init(rdev, ring, 4096);
8916 :
8917 0 : ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
8918 0 : ring->ring_obj = NULL;
8919 0 : r600_ring_init(rdev, ring, 4096);
8920 0 : }
8921 :
8922 0 : rdev->ih.ring_obj = NULL;
8923 0 : r600_ih_ring_init(rdev, 64 * 1024);
8924 :
8925 0 : r = r600_pcie_gart_init(rdev);
8926 0 : if (r)
8927 0 : return r;
8928 :
8929 0 : rdev->accel_working = true;
8930 0 : r = cik_startup(rdev);
8931 0 : if (r) {
8932 0 : dev_err(rdev->dev, "disabling GPU acceleration\n");
8933 0 : cik_cp_fini(rdev);
8934 0 : cik_sdma_fini(rdev);
8935 0 : cik_irq_fini(rdev);
8936 0 : sumo_rlc_fini(rdev);
8937 0 : cik_mec_fini(rdev);
8938 0 : radeon_wb_fini(rdev);
8939 0 : radeon_ib_pool_fini(rdev);
8940 0 : radeon_vm_manager_fini(rdev);
8941 0 : radeon_irq_kms_fini(rdev);
8942 0 : cik_pcie_gart_fini(rdev);
8943 0 : rdev->accel_working = false;
8944 0 : }
8945 :
8946 : /* Don't start up if the MC ucode is missing.
8947 : * The default clocks and voltages before the MC ucode
8948 : * is loaded are not suffient for advanced operations.
8949 : */
8950 0 : if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
8951 0 : DRM_ERROR("radeon: MC ucode required for NI+.\n");
8952 0 : return -EINVAL;
8953 : }
8954 :
8955 0 : return 0;
8956 0 : }
8957 :
8958 : /**
8959 : * cik_fini - asic specific driver and hw fini
8960 : *
8961 : * @rdev: radeon_device pointer
8962 : *
8963 : * Tear down the asic specific driver variables and program the hw
8964 : * to an idle state (CIK).
8965 : * Called at driver unload.
8966 : */
8967 0 : void cik_fini(struct radeon_device *rdev)
8968 : {
8969 0 : radeon_pm_fini(rdev);
8970 0 : cik_cp_fini(rdev);
8971 0 : cik_sdma_fini(rdev);
8972 0 : cik_fini_pg(rdev);
8973 0 : cik_fini_cg(rdev);
8974 0 : cik_irq_fini(rdev);
8975 0 : sumo_rlc_fini(rdev);
8976 0 : cik_mec_fini(rdev);
8977 0 : radeon_wb_fini(rdev);
8978 0 : radeon_vm_manager_fini(rdev);
8979 0 : radeon_ib_pool_fini(rdev);
8980 0 : radeon_irq_kms_fini(rdev);
8981 0 : uvd_v1_0_fini(rdev);
8982 0 : radeon_uvd_fini(rdev);
8983 0 : radeon_vce_fini(rdev);
8984 0 : cik_pcie_gart_fini(rdev);
8985 0 : r600_vram_scratch_fini(rdev);
8986 0 : radeon_gem_fini(rdev);
8987 0 : radeon_fence_driver_fini(rdev);
8988 0 : radeon_bo_fini(rdev);
8989 0 : radeon_atombios_fini(rdev);
8990 0 : kfree(rdev->bios);
8991 0 : rdev->bios = NULL;
8992 0 : }
8993 :
8994 0 : void dce8_program_fmt(struct drm_encoder *encoder)
8995 : {
8996 0 : struct drm_device *dev = encoder->dev;
8997 0 : struct radeon_device *rdev = dev->dev_private;
8998 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8999 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
9000 0 : struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
9001 : int bpc = 0;
9002 : u32 tmp = 0;
9003 : enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
9004 :
9005 0 : if (connector) {
9006 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
9007 0 : bpc = radeon_get_monitor_bpc(connector);
9008 0 : dither = radeon_connector->dither;
9009 0 : }
9010 :
9011 : /* LVDS/eDP FMT is set up by atom */
9012 0 : if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
9013 0 : return;
9014 :
9015 : /* not needed for analog */
9016 0 : if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
9017 0 : (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
9018 0 : return;
9019 :
9020 0 : if (bpc == 0)
9021 0 : return;
9022 :
9023 0 : switch (bpc) {
9024 : case 6:
9025 0 : if (dither == RADEON_FMT_DITHER_ENABLE)
9026 : /* XXX sort out optimal dither settings */
9027 0 : tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
9028 : FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(0));
9029 : else
9030 : tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
9031 : break;
9032 : case 8:
9033 0 : if (dither == RADEON_FMT_DITHER_ENABLE)
9034 : /* XXX sort out optimal dither settings */
9035 0 : tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
9036 : FMT_RGB_RANDOM_ENABLE |
9037 : FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(1));
9038 : else
9039 : tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
9040 : break;
9041 : case 10:
9042 0 : if (dither == RADEON_FMT_DITHER_ENABLE)
9043 : /* XXX sort out optimal dither settings */
9044 0 : tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
9045 : FMT_RGB_RANDOM_ENABLE |
9046 : FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(2));
9047 : else
9048 : tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
9049 : break;
9050 : default:
9051 : /* not needed */
9052 : break;
9053 : }
9054 :
9055 0 : WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
9056 0 : }
9057 :
9058 : /* display watermark setup */
9059 : /**
9060 : * dce8_line_buffer_adjust - Set up the line buffer
9061 : *
9062 : * @rdev: radeon_device pointer
9063 : * @radeon_crtc: the selected display controller
9064 : * @mode: the current display mode on the selected display
9065 : * controller
9066 : *
9067 : * Setup up the line buffer allocation for
9068 : * the selected display controller (CIK).
9069 : * Returns the line buffer size in pixels.
9070 : */
9071 0 : static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
9072 : struct radeon_crtc *radeon_crtc,
9073 : struct drm_display_mode *mode)
9074 : {
9075 : u32 tmp, buffer_alloc, i;
9076 0 : u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
9077 : /*
9078 : * Line Buffer Setup
9079 : * There are 6 line buffers, one for each display controllers.
9080 : * There are 3 partitions per LB. Select the number of partitions
9081 : * to enable based on the display width. For display widths larger
9082 : * than 4096, you need use to use 2 display controllers and combine
9083 : * them using the stereo blender.
9084 : */
9085 0 : if (radeon_crtc->base.enabled && mode) {
9086 0 : if (mode->crtc_hdisplay < 1920) {
9087 : tmp = 1;
9088 : buffer_alloc = 2;
9089 0 : } else if (mode->crtc_hdisplay < 2560) {
9090 : tmp = 2;
9091 : buffer_alloc = 2;
9092 0 : } else if (mode->crtc_hdisplay < 4096) {
9093 : tmp = 0;
9094 : buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
9095 0 : } else {
9096 : DRM_DEBUG_KMS("Mode too big for LB!\n");
9097 : tmp = 0;
9098 : buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
9099 : }
9100 : } else {
9101 : tmp = 1;
9102 : buffer_alloc = 0;
9103 : }
9104 :
9105 0 : WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
9106 : LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
9107 :
9108 0 : WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
9109 : DMIF_BUFFERS_ALLOCATED(buffer_alloc));
9110 0 : for (i = 0; i < rdev->usec_timeout; i++) {
9111 0 : if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
9112 : DMIF_BUFFERS_ALLOCATED_COMPLETED)
9113 : break;
9114 0 : udelay(1);
9115 : }
9116 :
9117 0 : if (radeon_crtc->base.enabled && mode) {
9118 0 : switch (tmp) {
9119 : case 0:
9120 : default:
9121 0 : return 4096 * 2;
9122 : case 1:
9123 0 : return 1920 * 2;
9124 : case 2:
9125 0 : return 2560 * 2;
9126 : }
9127 : }
9128 :
9129 : /* controller not enabled, so no lb used */
9130 0 : return 0;
9131 0 : }
9132 :
9133 : /**
9134 : * cik_get_number_of_dram_channels - get the number of dram channels
9135 : *
9136 : * @rdev: radeon_device pointer
9137 : *
9138 : * Look up the number of video ram channels (CIK).
9139 : * Used for display watermark bandwidth calculations
9140 : * Returns the number of dram channels
9141 : */
9142 0 : static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)
9143 : {
9144 0 : u32 tmp = RREG32(MC_SHARED_CHMAP);
9145 :
9146 0 : switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
9147 : case 0:
9148 : default:
9149 0 : return 1;
9150 : case 1:
9151 0 : return 2;
9152 : case 2:
9153 0 : return 4;
9154 : case 3:
9155 0 : return 8;
9156 : case 4:
9157 0 : return 3;
9158 : case 5:
9159 0 : return 6;
9160 : case 6:
9161 0 : return 10;
9162 : case 7:
9163 0 : return 12;
9164 : case 8:
9165 0 : return 16;
9166 : }
9167 0 : }
9168 :
9169 : struct dce8_wm_params {
9170 : u32 dram_channels; /* number of dram channels */
9171 : u32 yclk; /* bandwidth per dram data pin in kHz */
9172 : u32 sclk; /* engine clock in kHz */
9173 : u32 disp_clk; /* display clock in kHz */
9174 : u32 src_width; /* viewport width */
9175 : u32 active_time; /* active display time in ns */
9176 : u32 blank_time; /* blank time in ns */
9177 : bool interlaced; /* mode is interlaced */
9178 : fixed20_12 vsc; /* vertical scale ratio */
9179 : u32 num_heads; /* number of active crtcs */
9180 : u32 bytes_per_pixel; /* bytes per pixel display + overlay */
9181 : u32 lb_size; /* line buffer allocated to pipe */
9182 : u32 vtaps; /* vertical scaler taps */
9183 : };
9184 :
9185 : /**
9186 : * dce8_dram_bandwidth - get the dram bandwidth
9187 : *
9188 : * @wm: watermark calculation data
9189 : *
9190 : * Calculate the raw dram bandwidth (CIK).
9191 : * Used for display watermark bandwidth calculations
9192 : * Returns the dram bandwidth in MBytes/s
9193 : */
9194 0 : static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)
9195 : {
9196 : /* Calculate raw DRAM Bandwidth */
9197 : fixed20_12 dram_efficiency; /* 0.7 */
9198 : fixed20_12 yclk, dram_channels, bandwidth;
9199 : fixed20_12 a;
9200 :
9201 : a.full = dfixed_const(1000);
9202 0 : yclk.full = dfixed_const(wm->yclk);
9203 0 : yclk.full = dfixed_div(yclk, a);
9204 0 : dram_channels.full = dfixed_const(wm->dram_channels * 4);
9205 : a.full = dfixed_const(10);
9206 : dram_efficiency.full = dfixed_const(7);
9207 0 : dram_efficiency.full = dfixed_div(dram_efficiency, a);
9208 0 : bandwidth.full = dfixed_mul(dram_channels, yclk);
9209 0 : bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
9210 :
9211 0 : return dfixed_trunc(bandwidth);
9212 : }
9213 :
9214 : /**
9215 : * dce8_dram_bandwidth_for_display - get the dram bandwidth for display
9216 : *
9217 : * @wm: watermark calculation data
9218 : *
9219 : * Calculate the dram bandwidth used for display (CIK).
9220 : * Used for display watermark bandwidth calculations
9221 : * Returns the dram bandwidth for display in MBytes/s
9222 : */
9223 0 : static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm)
9224 : {
9225 : /* Calculate DRAM Bandwidth and the part allocated to display. */
9226 : fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
9227 : fixed20_12 yclk, dram_channels, bandwidth;
9228 : fixed20_12 a;
9229 :
9230 : a.full = dfixed_const(1000);
9231 0 : yclk.full = dfixed_const(wm->yclk);
9232 0 : yclk.full = dfixed_div(yclk, a);
9233 0 : dram_channels.full = dfixed_const(wm->dram_channels * 4);
9234 : a.full = dfixed_const(10);
9235 : disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
9236 0 : disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
9237 0 : bandwidth.full = dfixed_mul(dram_channels, yclk);
9238 0 : bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
9239 :
9240 0 : return dfixed_trunc(bandwidth);
9241 : }
9242 :
9243 : /**
9244 : * dce8_data_return_bandwidth - get the data return bandwidth
9245 : *
9246 : * @wm: watermark calculation data
9247 : *
9248 : * Calculate the data return bandwidth used for display (CIK).
9249 : * Used for display watermark bandwidth calculations
9250 : * Returns the data return bandwidth in MBytes/s
9251 : */
9252 0 : static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm)
9253 : {
9254 : /* Calculate the display Data return Bandwidth */
9255 : fixed20_12 return_efficiency; /* 0.8 */
9256 : fixed20_12 sclk, bandwidth;
9257 : fixed20_12 a;
9258 :
9259 : a.full = dfixed_const(1000);
9260 0 : sclk.full = dfixed_const(wm->sclk);
9261 0 : sclk.full = dfixed_div(sclk, a);
9262 : a.full = dfixed_const(10);
9263 : return_efficiency.full = dfixed_const(8);
9264 0 : return_efficiency.full = dfixed_div(return_efficiency, a);
9265 : a.full = dfixed_const(32);
9266 0 : bandwidth.full = dfixed_mul(a, sclk);
9267 0 : bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
9268 :
9269 0 : return dfixed_trunc(bandwidth);
9270 : }
9271 :
9272 : /**
9273 : * dce8_dmif_request_bandwidth - get the dmif bandwidth
9274 : *
9275 : * @wm: watermark calculation data
9276 : *
9277 : * Calculate the dmif bandwidth used for display (CIK).
9278 : * Used for display watermark bandwidth calculations
9279 : * Returns the dmif bandwidth in MBytes/s
9280 : */
9281 0 : static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm)
9282 : {
9283 : /* Calculate the DMIF Request Bandwidth */
9284 : fixed20_12 disp_clk_request_efficiency; /* 0.8 */
9285 : fixed20_12 disp_clk, bandwidth;
9286 : fixed20_12 a, b;
9287 :
9288 : a.full = dfixed_const(1000);
9289 0 : disp_clk.full = dfixed_const(wm->disp_clk);
9290 0 : disp_clk.full = dfixed_div(disp_clk, a);
9291 : a.full = dfixed_const(32);
9292 0 : b.full = dfixed_mul(a, disp_clk);
9293 :
9294 : a.full = dfixed_const(10);
9295 : disp_clk_request_efficiency.full = dfixed_const(8);
9296 0 : disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
9297 :
9298 0 : bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
9299 :
9300 0 : return dfixed_trunc(bandwidth);
9301 : }
9302 :
9303 : /**
9304 : * dce8_available_bandwidth - get the min available bandwidth
9305 : *
9306 : * @wm: watermark calculation data
9307 : *
9308 : * Calculate the min available bandwidth used for display (CIK).
9309 : * Used for display watermark bandwidth calculations
9310 : * Returns the min available bandwidth in MBytes/s
9311 : */
9312 0 : static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)
9313 : {
9314 : /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
9315 0 : u32 dram_bandwidth = dce8_dram_bandwidth(wm);
9316 0 : u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);
9317 0 : u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);
9318 :
9319 0 : return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
9320 : }
9321 :
9322 : /**
9323 : * dce8_average_bandwidth - get the average available bandwidth
9324 : *
9325 : * @wm: watermark calculation data
9326 : *
9327 : * Calculate the average available bandwidth used for display (CIK).
9328 : * Used for display watermark bandwidth calculations
9329 : * Returns the average available bandwidth in MBytes/s
9330 : */
9331 0 : static u32 dce8_average_bandwidth(struct dce8_wm_params *wm)
9332 : {
9333 : /* Calculate the display mode Average Bandwidth
9334 : * DisplayMode should contain the source and destination dimensions,
9335 : * timing, etc.
9336 : */
9337 : fixed20_12 bpp;
9338 : fixed20_12 line_time;
9339 : fixed20_12 src_width;
9340 : fixed20_12 bandwidth;
9341 : fixed20_12 a;
9342 :
9343 : a.full = dfixed_const(1000);
9344 0 : line_time.full = dfixed_const(wm->active_time + wm->blank_time);
9345 0 : line_time.full = dfixed_div(line_time, a);
9346 0 : bpp.full = dfixed_const(wm->bytes_per_pixel);
9347 0 : src_width.full = dfixed_const(wm->src_width);
9348 0 : bandwidth.full = dfixed_mul(src_width, bpp);
9349 0 : bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
9350 0 : bandwidth.full = dfixed_div(bandwidth, line_time);
9351 :
9352 0 : return dfixed_trunc(bandwidth);
9353 : }
9354 :
9355 : /**
9356 : * dce8_latency_watermark - get the latency watermark
9357 : *
9358 : * @wm: watermark calculation data
9359 : *
9360 : * Calculate the latency watermark (CIK).
9361 : * Used for display watermark bandwidth calculations
9362 : * Returns the latency watermark in ns
9363 : */
9364 0 : static u32 dce8_latency_watermark(struct dce8_wm_params *wm)
9365 : {
9366 : /* First calculate the latency in ns */
9367 : u32 mc_latency = 2000; /* 2000 ns. */
9368 0 : u32 available_bandwidth = dce8_available_bandwidth(wm);
9369 0 : u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
9370 0 : u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
9371 0 : u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
9372 0 : u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
9373 0 : (wm->num_heads * cursor_line_pair_return_time);
9374 0 : u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
9375 : u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
9376 : u32 tmp, dmif_size = 12288;
9377 : fixed20_12 a, b, c;
9378 :
9379 0 : if (wm->num_heads == 0)
9380 0 : return 0;
9381 :
9382 : a.full = dfixed_const(2);
9383 : b.full = dfixed_const(1);
9384 0 : if ((wm->vsc.full > a.full) ||
9385 0 : ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
9386 0 : (wm->vtaps >= 5) ||
9387 0 : ((wm->vsc.full >= a.full) && wm->interlaced))
9388 0 : max_src_lines_per_dst_line = 4;
9389 : else
9390 : max_src_lines_per_dst_line = 2;
9391 :
9392 0 : a.full = dfixed_const(available_bandwidth);
9393 0 : b.full = dfixed_const(wm->num_heads);
9394 0 : a.full = dfixed_div(a, b);
9395 :
9396 : b.full = dfixed_const(mc_latency + 512);
9397 0 : c.full = dfixed_const(wm->disp_clk);
9398 0 : b.full = dfixed_div(b, c);
9399 :
9400 : c.full = dfixed_const(dmif_size);
9401 0 : b.full = dfixed_div(c, b);
9402 :
9403 0 : tmp = min(dfixed_trunc(a), dfixed_trunc(b));
9404 :
9405 : b.full = dfixed_const(1000);
9406 0 : c.full = dfixed_const(wm->disp_clk);
9407 0 : b.full = dfixed_div(c, b);
9408 0 : c.full = dfixed_const(wm->bytes_per_pixel);
9409 0 : b.full = dfixed_mul(b, c);
9410 :
9411 0 : lb_fill_bw = min(tmp, dfixed_trunc(b));
9412 :
9413 0 : a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
9414 : b.full = dfixed_const(1000);
9415 0 : c.full = dfixed_const(lb_fill_bw);
9416 0 : b.full = dfixed_div(c, b);
9417 0 : a.full = dfixed_div(a, b);
9418 0 : line_fill_time = dfixed_trunc(a);
9419 :
9420 0 : if (line_fill_time < wm->active_time)
9421 0 : return latency;
9422 : else
9423 0 : return latency + (line_fill_time - wm->active_time);
9424 :
9425 0 : }
9426 :
9427 : /**
9428 : * dce8_average_bandwidth_vs_dram_bandwidth_for_display - check
9429 : * average and available dram bandwidth
9430 : *
9431 : * @wm: watermark calculation data
9432 : *
9433 : * Check if the display average bandwidth fits in the display
9434 : * dram bandwidth (CIK).
9435 : * Used for display watermark bandwidth calculations
9436 : * Returns true if the display fits, false if not.
9437 : */
9438 0 : static bool dce8_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
9439 : {
9440 0 : if (dce8_average_bandwidth(wm) <=
9441 0 : (dce8_dram_bandwidth_for_display(wm) / wm->num_heads))
9442 0 : return true;
9443 : else
9444 0 : return false;
9445 0 : }
9446 :
9447 : /**
9448 : * dce8_average_bandwidth_vs_available_bandwidth - check
9449 : * average and available bandwidth
9450 : *
9451 : * @wm: watermark calculation data
9452 : *
9453 : * Check if the display average bandwidth fits in the display
9454 : * available bandwidth (CIK).
9455 : * Used for display watermark bandwidth calculations
9456 : * Returns true if the display fits, false if not.
9457 : */
9458 0 : static bool dce8_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
9459 : {
9460 0 : if (dce8_average_bandwidth(wm) <=
9461 0 : (dce8_available_bandwidth(wm) / wm->num_heads))
9462 0 : return true;
9463 : else
9464 0 : return false;
9465 0 : }
9466 :
9467 : /**
9468 : * dce8_check_latency_hiding - check latency hiding
9469 : *
9470 : * @wm: watermark calculation data
9471 : *
9472 : * Check latency hiding (CIK).
9473 : * Used for display watermark bandwidth calculations
9474 : * Returns true if the display fits, false if not.
9475 : */
9476 0 : static bool dce8_check_latency_hiding(struct dce8_wm_params *wm)
9477 : {
9478 0 : u32 lb_partitions = wm->lb_size / wm->src_width;
9479 0 : u32 line_time = wm->active_time + wm->blank_time;
9480 : u32 latency_tolerant_lines;
9481 : u32 latency_hiding;
9482 : fixed20_12 a;
9483 :
9484 : a.full = dfixed_const(1);
9485 0 : if (wm->vsc.full > a.full)
9486 0 : latency_tolerant_lines = 1;
9487 : else {
9488 0 : if (lb_partitions <= (wm->vtaps + 1))
9489 0 : latency_tolerant_lines = 1;
9490 : else
9491 : latency_tolerant_lines = 2;
9492 : }
9493 :
9494 0 : latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
9495 :
9496 0 : if (dce8_latency_watermark(wm) <= latency_hiding)
9497 0 : return true;
9498 : else
9499 0 : return false;
9500 0 : }
9501 :
9502 : /**
9503 : * dce8_program_watermarks - program display watermarks
9504 : *
9505 : * @rdev: radeon_device pointer
9506 : * @radeon_crtc: the selected display controller
9507 : * @lb_size: line buffer size
9508 : * @num_heads: number of display controllers in use
9509 : *
9510 : * Calculate and program the display watermarks for the
9511 : * selected display controller (CIK).
9512 : */
9513 0 : static void dce8_program_watermarks(struct radeon_device *rdev,
9514 : struct radeon_crtc *radeon_crtc,
9515 : u32 lb_size, u32 num_heads)
9516 : {
9517 0 : struct drm_display_mode *mode = &radeon_crtc->base.mode;
9518 0 : struct dce8_wm_params wm_low, wm_high;
9519 : u32 pixel_period;
9520 : u32 line_time = 0;
9521 : u32 latency_watermark_a = 0, latency_watermark_b = 0;
9522 : u32 tmp, wm_mask;
9523 :
9524 0 : if (radeon_crtc->base.enabled && num_heads && mode) {
9525 0 : pixel_period = 1000000 / (u32)mode->clock;
9526 0 : line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
9527 :
9528 : /* watermark for high clocks */
9529 0 : if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
9530 0 : rdev->pm.dpm_enabled) {
9531 0 : wm_high.yclk =
9532 0 : radeon_dpm_get_mclk(rdev, false) * 10;
9533 0 : wm_high.sclk =
9534 0 : radeon_dpm_get_sclk(rdev, false) * 10;
9535 0 : } else {
9536 0 : wm_high.yclk = rdev->pm.current_mclk * 10;
9537 0 : wm_high.sclk = rdev->pm.current_sclk * 10;
9538 : }
9539 :
9540 0 : wm_high.disp_clk = mode->clock;
9541 0 : wm_high.src_width = mode->crtc_hdisplay;
9542 0 : wm_high.active_time = mode->crtc_hdisplay * pixel_period;
9543 0 : wm_high.blank_time = line_time - wm_high.active_time;
9544 0 : wm_high.interlaced = false;
9545 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
9546 0 : wm_high.interlaced = true;
9547 0 : wm_high.vsc = radeon_crtc->vsc;
9548 0 : wm_high.vtaps = 1;
9549 0 : if (radeon_crtc->rmx_type != RMX_OFF)
9550 0 : wm_high.vtaps = 2;
9551 0 : wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
9552 0 : wm_high.lb_size = lb_size;
9553 0 : wm_high.dram_channels = cik_get_number_of_dram_channels(rdev);
9554 0 : wm_high.num_heads = num_heads;
9555 :
9556 : /* set for high clocks */
9557 0 : latency_watermark_a = min(dce8_latency_watermark(&wm_high), (u32)65535);
9558 :
9559 : /* possibly force display priority to high */
9560 : /* should really do this at mode validation time... */
9561 0 : if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
9562 0 : !dce8_average_bandwidth_vs_available_bandwidth(&wm_high) ||
9563 0 : !dce8_check_latency_hiding(&wm_high) ||
9564 : (rdev->disp_priority == 2)) {
9565 : DRM_DEBUG_KMS("force priority to high\n");
9566 : }
9567 :
9568 : /* watermark for low clocks */
9569 0 : if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
9570 0 : rdev->pm.dpm_enabled) {
9571 0 : wm_low.yclk =
9572 0 : radeon_dpm_get_mclk(rdev, true) * 10;
9573 0 : wm_low.sclk =
9574 0 : radeon_dpm_get_sclk(rdev, true) * 10;
9575 0 : } else {
9576 0 : wm_low.yclk = rdev->pm.current_mclk * 10;
9577 0 : wm_low.sclk = rdev->pm.current_sclk * 10;
9578 : }
9579 :
9580 0 : wm_low.disp_clk = mode->clock;
9581 0 : wm_low.src_width = mode->crtc_hdisplay;
9582 0 : wm_low.active_time = mode->crtc_hdisplay * pixel_period;
9583 0 : wm_low.blank_time = line_time - wm_low.active_time;
9584 0 : wm_low.interlaced = false;
9585 0 : if (mode->flags & DRM_MODE_FLAG_INTERLACE)
9586 0 : wm_low.interlaced = true;
9587 0 : wm_low.vsc = radeon_crtc->vsc;
9588 0 : wm_low.vtaps = 1;
9589 0 : if (radeon_crtc->rmx_type != RMX_OFF)
9590 0 : wm_low.vtaps = 2;
9591 0 : wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
9592 0 : wm_low.lb_size = lb_size;
9593 0 : wm_low.dram_channels = cik_get_number_of_dram_channels(rdev);
9594 0 : wm_low.num_heads = num_heads;
9595 :
9596 : /* set for low clocks */
9597 0 : latency_watermark_b = min(dce8_latency_watermark(&wm_low), (u32)65535);
9598 :
9599 : /* possibly force display priority to high */
9600 : /* should really do this at mode validation time... */
9601 0 : if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
9602 0 : !dce8_average_bandwidth_vs_available_bandwidth(&wm_low) ||
9603 0 : !dce8_check_latency_hiding(&wm_low) ||
9604 : (rdev->disp_priority == 2)) {
9605 : DRM_DEBUG_KMS("force priority to high\n");
9606 : }
9607 :
9608 : /* Save number of lines the linebuffer leads before the scanout */
9609 0 : radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
9610 0 : }
9611 :
9612 : /* select wm A */
9613 0 : wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9614 : tmp = wm_mask;
9615 0 : tmp &= ~LATENCY_WATERMARK_MASK(3);
9616 0 : tmp |= LATENCY_WATERMARK_MASK(1);
9617 0 : WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9618 0 : WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
9619 : (LATENCY_LOW_WATERMARK(latency_watermark_a) |
9620 : LATENCY_HIGH_WATERMARK(line_time)));
9621 : /* select wm B */
9622 0 : tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9623 0 : tmp &= ~LATENCY_WATERMARK_MASK(3);
9624 0 : tmp |= LATENCY_WATERMARK_MASK(2);
9625 0 : WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9626 0 : WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
9627 : (LATENCY_LOW_WATERMARK(latency_watermark_b) |
9628 : LATENCY_HIGH_WATERMARK(line_time)));
9629 : /* restore original selection */
9630 0 : WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
9631 :
9632 : /* save values for DPM */
9633 0 : radeon_crtc->line_time = line_time;
9634 0 : radeon_crtc->wm_high = latency_watermark_a;
9635 0 : radeon_crtc->wm_low = latency_watermark_b;
9636 0 : }
9637 :
9638 : /**
9639 : * dce8_bandwidth_update - program display watermarks
9640 : *
9641 : * @rdev: radeon_device pointer
9642 : *
9643 : * Calculate and program the display watermarks and line
9644 : * buffer allocation (CIK).
9645 : */
9646 0 : void dce8_bandwidth_update(struct radeon_device *rdev)
9647 : {
9648 : struct drm_display_mode *mode = NULL;
9649 : u32 num_heads = 0, lb_size;
9650 : int i;
9651 :
9652 0 : if (!rdev->mode_info.mode_config_initialized)
9653 0 : return;
9654 :
9655 0 : radeon_update_display_priority(rdev);
9656 :
9657 0 : for (i = 0; i < rdev->num_crtc; i++) {
9658 0 : if (rdev->mode_info.crtcs[i]->base.enabled)
9659 0 : num_heads++;
9660 : }
9661 0 : for (i = 0; i < rdev->num_crtc; i++) {
9662 0 : mode = &rdev->mode_info.crtcs[i]->base.mode;
9663 0 : lb_size = dce8_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode);
9664 0 : dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
9665 : }
9666 0 : }
9667 :
9668 : /**
9669 : * cik_get_gpu_clock_counter - return GPU clock counter snapshot
9670 : *
9671 : * @rdev: radeon_device pointer
9672 : *
9673 : * Fetches a GPU clock counter snapshot (SI).
9674 : * Returns the 64 bit clock counter snapshot.
9675 : */
9676 0 : uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev)
9677 : {
9678 : uint64_t clock;
9679 :
9680 0 : mutex_lock(&rdev->gpu_clock_mutex);
9681 0 : WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
9682 0 : clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
9683 0 : ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
9684 0 : mutex_unlock(&rdev->gpu_clock_mutex);
9685 0 : return clock;
9686 : }
9687 :
9688 0 : static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,
9689 : u32 cntl_reg, u32 status_reg)
9690 : {
9691 : int r, i;
9692 0 : struct atom_clock_dividers dividers;
9693 : uint32_t tmp;
9694 :
9695 0 : r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
9696 : clock, false, ÷rs);
9697 0 : if (r)
9698 0 : return r;
9699 :
9700 0 : tmp = RREG32_SMC(cntl_reg);
9701 0 : tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
9702 0 : tmp |= dividers.post_divider;
9703 0 : WREG32_SMC(cntl_reg, tmp);
9704 :
9705 0 : for (i = 0; i < 100; i++) {
9706 0 : if (RREG32_SMC(status_reg) & DCLK_STATUS)
9707 : break;
9708 0 : mdelay(10);
9709 : }
9710 0 : if (i == 100)
9711 0 : return -ETIMEDOUT;
9712 :
9713 0 : return 0;
9714 0 : }
9715 :
9716 0 : int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
9717 : {
9718 : int r = 0;
9719 :
9720 0 : r = cik_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
9721 0 : if (r)
9722 0 : return r;
9723 :
9724 0 : r = cik_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
9725 0 : return r;
9726 0 : }
9727 :
9728 0 : int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
9729 : {
9730 : int r, i;
9731 0 : struct atom_clock_dividers dividers;
9732 : u32 tmp;
9733 :
9734 0 : r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
9735 : ecclk, false, ÷rs);
9736 0 : if (r)
9737 0 : return r;
9738 :
9739 0 : for (i = 0; i < 100; i++) {
9740 0 : if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
9741 : break;
9742 0 : mdelay(10);
9743 : }
9744 0 : if (i == 100)
9745 0 : return -ETIMEDOUT;
9746 :
9747 0 : tmp = RREG32_SMC(CG_ECLK_CNTL);
9748 0 : tmp &= ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK);
9749 0 : tmp |= dividers.post_divider;
9750 0 : WREG32_SMC(CG_ECLK_CNTL, tmp);
9751 :
9752 0 : for (i = 0; i < 100; i++) {
9753 0 : if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS)
9754 : break;
9755 0 : mdelay(10);
9756 : }
9757 0 : if (i == 100)
9758 0 : return -ETIMEDOUT;
9759 :
9760 0 : return 0;
9761 0 : }
9762 :
9763 0 : static void cik_pcie_gen3_enable(struct radeon_device *rdev)
9764 : {
9765 0 : struct pci_dev _root;
9766 : struct pci_dev *root;
9767 : int bridge_pos, gpu_pos;
9768 0 : u32 speed_cntl, mask, current_data_rate;
9769 : int ret, i;
9770 0 : u16 tmp16;
9771 :
9772 : root = &_root;
9773 0 : root->pc = rdev->pdev->pc;
9774 0 : root->tag = *rdev->ddev->bridgetag;
9775 :
9776 0 : if (pci_is_root_bus(rdev->pdev->bus))
9777 0 : return;
9778 :
9779 0 : if (radeon_pcie_gen2 == 0)
9780 0 : return;
9781 :
9782 0 : if (rdev->flags & RADEON_IS_IGP)
9783 0 : return;
9784 :
9785 0 : if (!(rdev->flags & RADEON_IS_PCIE))
9786 0 : return;
9787 :
9788 0 : ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
9789 0 : if (ret != 0)
9790 0 : return;
9791 :
9792 0 : if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
9793 0 : return;
9794 :
9795 0 : speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9796 0 : current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
9797 : LC_CURRENT_DATA_RATE_SHIFT;
9798 0 : if (mask & DRM_PCIE_SPEED_80) {
9799 0 : if (current_data_rate == 2) {
9800 : DRM_INFO("PCIE gen 3 link speeds already enabled\n");
9801 0 : return;
9802 : }
9803 : DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
9804 0 : } else if (mask & DRM_PCIE_SPEED_50) {
9805 0 : if (current_data_rate == 1) {
9806 : DRM_INFO("PCIE gen 2 link speeds already enabled\n");
9807 0 : return;
9808 : }
9809 : DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
9810 : }
9811 :
9812 0 : bridge_pos = pci_pcie_cap(root);
9813 0 : if (!bridge_pos)
9814 0 : return;
9815 :
9816 0 : gpu_pos = pci_pcie_cap(rdev->pdev);
9817 0 : if (!gpu_pos)
9818 0 : return;
9819 :
9820 0 : if (mask & DRM_PCIE_SPEED_80) {
9821 : /* re-try equalization if gen3 is not already enabled */
9822 0 : if (current_data_rate != 2) {
9823 0 : u16 bridge_cfg, gpu_cfg;
9824 0 : u16 bridge_cfg2, gpu_cfg2;
9825 : u32 max_lw, current_lw, tmp;
9826 :
9827 0 : pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
9828 0 : pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
9829 :
9830 0 : tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
9831 0 : pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
9832 :
9833 0 : tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
9834 0 : pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
9835 :
9836 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9837 0 : max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
9838 0 : current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
9839 :
9840 0 : if (current_lw < max_lw) {
9841 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9842 0 : if (tmp & LC_RENEGOTIATION_SUPPORT) {
9843 0 : tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
9844 0 : tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
9845 0 : tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
9846 0 : WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
9847 0 : }
9848 : }
9849 :
9850 0 : for (i = 0; i < 10; i++) {
9851 : /* check status */
9852 0 : pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
9853 0 : if (tmp16 & PCI_EXP_DEVSTA_TRPND)
9854 : break;
9855 :
9856 0 : pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
9857 0 : pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
9858 :
9859 0 : pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
9860 0 : pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
9861 :
9862 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9863 0 : tmp |= LC_SET_QUIESCE;
9864 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9865 :
9866 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9867 0 : tmp |= LC_REDO_EQ;
9868 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9869 :
9870 0 : mdelay(100);
9871 :
9872 : /* linkctl */
9873 0 : pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
9874 0 : tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
9875 0 : tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
9876 0 : pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
9877 :
9878 0 : pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
9879 0 : tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
9880 0 : tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
9881 0 : pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
9882 :
9883 : /* linkctl2 */
9884 0 : pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
9885 0 : tmp16 &= ~((1 << 4) | (7 << 9));
9886 0 : tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
9887 0 : pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
9888 :
9889 0 : pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9890 0 : tmp16 &= ~((1 << 4) | (7 << 9));
9891 0 : tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
9892 0 : pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9893 :
9894 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
9895 0 : tmp &= ~LC_SET_QUIESCE;
9896 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
9897 : }
9898 0 : }
9899 : }
9900 :
9901 : /* set the link speed */
9902 0 : speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
9903 0 : speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
9904 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9905 :
9906 0 : pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
9907 0 : tmp16 &= ~0xf;
9908 0 : if (mask & DRM_PCIE_SPEED_80)
9909 0 : tmp16 |= 3; /* gen3 */
9910 0 : else if (mask & DRM_PCIE_SPEED_50)
9911 0 : tmp16 |= 2; /* gen2 */
9912 : else
9913 0 : tmp16 |= 1; /* gen1 */
9914 0 : pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9915 :
9916 0 : speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9917 0 : speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
9918 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9919 :
9920 0 : for (i = 0; i < rdev->usec_timeout; i++) {
9921 0 : speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9922 0 : if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
9923 : break;
9924 0 : udelay(1);
9925 : }
9926 0 : }
9927 :
9928 0 : static void cik_program_aspm(struct radeon_device *rdev)
9929 : {
9930 : u32 data, orig;
9931 : bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
9932 : bool disable_clkreq = false;
9933 :
9934 0 : if (radeon_aspm == 0)
9935 0 : return;
9936 :
9937 : /* XXX double check IGPs */
9938 0 : if (rdev->flags & RADEON_IS_IGP)
9939 0 : return;
9940 :
9941 0 : if (!(rdev->flags & RADEON_IS_PCIE))
9942 0 : return;
9943 :
9944 0 : orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9945 0 : data &= ~LC_XMIT_N_FTS_MASK;
9946 0 : data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
9947 0 : if (orig != data)
9948 0 : WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
9949 :
9950 0 : orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
9951 0 : data |= LC_GO_TO_RECOVERY;
9952 0 : if (orig != data)
9953 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
9954 :
9955 0 : orig = data = RREG32_PCIE_PORT(PCIE_P_CNTL);
9956 0 : data |= P_IGNORE_EDB_ERR;
9957 0 : if (orig != data)
9958 0 : WREG32_PCIE_PORT(PCIE_P_CNTL, data);
9959 :
9960 0 : orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9961 0 : data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
9962 0 : data |= LC_PMI_TO_L1_DIS;
9963 0 : if (!disable_l0s)
9964 0 : data |= LC_L0S_INACTIVITY(7);
9965 :
9966 0 : if (!disable_l1) {
9967 0 : data |= LC_L1_INACTIVITY(7);
9968 0 : data &= ~LC_PMI_TO_L1_DIS;
9969 0 : if (orig != data)
9970 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9971 :
9972 0 : if (!disable_plloff_in_l1) {
9973 : bool clk_req_support;
9974 :
9975 0 : orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0);
9976 0 : data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9977 0 : data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9978 0 : if (orig != data)
9979 0 : WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0, data);
9980 :
9981 0 : orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1);
9982 0 : data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9983 0 : data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9984 0 : if (orig != data)
9985 0 : WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1, data);
9986 :
9987 0 : orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0);
9988 0 : data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9989 0 : data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9990 0 : if (orig != data)
9991 0 : WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0, data);
9992 :
9993 0 : orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1);
9994 0 : data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9995 0 : data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9996 0 : if (orig != data)
9997 0 : WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1, data);
9998 :
9999 0 : orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
10000 0 : data &= ~LC_DYN_LANES_PWR_STATE_MASK;
10001 0 : data |= LC_DYN_LANES_PWR_STATE(3);
10002 0 : if (orig != data)
10003 0 : WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
10004 :
10005 0 : if (!disable_clkreq &&
10006 0 : !pci_is_root_bus(rdev->pdev->bus)) {
10007 0 : u32 lnkcap;
10008 0 : struct pci_dev _root;
10009 : struct pci_dev *root;
10010 :
10011 : root = &_root;
10012 0 : root->pc = rdev->pdev->pc;
10013 0 : root->tag = *rdev->ddev->bridgetag;
10014 :
10015 : clk_req_support = false;
10016 0 : pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
10017 0 : if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
10018 0 : clk_req_support = true;
10019 0 : } else {
10020 : clk_req_support = false;
10021 : }
10022 :
10023 0 : if (clk_req_support) {
10024 0 : orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
10025 0 : data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
10026 0 : if (orig != data)
10027 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
10028 :
10029 0 : orig = data = RREG32_SMC(THM_CLK_CNTL);
10030 0 : data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
10031 0 : data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
10032 0 : if (orig != data)
10033 0 : WREG32_SMC(THM_CLK_CNTL, data);
10034 :
10035 0 : orig = data = RREG32_SMC(MISC_CLK_CTRL);
10036 0 : data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
10037 0 : data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
10038 0 : if (orig != data)
10039 0 : WREG32_SMC(MISC_CLK_CTRL, data);
10040 :
10041 0 : orig = data = RREG32_SMC(CG_CLKPIN_CNTL);
10042 0 : data &= ~BCLK_AS_XCLK;
10043 0 : if (orig != data)
10044 0 : WREG32_SMC(CG_CLKPIN_CNTL, data);
10045 :
10046 0 : orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2);
10047 0 : data &= ~FORCE_BIF_REFCLK_EN;
10048 0 : if (orig != data)
10049 0 : WREG32_SMC(CG_CLKPIN_CNTL_2, data);
10050 :
10051 0 : orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL);
10052 0 : data &= ~MPLL_CLKOUT_SEL_MASK;
10053 0 : data |= MPLL_CLKOUT_SEL(4);
10054 0 : if (orig != data)
10055 0 : WREG32_SMC(MPLL_BYPASSCLK_SEL, data);
10056 : }
10057 0 : }
10058 : } else {
10059 0 : if (orig != data)
10060 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
10061 : }
10062 :
10063 0 : orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
10064 0 : data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
10065 0 : if (orig != data)
10066 0 : WREG32_PCIE_PORT(PCIE_CNTL2, data);
10067 :
10068 0 : if (!disable_l0s) {
10069 0 : data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
10070 0 : if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
10071 0 : data = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
10072 0 : if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
10073 0 : orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
10074 0 : data &= ~LC_L0S_INACTIVITY_MASK;
10075 0 : if (orig != data)
10076 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
10077 : }
10078 : }
10079 : }
10080 0 : }
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