Line data Source code
1 : /*
2 : * Copyright 2013 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: Alex Deucher
23 : */
24 : #include <dev/pci/drm/drmP.h>
25 : #include "radeon.h"
26 : #include "radeon_ucode.h"
27 : #include "radeon_asic.h"
28 : #include "radeon_trace.h"
29 : #include "cikd.h"
30 :
31 : /* sdma */
32 : #define CIK_SDMA_UCODE_SIZE 1050
33 : #define CIK_SDMA_UCODE_VERSION 64
34 :
35 : u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
36 :
37 : /*
38 : * sDMA - System DMA
39 : * Starting with CIK, the GPU has new asynchronous
40 : * DMA engines. These engines are used for compute
41 : * and gfx. There are two DMA engines (SDMA0, SDMA1)
42 : * and each one supports 1 ring buffer used for gfx
43 : * and 2 queues used for compute.
44 : *
45 : * The programming model is very similar to the CP
46 : * (ring buffer, IBs, etc.), but sDMA has it's own
47 : * packet format that is different from the PM4 format
48 : * used by the CP. sDMA supports copying data, writing
49 : * embedded data, solid fills, and a number of other
50 : * things. It also has support for tiling/detiling of
51 : * buffers.
52 : */
53 :
54 : /**
55 : * cik_sdma_get_rptr - get the current read pointer
56 : *
57 : * @rdev: radeon_device pointer
58 : * @ring: radeon ring pointer
59 : *
60 : * Get the current rptr from the hardware (CIK+).
61 : */
62 0 : uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,
63 : struct radeon_ring *ring)
64 : {
65 : u32 rptr, reg;
66 :
67 0 : if (rdev->wb.enabled) {
68 0 : rptr = rdev->wb.wb[ring->rptr_offs/4];
69 0 : } else {
70 0 : if (ring->idx == R600_RING_TYPE_DMA_INDEX)
71 0 : reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
72 : else
73 : reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
74 :
75 0 : rptr = RREG32(reg);
76 : }
77 :
78 0 : return (rptr & 0x3fffc) >> 2;
79 : }
80 :
81 : /**
82 : * cik_sdma_get_wptr - get the current write pointer
83 : *
84 : * @rdev: radeon_device pointer
85 : * @ring: radeon ring pointer
86 : *
87 : * Get the current wptr from the hardware (CIK+).
88 : */
89 0 : uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,
90 : struct radeon_ring *ring)
91 : {
92 : u32 reg;
93 :
94 0 : if (ring->idx == R600_RING_TYPE_DMA_INDEX)
95 0 : reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
96 : else
97 : reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
98 :
99 0 : return (RREG32(reg) & 0x3fffc) >> 2;
100 : }
101 :
102 : /**
103 : * cik_sdma_set_wptr - commit the write pointer
104 : *
105 : * @rdev: radeon_device pointer
106 : * @ring: radeon ring pointer
107 : *
108 : * Write the wptr back to the hardware (CIK+).
109 : */
110 0 : void cik_sdma_set_wptr(struct radeon_device *rdev,
111 : struct radeon_ring *ring)
112 : {
113 : u32 reg;
114 :
115 0 : if (ring->idx == R600_RING_TYPE_DMA_INDEX)
116 0 : reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
117 : else
118 : reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
119 :
120 0 : WREG32(reg, (ring->wptr << 2) & 0x3fffc);
121 0 : (void)RREG32(reg);
122 0 : }
123 :
124 : /**
125 : * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
126 : *
127 : * @rdev: radeon_device pointer
128 : * @ib: IB object to schedule
129 : *
130 : * Schedule an IB in the DMA ring (CIK).
131 : */
132 0 : void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
133 : struct radeon_ib *ib)
134 : {
135 0 : struct radeon_ring *ring = &rdev->ring[ib->ring];
136 0 : u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;
137 :
138 0 : if (rdev->wb.enabled) {
139 0 : u32 next_rptr = ring->wptr + 5;
140 0 : while ((next_rptr & 7) != 4)
141 0 : next_rptr++;
142 0 : next_rptr += 4;
143 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
144 0 : radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
145 0 : radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
146 0 : radeon_ring_write(ring, 1); /* number of DWs to follow */
147 0 : radeon_ring_write(ring, next_rptr);
148 0 : }
149 :
150 : /* IB packet must end on a 8 DW boundary */
151 0 : while ((ring->wptr & 7) != 4)
152 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
153 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
154 0 : radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
155 0 : radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
156 0 : radeon_ring_write(ring, ib->length_dw);
157 :
158 0 : }
159 :
160 : /**
161 : * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
162 : *
163 : * @rdev: radeon_device pointer
164 : * @ridx: radeon ring index
165 : *
166 : * Emit an hdp flush packet on the requested DMA ring.
167 : */
168 0 : static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,
169 : int ridx)
170 : {
171 0 : struct radeon_ring *ring = &rdev->ring[ridx];
172 : u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
173 : SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
174 : u32 ref_and_mask;
175 :
176 0 : if (ridx == R600_RING_TYPE_DMA_INDEX)
177 0 : ref_and_mask = SDMA0;
178 : else
179 : ref_and_mask = SDMA1;
180 :
181 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
182 0 : radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
183 0 : radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
184 0 : radeon_ring_write(ring, ref_and_mask); /* reference */
185 0 : radeon_ring_write(ring, ref_and_mask); /* mask */
186 0 : radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
187 0 : }
188 :
189 : /**
190 : * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
191 : *
192 : * @rdev: radeon_device pointer
193 : * @fence: radeon fence object
194 : *
195 : * Add a DMA fence packet to the ring to write
196 : * the fence seq number and DMA trap packet to generate
197 : * an interrupt if needed (CIK).
198 : */
199 0 : void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
200 : struct radeon_fence *fence)
201 : {
202 0 : struct radeon_ring *ring = &rdev->ring[fence->ring];
203 0 : u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
204 :
205 : /* write the fence */
206 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
207 0 : radeon_ring_write(ring, lower_32_bits(addr));
208 0 : radeon_ring_write(ring, upper_32_bits(addr));
209 0 : radeon_ring_write(ring, fence->seq);
210 : /* generate an interrupt */
211 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
212 : /* flush HDP */
213 0 : cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);
214 0 : }
215 :
216 : /**
217 : * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
218 : *
219 : * @rdev: radeon_device pointer
220 : * @ring: radeon_ring structure holding ring information
221 : * @semaphore: radeon semaphore object
222 : * @emit_wait: wait or signal semaphore
223 : *
224 : * Add a DMA semaphore packet to the ring wait on or signal
225 : * other rings (CIK).
226 : */
227 0 : bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
228 : struct radeon_ring *ring,
229 : struct radeon_semaphore *semaphore,
230 : bool emit_wait)
231 : {
232 0 : u64 addr = semaphore->gpu_addr;
233 0 : u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
234 :
235 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
236 0 : radeon_ring_write(ring, addr & 0xfffffff8);
237 0 : radeon_ring_write(ring, upper_32_bits(addr));
238 :
239 0 : return true;
240 : }
241 :
242 : /**
243 : * cik_sdma_gfx_stop - stop the gfx async dma engines
244 : *
245 : * @rdev: radeon_device pointer
246 : *
247 : * Stop the gfx async dma ring buffers (CIK).
248 : */
249 0 : static void cik_sdma_gfx_stop(struct radeon_device *rdev)
250 : {
251 : u32 rb_cntl, reg_offset;
252 : int i;
253 :
254 0 : if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
255 0 : (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
256 0 : radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
257 :
258 0 : for (i = 0; i < 2; i++) {
259 0 : if (i == 0)
260 0 : reg_offset = SDMA0_REGISTER_OFFSET;
261 : else
262 : reg_offset = SDMA1_REGISTER_OFFSET;
263 0 : rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
264 0 : rb_cntl &= ~SDMA_RB_ENABLE;
265 0 : WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
266 0 : WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
267 : }
268 0 : rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
269 0 : rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
270 :
271 : /* FIXME use something else than big hammer but after few days can not
272 : * seem to find good combination so reset SDMA blocks as it seems we
273 : * do not shut them down properly. This fix hibernation and does not
274 : * affect suspend to ram.
275 : */
276 0 : WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
277 0 : (void)RREG32(SRBM_SOFT_RESET);
278 0 : udelay(50);
279 0 : WREG32(SRBM_SOFT_RESET, 0);
280 0 : (void)RREG32(SRBM_SOFT_RESET);
281 0 : }
282 :
283 : /**
284 : * cik_sdma_rlc_stop - stop the compute async dma engines
285 : *
286 : * @rdev: radeon_device pointer
287 : *
288 : * Stop the compute async dma queues (CIK).
289 : */
290 0 : static void cik_sdma_rlc_stop(struct radeon_device *rdev)
291 : {
292 : /* XXX todo */
293 0 : }
294 :
295 : /**
296 : * cik_sdma_ctx_switch_enable - enable/disable sdma engine preemption
297 : *
298 : * @rdev: radeon_device pointer
299 : * @enable: enable/disable preemption.
300 : *
301 : * Halt or unhalt the async dma engines (CIK).
302 : */
303 0 : static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable)
304 : {
305 : uint32_t reg_offset, value;
306 : int i;
307 :
308 0 : for (i = 0; i < 2; i++) {
309 0 : if (i == 0)
310 0 : reg_offset = SDMA0_REGISTER_OFFSET;
311 : else
312 : reg_offset = SDMA1_REGISTER_OFFSET;
313 0 : value = RREG32(SDMA0_CNTL + reg_offset);
314 0 : if (enable)
315 0 : value |= AUTO_CTXSW_ENABLE;
316 : else
317 0 : value &= ~AUTO_CTXSW_ENABLE;
318 0 : WREG32(SDMA0_CNTL + reg_offset, value);
319 : }
320 0 : }
321 :
322 : /**
323 : * cik_sdma_enable - stop the async dma engines
324 : *
325 : * @rdev: radeon_device pointer
326 : * @enable: enable/disable the DMA MEs.
327 : *
328 : * Halt or unhalt the async dma engines (CIK).
329 : */
330 0 : void cik_sdma_enable(struct radeon_device *rdev, bool enable)
331 : {
332 : u32 me_cntl, reg_offset;
333 : int i;
334 :
335 0 : if (enable == false) {
336 0 : cik_sdma_gfx_stop(rdev);
337 0 : cik_sdma_rlc_stop(rdev);
338 0 : }
339 :
340 0 : for (i = 0; i < 2; i++) {
341 0 : if (i == 0)
342 0 : reg_offset = SDMA0_REGISTER_OFFSET;
343 : else
344 : reg_offset = SDMA1_REGISTER_OFFSET;
345 0 : me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
346 0 : if (enable)
347 0 : me_cntl &= ~SDMA_HALT;
348 : else
349 0 : me_cntl |= SDMA_HALT;
350 0 : WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
351 : }
352 :
353 0 : cik_sdma_ctx_switch_enable(rdev, enable);
354 0 : }
355 :
356 : /**
357 : * cik_sdma_gfx_resume - setup and start the async dma engines
358 : *
359 : * @rdev: radeon_device pointer
360 : *
361 : * Set up the gfx DMA ring buffers and enable them (CIK).
362 : * Returns 0 for success, error for failure.
363 : */
364 0 : static int cik_sdma_gfx_resume(struct radeon_device *rdev)
365 : {
366 : struct radeon_ring *ring;
367 : u32 rb_cntl, ib_cntl;
368 : u32 rb_bufsz;
369 : u32 reg_offset, wb_offset;
370 : int i, r;
371 :
372 0 : for (i = 0; i < 2; i++) {
373 0 : if (i == 0) {
374 0 : ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
375 : reg_offset = SDMA0_REGISTER_OFFSET;
376 : wb_offset = R600_WB_DMA_RPTR_OFFSET;
377 0 : } else {
378 0 : ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
379 : reg_offset = SDMA1_REGISTER_OFFSET;
380 : wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
381 : }
382 :
383 0 : WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
384 0 : WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
385 :
386 : /* Set ring buffer size in dwords */
387 0 : rb_bufsz = order_base_2(ring->ring_size / 4);
388 0 : rb_cntl = rb_bufsz << 1;
389 : #ifdef __BIG_ENDIAN
390 : rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
391 : #endif
392 0 : WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
393 :
394 : /* Initialize the ring buffer's read and write pointers */
395 0 : WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
396 0 : WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
397 :
398 : /* set the wb address whether it's enabled or not */
399 0 : WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
400 : upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
401 0 : WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
402 : ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
403 :
404 0 : if (rdev->wb.enabled)
405 0 : rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;
406 :
407 0 : WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
408 0 : WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
409 :
410 0 : ring->wptr = 0;
411 0 : WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
412 :
413 : /* enable DMA RB */
414 0 : WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
415 :
416 : ib_cntl = SDMA_IB_ENABLE;
417 : #ifdef __BIG_ENDIAN
418 : ib_cntl |= SDMA_IB_SWAP_ENABLE;
419 : #endif
420 : /* enable DMA IBs */
421 0 : WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
422 :
423 0 : ring->ready = true;
424 :
425 0 : r = radeon_ring_test(rdev, ring->idx, ring);
426 0 : if (r) {
427 0 : ring->ready = false;
428 0 : return r;
429 : }
430 : }
431 :
432 0 : if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
433 0 : (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
434 0 : radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
435 :
436 0 : return 0;
437 0 : }
438 :
439 : /**
440 : * cik_sdma_rlc_resume - setup and start the async dma engines
441 : *
442 : * @rdev: radeon_device pointer
443 : *
444 : * Set up the compute DMA queues and enable them (CIK).
445 : * Returns 0 for success, error for failure.
446 : */
447 0 : static int cik_sdma_rlc_resume(struct radeon_device *rdev)
448 : {
449 : /* XXX todo */
450 0 : return 0;
451 : }
452 :
453 : /**
454 : * cik_sdma_load_microcode - load the sDMA ME ucode
455 : *
456 : * @rdev: radeon_device pointer
457 : *
458 : * Loads the sDMA0/1 ucode.
459 : * Returns 0 for success, -EINVAL if the ucode is not available.
460 : */
461 0 : static int cik_sdma_load_microcode(struct radeon_device *rdev)
462 : {
463 : int i;
464 :
465 0 : if (!rdev->sdma_fw)
466 0 : return -EINVAL;
467 :
468 : /* halt the MEs */
469 0 : cik_sdma_enable(rdev, false);
470 :
471 0 : if (rdev->new_fw) {
472 : const struct sdma_firmware_header_v1_0 *hdr =
473 0 : (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data;
474 : const __le32 *fw_data;
475 : u32 fw_size;
476 :
477 0 : radeon_ucode_print_sdma_hdr(&hdr->header);
478 :
479 : /* sdma0 */
480 0 : fw_data = (const __le32 *)
481 0 : (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
482 0 : fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
483 0 : WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
484 0 : for (i = 0; i < fw_size; i++)
485 0 : WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
486 0 : WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
487 :
488 : /* sdma1 */
489 0 : fw_data = (const __le32 *)
490 0 : (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
491 0 : fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
492 0 : WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
493 0 : for (i = 0; i < fw_size; i++)
494 0 : WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));
495 0 : WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
496 0 : } else {
497 : const __be32 *fw_data;
498 :
499 : /* sdma0 */
500 0 : fw_data = (const __be32 *)rdev->sdma_fw->data;
501 0 : WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
502 0 : for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
503 0 : WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
504 0 : WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
505 :
506 : /* sdma1 */
507 0 : fw_data = (const __be32 *)rdev->sdma_fw->data;
508 0 : WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
509 0 : for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
510 0 : WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
511 0 : WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
512 : }
513 :
514 0 : WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
515 0 : WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
516 0 : return 0;
517 0 : }
518 :
519 : /**
520 : * cik_sdma_resume - setup and start the async dma engines
521 : *
522 : * @rdev: radeon_device pointer
523 : *
524 : * Set up the DMA engines and enable them (CIK).
525 : * Returns 0 for success, error for failure.
526 : */
527 0 : int cik_sdma_resume(struct radeon_device *rdev)
528 : {
529 : int r;
530 :
531 0 : r = cik_sdma_load_microcode(rdev);
532 0 : if (r)
533 0 : return r;
534 :
535 : /* unhalt the MEs */
536 0 : cik_sdma_enable(rdev, true);
537 :
538 : /* start the gfx rings and rlc compute queues */
539 0 : r = cik_sdma_gfx_resume(rdev);
540 0 : if (r)
541 0 : return r;
542 0 : r = cik_sdma_rlc_resume(rdev);
543 0 : if (r)
544 0 : return r;
545 :
546 0 : return 0;
547 0 : }
548 :
549 : /**
550 : * cik_sdma_fini - tear down the async dma engines
551 : *
552 : * @rdev: radeon_device pointer
553 : *
554 : * Stop the async dma engines and free the rings (CIK).
555 : */
556 0 : void cik_sdma_fini(struct radeon_device *rdev)
557 : {
558 : /* halt the MEs */
559 0 : cik_sdma_enable(rdev, false);
560 0 : radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
561 0 : radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
562 : /* XXX - compute dma queue tear down */
563 0 : }
564 :
565 : /**
566 : * cik_copy_dma - copy pages using the DMA engine
567 : *
568 : * @rdev: radeon_device pointer
569 : * @src_offset: src GPU address
570 : * @dst_offset: dst GPU address
571 : * @num_gpu_pages: number of GPU pages to xfer
572 : * @resv: reservation object to sync to
573 : *
574 : * Copy GPU paging using the DMA engine (CIK).
575 : * Used by the radeon ttm implementation to move pages if
576 : * registered as the asic copy callback.
577 : */
578 0 : struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
579 : uint64_t src_offset, uint64_t dst_offset,
580 : unsigned num_gpu_pages,
581 : struct reservation_object *resv)
582 : {
583 0 : struct radeon_fence *fence;
584 0 : struct radeon_sync sync;
585 0 : int ring_index = rdev->asic->copy.dma_ring_index;
586 0 : struct radeon_ring *ring = &rdev->ring[ring_index];
587 : u32 size_in_bytes, cur_size_in_bytes;
588 : int i, num_loops;
589 : int r = 0;
590 :
591 0 : radeon_sync_create(&sync);
592 :
593 0 : size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
594 0 : num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
595 0 : r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
596 0 : if (r) {
597 0 : DRM_ERROR("radeon: moving bo (%d).\n", r);
598 0 : radeon_sync_free(rdev, &sync, NULL);
599 0 : return ERR_PTR(r);
600 : }
601 :
602 0 : radeon_sync_resv(rdev, &sync, resv, false);
603 0 : radeon_sync_rings(rdev, &sync, ring->idx);
604 :
605 0 : for (i = 0; i < num_loops; i++) {
606 : cur_size_in_bytes = size_in_bytes;
607 0 : if (cur_size_in_bytes > 0x1fffff)
608 : cur_size_in_bytes = 0x1fffff;
609 0 : size_in_bytes -= cur_size_in_bytes;
610 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
611 0 : radeon_ring_write(ring, cur_size_in_bytes);
612 0 : radeon_ring_write(ring, 0); /* src/dst endian swap */
613 0 : radeon_ring_write(ring, lower_32_bits(src_offset));
614 0 : radeon_ring_write(ring, upper_32_bits(src_offset));
615 0 : radeon_ring_write(ring, lower_32_bits(dst_offset));
616 0 : radeon_ring_write(ring, upper_32_bits(dst_offset));
617 0 : src_offset += cur_size_in_bytes;
618 0 : dst_offset += cur_size_in_bytes;
619 : }
620 :
621 0 : r = radeon_fence_emit(rdev, &fence, ring->idx);
622 0 : if (r) {
623 0 : radeon_ring_unlock_undo(rdev, ring);
624 0 : radeon_sync_free(rdev, &sync, NULL);
625 0 : return ERR_PTR(r);
626 : }
627 :
628 0 : radeon_ring_unlock_commit(rdev, ring, false);
629 0 : radeon_sync_free(rdev, &sync, fence);
630 :
631 0 : return fence;
632 0 : }
633 :
634 : /**
635 : * cik_sdma_ring_test - simple async dma engine test
636 : *
637 : * @rdev: radeon_device pointer
638 : * @ring: radeon_ring structure holding ring information
639 : *
640 : * Test the DMA engine by writing using it to write an
641 : * value to memory. (CIK).
642 : * Returns 0 for success, error for failure.
643 : */
644 0 : int cik_sdma_ring_test(struct radeon_device *rdev,
645 : struct radeon_ring *ring)
646 : {
647 : unsigned i;
648 : int r;
649 : unsigned index;
650 : u32 tmp;
651 : u64 gpu_addr;
652 :
653 0 : if (ring->idx == R600_RING_TYPE_DMA_INDEX)
654 0 : index = R600_WB_DMA_RING_TEST_OFFSET;
655 : else
656 : index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
657 :
658 0 : gpu_addr = rdev->wb.gpu_addr + index;
659 :
660 : tmp = 0xCAFEDEAD;
661 0 : rdev->wb.wb[index/4] = cpu_to_le32(tmp);
662 :
663 0 : r = radeon_ring_lock(rdev, ring, 5);
664 0 : if (r) {
665 0 : DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
666 0 : return r;
667 : }
668 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
669 0 : radeon_ring_write(ring, lower_32_bits(gpu_addr));
670 0 : radeon_ring_write(ring, upper_32_bits(gpu_addr));
671 0 : radeon_ring_write(ring, 1); /* number of DWs to follow */
672 0 : radeon_ring_write(ring, 0xDEADBEEF);
673 0 : radeon_ring_unlock_commit(rdev, ring, false);
674 :
675 0 : for (i = 0; i < rdev->usec_timeout; i++) {
676 0 : tmp = le32_to_cpu(rdev->wb.wb[index/4]);
677 0 : if (tmp == 0xDEADBEEF)
678 : break;
679 0 : DRM_UDELAY(1);
680 : }
681 :
682 0 : if (i < rdev->usec_timeout) {
683 : DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
684 : } else {
685 0 : DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
686 : ring->idx, tmp);
687 : r = -EINVAL;
688 : }
689 0 : return r;
690 0 : }
691 :
692 : /**
693 : * cik_sdma_ib_test - test an IB on the DMA engine
694 : *
695 : * @rdev: radeon_device pointer
696 : * @ring: radeon_ring structure holding ring information
697 : *
698 : * Test a simple IB in the DMA ring (CIK).
699 : * Returns 0 on success, error on failure.
700 : */
701 0 : int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
702 : {
703 0 : struct radeon_ib ib;
704 : unsigned i;
705 : unsigned index;
706 : int r;
707 : u32 tmp = 0;
708 : u64 gpu_addr;
709 :
710 0 : if (ring->idx == R600_RING_TYPE_DMA_INDEX)
711 0 : index = R600_WB_DMA_RING_TEST_OFFSET;
712 : else
713 : index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
714 :
715 0 : gpu_addr = rdev->wb.gpu_addr + index;
716 :
717 : tmp = 0xCAFEDEAD;
718 0 : rdev->wb.wb[index/4] = cpu_to_le32(tmp);
719 :
720 0 : r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
721 0 : if (r) {
722 0 : DRM_ERROR("radeon: failed to get ib (%d).\n", r);
723 0 : return r;
724 : }
725 :
726 0 : ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
727 0 : ib.ptr[1] = lower_32_bits(gpu_addr);
728 0 : ib.ptr[2] = upper_32_bits(gpu_addr);
729 0 : ib.ptr[3] = 1;
730 0 : ib.ptr[4] = 0xDEADBEEF;
731 0 : ib.length_dw = 5;
732 :
733 0 : r = radeon_ib_schedule(rdev, &ib, NULL, false);
734 0 : if (r) {
735 0 : radeon_ib_free(rdev, &ib);
736 0 : DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
737 0 : return r;
738 : }
739 0 : r = radeon_fence_wait(ib.fence, false);
740 0 : if (r) {
741 0 : DRM_ERROR("radeon: fence wait failed (%d).\n", r);
742 0 : return r;
743 : }
744 0 : for (i = 0; i < rdev->usec_timeout; i++) {
745 0 : tmp = le32_to_cpu(rdev->wb.wb[index/4]);
746 0 : if (tmp == 0xDEADBEEF)
747 : break;
748 0 : DRM_UDELAY(1);
749 : }
750 0 : if (i < rdev->usec_timeout) {
751 : DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
752 : } else {
753 0 : DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
754 : r = -EINVAL;
755 : }
756 0 : radeon_ib_free(rdev, &ib);
757 0 : return r;
758 0 : }
759 :
760 : /**
761 : * cik_sdma_is_lockup - Check if the DMA engine is locked up
762 : *
763 : * @rdev: radeon_device pointer
764 : * @ring: radeon_ring structure holding ring information
765 : *
766 : * Check if the async DMA engine is locked up (CIK).
767 : * Returns true if the engine appears to be locked up, false if not.
768 : */
769 0 : bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
770 : {
771 0 : u32 reset_mask = cik_gpu_check_soft_reset(rdev);
772 : u32 mask;
773 :
774 0 : if (ring->idx == R600_RING_TYPE_DMA_INDEX)
775 0 : mask = RADEON_RESET_DMA;
776 : else
777 : mask = RADEON_RESET_DMA1;
778 :
779 0 : if (!(reset_mask & mask)) {
780 0 : radeon_ring_lockup_update(rdev, ring);
781 0 : return false;
782 : }
783 0 : return radeon_ring_test_lockup(rdev, ring);
784 0 : }
785 :
786 : /**
787 : * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
788 : *
789 : * @rdev: radeon_device pointer
790 : * @ib: indirect buffer to fill with commands
791 : * @pe: addr of the page entry
792 : * @src: src addr to copy from
793 : * @count: number of page entries to update
794 : *
795 : * Update PTEs by copying them from the GART using sDMA (CIK).
796 : */
797 0 : void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
798 : struct radeon_ib *ib,
799 : uint64_t pe, uint64_t src,
800 : unsigned count)
801 : {
802 0 : while (count) {
803 0 : unsigned bytes = count * 8;
804 0 : if (bytes > 0x1FFFF8)
805 : bytes = 0x1FFFF8;
806 :
807 0 : ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
808 : SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
809 0 : ib->ptr[ib->length_dw++] = bytes;
810 0 : ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
811 0 : ib->ptr[ib->length_dw++] = lower_32_bits(src);
812 0 : ib->ptr[ib->length_dw++] = upper_32_bits(src);
813 0 : ib->ptr[ib->length_dw++] = lower_32_bits(pe);
814 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
815 :
816 0 : pe += bytes;
817 0 : src += bytes;
818 0 : count -= bytes / 8;
819 : }
820 0 : }
821 :
822 : /**
823 : * cik_sdma_vm_write_pages - update PTEs by writing them manually
824 : *
825 : * @rdev: radeon_device pointer
826 : * @ib: indirect buffer to fill with commands
827 : * @pe: addr of the page entry
828 : * @addr: dst addr to write into pe
829 : * @count: number of page entries to update
830 : * @incr: increase next addr by incr bytes
831 : * @flags: access flags
832 : *
833 : * Update PTEs by writing them manually using sDMA (CIK).
834 : */
835 0 : void cik_sdma_vm_write_pages(struct radeon_device *rdev,
836 : struct radeon_ib *ib,
837 : uint64_t pe,
838 : uint64_t addr, unsigned count,
839 : uint32_t incr, uint32_t flags)
840 : {
841 : uint64_t value;
842 : unsigned ndw;
843 :
844 0 : while (count) {
845 0 : ndw = count * 2;
846 0 : if (ndw > 0xFFFFE)
847 : ndw = 0xFFFFE;
848 :
849 : /* for non-physically contiguous pages (system) */
850 0 : ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
851 : SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
852 0 : ib->ptr[ib->length_dw++] = pe;
853 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
854 0 : ib->ptr[ib->length_dw++] = ndw;
855 0 : for (; ndw > 0; ndw -= 2, --count, pe += 8) {
856 0 : if (flags & R600_PTE_SYSTEM) {
857 0 : value = radeon_vm_map_gart(rdev, addr);
858 0 : } else if (flags & R600_PTE_VALID) {
859 : value = addr;
860 0 : } else {
861 : value = 0;
862 : }
863 0 : addr += incr;
864 0 : value |= flags;
865 0 : ib->ptr[ib->length_dw++] = value;
866 0 : ib->ptr[ib->length_dw++] = upper_32_bits(value);
867 : }
868 : }
869 0 : }
870 :
871 : /**
872 : * cik_sdma_vm_set_pages - update the page tables using sDMA
873 : *
874 : * @rdev: radeon_device pointer
875 : * @ib: indirect buffer to fill with commands
876 : * @pe: addr of the page entry
877 : * @addr: dst addr to write into pe
878 : * @count: number of page entries to update
879 : * @incr: increase next addr by incr bytes
880 : * @flags: access flags
881 : *
882 : * Update the page tables using sDMA (CIK).
883 : */
884 0 : void cik_sdma_vm_set_pages(struct radeon_device *rdev,
885 : struct radeon_ib *ib,
886 : uint64_t pe,
887 : uint64_t addr, unsigned count,
888 : uint32_t incr, uint32_t flags)
889 : {
890 : uint64_t value;
891 : unsigned ndw;
892 :
893 0 : while (count) {
894 : ndw = count;
895 0 : if (ndw > 0x7FFFF)
896 : ndw = 0x7FFFF;
897 :
898 0 : if (flags & R600_PTE_VALID)
899 0 : value = addr;
900 : else
901 : value = 0;
902 :
903 : /* for physically contiguous pages (vram) */
904 0 : ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
905 0 : ib->ptr[ib->length_dw++] = pe; /* dst addr */
906 0 : ib->ptr[ib->length_dw++] = upper_32_bits(pe);
907 0 : ib->ptr[ib->length_dw++] = flags; /* mask */
908 0 : ib->ptr[ib->length_dw++] = 0;
909 0 : ib->ptr[ib->length_dw++] = value; /* value */
910 0 : ib->ptr[ib->length_dw++] = upper_32_bits(value);
911 0 : ib->ptr[ib->length_dw++] = incr; /* increment size */
912 0 : ib->ptr[ib->length_dw++] = 0;
913 0 : ib->ptr[ib->length_dw++] = ndw; /* number of entries */
914 :
915 0 : pe += ndw * 8;
916 0 : addr += ndw * incr;
917 0 : count -= ndw;
918 : }
919 0 : }
920 :
921 : /**
922 : * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
923 : *
924 : * @ib: indirect buffer to fill with padding
925 : *
926 : */
927 0 : void cik_sdma_vm_pad_ib(struct radeon_ib *ib)
928 : {
929 0 : while (ib->length_dw & 0x7)
930 0 : ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
931 0 : }
932 :
933 : /**
934 : * cik_dma_vm_flush - cik vm flush using sDMA
935 : *
936 : * @rdev: radeon_device pointer
937 : *
938 : * Update the page table base and flush the VM TLB
939 : * using sDMA (CIK).
940 : */
941 0 : void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
942 : unsigned vm_id, uint64_t pd_addr)
943 : {
944 : u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
945 : SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
946 :
947 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
948 0 : if (vm_id < 8) {
949 0 : radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
950 0 : } else {
951 0 : radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
952 : }
953 0 : radeon_ring_write(ring, pd_addr >> 12);
954 :
955 : /* update SH_MEM_* regs */
956 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
957 0 : radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
958 0 : radeon_ring_write(ring, VMID(vm_id));
959 :
960 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
961 0 : radeon_ring_write(ring, SH_MEM_BASES >> 2);
962 0 : radeon_ring_write(ring, 0);
963 :
964 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
965 0 : radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
966 0 : radeon_ring_write(ring, 0);
967 :
968 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
969 0 : radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
970 0 : radeon_ring_write(ring, 1);
971 :
972 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
973 0 : radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
974 0 : radeon_ring_write(ring, 0);
975 :
976 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
977 0 : radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
978 0 : radeon_ring_write(ring, VMID(0));
979 :
980 : /* flush HDP */
981 0 : cik_sdma_hdp_flush_ring_emit(rdev, ring->idx);
982 :
983 : /* flush TLB */
984 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
985 0 : radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
986 0 : radeon_ring_write(ring, 1 << vm_id);
987 :
988 0 : radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
989 0 : radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
990 0 : radeon_ring_write(ring, 0);
991 0 : radeon_ring_write(ring, 0); /* reference */
992 0 : radeon_ring_write(ring, 0); /* mask */
993 0 : radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
994 0 : }
995 :
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