Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #include <dev/pci/drm/drmP.h>
29 : #include <dev/pci/drm/radeon_drm.h>
30 : #include "radeon_reg.h"
31 : #include "radeon.h"
32 : #include "radeon_asic.h"
33 : #include "r100d.h"
34 : #include "rs100d.h"
35 : #include "rv200d.h"
36 : #include "rv250d.h"
37 : #include "atom.h"
38 :
39 : #include "r100_reg_safe.h"
40 : #include "rn50_reg_safe.h"
41 :
42 : /* Firmware Names */
43 : #define FIRMWARE_R100 "radeon/R100_cp.bin"
44 : #define FIRMWARE_R200 "radeon/R200_cp.bin"
45 : #define FIRMWARE_R300 "radeon/R300_cp.bin"
46 : #define FIRMWARE_R420 "radeon/R420_cp.bin"
47 : #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
48 : #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
49 : #define FIRMWARE_R520 "radeon/R520_cp.bin"
50 :
51 : MODULE_FIRMWARE(FIRMWARE_R100);
52 : MODULE_FIRMWARE(FIRMWARE_R200);
53 : MODULE_FIRMWARE(FIRMWARE_R300);
54 : MODULE_FIRMWARE(FIRMWARE_R420);
55 : MODULE_FIRMWARE(FIRMWARE_RS690);
56 : MODULE_FIRMWARE(FIRMWARE_RS600);
57 : MODULE_FIRMWARE(FIRMWARE_R520);
58 :
59 : #include "r100_track.h"
60 :
61 : /* This files gather functions specifics to:
62 : * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
63 : * and others in some cases.
64 : */
65 :
66 0 : static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
67 : {
68 0 : if (crtc == 0) {
69 0 : if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
70 0 : return true;
71 : else
72 0 : return false;
73 : } else {
74 0 : if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
75 0 : return true;
76 : else
77 0 : return false;
78 : }
79 0 : }
80 :
81 0 : static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
82 : {
83 : u32 vline1, vline2;
84 :
85 0 : if (crtc == 0) {
86 0 : vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
87 0 : vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
88 0 : } else {
89 0 : vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
90 0 : vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
91 : }
92 0 : if (vline1 != vline2)
93 0 : return true;
94 : else
95 0 : return false;
96 0 : }
97 :
98 : /**
99 : * r100_wait_for_vblank - vblank wait asic callback.
100 : *
101 : * @rdev: radeon_device pointer
102 : * @crtc: crtc to wait for vblank on
103 : *
104 : * Wait for vblank on the requested crtc (r1xx-r4xx).
105 : */
106 0 : void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
107 : {
108 : unsigned i = 0;
109 :
110 0 : if (crtc >= rdev->num_crtc)
111 0 : return;
112 :
113 0 : if (crtc == 0) {
114 0 : if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
115 0 : return;
116 : } else {
117 0 : if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
118 0 : return;
119 : }
120 :
121 : /* depending on when we hit vblank, we may be close to active; if so,
122 : * wait for another frame.
123 : */
124 0 : while (r100_is_in_vblank(rdev, crtc)) {
125 0 : if (i++ % 100 == 0) {
126 0 : if (!r100_is_counter_moving(rdev, crtc))
127 : break;
128 : }
129 : }
130 :
131 0 : while (!r100_is_in_vblank(rdev, crtc)) {
132 0 : if (i++ % 100 == 0) {
133 0 : if (!r100_is_counter_moving(rdev, crtc))
134 : break;
135 : }
136 : }
137 0 : }
138 :
139 : /**
140 : * r100_page_flip - pageflip callback.
141 : *
142 : * @rdev: radeon_device pointer
143 : * @crtc_id: crtc to cleanup pageflip on
144 : * @crtc_base: new address of the crtc (GPU MC address)
145 : *
146 : * Does the actual pageflip (r1xx-r4xx).
147 : * During vblank we take the crtc lock and wait for the update_pending
148 : * bit to go high, when it does, we release the lock, and allow the
149 : * double buffered update to take place.
150 : */
151 0 : void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
152 : {
153 0 : struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
154 0 : u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
155 : int i;
156 :
157 : /* Lock the graphics update lock */
158 : /* update the scanout addresses */
159 0 : WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
160 :
161 : /* Wait for update_pending to go high. */
162 0 : for (i = 0; i < rdev->usec_timeout; i++) {
163 0 : if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
164 : break;
165 0 : udelay(1);
166 : }
167 : DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
168 :
169 : /* Unlock the lock, so double-buffering can take place inside vblank */
170 0 : tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
171 0 : WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
172 :
173 0 : }
174 :
175 : /**
176 : * r100_page_flip_pending - check if page flip is still pending
177 : *
178 : * @rdev: radeon_device pointer
179 : * @crtc_id: crtc to check
180 : *
181 : * Check if the last pagefilp is still pending (r1xx-r4xx).
182 : * Returns the current update pending status.
183 : */
184 0 : bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
185 : {
186 0 : struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
187 :
188 : /* Return current update_pending status: */
189 0 : return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
190 : RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
191 : }
192 :
193 : /**
194 : * r100_pm_get_dynpm_state - look up dynpm power state callback.
195 : *
196 : * @rdev: radeon_device pointer
197 : *
198 : * Look up the optimal power state based on the
199 : * current state of the GPU (r1xx-r5xx).
200 : * Used for dynpm only.
201 : */
202 0 : void r100_pm_get_dynpm_state(struct radeon_device *rdev)
203 : {
204 : int i;
205 0 : rdev->pm.dynpm_can_upclock = true;
206 0 : rdev->pm.dynpm_can_downclock = true;
207 :
208 0 : switch (rdev->pm.dynpm_planned_action) {
209 : case DYNPM_ACTION_MINIMUM:
210 0 : rdev->pm.requested_power_state_index = 0;
211 0 : rdev->pm.dynpm_can_downclock = false;
212 0 : break;
213 : case DYNPM_ACTION_DOWNCLOCK:
214 0 : if (rdev->pm.current_power_state_index == 0) {
215 0 : rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
216 0 : rdev->pm.dynpm_can_downclock = false;
217 0 : } else {
218 0 : if (rdev->pm.active_crtc_count > 1) {
219 0 : for (i = 0; i < rdev->pm.num_power_states; i++) {
220 0 : if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
221 : continue;
222 0 : else if (i >= rdev->pm.current_power_state_index) {
223 0 : rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
224 0 : break;
225 : } else {
226 0 : rdev->pm.requested_power_state_index = i;
227 0 : break;
228 : }
229 : }
230 : } else
231 0 : rdev->pm.requested_power_state_index =
232 0 : rdev->pm.current_power_state_index - 1;
233 : }
234 : /* don't use the power state if crtcs are active and no display flag is set */
235 0 : if ((rdev->pm.active_crtc_count > 0) &&
236 0 : (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
237 : RADEON_PM_MODE_NO_DISPLAY)) {
238 0 : rdev->pm.requested_power_state_index++;
239 0 : }
240 : break;
241 : case DYNPM_ACTION_UPCLOCK:
242 0 : if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
243 0 : rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
244 0 : rdev->pm.dynpm_can_upclock = false;
245 0 : } else {
246 0 : if (rdev->pm.active_crtc_count > 1) {
247 0 : for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
248 0 : if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
249 : continue;
250 0 : else if (i <= rdev->pm.current_power_state_index) {
251 0 : rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
252 0 : break;
253 : } else {
254 0 : rdev->pm.requested_power_state_index = i;
255 0 : break;
256 : }
257 : }
258 : } else
259 0 : rdev->pm.requested_power_state_index =
260 0 : rdev->pm.current_power_state_index + 1;
261 : }
262 : break;
263 : case DYNPM_ACTION_DEFAULT:
264 0 : rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
265 0 : rdev->pm.dynpm_can_upclock = false;
266 0 : break;
267 : case DYNPM_ACTION_NONE:
268 : default:
269 0 : DRM_ERROR("Requested mode for not defined action\n");
270 0 : return;
271 : }
272 : /* only one clock mode per power state */
273 0 : rdev->pm.requested_clock_mode_index = 0;
274 :
275 : DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
276 : rdev->pm.power_state[rdev->pm.requested_power_state_index].
277 : clock_info[rdev->pm.requested_clock_mode_index].sclk,
278 : rdev->pm.power_state[rdev->pm.requested_power_state_index].
279 : clock_info[rdev->pm.requested_clock_mode_index].mclk,
280 : rdev->pm.power_state[rdev->pm.requested_power_state_index].
281 : pcie_lanes);
282 0 : }
283 :
284 : /**
285 : * r100_pm_init_profile - Initialize power profiles callback.
286 : *
287 : * @rdev: radeon_device pointer
288 : *
289 : * Initialize the power states used in profile mode
290 : * (r1xx-r3xx).
291 : * Used for profile mode only.
292 : */
293 0 : void r100_pm_init_profile(struct radeon_device *rdev)
294 : {
295 : /* default */
296 0 : rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
297 0 : rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
298 0 : rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
299 0 : rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
300 : /* low sh */
301 0 : rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
302 0 : rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
303 0 : rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
304 0 : rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
305 : /* mid sh */
306 0 : rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
307 0 : rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
308 0 : rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
309 0 : rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
310 : /* high sh */
311 0 : rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
312 0 : rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
313 0 : rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
314 0 : rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
315 : /* low mh */
316 0 : rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
317 0 : rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
318 0 : rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
319 0 : rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
320 : /* mid mh */
321 0 : rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
322 0 : rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 0 : rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
324 0 : rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
325 : /* high mh */
326 0 : rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
327 0 : rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
328 0 : rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
329 0 : rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
330 0 : }
331 :
332 : /**
333 : * r100_pm_misc - set additional pm hw parameters callback.
334 : *
335 : * @rdev: radeon_device pointer
336 : *
337 : * Set non-clock parameters associated with a power state
338 : * (voltage, pcie lanes, etc.) (r1xx-r4xx).
339 : */
340 0 : void r100_pm_misc(struct radeon_device *rdev)
341 : {
342 0 : int requested_index = rdev->pm.requested_power_state_index;
343 0 : struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
344 0 : struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
345 : u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
346 :
347 0 : if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
348 0 : if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
349 : tmp = RREG32(voltage->gpio.reg);
350 0 : if (voltage->active_high)
351 0 : tmp |= voltage->gpio.mask;
352 : else
353 0 : tmp &= ~(voltage->gpio.mask);
354 0 : WREG32(voltage->gpio.reg, tmp);
355 0 : if (voltage->delay)
356 0 : udelay(voltage->delay);
357 : } else {
358 : tmp = RREG32(voltage->gpio.reg);
359 0 : if (voltage->active_high)
360 0 : tmp &= ~voltage->gpio.mask;
361 : else
362 0 : tmp |= voltage->gpio.mask;
363 0 : WREG32(voltage->gpio.reg, tmp);
364 0 : if (voltage->delay)
365 0 : udelay(voltage->delay);
366 : }
367 : }
368 :
369 0 : sclk_cntl = RREG32_PLL(SCLK_CNTL);
370 0 : sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
371 0 : sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
372 0 : sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
373 0 : sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
374 0 : if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
375 0 : sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
376 0 : if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
377 0 : sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
378 : else
379 0 : sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
380 0 : if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
381 0 : sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
382 0 : else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
383 0 : sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
384 : } else
385 0 : sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
386 :
387 0 : if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
388 0 : sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
389 0 : if (voltage->delay) {
390 0 : sclk_more_cntl |= VOLTAGE_DROP_SYNC;
391 0 : switch (voltage->delay) {
392 : case 33:
393 : sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
394 0 : break;
395 : case 66:
396 0 : sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
397 0 : break;
398 : case 99:
399 0 : sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
400 0 : break;
401 : case 132:
402 0 : sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
403 0 : break;
404 : }
405 : } else
406 0 : sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
407 : } else
408 0 : sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
409 :
410 0 : if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
411 0 : sclk_cntl &= ~FORCE_HDP;
412 : else
413 0 : sclk_cntl |= FORCE_HDP;
414 :
415 0 : WREG32_PLL(SCLK_CNTL, sclk_cntl);
416 0 : WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
417 0 : WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
418 :
419 : /* set pcie lanes */
420 0 : if ((rdev->flags & RADEON_IS_PCIE) &&
421 0 : !(rdev->flags & RADEON_IS_IGP) &&
422 0 : rdev->asic->pm.set_pcie_lanes &&
423 0 : (ps->pcie_lanes !=
424 0 : rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
425 0 : radeon_set_pcie_lanes(rdev,
426 : ps->pcie_lanes);
427 : DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
428 0 : }
429 0 : }
430 :
431 : /**
432 : * r100_pm_prepare - pre-power state change callback.
433 : *
434 : * @rdev: radeon_device pointer
435 : *
436 : * Prepare for a power state change (r1xx-r4xx).
437 : */
438 0 : void r100_pm_prepare(struct radeon_device *rdev)
439 : {
440 0 : struct drm_device *ddev = rdev->ddev;
441 : struct drm_crtc *crtc;
442 : struct radeon_crtc *radeon_crtc;
443 : u32 tmp;
444 :
445 : /* disable any active CRTCs */
446 0 : list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
447 0 : radeon_crtc = to_radeon_crtc(crtc);
448 0 : if (radeon_crtc->enabled) {
449 0 : if (radeon_crtc->crtc_id) {
450 0 : tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
451 0 : tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
452 0 : WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
453 0 : } else {
454 0 : tmp = RREG32(RADEON_CRTC_GEN_CNTL);
455 0 : tmp |= RADEON_CRTC_DISP_REQ_EN_B;
456 0 : WREG32(RADEON_CRTC_GEN_CNTL, tmp);
457 : }
458 : }
459 : }
460 0 : }
461 :
462 : /**
463 : * r100_pm_finish - post-power state change callback.
464 : *
465 : * @rdev: radeon_device pointer
466 : *
467 : * Clean up after a power state change (r1xx-r4xx).
468 : */
469 0 : void r100_pm_finish(struct radeon_device *rdev)
470 : {
471 0 : struct drm_device *ddev = rdev->ddev;
472 : struct drm_crtc *crtc;
473 : struct radeon_crtc *radeon_crtc;
474 : u32 tmp;
475 :
476 : /* enable any active CRTCs */
477 0 : list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
478 0 : radeon_crtc = to_radeon_crtc(crtc);
479 0 : if (radeon_crtc->enabled) {
480 0 : if (radeon_crtc->crtc_id) {
481 0 : tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
482 0 : tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
483 0 : WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
484 0 : } else {
485 0 : tmp = RREG32(RADEON_CRTC_GEN_CNTL);
486 0 : tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
487 0 : WREG32(RADEON_CRTC_GEN_CNTL, tmp);
488 : }
489 : }
490 : }
491 0 : }
492 :
493 : /**
494 : * r100_gui_idle - gui idle callback.
495 : *
496 : * @rdev: radeon_device pointer
497 : *
498 : * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
499 : * Returns true if idle, false if not.
500 : */
501 0 : bool r100_gui_idle(struct radeon_device *rdev)
502 : {
503 0 : if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
504 0 : return false;
505 : else
506 0 : return true;
507 0 : }
508 :
509 : /* hpd for digital panel detect/disconnect */
510 : /**
511 : * r100_hpd_sense - hpd sense callback.
512 : *
513 : * @rdev: radeon_device pointer
514 : * @hpd: hpd (hotplug detect) pin
515 : *
516 : * Checks if a digital monitor is connected (r1xx-r4xx).
517 : * Returns true if connected, false if not connected.
518 : */
519 0 : bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
520 : {
521 : bool connected = false;
522 :
523 0 : switch (hpd) {
524 : case RADEON_HPD_1:
525 0 : if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
526 0 : connected = true;
527 : break;
528 : case RADEON_HPD_2:
529 0 : if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
530 0 : connected = true;
531 : break;
532 : default:
533 : break;
534 : }
535 0 : return connected;
536 : }
537 :
538 : /**
539 : * r100_hpd_set_polarity - hpd set polarity callback.
540 : *
541 : * @rdev: radeon_device pointer
542 : * @hpd: hpd (hotplug detect) pin
543 : *
544 : * Set the polarity of the hpd pin (r1xx-r4xx).
545 : */
546 0 : void r100_hpd_set_polarity(struct radeon_device *rdev,
547 : enum radeon_hpd_id hpd)
548 : {
549 : u32 tmp;
550 0 : bool connected = r100_hpd_sense(rdev, hpd);
551 :
552 0 : switch (hpd) {
553 : case RADEON_HPD_1:
554 0 : tmp = RREG32(RADEON_FP_GEN_CNTL);
555 0 : if (connected)
556 0 : tmp &= ~RADEON_FP_DETECT_INT_POL;
557 : else
558 0 : tmp |= RADEON_FP_DETECT_INT_POL;
559 0 : WREG32(RADEON_FP_GEN_CNTL, tmp);
560 0 : break;
561 : case RADEON_HPD_2:
562 0 : tmp = RREG32(RADEON_FP2_GEN_CNTL);
563 0 : if (connected)
564 0 : tmp &= ~RADEON_FP2_DETECT_INT_POL;
565 : else
566 0 : tmp |= RADEON_FP2_DETECT_INT_POL;
567 0 : WREG32(RADEON_FP2_GEN_CNTL, tmp);
568 0 : break;
569 : default:
570 : break;
571 : }
572 0 : }
573 :
574 : /**
575 : * r100_hpd_init - hpd setup callback.
576 : *
577 : * @rdev: radeon_device pointer
578 : *
579 : * Setup the hpd pins used by the card (r1xx-r4xx).
580 : * Set the polarity, and enable the hpd interrupts.
581 : */
582 0 : void r100_hpd_init(struct radeon_device *rdev)
583 : {
584 0 : struct drm_device *dev = rdev->ddev;
585 : struct drm_connector *connector;
586 : unsigned enable = 0;
587 :
588 0 : list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
589 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
590 0 : enable |= 1 << radeon_connector->hpd.hpd;
591 0 : radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
592 : }
593 0 : radeon_irq_kms_enable_hpd(rdev, enable);
594 0 : }
595 :
596 : /**
597 : * r100_hpd_fini - hpd tear down callback.
598 : *
599 : * @rdev: radeon_device pointer
600 : *
601 : * Tear down the hpd pins used by the card (r1xx-r4xx).
602 : * Disable the hpd interrupts.
603 : */
604 0 : void r100_hpd_fini(struct radeon_device *rdev)
605 : {
606 0 : struct drm_device *dev = rdev->ddev;
607 : struct drm_connector *connector;
608 : unsigned disable = 0;
609 :
610 0 : list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
611 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
612 0 : disable |= 1 << radeon_connector->hpd.hpd;
613 : }
614 0 : radeon_irq_kms_disable_hpd(rdev, disable);
615 0 : }
616 :
617 : /*
618 : * PCI GART
619 : */
620 0 : void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
621 : {
622 : /* TODO: can we do somethings here ? */
623 : /* It seems hw only cache one entry so we should discard this
624 : * entry otherwise if first GPU GART read hit this entry it
625 : * could end up in wrong address. */
626 0 : }
627 :
628 0 : int r100_pci_gart_init(struct radeon_device *rdev)
629 : {
630 : int r;
631 :
632 0 : if (rdev->gart.ptr) {
633 0 : WARN(1, "R100 PCI GART already initialized\n");
634 0 : return 0;
635 : }
636 : /* Initialize common gart structure */
637 0 : r = radeon_gart_init(rdev);
638 0 : if (r)
639 0 : return r;
640 0 : rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
641 0 : rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
642 0 : rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
643 0 : rdev->asic->gart.set_page = &r100_pci_gart_set_page;
644 0 : return radeon_gart_table_ram_alloc(rdev);
645 0 : }
646 :
647 0 : int r100_pci_gart_enable(struct radeon_device *rdev)
648 : {
649 : uint32_t tmp;
650 :
651 : /* discard memory request outside of configured range */
652 0 : tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
653 0 : WREG32(RADEON_AIC_CNTL, tmp);
654 : /* set address range for PCI address translate */
655 0 : WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
656 0 : WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
657 : /* set PCI GART page-table base address */
658 0 : WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
659 0 : tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
660 0 : WREG32(RADEON_AIC_CNTL, tmp);
661 0 : r100_pci_gart_tlb_flush(rdev);
662 : DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
663 : (unsigned)(rdev->mc.gtt_size >> 20),
664 : (unsigned long long)rdev->gart.table_addr);
665 0 : rdev->gart.ready = true;
666 0 : return 0;
667 : }
668 :
669 0 : void r100_pci_gart_disable(struct radeon_device *rdev)
670 : {
671 : uint32_t tmp;
672 :
673 : /* discard memory request outside of configured range */
674 0 : tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
675 0 : WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
676 0 : WREG32(RADEON_AIC_LO_ADDR, 0);
677 0 : WREG32(RADEON_AIC_HI_ADDR, 0);
678 0 : }
679 :
680 0 : uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
681 : {
682 0 : return addr;
683 : }
684 :
685 0 : void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
686 : uint64_t entry)
687 : {
688 0 : u32 *gtt = rdev->gart.ptr;
689 0 : gtt[i] = cpu_to_le32(lower_32_bits(entry));
690 0 : }
691 :
692 0 : void r100_pci_gart_fini(struct radeon_device *rdev)
693 : {
694 0 : radeon_gart_fini(rdev);
695 0 : r100_pci_gart_disable(rdev);
696 0 : radeon_gart_table_ram_free(rdev);
697 0 : }
698 :
699 0 : int r100_irq_set(struct radeon_device *rdev)
700 : {
701 : uint32_t tmp = 0;
702 :
703 0 : if (!rdev->irq.installed) {
704 0 : WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
705 0 : WREG32(R_000040_GEN_INT_CNTL, 0);
706 0 : return -EINVAL;
707 : }
708 0 : if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
709 : tmp |= RADEON_SW_INT_ENABLE;
710 0 : }
711 0 : if (rdev->irq.crtc_vblank_int[0] ||
712 0 : atomic_read(&rdev->irq.pflip[0])) {
713 0 : tmp |= RADEON_CRTC_VBLANK_MASK;
714 0 : }
715 0 : if (rdev->irq.crtc_vblank_int[1] ||
716 0 : atomic_read(&rdev->irq.pflip[1])) {
717 0 : tmp |= RADEON_CRTC2_VBLANK_MASK;
718 0 : }
719 0 : if (rdev->irq.hpd[0]) {
720 0 : tmp |= RADEON_FP_DETECT_MASK;
721 0 : }
722 0 : if (rdev->irq.hpd[1]) {
723 0 : tmp |= RADEON_FP2_DETECT_MASK;
724 0 : }
725 0 : WREG32(RADEON_GEN_INT_CNTL, tmp);
726 :
727 : /* read back to post the write */
728 0 : RREG32(RADEON_GEN_INT_CNTL);
729 :
730 0 : return 0;
731 0 : }
732 :
733 0 : void r100_irq_disable(struct radeon_device *rdev)
734 : {
735 : u32 tmp;
736 :
737 0 : WREG32(R_000040_GEN_INT_CNTL, 0);
738 : /* Wait and acknowledge irq */
739 0 : mdelay(1);
740 0 : tmp = RREG32(R_000044_GEN_INT_STATUS);
741 0 : WREG32(R_000044_GEN_INT_STATUS, tmp);
742 0 : }
743 :
744 0 : static uint32_t r100_irq_ack(struct radeon_device *rdev)
745 : {
746 0 : uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
747 : uint32_t irq_mask = RADEON_SW_INT_TEST |
748 : RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
749 : RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
750 :
751 0 : if (irqs) {
752 0 : WREG32(RADEON_GEN_INT_STATUS, irqs);
753 0 : }
754 0 : return irqs & irq_mask;
755 : }
756 :
757 0 : int r100_irq_process(struct radeon_device *rdev)
758 : {
759 : uint32_t status, msi_rearm;
760 : bool queue_hotplug = false;
761 :
762 0 : status = r100_irq_ack(rdev);
763 0 : if (!status) {
764 0 : return IRQ_NONE;
765 : }
766 0 : if (rdev->shutdown) {
767 0 : return IRQ_NONE;
768 : }
769 0 : while (status) {
770 : /* SW interrupt */
771 0 : if (status & RADEON_SW_INT_TEST) {
772 0 : radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
773 0 : }
774 : /* Vertical blank interrupts */
775 0 : if (status & RADEON_CRTC_VBLANK_STAT) {
776 0 : if (rdev->irq.crtc_vblank_int[0]) {
777 0 : drm_handle_vblank(rdev->ddev, 0);
778 0 : rdev->pm.vblank_sync = true;
779 0 : wake_up(&rdev->irq.vblank_queue);
780 0 : }
781 0 : if (atomic_read(&rdev->irq.pflip[0]))
782 0 : radeon_crtc_handle_vblank(rdev, 0);
783 : }
784 0 : if (status & RADEON_CRTC2_VBLANK_STAT) {
785 0 : if (rdev->irq.crtc_vblank_int[1]) {
786 0 : drm_handle_vblank(rdev->ddev, 1);
787 0 : rdev->pm.vblank_sync = true;
788 0 : wake_up(&rdev->irq.vblank_queue);
789 0 : }
790 0 : if (atomic_read(&rdev->irq.pflip[1]))
791 0 : radeon_crtc_handle_vblank(rdev, 1);
792 : }
793 0 : if (status & RADEON_FP_DETECT_STAT) {
794 : queue_hotplug = true;
795 : DRM_DEBUG("HPD1\n");
796 0 : }
797 0 : if (status & RADEON_FP2_DETECT_STAT) {
798 : queue_hotplug = true;
799 : DRM_DEBUG("HPD2\n");
800 0 : }
801 0 : status = r100_irq_ack(rdev);
802 : }
803 0 : if (queue_hotplug)
804 0 : schedule_delayed_work(&rdev->hotplug_work, 0);
805 0 : if (rdev->msi_enabled) {
806 0 : switch (rdev->family) {
807 : case CHIP_RS400:
808 : case CHIP_RS480:
809 0 : msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
810 0 : WREG32(RADEON_AIC_CNTL, msi_rearm);
811 0 : WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
812 0 : break;
813 : default:
814 0 : WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
815 0 : break;
816 : }
817 : }
818 0 : return IRQ_HANDLED;
819 0 : }
820 :
821 0 : u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
822 : {
823 0 : if (crtc == 0)
824 0 : return RREG32(RADEON_CRTC_CRNT_FRAME);
825 : else
826 0 : return RREG32(RADEON_CRTC2_CRNT_FRAME);
827 0 : }
828 :
829 : /**
830 : * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
831 : * rdev: radeon device structure
832 : * ring: ring buffer struct for emitting packets
833 : */
834 0 : static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
835 : {
836 0 : radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
837 0 : radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
838 : RADEON_HDP_READ_BUFFER_INVALIDATE);
839 0 : radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
840 0 : radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
841 0 : }
842 :
843 : /* Who ever call radeon_fence_emit should call ring_lock and ask
844 : * for enough space (today caller are ib schedule and buffer move) */
845 0 : void r100_fence_ring_emit(struct radeon_device *rdev,
846 : struct radeon_fence *fence)
847 : {
848 0 : struct radeon_ring *ring = &rdev->ring[fence->ring];
849 :
850 : /* We have to make sure that caches are flushed before
851 : * CPU might read something from VRAM. */
852 0 : radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
853 0 : radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
854 0 : radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
855 0 : radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
856 : /* Wait until IDLE & CLEAN */
857 0 : radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
858 0 : radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
859 0 : r100_ring_hdp_flush(rdev, ring);
860 : /* Emit fence sequence & fire IRQ */
861 0 : radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
862 0 : radeon_ring_write(ring, fence->seq);
863 0 : radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
864 0 : radeon_ring_write(ring, RADEON_SW_INT_FIRE);
865 0 : }
866 :
867 0 : bool r100_semaphore_ring_emit(struct radeon_device *rdev,
868 : struct radeon_ring *ring,
869 : struct radeon_semaphore *semaphore,
870 : bool emit_wait)
871 : {
872 : /* Unused on older asics, since we don't have semaphores or multiple rings */
873 0 : BUG();
874 : return false;
875 : }
876 :
877 0 : struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
878 : uint64_t src_offset,
879 : uint64_t dst_offset,
880 : unsigned num_gpu_pages,
881 : struct reservation_object *resv)
882 : {
883 0 : struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
884 0 : struct radeon_fence *fence;
885 : uint32_t cur_pages;
886 : uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
887 : uint32_t pitch;
888 : uint32_t stride_pixels;
889 : unsigned ndw;
890 : int num_loops;
891 : int r = 0;
892 :
893 : /* radeon limited to 16k stride */
894 : stride_bytes &= 0x3fff;
895 : /* radeon pitch is /64 */
896 : pitch = stride_bytes / 64;
897 : stride_pixels = stride_bytes / 4;
898 0 : num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
899 :
900 : /* Ask for enough room for blit + flush + fence */
901 0 : ndw = 64 + (10 * num_loops);
902 0 : r = radeon_ring_lock(rdev, ring, ndw);
903 0 : if (r) {
904 0 : DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
905 0 : return ERR_PTR(-EINVAL);
906 : }
907 0 : while (num_gpu_pages > 0) {
908 : cur_pages = num_gpu_pages;
909 0 : if (cur_pages > 8191) {
910 : cur_pages = 8191;
911 : }
912 0 : num_gpu_pages -= cur_pages;
913 :
914 : /* pages are in Y direction - height
915 : page width in X direction - width */
916 0 : radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
917 0 : radeon_ring_write(ring,
918 : RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
919 : RADEON_GMC_DST_PITCH_OFFSET_CNTL |
920 : RADEON_GMC_SRC_CLIPPING |
921 : RADEON_GMC_DST_CLIPPING |
922 : RADEON_GMC_BRUSH_NONE |
923 : (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
924 : RADEON_GMC_SRC_DATATYPE_COLOR |
925 : RADEON_ROP3_S |
926 : RADEON_DP_SRC_SOURCE_MEMORY |
927 : RADEON_GMC_CLR_CMP_CNTL_DIS |
928 : RADEON_GMC_WR_MSK_DIS);
929 0 : radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
930 0 : radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
931 0 : radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
932 0 : radeon_ring_write(ring, 0);
933 0 : radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
934 0 : radeon_ring_write(ring, num_gpu_pages);
935 0 : radeon_ring_write(ring, num_gpu_pages);
936 0 : radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
937 : }
938 0 : radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
939 0 : radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
940 0 : radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
941 0 : radeon_ring_write(ring,
942 : RADEON_WAIT_2D_IDLECLEAN |
943 : RADEON_WAIT_HOST_IDLECLEAN |
944 : RADEON_WAIT_DMA_GUI_IDLE);
945 0 : r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
946 0 : if (r) {
947 0 : radeon_ring_unlock_undo(rdev, ring);
948 0 : return ERR_PTR(r);
949 : }
950 0 : radeon_ring_unlock_commit(rdev, ring, false);
951 0 : return fence;
952 0 : }
953 :
954 0 : static int r100_cp_wait_for_idle(struct radeon_device *rdev)
955 : {
956 : unsigned i;
957 : u32 tmp;
958 :
959 0 : for (i = 0; i < rdev->usec_timeout; i++) {
960 0 : tmp = RREG32(R_000E40_RBBM_STATUS);
961 0 : if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
962 0 : return 0;
963 : }
964 0 : udelay(1);
965 : }
966 0 : return -1;
967 0 : }
968 :
969 0 : void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
970 : {
971 : int r;
972 :
973 0 : r = radeon_ring_lock(rdev, ring, 2);
974 0 : if (r) {
975 0 : return;
976 : }
977 0 : radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
978 0 : radeon_ring_write(ring,
979 : RADEON_ISYNC_ANY2D_IDLE3D |
980 : RADEON_ISYNC_ANY3D_IDLE2D |
981 : RADEON_ISYNC_WAIT_IDLEGUI |
982 : RADEON_ISYNC_CPSCRATCH_IDLEGUI);
983 0 : radeon_ring_unlock_commit(rdev, ring, false);
984 0 : }
985 :
986 :
987 : /* Load the microcode for the CP */
988 0 : static int r100_cp_init_microcode(struct radeon_device *rdev)
989 : {
990 : const char *fw_name = NULL;
991 : int err;
992 :
993 : DRM_DEBUG_KMS("\n");
994 :
995 0 : if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
996 0 : (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
997 0 : (rdev->family == CHIP_RS200)) {
998 : DRM_INFO("Loading R100 Microcode\n");
999 : fw_name = FIRMWARE_R100;
1000 0 : } else if ((rdev->family == CHIP_R200) ||
1001 0 : (rdev->family == CHIP_RV250) ||
1002 0 : (rdev->family == CHIP_RV280) ||
1003 0 : (rdev->family == CHIP_RS300)) {
1004 : DRM_INFO("Loading R200 Microcode\n");
1005 : fw_name = FIRMWARE_R200;
1006 0 : } else if ((rdev->family == CHIP_R300) ||
1007 0 : (rdev->family == CHIP_R350) ||
1008 0 : (rdev->family == CHIP_RV350) ||
1009 0 : (rdev->family == CHIP_RV380) ||
1010 0 : (rdev->family == CHIP_RS400) ||
1011 0 : (rdev->family == CHIP_RS480)) {
1012 : DRM_INFO("Loading R300 Microcode\n");
1013 : fw_name = FIRMWARE_R300;
1014 0 : } else if ((rdev->family == CHIP_R420) ||
1015 0 : (rdev->family == CHIP_R423) ||
1016 0 : (rdev->family == CHIP_RV410)) {
1017 : DRM_INFO("Loading R400 Microcode\n");
1018 : fw_name = FIRMWARE_R420;
1019 0 : } else if ((rdev->family == CHIP_RS690) ||
1020 0 : (rdev->family == CHIP_RS740)) {
1021 : DRM_INFO("Loading RS690/RS740 Microcode\n");
1022 : fw_name = FIRMWARE_RS690;
1023 0 : } else if (rdev->family == CHIP_RS600) {
1024 : DRM_INFO("Loading RS600 Microcode\n");
1025 : fw_name = FIRMWARE_RS600;
1026 0 : } else if ((rdev->family == CHIP_RV515) ||
1027 0 : (rdev->family == CHIP_R520) ||
1028 0 : (rdev->family == CHIP_RV530) ||
1029 0 : (rdev->family == CHIP_R580) ||
1030 0 : (rdev->family == CHIP_RV560) ||
1031 0 : (rdev->family == CHIP_RV570)) {
1032 : DRM_INFO("Loading R500 Microcode\n");
1033 : fw_name = FIRMWARE_R520;
1034 0 : }
1035 :
1036 0 : err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1037 0 : if (err) {
1038 0 : printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1039 : fw_name);
1040 0 : } else if (rdev->me_fw->size % 8) {
1041 0 : printk(KERN_ERR
1042 : "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1043 : rdev->me_fw->size, fw_name);
1044 : err = -EINVAL;
1045 0 : release_firmware(rdev->me_fw);
1046 0 : rdev->me_fw = NULL;
1047 0 : }
1048 0 : return err;
1049 : }
1050 :
1051 0 : u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1052 : struct radeon_ring *ring)
1053 : {
1054 : u32 rptr;
1055 :
1056 0 : if (rdev->wb.enabled)
1057 0 : rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1058 : else
1059 0 : rptr = RREG32(RADEON_CP_RB_RPTR);
1060 :
1061 0 : return rptr;
1062 : }
1063 :
1064 0 : u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1065 : struct radeon_ring *ring)
1066 : {
1067 : u32 wptr;
1068 :
1069 0 : wptr = RREG32(RADEON_CP_RB_WPTR);
1070 :
1071 0 : return wptr;
1072 : }
1073 :
1074 0 : void r100_gfx_set_wptr(struct radeon_device *rdev,
1075 : struct radeon_ring *ring)
1076 : {
1077 0 : WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1078 0 : (void)RREG32(RADEON_CP_RB_WPTR);
1079 0 : }
1080 :
1081 0 : static void r100_cp_load_microcode(struct radeon_device *rdev)
1082 : {
1083 : const __be32 *fw_data;
1084 : int i, size;
1085 :
1086 0 : if (r100_gui_wait_for_idle(rdev)) {
1087 0 : printk(KERN_WARNING "Failed to wait GUI idle while "
1088 : "programming pipes. Bad things might happen.\n");
1089 0 : }
1090 :
1091 0 : if (rdev->me_fw) {
1092 0 : size = rdev->me_fw->size / 4;
1093 0 : fw_data = (const __be32 *)&rdev->me_fw->data[0];
1094 0 : WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1095 0 : for (i = 0; i < size; i += 2) {
1096 0 : WREG32(RADEON_CP_ME_RAM_DATAH,
1097 : be32_to_cpup(&fw_data[i]));
1098 0 : WREG32(RADEON_CP_ME_RAM_DATAL,
1099 : be32_to_cpup(&fw_data[i + 1]));
1100 : }
1101 : }
1102 0 : }
1103 :
1104 0 : int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1105 : {
1106 0 : struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1107 : unsigned rb_bufsz;
1108 : unsigned rb_blksz;
1109 : unsigned max_fetch;
1110 : unsigned pre_write_timer;
1111 : unsigned pre_write_limit;
1112 : unsigned indirect2_start;
1113 : unsigned indirect1_start;
1114 : uint32_t tmp;
1115 : int r;
1116 :
1117 0 : if (r100_debugfs_cp_init(rdev)) {
1118 0 : DRM_ERROR("Failed to register debugfs file for CP !\n");
1119 0 : }
1120 0 : if (!rdev->me_fw) {
1121 0 : r = r100_cp_init_microcode(rdev);
1122 0 : if (r) {
1123 0 : DRM_ERROR("Failed to load firmware!\n");
1124 0 : return r;
1125 : }
1126 : }
1127 :
1128 : /* Align ring size */
1129 0 : rb_bufsz = order_base_2(ring_size / 8);
1130 0 : ring_size = (1 << (rb_bufsz + 1)) * 4;
1131 0 : r100_cp_load_microcode(rdev);
1132 0 : r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1133 : RADEON_CP_PACKET2);
1134 0 : if (r) {
1135 0 : return r;
1136 : }
1137 : /* Each time the cp read 1024 bytes (16 dword/quadword) update
1138 : * the rptr copy in system ram */
1139 : rb_blksz = 9;
1140 : /* cp will read 128bytes at a time (4 dwords) */
1141 : max_fetch = 1;
1142 0 : ring->align_mask = 16 - 1;
1143 : /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1144 : pre_write_timer = 64;
1145 : /* Force CP_RB_WPTR write if written more than one time before the
1146 : * delay expire
1147 : */
1148 : pre_write_limit = 0;
1149 : /* Setup the cp cache like this (cache size is 96 dwords) :
1150 : * RING 0 to 15
1151 : * INDIRECT1 16 to 79
1152 : * INDIRECT2 80 to 95
1153 : * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1154 : * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1155 : * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1156 : * Idea being that most of the gpu cmd will be through indirect1 buffer
1157 : * so it gets the bigger cache.
1158 : */
1159 : indirect2_start = 80;
1160 : indirect1_start = 16;
1161 : /* cp setup */
1162 0 : WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1163 0 : tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1164 0 : REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1165 : REG_SET(RADEON_MAX_FETCH, max_fetch));
1166 : #ifdef __BIG_ENDIAN
1167 : tmp |= RADEON_BUF_SWAP_32BIT;
1168 : #endif
1169 0 : WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1170 :
1171 : /* Set ring address */
1172 : DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1173 0 : WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1174 : /* Force read & write ptr to 0 */
1175 0 : WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1176 0 : WREG32(RADEON_CP_RB_RPTR_WR, 0);
1177 0 : ring->wptr = 0;
1178 0 : WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1179 :
1180 : /* set the wb address whether it's enabled or not */
1181 0 : WREG32(R_00070C_CP_RB_RPTR_ADDR,
1182 : S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1183 0 : WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1184 :
1185 0 : if (rdev->wb.enabled)
1186 0 : WREG32(R_000770_SCRATCH_UMSK, 0xff);
1187 : else {
1188 : tmp |= RADEON_RB_NO_UPDATE;
1189 0 : WREG32(R_000770_SCRATCH_UMSK, 0);
1190 : }
1191 :
1192 0 : WREG32(RADEON_CP_RB_CNTL, tmp);
1193 0 : udelay(10);
1194 : /* Set cp mode to bus mastering & enable cp*/
1195 0 : WREG32(RADEON_CP_CSQ_MODE,
1196 : REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1197 : REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1198 0 : WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1199 0 : WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1200 0 : WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1201 :
1202 : /* at this point everything should be setup correctly to enable master */
1203 : pci_set_master(rdev->pdev);
1204 :
1205 0 : radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1206 0 : r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1207 0 : if (r) {
1208 0 : DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1209 0 : return r;
1210 : }
1211 0 : ring->ready = true;
1212 0 : radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1213 :
1214 0 : if (!ring->rptr_save_reg /* not resuming from suspend */
1215 0 : && radeon_ring_supports_scratch_reg(rdev, ring)) {
1216 0 : r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1217 0 : if (r) {
1218 0 : DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1219 0 : ring->rptr_save_reg = 0;
1220 0 : }
1221 : }
1222 0 : return 0;
1223 0 : }
1224 :
1225 0 : void r100_cp_fini(struct radeon_device *rdev)
1226 : {
1227 0 : if (r100_cp_wait_for_idle(rdev)) {
1228 0 : DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1229 0 : }
1230 : /* Disable ring */
1231 0 : r100_cp_disable(rdev);
1232 0 : radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1233 0 : radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1234 : DRM_INFO("radeon: cp finalized\n");
1235 0 : }
1236 :
1237 0 : void r100_cp_disable(struct radeon_device *rdev)
1238 : {
1239 : /* Disable ring */
1240 0 : radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1241 0 : rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1242 0 : WREG32(RADEON_CP_CSQ_MODE, 0);
1243 0 : WREG32(RADEON_CP_CSQ_CNTL, 0);
1244 0 : WREG32(R_000770_SCRATCH_UMSK, 0);
1245 0 : if (r100_gui_wait_for_idle(rdev)) {
1246 0 : printk(KERN_WARNING "Failed to wait GUI idle while "
1247 : "programming pipes. Bad things might happen.\n");
1248 0 : }
1249 0 : }
1250 :
1251 : /*
1252 : * CS functions
1253 : */
1254 0 : int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1255 : struct radeon_cs_packet *pkt,
1256 : unsigned idx,
1257 : unsigned reg)
1258 : {
1259 : int r;
1260 : u32 tile_flags = 0;
1261 : u32 tmp;
1262 0 : struct radeon_bo_list *reloc;
1263 : u32 value;
1264 :
1265 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1266 0 : if (r) {
1267 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1268 : idx, reg);
1269 0 : radeon_cs_dump_packet(p, pkt);
1270 0 : return r;
1271 : }
1272 :
1273 0 : value = radeon_get_ib_value(p, idx);
1274 0 : tmp = value & 0x003fffff;
1275 0 : tmp += (((u32)reloc->gpu_offset) >> 10);
1276 :
1277 0 : if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1278 0 : if (reloc->tiling_flags & RADEON_TILING_MACRO)
1279 0 : tile_flags |= RADEON_DST_TILE_MACRO;
1280 0 : if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1281 0 : if (reg == RADEON_SRC_PITCH_OFFSET) {
1282 0 : DRM_ERROR("Cannot src blit from microtiled surface\n");
1283 0 : radeon_cs_dump_packet(p, pkt);
1284 0 : return -EINVAL;
1285 : }
1286 0 : tile_flags |= RADEON_DST_TILE_MICRO;
1287 0 : }
1288 :
1289 0 : tmp |= tile_flags;
1290 0 : p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1291 0 : } else
1292 0 : p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1293 0 : return 0;
1294 0 : }
1295 :
1296 0 : int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1297 : struct radeon_cs_packet *pkt,
1298 : int idx)
1299 : {
1300 : unsigned c, i;
1301 0 : struct radeon_bo_list *reloc;
1302 : struct r100_cs_track *track;
1303 : int r = 0;
1304 : volatile uint32_t *ib;
1305 : u32 idx_value;
1306 :
1307 0 : ib = p->ib.ptr;
1308 0 : track = (struct r100_cs_track *)p->track;
1309 0 : c = radeon_get_ib_value(p, idx++) & 0x1F;
1310 0 : if (c > 16) {
1311 0 : DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1312 : pkt->opcode);
1313 0 : radeon_cs_dump_packet(p, pkt);
1314 0 : return -EINVAL;
1315 : }
1316 0 : track->num_arrays = c;
1317 0 : for (i = 0; i < (c - 1); i+=2, idx+=3) {
1318 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1319 0 : if (r) {
1320 0 : DRM_ERROR("No reloc for packet3 %d\n",
1321 : pkt->opcode);
1322 0 : radeon_cs_dump_packet(p, pkt);
1323 0 : return r;
1324 : }
1325 0 : idx_value = radeon_get_ib_value(p, idx);
1326 0 : ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1327 :
1328 0 : track->arrays[i + 0].esize = idx_value >> 8;
1329 0 : track->arrays[i + 0].robj = reloc->robj;
1330 0 : track->arrays[i + 0].esize &= 0x7F;
1331 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1332 0 : if (r) {
1333 0 : DRM_ERROR("No reloc for packet3 %d\n",
1334 : pkt->opcode);
1335 0 : radeon_cs_dump_packet(p, pkt);
1336 0 : return r;
1337 : }
1338 0 : ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1339 0 : track->arrays[i + 1].robj = reloc->robj;
1340 0 : track->arrays[i + 1].esize = idx_value >> 24;
1341 0 : track->arrays[i + 1].esize &= 0x7F;
1342 : }
1343 0 : if (c & 1) {
1344 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1345 0 : if (r) {
1346 0 : DRM_ERROR("No reloc for packet3 %d\n",
1347 : pkt->opcode);
1348 0 : radeon_cs_dump_packet(p, pkt);
1349 0 : return r;
1350 : }
1351 0 : idx_value = radeon_get_ib_value(p, idx);
1352 0 : ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1353 0 : track->arrays[i + 0].robj = reloc->robj;
1354 0 : track->arrays[i + 0].esize = idx_value >> 8;
1355 0 : track->arrays[i + 0].esize &= 0x7F;
1356 0 : }
1357 0 : return r;
1358 0 : }
1359 :
1360 0 : int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1361 : struct radeon_cs_packet *pkt,
1362 : const unsigned *auth, unsigned n,
1363 : radeon_packet0_check_t check)
1364 : {
1365 : unsigned reg;
1366 : unsigned i, j, m;
1367 : unsigned idx;
1368 : int r;
1369 :
1370 0 : idx = pkt->idx + 1;
1371 0 : reg = pkt->reg;
1372 : /* Check that register fall into register range
1373 : * determined by the number of entry (n) in the
1374 : * safe register bitmap.
1375 : */
1376 0 : if (pkt->one_reg_wr) {
1377 0 : if ((reg >> 7) > n) {
1378 0 : return -EINVAL;
1379 : }
1380 : } else {
1381 0 : if (((reg + (pkt->count << 2)) >> 7) > n) {
1382 0 : return -EINVAL;
1383 : }
1384 : }
1385 0 : for (i = 0; i <= pkt->count; i++, idx++) {
1386 0 : j = (reg >> 7);
1387 0 : m = 1 << ((reg >> 2) & 31);
1388 0 : if (auth[j] & m) {
1389 0 : r = check(p, pkt, idx, reg);
1390 0 : if (r) {
1391 0 : return r;
1392 : }
1393 : }
1394 0 : if (pkt->one_reg_wr) {
1395 0 : if (!(auth[j] & m)) {
1396 : break;
1397 : }
1398 : } else {
1399 0 : reg += 4;
1400 : }
1401 : }
1402 0 : return 0;
1403 0 : }
1404 :
1405 : /**
1406 : * r100_cs_packet_next_vline() - parse userspace VLINE packet
1407 : * @parser: parser structure holding parsing context.
1408 : *
1409 : * Userspace sends a special sequence for VLINE waits.
1410 : * PACKET0 - VLINE_START_END + value
1411 : * PACKET0 - WAIT_UNTIL +_value
1412 : * RELOC (P3) - crtc_id in reloc.
1413 : *
1414 : * This function parses this and relocates the VLINE START END
1415 : * and WAIT UNTIL packets to the correct crtc.
1416 : * It also detects a switched off crtc and nulls out the
1417 : * wait in that case.
1418 : */
1419 0 : int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1420 : {
1421 : struct drm_crtc *crtc;
1422 : struct radeon_crtc *radeon_crtc;
1423 0 : struct radeon_cs_packet p3reloc, waitreloc;
1424 : int crtc_id;
1425 : int r;
1426 : uint32_t header, h_idx, reg;
1427 : volatile uint32_t *ib;
1428 :
1429 0 : ib = p->ib.ptr;
1430 :
1431 : /* parse the wait until */
1432 0 : r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1433 0 : if (r)
1434 0 : return r;
1435 :
1436 : /* check its a wait until and only 1 count */
1437 0 : if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1438 0 : waitreloc.count != 0) {
1439 0 : DRM_ERROR("vline wait had illegal wait until segment\n");
1440 0 : return -EINVAL;
1441 : }
1442 :
1443 0 : if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1444 0 : DRM_ERROR("vline wait had illegal wait until\n");
1445 0 : return -EINVAL;
1446 : }
1447 :
1448 : /* jump over the NOP */
1449 0 : r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1450 0 : if (r)
1451 0 : return r;
1452 :
1453 0 : h_idx = p->idx - 2;
1454 0 : p->idx += waitreloc.count + 2;
1455 0 : p->idx += p3reloc.count + 2;
1456 :
1457 0 : header = radeon_get_ib_value(p, h_idx);
1458 0 : crtc_id = radeon_get_ib_value(p, h_idx + 5);
1459 0 : reg = R100_CP_PACKET0_GET_REG(header);
1460 0 : crtc = drm_crtc_find(p->rdev->ddev, crtc_id);
1461 0 : if (!crtc) {
1462 0 : DRM_ERROR("cannot find crtc %d\n", crtc_id);
1463 0 : return -ENOENT;
1464 : }
1465 0 : radeon_crtc = to_radeon_crtc(crtc);
1466 0 : crtc_id = radeon_crtc->crtc_id;
1467 :
1468 0 : if (!crtc->enabled) {
1469 : /* if the CRTC isn't enabled - we need to nop out the wait until */
1470 0 : ib[h_idx + 2] = PACKET2(0);
1471 0 : ib[h_idx + 3] = PACKET2(0);
1472 0 : } else if (crtc_id == 1) {
1473 0 : switch (reg) {
1474 : case AVIVO_D1MODE_VLINE_START_END:
1475 0 : header &= ~R300_CP_PACKET0_REG_MASK;
1476 0 : header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1477 0 : break;
1478 : case RADEON_CRTC_GUI_TRIG_VLINE:
1479 0 : header &= ~R300_CP_PACKET0_REG_MASK;
1480 0 : header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1481 0 : break;
1482 : default:
1483 0 : DRM_ERROR("unknown crtc reloc\n");
1484 0 : return -EINVAL;
1485 : }
1486 0 : ib[h_idx] = header;
1487 0 : ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1488 0 : }
1489 :
1490 0 : return 0;
1491 0 : }
1492 :
1493 0 : static int r100_get_vtx_size(uint32_t vtx_fmt)
1494 : {
1495 : int vtx_size;
1496 : vtx_size = 2;
1497 : /* ordered according to bits in spec */
1498 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1499 0 : vtx_size++;
1500 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1501 0 : vtx_size += 3;
1502 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1503 0 : vtx_size++;
1504 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1505 0 : vtx_size++;
1506 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1507 0 : vtx_size += 3;
1508 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1509 0 : vtx_size++;
1510 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1511 0 : vtx_size++;
1512 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1513 0 : vtx_size += 2;
1514 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1515 0 : vtx_size += 2;
1516 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1517 0 : vtx_size++;
1518 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1519 0 : vtx_size += 2;
1520 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1521 0 : vtx_size++;
1522 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1523 0 : vtx_size += 2;
1524 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1525 0 : vtx_size++;
1526 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1527 0 : vtx_size++;
1528 : /* blend weight */
1529 0 : if (vtx_fmt & (0x7 << 15))
1530 0 : vtx_size += (vtx_fmt >> 15) & 0x7;
1531 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1532 0 : vtx_size += 3;
1533 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1534 0 : vtx_size += 2;
1535 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1536 0 : vtx_size++;
1537 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1538 0 : vtx_size++;
1539 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1540 0 : vtx_size++;
1541 0 : if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1542 0 : vtx_size++;
1543 0 : return vtx_size;
1544 : }
1545 :
1546 0 : static int r100_packet0_check(struct radeon_cs_parser *p,
1547 : struct radeon_cs_packet *pkt,
1548 : unsigned idx, unsigned reg)
1549 : {
1550 0 : struct radeon_bo_list *reloc;
1551 : struct r100_cs_track *track;
1552 : volatile uint32_t *ib;
1553 : uint32_t tmp;
1554 : int r;
1555 : int i, face;
1556 : u32 tile_flags = 0;
1557 : u32 idx_value;
1558 :
1559 0 : ib = p->ib.ptr;
1560 0 : track = (struct r100_cs_track *)p->track;
1561 :
1562 0 : idx_value = radeon_get_ib_value(p, idx);
1563 :
1564 0 : switch (reg) {
1565 : case RADEON_CRTC_GUI_TRIG_VLINE:
1566 0 : r = r100_cs_packet_parse_vline(p);
1567 0 : if (r) {
1568 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1569 : idx, reg);
1570 0 : radeon_cs_dump_packet(p, pkt);
1571 0 : return r;
1572 : }
1573 : break;
1574 : /* FIXME: only allow PACKET3 blit? easier to check for out of
1575 : * range access */
1576 : case RADEON_DST_PITCH_OFFSET:
1577 : case RADEON_SRC_PITCH_OFFSET:
1578 0 : r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1579 0 : if (r)
1580 0 : return r;
1581 : break;
1582 : case RADEON_RB3D_DEPTHOFFSET:
1583 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1584 0 : if (r) {
1585 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1586 : idx, reg);
1587 0 : radeon_cs_dump_packet(p, pkt);
1588 0 : return r;
1589 : }
1590 0 : track->zb.robj = reloc->robj;
1591 0 : track->zb.offset = idx_value;
1592 0 : track->zb_dirty = true;
1593 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1594 0 : break;
1595 : case RADEON_RB3D_COLOROFFSET:
1596 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1597 0 : if (r) {
1598 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1599 : idx, reg);
1600 0 : radeon_cs_dump_packet(p, pkt);
1601 0 : return r;
1602 : }
1603 0 : track->cb[0].robj = reloc->robj;
1604 0 : track->cb[0].offset = idx_value;
1605 0 : track->cb_dirty = true;
1606 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1607 0 : break;
1608 : case RADEON_PP_TXOFFSET_0:
1609 : case RADEON_PP_TXOFFSET_1:
1610 : case RADEON_PP_TXOFFSET_2:
1611 0 : i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1612 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1613 0 : if (r) {
1614 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1615 : idx, reg);
1616 0 : radeon_cs_dump_packet(p, pkt);
1617 0 : return r;
1618 : }
1619 0 : if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1620 0 : if (reloc->tiling_flags & RADEON_TILING_MACRO)
1621 0 : tile_flags |= RADEON_TXO_MACRO_TILE;
1622 0 : if (reloc->tiling_flags & RADEON_TILING_MICRO)
1623 0 : tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1624 :
1625 0 : tmp = idx_value & ~(0x7 << 2);
1626 0 : tmp |= tile_flags;
1627 0 : ib[idx] = tmp + ((u32)reloc->gpu_offset);
1628 0 : } else
1629 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1630 0 : track->textures[i].robj = reloc->robj;
1631 0 : track->tex_dirty = true;
1632 0 : break;
1633 : case RADEON_PP_CUBIC_OFFSET_T0_0:
1634 : case RADEON_PP_CUBIC_OFFSET_T0_1:
1635 : case RADEON_PP_CUBIC_OFFSET_T0_2:
1636 : case RADEON_PP_CUBIC_OFFSET_T0_3:
1637 : case RADEON_PP_CUBIC_OFFSET_T0_4:
1638 0 : i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1639 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1640 0 : if (r) {
1641 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1642 : idx, reg);
1643 0 : radeon_cs_dump_packet(p, pkt);
1644 0 : return r;
1645 : }
1646 0 : track->textures[0].cube_info[i].offset = idx_value;
1647 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1648 0 : track->textures[0].cube_info[i].robj = reloc->robj;
1649 0 : track->tex_dirty = true;
1650 0 : break;
1651 : case RADEON_PP_CUBIC_OFFSET_T1_0:
1652 : case RADEON_PP_CUBIC_OFFSET_T1_1:
1653 : case RADEON_PP_CUBIC_OFFSET_T1_2:
1654 : case RADEON_PP_CUBIC_OFFSET_T1_3:
1655 : case RADEON_PP_CUBIC_OFFSET_T1_4:
1656 0 : i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1657 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1658 0 : if (r) {
1659 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1660 : idx, reg);
1661 0 : radeon_cs_dump_packet(p, pkt);
1662 0 : return r;
1663 : }
1664 0 : track->textures[1].cube_info[i].offset = idx_value;
1665 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1666 0 : track->textures[1].cube_info[i].robj = reloc->robj;
1667 0 : track->tex_dirty = true;
1668 0 : break;
1669 : case RADEON_PP_CUBIC_OFFSET_T2_0:
1670 : case RADEON_PP_CUBIC_OFFSET_T2_1:
1671 : case RADEON_PP_CUBIC_OFFSET_T2_2:
1672 : case RADEON_PP_CUBIC_OFFSET_T2_3:
1673 : case RADEON_PP_CUBIC_OFFSET_T2_4:
1674 0 : i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1675 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1676 0 : if (r) {
1677 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1678 : idx, reg);
1679 0 : radeon_cs_dump_packet(p, pkt);
1680 0 : return r;
1681 : }
1682 0 : track->textures[2].cube_info[i].offset = idx_value;
1683 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1684 0 : track->textures[2].cube_info[i].robj = reloc->robj;
1685 0 : track->tex_dirty = true;
1686 0 : break;
1687 : case RADEON_RE_WIDTH_HEIGHT:
1688 0 : track->maxy = ((idx_value >> 16) & 0x7FF);
1689 0 : track->cb_dirty = true;
1690 0 : track->zb_dirty = true;
1691 0 : break;
1692 : case RADEON_RB3D_COLORPITCH:
1693 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1694 0 : if (r) {
1695 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1696 : idx, reg);
1697 0 : radeon_cs_dump_packet(p, pkt);
1698 0 : return r;
1699 : }
1700 0 : if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1701 0 : if (reloc->tiling_flags & RADEON_TILING_MACRO)
1702 0 : tile_flags |= RADEON_COLOR_TILE_ENABLE;
1703 0 : if (reloc->tiling_flags & RADEON_TILING_MICRO)
1704 0 : tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1705 :
1706 0 : tmp = idx_value & ~(0x7 << 16);
1707 0 : tmp |= tile_flags;
1708 0 : ib[idx] = tmp;
1709 0 : } else
1710 0 : ib[idx] = idx_value;
1711 :
1712 0 : track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1713 0 : track->cb_dirty = true;
1714 0 : break;
1715 : case RADEON_RB3D_DEPTHPITCH:
1716 0 : track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1717 0 : track->zb_dirty = true;
1718 0 : break;
1719 : case RADEON_RB3D_CNTL:
1720 0 : switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1721 : case 7:
1722 : case 8:
1723 : case 9:
1724 : case 11:
1725 : case 12:
1726 0 : track->cb[0].cpp = 1;
1727 0 : break;
1728 : case 3:
1729 : case 4:
1730 : case 15:
1731 0 : track->cb[0].cpp = 2;
1732 0 : break;
1733 : case 6:
1734 0 : track->cb[0].cpp = 4;
1735 0 : break;
1736 : default:
1737 0 : DRM_ERROR("Invalid color buffer format (%d) !\n",
1738 : ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1739 0 : return -EINVAL;
1740 : }
1741 0 : track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1742 0 : track->cb_dirty = true;
1743 0 : track->zb_dirty = true;
1744 0 : break;
1745 : case RADEON_RB3D_ZSTENCILCNTL:
1746 0 : switch (idx_value & 0xf) {
1747 : case 0:
1748 0 : track->zb.cpp = 2;
1749 0 : break;
1750 : case 2:
1751 : case 3:
1752 : case 4:
1753 : case 5:
1754 : case 9:
1755 : case 11:
1756 0 : track->zb.cpp = 4;
1757 0 : break;
1758 : default:
1759 : break;
1760 : }
1761 0 : track->zb_dirty = true;
1762 0 : break;
1763 : case RADEON_RB3D_ZPASS_ADDR:
1764 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1765 0 : if (r) {
1766 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1767 : idx, reg);
1768 0 : radeon_cs_dump_packet(p, pkt);
1769 0 : return r;
1770 : }
1771 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1772 0 : break;
1773 : case RADEON_PP_CNTL:
1774 : {
1775 0 : uint32_t temp = idx_value >> 4;
1776 0 : for (i = 0; i < track->num_texture; i++)
1777 0 : track->textures[i].enabled = !!(temp & (1 << i));
1778 0 : track->tex_dirty = true;
1779 : }
1780 0 : break;
1781 : case RADEON_SE_VF_CNTL:
1782 0 : track->vap_vf_cntl = idx_value;
1783 0 : break;
1784 : case RADEON_SE_VTX_FMT:
1785 0 : track->vtx_size = r100_get_vtx_size(idx_value);
1786 0 : break;
1787 : case RADEON_PP_TEX_SIZE_0:
1788 : case RADEON_PP_TEX_SIZE_1:
1789 : case RADEON_PP_TEX_SIZE_2:
1790 0 : i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1791 0 : track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1792 0 : track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1793 0 : track->tex_dirty = true;
1794 0 : break;
1795 : case RADEON_PP_TEX_PITCH_0:
1796 : case RADEON_PP_TEX_PITCH_1:
1797 : case RADEON_PP_TEX_PITCH_2:
1798 0 : i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1799 0 : track->textures[i].pitch = idx_value + 32;
1800 0 : track->tex_dirty = true;
1801 0 : break;
1802 : case RADEON_PP_TXFILTER_0:
1803 : case RADEON_PP_TXFILTER_1:
1804 : case RADEON_PP_TXFILTER_2:
1805 0 : i = (reg - RADEON_PP_TXFILTER_0) / 24;
1806 0 : track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1807 0 : >> RADEON_MAX_MIP_LEVEL_SHIFT);
1808 0 : tmp = (idx_value >> 23) & 0x7;
1809 0 : if (tmp == 2 || tmp == 6)
1810 0 : track->textures[i].roundup_w = false;
1811 0 : tmp = (idx_value >> 27) & 0x7;
1812 0 : if (tmp == 2 || tmp == 6)
1813 0 : track->textures[i].roundup_h = false;
1814 0 : track->tex_dirty = true;
1815 0 : break;
1816 : case RADEON_PP_TXFORMAT_0:
1817 : case RADEON_PP_TXFORMAT_1:
1818 : case RADEON_PP_TXFORMAT_2:
1819 0 : i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1820 0 : if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1821 0 : track->textures[i].use_pitch = 1;
1822 0 : } else {
1823 0 : track->textures[i].use_pitch = 0;
1824 0 : track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1825 0 : track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1826 : }
1827 0 : if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1828 0 : track->textures[i].tex_coord_type = 2;
1829 0 : switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1830 : case RADEON_TXFORMAT_I8:
1831 : case RADEON_TXFORMAT_RGB332:
1832 : case RADEON_TXFORMAT_Y8:
1833 0 : track->textures[i].cpp = 1;
1834 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1835 0 : break;
1836 : case RADEON_TXFORMAT_AI88:
1837 : case RADEON_TXFORMAT_ARGB1555:
1838 : case RADEON_TXFORMAT_RGB565:
1839 : case RADEON_TXFORMAT_ARGB4444:
1840 : case RADEON_TXFORMAT_VYUY422:
1841 : case RADEON_TXFORMAT_YVYU422:
1842 : case RADEON_TXFORMAT_SHADOW16:
1843 : case RADEON_TXFORMAT_LDUDV655:
1844 : case RADEON_TXFORMAT_DUDV88:
1845 0 : track->textures[i].cpp = 2;
1846 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1847 0 : break;
1848 : case RADEON_TXFORMAT_ARGB8888:
1849 : case RADEON_TXFORMAT_RGBA8888:
1850 : case RADEON_TXFORMAT_SHADOW32:
1851 : case RADEON_TXFORMAT_LDUDUV8888:
1852 0 : track->textures[i].cpp = 4;
1853 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1854 0 : break;
1855 : case RADEON_TXFORMAT_DXT1:
1856 0 : track->textures[i].cpp = 1;
1857 0 : track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1858 0 : break;
1859 : case RADEON_TXFORMAT_DXT23:
1860 : case RADEON_TXFORMAT_DXT45:
1861 0 : track->textures[i].cpp = 1;
1862 0 : track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1863 0 : break;
1864 : }
1865 0 : track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1866 0 : track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1867 0 : track->tex_dirty = true;
1868 0 : break;
1869 : case RADEON_PP_CUBIC_FACES_0:
1870 : case RADEON_PP_CUBIC_FACES_1:
1871 : case RADEON_PP_CUBIC_FACES_2:
1872 : tmp = idx_value;
1873 0 : i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1874 0 : for (face = 0; face < 4; face++) {
1875 0 : track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1876 0 : track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1877 : }
1878 0 : track->tex_dirty = true;
1879 0 : break;
1880 : default:
1881 0 : printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1882 : reg, idx);
1883 0 : return -EINVAL;
1884 : }
1885 0 : return 0;
1886 0 : }
1887 :
1888 0 : int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1889 : struct radeon_cs_packet *pkt,
1890 : struct radeon_bo *robj)
1891 : {
1892 : unsigned idx;
1893 : u32 value;
1894 0 : idx = pkt->idx + 1;
1895 0 : value = radeon_get_ib_value(p, idx + 2);
1896 0 : if ((value + 1) > radeon_bo_size(robj)) {
1897 0 : DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1898 : "(need %u have %lu) !\n",
1899 : value + 1,
1900 : radeon_bo_size(robj));
1901 0 : return -EINVAL;
1902 : }
1903 0 : return 0;
1904 0 : }
1905 :
1906 0 : static int r100_packet3_check(struct radeon_cs_parser *p,
1907 : struct radeon_cs_packet *pkt)
1908 : {
1909 0 : struct radeon_bo_list *reloc;
1910 : struct r100_cs_track *track;
1911 : unsigned idx;
1912 : volatile uint32_t *ib;
1913 : int r;
1914 :
1915 0 : ib = p->ib.ptr;
1916 0 : idx = pkt->idx + 1;
1917 0 : track = (struct r100_cs_track *)p->track;
1918 0 : switch (pkt->opcode) {
1919 : case PACKET3_3D_LOAD_VBPNTR:
1920 0 : r = r100_packet3_load_vbpntr(p, pkt, idx);
1921 0 : if (r)
1922 0 : return r;
1923 : break;
1924 : case PACKET3_INDX_BUFFER:
1925 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1926 0 : if (r) {
1927 0 : DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1928 0 : radeon_cs_dump_packet(p, pkt);
1929 0 : return r;
1930 : }
1931 0 : ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1932 0 : r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1933 0 : if (r) {
1934 0 : return r;
1935 : }
1936 : break;
1937 : case 0x23:
1938 : /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1939 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1940 0 : if (r) {
1941 0 : DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1942 0 : radeon_cs_dump_packet(p, pkt);
1943 0 : return r;
1944 : }
1945 0 : ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1946 0 : track->num_arrays = 1;
1947 0 : track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1948 :
1949 0 : track->arrays[0].robj = reloc->robj;
1950 0 : track->arrays[0].esize = track->vtx_size;
1951 :
1952 0 : track->max_indx = radeon_get_ib_value(p, idx+1);
1953 :
1954 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1955 0 : track->immd_dwords = pkt->count - 1;
1956 0 : r = r100_cs_track_check(p->rdev, track);
1957 0 : if (r)
1958 0 : return r;
1959 : break;
1960 : case PACKET3_3D_DRAW_IMMD:
1961 0 : if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1962 0 : DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1963 0 : return -EINVAL;
1964 : }
1965 0 : track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1966 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1967 0 : track->immd_dwords = pkt->count - 1;
1968 0 : r = r100_cs_track_check(p->rdev, track);
1969 0 : if (r)
1970 0 : return r;
1971 : break;
1972 : /* triggers drawing using in-packet vertex data */
1973 : case PACKET3_3D_DRAW_IMMD_2:
1974 0 : if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1975 0 : DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1976 0 : return -EINVAL;
1977 : }
1978 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1979 0 : track->immd_dwords = pkt->count;
1980 0 : r = r100_cs_track_check(p->rdev, track);
1981 0 : if (r)
1982 0 : return r;
1983 : break;
1984 : /* triggers drawing using in-packet vertex data */
1985 : case PACKET3_3D_DRAW_VBUF_2:
1986 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1987 0 : r = r100_cs_track_check(p->rdev, track);
1988 0 : if (r)
1989 0 : return r;
1990 : break;
1991 : /* triggers drawing of vertex buffers setup elsewhere */
1992 : case PACKET3_3D_DRAW_INDX_2:
1993 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1994 0 : r = r100_cs_track_check(p->rdev, track);
1995 0 : if (r)
1996 0 : return r;
1997 : break;
1998 : /* triggers drawing using indices to vertex buffer */
1999 : case PACKET3_3D_DRAW_VBUF:
2000 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2001 0 : r = r100_cs_track_check(p->rdev, track);
2002 0 : if (r)
2003 0 : return r;
2004 : break;
2005 : /* triggers drawing of vertex buffers setup elsewhere */
2006 : case PACKET3_3D_DRAW_INDX:
2007 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2008 0 : r = r100_cs_track_check(p->rdev, track);
2009 0 : if (r)
2010 0 : return r;
2011 : break;
2012 : /* triggers drawing using indices to vertex buffer */
2013 : case PACKET3_3D_CLEAR_HIZ:
2014 : case PACKET3_3D_CLEAR_ZMASK:
2015 0 : if (p->rdev->hyperz_filp != p->filp)
2016 0 : return -EINVAL;
2017 : break;
2018 : case PACKET3_NOP:
2019 : break;
2020 : default:
2021 0 : DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2022 0 : return -EINVAL;
2023 : }
2024 0 : return 0;
2025 0 : }
2026 :
2027 0 : int r100_cs_parse(struct radeon_cs_parser *p)
2028 : {
2029 0 : struct radeon_cs_packet pkt;
2030 : struct r100_cs_track *track;
2031 : int r;
2032 :
2033 0 : track = kzalloc(sizeof(*track), GFP_KERNEL);
2034 0 : if (!track)
2035 0 : return -ENOMEM;
2036 0 : r100_cs_track_clear(p->rdev, track);
2037 0 : p->track = track;
2038 0 : do {
2039 0 : r = radeon_cs_packet_parse(p, &pkt, p->idx);
2040 0 : if (r) {
2041 0 : return r;
2042 : }
2043 0 : p->idx += pkt.count + 2;
2044 0 : switch (pkt.type) {
2045 : case RADEON_PACKET_TYPE0:
2046 0 : if (p->rdev->family >= CHIP_R200)
2047 0 : r = r100_cs_parse_packet0(p, &pkt,
2048 : p->rdev->config.r100.reg_safe_bm,
2049 : p->rdev->config.r100.reg_safe_bm_size,
2050 : &r200_packet0_check);
2051 : else
2052 0 : r = r100_cs_parse_packet0(p, &pkt,
2053 : p->rdev->config.r100.reg_safe_bm,
2054 : p->rdev->config.r100.reg_safe_bm_size,
2055 : &r100_packet0_check);
2056 : break;
2057 : case RADEON_PACKET_TYPE2:
2058 : break;
2059 : case RADEON_PACKET_TYPE3:
2060 0 : r = r100_packet3_check(p, &pkt);
2061 0 : break;
2062 : default:
2063 0 : DRM_ERROR("Unknown packet type %d !\n",
2064 : pkt.type);
2065 0 : return -EINVAL;
2066 : }
2067 0 : if (r)
2068 0 : return r;
2069 0 : } while (p->idx < p->chunk_ib->length_dw);
2070 0 : return 0;
2071 0 : }
2072 :
2073 0 : static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2074 : {
2075 0 : DRM_ERROR("pitch %d\n", t->pitch);
2076 0 : DRM_ERROR("use_pitch %d\n", t->use_pitch);
2077 0 : DRM_ERROR("width %d\n", t->width);
2078 0 : DRM_ERROR("width_11 %d\n", t->width_11);
2079 0 : DRM_ERROR("height %d\n", t->height);
2080 0 : DRM_ERROR("height_11 %d\n", t->height_11);
2081 0 : DRM_ERROR("num levels %d\n", t->num_levels);
2082 0 : DRM_ERROR("depth %d\n", t->txdepth);
2083 0 : DRM_ERROR("bpp %d\n", t->cpp);
2084 0 : DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2085 0 : DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2086 0 : DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2087 0 : DRM_ERROR("compress format %d\n", t->compress_format);
2088 0 : }
2089 :
2090 0 : static int r100_track_compress_size(int compress_format, int w, int h)
2091 : {
2092 : int block_width, block_height, block_bytes;
2093 : int wblocks, hblocks;
2094 : int min_wblocks;
2095 : int sz;
2096 :
2097 : block_width = 4;
2098 : block_height = 4;
2099 :
2100 0 : switch (compress_format) {
2101 : case R100_TRACK_COMP_DXT1:
2102 : block_bytes = 8;
2103 : min_wblocks = 4;
2104 0 : break;
2105 : default:
2106 : case R100_TRACK_COMP_DXT35:
2107 : block_bytes = 16;
2108 : min_wblocks = 2;
2109 0 : break;
2110 : }
2111 :
2112 0 : hblocks = (h + block_height - 1) / block_height;
2113 0 : wblocks = (w + block_width - 1) / block_width;
2114 0 : if (wblocks < min_wblocks)
2115 0 : wblocks = min_wblocks;
2116 0 : sz = wblocks * hblocks * block_bytes;
2117 0 : return sz;
2118 : }
2119 :
2120 0 : static int r100_cs_track_cube(struct radeon_device *rdev,
2121 : struct r100_cs_track *track, unsigned idx)
2122 : {
2123 : unsigned face, w, h;
2124 : struct radeon_bo *cube_robj;
2125 : unsigned long size;
2126 0 : unsigned compress_format = track->textures[idx].compress_format;
2127 :
2128 0 : for (face = 0; face < 5; face++) {
2129 0 : cube_robj = track->textures[idx].cube_info[face].robj;
2130 0 : w = track->textures[idx].cube_info[face].width;
2131 0 : h = track->textures[idx].cube_info[face].height;
2132 :
2133 0 : if (compress_format) {
2134 0 : size = r100_track_compress_size(compress_format, w, h);
2135 0 : } else
2136 0 : size = w * h;
2137 0 : size *= track->textures[idx].cpp;
2138 :
2139 0 : size += track->textures[idx].cube_info[face].offset;
2140 :
2141 0 : if (size > radeon_bo_size(cube_robj)) {
2142 0 : DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2143 : size, radeon_bo_size(cube_robj));
2144 0 : r100_cs_track_texture_print(&track->textures[idx]);
2145 0 : return -1;
2146 : }
2147 : }
2148 0 : return 0;
2149 0 : }
2150 :
2151 0 : static int r100_cs_track_texture_check(struct radeon_device *rdev,
2152 : struct r100_cs_track *track)
2153 : {
2154 : struct radeon_bo *robj;
2155 : unsigned long size;
2156 : unsigned u, i, w, h, d;
2157 : int ret;
2158 :
2159 0 : for (u = 0; u < track->num_texture; u++) {
2160 0 : if (!track->textures[u].enabled)
2161 : continue;
2162 0 : if (track->textures[u].lookup_disable)
2163 : continue;
2164 0 : robj = track->textures[u].robj;
2165 0 : if (robj == NULL) {
2166 0 : DRM_ERROR("No texture bound to unit %u\n", u);
2167 0 : return -EINVAL;
2168 : }
2169 : size = 0;
2170 0 : for (i = 0; i <= track->textures[u].num_levels; i++) {
2171 0 : if (track->textures[u].use_pitch) {
2172 0 : if (rdev->family < CHIP_R300)
2173 0 : w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2174 : else
2175 0 : w = track->textures[u].pitch / (1 << i);
2176 : } else {
2177 0 : w = track->textures[u].width;
2178 0 : if (rdev->family >= CHIP_RV515)
2179 0 : w |= track->textures[u].width_11;
2180 0 : w = w / (1 << i);
2181 0 : if (track->textures[u].roundup_w)
2182 0 : w = roundup_pow_of_two(w);
2183 : }
2184 0 : h = track->textures[u].height;
2185 0 : if (rdev->family >= CHIP_RV515)
2186 0 : h |= track->textures[u].height_11;
2187 0 : h = h / (1 << i);
2188 0 : if (track->textures[u].roundup_h)
2189 0 : h = roundup_pow_of_two(h);
2190 0 : if (track->textures[u].tex_coord_type == 1) {
2191 0 : d = (1 << track->textures[u].txdepth) / (1 << i);
2192 0 : if (!d)
2193 : d = 1;
2194 0 : } else {
2195 : d = 1;
2196 : }
2197 0 : if (track->textures[u].compress_format) {
2198 :
2199 0 : size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2200 : /* compressed textures are block based */
2201 0 : } else
2202 0 : size += w * h * d;
2203 : }
2204 0 : size *= track->textures[u].cpp;
2205 :
2206 0 : switch (track->textures[u].tex_coord_type) {
2207 : case 0:
2208 : case 1:
2209 : break;
2210 : case 2:
2211 0 : if (track->separate_cube) {
2212 0 : ret = r100_cs_track_cube(rdev, track, u);
2213 0 : if (ret)
2214 0 : return ret;
2215 : } else
2216 0 : size *= 6;
2217 : break;
2218 : default:
2219 0 : DRM_ERROR("Invalid texture coordinate type %u for unit "
2220 : "%u\n", track->textures[u].tex_coord_type, u);
2221 0 : return -EINVAL;
2222 : }
2223 0 : if (size > radeon_bo_size(robj)) {
2224 0 : DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2225 : "%lu\n", u, size, radeon_bo_size(robj));
2226 0 : r100_cs_track_texture_print(&track->textures[u]);
2227 0 : return -EINVAL;
2228 : }
2229 : }
2230 0 : return 0;
2231 0 : }
2232 :
2233 0 : int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2234 : {
2235 : unsigned i;
2236 : unsigned long size;
2237 : unsigned prim_walk;
2238 : unsigned nverts;
2239 0 : unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2240 :
2241 0 : if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2242 0 : !track->blend_read_enable)
2243 0 : num_cb = 0;
2244 :
2245 0 : for (i = 0; i < num_cb; i++) {
2246 0 : if (track->cb[i].robj == NULL) {
2247 0 : DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2248 0 : return -EINVAL;
2249 : }
2250 0 : size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2251 0 : size += track->cb[i].offset;
2252 0 : if (size > radeon_bo_size(track->cb[i].robj)) {
2253 0 : DRM_ERROR("[drm] Buffer too small for color buffer %d "
2254 : "(need %lu have %lu) !\n", i, size,
2255 : radeon_bo_size(track->cb[i].robj));
2256 0 : DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2257 : i, track->cb[i].pitch, track->cb[i].cpp,
2258 : track->cb[i].offset, track->maxy);
2259 0 : return -EINVAL;
2260 : }
2261 : }
2262 0 : track->cb_dirty = false;
2263 :
2264 0 : if (track->zb_dirty && track->z_enabled) {
2265 0 : if (track->zb.robj == NULL) {
2266 0 : DRM_ERROR("[drm] No buffer for z buffer !\n");
2267 0 : return -EINVAL;
2268 : }
2269 0 : size = track->zb.pitch * track->zb.cpp * track->maxy;
2270 0 : size += track->zb.offset;
2271 0 : if (size > radeon_bo_size(track->zb.robj)) {
2272 0 : DRM_ERROR("[drm] Buffer too small for z buffer "
2273 : "(need %lu have %lu) !\n", size,
2274 : radeon_bo_size(track->zb.robj));
2275 0 : DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2276 : track->zb.pitch, track->zb.cpp,
2277 : track->zb.offset, track->maxy);
2278 0 : return -EINVAL;
2279 : }
2280 : }
2281 0 : track->zb_dirty = false;
2282 :
2283 0 : if (track->aa_dirty && track->aaresolve) {
2284 0 : if (track->aa.robj == NULL) {
2285 0 : DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2286 0 : return -EINVAL;
2287 : }
2288 : /* I believe the format comes from colorbuffer0. */
2289 0 : size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2290 0 : size += track->aa.offset;
2291 0 : if (size > radeon_bo_size(track->aa.robj)) {
2292 0 : DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2293 : "(need %lu have %lu) !\n", i, size,
2294 : radeon_bo_size(track->aa.robj));
2295 0 : DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2296 : i, track->aa.pitch, track->cb[0].cpp,
2297 : track->aa.offset, track->maxy);
2298 0 : return -EINVAL;
2299 : }
2300 : }
2301 0 : track->aa_dirty = false;
2302 :
2303 0 : prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2304 0 : if (track->vap_vf_cntl & (1 << 14)) {
2305 0 : nverts = track->vap_alt_nverts;
2306 0 : } else {
2307 0 : nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2308 : }
2309 0 : switch (prim_walk) {
2310 : case 1:
2311 0 : for (i = 0; i < track->num_arrays; i++) {
2312 0 : size = track->arrays[i].esize * track->max_indx * 4;
2313 0 : if (track->arrays[i].robj == NULL) {
2314 0 : DRM_ERROR("(PW %u) Vertex array %u no buffer "
2315 : "bound\n", prim_walk, i);
2316 0 : return -EINVAL;
2317 : }
2318 0 : if (size > radeon_bo_size(track->arrays[i].robj)) {
2319 0 : dev_err(rdev->dev, "(PW %u) Vertex array %u "
2320 : "need %lu dwords have %lu dwords\n",
2321 : prim_walk, i, size >> 2,
2322 : radeon_bo_size(track->arrays[i].robj)
2323 : >> 2);
2324 0 : DRM_ERROR("Max indices %u\n", track->max_indx);
2325 0 : return -EINVAL;
2326 : }
2327 : }
2328 : break;
2329 : case 2:
2330 0 : for (i = 0; i < track->num_arrays; i++) {
2331 0 : size = track->arrays[i].esize * (nverts - 1) * 4;
2332 0 : if (track->arrays[i].robj == NULL) {
2333 0 : DRM_ERROR("(PW %u) Vertex array %u no buffer "
2334 : "bound\n", prim_walk, i);
2335 0 : return -EINVAL;
2336 : }
2337 0 : if (size > radeon_bo_size(track->arrays[i].robj)) {
2338 0 : dev_err(rdev->dev, "(PW %u) Vertex array %u "
2339 : "need %lu dwords have %lu dwords\n",
2340 : prim_walk, i, size >> 2,
2341 : radeon_bo_size(track->arrays[i].robj)
2342 : >> 2);
2343 0 : return -EINVAL;
2344 : }
2345 : }
2346 : break;
2347 : case 3:
2348 0 : size = track->vtx_size * nverts;
2349 0 : if (size != track->immd_dwords) {
2350 0 : DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2351 : track->immd_dwords, size);
2352 0 : DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2353 : nverts, track->vtx_size);
2354 0 : return -EINVAL;
2355 : }
2356 : break;
2357 : default:
2358 0 : DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2359 : prim_walk);
2360 0 : return -EINVAL;
2361 : }
2362 :
2363 0 : if (track->tex_dirty) {
2364 0 : track->tex_dirty = false;
2365 0 : return r100_cs_track_texture_check(rdev, track);
2366 : }
2367 0 : return 0;
2368 0 : }
2369 :
2370 0 : void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2371 : {
2372 : unsigned i, face;
2373 :
2374 0 : track->cb_dirty = true;
2375 0 : track->zb_dirty = true;
2376 0 : track->tex_dirty = true;
2377 0 : track->aa_dirty = true;
2378 :
2379 0 : if (rdev->family < CHIP_R300) {
2380 0 : track->num_cb = 1;
2381 0 : if (rdev->family <= CHIP_RS200)
2382 0 : track->num_texture = 3;
2383 : else
2384 0 : track->num_texture = 6;
2385 0 : track->maxy = 2048;
2386 0 : track->separate_cube = 1;
2387 0 : } else {
2388 0 : track->num_cb = 4;
2389 0 : track->num_texture = 16;
2390 0 : track->maxy = 4096;
2391 0 : track->separate_cube = 0;
2392 0 : track->aaresolve = false;
2393 0 : track->aa.robj = NULL;
2394 : }
2395 :
2396 0 : for (i = 0; i < track->num_cb; i++) {
2397 0 : track->cb[i].robj = NULL;
2398 0 : track->cb[i].pitch = 8192;
2399 0 : track->cb[i].cpp = 16;
2400 0 : track->cb[i].offset = 0;
2401 : }
2402 0 : track->z_enabled = true;
2403 0 : track->zb.robj = NULL;
2404 0 : track->zb.pitch = 8192;
2405 0 : track->zb.cpp = 4;
2406 0 : track->zb.offset = 0;
2407 0 : track->vtx_size = 0x7F;
2408 0 : track->immd_dwords = 0xFFFFFFFFUL;
2409 0 : track->num_arrays = 11;
2410 0 : track->max_indx = 0x00FFFFFFUL;
2411 0 : for (i = 0; i < track->num_arrays; i++) {
2412 0 : track->arrays[i].robj = NULL;
2413 0 : track->arrays[i].esize = 0x7F;
2414 : }
2415 0 : for (i = 0; i < track->num_texture; i++) {
2416 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2417 0 : track->textures[i].pitch = 16536;
2418 0 : track->textures[i].width = 16536;
2419 0 : track->textures[i].height = 16536;
2420 0 : track->textures[i].width_11 = 1 << 11;
2421 0 : track->textures[i].height_11 = 1 << 11;
2422 0 : track->textures[i].num_levels = 12;
2423 0 : if (rdev->family <= CHIP_RS200) {
2424 0 : track->textures[i].tex_coord_type = 0;
2425 0 : track->textures[i].txdepth = 0;
2426 0 : } else {
2427 0 : track->textures[i].txdepth = 16;
2428 0 : track->textures[i].tex_coord_type = 1;
2429 : }
2430 0 : track->textures[i].cpp = 64;
2431 0 : track->textures[i].robj = NULL;
2432 : /* CS IB emission code makes sure texture unit are disabled */
2433 0 : track->textures[i].enabled = false;
2434 0 : track->textures[i].lookup_disable = false;
2435 0 : track->textures[i].roundup_w = true;
2436 0 : track->textures[i].roundup_h = true;
2437 0 : if (track->separate_cube)
2438 0 : for (face = 0; face < 5; face++) {
2439 0 : track->textures[i].cube_info[face].robj = NULL;
2440 0 : track->textures[i].cube_info[face].width = 16536;
2441 0 : track->textures[i].cube_info[face].height = 16536;
2442 0 : track->textures[i].cube_info[face].offset = 0;
2443 : }
2444 : }
2445 0 : }
2446 :
2447 : /*
2448 : * Global GPU functions
2449 : */
2450 0 : static void r100_errata(struct radeon_device *rdev)
2451 : {
2452 0 : rdev->pll_errata = 0;
2453 :
2454 0 : if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2455 0 : rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2456 0 : }
2457 :
2458 0 : if (rdev->family == CHIP_RV100 ||
2459 0 : rdev->family == CHIP_RS100 ||
2460 0 : rdev->family == CHIP_RS200) {
2461 0 : rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2462 0 : }
2463 0 : }
2464 :
2465 0 : static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2466 : {
2467 : unsigned i;
2468 : uint32_t tmp;
2469 :
2470 0 : for (i = 0; i < rdev->usec_timeout; i++) {
2471 0 : tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2472 0 : if (tmp >= n) {
2473 0 : return 0;
2474 : }
2475 0 : DRM_UDELAY(1);
2476 : }
2477 0 : return -1;
2478 0 : }
2479 :
2480 0 : int r100_gui_wait_for_idle(struct radeon_device *rdev)
2481 : {
2482 : unsigned i;
2483 : uint32_t tmp;
2484 :
2485 0 : if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2486 0 : printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2487 : " Bad things might happen.\n");
2488 0 : }
2489 0 : for (i = 0; i < rdev->usec_timeout; i++) {
2490 0 : tmp = RREG32(RADEON_RBBM_STATUS);
2491 0 : if (!(tmp & RADEON_RBBM_ACTIVE)) {
2492 0 : return 0;
2493 : }
2494 0 : DRM_UDELAY(1);
2495 : }
2496 0 : return -1;
2497 0 : }
2498 :
2499 0 : int r100_mc_wait_for_idle(struct radeon_device *rdev)
2500 : {
2501 : unsigned i;
2502 : uint32_t tmp;
2503 :
2504 0 : for (i = 0; i < rdev->usec_timeout; i++) {
2505 : /* read MC_STATUS */
2506 0 : tmp = RREG32(RADEON_MC_STATUS);
2507 0 : if (tmp & RADEON_MC_IDLE) {
2508 0 : return 0;
2509 : }
2510 0 : DRM_UDELAY(1);
2511 : }
2512 0 : return -1;
2513 0 : }
2514 :
2515 0 : bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2516 : {
2517 : u32 rbbm_status;
2518 :
2519 0 : rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2520 0 : if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2521 0 : radeon_ring_lockup_update(rdev, ring);
2522 0 : return false;
2523 : }
2524 0 : return radeon_ring_test_lockup(rdev, ring);
2525 0 : }
2526 :
2527 : /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2528 0 : void r100_enable_bm(struct radeon_device *rdev)
2529 : {
2530 : uint32_t tmp;
2531 : /* Enable bus mastering */
2532 0 : tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2533 0 : WREG32(RADEON_BUS_CNTL, tmp);
2534 0 : }
2535 :
2536 0 : void r100_bm_disable(struct radeon_device *rdev)
2537 : {
2538 : u32 tmp;
2539 :
2540 : /* disable bus mastering */
2541 0 : tmp = RREG32(R_000030_BUS_CNTL);
2542 0 : WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2543 0 : mdelay(1);
2544 0 : WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2545 0 : mdelay(1);
2546 0 : WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2547 0 : tmp = RREG32(RADEON_BUS_CNTL);
2548 0 : mdelay(1);
2549 : pci_clear_master(rdev->pdev);
2550 0 : mdelay(1);
2551 0 : }
2552 :
2553 0 : int r100_asic_reset(struct radeon_device *rdev)
2554 : {
2555 0 : struct r100_mc_save save;
2556 : u32 status, tmp;
2557 : int ret = 0;
2558 :
2559 0 : status = RREG32(R_000E40_RBBM_STATUS);
2560 0 : if (!G_000E40_GUI_ACTIVE(status)) {
2561 0 : return 0;
2562 : }
2563 0 : r100_mc_stop(rdev, &save);
2564 0 : status = RREG32(R_000E40_RBBM_STATUS);
2565 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2566 : /* stop CP */
2567 0 : WREG32(RADEON_CP_CSQ_CNTL, 0);
2568 0 : tmp = RREG32(RADEON_CP_RB_CNTL);
2569 0 : WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2570 0 : WREG32(RADEON_CP_RB_RPTR_WR, 0);
2571 0 : WREG32(RADEON_CP_RB_WPTR, 0);
2572 0 : WREG32(RADEON_CP_RB_CNTL, tmp);
2573 : /* save PCI state */
2574 : pci_save_state(rdev->pdev);
2575 : /* disable bus mastering */
2576 0 : r100_bm_disable(rdev);
2577 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2578 : S_0000F0_SOFT_RESET_RE(1) |
2579 : S_0000F0_SOFT_RESET_PP(1) |
2580 : S_0000F0_SOFT_RESET_RB(1));
2581 0 : RREG32(R_0000F0_RBBM_SOFT_RESET);
2582 0 : mdelay(500);
2583 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2584 0 : mdelay(1);
2585 0 : status = RREG32(R_000E40_RBBM_STATUS);
2586 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2587 : /* reset CP */
2588 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2589 0 : RREG32(R_0000F0_RBBM_SOFT_RESET);
2590 0 : mdelay(500);
2591 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2592 0 : mdelay(1);
2593 0 : status = RREG32(R_000E40_RBBM_STATUS);
2594 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2595 : /* restore PCI & busmastering */
2596 : pci_restore_state(rdev->pdev);
2597 0 : r100_enable_bm(rdev);
2598 : /* Check if GPU is idle */
2599 0 : if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2600 0 : G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2601 0 : dev_err(rdev->dev, "failed to reset GPU\n");
2602 : ret = -1;
2603 0 : } else
2604 : dev_info(rdev->dev, "GPU reset succeed\n");
2605 0 : r100_mc_resume(rdev, &save);
2606 0 : return ret;
2607 0 : }
2608 :
2609 0 : void r100_set_common_regs(struct radeon_device *rdev)
2610 : {
2611 0 : struct drm_device *dev = rdev->ddev;
2612 : bool force_dac2 = false;
2613 : u32 tmp;
2614 :
2615 : /* set these so they don't interfere with anything */
2616 0 : WREG32(RADEON_OV0_SCALE_CNTL, 0);
2617 0 : WREG32(RADEON_SUBPIC_CNTL, 0);
2618 0 : WREG32(RADEON_VIPH_CONTROL, 0);
2619 0 : WREG32(RADEON_I2C_CNTL_1, 0);
2620 0 : WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2621 0 : WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2622 0 : WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2623 :
2624 : /* always set up dac2 on rn50 and some rv100 as lots
2625 : * of servers seem to wire it up to a VGA port but
2626 : * don't report it in the bios connector
2627 : * table.
2628 : */
2629 0 : switch (dev->pdev->device) {
2630 : /* RN50 */
2631 : case 0x515e:
2632 : case 0x5969:
2633 : force_dac2 = true;
2634 0 : break;
2635 : /* RV100*/
2636 : case 0x5159:
2637 : case 0x515a:
2638 : /* DELL triple head servers */
2639 0 : if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2640 0 : ((dev->pdev->subsystem_device == 0x016c) ||
2641 0 : (dev->pdev->subsystem_device == 0x016d) ||
2642 0 : (dev->pdev->subsystem_device == 0x016e) ||
2643 0 : (dev->pdev->subsystem_device == 0x016f) ||
2644 0 : (dev->pdev->subsystem_device == 0x0170) ||
2645 0 : (dev->pdev->subsystem_device == 0x017d) ||
2646 0 : (dev->pdev->subsystem_device == 0x017e) ||
2647 0 : (dev->pdev->subsystem_device == 0x0183) ||
2648 0 : (dev->pdev->subsystem_device == 0x018a) ||
2649 0 : (dev->pdev->subsystem_device == 0x019a)))
2650 0 : force_dac2 = true;
2651 : break;
2652 : }
2653 :
2654 0 : if (force_dac2) {
2655 0 : u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2656 0 : u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2657 0 : u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2658 :
2659 : /* For CRT on DAC2, don't turn it on if BIOS didn't
2660 : enable it, even it's detected.
2661 : */
2662 :
2663 : /* force it to crtc0 */
2664 0 : dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2665 0 : dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2666 0 : disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2667 :
2668 : /* set up the TV DAC */
2669 0 : tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2670 : RADEON_TV_DAC_STD_MASK |
2671 : RADEON_TV_DAC_RDACPD |
2672 : RADEON_TV_DAC_GDACPD |
2673 : RADEON_TV_DAC_BDACPD |
2674 : RADEON_TV_DAC_BGADJ_MASK |
2675 : RADEON_TV_DAC_DACADJ_MASK);
2676 0 : tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2677 : RADEON_TV_DAC_NHOLD |
2678 : RADEON_TV_DAC_STD_PS2 |
2679 : (0x58 << 16));
2680 :
2681 0 : WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2682 0 : WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2683 0 : WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2684 0 : }
2685 :
2686 : /* switch PM block to ACPI mode */
2687 0 : tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2688 0 : tmp &= ~RADEON_PM_MODE_SEL;
2689 0 : WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2690 :
2691 0 : }
2692 :
2693 : /*
2694 : * VRAM info
2695 : */
2696 0 : static void r100_vram_get_type(struct radeon_device *rdev)
2697 : {
2698 : uint32_t tmp;
2699 :
2700 0 : rdev->mc.vram_is_ddr = false;
2701 0 : if (rdev->flags & RADEON_IS_IGP)
2702 0 : rdev->mc.vram_is_ddr = true;
2703 0 : else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2704 0 : rdev->mc.vram_is_ddr = true;
2705 0 : if ((rdev->family == CHIP_RV100) ||
2706 0 : (rdev->family == CHIP_RS100) ||
2707 0 : (rdev->family == CHIP_RS200)) {
2708 0 : tmp = RREG32(RADEON_MEM_CNTL);
2709 0 : if (tmp & RV100_HALF_MODE) {
2710 0 : rdev->mc.vram_width = 32;
2711 0 : } else {
2712 0 : rdev->mc.vram_width = 64;
2713 : }
2714 0 : if (rdev->flags & RADEON_SINGLE_CRTC) {
2715 0 : rdev->mc.vram_width /= 4;
2716 0 : rdev->mc.vram_is_ddr = true;
2717 0 : }
2718 0 : } else if (rdev->family <= CHIP_RV280) {
2719 0 : tmp = RREG32(RADEON_MEM_CNTL);
2720 0 : if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2721 0 : rdev->mc.vram_width = 128;
2722 0 : } else {
2723 0 : rdev->mc.vram_width = 64;
2724 : }
2725 : } else {
2726 : /* newer IGPs */
2727 0 : rdev->mc.vram_width = 128;
2728 : }
2729 0 : }
2730 :
2731 0 : static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2732 : {
2733 : u32 aper_size;
2734 0 : u8 byte;
2735 :
2736 0 : aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2737 :
2738 : /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2739 : * that is has the 2nd generation multifunction PCI interface
2740 : */
2741 0 : if (rdev->family == CHIP_RV280 ||
2742 0 : rdev->family >= CHIP_RV350) {
2743 0 : WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2744 : ~RADEON_HDP_APER_CNTL);
2745 : DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2746 0 : return aper_size * 2;
2747 : }
2748 :
2749 : /* Older cards have all sorts of funny issues to deal with. First
2750 : * check if it's a multifunction card by reading the PCI config
2751 : * header type... Limit those to one aperture size
2752 : */
2753 0 : pci_read_config_byte(rdev->pdev, 0xe, &byte);
2754 0 : if (byte & 0x80) {
2755 : DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2756 : DRM_INFO("Limiting VRAM to one aperture\n");
2757 0 : return aper_size;
2758 : }
2759 :
2760 : /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2761 : * have set it up. We don't write this as it's broken on some ASICs but
2762 : * we expect the BIOS to have done the right thing (might be too optimistic...)
2763 : */
2764 0 : if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2765 0 : return aper_size * 2;
2766 0 : return aper_size;
2767 0 : }
2768 :
2769 0 : void r100_vram_init_sizes(struct radeon_device *rdev)
2770 : {
2771 : u64 config_aper_size;
2772 :
2773 : /* work out accessible VRAM */
2774 0 : rdev->mc.aper_base = rdev->fb_aper_offset;
2775 0 : rdev->mc.aper_size = rdev->fb_aper_size;
2776 0 : rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2777 : /* FIXME we don't use the second aperture yet when we could use it */
2778 0 : if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2779 0 : rdev->mc.visible_vram_size = rdev->mc.aper_size;
2780 0 : config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2781 0 : if (rdev->flags & RADEON_IS_IGP) {
2782 : uint32_t tom;
2783 : /* read NB_TOM to get the amount of ram stolen for the GPU */
2784 0 : tom = RREG32(RADEON_NB_TOM);
2785 0 : rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2786 0 : WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2787 0 : rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2788 0 : } else {
2789 0 : rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2790 : /* Some production boards of m6 will report 0
2791 : * if it's 8 MB
2792 : */
2793 0 : if (rdev->mc.real_vram_size == 0) {
2794 0 : rdev->mc.real_vram_size = 8192 * 1024;
2795 0 : WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2796 0 : }
2797 : /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2798 : * Novell bug 204882 + along with lots of ubuntu ones
2799 : */
2800 0 : if (rdev->mc.aper_size > config_aper_size)
2801 0 : config_aper_size = rdev->mc.aper_size;
2802 :
2803 0 : if (config_aper_size > rdev->mc.real_vram_size)
2804 0 : rdev->mc.mc_vram_size = config_aper_size;
2805 : else
2806 0 : rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2807 : }
2808 0 : }
2809 :
2810 0 : void r100_vga_set_state(struct radeon_device *rdev, bool state)
2811 : {
2812 : uint32_t temp;
2813 :
2814 0 : temp = RREG32(RADEON_CONFIG_CNTL);
2815 0 : if (state == false) {
2816 0 : temp &= ~RADEON_CFG_VGA_RAM_EN;
2817 0 : temp |= RADEON_CFG_VGA_IO_DIS;
2818 0 : } else {
2819 0 : temp &= ~RADEON_CFG_VGA_IO_DIS;
2820 : }
2821 0 : WREG32(RADEON_CONFIG_CNTL, temp);
2822 0 : }
2823 :
2824 0 : static void r100_mc_init(struct radeon_device *rdev)
2825 : {
2826 : u64 base;
2827 :
2828 0 : r100_vram_get_type(rdev);
2829 0 : r100_vram_init_sizes(rdev);
2830 0 : base = rdev->mc.aper_base;
2831 0 : if (rdev->flags & RADEON_IS_IGP)
2832 0 : base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2833 0 : radeon_vram_location(rdev, &rdev->mc, base);
2834 0 : rdev->mc.gtt_base_align = 0;
2835 0 : if (!(rdev->flags & RADEON_IS_AGP))
2836 0 : radeon_gtt_location(rdev, &rdev->mc);
2837 0 : radeon_update_bandwidth_info(rdev);
2838 0 : }
2839 :
2840 :
2841 : /*
2842 : * Indirect registers accessor
2843 : */
2844 0 : void r100_pll_errata_after_index(struct radeon_device *rdev)
2845 : {
2846 0 : if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2847 0 : (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2848 0 : (void)RREG32(RADEON_CRTC_GEN_CNTL);
2849 0 : }
2850 0 : }
2851 :
2852 0 : static void r100_pll_errata_after_data(struct radeon_device *rdev)
2853 : {
2854 : /* This workarounds is necessary on RV100, RS100 and RS200 chips
2855 : * or the chip could hang on a subsequent access
2856 : */
2857 0 : if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2858 0 : mdelay(5);
2859 0 : }
2860 :
2861 : /* This function is required to workaround a hardware bug in some (all?)
2862 : * revisions of the R300. This workaround should be called after every
2863 : * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2864 : * may not be correct.
2865 : */
2866 0 : if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2867 : uint32_t save, tmp;
2868 :
2869 0 : save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2870 0 : tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2871 0 : WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2872 0 : tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2873 0 : WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2874 0 : }
2875 0 : }
2876 :
2877 0 : uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2878 : {
2879 : unsigned long flags;
2880 : uint32_t data;
2881 :
2882 0 : spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2883 0 : WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2884 0 : r100_pll_errata_after_index(rdev);
2885 0 : data = RREG32(RADEON_CLOCK_CNTL_DATA);
2886 0 : r100_pll_errata_after_data(rdev);
2887 0 : spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2888 0 : return data;
2889 : }
2890 :
2891 0 : void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2892 : {
2893 : unsigned long flags;
2894 :
2895 0 : spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2896 0 : WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2897 0 : r100_pll_errata_after_index(rdev);
2898 0 : WREG32(RADEON_CLOCK_CNTL_DATA, v);
2899 0 : r100_pll_errata_after_data(rdev);
2900 0 : spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2901 0 : }
2902 :
2903 0 : static void r100_set_safe_registers(struct radeon_device *rdev)
2904 : {
2905 0 : if (ASIC_IS_RN50(rdev)) {
2906 0 : rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2907 0 : rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2908 0 : } else if (rdev->family < CHIP_R200) {
2909 0 : rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2910 0 : rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2911 0 : } else {
2912 0 : r200_set_safe_registers(rdev);
2913 : }
2914 0 : }
2915 :
2916 : /*
2917 : * Debugfs info
2918 : */
2919 : #if defined(CONFIG_DEBUG_FS)
2920 : static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2921 : {
2922 : struct drm_info_node *node = (struct drm_info_node *) m->private;
2923 : struct drm_device *dev = node->minor->dev;
2924 : struct radeon_device *rdev = dev->dev_private;
2925 : uint32_t reg, value;
2926 : unsigned i;
2927 :
2928 : seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2929 : seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2930 : seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2931 : for (i = 0; i < 64; i++) {
2932 : WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2933 : reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2934 : WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2935 : value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2936 : seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2937 : }
2938 : return 0;
2939 : }
2940 :
2941 : static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2942 : {
2943 : struct drm_info_node *node = (struct drm_info_node *) m->private;
2944 : struct drm_device *dev = node->minor->dev;
2945 : struct radeon_device *rdev = dev->dev_private;
2946 : struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2947 : uint32_t rdp, wdp;
2948 : unsigned count, i, j;
2949 :
2950 : radeon_ring_free_size(rdev, ring);
2951 : rdp = RREG32(RADEON_CP_RB_RPTR);
2952 : wdp = RREG32(RADEON_CP_RB_WPTR);
2953 : count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2954 : seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2955 : seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2956 : seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2957 : seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2958 : seq_printf(m, "%u dwords in ring\n", count);
2959 : if (ring->ready) {
2960 : for (j = 0; j <= count; j++) {
2961 : i = (rdp + j) & ring->ptr_mask;
2962 : seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2963 : }
2964 : }
2965 : return 0;
2966 : }
2967 :
2968 :
2969 : static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2970 : {
2971 : struct drm_info_node *node = (struct drm_info_node *) m->private;
2972 : struct drm_device *dev = node->minor->dev;
2973 : struct radeon_device *rdev = dev->dev_private;
2974 : uint32_t csq_stat, csq2_stat, tmp;
2975 : unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2976 : unsigned i;
2977 :
2978 : seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2979 : seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2980 : csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2981 : csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2982 : r_rptr = (csq_stat >> 0) & 0x3ff;
2983 : r_wptr = (csq_stat >> 10) & 0x3ff;
2984 : ib1_rptr = (csq_stat >> 20) & 0x3ff;
2985 : ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2986 : ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2987 : ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2988 : seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2989 : seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2990 : seq_printf(m, "Ring rptr %u\n", r_rptr);
2991 : seq_printf(m, "Ring wptr %u\n", r_wptr);
2992 : seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2993 : seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2994 : seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2995 : seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2996 : /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2997 : * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2998 : seq_printf(m, "Ring fifo:\n");
2999 : for (i = 0; i < 256; i++) {
3000 : WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3001 : tmp = RREG32(RADEON_CP_CSQ_DATA);
3002 : seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3003 : }
3004 : seq_printf(m, "Indirect1 fifo:\n");
3005 : for (i = 256; i <= 512; i++) {
3006 : WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3007 : tmp = RREG32(RADEON_CP_CSQ_DATA);
3008 : seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3009 : }
3010 : seq_printf(m, "Indirect2 fifo:\n");
3011 : for (i = 640; i < ib1_wptr; i++) {
3012 : WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3013 : tmp = RREG32(RADEON_CP_CSQ_DATA);
3014 : seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3015 : }
3016 : return 0;
3017 : }
3018 :
3019 : static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3020 : {
3021 : struct drm_info_node *node = (struct drm_info_node *) m->private;
3022 : struct drm_device *dev = node->minor->dev;
3023 : struct radeon_device *rdev = dev->dev_private;
3024 : uint32_t tmp;
3025 :
3026 : tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3027 : seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3028 : tmp = RREG32(RADEON_MC_FB_LOCATION);
3029 : seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3030 : tmp = RREG32(RADEON_BUS_CNTL);
3031 : seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3032 : tmp = RREG32(RADEON_MC_AGP_LOCATION);
3033 : seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3034 : tmp = RREG32(RADEON_AGP_BASE);
3035 : seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3036 : tmp = RREG32(RADEON_HOST_PATH_CNTL);
3037 : seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3038 : tmp = RREG32(0x01D0);
3039 : seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3040 : tmp = RREG32(RADEON_AIC_LO_ADDR);
3041 : seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3042 : tmp = RREG32(RADEON_AIC_HI_ADDR);
3043 : seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3044 : tmp = RREG32(0x01E4);
3045 : seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3046 : return 0;
3047 : }
3048 :
3049 : static struct drm_info_list r100_debugfs_rbbm_list[] = {
3050 : {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3051 : };
3052 :
3053 : static struct drm_info_list r100_debugfs_cp_list[] = {
3054 : {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3055 : {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3056 : };
3057 :
3058 : static struct drm_info_list r100_debugfs_mc_info_list[] = {
3059 : {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3060 : };
3061 : #endif
3062 :
3063 0 : int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3064 : {
3065 : #if defined(CONFIG_DEBUG_FS)
3066 : return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3067 : #else
3068 0 : return 0;
3069 : #endif
3070 : }
3071 :
3072 0 : int r100_debugfs_cp_init(struct radeon_device *rdev)
3073 : {
3074 : #if defined(CONFIG_DEBUG_FS)
3075 : return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3076 : #else
3077 0 : return 0;
3078 : #endif
3079 : }
3080 :
3081 0 : int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3082 : {
3083 : #if defined(CONFIG_DEBUG_FS)
3084 : return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3085 : #else
3086 0 : return 0;
3087 : #endif
3088 : }
3089 :
3090 0 : int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3091 : uint32_t tiling_flags, uint32_t pitch,
3092 : uint32_t offset, uint32_t obj_size)
3093 : {
3094 0 : int surf_index = reg * 16;
3095 : int flags = 0;
3096 :
3097 0 : if (rdev->family <= CHIP_RS200) {
3098 0 : if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3099 0 : == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3100 0 : flags |= RADEON_SURF_TILE_COLOR_BOTH;
3101 0 : if (tiling_flags & RADEON_TILING_MACRO)
3102 0 : flags |= RADEON_SURF_TILE_COLOR_MACRO;
3103 : /* setting pitch to 0 disables tiling */
3104 0 : if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3105 0 : == 0)
3106 0 : pitch = 0;
3107 0 : } else if (rdev->family <= CHIP_RV280) {
3108 0 : if (tiling_flags & (RADEON_TILING_MACRO))
3109 0 : flags |= R200_SURF_TILE_COLOR_MACRO;
3110 0 : if (tiling_flags & RADEON_TILING_MICRO)
3111 0 : flags |= R200_SURF_TILE_COLOR_MICRO;
3112 : } else {
3113 0 : if (tiling_flags & RADEON_TILING_MACRO)
3114 0 : flags |= R300_SURF_TILE_MACRO;
3115 0 : if (tiling_flags & RADEON_TILING_MICRO)
3116 0 : flags |= R300_SURF_TILE_MICRO;
3117 : }
3118 :
3119 0 : if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3120 0 : flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3121 0 : if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3122 0 : flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3123 :
3124 : /* r100/r200 divide by 16 */
3125 0 : if (rdev->family < CHIP_R300)
3126 0 : flags |= pitch / 16;
3127 : else
3128 0 : flags |= pitch / 8;
3129 :
3130 :
3131 : DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3132 0 : WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3133 0 : WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3134 0 : WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3135 0 : return 0;
3136 : }
3137 :
3138 0 : void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3139 : {
3140 0 : int surf_index = reg * 16;
3141 0 : WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3142 0 : }
3143 :
3144 0 : void r100_bandwidth_update(struct radeon_device *rdev)
3145 : {
3146 : fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3147 : fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3148 : fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3149 : uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3150 0 : fixed20_12 memtcas_ff[8] = {
3151 : dfixed_init(1),
3152 : dfixed_init(2),
3153 : dfixed_init(3),
3154 : dfixed_init(0),
3155 : dfixed_init_half(1),
3156 : dfixed_init_half(2),
3157 : dfixed_init(0),
3158 : };
3159 0 : fixed20_12 memtcas_rs480_ff[8] = {
3160 : dfixed_init(0),
3161 : dfixed_init(1),
3162 : dfixed_init(2),
3163 : dfixed_init(3),
3164 : dfixed_init(0),
3165 : dfixed_init_half(1),
3166 : dfixed_init_half(2),
3167 : dfixed_init_half(3),
3168 : };
3169 0 : fixed20_12 memtcas2_ff[8] = {
3170 : dfixed_init(0),
3171 : dfixed_init(1),
3172 : dfixed_init(2),
3173 : dfixed_init(3),
3174 : dfixed_init(4),
3175 : dfixed_init(5),
3176 : dfixed_init(6),
3177 : dfixed_init(7),
3178 : };
3179 0 : fixed20_12 memtrbs[8] = {
3180 : dfixed_init(1),
3181 : dfixed_init_half(1),
3182 : dfixed_init(2),
3183 : dfixed_init_half(2),
3184 : dfixed_init(3),
3185 : dfixed_init_half(3),
3186 : dfixed_init(4),
3187 : dfixed_init_half(4)
3188 : };
3189 0 : fixed20_12 memtrbs_r4xx[8] = {
3190 : dfixed_init(4),
3191 : dfixed_init(5),
3192 : dfixed_init(6),
3193 : dfixed_init(7),
3194 : dfixed_init(8),
3195 : dfixed_init(9),
3196 : dfixed_init(10),
3197 : dfixed_init(11)
3198 : };
3199 : fixed20_12 min_mem_eff;
3200 : fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3201 : fixed20_12 cur_latency_mclk, cur_latency_sclk;
3202 : fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3203 : disp_drain_rate2, read_return_rate;
3204 : fixed20_12 time_disp1_drop_priority;
3205 : int c;
3206 : int cur_size = 16; /* in octawords */
3207 : int critical_point = 0, critical_point2;
3208 : /* uint32_t read_return_rate, time_disp1_drop_priority; */
3209 : int stop_req, max_stop_req;
3210 : struct drm_display_mode *mode1 = NULL;
3211 : struct drm_display_mode *mode2 = NULL;
3212 : uint32_t pixel_bytes1 = 0;
3213 : uint32_t pixel_bytes2 = 0;
3214 :
3215 : /* Guess line buffer size to be 8192 pixels */
3216 : u32 lb_size = 8192;
3217 :
3218 0 : if (!rdev->mode_info.mode_config_initialized)
3219 0 : return;
3220 :
3221 0 : radeon_update_display_priority(rdev);
3222 :
3223 0 : if (rdev->mode_info.crtcs[0]->base.enabled) {
3224 0 : mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3225 0 : pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
3226 0 : }
3227 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3228 0 : if (rdev->mode_info.crtcs[1]->base.enabled) {
3229 0 : mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3230 0 : pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
3231 0 : }
3232 : }
3233 :
3234 : min_mem_eff.full = dfixed_const_8(0);
3235 : /* get modes */
3236 0 : if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3237 0 : uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3238 0 : mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3239 0 : mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3240 : /* check crtc enables */
3241 0 : if (mode2)
3242 0 : mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3243 0 : if (mode1)
3244 0 : mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3245 0 : WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3246 0 : }
3247 :
3248 : /*
3249 : * determine is there is enough bw for current mode
3250 : */
3251 0 : sclk_ff = rdev->pm.sclk;
3252 0 : mclk_ff = rdev->pm.mclk;
3253 :
3254 0 : temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3255 0 : temp_ff.full = dfixed_const(temp);
3256 0 : mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3257 :
3258 : pix_clk.full = 0;
3259 : pix_clk2.full = 0;
3260 : peak_disp_bw.full = 0;
3261 0 : if (mode1) {
3262 : temp_ff.full = dfixed_const(1000);
3263 0 : pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3264 0 : pix_clk.full = dfixed_div(pix_clk, temp_ff);
3265 0 : temp_ff.full = dfixed_const(pixel_bytes1);
3266 0 : peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3267 0 : }
3268 0 : if (mode2) {
3269 : temp_ff.full = dfixed_const(1000);
3270 0 : pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3271 0 : pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3272 0 : temp_ff.full = dfixed_const(pixel_bytes2);
3273 0 : peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3274 0 : }
3275 :
3276 0 : mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3277 0 : if (peak_disp_bw.full >= mem_bw.full) {
3278 0 : DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3279 : "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3280 0 : }
3281 :
3282 : /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3283 0 : temp = RREG32(RADEON_MEM_TIMING_CNTL);
3284 0 : if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3285 0 : mem_trcd = ((temp >> 2) & 0x3) + 1;
3286 0 : mem_trp = ((temp & 0x3)) + 1;
3287 0 : mem_tras = ((temp & 0x70) >> 4) + 1;
3288 0 : } else if (rdev->family == CHIP_R300 ||
3289 0 : rdev->family == CHIP_R350) { /* r300, r350 */
3290 0 : mem_trcd = (temp & 0x7) + 1;
3291 0 : mem_trp = ((temp >> 8) & 0x7) + 1;
3292 0 : mem_tras = ((temp >> 11) & 0xf) + 4;
3293 0 : } else if (rdev->family == CHIP_RV350 ||
3294 0 : rdev->family <= CHIP_RV380) {
3295 : /* rv3x0 */
3296 0 : mem_trcd = (temp & 0x7) + 3;
3297 0 : mem_trp = ((temp >> 8) & 0x7) + 3;
3298 0 : mem_tras = ((temp >> 11) & 0xf) + 6;
3299 0 : } else if (rdev->family == CHIP_R420 ||
3300 0 : rdev->family == CHIP_R423 ||
3301 0 : rdev->family == CHIP_RV410) {
3302 : /* r4xx */
3303 0 : mem_trcd = (temp & 0xf) + 3;
3304 0 : if (mem_trcd > 15)
3305 : mem_trcd = 15;
3306 0 : mem_trp = ((temp >> 8) & 0xf) + 3;
3307 0 : if (mem_trp > 15)
3308 : mem_trp = 15;
3309 0 : mem_tras = ((temp >> 12) & 0x1f) + 6;
3310 0 : if (mem_tras > 31)
3311 : mem_tras = 31;
3312 0 : } else { /* RV200, R200 */
3313 0 : mem_trcd = (temp & 0x7) + 1;
3314 0 : mem_trp = ((temp >> 8) & 0x7) + 1;
3315 0 : mem_tras = ((temp >> 12) & 0xf) + 4;
3316 : }
3317 : /* convert to FF */
3318 0 : trcd_ff.full = dfixed_const(mem_trcd);
3319 0 : trp_ff.full = dfixed_const(mem_trp);
3320 0 : tras_ff.full = dfixed_const(mem_tras);
3321 :
3322 : /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3323 0 : temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3324 0 : data = (temp & (7 << 20)) >> 20;
3325 0 : if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3326 0 : if (rdev->family == CHIP_RS480) /* don't think rs400 */
3327 0 : tcas_ff = memtcas_rs480_ff[data];
3328 : else
3329 0 : tcas_ff = memtcas_ff[data];
3330 : } else
3331 0 : tcas_ff = memtcas2_ff[data];
3332 :
3333 0 : if (rdev->family == CHIP_RS400 ||
3334 0 : rdev->family == CHIP_RS480) {
3335 : /* extra cas latency stored in bits 23-25 0-4 clocks */
3336 0 : data = (temp >> 23) & 0x7;
3337 0 : if (data < 5)
3338 0 : tcas_ff.full += dfixed_const(data);
3339 : }
3340 :
3341 0 : if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3342 : /* on the R300, Tcas is included in Trbs.
3343 : */
3344 0 : temp = RREG32(RADEON_MEM_CNTL);
3345 0 : data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3346 0 : if (data == 1) {
3347 0 : if (R300_MEM_USE_CD_CH_ONLY & temp) {
3348 0 : temp = RREG32(R300_MC_IND_INDEX);
3349 0 : temp &= ~R300_MC_IND_ADDR_MASK;
3350 0 : temp |= R300_MC_READ_CNTL_CD_mcind;
3351 0 : WREG32(R300_MC_IND_INDEX, temp);
3352 0 : temp = RREG32(R300_MC_IND_DATA);
3353 0 : data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3354 0 : } else {
3355 0 : temp = RREG32(R300_MC_READ_CNTL_AB);
3356 0 : data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3357 : }
3358 : } else {
3359 0 : temp = RREG32(R300_MC_READ_CNTL_AB);
3360 0 : data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3361 : }
3362 0 : if (rdev->family == CHIP_RV410 ||
3363 0 : rdev->family == CHIP_R420 ||
3364 0 : rdev->family == CHIP_R423)
3365 0 : trbs_ff = memtrbs_r4xx[data];
3366 : else
3367 0 : trbs_ff = memtrbs[data];
3368 0 : tcas_ff.full += trbs_ff.full;
3369 0 : }
3370 :
3371 : sclk_eff_ff.full = sclk_ff.full;
3372 :
3373 0 : if (rdev->flags & RADEON_IS_AGP) {
3374 : fixed20_12 agpmode_ff;
3375 0 : agpmode_ff.full = dfixed_const(radeon_agpmode);
3376 : temp_ff.full = dfixed_const_666(16);
3377 0 : sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3378 0 : }
3379 : /* TODO PCIE lanes may affect this - agpmode == 16?? */
3380 :
3381 0 : if (ASIC_IS_R300(rdev)) {
3382 : sclk_delay_ff.full = dfixed_const(250);
3383 0 : } else {
3384 0 : if ((rdev->family == CHIP_RV100) ||
3385 0 : rdev->flags & RADEON_IS_IGP) {
3386 0 : if (rdev->mc.vram_is_ddr)
3387 0 : sclk_delay_ff.full = dfixed_const(41);
3388 : else
3389 : sclk_delay_ff.full = dfixed_const(33);
3390 : } else {
3391 0 : if (rdev->mc.vram_width == 128)
3392 0 : sclk_delay_ff.full = dfixed_const(57);
3393 : else
3394 : sclk_delay_ff.full = dfixed_const(41);
3395 : }
3396 : }
3397 :
3398 0 : mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3399 :
3400 0 : if (rdev->mc.vram_is_ddr) {
3401 0 : if (rdev->mc.vram_width == 32) {
3402 : k1.full = dfixed_const(40);
3403 : c = 3;
3404 0 : } else {
3405 : k1.full = dfixed_const(20);
3406 : c = 1;
3407 : }
3408 : } else {
3409 : k1.full = dfixed_const(40);
3410 : c = 3;
3411 : }
3412 :
3413 : temp_ff.full = dfixed_const(2);
3414 0 : mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3415 0 : temp_ff.full = dfixed_const(c);
3416 0 : mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3417 : temp_ff.full = dfixed_const(4);
3418 0 : mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3419 0 : mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3420 0 : mc_latency_mclk.full += k1.full;
3421 :
3422 0 : mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3423 0 : mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3424 :
3425 : /*
3426 : HW cursor time assuming worst case of full size colour cursor.
3427 : */
3428 0 : temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3429 0 : temp_ff.full += trcd_ff.full;
3430 0 : if (temp_ff.full < tras_ff.full)
3431 0 : temp_ff.full = tras_ff.full;
3432 0 : cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3433 :
3434 : temp_ff.full = dfixed_const(cur_size);
3435 0 : cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3436 : /*
3437 : Find the total latency for the display data.
3438 : */
3439 : disp_latency_overhead.full = dfixed_const(8);
3440 0 : disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3441 0 : mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3442 0 : mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3443 :
3444 0 : if (mc_latency_mclk.full > mc_latency_sclk.full)
3445 0 : disp_latency.full = mc_latency_mclk.full;
3446 : else
3447 : disp_latency.full = mc_latency_sclk.full;
3448 :
3449 : /* setup Max GRPH_STOP_REQ default value */
3450 0 : if (ASIC_IS_RV100(rdev))
3451 0 : max_stop_req = 0x5c;
3452 : else
3453 : max_stop_req = 0x7c;
3454 :
3455 0 : if (mode1) {
3456 : /* CRTC1
3457 : Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3458 : GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3459 : */
3460 0 : stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3461 :
3462 0 : if (stop_req > max_stop_req)
3463 0 : stop_req = max_stop_req;
3464 :
3465 : /*
3466 : Find the drain rate of the display buffer.
3467 : */
3468 0 : temp_ff.full = dfixed_const((16/pixel_bytes1));
3469 0 : disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3470 :
3471 : /*
3472 : Find the critical point of the display buffer.
3473 : */
3474 0 : crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3475 0 : crit_point_ff.full += dfixed_const_half(0);
3476 :
3477 0 : critical_point = dfixed_trunc(crit_point_ff);
3478 :
3479 0 : if (rdev->disp_priority == 2) {
3480 : critical_point = 0;
3481 : }
3482 :
3483 : /*
3484 : The critical point should never be above max_stop_req-4. Setting
3485 : GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3486 : */
3487 0 : if (max_stop_req - critical_point < 4)
3488 : critical_point = 0;
3489 :
3490 0 : if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3491 : /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3492 : critical_point = 0x10;
3493 0 : }
3494 :
3495 0 : temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3496 0 : temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3497 0 : temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3498 0 : temp &= ~(RADEON_GRPH_START_REQ_MASK);
3499 0 : if ((rdev->family == CHIP_R350) &&
3500 0 : (stop_req > 0x15)) {
3501 0 : stop_req -= 0x10;
3502 0 : }
3503 0 : temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3504 0 : temp |= RADEON_GRPH_BUFFER_SIZE;
3505 0 : temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3506 : RADEON_GRPH_CRITICAL_AT_SOF |
3507 : RADEON_GRPH_STOP_CNTL);
3508 : /*
3509 : Write the result into the register.
3510 : */
3511 0 : WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3512 : (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3513 :
3514 : #if 0
3515 : if ((rdev->family == CHIP_RS400) ||
3516 : (rdev->family == CHIP_RS480)) {
3517 : /* attempt to program RS400 disp regs correctly ??? */
3518 : temp = RREG32(RS400_DISP1_REG_CNTL);
3519 : temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3520 : RS400_DISP1_STOP_REQ_LEVEL_MASK);
3521 : WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3522 : (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3523 : (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3524 : temp = RREG32(RS400_DMIF_MEM_CNTL1);
3525 : temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3526 : RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3527 : WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3528 : (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3529 : (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3530 : }
3531 : #endif
3532 :
3533 : DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3534 : /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3535 : (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3536 0 : }
3537 :
3538 0 : if (mode2) {
3539 : u32 grph2_cntl;
3540 0 : stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3541 :
3542 0 : if (stop_req > max_stop_req)
3543 0 : stop_req = max_stop_req;
3544 :
3545 : /*
3546 : Find the drain rate of the display buffer.
3547 : */
3548 0 : temp_ff.full = dfixed_const((16/pixel_bytes2));
3549 0 : disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3550 :
3551 0 : grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3552 0 : grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3553 0 : grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3554 0 : grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3555 0 : if ((rdev->family == CHIP_R350) &&
3556 0 : (stop_req > 0x15)) {
3557 0 : stop_req -= 0x10;
3558 0 : }
3559 0 : grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3560 0 : grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3561 0 : grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3562 : RADEON_GRPH_CRITICAL_AT_SOF |
3563 : RADEON_GRPH_STOP_CNTL);
3564 :
3565 0 : if ((rdev->family == CHIP_RS100) ||
3566 0 : (rdev->family == CHIP_RS200))
3567 0 : critical_point2 = 0;
3568 : else {
3569 0 : temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3570 0 : temp_ff.full = dfixed_const(temp);
3571 0 : temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3572 0 : if (sclk_ff.full < temp_ff.full)
3573 0 : temp_ff.full = sclk_ff.full;
3574 :
3575 : read_return_rate.full = temp_ff.full;
3576 :
3577 0 : if (mode1) {
3578 0 : temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3579 0 : time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3580 0 : } else {
3581 : time_disp1_drop_priority.full = 0;
3582 : }
3583 0 : crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3584 0 : crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3585 0 : crit_point_ff.full += dfixed_const_half(0);
3586 :
3587 0 : critical_point2 = dfixed_trunc(crit_point_ff);
3588 :
3589 0 : if (rdev->disp_priority == 2) {
3590 : critical_point2 = 0;
3591 : }
3592 :
3593 0 : if (max_stop_req - critical_point2 < 4)
3594 : critical_point2 = 0;
3595 :
3596 : }
3597 :
3598 0 : if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3599 : /* some R300 cards have problem with this set to 0 */
3600 : critical_point2 = 0x10;
3601 0 : }
3602 :
3603 0 : WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3604 : (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3605 :
3606 0 : if ((rdev->family == CHIP_RS400) ||
3607 0 : (rdev->family == CHIP_RS480)) {
3608 : #if 0
3609 : /* attempt to program RS400 disp2 regs correctly ??? */
3610 : temp = RREG32(RS400_DISP2_REQ_CNTL1);
3611 : temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3612 : RS400_DISP2_STOP_REQ_LEVEL_MASK);
3613 : WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3614 : (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3615 : (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3616 : temp = RREG32(RS400_DISP2_REQ_CNTL2);
3617 : temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3618 : RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3619 : WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3620 : (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3621 : (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3622 : #endif
3623 0 : WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3624 0 : WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3625 0 : WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3626 0 : WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3627 0 : }
3628 :
3629 : DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3630 : (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3631 0 : }
3632 :
3633 : /* Save number of lines the linebuffer leads before the scanout */
3634 0 : if (mode1)
3635 0 : rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3636 :
3637 0 : if (mode2)
3638 0 : rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3639 0 : }
3640 :
3641 0 : int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3642 : {
3643 0 : uint32_t scratch;
3644 : uint32_t tmp = 0;
3645 : unsigned i;
3646 : int r;
3647 :
3648 0 : r = radeon_scratch_get(rdev, &scratch);
3649 0 : if (r) {
3650 0 : DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3651 0 : return r;
3652 : }
3653 0 : WREG32(scratch, 0xCAFEDEAD);
3654 0 : r = radeon_ring_lock(rdev, ring, 2);
3655 0 : if (r) {
3656 0 : DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3657 0 : radeon_scratch_free(rdev, scratch);
3658 0 : return r;
3659 : }
3660 0 : radeon_ring_write(ring, PACKET0(scratch, 0));
3661 0 : radeon_ring_write(ring, 0xDEADBEEF);
3662 0 : radeon_ring_unlock_commit(rdev, ring, false);
3663 0 : for (i = 0; i < rdev->usec_timeout; i++) {
3664 0 : tmp = RREG32(scratch);
3665 0 : if (tmp == 0xDEADBEEF) {
3666 : break;
3667 : }
3668 0 : DRM_UDELAY(1);
3669 : }
3670 0 : if (i < rdev->usec_timeout) {
3671 : DRM_INFO("ring test succeeded in %d usecs\n", i);
3672 : } else {
3673 0 : DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3674 : scratch, tmp);
3675 : r = -EINVAL;
3676 : }
3677 0 : radeon_scratch_free(rdev, scratch);
3678 0 : return r;
3679 0 : }
3680 :
3681 0 : void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3682 : {
3683 0 : struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3684 :
3685 0 : if (ring->rptr_save_reg) {
3686 0 : u32 next_rptr = ring->wptr + 2 + 3;
3687 0 : radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3688 0 : radeon_ring_write(ring, next_rptr);
3689 0 : }
3690 :
3691 0 : radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3692 0 : radeon_ring_write(ring, ib->gpu_addr);
3693 0 : radeon_ring_write(ring, ib->length_dw);
3694 0 : }
3695 :
3696 0 : int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3697 : {
3698 0 : struct radeon_ib ib;
3699 0 : uint32_t scratch;
3700 : uint32_t tmp = 0;
3701 : unsigned i;
3702 : int r;
3703 :
3704 0 : r = radeon_scratch_get(rdev, &scratch);
3705 0 : if (r) {
3706 0 : DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3707 0 : return r;
3708 : }
3709 0 : WREG32(scratch, 0xCAFEDEAD);
3710 0 : r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3711 0 : if (r) {
3712 0 : DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3713 0 : goto free_scratch;
3714 : }
3715 0 : ib.ptr[0] = PACKET0(scratch, 0);
3716 0 : ib.ptr[1] = 0xDEADBEEF;
3717 0 : ib.ptr[2] = PACKET2(0);
3718 0 : ib.ptr[3] = PACKET2(0);
3719 0 : ib.ptr[4] = PACKET2(0);
3720 0 : ib.ptr[5] = PACKET2(0);
3721 0 : ib.ptr[6] = PACKET2(0);
3722 0 : ib.ptr[7] = PACKET2(0);
3723 0 : ib.length_dw = 8;
3724 0 : r = radeon_ib_schedule(rdev, &ib, NULL, false);
3725 0 : if (r) {
3726 0 : DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3727 0 : goto free_ib;
3728 : }
3729 0 : r = radeon_fence_wait(ib.fence, false);
3730 0 : if (r) {
3731 0 : DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3732 0 : goto free_ib;
3733 : }
3734 0 : for (i = 0; i < rdev->usec_timeout; i++) {
3735 0 : tmp = RREG32(scratch);
3736 0 : if (tmp == 0xDEADBEEF) {
3737 : break;
3738 : }
3739 0 : DRM_UDELAY(1);
3740 : }
3741 0 : if (i < rdev->usec_timeout) {
3742 : DRM_INFO("ib test succeeded in %u usecs\n", i);
3743 : } else {
3744 0 : DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3745 : scratch, tmp);
3746 : r = -EINVAL;
3747 : }
3748 : free_ib:
3749 0 : radeon_ib_free(rdev, &ib);
3750 : free_scratch:
3751 0 : radeon_scratch_free(rdev, scratch);
3752 0 : return r;
3753 0 : }
3754 :
3755 0 : void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3756 : {
3757 : /* Shutdown CP we shouldn't need to do that but better be safe than
3758 : * sorry
3759 : */
3760 0 : rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3761 0 : WREG32(R_000740_CP_CSQ_CNTL, 0);
3762 :
3763 : /* Save few CRTC registers */
3764 0 : save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3765 0 : save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3766 0 : save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3767 0 : save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3768 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3769 0 : save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3770 0 : save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3771 0 : }
3772 :
3773 : /* Disable VGA aperture access */
3774 0 : WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3775 : /* Disable cursor, overlay, crtc */
3776 0 : WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3777 0 : WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3778 : S_000054_CRTC_DISPLAY_DIS(1));
3779 0 : WREG32(R_000050_CRTC_GEN_CNTL,
3780 : (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3781 : S_000050_CRTC_DISP_REQ_EN_B(1));
3782 0 : WREG32(R_000420_OV0_SCALE_CNTL,
3783 : C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3784 0 : WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3785 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3786 0 : WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3787 : S_000360_CUR2_LOCK(1));
3788 0 : WREG32(R_0003F8_CRTC2_GEN_CNTL,
3789 : (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3790 : S_0003F8_CRTC2_DISPLAY_DIS(1) |
3791 : S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3792 0 : WREG32(R_000360_CUR2_OFFSET,
3793 : C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3794 0 : }
3795 0 : }
3796 :
3797 0 : void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3798 : {
3799 : /* Update base address for crtc */
3800 0 : WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3801 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3802 0 : WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3803 0 : }
3804 : /* Restore CRTC registers */
3805 0 : WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3806 0 : WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3807 0 : WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3808 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3809 0 : WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3810 0 : }
3811 0 : }
3812 :
3813 0 : void r100_vga_render_disable(struct radeon_device *rdev)
3814 : {
3815 : u32 tmp;
3816 :
3817 0 : tmp = RREG8(R_0003C2_GENMO_WT);
3818 0 : WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3819 0 : }
3820 :
3821 0 : static void r100_debugfs(struct radeon_device *rdev)
3822 : {
3823 : int r;
3824 :
3825 0 : r = r100_debugfs_mc_info_init(rdev);
3826 0 : if (r)
3827 0 : dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3828 0 : }
3829 :
3830 0 : static void r100_mc_program(struct radeon_device *rdev)
3831 : {
3832 0 : struct r100_mc_save save;
3833 :
3834 : /* Stops all mc clients */
3835 0 : r100_mc_stop(rdev, &save);
3836 0 : if (rdev->flags & RADEON_IS_AGP) {
3837 0 : WREG32(R_00014C_MC_AGP_LOCATION,
3838 : S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3839 : S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3840 0 : WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3841 0 : if (rdev->family > CHIP_RV200)
3842 0 : WREG32(R_00015C_AGP_BASE_2,
3843 : upper_32_bits(rdev->mc.agp_base) & 0xff);
3844 : } else {
3845 0 : WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3846 0 : WREG32(R_000170_AGP_BASE, 0);
3847 0 : if (rdev->family > CHIP_RV200)
3848 0 : WREG32(R_00015C_AGP_BASE_2, 0);
3849 : }
3850 : /* Wait for mc idle */
3851 0 : if (r100_mc_wait_for_idle(rdev))
3852 0 : dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3853 : /* Program MC, should be a 32bits limited address space */
3854 0 : WREG32(R_000148_MC_FB_LOCATION,
3855 : S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3856 : S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3857 0 : r100_mc_resume(rdev, &save);
3858 0 : }
3859 :
3860 0 : static void r100_clock_startup(struct radeon_device *rdev)
3861 : {
3862 : u32 tmp;
3863 :
3864 0 : if (radeon_dynclks != -1 && radeon_dynclks)
3865 0 : radeon_legacy_set_clock_gating(rdev, 1);
3866 : /* We need to force on some of the block */
3867 0 : tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3868 0 : tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3869 0 : if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3870 0 : tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3871 0 : WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3872 0 : }
3873 :
3874 0 : static int r100_startup(struct radeon_device *rdev)
3875 : {
3876 : int r;
3877 :
3878 : /* set common regs */
3879 0 : r100_set_common_regs(rdev);
3880 : /* program mc */
3881 0 : r100_mc_program(rdev);
3882 : /* Resume clock */
3883 0 : r100_clock_startup(rdev);
3884 : /* Initialize GART (initialize after TTM so we can allocate
3885 : * memory through TTM but finalize after TTM) */
3886 0 : r100_enable_bm(rdev);
3887 0 : if (rdev->flags & RADEON_IS_PCI) {
3888 0 : r = r100_pci_gart_enable(rdev);
3889 0 : if (r)
3890 0 : return r;
3891 : }
3892 :
3893 : /* allocate wb buffer */
3894 0 : r = radeon_wb_init(rdev);
3895 0 : if (r)
3896 0 : return r;
3897 :
3898 0 : r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3899 0 : if (r) {
3900 0 : dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3901 0 : return r;
3902 : }
3903 :
3904 : /* Enable IRQ */
3905 0 : if (!rdev->irq.installed) {
3906 0 : r = radeon_irq_kms_init(rdev);
3907 0 : if (r)
3908 0 : return r;
3909 : }
3910 :
3911 0 : r100_irq_set(rdev);
3912 0 : rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3913 : /* 1M ring buffer */
3914 0 : r = r100_cp_init(rdev, 1024 * 1024);
3915 0 : if (r) {
3916 0 : dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3917 0 : return r;
3918 : }
3919 :
3920 0 : r = radeon_ib_pool_init(rdev);
3921 0 : if (r) {
3922 0 : dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3923 0 : return r;
3924 : }
3925 :
3926 0 : return 0;
3927 0 : }
3928 :
3929 0 : int r100_resume(struct radeon_device *rdev)
3930 : {
3931 : int r;
3932 :
3933 : /* Make sur GART are not working */
3934 0 : if (rdev->flags & RADEON_IS_PCI)
3935 0 : r100_pci_gart_disable(rdev);
3936 : /* Resume clock before doing reset */
3937 0 : r100_clock_startup(rdev);
3938 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3939 0 : if (radeon_asic_reset(rdev)) {
3940 0 : dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3941 : RREG32(R_000E40_RBBM_STATUS),
3942 : RREG32(R_0007C0_CP_STAT));
3943 0 : }
3944 : /* post */
3945 0 : radeon_combios_asic_init(rdev->ddev);
3946 : /* Resume clock after posting */
3947 0 : r100_clock_startup(rdev);
3948 : /* Initialize surface registers */
3949 0 : radeon_surface_init(rdev);
3950 :
3951 0 : rdev->accel_working = true;
3952 0 : r = r100_startup(rdev);
3953 0 : if (r) {
3954 0 : rdev->accel_working = false;
3955 0 : }
3956 0 : return r;
3957 : }
3958 :
3959 0 : int r100_suspend(struct radeon_device *rdev)
3960 : {
3961 0 : radeon_pm_suspend(rdev);
3962 0 : r100_cp_disable(rdev);
3963 0 : radeon_wb_disable(rdev);
3964 0 : r100_irq_disable(rdev);
3965 0 : if (rdev->flags & RADEON_IS_PCI)
3966 0 : r100_pci_gart_disable(rdev);
3967 0 : return 0;
3968 : }
3969 :
3970 0 : void r100_fini(struct radeon_device *rdev)
3971 : {
3972 0 : radeon_pm_fini(rdev);
3973 0 : r100_cp_fini(rdev);
3974 0 : radeon_wb_fini(rdev);
3975 0 : radeon_ib_pool_fini(rdev);
3976 0 : radeon_gem_fini(rdev);
3977 0 : if (rdev->flags & RADEON_IS_PCI)
3978 0 : r100_pci_gart_fini(rdev);
3979 0 : radeon_agp_fini(rdev);
3980 0 : radeon_irq_kms_fini(rdev);
3981 0 : radeon_fence_driver_fini(rdev);
3982 0 : radeon_bo_fini(rdev);
3983 0 : radeon_atombios_fini(rdev);
3984 0 : kfree(rdev->bios);
3985 0 : rdev->bios = NULL;
3986 0 : }
3987 :
3988 : /*
3989 : * Due to how kexec works, it can leave the hw fully initialised when it
3990 : * boots the new kernel. However doing our init sequence with the CP and
3991 : * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3992 : * do some quick sanity checks and restore sane values to avoid this
3993 : * problem.
3994 : */
3995 0 : void r100_restore_sanity(struct radeon_device *rdev)
3996 : {
3997 : u32 tmp;
3998 :
3999 0 : tmp = RREG32(RADEON_CP_CSQ_CNTL);
4000 0 : if (tmp) {
4001 0 : WREG32(RADEON_CP_CSQ_CNTL, 0);
4002 0 : }
4003 0 : tmp = RREG32(RADEON_CP_RB_CNTL);
4004 0 : if (tmp) {
4005 0 : WREG32(RADEON_CP_RB_CNTL, 0);
4006 0 : }
4007 0 : tmp = RREG32(RADEON_SCRATCH_UMSK);
4008 0 : if (tmp) {
4009 0 : WREG32(RADEON_SCRATCH_UMSK, 0);
4010 0 : }
4011 0 : }
4012 :
4013 0 : int r100_init(struct radeon_device *rdev)
4014 : {
4015 : int r;
4016 :
4017 : /* Register debugfs file specific to this group of asics */
4018 0 : r100_debugfs(rdev);
4019 : /* Disable VGA */
4020 0 : r100_vga_render_disable(rdev);
4021 : /* Initialize scratch registers */
4022 0 : radeon_scratch_init(rdev);
4023 : /* Initialize surface registers */
4024 0 : radeon_surface_init(rdev);
4025 : /* sanity check some register to avoid hangs like after kexec */
4026 0 : r100_restore_sanity(rdev);
4027 : /* TODO: disable VGA need to use VGA request */
4028 : /* BIOS*/
4029 0 : if (!radeon_get_bios(rdev)) {
4030 0 : if (ASIC_IS_AVIVO(rdev))
4031 0 : return -EINVAL;
4032 : }
4033 0 : if (rdev->is_atom_bios) {
4034 0 : dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4035 0 : return -EINVAL;
4036 : } else {
4037 0 : r = radeon_combios_init(rdev);
4038 0 : if (r)
4039 0 : return r;
4040 : }
4041 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4042 0 : if (radeon_asic_reset(rdev)) {
4043 0 : dev_warn(rdev->dev,
4044 : "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4045 : RREG32(R_000E40_RBBM_STATUS),
4046 : RREG32(R_0007C0_CP_STAT));
4047 0 : }
4048 : /* check if cards are posted or not */
4049 0 : if (radeon_boot_test_post_card(rdev) == false)
4050 0 : return -EINVAL;
4051 : /* Set asic errata */
4052 0 : r100_errata(rdev);
4053 : /* Initialize clocks */
4054 0 : radeon_get_clock_info(rdev->ddev);
4055 : /* initialize AGP */
4056 0 : if (rdev->flags & RADEON_IS_AGP) {
4057 0 : r = radeon_agp_init(rdev);
4058 0 : if (r) {
4059 0 : radeon_agp_disable(rdev);
4060 0 : }
4061 : }
4062 : /* initialize VRAM */
4063 0 : r100_mc_init(rdev);
4064 : /* Fence driver */
4065 0 : r = radeon_fence_driver_init(rdev);
4066 0 : if (r)
4067 0 : return r;
4068 : /* Memory manager */
4069 0 : r = radeon_bo_init(rdev);
4070 0 : if (r)
4071 0 : return r;
4072 0 : if (rdev->flags & RADEON_IS_PCI) {
4073 0 : r = r100_pci_gart_init(rdev);
4074 0 : if (r)
4075 0 : return r;
4076 : }
4077 0 : r100_set_safe_registers(rdev);
4078 :
4079 : /* Initialize power management */
4080 0 : radeon_pm_init(rdev);
4081 :
4082 0 : rdev->accel_working = true;
4083 0 : r = r100_startup(rdev);
4084 0 : if (r) {
4085 : /* Somethings want wront with the accel init stop accel */
4086 0 : dev_err(rdev->dev, "Disabling GPU acceleration\n");
4087 0 : r100_cp_fini(rdev);
4088 0 : radeon_wb_fini(rdev);
4089 0 : radeon_ib_pool_fini(rdev);
4090 0 : radeon_irq_kms_fini(rdev);
4091 0 : if (rdev->flags & RADEON_IS_PCI)
4092 0 : r100_pci_gart_fini(rdev);
4093 0 : rdev->accel_working = false;
4094 0 : }
4095 0 : return 0;
4096 0 : }
4097 :
4098 0 : uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4099 : {
4100 : unsigned long flags;
4101 : uint32_t ret;
4102 :
4103 0 : spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4104 0 : bus_space_write_4(rdev->memt, rdev->rmmio_bsh,
4105 : RADEON_MM_INDEX, reg);
4106 0 : ret = bus_space_read_4(rdev->memt, rdev->rmmio_bsh,
4107 : RADEON_MM_DATA);
4108 0 : spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4109 0 : return ret;
4110 : }
4111 :
4112 0 : void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4113 : {
4114 : unsigned long flags;
4115 :
4116 0 : spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4117 0 : bus_space_write_4(rdev->memt, rdev->rmmio_bsh,
4118 : RADEON_MM_INDEX, reg);
4119 0 : bus_space_write_4(rdev->memt, rdev->rmmio_bsh,
4120 : RADEON_MM_DATA, v);
4121 0 : spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4122 0 : }
4123 :
4124 0 : u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4125 : {
4126 0 : if (reg < rdev->rio_mem_size)
4127 0 : return bus_space_read_4(rdev->iot, rdev->rio_mem, reg);
4128 : else {
4129 0 : bus_space_write_4(rdev->iot, rdev->rio_mem,
4130 : RADEON_MM_INDEX, reg);
4131 0 : return bus_space_read_4(rdev->iot, rdev->rio_mem,
4132 : RADEON_MM_DATA);
4133 : }
4134 0 : }
4135 :
4136 0 : void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4137 : {
4138 0 : if (reg < rdev->rio_mem_size)
4139 0 : bus_space_write_4(rdev->iot, rdev->rio_mem, reg, v);
4140 : else {
4141 0 : bus_space_write_4(rdev->iot, rdev->rio_mem,
4142 : RADEON_MM_INDEX, reg);
4143 0 : bus_space_write_4(rdev->iot, rdev->rio_mem,
4144 : RADEON_MM_DATA, v);
4145 : }
4146 0 : }
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