Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #include <dev/pci/drm/drmP.h>
29 : #include <dev/pci/drm/drm.h>
30 : #include <dev/pci/drm/drm_crtc_helper.h>
31 : #include "radeon_reg.h"
32 : #include "radeon.h"
33 : #include "radeon_asic.h"
34 : #include <dev/pci/drm/radeon_drm.h>
35 : #include "r100_track.h"
36 : #include "r300d.h"
37 : #include "rv350d.h"
38 : #include "r300_reg_safe.h"
39 :
40 : /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
41 : *
42 : * GPU Errata:
43 : * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
44 : * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
45 : * However, scheduling such write to the ring seems harmless, i suspect
46 : * the CP read collide with the flush somehow, or maybe the MC, hard to
47 : * tell. (Jerome Glisse)
48 : */
49 :
50 : /*
51 : * Indirect registers accessor
52 : */
53 0 : uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
54 : {
55 : unsigned long flags;
56 : uint32_t r;
57 :
58 0 : spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
59 0 : WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
60 0 : r = RREG32(RADEON_PCIE_DATA);
61 0 : spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
62 0 : return r;
63 : }
64 :
65 0 : void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
66 : {
67 : unsigned long flags;
68 :
69 0 : spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
70 0 : WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
71 0 : WREG32(RADEON_PCIE_DATA, (v));
72 0 : spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
73 0 : }
74 :
75 : /*
76 : * rv370,rv380 PCIE GART
77 : */
78 : static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
79 :
80 0 : void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
81 : {
82 : uint32_t tmp;
83 : int i;
84 :
85 : /* Workaround HW bug do flush 2 times */
86 0 : for (i = 0; i < 2; i++) {
87 0 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
88 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
89 0 : (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
90 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
91 : }
92 0 : mb();
93 0 : }
94 :
95 : #define R300_PTE_UNSNOOPED (1 << 0)
96 : #define R300_PTE_WRITEABLE (1 << 2)
97 : #define R300_PTE_READABLE (1 << 3)
98 :
99 0 : uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags)
100 : {
101 0 : addr = (lower_32_bits(addr) >> 8) |
102 0 : ((upper_32_bits(addr) & 0xff) << 24);
103 0 : if (flags & RADEON_GART_PAGE_READ)
104 0 : addr |= R300_PTE_READABLE;
105 0 : if (flags & RADEON_GART_PAGE_WRITE)
106 0 : addr |= R300_PTE_WRITEABLE;
107 0 : if (!(flags & RADEON_GART_PAGE_SNOOP))
108 0 : addr |= R300_PTE_UNSNOOPED;
109 0 : return addr;
110 : }
111 :
112 0 : void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
113 : uint64_t entry)
114 : {
115 0 : void __iomem *ptr = rdev->gart.ptr;
116 :
117 : /* on x86 we want this to be CPU endian, on powerpc
118 : * on powerpc without HW swappers, it'll get swapped on way
119 : * into VRAM - so no need for cpu_to_le32 on VRAM tables */
120 0 : writel(entry, ((void __iomem *)ptr) + (i * 4));
121 0 : }
122 :
123 0 : int rv370_pcie_gart_init(struct radeon_device *rdev)
124 : {
125 : int r;
126 :
127 0 : if (rdev->gart.robj) {
128 0 : WARN(1, "RV370 PCIE GART already initialized\n");
129 0 : return 0;
130 : }
131 : /* Initialize common gart structure */
132 0 : r = radeon_gart_init(rdev);
133 0 : if (r)
134 0 : return r;
135 0 : r = rv370_debugfs_pcie_gart_info_init(rdev);
136 0 : if (r)
137 0 : DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
138 0 : rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
139 0 : rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
140 0 : rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
141 0 : rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
142 0 : return radeon_gart_table_vram_alloc(rdev);
143 0 : }
144 :
145 0 : int rv370_pcie_gart_enable(struct radeon_device *rdev)
146 : {
147 : uint32_t table_addr;
148 : uint32_t tmp;
149 : int r;
150 :
151 0 : if (rdev->gart.robj == NULL) {
152 0 : dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
153 0 : return -EINVAL;
154 : }
155 0 : r = radeon_gart_table_vram_pin(rdev);
156 0 : if (r)
157 0 : return r;
158 : /* discard memory request outside of configured range */
159 : tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
160 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
161 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
162 0 : tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
163 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
164 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
165 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
166 0 : table_addr = rdev->gart.table_addr;
167 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
168 : /* FIXME: setup default page */
169 0 : WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
170 0 : WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
171 : /* Clear error */
172 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
173 0 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
174 0 : tmp |= RADEON_PCIE_TX_GART_EN;
175 0 : tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
176 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
177 0 : rv370_pcie_gart_tlb_flush(rdev);
178 : DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
179 : (unsigned)(rdev->mc.gtt_size >> 20),
180 : (unsigned long long)table_addr);
181 0 : rdev->gart.ready = true;
182 0 : return 0;
183 0 : }
184 :
185 0 : void rv370_pcie_gart_disable(struct radeon_device *rdev)
186 : {
187 : u32 tmp;
188 :
189 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
190 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
191 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
192 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
193 0 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
194 0 : tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
195 0 : WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
196 0 : radeon_gart_table_vram_unpin(rdev);
197 0 : }
198 :
199 0 : void rv370_pcie_gart_fini(struct radeon_device *rdev)
200 : {
201 0 : radeon_gart_fini(rdev);
202 0 : rv370_pcie_gart_disable(rdev);
203 0 : radeon_gart_table_vram_free(rdev);
204 0 : }
205 :
206 0 : void r300_fence_ring_emit(struct radeon_device *rdev,
207 : struct radeon_fence *fence)
208 : {
209 0 : struct radeon_ring *ring = &rdev->ring[fence->ring];
210 :
211 : /* Who ever call radeon_fence_emit should call ring_lock and ask
212 : * for enough space (today caller are ib schedule and buffer move) */
213 : /* Write SC register so SC & US assert idle */
214 0 : radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
215 0 : radeon_ring_write(ring, 0);
216 0 : radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
217 0 : radeon_ring_write(ring, 0);
218 : /* Flush 3D cache */
219 0 : radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
220 0 : radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
221 0 : radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
222 0 : radeon_ring_write(ring, R300_ZC_FLUSH);
223 : /* Wait until IDLE & CLEAN */
224 0 : radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
225 0 : radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
226 : RADEON_WAIT_2D_IDLECLEAN |
227 : RADEON_WAIT_DMA_GUI_IDLE));
228 0 : radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
229 0 : radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
230 : RADEON_HDP_READ_BUFFER_INVALIDATE);
231 0 : radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
232 0 : radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
233 : /* Emit fence sequence & fire IRQ */
234 0 : radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
235 0 : radeon_ring_write(ring, fence->seq);
236 0 : radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
237 0 : radeon_ring_write(ring, RADEON_SW_INT_FIRE);
238 0 : }
239 :
240 0 : void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
241 : {
242 : unsigned gb_tile_config;
243 : int r;
244 :
245 : /* Sub pixel 1/12 so we can have 4K rendering according to doc */
246 : gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
247 0 : switch(rdev->num_gb_pipes) {
248 : case 2:
249 : gb_tile_config |= R300_PIPE_COUNT_R300;
250 0 : break;
251 : case 3:
252 : gb_tile_config |= R300_PIPE_COUNT_R420_3P;
253 0 : break;
254 : case 4:
255 : gb_tile_config |= R300_PIPE_COUNT_R420;
256 0 : break;
257 : case 1:
258 : default:
259 : gb_tile_config |= R300_PIPE_COUNT_RV350;
260 0 : break;
261 : }
262 :
263 0 : r = radeon_ring_lock(rdev, ring, 64);
264 0 : if (r) {
265 0 : return;
266 : }
267 0 : radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
268 0 : radeon_ring_write(ring,
269 : RADEON_ISYNC_ANY2D_IDLE3D |
270 : RADEON_ISYNC_ANY3D_IDLE2D |
271 : RADEON_ISYNC_WAIT_IDLEGUI |
272 : RADEON_ISYNC_CPSCRATCH_IDLEGUI);
273 0 : radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
274 0 : radeon_ring_write(ring, gb_tile_config);
275 0 : radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
276 0 : radeon_ring_write(ring,
277 : RADEON_WAIT_2D_IDLECLEAN |
278 : RADEON_WAIT_3D_IDLECLEAN);
279 0 : radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
280 0 : radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
281 0 : radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
282 0 : radeon_ring_write(ring, 0);
283 0 : radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
284 0 : radeon_ring_write(ring, 0);
285 0 : radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
286 0 : radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
287 0 : radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
288 0 : radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
289 0 : radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
290 0 : radeon_ring_write(ring,
291 : RADEON_WAIT_2D_IDLECLEAN |
292 : RADEON_WAIT_3D_IDLECLEAN);
293 0 : radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
294 0 : radeon_ring_write(ring, 0);
295 0 : radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
296 0 : radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
297 0 : radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
298 0 : radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
299 0 : radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
300 0 : radeon_ring_write(ring,
301 : ((6 << R300_MS_X0_SHIFT) |
302 : (6 << R300_MS_Y0_SHIFT) |
303 : (6 << R300_MS_X1_SHIFT) |
304 : (6 << R300_MS_Y1_SHIFT) |
305 : (6 << R300_MS_X2_SHIFT) |
306 : (6 << R300_MS_Y2_SHIFT) |
307 : (6 << R300_MSBD0_Y_SHIFT) |
308 : (6 << R300_MSBD0_X_SHIFT)));
309 0 : radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
310 0 : radeon_ring_write(ring,
311 : ((6 << R300_MS_X3_SHIFT) |
312 : (6 << R300_MS_Y3_SHIFT) |
313 : (6 << R300_MS_X4_SHIFT) |
314 : (6 << R300_MS_Y4_SHIFT) |
315 : (6 << R300_MS_X5_SHIFT) |
316 : (6 << R300_MS_Y5_SHIFT) |
317 : (6 << R300_MSBD1_SHIFT)));
318 0 : radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
319 0 : radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
320 0 : radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
321 0 : radeon_ring_write(ring,
322 : R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
323 0 : radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
324 0 : radeon_ring_write(ring,
325 : R300_GEOMETRY_ROUND_NEAREST |
326 : R300_COLOR_ROUND_NEAREST);
327 0 : radeon_ring_unlock_commit(rdev, ring, false);
328 0 : }
329 :
330 0 : static void r300_errata(struct radeon_device *rdev)
331 : {
332 0 : rdev->pll_errata = 0;
333 :
334 0 : if (rdev->family == CHIP_R300 &&
335 0 : (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
336 0 : rdev->pll_errata |= CHIP_ERRATA_R300_CG;
337 0 : }
338 0 : }
339 :
340 0 : int r300_mc_wait_for_idle(struct radeon_device *rdev)
341 : {
342 : unsigned i;
343 : uint32_t tmp;
344 :
345 0 : for (i = 0; i < rdev->usec_timeout; i++) {
346 : /* read MC_STATUS */
347 0 : tmp = RREG32(RADEON_MC_STATUS);
348 0 : if (tmp & R300_MC_IDLE) {
349 0 : return 0;
350 : }
351 0 : DRM_UDELAY(1);
352 : }
353 0 : return -1;
354 0 : }
355 :
356 0 : static void r300_gpu_init(struct radeon_device *rdev)
357 : {
358 : uint32_t gb_tile_config, tmp;
359 :
360 0 : if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
361 0 : (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
362 : /* r300,r350 */
363 0 : rdev->num_gb_pipes = 2;
364 0 : } else {
365 : /* rv350,rv370,rv380,r300 AD, r350 AH */
366 0 : rdev->num_gb_pipes = 1;
367 : }
368 0 : rdev->num_z_pipes = 1;
369 : gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
370 0 : switch (rdev->num_gb_pipes) {
371 : case 2:
372 : gb_tile_config |= R300_PIPE_COUNT_R300;
373 0 : break;
374 : case 3:
375 : gb_tile_config |= R300_PIPE_COUNT_R420_3P;
376 0 : break;
377 : case 4:
378 : gb_tile_config |= R300_PIPE_COUNT_R420;
379 0 : break;
380 : default:
381 : case 1:
382 : gb_tile_config |= R300_PIPE_COUNT_RV350;
383 0 : break;
384 : }
385 0 : WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
386 :
387 0 : if (r100_gui_wait_for_idle(rdev)) {
388 0 : printk(KERN_WARNING "Failed to wait GUI idle while "
389 : "programming pipes. Bad things might happen.\n");
390 0 : }
391 :
392 0 : tmp = RREG32(R300_DST_PIPE_CONFIG);
393 0 : WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
394 :
395 0 : WREG32(R300_RB2D_DSTCACHE_MODE,
396 : R300_DC_AUTOFLUSH_ENABLE |
397 : R300_DC_DC_DISABLE_IGNORE_PE);
398 :
399 0 : if (r100_gui_wait_for_idle(rdev)) {
400 0 : printk(KERN_WARNING "Failed to wait GUI idle while "
401 : "programming pipes. Bad things might happen.\n");
402 0 : }
403 0 : if (r300_mc_wait_for_idle(rdev)) {
404 0 : printk(KERN_WARNING "Failed to wait MC idle while "
405 : "programming pipes. Bad things might happen.\n");
406 0 : }
407 : DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
408 : rdev->num_gb_pipes, rdev->num_z_pipes);
409 0 : }
410 :
411 0 : int r300_asic_reset(struct radeon_device *rdev)
412 : {
413 0 : struct r100_mc_save save;
414 : u32 status, tmp;
415 : int ret = 0;
416 :
417 0 : status = RREG32(R_000E40_RBBM_STATUS);
418 0 : if (!G_000E40_GUI_ACTIVE(status)) {
419 0 : return 0;
420 : }
421 0 : r100_mc_stop(rdev, &save);
422 0 : status = RREG32(R_000E40_RBBM_STATUS);
423 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
424 : /* stop CP */
425 0 : WREG32(RADEON_CP_CSQ_CNTL, 0);
426 0 : tmp = RREG32(RADEON_CP_RB_CNTL);
427 0 : WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
428 0 : WREG32(RADEON_CP_RB_RPTR_WR, 0);
429 0 : WREG32(RADEON_CP_RB_WPTR, 0);
430 0 : WREG32(RADEON_CP_RB_CNTL, tmp);
431 : /* save PCI state */
432 : pci_save_state(rdev->pdev);
433 : /* disable bus mastering */
434 0 : r100_bm_disable(rdev);
435 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
436 : S_0000F0_SOFT_RESET_GA(1));
437 0 : RREG32(R_0000F0_RBBM_SOFT_RESET);
438 0 : mdelay(500);
439 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
440 0 : mdelay(1);
441 0 : status = RREG32(R_000E40_RBBM_STATUS);
442 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
443 : /* resetting the CP seems to be problematic sometimes it end up
444 : * hard locking the computer, but it's necessary for successful
445 : * reset more test & playing is needed on R3XX/R4XX to find a
446 : * reliable (if any solution)
447 : */
448 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
449 0 : RREG32(R_0000F0_RBBM_SOFT_RESET);
450 0 : mdelay(500);
451 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
452 0 : mdelay(1);
453 0 : status = RREG32(R_000E40_RBBM_STATUS);
454 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
455 : /* restore PCI & busmastering */
456 : pci_restore_state(rdev->pdev);
457 0 : r100_enable_bm(rdev);
458 : /* Check if GPU is idle */
459 0 : if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
460 0 : dev_err(rdev->dev, "failed to reset GPU\n");
461 : ret = -1;
462 0 : } else
463 : dev_info(rdev->dev, "GPU reset succeed\n");
464 0 : r100_mc_resume(rdev, &save);
465 0 : return ret;
466 0 : }
467 :
468 : /*
469 : * r300,r350,rv350,rv380 VRAM info
470 : */
471 0 : void r300_mc_init(struct radeon_device *rdev)
472 : {
473 : u64 base;
474 : u32 tmp;
475 :
476 : /* DDR for all card after R300 & IGP */
477 0 : rdev->mc.vram_is_ddr = true;
478 0 : tmp = RREG32(RADEON_MEM_CNTL);
479 0 : tmp &= R300_MEM_NUM_CHANNELS_MASK;
480 0 : switch (tmp) {
481 0 : case 0: rdev->mc.vram_width = 64; break;
482 0 : case 1: rdev->mc.vram_width = 128; break;
483 0 : case 2: rdev->mc.vram_width = 256; break;
484 0 : default: rdev->mc.vram_width = 128; break;
485 : }
486 0 : r100_vram_init_sizes(rdev);
487 0 : base = rdev->mc.aper_base;
488 0 : if (rdev->flags & RADEON_IS_IGP)
489 0 : base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
490 0 : radeon_vram_location(rdev, &rdev->mc, base);
491 0 : rdev->mc.gtt_base_align = 0;
492 0 : if (!(rdev->flags & RADEON_IS_AGP))
493 0 : radeon_gtt_location(rdev, &rdev->mc);
494 0 : radeon_update_bandwidth_info(rdev);
495 0 : }
496 :
497 0 : void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
498 : {
499 : uint32_t link_width_cntl, mask;
500 :
501 0 : if (rdev->flags & RADEON_IS_IGP)
502 0 : return;
503 :
504 0 : if (!(rdev->flags & RADEON_IS_PCIE))
505 0 : return;
506 :
507 : /* FIXME wait for idle */
508 :
509 0 : switch (lanes) {
510 : case 0:
511 : mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
512 0 : break;
513 : case 1:
514 : mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
515 0 : break;
516 : case 2:
517 : mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
518 0 : break;
519 : case 4:
520 : mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
521 0 : break;
522 : case 8:
523 : mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
524 0 : break;
525 : case 12:
526 : mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
527 0 : break;
528 : case 16:
529 : default:
530 : mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
531 0 : break;
532 : }
533 :
534 0 : link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
535 :
536 0 : if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
537 0 : (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
538 0 : return;
539 :
540 0 : link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
541 : RADEON_PCIE_LC_RECONFIG_NOW |
542 : RADEON_PCIE_LC_RECONFIG_LATER |
543 : RADEON_PCIE_LC_SHORT_RECONFIG_EN);
544 0 : link_width_cntl |= mask;
545 0 : WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
546 0 : WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
547 : RADEON_PCIE_LC_RECONFIG_NOW));
548 :
549 : /* wait for lane set to complete */
550 0 : link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
551 0 : while (link_width_cntl == 0xffffffff)
552 0 : link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
553 :
554 0 : }
555 :
556 0 : int rv370_get_pcie_lanes(struct radeon_device *rdev)
557 : {
558 : u32 link_width_cntl;
559 :
560 0 : if (rdev->flags & RADEON_IS_IGP)
561 0 : return 0;
562 :
563 0 : if (!(rdev->flags & RADEON_IS_PCIE))
564 0 : return 0;
565 :
566 : /* FIXME wait for idle */
567 :
568 0 : link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
569 :
570 0 : switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
571 : case RADEON_PCIE_LC_LINK_WIDTH_X0:
572 0 : return 0;
573 : case RADEON_PCIE_LC_LINK_WIDTH_X1:
574 0 : return 1;
575 : case RADEON_PCIE_LC_LINK_WIDTH_X2:
576 0 : return 2;
577 : case RADEON_PCIE_LC_LINK_WIDTH_X4:
578 0 : return 4;
579 : case RADEON_PCIE_LC_LINK_WIDTH_X8:
580 0 : return 8;
581 : case RADEON_PCIE_LC_LINK_WIDTH_X16:
582 : default:
583 0 : return 16;
584 : }
585 0 : }
586 :
587 : #if defined(CONFIG_DEBUG_FS)
588 : static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
589 : {
590 : struct drm_info_node *node = (struct drm_info_node *) m->private;
591 : struct drm_device *dev = node->minor->dev;
592 : struct radeon_device *rdev = dev->dev_private;
593 : uint32_t tmp;
594 :
595 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
596 : seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
597 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
598 : seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
599 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
600 : seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
601 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
602 : seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
603 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
604 : seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
605 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
606 : seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
607 : tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
608 : seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
609 : return 0;
610 : }
611 :
612 : static struct drm_info_list rv370_pcie_gart_info_list[] = {
613 : {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
614 : };
615 : #endif
616 :
617 0 : static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
618 : {
619 : #if defined(CONFIG_DEBUG_FS)
620 : return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
621 : #else
622 0 : return 0;
623 : #endif
624 : }
625 :
626 0 : static int r300_packet0_check(struct radeon_cs_parser *p,
627 : struct radeon_cs_packet *pkt,
628 : unsigned idx, unsigned reg)
629 : {
630 0 : struct radeon_bo_list *reloc;
631 : struct r100_cs_track *track;
632 : volatile uint32_t *ib;
633 : uint32_t tmp, tile_flags = 0;
634 : unsigned i;
635 : int r;
636 : u32 idx_value;
637 :
638 0 : ib = p->ib.ptr;
639 0 : track = (struct r100_cs_track *)p->track;
640 0 : idx_value = radeon_get_ib_value(p, idx);
641 :
642 0 : switch(reg) {
643 : case AVIVO_D1MODE_VLINE_START_END:
644 : case RADEON_CRTC_GUI_TRIG_VLINE:
645 0 : r = r100_cs_packet_parse_vline(p);
646 0 : if (r) {
647 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
648 : idx, reg);
649 0 : radeon_cs_dump_packet(p, pkt);
650 0 : return r;
651 : }
652 : break;
653 : case RADEON_DST_PITCH_OFFSET:
654 : case RADEON_SRC_PITCH_OFFSET:
655 0 : r = r100_reloc_pitch_offset(p, pkt, idx, reg);
656 0 : if (r)
657 0 : return r;
658 : break;
659 : case R300_RB3D_COLOROFFSET0:
660 : case R300_RB3D_COLOROFFSET1:
661 : case R300_RB3D_COLOROFFSET2:
662 : case R300_RB3D_COLOROFFSET3:
663 0 : i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
664 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
665 0 : if (r) {
666 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
667 : idx, reg);
668 0 : radeon_cs_dump_packet(p, pkt);
669 0 : return r;
670 : }
671 0 : track->cb[i].robj = reloc->robj;
672 0 : track->cb[i].offset = idx_value;
673 0 : track->cb_dirty = true;
674 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
675 0 : break;
676 : case R300_ZB_DEPTHOFFSET:
677 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
678 0 : if (r) {
679 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
680 : idx, reg);
681 0 : radeon_cs_dump_packet(p, pkt);
682 0 : return r;
683 : }
684 0 : track->zb.robj = reloc->robj;
685 0 : track->zb.offset = idx_value;
686 0 : track->zb_dirty = true;
687 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
688 0 : break;
689 : case R300_TX_OFFSET_0:
690 : case R300_TX_OFFSET_0+4:
691 : case R300_TX_OFFSET_0+8:
692 : case R300_TX_OFFSET_0+12:
693 : case R300_TX_OFFSET_0+16:
694 : case R300_TX_OFFSET_0+20:
695 : case R300_TX_OFFSET_0+24:
696 : case R300_TX_OFFSET_0+28:
697 : case R300_TX_OFFSET_0+32:
698 : case R300_TX_OFFSET_0+36:
699 : case R300_TX_OFFSET_0+40:
700 : case R300_TX_OFFSET_0+44:
701 : case R300_TX_OFFSET_0+48:
702 : case R300_TX_OFFSET_0+52:
703 : case R300_TX_OFFSET_0+56:
704 : case R300_TX_OFFSET_0+60:
705 0 : i = (reg - R300_TX_OFFSET_0) >> 2;
706 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
707 0 : if (r) {
708 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
709 : idx, reg);
710 0 : radeon_cs_dump_packet(p, pkt);
711 0 : return r;
712 : }
713 :
714 0 : if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
715 0 : ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
716 0 : ((idx_value & ~31) + (u32)reloc->gpu_offset);
717 0 : } else {
718 0 : if (reloc->tiling_flags & RADEON_TILING_MACRO)
719 0 : tile_flags |= R300_TXO_MACRO_TILE;
720 0 : if (reloc->tiling_flags & RADEON_TILING_MICRO)
721 0 : tile_flags |= R300_TXO_MICRO_TILE;
722 0 : else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
723 0 : tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
724 :
725 0 : tmp = idx_value + ((u32)reloc->gpu_offset);
726 0 : tmp |= tile_flags;
727 0 : ib[idx] = tmp;
728 : }
729 0 : track->textures[i].robj = reloc->robj;
730 0 : track->tex_dirty = true;
731 0 : break;
732 : /* Tracked registers */
733 : case 0x2084:
734 : /* VAP_VF_CNTL */
735 0 : track->vap_vf_cntl = idx_value;
736 0 : break;
737 : case 0x20B4:
738 : /* VAP_VTX_SIZE */
739 0 : track->vtx_size = idx_value & 0x7F;
740 0 : break;
741 : case 0x2134:
742 : /* VAP_VF_MAX_VTX_INDX */
743 0 : track->max_indx = idx_value & 0x00FFFFFFUL;
744 0 : break;
745 : case 0x2088:
746 : /* VAP_ALT_NUM_VERTICES - only valid on r500 */
747 0 : if (p->rdev->family < CHIP_RV515)
748 : goto fail;
749 0 : track->vap_alt_nverts = idx_value & 0xFFFFFF;
750 0 : break;
751 : case 0x43E4:
752 : /* SC_SCISSOR1 */
753 0 : track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
754 0 : if (p->rdev->family < CHIP_RV515) {
755 0 : track->maxy -= 1440;
756 0 : }
757 0 : track->cb_dirty = true;
758 0 : track->zb_dirty = true;
759 0 : break;
760 : case 0x4E00:
761 : /* RB3D_CCTL */
762 0 : if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
763 0 : p->rdev->cmask_filp != p->filp) {
764 0 : DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
765 0 : return -EINVAL;
766 : }
767 0 : track->num_cb = ((idx_value >> 5) & 0x3) + 1;
768 0 : track->cb_dirty = true;
769 0 : break;
770 : case 0x4E38:
771 : case 0x4E3C:
772 : case 0x4E40:
773 : case 0x4E44:
774 : /* RB3D_COLORPITCH0 */
775 : /* RB3D_COLORPITCH1 */
776 : /* RB3D_COLORPITCH2 */
777 : /* RB3D_COLORPITCH3 */
778 0 : if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
779 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
780 0 : if (r) {
781 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
782 : idx, reg);
783 0 : radeon_cs_dump_packet(p, pkt);
784 0 : return r;
785 : }
786 :
787 0 : if (reloc->tiling_flags & RADEON_TILING_MACRO)
788 0 : tile_flags |= R300_COLOR_TILE_ENABLE;
789 0 : if (reloc->tiling_flags & RADEON_TILING_MICRO)
790 0 : tile_flags |= R300_COLOR_MICROTILE_ENABLE;
791 0 : else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
792 0 : tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
793 :
794 0 : tmp = idx_value & ~(0x7 << 16);
795 0 : tmp |= tile_flags;
796 0 : ib[idx] = tmp;
797 0 : }
798 0 : i = (reg - 0x4E38) >> 2;
799 0 : track->cb[i].pitch = idx_value & 0x3FFE;
800 0 : switch (((idx_value >> 21) & 0xF)) {
801 : case 9:
802 : case 11:
803 : case 12:
804 0 : track->cb[i].cpp = 1;
805 0 : break;
806 : case 3:
807 : case 4:
808 : case 13:
809 : case 15:
810 0 : track->cb[i].cpp = 2;
811 0 : break;
812 : case 5:
813 0 : if (p->rdev->family < CHIP_RV515) {
814 0 : DRM_ERROR("Invalid color buffer format (%d)!\n",
815 : ((idx_value >> 21) & 0xF));
816 0 : return -EINVAL;
817 : }
818 : /* Pass through. */
819 : case 6:
820 0 : track->cb[i].cpp = 4;
821 0 : break;
822 : case 10:
823 0 : track->cb[i].cpp = 8;
824 0 : break;
825 : case 7:
826 0 : track->cb[i].cpp = 16;
827 0 : break;
828 : default:
829 0 : DRM_ERROR("Invalid color buffer format (%d) !\n",
830 : ((idx_value >> 21) & 0xF));
831 0 : return -EINVAL;
832 : }
833 0 : track->cb_dirty = true;
834 0 : break;
835 : case 0x4F00:
836 : /* ZB_CNTL */
837 0 : if (idx_value & 2) {
838 0 : track->z_enabled = true;
839 0 : } else {
840 0 : track->z_enabled = false;
841 : }
842 0 : track->zb_dirty = true;
843 0 : break;
844 : case 0x4F10:
845 : /* ZB_FORMAT */
846 0 : switch ((idx_value & 0xF)) {
847 : case 0:
848 : case 1:
849 0 : track->zb.cpp = 2;
850 0 : break;
851 : case 2:
852 0 : track->zb.cpp = 4;
853 0 : break;
854 : default:
855 0 : DRM_ERROR("Invalid z buffer format (%d) !\n",
856 : (idx_value & 0xF));
857 0 : return -EINVAL;
858 : }
859 0 : track->zb_dirty = true;
860 0 : break;
861 : case 0x4F24:
862 : /* ZB_DEPTHPITCH */
863 0 : if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
864 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
865 0 : if (r) {
866 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
867 : idx, reg);
868 0 : radeon_cs_dump_packet(p, pkt);
869 0 : return r;
870 : }
871 :
872 0 : if (reloc->tiling_flags & RADEON_TILING_MACRO)
873 0 : tile_flags |= R300_DEPTHMACROTILE_ENABLE;
874 0 : if (reloc->tiling_flags & RADEON_TILING_MICRO)
875 0 : tile_flags |= R300_DEPTHMICROTILE_TILED;
876 0 : else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
877 0 : tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
878 :
879 0 : tmp = idx_value & ~(0x7 << 16);
880 0 : tmp |= tile_flags;
881 0 : ib[idx] = tmp;
882 0 : }
883 0 : track->zb.pitch = idx_value & 0x3FFC;
884 0 : track->zb_dirty = true;
885 0 : break;
886 : case 0x4104:
887 : /* TX_ENABLE */
888 0 : for (i = 0; i < 16; i++) {
889 : bool enabled;
890 :
891 0 : enabled = !!(idx_value & (1 << i));
892 0 : track->textures[i].enabled = enabled;
893 : }
894 0 : track->tex_dirty = true;
895 0 : break;
896 : case 0x44C0:
897 : case 0x44C4:
898 : case 0x44C8:
899 : case 0x44CC:
900 : case 0x44D0:
901 : case 0x44D4:
902 : case 0x44D8:
903 : case 0x44DC:
904 : case 0x44E0:
905 : case 0x44E4:
906 : case 0x44E8:
907 : case 0x44EC:
908 : case 0x44F0:
909 : case 0x44F4:
910 : case 0x44F8:
911 : case 0x44FC:
912 : /* TX_FORMAT1_[0-15] */
913 0 : i = (reg - 0x44C0) >> 2;
914 0 : tmp = (idx_value >> 25) & 0x3;
915 0 : track->textures[i].tex_coord_type = tmp;
916 0 : switch ((idx_value & 0x1F)) {
917 : case R300_TX_FORMAT_X8:
918 : case R300_TX_FORMAT_Y4X4:
919 : case R300_TX_FORMAT_Z3Y3X2:
920 0 : track->textures[i].cpp = 1;
921 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
922 0 : break;
923 : case R300_TX_FORMAT_X16:
924 : case R300_TX_FORMAT_FL_I16:
925 : case R300_TX_FORMAT_Y8X8:
926 : case R300_TX_FORMAT_Z5Y6X5:
927 : case R300_TX_FORMAT_Z6Y5X5:
928 : case R300_TX_FORMAT_W4Z4Y4X4:
929 : case R300_TX_FORMAT_W1Z5Y5X5:
930 : case R300_TX_FORMAT_D3DMFT_CxV8U8:
931 : case R300_TX_FORMAT_B8G8_B8G8:
932 : case R300_TX_FORMAT_G8R8_G8B8:
933 0 : track->textures[i].cpp = 2;
934 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
935 0 : break;
936 : case R300_TX_FORMAT_Y16X16:
937 : case R300_TX_FORMAT_FL_I16A16:
938 : case R300_TX_FORMAT_Z11Y11X10:
939 : case R300_TX_FORMAT_Z10Y11X11:
940 : case R300_TX_FORMAT_W8Z8Y8X8:
941 : case R300_TX_FORMAT_W2Z10Y10X10:
942 : case 0x17:
943 : case R300_TX_FORMAT_FL_I32:
944 : case 0x1e:
945 0 : track->textures[i].cpp = 4;
946 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
947 0 : break;
948 : case R300_TX_FORMAT_W16Z16Y16X16:
949 : case R300_TX_FORMAT_FL_R16G16B16A16:
950 : case R300_TX_FORMAT_FL_I32A32:
951 0 : track->textures[i].cpp = 8;
952 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
953 0 : break;
954 : case R300_TX_FORMAT_FL_R32G32B32A32:
955 0 : track->textures[i].cpp = 16;
956 0 : track->textures[i].compress_format = R100_TRACK_COMP_NONE;
957 0 : break;
958 : case R300_TX_FORMAT_DXT1:
959 0 : track->textures[i].cpp = 1;
960 0 : track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
961 0 : break;
962 : case R300_TX_FORMAT_ATI2N:
963 0 : if (p->rdev->family < CHIP_R420) {
964 0 : DRM_ERROR("Invalid texture format %u\n",
965 : (idx_value & 0x1F));
966 0 : return -EINVAL;
967 : }
968 : /* The same rules apply as for DXT3/5. */
969 : /* Pass through. */
970 : case R300_TX_FORMAT_DXT3:
971 : case R300_TX_FORMAT_DXT5:
972 0 : track->textures[i].cpp = 1;
973 0 : track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
974 0 : break;
975 : default:
976 0 : DRM_ERROR("Invalid texture format %u\n",
977 : (idx_value & 0x1F));
978 0 : return -EINVAL;
979 : }
980 0 : track->tex_dirty = true;
981 0 : break;
982 : case 0x4400:
983 : case 0x4404:
984 : case 0x4408:
985 : case 0x440C:
986 : case 0x4410:
987 : case 0x4414:
988 : case 0x4418:
989 : case 0x441C:
990 : case 0x4420:
991 : case 0x4424:
992 : case 0x4428:
993 : case 0x442C:
994 : case 0x4430:
995 : case 0x4434:
996 : case 0x4438:
997 : case 0x443C:
998 : /* TX_FILTER0_[0-15] */
999 0 : i = (reg - 0x4400) >> 2;
1000 0 : tmp = idx_value & 0x7;
1001 0 : if (tmp == 2 || tmp == 4 || tmp == 6) {
1002 0 : track->textures[i].roundup_w = false;
1003 0 : }
1004 0 : tmp = (idx_value >> 3) & 0x7;
1005 0 : if (tmp == 2 || tmp == 4 || tmp == 6) {
1006 0 : track->textures[i].roundup_h = false;
1007 0 : }
1008 0 : track->tex_dirty = true;
1009 0 : break;
1010 : case 0x4500:
1011 : case 0x4504:
1012 : case 0x4508:
1013 : case 0x450C:
1014 : case 0x4510:
1015 : case 0x4514:
1016 : case 0x4518:
1017 : case 0x451C:
1018 : case 0x4520:
1019 : case 0x4524:
1020 : case 0x4528:
1021 : case 0x452C:
1022 : case 0x4530:
1023 : case 0x4534:
1024 : case 0x4538:
1025 : case 0x453C:
1026 : /* TX_FORMAT2_[0-15] */
1027 0 : i = (reg - 0x4500) >> 2;
1028 0 : tmp = idx_value & 0x3FFF;
1029 0 : track->textures[i].pitch = tmp + 1;
1030 0 : if (p->rdev->family >= CHIP_RV515) {
1031 0 : tmp = ((idx_value >> 15) & 1) << 11;
1032 0 : track->textures[i].width_11 = tmp;
1033 0 : tmp = ((idx_value >> 16) & 1) << 11;
1034 0 : track->textures[i].height_11 = tmp;
1035 :
1036 : /* ATI1N */
1037 0 : if (idx_value & (1 << 14)) {
1038 : /* The same rules apply as for DXT1. */
1039 0 : track->textures[i].compress_format =
1040 : R100_TRACK_COMP_DXT1;
1041 0 : }
1042 0 : } else if (idx_value & (1 << 14)) {
1043 0 : DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1044 0 : return -EINVAL;
1045 : }
1046 0 : track->tex_dirty = true;
1047 0 : break;
1048 : case 0x4480:
1049 : case 0x4484:
1050 : case 0x4488:
1051 : case 0x448C:
1052 : case 0x4490:
1053 : case 0x4494:
1054 : case 0x4498:
1055 : case 0x449C:
1056 : case 0x44A0:
1057 : case 0x44A4:
1058 : case 0x44A8:
1059 : case 0x44AC:
1060 : case 0x44B0:
1061 : case 0x44B4:
1062 : case 0x44B8:
1063 : case 0x44BC:
1064 : /* TX_FORMAT0_[0-15] */
1065 0 : i = (reg - 0x4480) >> 2;
1066 0 : tmp = idx_value & 0x7FF;
1067 0 : track->textures[i].width = tmp + 1;
1068 0 : tmp = (idx_value >> 11) & 0x7FF;
1069 0 : track->textures[i].height = tmp + 1;
1070 0 : tmp = (idx_value >> 26) & 0xF;
1071 0 : track->textures[i].num_levels = tmp;
1072 0 : tmp = idx_value & (1 << 31);
1073 0 : track->textures[i].use_pitch = !!tmp;
1074 0 : tmp = (idx_value >> 22) & 0xF;
1075 0 : track->textures[i].txdepth = tmp;
1076 0 : track->tex_dirty = true;
1077 0 : break;
1078 : case R300_ZB_ZPASS_ADDR:
1079 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1080 0 : if (r) {
1081 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1082 : idx, reg);
1083 0 : radeon_cs_dump_packet(p, pkt);
1084 0 : return r;
1085 : }
1086 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1087 0 : break;
1088 : case 0x4e0c:
1089 : /* RB3D_COLOR_CHANNEL_MASK */
1090 0 : track->color_channel_mask = idx_value;
1091 0 : track->cb_dirty = true;
1092 0 : break;
1093 : case 0x43a4:
1094 : /* SC_HYPERZ_EN */
1095 : /* r300c emits this register - we need to disable hyperz for it
1096 : * without complaining */
1097 0 : if (p->rdev->hyperz_filp != p->filp) {
1098 0 : if (idx_value & 0x1)
1099 0 : ib[idx] = idx_value & ~1;
1100 : }
1101 : break;
1102 : case 0x4f1c:
1103 : /* ZB_BW_CNTL */
1104 0 : track->zb_cb_clear = !!(idx_value & (1 << 5));
1105 0 : track->cb_dirty = true;
1106 0 : track->zb_dirty = true;
1107 0 : if (p->rdev->hyperz_filp != p->filp) {
1108 0 : if (idx_value & (R300_HIZ_ENABLE |
1109 : R300_RD_COMP_ENABLE |
1110 : R300_WR_COMP_ENABLE |
1111 : R300_FAST_FILL_ENABLE))
1112 : goto fail;
1113 : }
1114 : break;
1115 : case 0x4e04:
1116 : /* RB3D_BLENDCNTL */
1117 0 : track->blend_read_enable = !!(idx_value & (1 << 2));
1118 0 : track->cb_dirty = true;
1119 0 : break;
1120 : case R300_RB3D_AARESOLVE_OFFSET:
1121 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1122 0 : if (r) {
1123 0 : DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1124 : idx, reg);
1125 0 : radeon_cs_dump_packet(p, pkt);
1126 0 : return r;
1127 : }
1128 0 : track->aa.robj = reloc->robj;
1129 0 : track->aa.offset = idx_value;
1130 0 : track->aa_dirty = true;
1131 0 : ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1132 0 : break;
1133 : case R300_RB3D_AARESOLVE_PITCH:
1134 0 : track->aa.pitch = idx_value & 0x3FFE;
1135 0 : track->aa_dirty = true;
1136 0 : break;
1137 : case R300_RB3D_AARESOLVE_CTL:
1138 0 : track->aaresolve = idx_value & 0x1;
1139 0 : track->aa_dirty = true;
1140 0 : break;
1141 : case 0x4f30: /* ZB_MASK_OFFSET */
1142 : case 0x4f34: /* ZB_ZMASK_PITCH */
1143 : case 0x4f44: /* ZB_HIZ_OFFSET */
1144 : case 0x4f54: /* ZB_HIZ_PITCH */
1145 0 : if (idx_value && (p->rdev->hyperz_filp != p->filp))
1146 : goto fail;
1147 : break;
1148 : case 0x4028:
1149 0 : if (idx_value && (p->rdev->hyperz_filp != p->filp))
1150 : goto fail;
1151 : /* GB_Z_PEQ_CONFIG */
1152 0 : if (p->rdev->family >= CHIP_RV350)
1153 : break;
1154 : goto fail;
1155 : break;
1156 : case 0x4be8:
1157 : /* valid register only on RV530 */
1158 0 : if (p->rdev->family == CHIP_RV530)
1159 : break;
1160 : /* fallthrough do not move */
1161 : default:
1162 : goto fail;
1163 : }
1164 0 : return 0;
1165 : fail:
1166 0 : printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1167 : reg, idx, idx_value);
1168 0 : return -EINVAL;
1169 0 : }
1170 :
1171 0 : static int r300_packet3_check(struct radeon_cs_parser *p,
1172 : struct radeon_cs_packet *pkt)
1173 : {
1174 0 : struct radeon_bo_list *reloc;
1175 : struct r100_cs_track *track;
1176 : volatile uint32_t *ib;
1177 : unsigned idx;
1178 : int r;
1179 :
1180 0 : ib = p->ib.ptr;
1181 0 : idx = pkt->idx + 1;
1182 0 : track = (struct r100_cs_track *)p->track;
1183 0 : switch(pkt->opcode) {
1184 : case PACKET3_3D_LOAD_VBPNTR:
1185 0 : r = r100_packet3_load_vbpntr(p, pkt, idx);
1186 0 : if (r)
1187 0 : return r;
1188 : break;
1189 : case PACKET3_INDX_BUFFER:
1190 0 : r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1191 0 : if (r) {
1192 0 : DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1193 0 : radeon_cs_dump_packet(p, pkt);
1194 0 : return r;
1195 : }
1196 0 : ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1197 0 : r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1198 0 : if (r) {
1199 0 : return r;
1200 : }
1201 : break;
1202 : /* Draw packet */
1203 : case PACKET3_3D_DRAW_IMMD:
1204 : /* Number of dwords is vtx_size * (num_vertices - 1)
1205 : * PRIM_WALK must be equal to 3 vertex data in embedded
1206 : * in cmd stream */
1207 0 : if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1208 0 : DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1209 0 : return -EINVAL;
1210 : }
1211 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1212 0 : track->immd_dwords = pkt->count - 1;
1213 0 : r = r100_cs_track_check(p->rdev, track);
1214 0 : if (r) {
1215 0 : return r;
1216 : }
1217 : break;
1218 : case PACKET3_3D_DRAW_IMMD_2:
1219 : /* Number of dwords is vtx_size * (num_vertices - 1)
1220 : * PRIM_WALK must be equal to 3 vertex data in embedded
1221 : * in cmd stream */
1222 0 : if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1223 0 : DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1224 0 : return -EINVAL;
1225 : }
1226 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1227 0 : track->immd_dwords = pkt->count;
1228 0 : r = r100_cs_track_check(p->rdev, track);
1229 0 : if (r) {
1230 0 : return r;
1231 : }
1232 : break;
1233 : case PACKET3_3D_DRAW_VBUF:
1234 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1235 0 : r = r100_cs_track_check(p->rdev, track);
1236 0 : if (r) {
1237 0 : return r;
1238 : }
1239 : break;
1240 : case PACKET3_3D_DRAW_VBUF_2:
1241 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1242 0 : r = r100_cs_track_check(p->rdev, track);
1243 0 : if (r) {
1244 0 : return r;
1245 : }
1246 : break;
1247 : case PACKET3_3D_DRAW_INDX:
1248 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1249 0 : r = r100_cs_track_check(p->rdev, track);
1250 0 : if (r) {
1251 0 : return r;
1252 : }
1253 : break;
1254 : case PACKET3_3D_DRAW_INDX_2:
1255 0 : track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1256 0 : r = r100_cs_track_check(p->rdev, track);
1257 0 : if (r) {
1258 0 : return r;
1259 : }
1260 : break;
1261 : case PACKET3_3D_CLEAR_HIZ:
1262 : case PACKET3_3D_CLEAR_ZMASK:
1263 0 : if (p->rdev->hyperz_filp != p->filp)
1264 0 : return -EINVAL;
1265 : break;
1266 : case PACKET3_3D_CLEAR_CMASK:
1267 0 : if (p->rdev->cmask_filp != p->filp)
1268 0 : return -EINVAL;
1269 : break;
1270 : case PACKET3_NOP:
1271 : break;
1272 : default:
1273 0 : DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1274 0 : return -EINVAL;
1275 : }
1276 0 : return 0;
1277 0 : }
1278 :
1279 0 : int r300_cs_parse(struct radeon_cs_parser *p)
1280 : {
1281 0 : struct radeon_cs_packet pkt;
1282 : struct r100_cs_track *track;
1283 : int r;
1284 :
1285 0 : track = kzalloc(sizeof(*track), GFP_KERNEL);
1286 0 : if (track == NULL)
1287 0 : return -ENOMEM;
1288 0 : r100_cs_track_clear(p->rdev, track);
1289 0 : p->track = track;
1290 0 : do {
1291 0 : r = radeon_cs_packet_parse(p, &pkt, p->idx);
1292 0 : if (r) {
1293 0 : return r;
1294 : }
1295 0 : p->idx += pkt.count + 2;
1296 0 : switch (pkt.type) {
1297 : case RADEON_PACKET_TYPE0:
1298 0 : r = r100_cs_parse_packet0(p, &pkt,
1299 0 : p->rdev->config.r300.reg_safe_bm,
1300 0 : p->rdev->config.r300.reg_safe_bm_size,
1301 : &r300_packet0_check);
1302 0 : break;
1303 : case RADEON_PACKET_TYPE2:
1304 : break;
1305 : case RADEON_PACKET_TYPE3:
1306 0 : r = r300_packet3_check(p, &pkt);
1307 0 : break;
1308 : default:
1309 0 : DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1310 0 : return -EINVAL;
1311 : }
1312 0 : if (r) {
1313 0 : return r;
1314 : }
1315 0 : } while (p->idx < p->chunk_ib->length_dw);
1316 0 : return 0;
1317 0 : }
1318 :
1319 0 : void r300_set_reg_safe(struct radeon_device *rdev)
1320 : {
1321 0 : rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1322 0 : rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1323 0 : }
1324 :
1325 0 : void r300_mc_program(struct radeon_device *rdev)
1326 : {
1327 0 : struct r100_mc_save save;
1328 : int r;
1329 :
1330 0 : r = r100_debugfs_mc_info_init(rdev);
1331 0 : if (r) {
1332 0 : dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1333 0 : }
1334 :
1335 : /* Stops all mc clients */
1336 0 : r100_mc_stop(rdev, &save);
1337 0 : if (rdev->flags & RADEON_IS_AGP) {
1338 0 : WREG32(R_00014C_MC_AGP_LOCATION,
1339 : S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1340 : S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1341 0 : WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1342 0 : WREG32(R_00015C_AGP_BASE_2,
1343 : upper_32_bits(rdev->mc.agp_base) & 0xff);
1344 0 : } else {
1345 0 : WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1346 0 : WREG32(R_000170_AGP_BASE, 0);
1347 0 : WREG32(R_00015C_AGP_BASE_2, 0);
1348 : }
1349 : /* Wait for mc idle */
1350 0 : if (r300_mc_wait_for_idle(rdev))
1351 : DRM_INFO("Failed to wait MC idle before programming MC.\n");
1352 : /* Program MC, should be a 32bits limited address space */
1353 0 : WREG32(R_000148_MC_FB_LOCATION,
1354 : S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1355 : S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1356 0 : r100_mc_resume(rdev, &save);
1357 0 : }
1358 :
1359 0 : void r300_clock_startup(struct radeon_device *rdev)
1360 : {
1361 : u32 tmp;
1362 :
1363 0 : if (radeon_dynclks != -1 && radeon_dynclks)
1364 0 : radeon_legacy_set_clock_gating(rdev, 1);
1365 : /* We need to force on some of the block */
1366 0 : tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1367 0 : tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1368 0 : if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1369 0 : tmp |= S_00000D_FORCE_VAP(1);
1370 0 : WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1371 0 : }
1372 :
1373 0 : static int r300_startup(struct radeon_device *rdev)
1374 : {
1375 : int r;
1376 :
1377 : /* set common regs */
1378 0 : r100_set_common_regs(rdev);
1379 : /* program mc */
1380 0 : r300_mc_program(rdev);
1381 : /* Resume clock */
1382 0 : r300_clock_startup(rdev);
1383 : /* Initialize GPU configuration (# pipes, ...) */
1384 0 : r300_gpu_init(rdev);
1385 : /* Initialize GART (initialize after TTM so we can allocate
1386 : * memory through TTM but finalize after TTM) */
1387 0 : if (rdev->flags & RADEON_IS_PCIE) {
1388 0 : r = rv370_pcie_gart_enable(rdev);
1389 0 : if (r)
1390 0 : return r;
1391 : }
1392 :
1393 0 : if (rdev->family == CHIP_R300 ||
1394 0 : rdev->family == CHIP_R350 ||
1395 0 : rdev->family == CHIP_RV350)
1396 0 : r100_enable_bm(rdev);
1397 :
1398 0 : if (rdev->flags & RADEON_IS_PCI) {
1399 0 : r = r100_pci_gart_enable(rdev);
1400 0 : if (r)
1401 0 : return r;
1402 : }
1403 :
1404 : /* allocate wb buffer */
1405 0 : r = radeon_wb_init(rdev);
1406 0 : if (r)
1407 0 : return r;
1408 :
1409 0 : r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1410 0 : if (r) {
1411 0 : dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1412 0 : return r;
1413 : }
1414 :
1415 : /* Enable IRQ */
1416 0 : if (!rdev->irq.installed) {
1417 0 : r = radeon_irq_kms_init(rdev);
1418 0 : if (r)
1419 0 : return r;
1420 : }
1421 :
1422 0 : r100_irq_set(rdev);
1423 0 : rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1424 : /* 1M ring buffer */
1425 0 : r = r100_cp_init(rdev, 1024 * 1024);
1426 0 : if (r) {
1427 0 : dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1428 0 : return r;
1429 : }
1430 :
1431 0 : r = radeon_ib_pool_init(rdev);
1432 0 : if (r) {
1433 0 : dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1434 0 : return r;
1435 : }
1436 :
1437 0 : return 0;
1438 0 : }
1439 :
1440 0 : int r300_resume(struct radeon_device *rdev)
1441 : {
1442 : int r;
1443 :
1444 : /* Make sur GART are not working */
1445 0 : if (rdev->flags & RADEON_IS_PCIE)
1446 0 : rv370_pcie_gart_disable(rdev);
1447 0 : if (rdev->flags & RADEON_IS_PCI)
1448 0 : r100_pci_gart_disable(rdev);
1449 : /* Resume clock before doing reset */
1450 0 : r300_clock_startup(rdev);
1451 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1452 0 : if (radeon_asic_reset(rdev)) {
1453 0 : dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1454 : RREG32(R_000E40_RBBM_STATUS),
1455 : RREG32(R_0007C0_CP_STAT));
1456 0 : }
1457 : /* post */
1458 0 : radeon_combios_asic_init(rdev->ddev);
1459 : /* Resume clock after posting */
1460 0 : r300_clock_startup(rdev);
1461 : /* Initialize surface registers */
1462 0 : radeon_surface_init(rdev);
1463 :
1464 0 : rdev->accel_working = true;
1465 0 : r = r300_startup(rdev);
1466 0 : if (r) {
1467 0 : rdev->accel_working = false;
1468 0 : }
1469 0 : return r;
1470 : }
1471 :
1472 0 : int r300_suspend(struct radeon_device *rdev)
1473 : {
1474 0 : radeon_pm_suspend(rdev);
1475 0 : r100_cp_disable(rdev);
1476 0 : radeon_wb_disable(rdev);
1477 0 : r100_irq_disable(rdev);
1478 0 : if (rdev->flags & RADEON_IS_PCIE)
1479 0 : rv370_pcie_gart_disable(rdev);
1480 0 : if (rdev->flags & RADEON_IS_PCI)
1481 0 : r100_pci_gart_disable(rdev);
1482 0 : return 0;
1483 : }
1484 :
1485 0 : void r300_fini(struct radeon_device *rdev)
1486 : {
1487 0 : radeon_pm_fini(rdev);
1488 0 : r100_cp_fini(rdev);
1489 0 : radeon_wb_fini(rdev);
1490 0 : radeon_ib_pool_fini(rdev);
1491 0 : radeon_gem_fini(rdev);
1492 0 : if (rdev->flags & RADEON_IS_PCIE)
1493 0 : rv370_pcie_gart_fini(rdev);
1494 0 : if (rdev->flags & RADEON_IS_PCI)
1495 0 : r100_pci_gart_fini(rdev);
1496 0 : radeon_agp_fini(rdev);
1497 0 : radeon_irq_kms_fini(rdev);
1498 0 : radeon_fence_driver_fini(rdev);
1499 0 : radeon_bo_fini(rdev);
1500 0 : radeon_atombios_fini(rdev);
1501 0 : kfree(rdev->bios);
1502 0 : rdev->bios = NULL;
1503 0 : }
1504 :
1505 0 : int r300_init(struct radeon_device *rdev)
1506 : {
1507 : int r;
1508 :
1509 : /* Disable VGA */
1510 0 : r100_vga_render_disable(rdev);
1511 : /* Initialize scratch registers */
1512 0 : radeon_scratch_init(rdev);
1513 : /* Initialize surface registers */
1514 0 : radeon_surface_init(rdev);
1515 : /* TODO: disable VGA need to use VGA request */
1516 : /* restore some register to sane defaults */
1517 0 : r100_restore_sanity(rdev);
1518 : /* BIOS*/
1519 0 : if (!radeon_get_bios(rdev)) {
1520 0 : if (ASIC_IS_AVIVO(rdev))
1521 0 : return -EINVAL;
1522 : }
1523 0 : if (rdev->is_atom_bios) {
1524 0 : dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1525 0 : return -EINVAL;
1526 : } else {
1527 0 : r = radeon_combios_init(rdev);
1528 0 : if (r)
1529 0 : return r;
1530 : }
1531 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1532 0 : if (radeon_asic_reset(rdev)) {
1533 0 : dev_warn(rdev->dev,
1534 : "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1535 : RREG32(R_000E40_RBBM_STATUS),
1536 : RREG32(R_0007C0_CP_STAT));
1537 0 : }
1538 : /* check if cards are posted or not */
1539 0 : if (radeon_boot_test_post_card(rdev) == false)
1540 0 : return -EINVAL;
1541 : /* Set asic errata */
1542 0 : r300_errata(rdev);
1543 : /* Initialize clocks */
1544 0 : radeon_get_clock_info(rdev->ddev);
1545 : /* initialize AGP */
1546 0 : if (rdev->flags & RADEON_IS_AGP) {
1547 0 : r = radeon_agp_init(rdev);
1548 0 : if (r) {
1549 0 : radeon_agp_disable(rdev);
1550 0 : }
1551 : }
1552 : /* initialize memory controller */
1553 0 : r300_mc_init(rdev);
1554 : /* Fence driver */
1555 0 : r = radeon_fence_driver_init(rdev);
1556 0 : if (r)
1557 0 : return r;
1558 : /* Memory manager */
1559 0 : r = radeon_bo_init(rdev);
1560 0 : if (r)
1561 0 : return r;
1562 0 : if (rdev->flags & RADEON_IS_PCIE) {
1563 0 : r = rv370_pcie_gart_init(rdev);
1564 0 : if (r)
1565 0 : return r;
1566 : }
1567 0 : if (rdev->flags & RADEON_IS_PCI) {
1568 0 : r = r100_pci_gart_init(rdev);
1569 0 : if (r)
1570 0 : return r;
1571 : }
1572 0 : r300_set_reg_safe(rdev);
1573 :
1574 : /* Initialize power management */
1575 0 : radeon_pm_init(rdev);
1576 :
1577 0 : rdev->accel_working = true;
1578 0 : r = r300_startup(rdev);
1579 0 : if (r) {
1580 : /* Something went wrong with the accel init, so stop accel */
1581 0 : dev_err(rdev->dev, "Disabling GPU acceleration\n");
1582 0 : r100_cp_fini(rdev);
1583 0 : radeon_wb_fini(rdev);
1584 0 : radeon_ib_pool_fini(rdev);
1585 0 : radeon_irq_kms_fini(rdev);
1586 0 : if (rdev->flags & RADEON_IS_PCIE)
1587 0 : rv370_pcie_gart_fini(rdev);
1588 0 : if (rdev->flags & RADEON_IS_PCI)
1589 0 : r100_pci_gart_fini(rdev);
1590 0 : radeon_agp_fini(rdev);
1591 0 : rdev->accel_working = false;
1592 0 : }
1593 0 : return 0;
1594 0 : }
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