Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Christian König.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Christian König
25 : */
26 : #include <dev/pci/drm/linux_hdmi.h>
27 : #include <dev/pci/drm/drmP.h>
28 : #include <dev/pci/drm/radeon_drm.h>
29 : #include "radeon.h"
30 : #include "radeon_asic.h"
31 : #include "radeon_audio.h"
32 : #include "r600d.h"
33 : #include "atom.h"
34 :
35 : /*
36 : * HDMI color format
37 : */
38 : enum r600_hdmi_color_format {
39 : RGB = 0,
40 : YCC_422 = 1,
41 : YCC_444 = 2
42 : };
43 :
44 : /*
45 : * IEC60958 status bits
46 : */
47 : enum r600_hdmi_iec_status_bits {
48 : AUDIO_STATUS_DIG_ENABLE = 0x01,
49 : AUDIO_STATUS_V = 0x02,
50 : AUDIO_STATUS_VCFG = 0x04,
51 : AUDIO_STATUS_EMPHASIS = 0x08,
52 : AUDIO_STATUS_COPYRIGHT = 0x10,
53 : AUDIO_STATUS_NONAUDIO = 0x20,
54 : AUDIO_STATUS_PROFESSIONAL = 0x40,
55 : AUDIO_STATUS_LEVEL = 0x80
56 : };
57 :
58 0 : static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
59 : {
60 0 : struct r600_audio_pin status;
61 : uint32_t value;
62 :
63 0 : value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
64 :
65 : /* number of channels */
66 0 : status.channels = (value & 0x7) + 1;
67 :
68 : /* bits per sample */
69 0 : switch ((value & 0xF0) >> 4) {
70 : case 0x0:
71 : status.bits_per_sample = 8;
72 0 : break;
73 : case 0x1:
74 : status.bits_per_sample = 16;
75 0 : break;
76 : case 0x2:
77 : status.bits_per_sample = 20;
78 0 : break;
79 : case 0x3:
80 : status.bits_per_sample = 24;
81 0 : break;
82 : case 0x4:
83 : status.bits_per_sample = 32;
84 0 : break;
85 : default:
86 0 : dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
87 : (int)value);
88 : status.bits_per_sample = 16;
89 0 : }
90 :
91 : /* current sampling rate in HZ */
92 0 : if (value & 0x4000)
93 0 : status.rate = 44100;
94 : else
95 : status.rate = 48000;
96 0 : status.rate *= ((value >> 11) & 0x7) + 1;
97 0 : status.rate /= ((value >> 8) & 0x7) + 1;
98 :
99 0 : value = RREG32(R600_AUDIO_STATUS_BITS);
100 :
101 : /* iec 60958 status bits */
102 0 : status.status_bits = value & 0xff;
103 :
104 : /* iec 60958 category code */
105 0 : status.category_code = (value >> 8) & 0xff;
106 :
107 0 : return status;
108 0 : }
109 :
110 : /*
111 : * update all hdmi interfaces with current audio parameters
112 : */
113 0 : void r600_audio_update_hdmi(struct work_struct *work)
114 : {
115 0 : struct radeon_device *rdev = container_of(work, struct radeon_device,
116 : audio_work);
117 0 : struct drm_device *dev = rdev->ddev;
118 0 : struct r600_audio_pin audio_status = r600_audio_status(rdev);
119 : struct drm_encoder *encoder;
120 : bool changed = false;
121 :
122 0 : if (rdev->audio.pin[0].channels != audio_status.channels ||
123 0 : rdev->audio.pin[0].rate != audio_status.rate ||
124 0 : rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
125 0 : rdev->audio.pin[0].status_bits != audio_status.status_bits ||
126 0 : rdev->audio.pin[0].category_code != audio_status.category_code) {
127 0 : rdev->audio.pin[0] = audio_status;
128 : changed = true;
129 0 : }
130 :
131 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
132 0 : if (!radeon_encoder_is_digital(encoder))
133 : continue;
134 0 : if (changed || r600_hdmi_buffer_status_changed(encoder))
135 0 : r600_hdmi_update_audio_settings(encoder);
136 : }
137 0 : }
138 :
139 : /* enable the audio stream */
140 0 : void r600_audio_enable(struct radeon_device *rdev,
141 : struct r600_audio_pin *pin,
142 : u8 enable_mask)
143 : {
144 0 : u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
145 :
146 0 : if (!pin)
147 0 : return;
148 :
149 0 : if (enable_mask) {
150 0 : tmp |= AUDIO_ENABLED;
151 0 : if (enable_mask & 1)
152 0 : tmp |= PIN0_AUDIO_ENABLED;
153 0 : if (enable_mask & 2)
154 0 : tmp |= PIN1_AUDIO_ENABLED;
155 0 : if (enable_mask & 4)
156 0 : tmp |= PIN2_AUDIO_ENABLED;
157 0 : if (enable_mask & 8)
158 0 : tmp |= PIN3_AUDIO_ENABLED;
159 : } else {
160 0 : tmp &= ~(AUDIO_ENABLED |
161 : PIN0_AUDIO_ENABLED |
162 : PIN1_AUDIO_ENABLED |
163 : PIN2_AUDIO_ENABLED |
164 : PIN3_AUDIO_ENABLED);
165 : }
166 :
167 0 : WREG32(AZ_HOT_PLUG_CONTROL, tmp);
168 0 : }
169 :
170 0 : struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
171 : {
172 : /* only one pin on 6xx-NI */
173 0 : return &rdev->audio.pin[0];
174 : }
175 :
176 0 : void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
177 : const struct radeon_hdmi_acr *acr)
178 : {
179 0 : struct drm_device *dev = encoder->dev;
180 0 : struct radeon_device *rdev = dev->dev_private;
181 :
182 : /* DCE 3.0 uses register that's normally for CRC_CONTROL */
183 0 : uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
184 : HDMI0_ACR_PACKET_CONTROL;
185 0 : WREG32_P(acr_ctl + offset,
186 : HDMI0_ACR_SOURCE | /* select SW CTS value */
187 : HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
188 : ~(HDMI0_ACR_SOURCE |
189 : HDMI0_ACR_AUTO_SEND));
190 :
191 0 : WREG32_P(HDMI0_ACR_32_0 + offset,
192 : HDMI0_ACR_CTS_32(acr->cts_32khz),
193 : ~HDMI0_ACR_CTS_32_MASK);
194 0 : WREG32_P(HDMI0_ACR_32_1 + offset,
195 : HDMI0_ACR_N_32(acr->n_32khz),
196 : ~HDMI0_ACR_N_32_MASK);
197 :
198 0 : WREG32_P(HDMI0_ACR_44_0 + offset,
199 : HDMI0_ACR_CTS_44(acr->cts_44_1khz),
200 : ~HDMI0_ACR_CTS_44_MASK);
201 0 : WREG32_P(HDMI0_ACR_44_1 + offset,
202 : HDMI0_ACR_N_44(acr->n_44_1khz),
203 : ~HDMI0_ACR_N_44_MASK);
204 :
205 0 : WREG32_P(HDMI0_ACR_48_0 + offset,
206 : HDMI0_ACR_CTS_48(acr->cts_48khz),
207 : ~HDMI0_ACR_CTS_48_MASK);
208 0 : WREG32_P(HDMI0_ACR_48_1 + offset,
209 : HDMI0_ACR_N_48(acr->n_48khz),
210 : ~HDMI0_ACR_N_48_MASK);
211 0 : }
212 :
213 : /*
214 : * build a HDMI Video Info Frame
215 : */
216 0 : void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,
217 : unsigned char *buffer, size_t size)
218 : {
219 0 : uint8_t *frame = buffer + 3;
220 :
221 0 : WREG32(HDMI0_AVI_INFO0 + offset,
222 : frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
223 0 : WREG32(HDMI0_AVI_INFO1 + offset,
224 : frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
225 0 : WREG32(HDMI0_AVI_INFO2 + offset,
226 : frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
227 0 : WREG32(HDMI0_AVI_INFO3 + offset,
228 : frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
229 :
230 0 : WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
231 : HDMI0_AVI_INFO_LINE(2)); /* anything other than 0 */
232 :
233 0 : WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
234 : HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
235 : HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */
236 :
237 0 : }
238 :
239 : /*
240 : * build a Audio Info Frame
241 : */
242 0 : static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
243 : const void *buffer, size_t size)
244 : {
245 0 : struct drm_device *dev = encoder->dev;
246 0 : struct radeon_device *rdev = dev->dev_private;
247 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
248 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
249 0 : uint32_t offset = dig->afmt->offset;
250 0 : const u8 *frame = buffer + 3;
251 :
252 0 : WREG32(HDMI0_AUDIO_INFO0 + offset,
253 : frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
254 0 : WREG32(HDMI0_AUDIO_INFO1 + offset,
255 : frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
256 0 : }
257 :
258 : /*
259 : * test if audio buffer is filled enough to start playing
260 : */
261 0 : static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
262 : {
263 0 : struct drm_device *dev = encoder->dev;
264 0 : struct radeon_device *rdev = dev->dev_private;
265 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
266 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
267 0 : uint32_t offset = dig->afmt->offset;
268 :
269 0 : return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
270 : }
271 :
272 : /*
273 : * have buffer status changed since last call?
274 : */
275 0 : int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
276 : {
277 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
278 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
279 : int status, result;
280 :
281 0 : if (!dig->afmt || !dig->afmt->enabled)
282 0 : return 0;
283 :
284 0 : status = r600_hdmi_is_audio_buffer_filled(encoder);
285 0 : result = dig->afmt->last_buffer_filled_status != status;
286 0 : dig->afmt->last_buffer_filled_status = status;
287 :
288 0 : return result;
289 0 : }
290 :
291 : /*
292 : * write the audio workaround status to the hardware
293 : */
294 0 : void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
295 : {
296 0 : struct drm_device *dev = encoder->dev;
297 0 : struct radeon_device *rdev = dev->dev_private;
298 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
299 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
300 0 : uint32_t offset = dig->afmt->offset;
301 : bool hdmi_audio_workaround = false; /* FIXME */
302 : u32 value;
303 :
304 0 : if (!hdmi_audio_workaround ||
305 0 : r600_hdmi_is_audio_buffer_filled(encoder))
306 0 : value = 0; /* disable workaround */
307 : else
308 : value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
309 0 : WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
310 : value, ~HDMI0_AUDIO_TEST_EN);
311 0 : }
312 :
313 0 : void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
314 : struct radeon_crtc *crtc, unsigned int clock)
315 : {
316 : struct radeon_encoder *radeon_encoder;
317 : struct radeon_encoder_atom_dig *dig;
318 :
319 0 : if (!crtc)
320 0 : return;
321 :
322 0 : radeon_encoder = to_radeon_encoder(crtc->encoder);
323 0 : dig = radeon_encoder->enc_priv;
324 :
325 0 : if (!dig)
326 0 : return;
327 :
328 0 : if (dig->dig_encoder == 0) {
329 0 : WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
330 0 : WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
331 0 : WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
332 0 : } else {
333 0 : WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
334 0 : WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
335 0 : WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
336 : }
337 0 : }
338 :
339 0 : void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
340 : {
341 0 : struct drm_device *dev = encoder->dev;
342 0 : struct radeon_device *rdev = dev->dev_private;
343 :
344 0 : WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
345 : HDMI0_NULL_SEND | /* send null packets when required */
346 : HDMI0_GC_SEND | /* send general control packets */
347 : HDMI0_GC_CONT); /* send general control packets every frame */
348 0 : }
349 :
350 0 : void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)
351 : {
352 0 : struct drm_device *dev = encoder->dev;
353 0 : struct radeon_device *rdev = dev->dev_private;
354 :
355 0 : WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
356 : HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
357 : HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
358 : HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
359 : HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
360 : ~(HDMI0_AUDIO_SAMPLE_SEND |
361 : HDMI0_AUDIO_DELAY_EN_MASK |
362 : HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
363 : HDMI0_60958_CS_UPDATE));
364 :
365 0 : WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
366 : HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
367 : HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
368 :
369 0 : WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
370 : HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
371 : ~HDMI0_AUDIO_INFO_LINE_MASK);
372 :
373 0 : WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
374 : ~(HDMI0_GENERIC0_SEND |
375 : HDMI0_GENERIC0_CONT |
376 : HDMI0_GENERIC0_UPDATE |
377 : HDMI0_GENERIC1_SEND |
378 : HDMI0_GENERIC1_CONT |
379 : HDMI0_GENERIC0_LINE_MASK |
380 : HDMI0_GENERIC1_LINE_MASK));
381 :
382 0 : WREG32_P(HDMI0_60958_0 + offset,
383 : HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
384 : ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
385 : HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
386 :
387 0 : WREG32_P(HDMI0_60958_1 + offset,
388 : HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
389 : ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
390 0 : }
391 :
392 0 : void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
393 : {
394 0 : struct drm_device *dev = encoder->dev;
395 0 : struct radeon_device *rdev = dev->dev_private;
396 :
397 0 : if (mute)
398 0 : WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
399 : else
400 0 : WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
401 0 : }
402 :
403 : /**
404 : * r600_hdmi_update_audio_settings - Update audio infoframe
405 : *
406 : * @encoder: drm encoder
407 : *
408 : * Gets info about current audio stream and updates audio infoframe.
409 : */
410 0 : void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
411 : {
412 0 : struct drm_device *dev = encoder->dev;
413 0 : struct radeon_device *rdev = dev->dev_private;
414 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
415 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
416 0 : struct r600_audio_pin audio = r600_audio_status(rdev);
417 0 : uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
418 0 : struct hdmi_audio_infoframe frame;
419 : uint32_t offset;
420 : uint32_t value;
421 : ssize_t err;
422 :
423 0 : if (!dig->afmt || !dig->afmt->enabled)
424 0 : return;
425 0 : offset = dig->afmt->offset;
426 :
427 : DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
428 : r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
429 : audio.channels, audio.rate, audio.bits_per_sample);
430 : DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
431 : (int)audio.status_bits, (int)audio.category_code);
432 :
433 0 : err = hdmi_audio_infoframe_init(&frame);
434 0 : if (err < 0) {
435 0 : DRM_ERROR("failed to setup audio infoframe\n");
436 0 : return;
437 : }
438 :
439 0 : frame.channels = audio.channels;
440 :
441 0 : err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
442 0 : if (err < 0) {
443 0 : DRM_ERROR("failed to pack audio infoframe\n");
444 0 : return;
445 : }
446 :
447 0 : value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
448 0 : if (value & HDMI0_AUDIO_TEST_EN)
449 0 : WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
450 : value & ~HDMI0_AUDIO_TEST_EN);
451 :
452 0 : WREG32_OR(HDMI0_CONTROL + offset,
453 : HDMI0_ERROR_ACK);
454 :
455 0 : WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
456 : ~HDMI0_AUDIO_INFO_SOURCE);
457 :
458 0 : r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
459 :
460 0 : WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
461 : HDMI0_AUDIO_INFO_CONT |
462 : HDMI0_AUDIO_INFO_UPDATE);
463 0 : }
464 :
465 : /*
466 : * enable the HDMI engine
467 : */
468 0 : void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
469 : {
470 0 : struct drm_device *dev = encoder->dev;
471 0 : struct radeon_device *rdev = dev->dev_private;
472 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
473 0 : struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
474 : u32 hdmi = HDMI0_ERROR_ACK;
475 :
476 0 : if (!dig || !dig->afmt)
477 0 : return;
478 :
479 : /* Older chipsets require setting HDMI and routing manually */
480 0 : if (!ASIC_IS_DCE3(rdev)) {
481 0 : if (enable)
482 0 : hdmi |= HDMI0_ENABLE;
483 0 : switch (radeon_encoder->encoder_id) {
484 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
485 0 : if (enable) {
486 0 : WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
487 : hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
488 0 : } else {
489 0 : WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
490 : }
491 : break;
492 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
493 0 : if (enable) {
494 0 : WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
495 0 : hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
496 0 : } else {
497 0 : WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
498 : }
499 : break;
500 : case ENCODER_OBJECT_ID_INTERNAL_DDI:
501 0 : if (enable) {
502 0 : WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
503 0 : hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
504 0 : } else {
505 0 : WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
506 : }
507 : break;
508 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
509 0 : if (enable)
510 0 : hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
511 : break;
512 : default:
513 0 : dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
514 : radeon_encoder->encoder_id);
515 0 : break;
516 : }
517 0 : WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
518 0 : }
519 :
520 0 : if (rdev->irq.installed) {
521 : /* if irq is available use it */
522 : /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
523 0 : if (enable)
524 0 : radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
525 : else
526 0 : radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
527 : }
528 :
529 0 : dig->afmt->enabled = enable;
530 :
531 : DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
532 : enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
533 0 : }
534 :
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