Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #ifndef __RADEON_H__
29 : #define __RADEON_H__
30 :
31 : /* TODO: Here are things that needs to be done :
32 : * - surface allocator & initializer : (bit like scratch reg) should
33 : * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 : * related to surface
35 : * - WB : write back stuff (do it bit like scratch reg things)
36 : * - Vblank : look at Jesse's rework and what we should do
37 : * - r600/r700: gart & cp
38 : * - cs : clean cs ioctl use bitmap & things like that.
39 : * - power management stuff
40 : * - Barrier in gart code
41 : * - Unmappabled vram ?
42 : * - TESTING, TESTING, TESTING
43 : */
44 :
45 : /* Initialization path:
46 : * We expect that acceleration initialization might fail for various
47 : * reasons even thought we work hard to make it works on most
48 : * configurations. In order to still have a working userspace in such
49 : * situation the init path must succeed up to the memory controller
50 : * initialization point. Failure before this point are considered as
51 : * fatal error. Here is the init callchain :
52 : * radeon_device_init perform common structure, mutex initialization
53 : * asic_init setup the GPU memory layout and perform all
54 : * one time initialization (failure in this
55 : * function are considered fatal)
56 : * asic_startup setup the GPU acceleration, in order to
57 : * follow guideline the first thing this
58 : * function should do is setting the GPU
59 : * memory controller (only MC setup failure
60 : * are considered as fatal)
61 : */
62 :
63 : #include <dev/pci/drm/drm_linux.h>
64 :
65 : #include <dev/pci/drm/ttm/ttm_bo_api.h>
66 : #include <dev/pci/drm/ttm/ttm_bo_driver.h>
67 : #include <dev/pci/drm/ttm/ttm_placement.h>
68 : #include <dev/pci/drm/ttm/ttm_module.h>
69 : #include <dev/pci/drm/ttm/ttm_execbuf_util.h>
70 :
71 : #include <dev/pci/drm/drmP.h>
72 :
73 : #include <dev/wscons/wsconsio.h>
74 : #include <dev/wscons/wsdisplayvar.h>
75 : #include <dev/rasops/rasops.h>
76 :
77 : #ifdef __sparc64__
78 : #include <machine/fbvar.h>
79 : #endif
80 :
81 : #include "radeon_family.h"
82 : #include "radeon_mode.h"
83 : #include "radeon_reg.h"
84 :
85 : /*
86 : * Modules parameters.
87 : */
88 : extern int radeon_no_wb;
89 : extern int radeon_modeset;
90 : extern int radeon_dynclks;
91 : extern int radeon_r4xx_atom;
92 : extern int radeon_agpmode;
93 : extern int radeon_vram_limit;
94 : extern int radeon_gart_size;
95 : extern int radeon_benchmarking;
96 : extern int radeon_testing;
97 : extern int radeon_connector_table;
98 : extern int radeon_tv;
99 : extern int radeon_audio;
100 : extern int radeon_disp_priority;
101 : extern int radeon_hw_i2c;
102 : extern int radeon_pcie_gen2;
103 : extern int radeon_msi;
104 : extern int radeon_lockup_timeout;
105 : extern int radeon_fastfb;
106 : extern int radeon_dpm;
107 : extern int radeon_aspm;
108 : extern int radeon_runtime_pm;
109 : extern int radeon_hard_reset;
110 : extern int radeon_vm_size;
111 : extern int radeon_vm_block_size;
112 : extern int radeon_deep_color;
113 : extern int radeon_use_pflipirq;
114 : extern int radeon_bapm;
115 : extern int radeon_backlight;
116 : extern int radeon_auxch;
117 : extern int radeon_mst;
118 :
119 : /*
120 : * Copy from radeon_drv.h so we don't have to include both and have conflicting
121 : * symbol;
122 : */
123 : #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
124 : #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
125 : /* RADEON_IB_POOL_SIZE must be a power of 2 */
126 : #define RADEON_IB_POOL_SIZE 16
127 : #define RADEON_DEBUGFS_MAX_COMPONENTS 32
128 : #define RADEONFB_CONN_LIMIT 4
129 : #define RADEON_BIOS_NUM_SCRATCH 8
130 :
131 : /* internal ring indices */
132 : /* r1xx+ has gfx CP ring */
133 : #define RADEON_RING_TYPE_GFX_INDEX 0
134 :
135 : /* cayman has 2 compute CP rings */
136 : #define CAYMAN_RING_TYPE_CP1_INDEX 1
137 : #define CAYMAN_RING_TYPE_CP2_INDEX 2
138 :
139 : /* R600+ has an async dma ring */
140 : #define R600_RING_TYPE_DMA_INDEX 3
141 : /* cayman add a second async dma ring */
142 : #define CAYMAN_RING_TYPE_DMA1_INDEX 4
143 :
144 : /* R600+ */
145 : #define R600_RING_TYPE_UVD_INDEX 5
146 :
147 : /* TN+ */
148 : #define TN_RING_TYPE_VCE1_INDEX 6
149 : #define TN_RING_TYPE_VCE2_INDEX 7
150 :
151 : /* max number of rings */
152 : #define RADEON_NUM_RINGS 8
153 :
154 : /* number of hw syncs before falling back on blocking */
155 : #define RADEON_NUM_SYNCS 4
156 :
157 : /* hardcode those limit for now */
158 : #define RADEON_VA_IB_OFFSET (1 << 20)
159 : #define RADEON_VA_RESERVED_SIZE (8 << 20)
160 : #define RADEON_IB_VM_MAX_SIZE (64 << 10)
161 :
162 : /* hard reset data */
163 : #define RADEON_ASIC_RESET_DATA 0x39d5e86b
164 :
165 : /* reset flags */
166 : #define RADEON_RESET_GFX (1 << 0)
167 : #define RADEON_RESET_COMPUTE (1 << 1)
168 : #define RADEON_RESET_DMA (1 << 2)
169 : #define RADEON_RESET_CP (1 << 3)
170 : #define RADEON_RESET_GRBM (1 << 4)
171 : #define RADEON_RESET_DMA1 (1 << 5)
172 : #define RADEON_RESET_RLC (1 << 6)
173 : #define RADEON_RESET_SEM (1 << 7)
174 : #define RADEON_RESET_IH (1 << 8)
175 : #define RADEON_RESET_VMC (1 << 9)
176 : #define RADEON_RESET_MC (1 << 10)
177 : #define RADEON_RESET_DISPLAY (1 << 11)
178 :
179 : /* CG block flags */
180 : #define RADEON_CG_BLOCK_GFX (1 << 0)
181 : #define RADEON_CG_BLOCK_MC (1 << 1)
182 : #define RADEON_CG_BLOCK_SDMA (1 << 2)
183 : #define RADEON_CG_BLOCK_UVD (1 << 3)
184 : #define RADEON_CG_BLOCK_VCE (1 << 4)
185 : #define RADEON_CG_BLOCK_HDP (1 << 5)
186 : #define RADEON_CG_BLOCK_BIF (1 << 6)
187 :
188 : /* CG flags */
189 : #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
190 : #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
191 : #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
192 : #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
193 : #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
194 : #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
195 : #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
196 : #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
197 : #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
198 : #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
199 : #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
200 : #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
201 : #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
202 : #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
203 : #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
204 : #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
205 : #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
206 :
207 : /* PG flags */
208 : #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
209 : #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
210 : #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
211 : #define RADEON_PG_SUPPORT_UVD (1 << 3)
212 : #define RADEON_PG_SUPPORT_VCE (1 << 4)
213 : #define RADEON_PG_SUPPORT_CP (1 << 5)
214 : #define RADEON_PG_SUPPORT_GDS (1 << 6)
215 : #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
216 : #define RADEON_PG_SUPPORT_SDMA (1 << 8)
217 : #define RADEON_PG_SUPPORT_ACP (1 << 9)
218 : #define RADEON_PG_SUPPORT_SAMU (1 << 10)
219 :
220 : /* max cursor sizes (in pixels) */
221 : #define CURSOR_WIDTH 64
222 : #define CURSOR_HEIGHT 64
223 :
224 : #define CIK_CURSOR_WIDTH 128
225 : #define CIK_CURSOR_HEIGHT 128
226 :
227 : /*
228 : * Errata workarounds.
229 : */
230 : enum radeon_pll_errata {
231 : CHIP_ERRATA_R300_CG = 0x00000001,
232 : CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
233 : CHIP_ERRATA_PLL_DELAY = 0x00000004
234 : };
235 :
236 :
237 : struct radeon_device;
238 :
239 :
240 : /*
241 : * BIOS.
242 : */
243 : bool radeon_get_bios(struct radeon_device *rdev);
244 :
245 : /*
246 : * Dummy page
247 : */
248 : struct radeon_dummy_page {
249 : uint64_t entry;
250 : struct drm_dmamem *dmah;
251 : dma_addr_t addr;
252 : };
253 : int radeon_dummy_page_init(struct radeon_device *rdev);
254 : void radeon_dummy_page_fini(struct radeon_device *rdev);
255 :
256 :
257 : /*
258 : * Clocks
259 : */
260 : struct radeon_clock {
261 : struct radeon_pll p1pll;
262 : struct radeon_pll p2pll;
263 : struct radeon_pll dcpll;
264 : struct radeon_pll spll;
265 : struct radeon_pll mpll;
266 : /* 10 Khz units */
267 : uint32_t default_mclk;
268 : uint32_t default_sclk;
269 : uint32_t default_dispclk;
270 : uint32_t current_dispclk;
271 : uint32_t dp_extclk;
272 : uint32_t max_pixel_clock;
273 : uint32_t vco_freq;
274 : };
275 :
276 : /*
277 : * Power management
278 : */
279 : int radeon_pm_init(struct radeon_device *rdev);
280 : int radeon_pm_late_init(struct radeon_device *rdev);
281 : void radeon_pm_fini(struct radeon_device *rdev);
282 : void radeon_pm_compute_clocks(struct radeon_device *rdev);
283 : void radeon_pm_suspend(struct radeon_device *rdev);
284 : void radeon_pm_resume(struct radeon_device *rdev);
285 : void radeon_combios_get_power_modes(struct radeon_device *rdev);
286 : void radeon_atombios_get_power_modes(struct radeon_device *rdev);
287 : int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
288 : u8 clock_type,
289 : u32 clock,
290 : bool strobe_mode,
291 : struct atom_clock_dividers *dividers);
292 : int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
293 : u32 clock,
294 : bool strobe_mode,
295 : struct atom_mpll_param *mpll_param);
296 : void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
297 : int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
298 : u16 voltage_level, u8 voltage_type,
299 : u32 *gpio_value, u32 *gpio_mask);
300 : void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
301 : u32 eng_clock, u32 mem_clock);
302 : int radeon_atom_get_voltage_step(struct radeon_device *rdev,
303 : u8 voltage_type, u16 *voltage_step);
304 : int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
305 : u16 voltage_id, u16 *voltage);
306 : int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
307 : u16 *voltage,
308 : u16 leakage_idx);
309 : int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
310 : u16 *leakage_id);
311 : int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
312 : u16 *vddc, u16 *vddci,
313 : u16 virtual_voltage_id,
314 : u16 vbios_voltage_id);
315 : int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
316 : u16 virtual_voltage_id,
317 : u16 *voltage);
318 : int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
319 : u8 voltage_type,
320 : u16 nominal_voltage,
321 : u16 *true_voltage);
322 : int radeon_atom_get_min_voltage(struct radeon_device *rdev,
323 : u8 voltage_type, u16 *min_voltage);
324 : int radeon_atom_get_max_voltage(struct radeon_device *rdev,
325 : u8 voltage_type, u16 *max_voltage);
326 : int radeon_atom_get_voltage_table(struct radeon_device *rdev,
327 : u8 voltage_type, u8 voltage_mode,
328 : struct atom_voltage_table *voltage_table);
329 : bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
330 : u8 voltage_type, u8 voltage_mode);
331 : int radeon_atom_get_svi2_info(struct radeon_device *rdev,
332 : u8 voltage_type,
333 : u8 *svd_gpio_id, u8 *svc_gpio_id);
334 : void radeon_atom_update_memory_dll(struct radeon_device *rdev,
335 : u32 mem_clock);
336 : void radeon_atom_set_ac_timing(struct radeon_device *rdev,
337 : u32 mem_clock);
338 : int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
339 : u8 module_index,
340 : struct atom_mc_reg_table *reg_table);
341 : int radeon_atom_get_memory_info(struct radeon_device *rdev,
342 : u8 module_index, struct atom_memory_info *mem_info);
343 : int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
344 : bool gddr5, u8 module_index,
345 : struct atom_memory_clock_range_table *mclk_range_table);
346 : int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
347 : u16 voltage_id, u16 *voltage);
348 : void rs690_pm_info(struct radeon_device *rdev);
349 : extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
350 : unsigned *bankh, unsigned *mtaspect,
351 : unsigned *tile_split);
352 :
353 : /*
354 : * Fences.
355 : */
356 : struct radeon_fence_driver {
357 : struct radeon_device *rdev;
358 : uint32_t scratch_reg;
359 : uint64_t gpu_addr;
360 : volatile uint32_t *cpu_addr;
361 : /* sync_seq is protected by ring emission lock */
362 : uint64_t sync_seq[RADEON_NUM_RINGS];
363 : atomic64_t last_seq;
364 : bool initialized, delayed_irq;
365 : struct delayed_work lockup_work;
366 : };
367 :
368 : struct radeon_fence {
369 : struct fence base;
370 :
371 : struct radeon_device *rdev;
372 : uint64_t seq;
373 : /* RB, DMA, etc. */
374 : unsigned ring;
375 : bool is_vm_update;
376 :
377 : wait_queue_t fence_wake;
378 : };
379 :
380 : int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
381 : int radeon_fence_driver_init(struct radeon_device *rdev);
382 : void radeon_fence_driver_fini(struct radeon_device *rdev);
383 : void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
384 : int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
385 : void radeon_fence_process(struct radeon_device *rdev, int ring);
386 : bool radeon_fence_signaled(struct radeon_fence *fence);
387 : int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
388 : int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
389 : int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
390 : int radeon_fence_wait_any(struct radeon_device *rdev,
391 : struct radeon_fence **fences,
392 : bool intr);
393 : struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
394 : void radeon_fence_unref(struct radeon_fence **fence);
395 : unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
396 : bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
397 : void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
398 0 : static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
399 : struct radeon_fence *b)
400 : {
401 0 : if (!a) {
402 0 : return b;
403 : }
404 :
405 0 : if (!b) {
406 0 : return a;
407 : }
408 :
409 0 : BUG_ON(a->ring != b->ring);
410 :
411 0 : if (a->seq > b->seq) {
412 0 : return a;
413 : } else {
414 0 : return b;
415 : }
416 0 : }
417 :
418 0 : static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
419 : struct radeon_fence *b)
420 : {
421 0 : if (!a) {
422 0 : return false;
423 : }
424 :
425 0 : if (!b) {
426 0 : return true;
427 : }
428 :
429 0 : BUG_ON(a->ring != b->ring);
430 :
431 0 : return a->seq < b->seq;
432 0 : }
433 :
434 : /*
435 : * Tiling registers
436 : */
437 : struct radeon_surface_reg {
438 : struct radeon_bo *bo;
439 : };
440 :
441 : #define RADEON_GEM_MAX_SURFACES 8
442 :
443 : /*
444 : * TTM.
445 : */
446 : struct radeon_mman {
447 : struct ttm_bo_global_ref bo_global_ref;
448 : struct drm_global_reference mem_global_ref;
449 : struct ttm_bo_device bdev;
450 : bool mem_global_referenced;
451 : bool initialized;
452 :
453 : #if defined(CONFIG_DEBUG_FS)
454 : struct dentry *vram;
455 : struct dentry *gtt;
456 : #endif
457 : };
458 :
459 : struct radeon_bo_list {
460 : struct radeon_bo *robj;
461 : struct ttm_validate_buffer tv;
462 : uint64_t gpu_offset;
463 : unsigned prefered_domains;
464 : unsigned allowed_domains;
465 : uint32_t tiling_flags;
466 : };
467 :
468 : /* bo virtual address in a specific vm */
469 : struct radeon_bo_va {
470 : /* protected by bo being reserved */
471 : struct list_head bo_list;
472 : uint32_t flags;
473 : struct radeon_fence *last_pt_update;
474 : unsigned ref_count;
475 :
476 : /* protected by vm mutex */
477 : struct interval_tree_node it;
478 : struct list_head vm_status;
479 :
480 : /* constant after initialization */
481 : struct radeon_vm *vm;
482 : struct radeon_bo *bo;
483 : };
484 :
485 : struct radeon_bo {
486 : /* Protected by gem.mutex */
487 : struct list_head list;
488 : /* Protected by tbo.reserved */
489 : u32 initial_domain;
490 : struct ttm_place placements[4];
491 : struct ttm_placement placement;
492 : struct ttm_buffer_object tbo;
493 : struct ttm_bo_kmap_obj kmap;
494 : u32 flags;
495 : unsigned pin_count;
496 : void *kptr;
497 : u32 tiling_flags;
498 : u32 pitch;
499 : int surface_reg;
500 : /* list of all virtual address to which this bo
501 : * is associated to
502 : */
503 : struct list_head va;
504 : /* Constant after initialization */
505 : struct radeon_device *rdev;
506 : struct drm_gem_object gem_base;
507 :
508 : struct ttm_bo_kmap_obj dma_buf_vmap;
509 : pid_t pid;
510 :
511 : struct radeon_mn *mn;
512 : struct list_head mn_list;
513 : };
514 : #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
515 :
516 : int radeon_gem_debugfs_init(struct radeon_device *rdev);
517 :
518 : /* sub-allocation manager, it has to be protected by another lock.
519 : * By conception this is an helper for other part of the driver
520 : * like the indirect buffer or semaphore, which both have their
521 : * locking.
522 : *
523 : * Principe is simple, we keep a list of sub allocation in offset
524 : * order (first entry has offset == 0, last entry has the highest
525 : * offset).
526 : *
527 : * When allocating new object we first check if there is room at
528 : * the end total_size - (last_object_offset + last_object_size) >=
529 : * alloc_size. If so we allocate new object there.
530 : *
531 : * When there is not enough room at the end, we start waiting for
532 : * each sub object until we reach object_offset+object_size >=
533 : * alloc_size, this object then become the sub object we return.
534 : *
535 : * Alignment can't be bigger than page size.
536 : *
537 : * Hole are not considered for allocation to keep things simple.
538 : * Assumption is that there won't be hole (all object on same
539 : * alignment).
540 : */
541 : struct radeon_sa_manager {
542 : wait_queue_head_t wq;
543 : struct radeon_bo *bo;
544 : struct list_head *hole;
545 : struct list_head flist[RADEON_NUM_RINGS];
546 : struct list_head olist;
547 : unsigned size;
548 : uint64_t gpu_addr;
549 : void *cpu_ptr;
550 : uint32_t domain;
551 : uint32_t align;
552 : };
553 :
554 : struct radeon_sa_bo;
555 :
556 : /* sub-allocation buffer */
557 : struct radeon_sa_bo {
558 : struct list_head olist;
559 : struct list_head flist;
560 : struct radeon_sa_manager *manager;
561 : unsigned soffset;
562 : unsigned eoffset;
563 : struct radeon_fence *fence;
564 : };
565 :
566 : /*
567 : * GEM objects.
568 : */
569 : struct radeon_gem {
570 : struct rwlock mutex;
571 : struct list_head objects;
572 : };
573 :
574 : int radeon_gem_init(struct radeon_device *rdev);
575 : void radeon_gem_fini(struct radeon_device *rdev);
576 : int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
577 : int alignment, int initial_domain,
578 : u32 flags, bool kernel,
579 : struct drm_gem_object **obj);
580 :
581 : int radeon_mode_dumb_create(struct drm_file *file_priv,
582 : struct drm_device *dev,
583 : struct drm_mode_create_dumb *args);
584 : int radeon_mode_dumb_mmap(struct drm_file *filp,
585 : struct drm_device *dev,
586 : uint32_t handle, uint64_t *offset_p);
587 :
588 : /*
589 : * Semaphores.
590 : */
591 : struct radeon_semaphore {
592 : struct radeon_sa_bo *sa_bo;
593 : signed waiters;
594 : uint64_t gpu_addr;
595 : };
596 :
597 : int radeon_semaphore_create(struct radeon_device *rdev,
598 : struct radeon_semaphore **semaphore);
599 : bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
600 : struct radeon_semaphore *semaphore);
601 : bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
602 : struct radeon_semaphore *semaphore);
603 : void radeon_semaphore_free(struct radeon_device *rdev,
604 : struct radeon_semaphore **semaphore,
605 : struct radeon_fence *fence);
606 :
607 : /*
608 : * Synchronization
609 : */
610 : struct radeon_sync {
611 : struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
612 : struct radeon_fence *sync_to[RADEON_NUM_RINGS];
613 : struct radeon_fence *last_vm_update;
614 : };
615 :
616 : void radeon_sync_create(struct radeon_sync *sync);
617 : void radeon_sync_fence(struct radeon_sync *sync,
618 : struct radeon_fence *fence);
619 : int radeon_sync_resv(struct radeon_device *rdev,
620 : struct radeon_sync *sync,
621 : struct reservation_object *resv,
622 : bool shared);
623 : int radeon_sync_rings(struct radeon_device *rdev,
624 : struct radeon_sync *sync,
625 : int waiting_ring);
626 : void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
627 : struct radeon_fence *fence);
628 :
629 : /*
630 : * GART structures, functions & helpers
631 : */
632 : struct radeon_mc;
633 :
634 : #define RADEON_GPU_PAGE_SIZE 4096
635 : #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
636 : #define RADEON_GPU_PAGE_SHIFT 12
637 : #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
638 :
639 : #define RADEON_GART_PAGE_DUMMY 0
640 : #define RADEON_GART_PAGE_VALID (1 << 0)
641 : #define RADEON_GART_PAGE_READ (1 << 1)
642 : #define RADEON_GART_PAGE_WRITE (1 << 2)
643 : #define RADEON_GART_PAGE_SNOOP (1 << 3)
644 :
645 : struct radeon_gart {
646 : dma_addr_t table_addr;
647 : struct drm_dmamem *dmah;
648 : struct radeon_bo *robj;
649 : void *ptr;
650 : unsigned num_gpu_pages;
651 : unsigned num_cpu_pages;
652 : unsigned table_size;
653 : struct vm_page **pages;
654 : uint64_t *pages_entry;
655 : bool ready;
656 : };
657 :
658 : int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
659 : void radeon_gart_table_ram_free(struct radeon_device *rdev);
660 : int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
661 : void radeon_gart_table_vram_free(struct radeon_device *rdev);
662 : int radeon_gart_table_vram_pin(struct radeon_device *rdev);
663 : void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
664 : int radeon_gart_init(struct radeon_device *rdev);
665 : void radeon_gart_fini(struct radeon_device *rdev);
666 : void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
667 : int pages);
668 : int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
669 : int pages, struct vm_page **pagelist,
670 : dma_addr_t *dma_addr, uint32_t flags);
671 :
672 :
673 : /*
674 : * GPU MC structures, functions & helpers
675 : */
676 : struct radeon_mc {
677 : resource_size_t aper_size;
678 : resource_size_t aper_base;
679 : resource_size_t agp_base;
680 : /* for some chips with <= 32MB we need to lie
681 : * about vram size near mc fb location */
682 : u64 mc_vram_size;
683 : u64 visible_vram_size;
684 : u64 gtt_size;
685 : u64 gtt_start;
686 : u64 gtt_end;
687 : u64 vram_start;
688 : u64 vram_end;
689 : unsigned vram_width;
690 : u64 real_vram_size;
691 : int vram_mtrr;
692 : bool vram_is_ddr;
693 : bool igp_sideport_enabled;
694 : u64 gtt_base_align;
695 : u64 mc_mask;
696 : };
697 :
698 : bool radeon_combios_sideport_present(struct radeon_device *rdev);
699 : bool radeon_atombios_sideport_present(struct radeon_device *rdev);
700 :
701 : /*
702 : * GPU scratch registers structures, functions & helpers
703 : */
704 : struct radeon_scratch {
705 : unsigned num_reg;
706 : uint32_t reg_base;
707 : bool free[32];
708 : uint32_t reg[32];
709 : };
710 :
711 : int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
712 : void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
713 :
714 : /*
715 : * GPU doorbell structures, functions & helpers
716 : */
717 : #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
718 :
719 : struct radeon_doorbell {
720 : /* doorbell mmio */
721 : resource_size_t base;
722 : resource_size_t size;
723 : bus_space_handle_t bsh;
724 : u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
725 : DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
726 : };
727 :
728 : int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
729 : void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
730 : void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
731 : phys_addr_t *aperture_base,
732 : size_t *aperture_size,
733 : size_t *start_offset);
734 :
735 : /*
736 : * IRQS.
737 : */
738 :
739 : struct radeon_flip_work {
740 : struct work_struct flip_work;
741 : struct work_struct unpin_work;
742 : struct radeon_device *rdev;
743 : int crtc_id;
744 : uint64_t base;
745 : struct drm_pending_vblank_event *event;
746 : struct radeon_bo *old_rbo;
747 : struct fence *fence;
748 : };
749 :
750 : struct r500_irq_stat_regs {
751 : u32 disp_int;
752 : u32 hdmi0_status;
753 : };
754 :
755 : struct r600_irq_stat_regs {
756 : u32 disp_int;
757 : u32 disp_int_cont;
758 : u32 disp_int_cont2;
759 : u32 d1grph_int;
760 : u32 d2grph_int;
761 : u32 hdmi0_status;
762 : u32 hdmi1_status;
763 : };
764 :
765 : struct evergreen_irq_stat_regs {
766 : u32 disp_int;
767 : u32 disp_int_cont;
768 : u32 disp_int_cont2;
769 : u32 disp_int_cont3;
770 : u32 disp_int_cont4;
771 : u32 disp_int_cont5;
772 : u32 d1grph_int;
773 : u32 d2grph_int;
774 : u32 d3grph_int;
775 : u32 d4grph_int;
776 : u32 d5grph_int;
777 : u32 d6grph_int;
778 : u32 afmt_status1;
779 : u32 afmt_status2;
780 : u32 afmt_status3;
781 : u32 afmt_status4;
782 : u32 afmt_status5;
783 : u32 afmt_status6;
784 : };
785 :
786 : struct cik_irq_stat_regs {
787 : u32 disp_int;
788 : u32 disp_int_cont;
789 : u32 disp_int_cont2;
790 : u32 disp_int_cont3;
791 : u32 disp_int_cont4;
792 : u32 disp_int_cont5;
793 : u32 disp_int_cont6;
794 : u32 d1grph_int;
795 : u32 d2grph_int;
796 : u32 d3grph_int;
797 : u32 d4grph_int;
798 : u32 d5grph_int;
799 : u32 d6grph_int;
800 : };
801 :
802 : union radeon_irq_stat_regs {
803 : struct r500_irq_stat_regs r500;
804 : struct r600_irq_stat_regs r600;
805 : struct evergreen_irq_stat_regs evergreen;
806 : struct cik_irq_stat_regs cik;
807 : };
808 :
809 : struct radeon_irq {
810 : bool installed;
811 : spinlock_t lock;
812 : atomic_t ring_int[RADEON_NUM_RINGS];
813 : bool crtc_vblank_int[RADEON_MAX_CRTCS];
814 : atomic_t pflip[RADEON_MAX_CRTCS];
815 : wait_queue_head_t vblank_queue;
816 : bool hpd[RADEON_MAX_HPD_PINS];
817 : bool afmt[RADEON_MAX_AFMT_BLOCKS];
818 : union radeon_irq_stat_regs stat_regs;
819 : bool dpm_thermal;
820 : };
821 :
822 : int radeon_irq_kms_init(struct radeon_device *rdev);
823 : void radeon_irq_kms_fini(struct radeon_device *rdev);
824 : void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
825 : bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
826 : void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
827 : void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
828 : void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
829 : void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
830 : void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
831 : void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
832 : void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
833 :
834 : /*
835 : * CP & rings.
836 : */
837 :
838 : struct radeon_ib {
839 : struct radeon_sa_bo *sa_bo;
840 : uint32_t length_dw;
841 : uint64_t gpu_addr;
842 : uint32_t *ptr;
843 : int ring;
844 : struct radeon_fence *fence;
845 : struct radeon_vm *vm;
846 : bool is_const_ib;
847 : struct radeon_sync sync;
848 : };
849 :
850 : struct radeon_ring {
851 : struct radeon_bo *ring_obj;
852 : volatile uint32_t *ring;
853 : unsigned rptr_offs;
854 : unsigned rptr_save_reg;
855 : u64 next_rptr_gpu_addr;
856 : volatile u32 *next_rptr_cpu_addr;
857 : unsigned wptr;
858 : unsigned wptr_old;
859 : unsigned ring_size;
860 : unsigned ring_free_dw;
861 : int count_dw;
862 : atomic_t last_rptr;
863 : atomic64_t last_activity;
864 : uint64_t gpu_addr;
865 : uint32_t align_mask;
866 : uint32_t ptr_mask;
867 : bool ready;
868 : u32 nop;
869 : u32 idx;
870 : u64 last_semaphore_signal_addr;
871 : u64 last_semaphore_wait_addr;
872 : /* for CIK queues */
873 : u32 me;
874 : u32 pipe;
875 : u32 queue;
876 : struct radeon_bo *mqd_obj;
877 : u32 doorbell_index;
878 : unsigned wptr_offs;
879 : };
880 :
881 : struct radeon_mec {
882 : struct radeon_bo *hpd_eop_obj;
883 : u64 hpd_eop_gpu_addr;
884 : u32 num_pipe;
885 : u32 num_mec;
886 : u32 num_queue;
887 : };
888 :
889 : /*
890 : * VM
891 : */
892 :
893 : /* maximum number of VMIDs */
894 : #define RADEON_NUM_VM 16
895 :
896 : /* number of entries in page table */
897 : #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
898 :
899 : /* PTBs (Page Table Blocks) need to be aligned to 32K */
900 : #define RADEON_VM_PTB_ALIGN_SIZE 32768
901 : #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
902 : #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
903 :
904 : #define R600_PTE_VALID (1 << 0)
905 : #define R600_PTE_SYSTEM (1 << 1)
906 : #define R600_PTE_SNOOPED (1 << 2)
907 : #define R600_PTE_READABLE (1 << 5)
908 : #define R600_PTE_WRITEABLE (1 << 6)
909 :
910 : /* PTE (Page Table Entry) fragment field for different page sizes */
911 : #define R600_PTE_FRAG_4KB (0 << 7)
912 : #define R600_PTE_FRAG_64KB (4 << 7)
913 : #define R600_PTE_FRAG_256KB (6 << 7)
914 :
915 : /* flags needed to be set so we can copy directly from the GART table */
916 : #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
917 : R600_PTE_SYSTEM | R600_PTE_VALID )
918 :
919 : struct radeon_vm_pt {
920 : struct radeon_bo *bo;
921 : uint64_t addr;
922 : };
923 :
924 : struct radeon_vm_id {
925 : unsigned id;
926 : uint64_t pd_gpu_addr;
927 : /* last flushed PD/PT update */
928 : struct radeon_fence *flushed_updates;
929 : /* last use of vmid */
930 : struct radeon_fence *last_id_use;
931 : };
932 :
933 : struct radeon_vm {
934 : struct rwlock mutex;
935 :
936 : struct rb_root va;
937 :
938 : /* protecting invalidated and freed */
939 : spinlock_t status_lock;
940 :
941 : /* BOs moved, but not yet updated in the PT */
942 : struct list_head invalidated;
943 :
944 : /* BOs freed, but not yet updated in the PT */
945 : struct list_head freed;
946 :
947 : /* BOs cleared in the PT */
948 : struct list_head cleared;
949 :
950 : /* contains the page directory */
951 : struct radeon_bo *page_directory;
952 : unsigned max_pde_used;
953 :
954 : /* array of page tables, one for each page directory entry */
955 : struct radeon_vm_pt *page_tables;
956 :
957 : struct radeon_bo_va *ib_bo_va;
958 :
959 : /* for id and flush management per ring */
960 : struct radeon_vm_id ids[RADEON_NUM_RINGS];
961 : };
962 :
963 : struct radeon_vm_manager {
964 : struct radeon_fence *active[RADEON_NUM_VM];
965 : uint32_t max_pfn;
966 : /* number of VMIDs */
967 : unsigned nvm;
968 : /* vram base address for page table entry */
969 : u64 vram_base_offset;
970 : /* is vm enabled? */
971 : bool enabled;
972 : /* for hw to save the PD addr on suspend/resume */
973 : uint32_t saved_table_addr[RADEON_NUM_VM];
974 : };
975 :
976 : /*
977 : * file private structure
978 : */
979 : struct radeon_fpriv {
980 : struct radeon_vm vm;
981 : };
982 :
983 : /*
984 : * R6xx+ IH ring
985 : */
986 : struct r600_ih {
987 : struct radeon_bo *ring_obj;
988 : volatile uint32_t *ring;
989 : unsigned rptr;
990 : unsigned ring_size;
991 : uint64_t gpu_addr;
992 : uint32_t ptr_mask;
993 : atomic_t lock;
994 : bool enabled;
995 : };
996 :
997 : /*
998 : * RLC stuff
999 : */
1000 : #include "clearstate_defs.h"
1001 :
1002 : struct radeon_rlc {
1003 : /* for power gating */
1004 : struct radeon_bo *save_restore_obj;
1005 : uint64_t save_restore_gpu_addr;
1006 : volatile uint32_t *sr_ptr;
1007 : const u32 *reg_list;
1008 : u32 reg_list_size;
1009 : /* for clear state */
1010 : struct radeon_bo *clear_state_obj;
1011 : uint64_t clear_state_gpu_addr;
1012 : volatile uint32_t *cs_ptr;
1013 : const struct cs_section_def *cs_data;
1014 : u32 clear_state_size;
1015 : /* for cp tables */
1016 : struct radeon_bo *cp_table_obj;
1017 : uint64_t cp_table_gpu_addr;
1018 : volatile uint32_t *cp_table_ptr;
1019 : u32 cp_table_size;
1020 : };
1021 :
1022 : int radeon_ib_get(struct radeon_device *rdev, int ring,
1023 : struct radeon_ib *ib, struct radeon_vm *vm,
1024 : unsigned size);
1025 : void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1026 : int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1027 : struct radeon_ib *const_ib, bool hdp_flush);
1028 : int radeon_ib_pool_init(struct radeon_device *rdev);
1029 : void radeon_ib_pool_fini(struct radeon_device *rdev);
1030 : int radeon_ib_ring_tests(struct radeon_device *rdev);
1031 : /* Ring access between begin & end cannot sleep */
1032 : bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1033 : struct radeon_ring *ring);
1034 : void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1035 : int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1036 : int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1037 : void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1038 : bool hdp_flush);
1039 : void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1040 : bool hdp_flush);
1041 : void radeon_ring_undo(struct radeon_ring *ring);
1042 : void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1043 : int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1044 : void radeon_ring_lockup_update(struct radeon_device *rdev,
1045 : struct radeon_ring *ring);
1046 : bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1047 : unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1048 : uint32_t **data);
1049 : int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1050 : unsigned size, uint32_t *data);
1051 : int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1052 : unsigned rptr_offs, u32 nop);
1053 : void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1054 :
1055 :
1056 : /* r600 async dma */
1057 : void r600_dma_stop(struct radeon_device *rdev);
1058 : int r600_dma_resume(struct radeon_device *rdev);
1059 : void r600_dma_fini(struct radeon_device *rdev);
1060 :
1061 : void cayman_dma_stop(struct radeon_device *rdev);
1062 : int cayman_dma_resume(struct radeon_device *rdev);
1063 : void cayman_dma_fini(struct radeon_device *rdev);
1064 :
1065 : /*
1066 : * CS.
1067 : */
1068 : struct radeon_cs_chunk {
1069 : uint32_t length_dw;
1070 : uint32_t *kdata;
1071 : void __user *user_ptr;
1072 : };
1073 :
1074 : struct radeon_cs_parser {
1075 : struct device *dev;
1076 : struct radeon_device *rdev;
1077 : struct drm_file *filp;
1078 : /* chunks */
1079 : unsigned nchunks;
1080 : struct radeon_cs_chunk *chunks;
1081 : uint64_t *chunks_array;
1082 : /* IB */
1083 : unsigned idx;
1084 : /* relocations */
1085 : unsigned nrelocs;
1086 : struct radeon_bo_list *relocs;
1087 : struct radeon_bo_list *vm_bos;
1088 : struct list_head validated;
1089 : unsigned dma_reloc_idx;
1090 : /* indices of various chunks */
1091 : struct radeon_cs_chunk *chunk_ib;
1092 : struct radeon_cs_chunk *chunk_relocs;
1093 : struct radeon_cs_chunk *chunk_flags;
1094 : struct radeon_cs_chunk *chunk_const_ib;
1095 : struct radeon_ib ib;
1096 : struct radeon_ib const_ib;
1097 : void *track;
1098 : unsigned family;
1099 : int parser_error;
1100 : u32 cs_flags;
1101 : u32 ring;
1102 : s32 priority;
1103 : struct ww_acquire_ctx ticket;
1104 : };
1105 :
1106 0 : static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1107 : {
1108 0 : struct radeon_cs_chunk *ibc = p->chunk_ib;
1109 :
1110 0 : if (ibc->kdata)
1111 0 : return ibc->kdata[idx];
1112 0 : return p->ib.ptr[idx];
1113 0 : }
1114 :
1115 :
1116 : struct radeon_cs_packet {
1117 : unsigned idx;
1118 : unsigned type;
1119 : unsigned reg;
1120 : unsigned opcode;
1121 : int count;
1122 : unsigned one_reg_wr;
1123 : };
1124 :
1125 : typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1126 : struct radeon_cs_packet *pkt,
1127 : unsigned idx, unsigned reg);
1128 : typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1129 : struct radeon_cs_packet *pkt);
1130 :
1131 :
1132 : /*
1133 : * AGP
1134 : */
1135 : int radeon_agp_init(struct radeon_device *rdev);
1136 : void radeon_agp_resume(struct radeon_device *rdev);
1137 : void radeon_agp_suspend(struct radeon_device *rdev);
1138 : void radeon_agp_fini(struct radeon_device *rdev);
1139 :
1140 :
1141 : /*
1142 : * Writeback
1143 : */
1144 : struct radeon_wb {
1145 : struct radeon_bo *wb_obj;
1146 : volatile uint32_t *wb;
1147 : uint64_t gpu_addr;
1148 : bool enabled;
1149 : bool use_event;
1150 : };
1151 :
1152 : #define RADEON_WB_SCRATCH_OFFSET 0
1153 : #define RADEON_WB_RING0_NEXT_RPTR 256
1154 : #define RADEON_WB_CP_RPTR_OFFSET 1024
1155 : #define RADEON_WB_CP1_RPTR_OFFSET 1280
1156 : #define RADEON_WB_CP2_RPTR_OFFSET 1536
1157 : #define R600_WB_DMA_RPTR_OFFSET 1792
1158 : #define R600_WB_IH_WPTR_OFFSET 2048
1159 : #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1160 : #define R600_WB_EVENT_OFFSET 3072
1161 : #define CIK_WB_CP1_WPTR_OFFSET 3328
1162 : #define CIK_WB_CP2_WPTR_OFFSET 3584
1163 : #define R600_WB_DMA_RING_TEST_OFFSET 3588
1164 : #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1165 :
1166 : /**
1167 : * struct radeon_pm - power management datas
1168 : * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1169 : * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1170 : * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1171 : * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1172 : * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1173 : * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1174 : * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1175 : * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1176 : * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1177 : * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1178 : * @needed_bandwidth: current bandwidth needs
1179 : *
1180 : * It keeps track of various data needed to take powermanagement decision.
1181 : * Bandwidth need is used to determine minimun clock of the GPU and memory.
1182 : * Equation between gpu/memory clock and available bandwidth is hw dependent
1183 : * (type of memory, bus size, efficiency, ...)
1184 : */
1185 :
1186 : enum radeon_pm_method {
1187 : PM_METHOD_PROFILE,
1188 : PM_METHOD_DYNPM,
1189 : PM_METHOD_DPM,
1190 : };
1191 :
1192 : enum radeon_dynpm_state {
1193 : DYNPM_STATE_DISABLED,
1194 : DYNPM_STATE_MINIMUM,
1195 : DYNPM_STATE_PAUSED,
1196 : DYNPM_STATE_ACTIVE,
1197 : DYNPM_STATE_SUSPENDED,
1198 : };
1199 : enum radeon_dynpm_action {
1200 : DYNPM_ACTION_NONE,
1201 : DYNPM_ACTION_MINIMUM,
1202 : DYNPM_ACTION_DOWNCLOCK,
1203 : DYNPM_ACTION_UPCLOCK,
1204 : DYNPM_ACTION_DEFAULT
1205 : };
1206 :
1207 : enum radeon_voltage_type {
1208 : VOLTAGE_NONE = 0,
1209 : VOLTAGE_GPIO,
1210 : VOLTAGE_VDDC,
1211 : VOLTAGE_SW
1212 : };
1213 :
1214 : enum radeon_pm_state_type {
1215 : /* not used for dpm */
1216 : POWER_STATE_TYPE_DEFAULT,
1217 : POWER_STATE_TYPE_POWERSAVE,
1218 : /* user selectable states */
1219 : POWER_STATE_TYPE_BATTERY,
1220 : POWER_STATE_TYPE_BALANCED,
1221 : POWER_STATE_TYPE_PERFORMANCE,
1222 : /* internal states */
1223 : POWER_STATE_TYPE_INTERNAL_UVD,
1224 : POWER_STATE_TYPE_INTERNAL_UVD_SD,
1225 : POWER_STATE_TYPE_INTERNAL_UVD_HD,
1226 : POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1227 : POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1228 : POWER_STATE_TYPE_INTERNAL_BOOT,
1229 : POWER_STATE_TYPE_INTERNAL_THERMAL,
1230 : POWER_STATE_TYPE_INTERNAL_ACPI,
1231 : POWER_STATE_TYPE_INTERNAL_ULV,
1232 : POWER_STATE_TYPE_INTERNAL_3DPERF,
1233 : };
1234 :
1235 : enum radeon_pm_profile_type {
1236 : PM_PROFILE_DEFAULT,
1237 : PM_PROFILE_AUTO,
1238 : PM_PROFILE_LOW,
1239 : PM_PROFILE_MID,
1240 : PM_PROFILE_HIGH,
1241 : };
1242 :
1243 : #define PM_PROFILE_DEFAULT_IDX 0
1244 : #define PM_PROFILE_LOW_SH_IDX 1
1245 : #define PM_PROFILE_MID_SH_IDX 2
1246 : #define PM_PROFILE_HIGH_SH_IDX 3
1247 : #define PM_PROFILE_LOW_MH_IDX 4
1248 : #define PM_PROFILE_MID_MH_IDX 5
1249 : #define PM_PROFILE_HIGH_MH_IDX 6
1250 : #define PM_PROFILE_MAX 7
1251 :
1252 : struct radeon_pm_profile {
1253 : int dpms_off_ps_idx;
1254 : int dpms_on_ps_idx;
1255 : int dpms_off_cm_idx;
1256 : int dpms_on_cm_idx;
1257 : };
1258 :
1259 : enum radeon_int_thermal_type {
1260 : THERMAL_TYPE_NONE,
1261 : THERMAL_TYPE_EXTERNAL,
1262 : THERMAL_TYPE_EXTERNAL_GPIO,
1263 : THERMAL_TYPE_RV6XX,
1264 : THERMAL_TYPE_RV770,
1265 : THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1266 : THERMAL_TYPE_EVERGREEN,
1267 : THERMAL_TYPE_SUMO,
1268 : THERMAL_TYPE_NI,
1269 : THERMAL_TYPE_SI,
1270 : THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1271 : THERMAL_TYPE_CI,
1272 : THERMAL_TYPE_KV,
1273 : };
1274 :
1275 : struct radeon_voltage {
1276 : enum radeon_voltage_type type;
1277 : /* gpio voltage */
1278 : struct radeon_gpio_rec gpio;
1279 : u32 delay; /* delay in usec from voltage drop to sclk change */
1280 : bool active_high; /* voltage drop is active when bit is high */
1281 : /* VDDC voltage */
1282 : u8 vddc_id; /* index into vddc voltage table */
1283 : u8 vddci_id; /* index into vddci voltage table */
1284 : bool vddci_enabled;
1285 : /* r6xx+ sw */
1286 : u16 voltage;
1287 : /* evergreen+ vddci */
1288 : u16 vddci;
1289 : };
1290 :
1291 : /* clock mode flags */
1292 : #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1293 :
1294 : struct radeon_pm_clock_info {
1295 : /* memory clock */
1296 : u32 mclk;
1297 : /* engine clock */
1298 : u32 sclk;
1299 : /* voltage info */
1300 : struct radeon_voltage voltage;
1301 : /* standardized clock flags */
1302 : u32 flags;
1303 : };
1304 :
1305 : /* state flags */
1306 : #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1307 :
1308 : struct radeon_power_state {
1309 : enum radeon_pm_state_type type;
1310 : struct radeon_pm_clock_info *clock_info;
1311 : /* number of valid clock modes in this power state */
1312 : int num_clock_modes;
1313 : struct radeon_pm_clock_info *default_clock_mode;
1314 : /* standardized state flags */
1315 : u32 flags;
1316 : u32 misc; /* vbios specific flags */
1317 : u32 misc2; /* vbios specific flags */
1318 : int pcie_lanes; /* pcie lanes */
1319 : };
1320 :
1321 : /*
1322 : * Some modes are overclocked by very low value, accept them
1323 : */
1324 : #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1325 :
1326 : enum radeon_dpm_auto_throttle_src {
1327 : RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1328 : RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1329 : };
1330 :
1331 : enum radeon_dpm_event_src {
1332 : RADEON_DPM_EVENT_SRC_ANALOG = 0,
1333 : RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1334 : RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1335 : RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1336 : RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1337 : };
1338 :
1339 : #define RADEON_MAX_VCE_LEVELS 6
1340 :
1341 : enum radeon_vce_level {
1342 : RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1343 : RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1344 : RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1345 : RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1346 : RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1347 : RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1348 : };
1349 :
1350 : struct radeon_ps {
1351 : u32 caps; /* vbios flags */
1352 : u32 class; /* vbios flags */
1353 : u32 class2; /* vbios flags */
1354 : /* UVD clocks */
1355 : u32 vclk;
1356 : u32 dclk;
1357 : /* VCE clocks */
1358 : u32 evclk;
1359 : u32 ecclk;
1360 : bool vce_active;
1361 : enum radeon_vce_level vce_level;
1362 : /* asic priv */
1363 : void *ps_priv;
1364 : };
1365 :
1366 : struct radeon_dpm_thermal {
1367 : /* thermal interrupt work */
1368 : struct work_struct work;
1369 : /* low temperature threshold */
1370 : int min_temp;
1371 : /* high temperature threshold */
1372 : int max_temp;
1373 : /* was interrupt low to high or high to low */
1374 : bool high_to_low;
1375 : };
1376 :
1377 : enum radeon_clk_action
1378 : {
1379 : RADEON_SCLK_UP = 1,
1380 : RADEON_SCLK_DOWN
1381 : };
1382 :
1383 : struct radeon_blacklist_clocks
1384 : {
1385 : u32 sclk;
1386 : u32 mclk;
1387 : enum radeon_clk_action action;
1388 : };
1389 :
1390 : struct radeon_clock_and_voltage_limits {
1391 : u32 sclk;
1392 : u32 mclk;
1393 : u16 vddc;
1394 : u16 vddci;
1395 : };
1396 :
1397 : struct radeon_clock_array {
1398 : u32 count;
1399 : u32 *values;
1400 : };
1401 :
1402 : struct radeon_clock_voltage_dependency_entry {
1403 : u32 clk;
1404 : u16 v;
1405 : };
1406 :
1407 : struct radeon_clock_voltage_dependency_table {
1408 : u32 count;
1409 : struct radeon_clock_voltage_dependency_entry *entries;
1410 : };
1411 :
1412 : union radeon_cac_leakage_entry {
1413 : struct {
1414 : u16 vddc;
1415 : u32 leakage;
1416 : };
1417 : struct {
1418 : u16 vddc1;
1419 : u16 vddc2;
1420 : u16 vddc3;
1421 : };
1422 : };
1423 :
1424 : struct radeon_cac_leakage_table {
1425 : u32 count;
1426 : union radeon_cac_leakage_entry *entries;
1427 : };
1428 :
1429 : struct radeon_phase_shedding_limits_entry {
1430 : u16 voltage;
1431 : u32 sclk;
1432 : u32 mclk;
1433 : };
1434 :
1435 : struct radeon_phase_shedding_limits_table {
1436 : u32 count;
1437 : struct radeon_phase_shedding_limits_entry *entries;
1438 : };
1439 :
1440 : struct radeon_uvd_clock_voltage_dependency_entry {
1441 : u32 vclk;
1442 : u32 dclk;
1443 : u16 v;
1444 : };
1445 :
1446 : struct radeon_uvd_clock_voltage_dependency_table {
1447 : u8 count;
1448 : struct radeon_uvd_clock_voltage_dependency_entry *entries;
1449 : };
1450 :
1451 : struct radeon_vce_clock_voltage_dependency_entry {
1452 : u32 ecclk;
1453 : u32 evclk;
1454 : u16 v;
1455 : };
1456 :
1457 : struct radeon_vce_clock_voltage_dependency_table {
1458 : u8 count;
1459 : struct radeon_vce_clock_voltage_dependency_entry *entries;
1460 : };
1461 :
1462 : struct radeon_ppm_table {
1463 : u8 ppm_design;
1464 : u16 cpu_core_number;
1465 : u32 platform_tdp;
1466 : u32 small_ac_platform_tdp;
1467 : u32 platform_tdc;
1468 : u32 small_ac_platform_tdc;
1469 : u32 apu_tdp;
1470 : u32 dgpu_tdp;
1471 : u32 dgpu_ulv_power;
1472 : u32 tj_max;
1473 : };
1474 :
1475 : struct radeon_cac_tdp_table {
1476 : u16 tdp;
1477 : u16 configurable_tdp;
1478 : u16 tdc;
1479 : u16 battery_power_limit;
1480 : u16 small_power_limit;
1481 : u16 low_cac_leakage;
1482 : u16 high_cac_leakage;
1483 : u16 maximum_power_delivery_limit;
1484 : };
1485 :
1486 : struct radeon_dpm_dynamic_state {
1487 : struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1488 : struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1489 : struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1490 : struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1491 : struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1492 : struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1493 : struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1494 : struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1495 : struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1496 : struct radeon_clock_array valid_sclk_values;
1497 : struct radeon_clock_array valid_mclk_values;
1498 : struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1499 : struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1500 : u32 mclk_sclk_ratio;
1501 : u32 sclk_mclk_delta;
1502 : u16 vddc_vddci_delta;
1503 : u16 min_vddc_for_pcie_gen2;
1504 : struct radeon_cac_leakage_table cac_leakage_table;
1505 : struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1506 : struct radeon_ppm_table *ppm_table;
1507 : struct radeon_cac_tdp_table *cac_tdp_table;
1508 : };
1509 :
1510 : struct radeon_dpm_fan {
1511 : u16 t_min;
1512 : u16 t_med;
1513 : u16 t_high;
1514 : u16 pwm_min;
1515 : u16 pwm_med;
1516 : u16 pwm_high;
1517 : u8 t_hyst;
1518 : u32 cycle_delay;
1519 : u16 t_max;
1520 : u8 control_mode;
1521 : u16 default_max_fan_pwm;
1522 : u16 default_fan_output_sensitivity;
1523 : u16 fan_output_sensitivity;
1524 : bool ucode_fan_control;
1525 : };
1526 :
1527 : enum radeon_pcie_gen {
1528 : RADEON_PCIE_GEN1 = 0,
1529 : RADEON_PCIE_GEN2 = 1,
1530 : RADEON_PCIE_GEN3 = 2,
1531 : RADEON_PCIE_GEN_INVALID = 0xffff
1532 : };
1533 :
1534 : enum radeon_dpm_forced_level {
1535 : RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1536 : RADEON_DPM_FORCED_LEVEL_LOW = 1,
1537 : RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1538 : };
1539 :
1540 : struct radeon_vce_state {
1541 : /* vce clocks */
1542 : u32 evclk;
1543 : u32 ecclk;
1544 : /* gpu clocks */
1545 : u32 sclk;
1546 : u32 mclk;
1547 : u8 clk_idx;
1548 : u8 pstate;
1549 : };
1550 :
1551 : struct radeon_dpm {
1552 : struct radeon_ps *ps;
1553 : /* number of valid power states */
1554 : int num_ps;
1555 : /* current power state that is active */
1556 : struct radeon_ps *current_ps;
1557 : /* requested power state */
1558 : struct radeon_ps *requested_ps;
1559 : /* boot up power state */
1560 : struct radeon_ps *boot_ps;
1561 : /* default uvd power state */
1562 : struct radeon_ps *uvd_ps;
1563 : /* vce requirements */
1564 : struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1565 : enum radeon_vce_level vce_level;
1566 : enum radeon_pm_state_type state;
1567 : enum radeon_pm_state_type user_state;
1568 : u32 platform_caps;
1569 : u32 voltage_response_time;
1570 : u32 backbias_response_time;
1571 : void *priv;
1572 : u32 new_active_crtcs;
1573 : int new_active_crtc_count;
1574 : u32 current_active_crtcs;
1575 : int current_active_crtc_count;
1576 : bool single_display;
1577 : struct radeon_dpm_dynamic_state dyn_state;
1578 : struct radeon_dpm_fan fan;
1579 : u32 tdp_limit;
1580 : u32 near_tdp_limit;
1581 : u32 near_tdp_limit_adjusted;
1582 : u32 sq_ramping_threshold;
1583 : u32 cac_leakage;
1584 : u16 tdp_od_limit;
1585 : u32 tdp_adjustment;
1586 : u16 load_line_slope;
1587 : bool power_control;
1588 : bool ac_power;
1589 : /* special states active */
1590 : bool thermal_active;
1591 : bool uvd_active;
1592 : bool vce_active;
1593 : /* thermal handling */
1594 : struct radeon_dpm_thermal thermal;
1595 : /* forced levels */
1596 : enum radeon_dpm_forced_level forced_level;
1597 : /* track UVD streams */
1598 : unsigned sd;
1599 : unsigned hd;
1600 : };
1601 :
1602 : void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1603 : void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1604 :
1605 : struct radeon_pm {
1606 : struct rwlock mutex;
1607 : /* write locked while reprogramming mclk */
1608 : struct rwlock mclk_lock;
1609 : u32 active_crtcs;
1610 : int active_crtc_count;
1611 : int req_vblank;
1612 : bool vblank_sync;
1613 : fixed20_12 max_bandwidth;
1614 : fixed20_12 igp_sideport_mclk;
1615 : fixed20_12 igp_system_mclk;
1616 : fixed20_12 igp_ht_link_clk;
1617 : fixed20_12 igp_ht_link_width;
1618 : fixed20_12 k8_bandwidth;
1619 : fixed20_12 sideport_bandwidth;
1620 : fixed20_12 ht_bandwidth;
1621 : fixed20_12 core_bandwidth;
1622 : fixed20_12 sclk;
1623 : fixed20_12 mclk;
1624 : fixed20_12 needed_bandwidth;
1625 : struct radeon_power_state *power_state;
1626 : /* number of valid power states */
1627 : int num_power_states;
1628 : int current_power_state_index;
1629 : int current_clock_mode_index;
1630 : int requested_power_state_index;
1631 : int requested_clock_mode_index;
1632 : int default_power_state_index;
1633 : u32 current_sclk;
1634 : u32 current_mclk;
1635 : u16 current_vddc;
1636 : u16 current_vddci;
1637 : u32 default_sclk;
1638 : u32 default_mclk;
1639 : u16 default_vddc;
1640 : u16 default_vddci;
1641 : struct radeon_i2c_chan *i2c_bus;
1642 : /* selected pm method */
1643 : enum radeon_pm_method pm_method;
1644 : /* dynpm power management */
1645 : struct delayed_work dynpm_idle_work;
1646 : enum radeon_dynpm_state dynpm_state;
1647 : enum radeon_dynpm_action dynpm_planned_action;
1648 : unsigned long dynpm_action_timeout;
1649 : bool dynpm_can_upclock;
1650 : bool dynpm_can_downclock;
1651 : /* profile-based power management */
1652 : enum radeon_pm_profile_type profile;
1653 : int profile_index;
1654 : struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1655 : /* internal thermal controller on rv6xx+ */
1656 : enum radeon_int_thermal_type int_thermal_type;
1657 : struct device *int_hwmon_dev;
1658 : /* fan control parameters */
1659 : bool no_fan;
1660 : u8 fan_pulses_per_revolution;
1661 : u8 fan_min_rpm;
1662 : u8 fan_max_rpm;
1663 : /* dpm */
1664 : bool dpm_enabled;
1665 : bool sysfs_initialized;
1666 : struct radeon_dpm dpm;
1667 : };
1668 :
1669 : int radeon_pm_get_type_index(struct radeon_device *rdev,
1670 : enum radeon_pm_state_type ps_type,
1671 : int instance);
1672 : /*
1673 : * UVD
1674 : */
1675 : #define RADEON_MAX_UVD_HANDLES 10
1676 : #define RADEON_UVD_STACK_SIZE (1024*1024)
1677 : #define RADEON_UVD_HEAP_SIZE (1024*1024)
1678 :
1679 : struct radeon_uvd {
1680 : struct radeon_bo *vcpu_bo;
1681 : void *cpu_addr;
1682 : uint64_t gpu_addr;
1683 : atomic_t handles[RADEON_MAX_UVD_HANDLES];
1684 : struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1685 : unsigned img_size[RADEON_MAX_UVD_HANDLES];
1686 : struct delayed_work idle_work;
1687 : };
1688 :
1689 : int radeon_uvd_init(struct radeon_device *rdev);
1690 : void radeon_uvd_fini(struct radeon_device *rdev);
1691 : int radeon_uvd_suspend(struct radeon_device *rdev);
1692 : int radeon_uvd_resume(struct radeon_device *rdev);
1693 : int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1694 : uint32_t handle, struct radeon_fence **fence);
1695 : int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1696 : uint32_t handle, struct radeon_fence **fence);
1697 : void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1698 : uint32_t allowed_domains);
1699 : void radeon_uvd_free_handles(struct radeon_device *rdev,
1700 : struct drm_file *filp);
1701 : int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1702 : void radeon_uvd_note_usage(struct radeon_device *rdev);
1703 : int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1704 : unsigned vclk, unsigned dclk,
1705 : unsigned vco_min, unsigned vco_max,
1706 : unsigned fb_factor, unsigned fb_mask,
1707 : unsigned pd_min, unsigned pd_max,
1708 : unsigned pd_even,
1709 : unsigned *optimal_fb_div,
1710 : unsigned *optimal_vclk_div,
1711 : unsigned *optimal_dclk_div);
1712 : int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1713 : unsigned cg_upll_func_cntl);
1714 :
1715 : /*
1716 : * VCE
1717 : */
1718 : #define RADEON_MAX_VCE_HANDLES 16
1719 :
1720 : struct radeon_vce {
1721 : struct radeon_bo *vcpu_bo;
1722 : uint64_t gpu_addr;
1723 : unsigned fw_version;
1724 : unsigned fb_version;
1725 : atomic_t handles[RADEON_MAX_VCE_HANDLES];
1726 : struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1727 : unsigned img_size[RADEON_MAX_VCE_HANDLES];
1728 : struct delayed_work idle_work;
1729 : uint32_t keyselect;
1730 : };
1731 :
1732 : int radeon_vce_init(struct radeon_device *rdev);
1733 : void radeon_vce_fini(struct radeon_device *rdev);
1734 : int radeon_vce_suspend(struct radeon_device *rdev);
1735 : int radeon_vce_resume(struct radeon_device *rdev);
1736 : int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1737 : uint32_t handle, struct radeon_fence **fence);
1738 : int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1739 : uint32_t handle, struct radeon_fence **fence);
1740 : void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1741 : void radeon_vce_note_usage(struct radeon_device *rdev);
1742 : int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1743 : int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1744 : bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1745 : struct radeon_ring *ring,
1746 : struct radeon_semaphore *semaphore,
1747 : bool emit_wait);
1748 : void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1749 : void radeon_vce_fence_emit(struct radeon_device *rdev,
1750 : struct radeon_fence *fence);
1751 : int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1752 : int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1753 :
1754 : struct r600_audio_pin {
1755 : int channels;
1756 : int rate;
1757 : int bits_per_sample;
1758 : u8 status_bits;
1759 : u8 category_code;
1760 : u32 offset;
1761 : bool connected;
1762 : u32 id;
1763 : };
1764 :
1765 : struct r600_audio {
1766 : bool enabled;
1767 : struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1768 : int num_pins;
1769 : struct radeon_audio_funcs *hdmi_funcs;
1770 : struct radeon_audio_funcs *dp_funcs;
1771 : struct radeon_audio_basic_funcs *funcs;
1772 : };
1773 :
1774 : /*
1775 : * Benchmarking
1776 : */
1777 : void radeon_benchmark(struct radeon_device *rdev, int test_number);
1778 :
1779 :
1780 : /*
1781 : * Testing
1782 : */
1783 : void radeon_test_moves(struct radeon_device *rdev);
1784 : void radeon_test_ring_sync(struct radeon_device *rdev,
1785 : struct radeon_ring *cpA,
1786 : struct radeon_ring *cpB);
1787 : void radeon_test_syncing(struct radeon_device *rdev);
1788 :
1789 : /*
1790 : * MMU Notifier
1791 : */
1792 : #if defined(CONFIG_MMU_NOTIFIER)
1793 : int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1794 : void radeon_mn_unregister(struct radeon_bo *bo);
1795 : #else
1796 : static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1797 : {
1798 : return -ENODEV;
1799 : }
1800 0 : static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1801 : #endif
1802 :
1803 : /*
1804 : * Debugfs
1805 : */
1806 : struct radeon_debugfs {
1807 : struct drm_info_list *files;
1808 : unsigned num_files;
1809 : };
1810 :
1811 : int radeon_debugfs_add_files(struct radeon_device *rdev,
1812 : struct drm_info_list *files,
1813 : unsigned nfiles);
1814 : int radeon_debugfs_fence_init(struct radeon_device *rdev);
1815 :
1816 : /*
1817 : * ASIC ring specific functions.
1818 : */
1819 : struct radeon_asic_ring {
1820 : /* ring read/write ptr handling */
1821 : u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1822 : u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1823 : void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1824 :
1825 : /* validating and patching of IBs */
1826 : int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1827 : int (*cs_parse)(struct radeon_cs_parser *p);
1828 :
1829 : /* command emmit functions */
1830 : void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1831 : void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1832 : void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1833 : bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1834 : struct radeon_semaphore *semaphore, bool emit_wait);
1835 : void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1836 : unsigned vm_id, uint64_t pd_addr);
1837 :
1838 : /* testing functions */
1839 : int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1840 : int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1841 : bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1842 :
1843 : /* deprecated */
1844 : void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1845 : };
1846 :
1847 : /*
1848 : * ASIC specific functions.
1849 : */
1850 : struct radeon_asic {
1851 : int (*init)(struct radeon_device *rdev);
1852 : void (*fini)(struct radeon_device *rdev);
1853 : int (*resume)(struct radeon_device *rdev);
1854 : int (*suspend)(struct radeon_device *rdev);
1855 : void (*vga_set_state)(struct radeon_device *rdev, bool state);
1856 : int (*asic_reset)(struct radeon_device *rdev);
1857 : /* Flush the HDP cache via MMIO */
1858 : void (*mmio_hdp_flush)(struct radeon_device *rdev);
1859 : /* check if 3D engine is idle */
1860 : bool (*gui_idle)(struct radeon_device *rdev);
1861 : /* wait for mc_idle */
1862 : int (*mc_wait_for_idle)(struct radeon_device *rdev);
1863 : /* get the reference clock */
1864 : u32 (*get_xclk)(struct radeon_device *rdev);
1865 : /* get the gpu clock counter */
1866 : uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1867 : /* get register for info ioctl */
1868 : int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1869 : /* gart */
1870 : struct {
1871 : void (*tlb_flush)(struct radeon_device *rdev);
1872 : uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1873 : void (*set_page)(struct radeon_device *rdev, unsigned i,
1874 : uint64_t entry);
1875 : } gart;
1876 : struct {
1877 : int (*init)(struct radeon_device *rdev);
1878 : void (*fini)(struct radeon_device *rdev);
1879 : void (*copy_pages)(struct radeon_device *rdev,
1880 : struct radeon_ib *ib,
1881 : uint64_t pe, uint64_t src,
1882 : unsigned count);
1883 : void (*write_pages)(struct radeon_device *rdev,
1884 : struct radeon_ib *ib,
1885 : uint64_t pe,
1886 : uint64_t addr, unsigned count,
1887 : uint32_t incr, uint32_t flags);
1888 : void (*set_pages)(struct radeon_device *rdev,
1889 : struct radeon_ib *ib,
1890 : uint64_t pe,
1891 : uint64_t addr, unsigned count,
1892 : uint32_t incr, uint32_t flags);
1893 : void (*pad_ib)(struct radeon_ib *ib);
1894 : } vm;
1895 : /* ring specific callbacks */
1896 : struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1897 : /* irqs */
1898 : struct {
1899 : int (*set)(struct radeon_device *rdev);
1900 : int (*process)(struct radeon_device *rdev);
1901 : } irq;
1902 : /* displays */
1903 : struct {
1904 : /* display watermarks */
1905 : void (*bandwidth_update)(struct radeon_device *rdev);
1906 : /* get frame count */
1907 : u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1908 : /* wait for vblank */
1909 : void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1910 : /* set backlight level */
1911 : void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1912 : /* get backlight level */
1913 : u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1914 : /* audio callbacks */
1915 : void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1916 : void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1917 : } display;
1918 : /* copy functions for bo handling */
1919 : struct {
1920 : struct radeon_fence *(*blit)(struct radeon_device *rdev,
1921 : uint64_t src_offset,
1922 : uint64_t dst_offset,
1923 : unsigned num_gpu_pages,
1924 : struct reservation_object *resv);
1925 : u32 blit_ring_index;
1926 : struct radeon_fence *(*dma)(struct radeon_device *rdev,
1927 : uint64_t src_offset,
1928 : uint64_t dst_offset,
1929 : unsigned num_gpu_pages,
1930 : struct reservation_object *resv);
1931 : u32 dma_ring_index;
1932 : /* method used for bo copy */
1933 : struct radeon_fence *(*copy)(struct radeon_device *rdev,
1934 : uint64_t src_offset,
1935 : uint64_t dst_offset,
1936 : unsigned num_gpu_pages,
1937 : struct reservation_object *resv);
1938 : /* ring used for bo copies */
1939 : u32 copy_ring_index;
1940 : } copy;
1941 : /* surfaces */
1942 : struct {
1943 : int (*set_reg)(struct radeon_device *rdev, int reg,
1944 : uint32_t tiling_flags, uint32_t pitch,
1945 : uint32_t offset, uint32_t obj_size);
1946 : void (*clear_reg)(struct radeon_device *rdev, int reg);
1947 : } surface;
1948 : /* hotplug detect */
1949 : struct {
1950 : void (*init)(struct radeon_device *rdev);
1951 : void (*fini)(struct radeon_device *rdev);
1952 : bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1953 : void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1954 : } hpd;
1955 : /* static power management */
1956 : struct {
1957 : void (*misc)(struct radeon_device *rdev);
1958 : void (*prepare)(struct radeon_device *rdev);
1959 : void (*finish)(struct radeon_device *rdev);
1960 : void (*init_profile)(struct radeon_device *rdev);
1961 : void (*get_dynpm_state)(struct radeon_device *rdev);
1962 : uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1963 : void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1964 : uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1965 : void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1966 : int (*get_pcie_lanes)(struct radeon_device *rdev);
1967 : void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1968 : void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1969 : int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1970 : int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1971 : int (*get_temperature)(struct radeon_device *rdev);
1972 : } pm;
1973 : /* dynamic power management */
1974 : struct {
1975 : int (*init)(struct radeon_device *rdev);
1976 : void (*setup_asic)(struct radeon_device *rdev);
1977 : int (*enable)(struct radeon_device *rdev);
1978 : int (*late_enable)(struct radeon_device *rdev);
1979 : void (*disable)(struct radeon_device *rdev);
1980 : int (*pre_set_power_state)(struct radeon_device *rdev);
1981 : int (*set_power_state)(struct radeon_device *rdev);
1982 : void (*post_set_power_state)(struct radeon_device *rdev);
1983 : void (*display_configuration_changed)(struct radeon_device *rdev);
1984 : void (*fini)(struct radeon_device *rdev);
1985 : u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1986 : u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1987 : void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1988 : void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1989 : int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1990 : bool (*vblank_too_short)(struct radeon_device *rdev);
1991 : void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1992 : void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1993 : void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1994 : u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1995 : int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1996 : int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1997 : u32 (*get_current_sclk)(struct radeon_device *rdev);
1998 : u32 (*get_current_mclk)(struct radeon_device *rdev);
1999 : } dpm;
2000 : /* pageflipping */
2001 : struct {
2002 : void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
2003 : bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2004 : } pflip;
2005 : };
2006 :
2007 : /*
2008 : * Asic structures
2009 : */
2010 : struct r100_asic {
2011 : const unsigned *reg_safe_bm;
2012 : unsigned reg_safe_bm_size;
2013 : u32 hdp_cntl;
2014 : };
2015 :
2016 : struct r300_asic {
2017 : const unsigned *reg_safe_bm;
2018 : unsigned reg_safe_bm_size;
2019 : u32 resync_scratch;
2020 : u32 hdp_cntl;
2021 : };
2022 :
2023 : struct r600_asic {
2024 : unsigned max_pipes;
2025 : unsigned max_tile_pipes;
2026 : unsigned max_simds;
2027 : unsigned max_backends;
2028 : unsigned max_gprs;
2029 : unsigned max_threads;
2030 : unsigned max_stack_entries;
2031 : unsigned max_hw_contexts;
2032 : unsigned max_gs_threads;
2033 : unsigned sx_max_export_size;
2034 : unsigned sx_max_export_pos_size;
2035 : unsigned sx_max_export_smx_size;
2036 : unsigned sq_num_cf_insts;
2037 : unsigned tiling_nbanks;
2038 : unsigned tiling_npipes;
2039 : unsigned tiling_group_size;
2040 : unsigned tile_config;
2041 : unsigned backend_map;
2042 : unsigned active_simds;
2043 : };
2044 :
2045 : struct rv770_asic {
2046 : unsigned max_pipes;
2047 : unsigned max_tile_pipes;
2048 : unsigned max_simds;
2049 : unsigned max_backends;
2050 : unsigned max_gprs;
2051 : unsigned max_threads;
2052 : unsigned max_stack_entries;
2053 : unsigned max_hw_contexts;
2054 : unsigned max_gs_threads;
2055 : unsigned sx_max_export_size;
2056 : unsigned sx_max_export_pos_size;
2057 : unsigned sx_max_export_smx_size;
2058 : unsigned sq_num_cf_insts;
2059 : unsigned sx_num_of_sets;
2060 : unsigned sc_prim_fifo_size;
2061 : unsigned sc_hiz_tile_fifo_size;
2062 : unsigned sc_earlyz_tile_fifo_fize;
2063 : unsigned tiling_nbanks;
2064 : unsigned tiling_npipes;
2065 : unsigned tiling_group_size;
2066 : unsigned tile_config;
2067 : unsigned backend_map;
2068 : unsigned active_simds;
2069 : };
2070 :
2071 : struct evergreen_asic {
2072 : unsigned num_ses;
2073 : unsigned max_pipes;
2074 : unsigned max_tile_pipes;
2075 : unsigned max_simds;
2076 : unsigned max_backends;
2077 : unsigned max_gprs;
2078 : unsigned max_threads;
2079 : unsigned max_stack_entries;
2080 : unsigned max_hw_contexts;
2081 : unsigned max_gs_threads;
2082 : unsigned sx_max_export_size;
2083 : unsigned sx_max_export_pos_size;
2084 : unsigned sx_max_export_smx_size;
2085 : unsigned sq_num_cf_insts;
2086 : unsigned sx_num_of_sets;
2087 : unsigned sc_prim_fifo_size;
2088 : unsigned sc_hiz_tile_fifo_size;
2089 : unsigned sc_earlyz_tile_fifo_size;
2090 : unsigned tiling_nbanks;
2091 : unsigned tiling_npipes;
2092 : unsigned tiling_group_size;
2093 : unsigned tile_config;
2094 : unsigned backend_map;
2095 : unsigned active_simds;
2096 : };
2097 :
2098 : struct cayman_asic {
2099 : unsigned max_shader_engines;
2100 : unsigned max_pipes_per_simd;
2101 : unsigned max_tile_pipes;
2102 : unsigned max_simds_per_se;
2103 : unsigned max_backends_per_se;
2104 : unsigned max_texture_channel_caches;
2105 : unsigned max_gprs;
2106 : unsigned max_threads;
2107 : unsigned max_gs_threads;
2108 : unsigned max_stack_entries;
2109 : unsigned sx_num_of_sets;
2110 : unsigned sx_max_export_size;
2111 : unsigned sx_max_export_pos_size;
2112 : unsigned sx_max_export_smx_size;
2113 : unsigned max_hw_contexts;
2114 : unsigned sq_num_cf_insts;
2115 : unsigned sc_prim_fifo_size;
2116 : unsigned sc_hiz_tile_fifo_size;
2117 : unsigned sc_earlyz_tile_fifo_size;
2118 :
2119 : unsigned num_shader_engines;
2120 : unsigned num_shader_pipes_per_simd;
2121 : unsigned num_tile_pipes;
2122 : unsigned num_simds_per_se;
2123 : unsigned num_backends_per_se;
2124 : unsigned backend_disable_mask_per_asic;
2125 : unsigned backend_map;
2126 : unsigned num_texture_channel_caches;
2127 : unsigned mem_max_burst_length_bytes;
2128 : unsigned mem_row_size_in_kb;
2129 : unsigned shader_engine_tile_size;
2130 : unsigned num_gpus;
2131 : unsigned multi_gpu_tile_size;
2132 :
2133 : unsigned tile_config;
2134 : unsigned active_simds;
2135 : };
2136 :
2137 : struct si_asic {
2138 : unsigned max_shader_engines;
2139 : unsigned max_tile_pipes;
2140 : unsigned max_cu_per_sh;
2141 : unsigned max_sh_per_se;
2142 : unsigned max_backends_per_se;
2143 : unsigned max_texture_channel_caches;
2144 : unsigned max_gprs;
2145 : unsigned max_gs_threads;
2146 : unsigned max_hw_contexts;
2147 : unsigned sc_prim_fifo_size_frontend;
2148 : unsigned sc_prim_fifo_size_backend;
2149 : unsigned sc_hiz_tile_fifo_size;
2150 : unsigned sc_earlyz_tile_fifo_size;
2151 :
2152 : unsigned num_tile_pipes;
2153 : unsigned backend_enable_mask;
2154 : unsigned backend_disable_mask_per_asic;
2155 : unsigned backend_map;
2156 : unsigned num_texture_channel_caches;
2157 : unsigned mem_max_burst_length_bytes;
2158 : unsigned mem_row_size_in_kb;
2159 : unsigned shader_engine_tile_size;
2160 : unsigned num_gpus;
2161 : unsigned multi_gpu_tile_size;
2162 :
2163 : unsigned tile_config;
2164 : uint32_t tile_mode_array[32];
2165 : uint32_t active_cus;
2166 : };
2167 :
2168 : struct cik_asic {
2169 : unsigned max_shader_engines;
2170 : unsigned max_tile_pipes;
2171 : unsigned max_cu_per_sh;
2172 : unsigned max_sh_per_se;
2173 : unsigned max_backends_per_se;
2174 : unsigned max_texture_channel_caches;
2175 : unsigned max_gprs;
2176 : unsigned max_gs_threads;
2177 : unsigned max_hw_contexts;
2178 : unsigned sc_prim_fifo_size_frontend;
2179 : unsigned sc_prim_fifo_size_backend;
2180 : unsigned sc_hiz_tile_fifo_size;
2181 : unsigned sc_earlyz_tile_fifo_size;
2182 :
2183 : unsigned num_tile_pipes;
2184 : unsigned backend_enable_mask;
2185 : unsigned backend_disable_mask_per_asic;
2186 : unsigned backend_map;
2187 : unsigned num_texture_channel_caches;
2188 : unsigned mem_max_burst_length_bytes;
2189 : unsigned mem_row_size_in_kb;
2190 : unsigned shader_engine_tile_size;
2191 : unsigned num_gpus;
2192 : unsigned multi_gpu_tile_size;
2193 :
2194 : unsigned tile_config;
2195 : uint32_t tile_mode_array[32];
2196 : uint32_t macrotile_mode_array[16];
2197 : uint32_t active_cus;
2198 : };
2199 :
2200 : union radeon_asic_config {
2201 : struct r300_asic r300;
2202 : struct r100_asic r100;
2203 : struct r600_asic r600;
2204 : struct rv770_asic rv770;
2205 : struct evergreen_asic evergreen;
2206 : struct cayman_asic cayman;
2207 : struct si_asic si;
2208 : struct cik_asic cik;
2209 : };
2210 :
2211 : /*
2212 : * asic initizalization from radeon_asic.c
2213 : */
2214 : void radeon_agp_disable(struct radeon_device *rdev);
2215 : int radeon_asic_init(struct radeon_device *rdev);
2216 :
2217 :
2218 : /*
2219 : * IOCTL.
2220 : */
2221 : int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2222 : struct drm_file *filp);
2223 : int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2224 : struct drm_file *filp);
2225 : int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2226 : struct drm_file *filp);
2227 : int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2228 : struct drm_file *file_priv);
2229 : int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2230 : struct drm_file *file_priv);
2231 : int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2232 : struct drm_file *file_priv);
2233 : int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2234 : struct drm_file *file_priv);
2235 : int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2236 : struct drm_file *filp);
2237 : int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2238 : struct drm_file *filp);
2239 : int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2240 : struct drm_file *filp);
2241 : int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2242 : struct drm_file *filp);
2243 : int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2244 : struct drm_file *filp);
2245 : int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2246 : struct drm_file *filp);
2247 : int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2248 : int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2249 : struct drm_file *filp);
2250 : int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2251 : struct drm_file *filp);
2252 :
2253 : /* VRAM scratch page for HDP bug, default vram page */
2254 : struct r600_vram_scratch {
2255 : struct radeon_bo *robj;
2256 : volatile uint32_t *ptr;
2257 : u64 gpu_addr;
2258 : };
2259 :
2260 : /*
2261 : * ACPI
2262 : */
2263 : struct radeon_atif_notification_cfg {
2264 : bool enabled;
2265 : int command_code;
2266 : };
2267 :
2268 : struct radeon_atif_notifications {
2269 : bool display_switch;
2270 : bool expansion_mode_change;
2271 : bool thermal_state;
2272 : bool forced_power_state;
2273 : bool system_power_state;
2274 : bool display_conf_change;
2275 : bool px_gfx_switch;
2276 : bool brightness_change;
2277 : bool dgpu_display_event;
2278 : };
2279 :
2280 : struct radeon_atif_functions {
2281 : bool system_params;
2282 : bool sbios_requests;
2283 : bool select_active_disp;
2284 : bool lid_state;
2285 : bool get_tv_standard;
2286 : bool set_tv_standard;
2287 : bool get_panel_expansion_mode;
2288 : bool set_panel_expansion_mode;
2289 : bool temperature_change;
2290 : bool graphics_device_types;
2291 : };
2292 :
2293 : struct radeon_atif {
2294 : struct radeon_atif_notifications notifications;
2295 : struct radeon_atif_functions functions;
2296 : struct radeon_atif_notification_cfg notification_cfg;
2297 : struct radeon_encoder *encoder_for_bl;
2298 : };
2299 :
2300 : struct radeon_atcs_functions {
2301 : bool get_ext_state;
2302 : bool pcie_perf_req;
2303 : bool pcie_dev_rdy;
2304 : bool pcie_bus_width;
2305 : };
2306 :
2307 : struct radeon_atcs {
2308 : struct radeon_atcs_functions functions;
2309 : };
2310 :
2311 : /*
2312 : * Core structure, functions and helpers.
2313 : */
2314 : typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2315 : typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2316 :
2317 : struct radeon_device {
2318 : struct device self;
2319 : struct device *dev;
2320 : struct drm_device *ddev;
2321 : struct pci_dev *pdev;
2322 : struct rwlock exclusive_lock;
2323 :
2324 : pci_chipset_tag_t pc;
2325 : pcitag_t pa_tag;
2326 : pci_intr_handle_t intrh;
2327 : bus_space_tag_t iot;
2328 : bus_space_tag_t memt;
2329 : bus_dma_tag_t dmat;
2330 : void *irqh;
2331 :
2332 : void (*switchcb)(void *, int, int);
2333 : void *switchcbarg;
2334 : void *switchcookie;
2335 : struct task switchtask;
2336 : struct rasops_info ro;
2337 : int console;
2338 :
2339 : struct task burner_task;
2340 : int burner_fblank;
2341 :
2342 : #ifdef __sparc64__
2343 : struct sunfb sf;
2344 : bus_size_t fb_offset;
2345 : bus_space_handle_t memh;
2346 : #endif
2347 :
2348 : unsigned long fb_aper_offset;
2349 : unsigned long fb_aper_size;
2350 :
2351 : /* ASIC */
2352 : union radeon_asic_config config;
2353 : enum radeon_family family;
2354 : unsigned long flags;
2355 : int usec_timeout;
2356 : enum radeon_pll_errata pll_errata;
2357 : int num_gb_pipes;
2358 : int num_z_pipes;
2359 : int disp_priority;
2360 : /* BIOS */
2361 : uint8_t *bios;
2362 : bool is_atom_bios;
2363 : uint16_t bios_header_start;
2364 : struct radeon_bo *stollen_vga_memory;
2365 : /* Register mmio */
2366 : resource_size_t rmmio_base;
2367 : resource_size_t rmmio_size;
2368 : /* protects concurrent MM_INDEX/DATA based register access */
2369 : spinlock_t mmio_idx_lock;
2370 : /* protects concurrent SMC based register access */
2371 : spinlock_t smc_idx_lock;
2372 : /* protects concurrent PLL register access */
2373 : spinlock_t pll_idx_lock;
2374 : /* protects concurrent MC register access */
2375 : spinlock_t mc_idx_lock;
2376 : /* protects concurrent PCIE register access */
2377 : spinlock_t pcie_idx_lock;
2378 : /* protects concurrent PCIE_PORT register access */
2379 : spinlock_t pciep_idx_lock;
2380 : /* protects concurrent PIF register access */
2381 : spinlock_t pif_idx_lock;
2382 : /* protects concurrent CG register access */
2383 : spinlock_t cg_idx_lock;
2384 : /* protects concurrent UVD register access */
2385 : spinlock_t uvd_idx_lock;
2386 : /* protects concurrent RCU register access */
2387 : spinlock_t rcu_idx_lock;
2388 : /* protects concurrent DIDT register access */
2389 : spinlock_t didt_idx_lock;
2390 : /* protects concurrent ENDPOINT (audio) register access */
2391 : spinlock_t end_idx_lock;
2392 : bus_space_handle_t rmmio_bsh;
2393 : radeon_rreg_t mc_rreg;
2394 : radeon_wreg_t mc_wreg;
2395 : radeon_rreg_t pll_rreg;
2396 : radeon_wreg_t pll_wreg;
2397 : uint32_t pcie_reg_mask;
2398 : radeon_rreg_t pciep_rreg;
2399 : radeon_wreg_t pciep_wreg;
2400 : /* io port */
2401 : bus_space_handle_t rio_mem;
2402 : resource_size_t rio_mem_size;
2403 : struct radeon_clock clock;
2404 : struct radeon_mc mc;
2405 : struct radeon_gart gart;
2406 : struct radeon_mode_info mode_info;
2407 : struct radeon_scratch scratch;
2408 : struct radeon_doorbell doorbell;
2409 : struct radeon_mman mman;
2410 : struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2411 : wait_queue_head_t fence_queue;
2412 : unsigned fence_context;
2413 : struct rwlock ring_lock;
2414 : struct radeon_ring ring[RADEON_NUM_RINGS];
2415 : bool ib_pool_ready;
2416 : struct radeon_sa_manager ring_tmp_bo;
2417 : struct radeon_irq irq;
2418 : struct radeon_asic *asic;
2419 : struct radeon_gem gem;
2420 : struct radeon_pm pm;
2421 : struct radeon_uvd uvd;
2422 : struct radeon_vce vce;
2423 : uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2424 : struct radeon_wb wb;
2425 : struct radeon_dummy_page dummy_page;
2426 : bool shutdown;
2427 : bool suspend;
2428 : bool need_dma32;
2429 : bool accel_working;
2430 : bool fastfb_working; /* IGP feature*/
2431 : bool needs_reset, in_reset;
2432 : struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2433 : const struct firmware *me_fw; /* all family ME firmware */
2434 : const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2435 : const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2436 : const struct firmware *mc_fw; /* NI MC firmware */
2437 : const struct firmware *ce_fw; /* SI CE firmware */
2438 : const struct firmware *mec_fw; /* CIK MEC firmware */
2439 : const struct firmware *mec2_fw; /* KV MEC2 firmware */
2440 : const struct firmware *sdma_fw; /* CIK SDMA firmware */
2441 : const struct firmware *smc_fw; /* SMC firmware */
2442 : const struct firmware *uvd_fw; /* UVD firmware */
2443 : const struct firmware *vce_fw; /* VCE firmware */
2444 : bool new_fw;
2445 : struct r600_vram_scratch vram_scratch;
2446 : int msi_enabled; /* msi enabled */
2447 : struct r600_ih ih; /* r6/700 interrupt ring */
2448 : struct radeon_rlc rlc;
2449 : struct radeon_mec mec;
2450 : struct delayed_work hotplug_work;
2451 : struct work_struct dp_work;
2452 : struct work_struct audio_work;
2453 : int num_crtc; /* number of crtcs */
2454 : struct rwlock dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2455 : bool has_uvd;
2456 : struct r600_audio audio; /* audio stuff */
2457 : struct notifier_block acpi_nb;
2458 : /* only one userspace can use Hyperz features or CMASK at a time */
2459 : struct drm_file *hyperz_filp;
2460 : struct drm_file *cmask_filp;
2461 : /* i2c buses */
2462 : struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2463 : /* debugfs */
2464 : struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2465 : unsigned debugfs_count;
2466 : /* virtual memory */
2467 : struct radeon_vm_manager vm_manager;
2468 : struct rwlock gpu_clock_mutex;
2469 : /* memory stats */
2470 : atomic64_t vram_usage;
2471 : atomic64_t gtt_usage;
2472 : atomic64_t num_bytes_moved;
2473 : atomic_t gpu_reset_counter;
2474 : /* ACPI interface */
2475 : struct radeon_atif atif;
2476 : struct radeon_atcs atcs;
2477 : /* srbm instance registers */
2478 : struct rwlock srbm_mutex;
2479 : /* GRBM index mutex. Protects concurrents access to GRBM index */
2480 : struct rwlock grbm_idx_mutex;
2481 : /* clock, powergating flags */
2482 : u32 cg_flags;
2483 : u32 pg_flags;
2484 :
2485 : #ifdef __linux__
2486 : struct dev_pm_domain vga_pm_domain;
2487 : #endif
2488 : bool have_disp_power_ref;
2489 : u32 px_quirk_flags;
2490 :
2491 : /* tracking pinned memory */
2492 : u64 vram_pin_size;
2493 : u64 gart_pin_size;
2494 :
2495 : /* amdkfd interface */
2496 : struct kfd_dev *kfd;
2497 :
2498 : struct rwlock mn_lock;
2499 : DECLARE_HASHTABLE(mn_hash, 7);
2500 : };
2501 :
2502 : bool radeon_is_px(struct drm_device *dev);
2503 : int radeon_device_init(struct radeon_device *rdev,
2504 : struct drm_device *ddev,
2505 : struct pci_dev *pdev,
2506 : uint32_t flags);
2507 : void radeon_device_fini(struct radeon_device *rdev);
2508 : int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2509 :
2510 : #define RADEON_MIN_MMIO_SIZE 0x10000
2511 :
2512 : uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2513 : void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2514 0 : static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2515 : bool always_indirect)
2516 : {
2517 : /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2518 0 : if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2519 0 : return bus_space_read_4(rdev->memt, rdev->rmmio_bsh, reg);
2520 : else
2521 0 : return r100_mm_rreg_slow(rdev, reg);
2522 0 : }
2523 0 : static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2524 : bool always_indirect)
2525 : {
2526 0 : if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2527 0 : bus_space_write_4(rdev->memt, rdev->rmmio_bsh, reg, v);
2528 : else
2529 0 : r100_mm_wreg_slow(rdev, reg, v);
2530 0 : }
2531 :
2532 : u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2533 : void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2534 :
2535 : u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2536 : void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2537 :
2538 : /*
2539 : * Cast helper
2540 : */
2541 : extern const struct fence_ops radeon_fence_ops;
2542 :
2543 0 : static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2544 : {
2545 0 : struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2546 :
2547 0 : if (__f->base.ops == &radeon_fence_ops)
2548 0 : return __f;
2549 :
2550 0 : return NULL;
2551 0 : }
2552 :
2553 : /*
2554 : * Registers read & write functions.
2555 : */
2556 : #define RREG8(reg) \
2557 : bus_space_read_1(rdev->memt, rdev->rmmio_bsh, (reg))
2558 : #define WREG8(reg, v) \
2559 : bus_space_write_1(rdev->memt, rdev->rmmio_bsh, (reg), (v))
2560 : #define RREG16(reg) \
2561 : bus_space_read_2(rdev->memt, rdev->rmmio_bsh, (reg))
2562 : #define WREG16(reg, v) \
2563 : bus_space_write_2(rdev->memt, rdev->rmmio_bsh, (reg), (v))
2564 : #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2565 : #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2566 : #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2567 : #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2568 : #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2569 : #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2570 : #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2571 : #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2572 : #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2573 : #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2574 : #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2575 : #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2576 : #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2577 : #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2578 : #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2579 : #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2580 : #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2581 : #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2582 : #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2583 : #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2584 : #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2585 : #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2586 : #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2587 : #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2588 : #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2589 : #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2590 : #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2591 : #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2592 : #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2593 : #define WREG32_P(reg, val, mask) \
2594 : do { \
2595 : uint32_t tmp_ = RREG32(reg); \
2596 : tmp_ &= (mask); \
2597 : tmp_ |= ((val) & ~(mask)); \
2598 : WREG32(reg, tmp_); \
2599 : } while (0)
2600 : #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2601 : #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2602 : #define WREG32_PLL_P(reg, val, mask) \
2603 : do { \
2604 : uint32_t tmp_ = RREG32_PLL(reg); \
2605 : tmp_ &= (mask); \
2606 : tmp_ |= ((val) & ~(mask)); \
2607 : WREG32_PLL(reg, tmp_); \
2608 : } while (0)
2609 : #define WREG32_SMC_P(reg, val, mask) \
2610 : do { \
2611 : uint32_t tmp_ = RREG32_SMC(reg); \
2612 : tmp_ &= (mask); \
2613 : tmp_ |= ((val) & ~(mask)); \
2614 : WREG32_SMC(reg, tmp_); \
2615 : } while (0)
2616 : #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2617 : #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2618 : #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2619 :
2620 : #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2621 : #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2622 :
2623 : /*
2624 : * Indirect registers accessors.
2625 : * They used to be inlined, but this increases code size by ~65 kbytes.
2626 : * Since each performs a pair of MMIO ops
2627 : * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2628 : * the cost of call+ret is almost negligible. MMIO and locking
2629 : * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2630 : */
2631 : uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2632 : void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2633 : u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2634 : void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2635 : u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2636 : void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2637 : u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2638 : void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2639 : u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2640 : void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2641 : u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2642 : void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2643 : u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2644 : void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2645 : u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2646 : void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2647 :
2648 : void r100_pll_errata_after_index(struct radeon_device *rdev);
2649 :
2650 :
2651 : /*
2652 : * ASICs helpers.
2653 : */
2654 : #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2655 : (rdev->pdev->device == 0x5969))
2656 : #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2657 : (rdev->family == CHIP_RV200) || \
2658 : (rdev->family == CHIP_RS100) || \
2659 : (rdev->family == CHIP_RS200) || \
2660 : (rdev->family == CHIP_RV250) || \
2661 : (rdev->family == CHIP_RV280) || \
2662 : (rdev->family == CHIP_RS300))
2663 : #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2664 : (rdev->family == CHIP_RV350) || \
2665 : (rdev->family == CHIP_R350) || \
2666 : (rdev->family == CHIP_RV380) || \
2667 : (rdev->family == CHIP_R420) || \
2668 : (rdev->family == CHIP_R423) || \
2669 : (rdev->family == CHIP_RV410) || \
2670 : (rdev->family == CHIP_RS400) || \
2671 : (rdev->family == CHIP_RS480))
2672 : #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2673 : (rdev->ddev->pdev->device == 0x9443) || \
2674 : (rdev->ddev->pdev->device == 0x944B) || \
2675 : (rdev->ddev->pdev->device == 0x9506) || \
2676 : (rdev->ddev->pdev->device == 0x9509) || \
2677 : (rdev->ddev->pdev->device == 0x950F) || \
2678 : (rdev->ddev->pdev->device == 0x689C) || \
2679 : (rdev->ddev->pdev->device == 0x689D))
2680 : #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2681 : #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2682 : (rdev->family == CHIP_RS690) || \
2683 : (rdev->family == CHIP_RS740) || \
2684 : (rdev->family >= CHIP_R600))
2685 : #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2686 : #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2687 : #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2688 : #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2689 : (rdev->flags & RADEON_IS_IGP))
2690 : #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2691 : #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2692 : #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2693 : (rdev->flags & RADEON_IS_IGP))
2694 : #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2695 : #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2696 : #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2697 : #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2698 : #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2699 : #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2700 : (rdev->family == CHIP_MULLINS))
2701 :
2702 : #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2703 : (rdev->ddev->pdev->device == 0x6850) || \
2704 : (rdev->ddev->pdev->device == 0x6858) || \
2705 : (rdev->ddev->pdev->device == 0x6859) || \
2706 : (rdev->ddev->pdev->device == 0x6840) || \
2707 : (rdev->ddev->pdev->device == 0x6841) || \
2708 : (rdev->ddev->pdev->device == 0x6842) || \
2709 : (rdev->ddev->pdev->device == 0x6843))
2710 :
2711 : /*
2712 : * BIOS helpers.
2713 : */
2714 : #define RBIOS8(i) (rdev->bios[i])
2715 : #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2716 : #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2717 :
2718 : int radeon_combios_init(struct radeon_device *rdev);
2719 : void radeon_combios_fini(struct radeon_device *rdev);
2720 : int radeon_atombios_init(struct radeon_device *rdev);
2721 : void radeon_atombios_fini(struct radeon_device *rdev);
2722 :
2723 :
2724 : /*
2725 : * RING helpers.
2726 : */
2727 :
2728 : /**
2729 : * radeon_ring_write - write a value to the ring
2730 : *
2731 : * @ring: radeon_ring structure holding ring information
2732 : * @v: dword (dw) value to write
2733 : *
2734 : * Write a value to the requested ring buffer (all asics).
2735 : */
2736 0 : static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2737 : {
2738 0 : if (ring->count_dw <= 0)
2739 0 : DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2740 :
2741 0 : ring->ring[ring->wptr++] = v;
2742 0 : ring->wptr &= ring->ptr_mask;
2743 0 : ring->count_dw--;
2744 0 : ring->ring_free_dw--;
2745 0 : }
2746 :
2747 : /*
2748 : * ASICs macro.
2749 : */
2750 : #define radeon_init(rdev) (rdev)->asic->init((rdev))
2751 : #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2752 : #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2753 : #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2754 : #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2755 : #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2756 : #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2757 : #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2758 : #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2759 : #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2760 : #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2761 : #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2762 : #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2763 : #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2764 : #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2765 : #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2766 : #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2767 : #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2768 : #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2769 : #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2770 : #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2771 : #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2772 : #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2773 : #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2774 : #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2775 : #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2776 : #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2777 : #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2778 : #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2779 : #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2780 : #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2781 : #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2782 : #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2783 : #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2784 : #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2785 : #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2786 : #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2787 : #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2788 : #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2789 : #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2790 : #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2791 : #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2792 : #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2793 : #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2794 : #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2795 : #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2796 : #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2797 : #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2798 : #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2799 : #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2800 : #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2801 : #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2802 : #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2803 : #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2804 : #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2805 : #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2806 : #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2807 : #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2808 : #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2809 : #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2810 : #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2811 : #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2812 : #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2813 : #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2814 : #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2815 : #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2816 : #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2817 : #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2818 : #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2819 : #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2820 : #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2821 : #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2822 : #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2823 : #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2824 : #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2825 : #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2826 : #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2827 : #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2828 : #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2829 : #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2830 : #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2831 : #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2832 : #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2833 : #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2834 : #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2835 : #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2836 : #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2837 : #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2838 : #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2839 : #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2840 : #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2841 :
2842 : /* Common functions */
2843 : /* AGP */
2844 : extern int radeon_gpu_reset(struct radeon_device *rdev);
2845 : extern void radeon_pci_config_reset(struct radeon_device *rdev);
2846 : extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2847 : extern void radeon_agp_disable(struct radeon_device *rdev);
2848 : extern int radeon_modeset_init(struct radeon_device *rdev);
2849 : extern void radeon_modeset_fini(struct radeon_device *rdev);
2850 : extern bool radeon_card_posted(struct radeon_device *rdev);
2851 : extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2852 : extern void radeon_update_display_priority(struct radeon_device *rdev);
2853 : extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2854 : extern void radeon_scratch_init(struct radeon_device *rdev);
2855 : extern void radeon_wb_fini(struct radeon_device *rdev);
2856 : extern int radeon_wb_init(struct radeon_device *rdev);
2857 : extern void radeon_wb_disable(struct radeon_device *rdev);
2858 : extern void radeon_surface_init(struct radeon_device *rdev);
2859 : extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2860 : extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2861 : extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2862 : extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2863 : extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2864 : extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2865 : uint32_t flags);
2866 : extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2867 : extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2868 : extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2869 : extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2870 : extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2871 : extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2872 : extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2873 : extern void radeon_program_register_sequence(struct radeon_device *rdev,
2874 : const u32 *registers,
2875 : const u32 array_size);
2876 :
2877 : /*
2878 : * vm
2879 : */
2880 : int radeon_vm_manager_init(struct radeon_device *rdev);
2881 : void radeon_vm_manager_fini(struct radeon_device *rdev);
2882 : int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2883 : void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2884 : struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2885 : struct radeon_vm *vm,
2886 : struct list_head *head);
2887 : struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2888 : struct radeon_vm *vm, int ring);
2889 : void radeon_vm_flush(struct radeon_device *rdev,
2890 : struct radeon_vm *vm,
2891 : int ring, struct radeon_fence *fence);
2892 : void radeon_vm_fence(struct radeon_device *rdev,
2893 : struct radeon_vm *vm,
2894 : struct radeon_fence *fence);
2895 : uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2896 : int radeon_vm_update_page_directory(struct radeon_device *rdev,
2897 : struct radeon_vm *vm);
2898 : int radeon_vm_clear_freed(struct radeon_device *rdev,
2899 : struct radeon_vm *vm);
2900 : int radeon_vm_clear_invalids(struct radeon_device *rdev,
2901 : struct radeon_vm *vm);
2902 : int radeon_vm_bo_update(struct radeon_device *rdev,
2903 : struct radeon_bo_va *bo_va,
2904 : struct ttm_mem_reg *mem);
2905 : void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2906 : struct radeon_bo *bo);
2907 : struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2908 : struct radeon_bo *bo);
2909 : struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2910 : struct radeon_vm *vm,
2911 : struct radeon_bo *bo);
2912 : int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2913 : struct radeon_bo_va *bo_va,
2914 : uint64_t offset,
2915 : uint32_t flags);
2916 : void radeon_vm_bo_rmv(struct radeon_device *rdev,
2917 : struct radeon_bo_va *bo_va);
2918 :
2919 : /* audio */
2920 : void r600_audio_update_hdmi(struct work_struct *work);
2921 : struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2922 : struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2923 : void r600_audio_enable(struct radeon_device *rdev,
2924 : struct r600_audio_pin *pin,
2925 : u8 enable_mask);
2926 : void dce6_audio_enable(struct radeon_device *rdev,
2927 : struct r600_audio_pin *pin,
2928 : u8 enable_mask);
2929 :
2930 : /*
2931 : * R600 vram scratch functions
2932 : */
2933 : int r600_vram_scratch_init(struct radeon_device *rdev);
2934 : void r600_vram_scratch_fini(struct radeon_device *rdev);
2935 :
2936 : /*
2937 : * r600 cs checking helper
2938 : */
2939 : unsigned r600_mip_minify(unsigned size, unsigned level);
2940 : bool r600_fmt_is_valid_color(u32 format);
2941 : bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2942 : int r600_fmt_get_blocksize(u32 format);
2943 : int r600_fmt_get_nblocksx(u32 format, u32 w);
2944 : int r600_fmt_get_nblocksy(u32 format, u32 h);
2945 :
2946 : /*
2947 : * r600 functions used by radeon_encoder.c
2948 : */
2949 : struct radeon_hdmi_acr {
2950 : u32 clock;
2951 :
2952 : int n_32khz;
2953 : int cts_32khz;
2954 :
2955 : int n_44_1khz;
2956 : int cts_44_1khz;
2957 :
2958 : int n_48khz;
2959 : int cts_48khz;
2960 :
2961 : };
2962 :
2963 : extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2964 :
2965 : extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2966 : u32 tiling_pipe_num,
2967 : u32 max_rb_num,
2968 : u32 total_max_rb_num,
2969 : u32 enabled_rb_mask);
2970 :
2971 : /*
2972 : * evergreen functions used by radeon_encoder.c
2973 : */
2974 :
2975 : extern int ni_init_microcode(struct radeon_device *rdev);
2976 : extern int ni_mc_load_microcode(struct radeon_device *rdev);
2977 :
2978 : /* radeon_acpi.c */
2979 : #if defined(CONFIG_ACPI)
2980 : extern int radeon_acpi_init(struct radeon_device *rdev);
2981 : extern void radeon_acpi_fini(struct radeon_device *rdev);
2982 : extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2983 : extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2984 : u8 perf_req, bool advertise);
2985 : extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2986 : #else
2987 0 : static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2988 0 : static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2989 : #endif
2990 :
2991 : int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2992 : struct radeon_cs_packet *pkt,
2993 : unsigned idx);
2994 : bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2995 : void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2996 : struct radeon_cs_packet *pkt);
2997 : int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2998 : struct radeon_bo_list **cs_reloc,
2999 : int nomm);
3000 : int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3001 : uint32_t *vline_start_end,
3002 : uint32_t *vline_status);
3003 :
3004 : #include "radeon_object.h"
3005 :
3006 : #endif
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