Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 :
29 : #include <dev/pci/drm/drmP.h>
30 : #include <dev/pci/drm/drm_crtc_helper.h>
31 : #include <dev/pci/drm/radeon_drm.h>
32 : #include "radeon_reg.h"
33 : #include "radeon.h"
34 : #include "radeon_asic.h"
35 : #include "atom.h"
36 :
37 : /*
38 : * Registers accessors functions.
39 : */
40 : /**
41 : * radeon_invalid_rreg - dummy reg read function
42 : *
43 : * @rdev: radeon device pointer
44 : * @reg: offset of register
45 : *
46 : * Dummy register read function. Used for register blocks
47 : * that certain asics don't have (all asics).
48 : * Returns the value in the register.
49 : */
50 0 : static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
51 : {
52 0 : DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
53 0 : BUG_ON(1);
54 : return 0;
55 : }
56 :
57 : /**
58 : * radeon_invalid_wreg - dummy reg write function
59 : *
60 : * @rdev: radeon device pointer
61 : * @reg: offset of register
62 : * @v: value to write to the register
63 : *
64 : * Dummy register read function. Used for register blocks
65 : * that certain asics don't have (all asics).
66 : */
67 0 : static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
68 : {
69 0 : DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
70 : reg, v);
71 0 : BUG_ON(1);
72 : }
73 :
74 : /**
75 : * radeon_register_accessor_init - sets up the register accessor callbacks
76 : *
77 : * @rdev: radeon device pointer
78 : *
79 : * Sets up the register accessor callbacks for various register
80 : * apertures. Not all asics have all apertures (all asics).
81 : */
82 0 : static void radeon_register_accessor_init(struct radeon_device *rdev)
83 : {
84 0 : rdev->mc_rreg = &radeon_invalid_rreg;
85 0 : rdev->mc_wreg = &radeon_invalid_wreg;
86 0 : rdev->pll_rreg = &radeon_invalid_rreg;
87 0 : rdev->pll_wreg = &radeon_invalid_wreg;
88 0 : rdev->pciep_rreg = &radeon_invalid_rreg;
89 0 : rdev->pciep_wreg = &radeon_invalid_wreg;
90 :
91 : /* Don't change order as we are overridding accessor. */
92 0 : if (rdev->family < CHIP_RV515) {
93 0 : rdev->pcie_reg_mask = 0xff;
94 0 : } else {
95 0 : rdev->pcie_reg_mask = 0x7ff;
96 : }
97 : /* FIXME: not sure here */
98 0 : if (rdev->family <= CHIP_R580) {
99 0 : rdev->pll_rreg = &r100_pll_rreg;
100 0 : rdev->pll_wreg = &r100_pll_wreg;
101 0 : }
102 0 : if (rdev->family >= CHIP_R420) {
103 0 : rdev->mc_rreg = &r420_mc_rreg;
104 0 : rdev->mc_wreg = &r420_mc_wreg;
105 0 : }
106 0 : if (rdev->family >= CHIP_RV515) {
107 0 : rdev->mc_rreg = &rv515_mc_rreg;
108 0 : rdev->mc_wreg = &rv515_mc_wreg;
109 0 : }
110 0 : if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
111 0 : rdev->mc_rreg = &rs400_mc_rreg;
112 0 : rdev->mc_wreg = &rs400_mc_wreg;
113 0 : }
114 0 : if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
115 0 : rdev->mc_rreg = &rs690_mc_rreg;
116 0 : rdev->mc_wreg = &rs690_mc_wreg;
117 0 : }
118 0 : if (rdev->family == CHIP_RS600) {
119 0 : rdev->mc_rreg = &rs600_mc_rreg;
120 0 : rdev->mc_wreg = &rs600_mc_wreg;
121 0 : }
122 0 : if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
123 0 : rdev->mc_rreg = &rs780_mc_rreg;
124 0 : rdev->mc_wreg = &rs780_mc_wreg;
125 0 : }
126 :
127 0 : if (rdev->family >= CHIP_BONAIRE) {
128 0 : rdev->pciep_rreg = &cik_pciep_rreg;
129 0 : rdev->pciep_wreg = &cik_pciep_wreg;
130 0 : } else if (rdev->family >= CHIP_R600) {
131 0 : rdev->pciep_rreg = &r600_pciep_rreg;
132 0 : rdev->pciep_wreg = &r600_pciep_wreg;
133 0 : }
134 0 : }
135 :
136 0 : static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
137 : u32 reg, u32 *val)
138 : {
139 0 : return -EINVAL;
140 : }
141 :
142 : /* helper to disable agp */
143 : /**
144 : * radeon_agp_disable - AGP disable helper function
145 : *
146 : * @rdev: radeon device pointer
147 : *
148 : * Removes AGP flags and changes the gart callbacks on AGP
149 : * cards when using the internal gart rather than AGP (all asics).
150 : */
151 0 : void radeon_agp_disable(struct radeon_device *rdev)
152 : {
153 0 : rdev->flags &= ~RADEON_IS_AGP;
154 0 : if (rdev->family >= CHIP_R600) {
155 : DRM_INFO("Forcing AGP to PCIE mode\n");
156 0 : rdev->flags |= RADEON_IS_PCIE;
157 0 : } else if (rdev->family >= CHIP_RV515 ||
158 0 : rdev->family == CHIP_RV380 ||
159 0 : rdev->family == CHIP_RV410 ||
160 0 : rdev->family == CHIP_R423) {
161 : DRM_INFO("Forcing AGP to PCIE mode\n");
162 0 : rdev->flags |= RADEON_IS_PCIE;
163 0 : rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
164 0 : rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
165 0 : rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
166 0 : } else {
167 : DRM_INFO("Forcing AGP to PCI mode\n");
168 0 : rdev->flags |= RADEON_IS_PCI;
169 0 : rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
170 0 : rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
171 0 : rdev->asic->gart.set_page = &r100_pci_gart_set_page;
172 : }
173 0 : rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
174 0 : }
175 :
176 : /*
177 : * ASIC
178 : */
179 :
180 : static struct radeon_asic_ring r100_gfx_ring = {
181 : .ib_execute = &r100_ring_ib_execute,
182 : .emit_fence = &r100_fence_ring_emit,
183 : .emit_semaphore = &r100_semaphore_ring_emit,
184 : .cs_parse = &r100_cs_parse,
185 : .ring_start = &r100_ring_start,
186 : .ring_test = &r100_ring_test,
187 : .ib_test = &r100_ib_test,
188 : .is_lockup = &r100_gpu_is_lockup,
189 : .get_rptr = &r100_gfx_get_rptr,
190 : .get_wptr = &r100_gfx_get_wptr,
191 : .set_wptr = &r100_gfx_set_wptr,
192 : };
193 :
194 : static struct radeon_asic r100_asic = {
195 : .init = &r100_init,
196 : .fini = &r100_fini,
197 : .suspend = &r100_suspend,
198 : .resume = &r100_resume,
199 : .vga_set_state = &r100_vga_set_state,
200 : .asic_reset = &r100_asic_reset,
201 : .mmio_hdp_flush = NULL,
202 : .gui_idle = &r100_gui_idle,
203 : .mc_wait_for_idle = &r100_mc_wait_for_idle,
204 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
205 : .gart = {
206 : .tlb_flush = &r100_pci_gart_tlb_flush,
207 : .get_page_entry = &r100_pci_gart_get_page_entry,
208 : .set_page = &r100_pci_gart_set_page,
209 : },
210 : .ring = {
211 : [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
212 : },
213 : .irq = {
214 : .set = &r100_irq_set,
215 : .process = &r100_irq_process,
216 : },
217 : .display = {
218 : .bandwidth_update = &r100_bandwidth_update,
219 : .get_vblank_counter = &r100_get_vblank_counter,
220 : .wait_for_vblank = &r100_wait_for_vblank,
221 : .set_backlight_level = &radeon_legacy_set_backlight_level,
222 : .get_backlight_level = &radeon_legacy_get_backlight_level,
223 : },
224 : .copy = {
225 : .blit = &r100_copy_blit,
226 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
227 : .dma = NULL,
228 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
229 : .copy = &r100_copy_blit,
230 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
231 : },
232 : .surface = {
233 : .set_reg = r100_set_surface_reg,
234 : .clear_reg = r100_clear_surface_reg,
235 : },
236 : .hpd = {
237 : .init = &r100_hpd_init,
238 : .fini = &r100_hpd_fini,
239 : .sense = &r100_hpd_sense,
240 : .set_polarity = &r100_hpd_set_polarity,
241 : },
242 : .pm = {
243 : .misc = &r100_pm_misc,
244 : .prepare = &r100_pm_prepare,
245 : .finish = &r100_pm_finish,
246 : .init_profile = &r100_pm_init_profile,
247 : .get_dynpm_state = &r100_pm_get_dynpm_state,
248 : .get_engine_clock = &radeon_legacy_get_engine_clock,
249 : .set_engine_clock = &radeon_legacy_set_engine_clock,
250 : .get_memory_clock = &radeon_legacy_get_memory_clock,
251 : .set_memory_clock = NULL,
252 : .get_pcie_lanes = NULL,
253 : .set_pcie_lanes = NULL,
254 : .set_clock_gating = &radeon_legacy_set_clock_gating,
255 : },
256 : .pflip = {
257 : .page_flip = &r100_page_flip,
258 : .page_flip_pending = &r100_page_flip_pending,
259 : },
260 : };
261 :
262 : static struct radeon_asic r200_asic = {
263 : .init = &r100_init,
264 : .fini = &r100_fini,
265 : .suspend = &r100_suspend,
266 : .resume = &r100_resume,
267 : .vga_set_state = &r100_vga_set_state,
268 : .asic_reset = &r100_asic_reset,
269 : .mmio_hdp_flush = NULL,
270 : .gui_idle = &r100_gui_idle,
271 : .mc_wait_for_idle = &r100_mc_wait_for_idle,
272 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
273 : .gart = {
274 : .tlb_flush = &r100_pci_gart_tlb_flush,
275 : .get_page_entry = &r100_pci_gart_get_page_entry,
276 : .set_page = &r100_pci_gart_set_page,
277 : },
278 : .ring = {
279 : [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
280 : },
281 : .irq = {
282 : .set = &r100_irq_set,
283 : .process = &r100_irq_process,
284 : },
285 : .display = {
286 : .bandwidth_update = &r100_bandwidth_update,
287 : .get_vblank_counter = &r100_get_vblank_counter,
288 : .wait_for_vblank = &r100_wait_for_vblank,
289 : .set_backlight_level = &radeon_legacy_set_backlight_level,
290 : .get_backlight_level = &radeon_legacy_get_backlight_level,
291 : },
292 : .copy = {
293 : .blit = &r100_copy_blit,
294 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
295 : .dma = &r200_copy_dma,
296 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297 : .copy = &r100_copy_blit,
298 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299 : },
300 : .surface = {
301 : .set_reg = r100_set_surface_reg,
302 : .clear_reg = r100_clear_surface_reg,
303 : },
304 : .hpd = {
305 : .init = &r100_hpd_init,
306 : .fini = &r100_hpd_fini,
307 : .sense = &r100_hpd_sense,
308 : .set_polarity = &r100_hpd_set_polarity,
309 : },
310 : .pm = {
311 : .misc = &r100_pm_misc,
312 : .prepare = &r100_pm_prepare,
313 : .finish = &r100_pm_finish,
314 : .init_profile = &r100_pm_init_profile,
315 : .get_dynpm_state = &r100_pm_get_dynpm_state,
316 : .get_engine_clock = &radeon_legacy_get_engine_clock,
317 : .set_engine_clock = &radeon_legacy_set_engine_clock,
318 : .get_memory_clock = &radeon_legacy_get_memory_clock,
319 : .set_memory_clock = NULL,
320 : .get_pcie_lanes = NULL,
321 : .set_pcie_lanes = NULL,
322 : .set_clock_gating = &radeon_legacy_set_clock_gating,
323 : },
324 : .pflip = {
325 : .page_flip = &r100_page_flip,
326 : .page_flip_pending = &r100_page_flip_pending,
327 : },
328 : };
329 :
330 : static struct radeon_asic_ring r300_gfx_ring = {
331 : .ib_execute = &r100_ring_ib_execute,
332 : .emit_fence = &r300_fence_ring_emit,
333 : .emit_semaphore = &r100_semaphore_ring_emit,
334 : .cs_parse = &r300_cs_parse,
335 : .ring_start = &r300_ring_start,
336 : .ring_test = &r100_ring_test,
337 : .ib_test = &r100_ib_test,
338 : .is_lockup = &r100_gpu_is_lockup,
339 : .get_rptr = &r100_gfx_get_rptr,
340 : .get_wptr = &r100_gfx_get_wptr,
341 : .set_wptr = &r100_gfx_set_wptr,
342 : };
343 :
344 : static struct radeon_asic_ring rv515_gfx_ring = {
345 : .ib_execute = &r100_ring_ib_execute,
346 : .emit_fence = &r300_fence_ring_emit,
347 : .emit_semaphore = &r100_semaphore_ring_emit,
348 : .cs_parse = &r300_cs_parse,
349 : .ring_start = &rv515_ring_start,
350 : .ring_test = &r100_ring_test,
351 : .ib_test = &r100_ib_test,
352 : .is_lockup = &r100_gpu_is_lockup,
353 : .get_rptr = &r100_gfx_get_rptr,
354 : .get_wptr = &r100_gfx_get_wptr,
355 : .set_wptr = &r100_gfx_set_wptr,
356 : };
357 :
358 : static struct radeon_asic r300_asic = {
359 : .init = &r300_init,
360 : .fini = &r300_fini,
361 : .suspend = &r300_suspend,
362 : .resume = &r300_resume,
363 : .vga_set_state = &r100_vga_set_state,
364 : .asic_reset = &r300_asic_reset,
365 : .mmio_hdp_flush = NULL,
366 : .gui_idle = &r100_gui_idle,
367 : .mc_wait_for_idle = &r300_mc_wait_for_idle,
368 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
369 : .gart = {
370 : .tlb_flush = &r100_pci_gart_tlb_flush,
371 : .get_page_entry = &r100_pci_gart_get_page_entry,
372 : .set_page = &r100_pci_gart_set_page,
373 : },
374 : .ring = {
375 : [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
376 : },
377 : .irq = {
378 : .set = &r100_irq_set,
379 : .process = &r100_irq_process,
380 : },
381 : .display = {
382 : .bandwidth_update = &r100_bandwidth_update,
383 : .get_vblank_counter = &r100_get_vblank_counter,
384 : .wait_for_vblank = &r100_wait_for_vblank,
385 : .set_backlight_level = &radeon_legacy_set_backlight_level,
386 : .get_backlight_level = &radeon_legacy_get_backlight_level,
387 : },
388 : .copy = {
389 : .blit = &r100_copy_blit,
390 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
391 : .dma = &r200_copy_dma,
392 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
393 : .copy = &r100_copy_blit,
394 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
395 : },
396 : .surface = {
397 : .set_reg = r100_set_surface_reg,
398 : .clear_reg = r100_clear_surface_reg,
399 : },
400 : .hpd = {
401 : .init = &r100_hpd_init,
402 : .fini = &r100_hpd_fini,
403 : .sense = &r100_hpd_sense,
404 : .set_polarity = &r100_hpd_set_polarity,
405 : },
406 : .pm = {
407 : .misc = &r100_pm_misc,
408 : .prepare = &r100_pm_prepare,
409 : .finish = &r100_pm_finish,
410 : .init_profile = &r100_pm_init_profile,
411 : .get_dynpm_state = &r100_pm_get_dynpm_state,
412 : .get_engine_clock = &radeon_legacy_get_engine_clock,
413 : .set_engine_clock = &radeon_legacy_set_engine_clock,
414 : .get_memory_clock = &radeon_legacy_get_memory_clock,
415 : .set_memory_clock = NULL,
416 : .get_pcie_lanes = &rv370_get_pcie_lanes,
417 : .set_pcie_lanes = &rv370_set_pcie_lanes,
418 : .set_clock_gating = &radeon_legacy_set_clock_gating,
419 : },
420 : .pflip = {
421 : .page_flip = &r100_page_flip,
422 : .page_flip_pending = &r100_page_flip_pending,
423 : },
424 : };
425 :
426 : static struct radeon_asic r300_asic_pcie = {
427 : .init = &r300_init,
428 : .fini = &r300_fini,
429 : .suspend = &r300_suspend,
430 : .resume = &r300_resume,
431 : .vga_set_state = &r100_vga_set_state,
432 : .asic_reset = &r300_asic_reset,
433 : .mmio_hdp_flush = NULL,
434 : .gui_idle = &r100_gui_idle,
435 : .mc_wait_for_idle = &r300_mc_wait_for_idle,
436 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
437 : .gart = {
438 : .tlb_flush = &rv370_pcie_gart_tlb_flush,
439 : .get_page_entry = &rv370_pcie_gart_get_page_entry,
440 : .set_page = &rv370_pcie_gart_set_page,
441 : },
442 : .ring = {
443 : [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
444 : },
445 : .irq = {
446 : .set = &r100_irq_set,
447 : .process = &r100_irq_process,
448 : },
449 : .display = {
450 : .bandwidth_update = &r100_bandwidth_update,
451 : .get_vblank_counter = &r100_get_vblank_counter,
452 : .wait_for_vblank = &r100_wait_for_vblank,
453 : .set_backlight_level = &radeon_legacy_set_backlight_level,
454 : .get_backlight_level = &radeon_legacy_get_backlight_level,
455 : },
456 : .copy = {
457 : .blit = &r100_copy_blit,
458 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
459 : .dma = &r200_copy_dma,
460 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
461 : .copy = &r100_copy_blit,
462 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
463 : },
464 : .surface = {
465 : .set_reg = r100_set_surface_reg,
466 : .clear_reg = r100_clear_surface_reg,
467 : },
468 : .hpd = {
469 : .init = &r100_hpd_init,
470 : .fini = &r100_hpd_fini,
471 : .sense = &r100_hpd_sense,
472 : .set_polarity = &r100_hpd_set_polarity,
473 : },
474 : .pm = {
475 : .misc = &r100_pm_misc,
476 : .prepare = &r100_pm_prepare,
477 : .finish = &r100_pm_finish,
478 : .init_profile = &r100_pm_init_profile,
479 : .get_dynpm_state = &r100_pm_get_dynpm_state,
480 : .get_engine_clock = &radeon_legacy_get_engine_clock,
481 : .set_engine_clock = &radeon_legacy_set_engine_clock,
482 : .get_memory_clock = &radeon_legacy_get_memory_clock,
483 : .set_memory_clock = NULL,
484 : .get_pcie_lanes = &rv370_get_pcie_lanes,
485 : .set_pcie_lanes = &rv370_set_pcie_lanes,
486 : .set_clock_gating = &radeon_legacy_set_clock_gating,
487 : },
488 : .pflip = {
489 : .page_flip = &r100_page_flip,
490 : .page_flip_pending = &r100_page_flip_pending,
491 : },
492 : };
493 :
494 : static struct radeon_asic r420_asic = {
495 : .init = &r420_init,
496 : .fini = &r420_fini,
497 : .suspend = &r420_suspend,
498 : .resume = &r420_resume,
499 : .vga_set_state = &r100_vga_set_state,
500 : .asic_reset = &r300_asic_reset,
501 : .mmio_hdp_flush = NULL,
502 : .gui_idle = &r100_gui_idle,
503 : .mc_wait_for_idle = &r300_mc_wait_for_idle,
504 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
505 : .gart = {
506 : .tlb_flush = &rv370_pcie_gart_tlb_flush,
507 : .get_page_entry = &rv370_pcie_gart_get_page_entry,
508 : .set_page = &rv370_pcie_gart_set_page,
509 : },
510 : .ring = {
511 : [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
512 : },
513 : .irq = {
514 : .set = &r100_irq_set,
515 : .process = &r100_irq_process,
516 : },
517 : .display = {
518 : .bandwidth_update = &r100_bandwidth_update,
519 : .get_vblank_counter = &r100_get_vblank_counter,
520 : .wait_for_vblank = &r100_wait_for_vblank,
521 : .set_backlight_level = &atombios_set_backlight_level,
522 : .get_backlight_level = &atombios_get_backlight_level,
523 : },
524 : .copy = {
525 : .blit = &r100_copy_blit,
526 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
527 : .dma = &r200_copy_dma,
528 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
529 : .copy = &r100_copy_blit,
530 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
531 : },
532 : .surface = {
533 : .set_reg = r100_set_surface_reg,
534 : .clear_reg = r100_clear_surface_reg,
535 : },
536 : .hpd = {
537 : .init = &r100_hpd_init,
538 : .fini = &r100_hpd_fini,
539 : .sense = &r100_hpd_sense,
540 : .set_polarity = &r100_hpd_set_polarity,
541 : },
542 : .pm = {
543 : .misc = &r100_pm_misc,
544 : .prepare = &r100_pm_prepare,
545 : .finish = &r100_pm_finish,
546 : .init_profile = &r420_pm_init_profile,
547 : .get_dynpm_state = &r100_pm_get_dynpm_state,
548 : .get_engine_clock = &radeon_atom_get_engine_clock,
549 : .set_engine_clock = &radeon_atom_set_engine_clock,
550 : .get_memory_clock = &radeon_atom_get_memory_clock,
551 : .set_memory_clock = &radeon_atom_set_memory_clock,
552 : .get_pcie_lanes = &rv370_get_pcie_lanes,
553 : .set_pcie_lanes = &rv370_set_pcie_lanes,
554 : .set_clock_gating = &radeon_atom_set_clock_gating,
555 : },
556 : .pflip = {
557 : .page_flip = &r100_page_flip,
558 : .page_flip_pending = &r100_page_flip_pending,
559 : },
560 : };
561 :
562 : static struct radeon_asic rs400_asic = {
563 : .init = &rs400_init,
564 : .fini = &rs400_fini,
565 : .suspend = &rs400_suspend,
566 : .resume = &rs400_resume,
567 : .vga_set_state = &r100_vga_set_state,
568 : .asic_reset = &r300_asic_reset,
569 : .mmio_hdp_flush = NULL,
570 : .gui_idle = &r100_gui_idle,
571 : .mc_wait_for_idle = &rs400_mc_wait_for_idle,
572 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
573 : .gart = {
574 : .tlb_flush = &rs400_gart_tlb_flush,
575 : .get_page_entry = &rs400_gart_get_page_entry,
576 : .set_page = &rs400_gart_set_page,
577 : },
578 : .ring = {
579 : [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
580 : },
581 : .irq = {
582 : .set = &r100_irq_set,
583 : .process = &r100_irq_process,
584 : },
585 : .display = {
586 : .bandwidth_update = &r100_bandwidth_update,
587 : .get_vblank_counter = &r100_get_vblank_counter,
588 : .wait_for_vblank = &r100_wait_for_vblank,
589 : .set_backlight_level = &radeon_legacy_set_backlight_level,
590 : .get_backlight_level = &radeon_legacy_get_backlight_level,
591 : },
592 : .copy = {
593 : .blit = &r100_copy_blit,
594 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
595 : .dma = &r200_copy_dma,
596 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
597 : .copy = &r100_copy_blit,
598 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
599 : },
600 : .surface = {
601 : .set_reg = r100_set_surface_reg,
602 : .clear_reg = r100_clear_surface_reg,
603 : },
604 : .hpd = {
605 : .init = &r100_hpd_init,
606 : .fini = &r100_hpd_fini,
607 : .sense = &r100_hpd_sense,
608 : .set_polarity = &r100_hpd_set_polarity,
609 : },
610 : .pm = {
611 : .misc = &r100_pm_misc,
612 : .prepare = &r100_pm_prepare,
613 : .finish = &r100_pm_finish,
614 : .init_profile = &r100_pm_init_profile,
615 : .get_dynpm_state = &r100_pm_get_dynpm_state,
616 : .get_engine_clock = &radeon_legacy_get_engine_clock,
617 : .set_engine_clock = &radeon_legacy_set_engine_clock,
618 : .get_memory_clock = &radeon_legacy_get_memory_clock,
619 : .set_memory_clock = NULL,
620 : .get_pcie_lanes = NULL,
621 : .set_pcie_lanes = NULL,
622 : .set_clock_gating = &radeon_legacy_set_clock_gating,
623 : },
624 : .pflip = {
625 : .page_flip = &r100_page_flip,
626 : .page_flip_pending = &r100_page_flip_pending,
627 : },
628 : };
629 :
630 : static struct radeon_asic rs600_asic = {
631 : .init = &rs600_init,
632 : .fini = &rs600_fini,
633 : .suspend = &rs600_suspend,
634 : .resume = &rs600_resume,
635 : .vga_set_state = &r100_vga_set_state,
636 : .asic_reset = &rs600_asic_reset,
637 : .mmio_hdp_flush = NULL,
638 : .gui_idle = &r100_gui_idle,
639 : .mc_wait_for_idle = &rs600_mc_wait_for_idle,
640 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
641 : .gart = {
642 : .tlb_flush = &rs600_gart_tlb_flush,
643 : .get_page_entry = &rs600_gart_get_page_entry,
644 : .set_page = &rs600_gart_set_page,
645 : },
646 : .ring = {
647 : [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
648 : },
649 : .irq = {
650 : .set = &rs600_irq_set,
651 : .process = &rs600_irq_process,
652 : },
653 : .display = {
654 : .bandwidth_update = &rs600_bandwidth_update,
655 : .get_vblank_counter = &rs600_get_vblank_counter,
656 : .wait_for_vblank = &avivo_wait_for_vblank,
657 : .set_backlight_level = &atombios_set_backlight_level,
658 : .get_backlight_level = &atombios_get_backlight_level,
659 : },
660 : .copy = {
661 : .blit = &r100_copy_blit,
662 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
663 : .dma = &r200_copy_dma,
664 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
665 : .copy = &r100_copy_blit,
666 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
667 : },
668 : .surface = {
669 : .set_reg = r100_set_surface_reg,
670 : .clear_reg = r100_clear_surface_reg,
671 : },
672 : .hpd = {
673 : .init = &rs600_hpd_init,
674 : .fini = &rs600_hpd_fini,
675 : .sense = &rs600_hpd_sense,
676 : .set_polarity = &rs600_hpd_set_polarity,
677 : },
678 : .pm = {
679 : .misc = &rs600_pm_misc,
680 : .prepare = &rs600_pm_prepare,
681 : .finish = &rs600_pm_finish,
682 : .init_profile = &r420_pm_init_profile,
683 : .get_dynpm_state = &r100_pm_get_dynpm_state,
684 : .get_engine_clock = &radeon_atom_get_engine_clock,
685 : .set_engine_clock = &radeon_atom_set_engine_clock,
686 : .get_memory_clock = &radeon_atom_get_memory_clock,
687 : .set_memory_clock = &radeon_atom_set_memory_clock,
688 : .get_pcie_lanes = NULL,
689 : .set_pcie_lanes = NULL,
690 : .set_clock_gating = &radeon_atom_set_clock_gating,
691 : },
692 : .pflip = {
693 : .page_flip = &rs600_page_flip,
694 : .page_flip_pending = &rs600_page_flip_pending,
695 : },
696 : };
697 :
698 : static struct radeon_asic rs690_asic = {
699 : .init = &rs690_init,
700 : .fini = &rs690_fini,
701 : .suspend = &rs690_suspend,
702 : .resume = &rs690_resume,
703 : .vga_set_state = &r100_vga_set_state,
704 : .asic_reset = &rs600_asic_reset,
705 : .mmio_hdp_flush = NULL,
706 : .gui_idle = &r100_gui_idle,
707 : .mc_wait_for_idle = &rs690_mc_wait_for_idle,
708 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
709 : .gart = {
710 : .tlb_flush = &rs400_gart_tlb_flush,
711 : .get_page_entry = &rs400_gart_get_page_entry,
712 : .set_page = &rs400_gart_set_page,
713 : },
714 : .ring = {
715 : [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
716 : },
717 : .irq = {
718 : .set = &rs600_irq_set,
719 : .process = &rs600_irq_process,
720 : },
721 : .display = {
722 : .get_vblank_counter = &rs600_get_vblank_counter,
723 : .bandwidth_update = &rs690_bandwidth_update,
724 : .wait_for_vblank = &avivo_wait_for_vblank,
725 : .set_backlight_level = &atombios_set_backlight_level,
726 : .get_backlight_level = &atombios_get_backlight_level,
727 : },
728 : .copy = {
729 : .blit = &r100_copy_blit,
730 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
731 : .dma = &r200_copy_dma,
732 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
733 : .copy = &r200_copy_dma,
734 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
735 : },
736 : .surface = {
737 : .set_reg = r100_set_surface_reg,
738 : .clear_reg = r100_clear_surface_reg,
739 : },
740 : .hpd = {
741 : .init = &rs600_hpd_init,
742 : .fini = &rs600_hpd_fini,
743 : .sense = &rs600_hpd_sense,
744 : .set_polarity = &rs600_hpd_set_polarity,
745 : },
746 : .pm = {
747 : .misc = &rs600_pm_misc,
748 : .prepare = &rs600_pm_prepare,
749 : .finish = &rs600_pm_finish,
750 : .init_profile = &r420_pm_init_profile,
751 : .get_dynpm_state = &r100_pm_get_dynpm_state,
752 : .get_engine_clock = &radeon_atom_get_engine_clock,
753 : .set_engine_clock = &radeon_atom_set_engine_clock,
754 : .get_memory_clock = &radeon_atom_get_memory_clock,
755 : .set_memory_clock = &radeon_atom_set_memory_clock,
756 : .get_pcie_lanes = NULL,
757 : .set_pcie_lanes = NULL,
758 : .set_clock_gating = &radeon_atom_set_clock_gating,
759 : },
760 : .pflip = {
761 : .page_flip = &rs600_page_flip,
762 : .page_flip_pending = &rs600_page_flip_pending,
763 : },
764 : };
765 :
766 : static struct radeon_asic rv515_asic = {
767 : .init = &rv515_init,
768 : .fini = &rv515_fini,
769 : .suspend = &rv515_suspend,
770 : .resume = &rv515_resume,
771 : .vga_set_state = &r100_vga_set_state,
772 : .asic_reset = &rs600_asic_reset,
773 : .mmio_hdp_flush = NULL,
774 : .gui_idle = &r100_gui_idle,
775 : .mc_wait_for_idle = &rv515_mc_wait_for_idle,
776 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
777 : .gart = {
778 : .tlb_flush = &rv370_pcie_gart_tlb_flush,
779 : .get_page_entry = &rv370_pcie_gart_get_page_entry,
780 : .set_page = &rv370_pcie_gart_set_page,
781 : },
782 : .ring = {
783 : [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
784 : },
785 : .irq = {
786 : .set = &rs600_irq_set,
787 : .process = &rs600_irq_process,
788 : },
789 : .display = {
790 : .get_vblank_counter = &rs600_get_vblank_counter,
791 : .bandwidth_update = &rv515_bandwidth_update,
792 : .wait_for_vblank = &avivo_wait_for_vblank,
793 : .set_backlight_level = &atombios_set_backlight_level,
794 : .get_backlight_level = &atombios_get_backlight_level,
795 : },
796 : .copy = {
797 : .blit = &r100_copy_blit,
798 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
799 : .dma = &r200_copy_dma,
800 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
801 : .copy = &r100_copy_blit,
802 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
803 : },
804 : .surface = {
805 : .set_reg = r100_set_surface_reg,
806 : .clear_reg = r100_clear_surface_reg,
807 : },
808 : .hpd = {
809 : .init = &rs600_hpd_init,
810 : .fini = &rs600_hpd_fini,
811 : .sense = &rs600_hpd_sense,
812 : .set_polarity = &rs600_hpd_set_polarity,
813 : },
814 : .pm = {
815 : .misc = &rs600_pm_misc,
816 : .prepare = &rs600_pm_prepare,
817 : .finish = &rs600_pm_finish,
818 : .init_profile = &r420_pm_init_profile,
819 : .get_dynpm_state = &r100_pm_get_dynpm_state,
820 : .get_engine_clock = &radeon_atom_get_engine_clock,
821 : .set_engine_clock = &radeon_atom_set_engine_clock,
822 : .get_memory_clock = &radeon_atom_get_memory_clock,
823 : .set_memory_clock = &radeon_atom_set_memory_clock,
824 : .get_pcie_lanes = &rv370_get_pcie_lanes,
825 : .set_pcie_lanes = &rv370_set_pcie_lanes,
826 : .set_clock_gating = &radeon_atom_set_clock_gating,
827 : },
828 : .pflip = {
829 : .page_flip = &rs600_page_flip,
830 : .page_flip_pending = &rs600_page_flip_pending,
831 : },
832 : };
833 :
834 : static struct radeon_asic r520_asic = {
835 : .init = &r520_init,
836 : .fini = &rv515_fini,
837 : .suspend = &rv515_suspend,
838 : .resume = &r520_resume,
839 : .vga_set_state = &r100_vga_set_state,
840 : .asic_reset = &rs600_asic_reset,
841 : .mmio_hdp_flush = NULL,
842 : .gui_idle = &r100_gui_idle,
843 : .mc_wait_for_idle = &r520_mc_wait_for_idle,
844 : .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
845 : .gart = {
846 : .tlb_flush = &rv370_pcie_gart_tlb_flush,
847 : .get_page_entry = &rv370_pcie_gart_get_page_entry,
848 : .set_page = &rv370_pcie_gart_set_page,
849 : },
850 : .ring = {
851 : [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
852 : },
853 : .irq = {
854 : .set = &rs600_irq_set,
855 : .process = &rs600_irq_process,
856 : },
857 : .display = {
858 : .bandwidth_update = &rv515_bandwidth_update,
859 : .get_vblank_counter = &rs600_get_vblank_counter,
860 : .wait_for_vblank = &avivo_wait_for_vblank,
861 : .set_backlight_level = &atombios_set_backlight_level,
862 : .get_backlight_level = &atombios_get_backlight_level,
863 : },
864 : .copy = {
865 : .blit = &r100_copy_blit,
866 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
867 : .dma = &r200_copy_dma,
868 : .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
869 : .copy = &r100_copy_blit,
870 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
871 : },
872 : .surface = {
873 : .set_reg = r100_set_surface_reg,
874 : .clear_reg = r100_clear_surface_reg,
875 : },
876 : .hpd = {
877 : .init = &rs600_hpd_init,
878 : .fini = &rs600_hpd_fini,
879 : .sense = &rs600_hpd_sense,
880 : .set_polarity = &rs600_hpd_set_polarity,
881 : },
882 : .pm = {
883 : .misc = &rs600_pm_misc,
884 : .prepare = &rs600_pm_prepare,
885 : .finish = &rs600_pm_finish,
886 : .init_profile = &r420_pm_init_profile,
887 : .get_dynpm_state = &r100_pm_get_dynpm_state,
888 : .get_engine_clock = &radeon_atom_get_engine_clock,
889 : .set_engine_clock = &radeon_atom_set_engine_clock,
890 : .get_memory_clock = &radeon_atom_get_memory_clock,
891 : .set_memory_clock = &radeon_atom_set_memory_clock,
892 : .get_pcie_lanes = &rv370_get_pcie_lanes,
893 : .set_pcie_lanes = &rv370_set_pcie_lanes,
894 : .set_clock_gating = &radeon_atom_set_clock_gating,
895 : },
896 : .pflip = {
897 : .page_flip = &rs600_page_flip,
898 : .page_flip_pending = &rs600_page_flip_pending,
899 : },
900 : };
901 :
902 : static struct radeon_asic_ring r600_gfx_ring = {
903 : .ib_execute = &r600_ring_ib_execute,
904 : .emit_fence = &r600_fence_ring_emit,
905 : .emit_semaphore = &r600_semaphore_ring_emit,
906 : .cs_parse = &r600_cs_parse,
907 : .ring_test = &r600_ring_test,
908 : .ib_test = &r600_ib_test,
909 : .is_lockup = &r600_gfx_is_lockup,
910 : .get_rptr = &r600_gfx_get_rptr,
911 : .get_wptr = &r600_gfx_get_wptr,
912 : .set_wptr = &r600_gfx_set_wptr,
913 : };
914 :
915 : static struct radeon_asic_ring r600_dma_ring = {
916 : .ib_execute = &r600_dma_ring_ib_execute,
917 : .emit_fence = &r600_dma_fence_ring_emit,
918 : .emit_semaphore = &r600_dma_semaphore_ring_emit,
919 : .cs_parse = &r600_dma_cs_parse,
920 : .ring_test = &r600_dma_ring_test,
921 : .ib_test = &r600_dma_ib_test,
922 : .is_lockup = &r600_dma_is_lockup,
923 : .get_rptr = &r600_dma_get_rptr,
924 : .get_wptr = &r600_dma_get_wptr,
925 : .set_wptr = &r600_dma_set_wptr,
926 : };
927 :
928 : static struct radeon_asic r600_asic = {
929 : .init = &r600_init,
930 : .fini = &r600_fini,
931 : .suspend = &r600_suspend,
932 : .resume = &r600_resume,
933 : .vga_set_state = &r600_vga_set_state,
934 : .asic_reset = &r600_asic_reset,
935 : .mmio_hdp_flush = r600_mmio_hdp_flush,
936 : .gui_idle = &r600_gui_idle,
937 : .mc_wait_for_idle = &r600_mc_wait_for_idle,
938 : .get_xclk = &r600_get_xclk,
939 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
940 : .get_allowed_info_register = r600_get_allowed_info_register,
941 : .gart = {
942 : .tlb_flush = &r600_pcie_gart_tlb_flush,
943 : .get_page_entry = &rs600_gart_get_page_entry,
944 : .set_page = &rs600_gart_set_page,
945 : },
946 : .ring = {
947 : [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
948 : [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
949 : },
950 : .irq = {
951 : .set = &r600_irq_set,
952 : .process = &r600_irq_process,
953 : },
954 : .display = {
955 : .bandwidth_update = &rv515_bandwidth_update,
956 : .get_vblank_counter = &rs600_get_vblank_counter,
957 : .wait_for_vblank = &avivo_wait_for_vblank,
958 : .set_backlight_level = &atombios_set_backlight_level,
959 : .get_backlight_level = &atombios_get_backlight_level,
960 : },
961 : .copy = {
962 : .blit = &r600_copy_cpdma,
963 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
964 : .dma = &r600_copy_dma,
965 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
966 : .copy = &r600_copy_cpdma,
967 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
968 : },
969 : .surface = {
970 : .set_reg = r600_set_surface_reg,
971 : .clear_reg = r600_clear_surface_reg,
972 : },
973 : .hpd = {
974 : .init = &r600_hpd_init,
975 : .fini = &r600_hpd_fini,
976 : .sense = &r600_hpd_sense,
977 : .set_polarity = &r600_hpd_set_polarity,
978 : },
979 : .pm = {
980 : .misc = &r600_pm_misc,
981 : .prepare = &rs600_pm_prepare,
982 : .finish = &rs600_pm_finish,
983 : .init_profile = &r600_pm_init_profile,
984 : .get_dynpm_state = &r600_pm_get_dynpm_state,
985 : .get_engine_clock = &radeon_atom_get_engine_clock,
986 : .set_engine_clock = &radeon_atom_set_engine_clock,
987 : .get_memory_clock = &radeon_atom_get_memory_clock,
988 : .set_memory_clock = &radeon_atom_set_memory_clock,
989 : .get_pcie_lanes = &r600_get_pcie_lanes,
990 : .set_pcie_lanes = &r600_set_pcie_lanes,
991 : .set_clock_gating = NULL,
992 : .get_temperature = &rv6xx_get_temp,
993 : },
994 : .pflip = {
995 : .page_flip = &rs600_page_flip,
996 : .page_flip_pending = &rs600_page_flip_pending,
997 : },
998 : };
999 :
1000 : static struct radeon_asic_ring rv6xx_uvd_ring = {
1001 : .ib_execute = &uvd_v1_0_ib_execute,
1002 : .emit_fence = &uvd_v1_0_fence_emit,
1003 : .emit_semaphore = &uvd_v1_0_semaphore_emit,
1004 : .cs_parse = &radeon_uvd_cs_parse,
1005 : .ring_test = &uvd_v1_0_ring_test,
1006 : .ib_test = &uvd_v1_0_ib_test,
1007 : .is_lockup = &radeon_ring_test_lockup,
1008 : .get_rptr = &uvd_v1_0_get_rptr,
1009 : .get_wptr = &uvd_v1_0_get_wptr,
1010 : .set_wptr = &uvd_v1_0_set_wptr,
1011 : };
1012 :
1013 : static struct radeon_asic rv6xx_asic = {
1014 : .init = &r600_init,
1015 : .fini = &r600_fini,
1016 : .suspend = &r600_suspend,
1017 : .resume = &r600_resume,
1018 : .vga_set_state = &r600_vga_set_state,
1019 : .asic_reset = &r600_asic_reset,
1020 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1021 : .gui_idle = &r600_gui_idle,
1022 : .mc_wait_for_idle = &r600_mc_wait_for_idle,
1023 : .get_xclk = &r600_get_xclk,
1024 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1025 : .get_allowed_info_register = r600_get_allowed_info_register,
1026 : .gart = {
1027 : .tlb_flush = &r600_pcie_gart_tlb_flush,
1028 : .get_page_entry = &rs600_gart_get_page_entry,
1029 : .set_page = &rs600_gart_set_page,
1030 : },
1031 : .ring = {
1032 : [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1033 : [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1034 : [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1035 : },
1036 : .irq = {
1037 : .set = &r600_irq_set,
1038 : .process = &r600_irq_process,
1039 : },
1040 : .display = {
1041 : .bandwidth_update = &rv515_bandwidth_update,
1042 : .get_vblank_counter = &rs600_get_vblank_counter,
1043 : .wait_for_vblank = &avivo_wait_for_vblank,
1044 : .set_backlight_level = &atombios_set_backlight_level,
1045 : .get_backlight_level = &atombios_get_backlight_level,
1046 : },
1047 : .copy = {
1048 : .blit = &r600_copy_cpdma,
1049 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1050 : .dma = &r600_copy_dma,
1051 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1052 : .copy = &r600_copy_cpdma,
1053 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1054 : },
1055 : .surface = {
1056 : .set_reg = r600_set_surface_reg,
1057 : .clear_reg = r600_clear_surface_reg,
1058 : },
1059 : .hpd = {
1060 : .init = &r600_hpd_init,
1061 : .fini = &r600_hpd_fini,
1062 : .sense = &r600_hpd_sense,
1063 : .set_polarity = &r600_hpd_set_polarity,
1064 : },
1065 : .pm = {
1066 : .misc = &r600_pm_misc,
1067 : .prepare = &rs600_pm_prepare,
1068 : .finish = &rs600_pm_finish,
1069 : .init_profile = &r600_pm_init_profile,
1070 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1071 : .get_engine_clock = &radeon_atom_get_engine_clock,
1072 : .set_engine_clock = &radeon_atom_set_engine_clock,
1073 : .get_memory_clock = &radeon_atom_get_memory_clock,
1074 : .set_memory_clock = &radeon_atom_set_memory_clock,
1075 : .get_pcie_lanes = &r600_get_pcie_lanes,
1076 : .set_pcie_lanes = &r600_set_pcie_lanes,
1077 : .set_clock_gating = NULL,
1078 : .get_temperature = &rv6xx_get_temp,
1079 : .set_uvd_clocks = &r600_set_uvd_clocks,
1080 : },
1081 : .dpm = {
1082 : .init = &rv6xx_dpm_init,
1083 : .setup_asic = &rv6xx_setup_asic,
1084 : .enable = &rv6xx_dpm_enable,
1085 : .late_enable = &r600_dpm_late_enable,
1086 : .disable = &rv6xx_dpm_disable,
1087 : .pre_set_power_state = &r600_dpm_pre_set_power_state,
1088 : .set_power_state = &rv6xx_dpm_set_power_state,
1089 : .post_set_power_state = &r600_dpm_post_set_power_state,
1090 : .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1091 : .fini = &rv6xx_dpm_fini,
1092 : .get_sclk = &rv6xx_dpm_get_sclk,
1093 : .get_mclk = &rv6xx_dpm_get_mclk,
1094 : .print_power_state = &rv6xx_dpm_print_power_state,
1095 : .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1096 : .force_performance_level = &rv6xx_dpm_force_performance_level,
1097 : .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1098 : .get_current_mclk = &rv6xx_dpm_get_current_mclk,
1099 : },
1100 : .pflip = {
1101 : .page_flip = &rs600_page_flip,
1102 : .page_flip_pending = &rs600_page_flip_pending,
1103 : },
1104 : };
1105 :
1106 : static struct radeon_asic rs780_asic = {
1107 : .init = &r600_init,
1108 : .fini = &r600_fini,
1109 : .suspend = &r600_suspend,
1110 : .resume = &r600_resume,
1111 : .vga_set_state = &r600_vga_set_state,
1112 : .asic_reset = &r600_asic_reset,
1113 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1114 : .gui_idle = &r600_gui_idle,
1115 : .mc_wait_for_idle = &r600_mc_wait_for_idle,
1116 : .get_xclk = &r600_get_xclk,
1117 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1118 : .get_allowed_info_register = r600_get_allowed_info_register,
1119 : .gart = {
1120 : .tlb_flush = &r600_pcie_gart_tlb_flush,
1121 : .get_page_entry = &rs600_gart_get_page_entry,
1122 : .set_page = &rs600_gart_set_page,
1123 : },
1124 : .ring = {
1125 : [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1126 : [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1127 : [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1128 : },
1129 : .irq = {
1130 : .set = &r600_irq_set,
1131 : .process = &r600_irq_process,
1132 : },
1133 : .display = {
1134 : .bandwidth_update = &rs690_bandwidth_update,
1135 : .get_vblank_counter = &rs600_get_vblank_counter,
1136 : .wait_for_vblank = &avivo_wait_for_vblank,
1137 : .set_backlight_level = &atombios_set_backlight_level,
1138 : .get_backlight_level = &atombios_get_backlight_level,
1139 : },
1140 : .copy = {
1141 : .blit = &r600_copy_cpdma,
1142 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1143 : .dma = &r600_copy_dma,
1144 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1145 : .copy = &r600_copy_cpdma,
1146 : .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1147 : },
1148 : .surface = {
1149 : .set_reg = r600_set_surface_reg,
1150 : .clear_reg = r600_clear_surface_reg,
1151 : },
1152 : .hpd = {
1153 : .init = &r600_hpd_init,
1154 : .fini = &r600_hpd_fini,
1155 : .sense = &r600_hpd_sense,
1156 : .set_polarity = &r600_hpd_set_polarity,
1157 : },
1158 : .pm = {
1159 : .misc = &r600_pm_misc,
1160 : .prepare = &rs600_pm_prepare,
1161 : .finish = &rs600_pm_finish,
1162 : .init_profile = &rs780_pm_init_profile,
1163 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1164 : .get_engine_clock = &radeon_atom_get_engine_clock,
1165 : .set_engine_clock = &radeon_atom_set_engine_clock,
1166 : .get_memory_clock = NULL,
1167 : .set_memory_clock = NULL,
1168 : .get_pcie_lanes = NULL,
1169 : .set_pcie_lanes = NULL,
1170 : .set_clock_gating = NULL,
1171 : .get_temperature = &rv6xx_get_temp,
1172 : .set_uvd_clocks = &r600_set_uvd_clocks,
1173 : },
1174 : .dpm = {
1175 : .init = &rs780_dpm_init,
1176 : .setup_asic = &rs780_dpm_setup_asic,
1177 : .enable = &rs780_dpm_enable,
1178 : .late_enable = &r600_dpm_late_enable,
1179 : .disable = &rs780_dpm_disable,
1180 : .pre_set_power_state = &r600_dpm_pre_set_power_state,
1181 : .set_power_state = &rs780_dpm_set_power_state,
1182 : .post_set_power_state = &r600_dpm_post_set_power_state,
1183 : .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1184 : .fini = &rs780_dpm_fini,
1185 : .get_sclk = &rs780_dpm_get_sclk,
1186 : .get_mclk = &rs780_dpm_get_mclk,
1187 : .print_power_state = &rs780_dpm_print_power_state,
1188 : .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1189 : .force_performance_level = &rs780_dpm_force_performance_level,
1190 : .get_current_sclk = &rs780_dpm_get_current_sclk,
1191 : .get_current_mclk = &rs780_dpm_get_current_mclk,
1192 : },
1193 : .pflip = {
1194 : .page_flip = &rs600_page_flip,
1195 : .page_flip_pending = &rs600_page_flip_pending,
1196 : },
1197 : };
1198 :
1199 : static struct radeon_asic_ring rv770_uvd_ring = {
1200 : .ib_execute = &uvd_v1_0_ib_execute,
1201 : .emit_fence = &uvd_v2_2_fence_emit,
1202 : .emit_semaphore = &uvd_v2_2_semaphore_emit,
1203 : .cs_parse = &radeon_uvd_cs_parse,
1204 : .ring_test = &uvd_v1_0_ring_test,
1205 : .ib_test = &uvd_v1_0_ib_test,
1206 : .is_lockup = &radeon_ring_test_lockup,
1207 : .get_rptr = &uvd_v1_0_get_rptr,
1208 : .get_wptr = &uvd_v1_0_get_wptr,
1209 : .set_wptr = &uvd_v1_0_set_wptr,
1210 : };
1211 :
1212 : static struct radeon_asic rv770_asic = {
1213 : .init = &rv770_init,
1214 : .fini = &rv770_fini,
1215 : .suspend = &rv770_suspend,
1216 : .resume = &rv770_resume,
1217 : .asic_reset = &r600_asic_reset,
1218 : .vga_set_state = &r600_vga_set_state,
1219 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1220 : .gui_idle = &r600_gui_idle,
1221 : .mc_wait_for_idle = &r600_mc_wait_for_idle,
1222 : .get_xclk = &rv770_get_xclk,
1223 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1224 : .get_allowed_info_register = r600_get_allowed_info_register,
1225 : .gart = {
1226 : .tlb_flush = &r600_pcie_gart_tlb_flush,
1227 : .get_page_entry = &rs600_gart_get_page_entry,
1228 : .set_page = &rs600_gart_set_page,
1229 : },
1230 : .ring = {
1231 : [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1232 : [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1233 : [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1234 : },
1235 : .irq = {
1236 : .set = &r600_irq_set,
1237 : .process = &r600_irq_process,
1238 : },
1239 : .display = {
1240 : .bandwidth_update = &rv515_bandwidth_update,
1241 : .get_vblank_counter = &rs600_get_vblank_counter,
1242 : .wait_for_vblank = &avivo_wait_for_vblank,
1243 : .set_backlight_level = &atombios_set_backlight_level,
1244 : .get_backlight_level = &atombios_get_backlight_level,
1245 : },
1246 : .copy = {
1247 : .blit = &r600_copy_cpdma,
1248 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1249 : .dma = &rv770_copy_dma,
1250 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1251 : .copy = &rv770_copy_dma,
1252 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1253 : },
1254 : .surface = {
1255 : .set_reg = r600_set_surface_reg,
1256 : .clear_reg = r600_clear_surface_reg,
1257 : },
1258 : .hpd = {
1259 : .init = &r600_hpd_init,
1260 : .fini = &r600_hpd_fini,
1261 : .sense = &r600_hpd_sense,
1262 : .set_polarity = &r600_hpd_set_polarity,
1263 : },
1264 : .pm = {
1265 : .misc = &rv770_pm_misc,
1266 : .prepare = &rs600_pm_prepare,
1267 : .finish = &rs600_pm_finish,
1268 : .init_profile = &r600_pm_init_profile,
1269 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1270 : .get_engine_clock = &radeon_atom_get_engine_clock,
1271 : .set_engine_clock = &radeon_atom_set_engine_clock,
1272 : .get_memory_clock = &radeon_atom_get_memory_clock,
1273 : .set_memory_clock = &radeon_atom_set_memory_clock,
1274 : .get_pcie_lanes = &r600_get_pcie_lanes,
1275 : .set_pcie_lanes = &r600_set_pcie_lanes,
1276 : .set_clock_gating = &radeon_atom_set_clock_gating,
1277 : .set_uvd_clocks = &rv770_set_uvd_clocks,
1278 : .get_temperature = &rv770_get_temp,
1279 : },
1280 : .dpm = {
1281 : .init = &rv770_dpm_init,
1282 : .setup_asic = &rv770_dpm_setup_asic,
1283 : .enable = &rv770_dpm_enable,
1284 : .late_enable = &rv770_dpm_late_enable,
1285 : .disable = &rv770_dpm_disable,
1286 : .pre_set_power_state = &r600_dpm_pre_set_power_state,
1287 : .set_power_state = &rv770_dpm_set_power_state,
1288 : .post_set_power_state = &r600_dpm_post_set_power_state,
1289 : .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1290 : .fini = &rv770_dpm_fini,
1291 : .get_sclk = &rv770_dpm_get_sclk,
1292 : .get_mclk = &rv770_dpm_get_mclk,
1293 : .print_power_state = &rv770_dpm_print_power_state,
1294 : .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1295 : .force_performance_level = &rv770_dpm_force_performance_level,
1296 : .vblank_too_short = &rv770_dpm_vblank_too_short,
1297 : .get_current_sclk = &rv770_dpm_get_current_sclk,
1298 : .get_current_mclk = &rv770_dpm_get_current_mclk,
1299 : },
1300 : .pflip = {
1301 : .page_flip = &rv770_page_flip,
1302 : .page_flip_pending = &rv770_page_flip_pending,
1303 : },
1304 : };
1305 :
1306 : static struct radeon_asic_ring evergreen_gfx_ring = {
1307 : .ib_execute = &evergreen_ring_ib_execute,
1308 : .emit_fence = &r600_fence_ring_emit,
1309 : .emit_semaphore = &r600_semaphore_ring_emit,
1310 : .cs_parse = &evergreen_cs_parse,
1311 : .ring_test = &r600_ring_test,
1312 : .ib_test = &r600_ib_test,
1313 : .is_lockup = &evergreen_gfx_is_lockup,
1314 : .get_rptr = &r600_gfx_get_rptr,
1315 : .get_wptr = &r600_gfx_get_wptr,
1316 : .set_wptr = &r600_gfx_set_wptr,
1317 : };
1318 :
1319 : static struct radeon_asic_ring evergreen_dma_ring = {
1320 : .ib_execute = &evergreen_dma_ring_ib_execute,
1321 : .emit_fence = &evergreen_dma_fence_ring_emit,
1322 : .emit_semaphore = &r600_dma_semaphore_ring_emit,
1323 : .cs_parse = &evergreen_dma_cs_parse,
1324 : .ring_test = &r600_dma_ring_test,
1325 : .ib_test = &r600_dma_ib_test,
1326 : .is_lockup = &evergreen_dma_is_lockup,
1327 : .get_rptr = &r600_dma_get_rptr,
1328 : .get_wptr = &r600_dma_get_wptr,
1329 : .set_wptr = &r600_dma_set_wptr,
1330 : };
1331 :
1332 : static struct radeon_asic evergreen_asic = {
1333 : .init = &evergreen_init,
1334 : .fini = &evergreen_fini,
1335 : .suspend = &evergreen_suspend,
1336 : .resume = &evergreen_resume,
1337 : .asic_reset = &evergreen_asic_reset,
1338 : .vga_set_state = &r600_vga_set_state,
1339 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1340 : .gui_idle = &r600_gui_idle,
1341 : .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1342 : .get_xclk = &rv770_get_xclk,
1343 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1344 : .get_allowed_info_register = evergreen_get_allowed_info_register,
1345 : .gart = {
1346 : .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1347 : .get_page_entry = &rs600_gart_get_page_entry,
1348 : .set_page = &rs600_gart_set_page,
1349 : },
1350 : .ring = {
1351 : [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1352 : [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1353 : [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1354 : },
1355 : .irq = {
1356 : .set = &evergreen_irq_set,
1357 : .process = &evergreen_irq_process,
1358 : },
1359 : .display = {
1360 : .bandwidth_update = &evergreen_bandwidth_update,
1361 : .get_vblank_counter = &evergreen_get_vblank_counter,
1362 : .wait_for_vblank = &dce4_wait_for_vblank,
1363 : .set_backlight_level = &atombios_set_backlight_level,
1364 : .get_backlight_level = &atombios_get_backlight_level,
1365 : },
1366 : .copy = {
1367 : .blit = &r600_copy_cpdma,
1368 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1369 : .dma = &evergreen_copy_dma,
1370 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1371 : .copy = &evergreen_copy_dma,
1372 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1373 : },
1374 : .surface = {
1375 : .set_reg = r600_set_surface_reg,
1376 : .clear_reg = r600_clear_surface_reg,
1377 : },
1378 : .hpd = {
1379 : .init = &evergreen_hpd_init,
1380 : .fini = &evergreen_hpd_fini,
1381 : .sense = &evergreen_hpd_sense,
1382 : .set_polarity = &evergreen_hpd_set_polarity,
1383 : },
1384 : .pm = {
1385 : .misc = &evergreen_pm_misc,
1386 : .prepare = &evergreen_pm_prepare,
1387 : .finish = &evergreen_pm_finish,
1388 : .init_profile = &r600_pm_init_profile,
1389 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1390 : .get_engine_clock = &radeon_atom_get_engine_clock,
1391 : .set_engine_clock = &radeon_atom_set_engine_clock,
1392 : .get_memory_clock = &radeon_atom_get_memory_clock,
1393 : .set_memory_clock = &radeon_atom_set_memory_clock,
1394 : .get_pcie_lanes = &r600_get_pcie_lanes,
1395 : .set_pcie_lanes = &r600_set_pcie_lanes,
1396 : .set_clock_gating = NULL,
1397 : .set_uvd_clocks = &evergreen_set_uvd_clocks,
1398 : .get_temperature = &evergreen_get_temp,
1399 : },
1400 : .dpm = {
1401 : .init = &cypress_dpm_init,
1402 : .setup_asic = &cypress_dpm_setup_asic,
1403 : .enable = &cypress_dpm_enable,
1404 : .late_enable = &rv770_dpm_late_enable,
1405 : .disable = &cypress_dpm_disable,
1406 : .pre_set_power_state = &r600_dpm_pre_set_power_state,
1407 : .set_power_state = &cypress_dpm_set_power_state,
1408 : .post_set_power_state = &r600_dpm_post_set_power_state,
1409 : .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1410 : .fini = &cypress_dpm_fini,
1411 : .get_sclk = &rv770_dpm_get_sclk,
1412 : .get_mclk = &rv770_dpm_get_mclk,
1413 : .print_power_state = &rv770_dpm_print_power_state,
1414 : .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1415 : .force_performance_level = &rv770_dpm_force_performance_level,
1416 : .vblank_too_short = &cypress_dpm_vblank_too_short,
1417 : .get_current_sclk = &rv770_dpm_get_current_sclk,
1418 : .get_current_mclk = &rv770_dpm_get_current_mclk,
1419 : },
1420 : .pflip = {
1421 : .page_flip = &evergreen_page_flip,
1422 : .page_flip_pending = &evergreen_page_flip_pending,
1423 : },
1424 : };
1425 :
1426 : static struct radeon_asic sumo_asic = {
1427 : .init = &evergreen_init,
1428 : .fini = &evergreen_fini,
1429 : .suspend = &evergreen_suspend,
1430 : .resume = &evergreen_resume,
1431 : .asic_reset = &evergreen_asic_reset,
1432 : .vga_set_state = &r600_vga_set_state,
1433 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1434 : .gui_idle = &r600_gui_idle,
1435 : .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1436 : .get_xclk = &r600_get_xclk,
1437 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1438 : .get_allowed_info_register = evergreen_get_allowed_info_register,
1439 : .gart = {
1440 : .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1441 : .get_page_entry = &rs600_gart_get_page_entry,
1442 : .set_page = &rs600_gart_set_page,
1443 : },
1444 : .ring = {
1445 : [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1446 : [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1447 : [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1448 : },
1449 : .irq = {
1450 : .set = &evergreen_irq_set,
1451 : .process = &evergreen_irq_process,
1452 : },
1453 : .display = {
1454 : .bandwidth_update = &evergreen_bandwidth_update,
1455 : .get_vblank_counter = &evergreen_get_vblank_counter,
1456 : .wait_for_vblank = &dce4_wait_for_vblank,
1457 : .set_backlight_level = &atombios_set_backlight_level,
1458 : .get_backlight_level = &atombios_get_backlight_level,
1459 : },
1460 : .copy = {
1461 : .blit = &r600_copy_cpdma,
1462 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1463 : .dma = &evergreen_copy_dma,
1464 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1465 : .copy = &evergreen_copy_dma,
1466 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1467 : },
1468 : .surface = {
1469 : .set_reg = r600_set_surface_reg,
1470 : .clear_reg = r600_clear_surface_reg,
1471 : },
1472 : .hpd = {
1473 : .init = &evergreen_hpd_init,
1474 : .fini = &evergreen_hpd_fini,
1475 : .sense = &evergreen_hpd_sense,
1476 : .set_polarity = &evergreen_hpd_set_polarity,
1477 : },
1478 : .pm = {
1479 : .misc = &evergreen_pm_misc,
1480 : .prepare = &evergreen_pm_prepare,
1481 : .finish = &evergreen_pm_finish,
1482 : .init_profile = &sumo_pm_init_profile,
1483 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1484 : .get_engine_clock = &radeon_atom_get_engine_clock,
1485 : .set_engine_clock = &radeon_atom_set_engine_clock,
1486 : .get_memory_clock = NULL,
1487 : .set_memory_clock = NULL,
1488 : .get_pcie_lanes = NULL,
1489 : .set_pcie_lanes = NULL,
1490 : .set_clock_gating = NULL,
1491 : .set_uvd_clocks = &sumo_set_uvd_clocks,
1492 : .get_temperature = &sumo_get_temp,
1493 : },
1494 : .dpm = {
1495 : .init = &sumo_dpm_init,
1496 : .setup_asic = &sumo_dpm_setup_asic,
1497 : .enable = &sumo_dpm_enable,
1498 : .late_enable = &sumo_dpm_late_enable,
1499 : .disable = &sumo_dpm_disable,
1500 : .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1501 : .set_power_state = &sumo_dpm_set_power_state,
1502 : .post_set_power_state = &sumo_dpm_post_set_power_state,
1503 : .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1504 : .fini = &sumo_dpm_fini,
1505 : .get_sclk = &sumo_dpm_get_sclk,
1506 : .get_mclk = &sumo_dpm_get_mclk,
1507 : .print_power_state = &sumo_dpm_print_power_state,
1508 : .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1509 : .force_performance_level = &sumo_dpm_force_performance_level,
1510 : .get_current_sclk = &sumo_dpm_get_current_sclk,
1511 : .get_current_mclk = &sumo_dpm_get_current_mclk,
1512 : },
1513 : .pflip = {
1514 : .page_flip = &evergreen_page_flip,
1515 : .page_flip_pending = &evergreen_page_flip_pending,
1516 : },
1517 : };
1518 :
1519 : static struct radeon_asic btc_asic = {
1520 : .init = &evergreen_init,
1521 : .fini = &evergreen_fini,
1522 : .suspend = &evergreen_suspend,
1523 : .resume = &evergreen_resume,
1524 : .asic_reset = &evergreen_asic_reset,
1525 : .vga_set_state = &r600_vga_set_state,
1526 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1527 : .gui_idle = &r600_gui_idle,
1528 : .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1529 : .get_xclk = &rv770_get_xclk,
1530 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1531 : .get_allowed_info_register = evergreen_get_allowed_info_register,
1532 : .gart = {
1533 : .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1534 : .get_page_entry = &rs600_gart_get_page_entry,
1535 : .set_page = &rs600_gart_set_page,
1536 : },
1537 : .ring = {
1538 : [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1539 : [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1540 : [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1541 : },
1542 : .irq = {
1543 : .set = &evergreen_irq_set,
1544 : .process = &evergreen_irq_process,
1545 : },
1546 : .display = {
1547 : .bandwidth_update = &evergreen_bandwidth_update,
1548 : .get_vblank_counter = &evergreen_get_vblank_counter,
1549 : .wait_for_vblank = &dce4_wait_for_vblank,
1550 : .set_backlight_level = &atombios_set_backlight_level,
1551 : .get_backlight_level = &atombios_get_backlight_level,
1552 : },
1553 : .copy = {
1554 : .blit = &r600_copy_cpdma,
1555 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1556 : .dma = &evergreen_copy_dma,
1557 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1558 : .copy = &evergreen_copy_dma,
1559 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1560 : },
1561 : .surface = {
1562 : .set_reg = r600_set_surface_reg,
1563 : .clear_reg = r600_clear_surface_reg,
1564 : },
1565 : .hpd = {
1566 : .init = &evergreen_hpd_init,
1567 : .fini = &evergreen_hpd_fini,
1568 : .sense = &evergreen_hpd_sense,
1569 : .set_polarity = &evergreen_hpd_set_polarity,
1570 : },
1571 : .pm = {
1572 : .misc = &evergreen_pm_misc,
1573 : .prepare = &evergreen_pm_prepare,
1574 : .finish = &evergreen_pm_finish,
1575 : .init_profile = &btc_pm_init_profile,
1576 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1577 : .get_engine_clock = &radeon_atom_get_engine_clock,
1578 : .set_engine_clock = &radeon_atom_set_engine_clock,
1579 : .get_memory_clock = &radeon_atom_get_memory_clock,
1580 : .set_memory_clock = &radeon_atom_set_memory_clock,
1581 : .get_pcie_lanes = &r600_get_pcie_lanes,
1582 : .set_pcie_lanes = &r600_set_pcie_lanes,
1583 : .set_clock_gating = NULL,
1584 : .set_uvd_clocks = &evergreen_set_uvd_clocks,
1585 : .get_temperature = &evergreen_get_temp,
1586 : },
1587 : .dpm = {
1588 : .init = &btc_dpm_init,
1589 : .setup_asic = &btc_dpm_setup_asic,
1590 : .enable = &btc_dpm_enable,
1591 : .late_enable = &rv770_dpm_late_enable,
1592 : .disable = &btc_dpm_disable,
1593 : .pre_set_power_state = &btc_dpm_pre_set_power_state,
1594 : .set_power_state = &btc_dpm_set_power_state,
1595 : .post_set_power_state = &btc_dpm_post_set_power_state,
1596 : .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1597 : .fini = &btc_dpm_fini,
1598 : .get_sclk = &btc_dpm_get_sclk,
1599 : .get_mclk = &btc_dpm_get_mclk,
1600 : .print_power_state = &rv770_dpm_print_power_state,
1601 : .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1602 : .force_performance_level = &rv770_dpm_force_performance_level,
1603 : .vblank_too_short = &btc_dpm_vblank_too_short,
1604 : .get_current_sclk = &btc_dpm_get_current_sclk,
1605 : .get_current_mclk = &btc_dpm_get_current_mclk,
1606 : },
1607 : .pflip = {
1608 : .page_flip = &evergreen_page_flip,
1609 : .page_flip_pending = &evergreen_page_flip_pending,
1610 : },
1611 : };
1612 :
1613 : static struct radeon_asic_ring cayman_gfx_ring = {
1614 : .ib_execute = &cayman_ring_ib_execute,
1615 : .ib_parse = &evergreen_ib_parse,
1616 : .emit_fence = &cayman_fence_ring_emit,
1617 : .emit_semaphore = &r600_semaphore_ring_emit,
1618 : .cs_parse = &evergreen_cs_parse,
1619 : .ring_test = &r600_ring_test,
1620 : .ib_test = &r600_ib_test,
1621 : .is_lockup = &cayman_gfx_is_lockup,
1622 : .vm_flush = &cayman_vm_flush,
1623 : .get_rptr = &cayman_gfx_get_rptr,
1624 : .get_wptr = &cayman_gfx_get_wptr,
1625 : .set_wptr = &cayman_gfx_set_wptr,
1626 : };
1627 :
1628 : static struct radeon_asic_ring cayman_dma_ring = {
1629 : .ib_execute = &cayman_dma_ring_ib_execute,
1630 : .ib_parse = &evergreen_dma_ib_parse,
1631 : .emit_fence = &evergreen_dma_fence_ring_emit,
1632 : .emit_semaphore = &r600_dma_semaphore_ring_emit,
1633 : .cs_parse = &evergreen_dma_cs_parse,
1634 : .ring_test = &r600_dma_ring_test,
1635 : .ib_test = &r600_dma_ib_test,
1636 : .is_lockup = &cayman_dma_is_lockup,
1637 : .vm_flush = &cayman_dma_vm_flush,
1638 : .get_rptr = &cayman_dma_get_rptr,
1639 : .get_wptr = &cayman_dma_get_wptr,
1640 : .set_wptr = &cayman_dma_set_wptr
1641 : };
1642 :
1643 : static struct radeon_asic_ring cayman_uvd_ring = {
1644 : .ib_execute = &uvd_v1_0_ib_execute,
1645 : .emit_fence = &uvd_v2_2_fence_emit,
1646 : .emit_semaphore = &uvd_v3_1_semaphore_emit,
1647 : .cs_parse = &radeon_uvd_cs_parse,
1648 : .ring_test = &uvd_v1_0_ring_test,
1649 : .ib_test = &uvd_v1_0_ib_test,
1650 : .is_lockup = &radeon_ring_test_lockup,
1651 : .get_rptr = &uvd_v1_0_get_rptr,
1652 : .get_wptr = &uvd_v1_0_get_wptr,
1653 : .set_wptr = &uvd_v1_0_set_wptr,
1654 : };
1655 :
1656 : static struct radeon_asic cayman_asic = {
1657 : .init = &cayman_init,
1658 : .fini = &cayman_fini,
1659 : .suspend = &cayman_suspend,
1660 : .resume = &cayman_resume,
1661 : .asic_reset = &cayman_asic_reset,
1662 : .vga_set_state = &r600_vga_set_state,
1663 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1664 : .gui_idle = &r600_gui_idle,
1665 : .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1666 : .get_xclk = &rv770_get_xclk,
1667 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1668 : .get_allowed_info_register = cayman_get_allowed_info_register,
1669 : .gart = {
1670 : .tlb_flush = &cayman_pcie_gart_tlb_flush,
1671 : .get_page_entry = &rs600_gart_get_page_entry,
1672 : .set_page = &rs600_gart_set_page,
1673 : },
1674 : .vm = {
1675 : .init = &cayman_vm_init,
1676 : .fini = &cayman_vm_fini,
1677 : .copy_pages = &cayman_dma_vm_copy_pages,
1678 : .write_pages = &cayman_dma_vm_write_pages,
1679 : .set_pages = &cayman_dma_vm_set_pages,
1680 : .pad_ib = &cayman_dma_vm_pad_ib,
1681 : },
1682 : .ring = {
1683 : [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1684 : [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1685 : [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1686 : [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1687 : [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1688 : [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1689 : },
1690 : .irq = {
1691 : .set = &evergreen_irq_set,
1692 : .process = &evergreen_irq_process,
1693 : },
1694 : .display = {
1695 : .bandwidth_update = &evergreen_bandwidth_update,
1696 : .get_vblank_counter = &evergreen_get_vblank_counter,
1697 : .wait_for_vblank = &dce4_wait_for_vblank,
1698 : .set_backlight_level = &atombios_set_backlight_level,
1699 : .get_backlight_level = &atombios_get_backlight_level,
1700 : },
1701 : .copy = {
1702 : .blit = &r600_copy_cpdma,
1703 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1704 : .dma = &evergreen_copy_dma,
1705 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1706 : .copy = &evergreen_copy_dma,
1707 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1708 : },
1709 : .surface = {
1710 : .set_reg = r600_set_surface_reg,
1711 : .clear_reg = r600_clear_surface_reg,
1712 : },
1713 : .hpd = {
1714 : .init = &evergreen_hpd_init,
1715 : .fini = &evergreen_hpd_fini,
1716 : .sense = &evergreen_hpd_sense,
1717 : .set_polarity = &evergreen_hpd_set_polarity,
1718 : },
1719 : .pm = {
1720 : .misc = &evergreen_pm_misc,
1721 : .prepare = &evergreen_pm_prepare,
1722 : .finish = &evergreen_pm_finish,
1723 : .init_profile = &btc_pm_init_profile,
1724 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1725 : .get_engine_clock = &radeon_atom_get_engine_clock,
1726 : .set_engine_clock = &radeon_atom_set_engine_clock,
1727 : .get_memory_clock = &radeon_atom_get_memory_clock,
1728 : .set_memory_clock = &radeon_atom_set_memory_clock,
1729 : .get_pcie_lanes = &r600_get_pcie_lanes,
1730 : .set_pcie_lanes = &r600_set_pcie_lanes,
1731 : .set_clock_gating = NULL,
1732 : .set_uvd_clocks = &evergreen_set_uvd_clocks,
1733 : .get_temperature = &evergreen_get_temp,
1734 : },
1735 : .dpm = {
1736 : .init = &ni_dpm_init,
1737 : .setup_asic = &ni_dpm_setup_asic,
1738 : .enable = &ni_dpm_enable,
1739 : .late_enable = &rv770_dpm_late_enable,
1740 : .disable = &ni_dpm_disable,
1741 : .pre_set_power_state = &ni_dpm_pre_set_power_state,
1742 : .set_power_state = &ni_dpm_set_power_state,
1743 : .post_set_power_state = &ni_dpm_post_set_power_state,
1744 : .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1745 : .fini = &ni_dpm_fini,
1746 : .get_sclk = &ni_dpm_get_sclk,
1747 : .get_mclk = &ni_dpm_get_mclk,
1748 : .print_power_state = &ni_dpm_print_power_state,
1749 : .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1750 : .force_performance_level = &ni_dpm_force_performance_level,
1751 : .vblank_too_short = &ni_dpm_vblank_too_short,
1752 : .get_current_sclk = &ni_dpm_get_current_sclk,
1753 : .get_current_mclk = &ni_dpm_get_current_mclk,
1754 : },
1755 : .pflip = {
1756 : .page_flip = &evergreen_page_flip,
1757 : .page_flip_pending = &evergreen_page_flip_pending,
1758 : },
1759 : };
1760 :
1761 : static struct radeon_asic_ring trinity_vce_ring = {
1762 : .ib_execute = &radeon_vce_ib_execute,
1763 : .emit_fence = &radeon_vce_fence_emit,
1764 : .emit_semaphore = &radeon_vce_semaphore_emit,
1765 : .cs_parse = &radeon_vce_cs_parse,
1766 : .ring_test = &radeon_vce_ring_test,
1767 : .ib_test = &radeon_vce_ib_test,
1768 : .is_lockup = &radeon_ring_test_lockup,
1769 : .get_rptr = &vce_v1_0_get_rptr,
1770 : .get_wptr = &vce_v1_0_get_wptr,
1771 : .set_wptr = &vce_v1_0_set_wptr,
1772 : };
1773 :
1774 : static struct radeon_asic trinity_asic = {
1775 : .init = &cayman_init,
1776 : .fini = &cayman_fini,
1777 : .suspend = &cayman_suspend,
1778 : .resume = &cayman_resume,
1779 : .asic_reset = &cayman_asic_reset,
1780 : .vga_set_state = &r600_vga_set_state,
1781 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1782 : .gui_idle = &r600_gui_idle,
1783 : .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1784 : .get_xclk = &r600_get_xclk,
1785 : .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1786 : .get_allowed_info_register = cayman_get_allowed_info_register,
1787 : .gart = {
1788 : .tlb_flush = &cayman_pcie_gart_tlb_flush,
1789 : .get_page_entry = &rs600_gart_get_page_entry,
1790 : .set_page = &rs600_gart_set_page,
1791 : },
1792 : .vm = {
1793 : .init = &cayman_vm_init,
1794 : .fini = &cayman_vm_fini,
1795 : .copy_pages = &cayman_dma_vm_copy_pages,
1796 : .write_pages = &cayman_dma_vm_write_pages,
1797 : .set_pages = &cayman_dma_vm_set_pages,
1798 : .pad_ib = &cayman_dma_vm_pad_ib,
1799 : },
1800 : .ring = {
1801 : [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1802 : [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1803 : [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1804 : [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1805 : [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1806 : [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1807 : [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
1808 : [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
1809 : },
1810 : .irq = {
1811 : .set = &evergreen_irq_set,
1812 : .process = &evergreen_irq_process,
1813 : },
1814 : .display = {
1815 : .bandwidth_update = &dce6_bandwidth_update,
1816 : .get_vblank_counter = &evergreen_get_vblank_counter,
1817 : .wait_for_vblank = &dce4_wait_for_vblank,
1818 : .set_backlight_level = &atombios_set_backlight_level,
1819 : .get_backlight_level = &atombios_get_backlight_level,
1820 : },
1821 : .copy = {
1822 : .blit = &r600_copy_cpdma,
1823 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1824 : .dma = &evergreen_copy_dma,
1825 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1826 : .copy = &evergreen_copy_dma,
1827 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1828 : },
1829 : .surface = {
1830 : .set_reg = r600_set_surface_reg,
1831 : .clear_reg = r600_clear_surface_reg,
1832 : },
1833 : .hpd = {
1834 : .init = &evergreen_hpd_init,
1835 : .fini = &evergreen_hpd_fini,
1836 : .sense = &evergreen_hpd_sense,
1837 : .set_polarity = &evergreen_hpd_set_polarity,
1838 : },
1839 : .pm = {
1840 : .misc = &evergreen_pm_misc,
1841 : .prepare = &evergreen_pm_prepare,
1842 : .finish = &evergreen_pm_finish,
1843 : .init_profile = &sumo_pm_init_profile,
1844 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1845 : .get_engine_clock = &radeon_atom_get_engine_clock,
1846 : .set_engine_clock = &radeon_atom_set_engine_clock,
1847 : .get_memory_clock = NULL,
1848 : .set_memory_clock = NULL,
1849 : .get_pcie_lanes = NULL,
1850 : .set_pcie_lanes = NULL,
1851 : .set_clock_gating = NULL,
1852 : .set_uvd_clocks = &sumo_set_uvd_clocks,
1853 : .set_vce_clocks = &tn_set_vce_clocks,
1854 : .get_temperature = &tn_get_temp,
1855 : },
1856 : .dpm = {
1857 : .init = &trinity_dpm_init,
1858 : .setup_asic = &trinity_dpm_setup_asic,
1859 : .enable = &trinity_dpm_enable,
1860 : .late_enable = &trinity_dpm_late_enable,
1861 : .disable = &trinity_dpm_disable,
1862 : .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1863 : .set_power_state = &trinity_dpm_set_power_state,
1864 : .post_set_power_state = &trinity_dpm_post_set_power_state,
1865 : .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1866 : .fini = &trinity_dpm_fini,
1867 : .get_sclk = &trinity_dpm_get_sclk,
1868 : .get_mclk = &trinity_dpm_get_mclk,
1869 : .print_power_state = &trinity_dpm_print_power_state,
1870 : .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1871 : .force_performance_level = &trinity_dpm_force_performance_level,
1872 : .enable_bapm = &trinity_dpm_enable_bapm,
1873 : .get_current_sclk = &trinity_dpm_get_current_sclk,
1874 : .get_current_mclk = &trinity_dpm_get_current_mclk,
1875 : },
1876 : .pflip = {
1877 : .page_flip = &evergreen_page_flip,
1878 : .page_flip_pending = &evergreen_page_flip_pending,
1879 : },
1880 : };
1881 :
1882 : static struct radeon_asic_ring si_gfx_ring = {
1883 : .ib_execute = &si_ring_ib_execute,
1884 : .ib_parse = &si_ib_parse,
1885 : .emit_fence = &si_fence_ring_emit,
1886 : .emit_semaphore = &r600_semaphore_ring_emit,
1887 : .cs_parse = NULL,
1888 : .ring_test = &r600_ring_test,
1889 : .ib_test = &r600_ib_test,
1890 : .is_lockup = &si_gfx_is_lockup,
1891 : .vm_flush = &si_vm_flush,
1892 : .get_rptr = &cayman_gfx_get_rptr,
1893 : .get_wptr = &cayman_gfx_get_wptr,
1894 : .set_wptr = &cayman_gfx_set_wptr,
1895 : };
1896 :
1897 : static struct radeon_asic_ring si_dma_ring = {
1898 : .ib_execute = &cayman_dma_ring_ib_execute,
1899 : .ib_parse = &evergreen_dma_ib_parse,
1900 : .emit_fence = &evergreen_dma_fence_ring_emit,
1901 : .emit_semaphore = &r600_dma_semaphore_ring_emit,
1902 : .cs_parse = NULL,
1903 : .ring_test = &r600_dma_ring_test,
1904 : .ib_test = &r600_dma_ib_test,
1905 : .is_lockup = &si_dma_is_lockup,
1906 : .vm_flush = &si_dma_vm_flush,
1907 : .get_rptr = &cayman_dma_get_rptr,
1908 : .get_wptr = &cayman_dma_get_wptr,
1909 : .set_wptr = &cayman_dma_set_wptr,
1910 : };
1911 :
1912 : static struct radeon_asic si_asic = {
1913 : .init = &si_init,
1914 : .fini = &si_fini,
1915 : .suspend = &si_suspend,
1916 : .resume = &si_resume,
1917 : .asic_reset = &si_asic_reset,
1918 : .vga_set_state = &r600_vga_set_state,
1919 : .mmio_hdp_flush = r600_mmio_hdp_flush,
1920 : .gui_idle = &r600_gui_idle,
1921 : .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1922 : .get_xclk = &si_get_xclk,
1923 : .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1924 : .get_allowed_info_register = si_get_allowed_info_register,
1925 : .gart = {
1926 : .tlb_flush = &si_pcie_gart_tlb_flush,
1927 : .get_page_entry = &rs600_gart_get_page_entry,
1928 : .set_page = &rs600_gart_set_page,
1929 : },
1930 : .vm = {
1931 : .init = &si_vm_init,
1932 : .fini = &si_vm_fini,
1933 : .copy_pages = &si_dma_vm_copy_pages,
1934 : .write_pages = &si_dma_vm_write_pages,
1935 : .set_pages = &si_dma_vm_set_pages,
1936 : .pad_ib = &cayman_dma_vm_pad_ib,
1937 : },
1938 : .ring = {
1939 : [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1940 : [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1941 : [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1942 : [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1943 : [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1944 : [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1945 : [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
1946 : [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
1947 : },
1948 : .irq = {
1949 : .set = &si_irq_set,
1950 : .process = &si_irq_process,
1951 : },
1952 : .display = {
1953 : .bandwidth_update = &dce6_bandwidth_update,
1954 : .get_vblank_counter = &evergreen_get_vblank_counter,
1955 : .wait_for_vblank = &dce4_wait_for_vblank,
1956 : .set_backlight_level = &atombios_set_backlight_level,
1957 : .get_backlight_level = &atombios_get_backlight_level,
1958 : },
1959 : .copy = {
1960 : .blit = &r600_copy_cpdma,
1961 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1962 : .dma = &si_copy_dma,
1963 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1964 : .copy = &si_copy_dma,
1965 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1966 : },
1967 : .surface = {
1968 : .set_reg = r600_set_surface_reg,
1969 : .clear_reg = r600_clear_surface_reg,
1970 : },
1971 : .hpd = {
1972 : .init = &evergreen_hpd_init,
1973 : .fini = &evergreen_hpd_fini,
1974 : .sense = &evergreen_hpd_sense,
1975 : .set_polarity = &evergreen_hpd_set_polarity,
1976 : },
1977 : .pm = {
1978 : .misc = &evergreen_pm_misc,
1979 : .prepare = &evergreen_pm_prepare,
1980 : .finish = &evergreen_pm_finish,
1981 : .init_profile = &sumo_pm_init_profile,
1982 : .get_dynpm_state = &r600_pm_get_dynpm_state,
1983 : .get_engine_clock = &radeon_atom_get_engine_clock,
1984 : .set_engine_clock = &radeon_atom_set_engine_clock,
1985 : .get_memory_clock = &radeon_atom_get_memory_clock,
1986 : .set_memory_clock = &radeon_atom_set_memory_clock,
1987 : .get_pcie_lanes = &r600_get_pcie_lanes,
1988 : .set_pcie_lanes = &r600_set_pcie_lanes,
1989 : .set_clock_gating = NULL,
1990 : .set_uvd_clocks = &si_set_uvd_clocks,
1991 : .set_vce_clocks = &si_set_vce_clocks,
1992 : .get_temperature = &si_get_temp,
1993 : },
1994 : .dpm = {
1995 : .init = &si_dpm_init,
1996 : .setup_asic = &si_dpm_setup_asic,
1997 : .enable = &si_dpm_enable,
1998 : .late_enable = &si_dpm_late_enable,
1999 : .disable = &si_dpm_disable,
2000 : .pre_set_power_state = &si_dpm_pre_set_power_state,
2001 : .set_power_state = &si_dpm_set_power_state,
2002 : .post_set_power_state = &si_dpm_post_set_power_state,
2003 : .display_configuration_changed = &si_dpm_display_configuration_changed,
2004 : .fini = &si_dpm_fini,
2005 : .get_sclk = &ni_dpm_get_sclk,
2006 : .get_mclk = &ni_dpm_get_mclk,
2007 : .print_power_state = &ni_dpm_print_power_state,
2008 : .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
2009 : .force_performance_level = &si_dpm_force_performance_level,
2010 : .vblank_too_short = &ni_dpm_vblank_too_short,
2011 : .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
2012 : .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
2013 : .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
2014 : .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
2015 : .get_current_sclk = &si_dpm_get_current_sclk,
2016 : .get_current_mclk = &si_dpm_get_current_mclk,
2017 : },
2018 : .pflip = {
2019 : .page_flip = &evergreen_page_flip,
2020 : .page_flip_pending = &evergreen_page_flip_pending,
2021 : },
2022 : };
2023 :
2024 : static struct radeon_asic_ring ci_gfx_ring = {
2025 : .ib_execute = &cik_ring_ib_execute,
2026 : .ib_parse = &cik_ib_parse,
2027 : .emit_fence = &cik_fence_gfx_ring_emit,
2028 : .emit_semaphore = &cik_semaphore_ring_emit,
2029 : .cs_parse = NULL,
2030 : .ring_test = &cik_ring_test,
2031 : .ib_test = &cik_ib_test,
2032 : .is_lockup = &cik_gfx_is_lockup,
2033 : .vm_flush = &cik_vm_flush,
2034 : .get_rptr = &cik_gfx_get_rptr,
2035 : .get_wptr = &cik_gfx_get_wptr,
2036 : .set_wptr = &cik_gfx_set_wptr,
2037 : };
2038 :
2039 : static struct radeon_asic_ring ci_cp_ring = {
2040 : .ib_execute = &cik_ring_ib_execute,
2041 : .ib_parse = &cik_ib_parse,
2042 : .emit_fence = &cik_fence_compute_ring_emit,
2043 : .emit_semaphore = &cik_semaphore_ring_emit,
2044 : .cs_parse = NULL,
2045 : .ring_test = &cik_ring_test,
2046 : .ib_test = &cik_ib_test,
2047 : .is_lockup = &cik_gfx_is_lockup,
2048 : .vm_flush = &cik_vm_flush,
2049 : .get_rptr = &cik_compute_get_rptr,
2050 : .get_wptr = &cik_compute_get_wptr,
2051 : .set_wptr = &cik_compute_set_wptr,
2052 : };
2053 :
2054 : static struct radeon_asic_ring ci_dma_ring = {
2055 : .ib_execute = &cik_sdma_ring_ib_execute,
2056 : .ib_parse = &cik_ib_parse,
2057 : .emit_fence = &cik_sdma_fence_ring_emit,
2058 : .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2059 : .cs_parse = NULL,
2060 : .ring_test = &cik_sdma_ring_test,
2061 : .ib_test = &cik_sdma_ib_test,
2062 : .is_lockup = &cik_sdma_is_lockup,
2063 : .vm_flush = &cik_dma_vm_flush,
2064 : .get_rptr = &cik_sdma_get_rptr,
2065 : .get_wptr = &cik_sdma_get_wptr,
2066 : .set_wptr = &cik_sdma_set_wptr,
2067 : };
2068 :
2069 : static struct radeon_asic_ring ci_vce_ring = {
2070 : .ib_execute = &radeon_vce_ib_execute,
2071 : .emit_fence = &radeon_vce_fence_emit,
2072 : .emit_semaphore = &radeon_vce_semaphore_emit,
2073 : .cs_parse = &radeon_vce_cs_parse,
2074 : .ring_test = &radeon_vce_ring_test,
2075 : .ib_test = &radeon_vce_ib_test,
2076 : .is_lockup = &radeon_ring_test_lockup,
2077 : .get_rptr = &vce_v1_0_get_rptr,
2078 : .get_wptr = &vce_v1_0_get_wptr,
2079 : .set_wptr = &vce_v1_0_set_wptr,
2080 : };
2081 :
2082 : static struct radeon_asic ci_asic = {
2083 : .init = &cik_init,
2084 : .fini = &cik_fini,
2085 : .suspend = &cik_suspend,
2086 : .resume = &cik_resume,
2087 : .asic_reset = &cik_asic_reset,
2088 : .vga_set_state = &r600_vga_set_state,
2089 : .mmio_hdp_flush = &r600_mmio_hdp_flush,
2090 : .gui_idle = &r600_gui_idle,
2091 : .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2092 : .get_xclk = &cik_get_xclk,
2093 : .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2094 : .get_allowed_info_register = cik_get_allowed_info_register,
2095 : .gart = {
2096 : .tlb_flush = &cik_pcie_gart_tlb_flush,
2097 : .get_page_entry = &rs600_gart_get_page_entry,
2098 : .set_page = &rs600_gart_set_page,
2099 : },
2100 : .vm = {
2101 : .init = &cik_vm_init,
2102 : .fini = &cik_vm_fini,
2103 : .copy_pages = &cik_sdma_vm_copy_pages,
2104 : .write_pages = &cik_sdma_vm_write_pages,
2105 : .set_pages = &cik_sdma_vm_set_pages,
2106 : .pad_ib = &cik_sdma_vm_pad_ib,
2107 : },
2108 : .ring = {
2109 : [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2110 : [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2111 : [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2112 : [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2113 : [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2114 : [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2115 : [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2116 : [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2117 : },
2118 : .irq = {
2119 : .set = &cik_irq_set,
2120 : .process = &cik_irq_process,
2121 : },
2122 : .display = {
2123 : .bandwidth_update = &dce8_bandwidth_update,
2124 : .get_vblank_counter = &evergreen_get_vblank_counter,
2125 : .wait_for_vblank = &dce4_wait_for_vblank,
2126 : .set_backlight_level = &atombios_set_backlight_level,
2127 : .get_backlight_level = &atombios_get_backlight_level,
2128 : },
2129 : .copy = {
2130 : .blit = &cik_copy_cpdma,
2131 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2132 : .dma = &cik_copy_dma,
2133 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2134 : .copy = &cik_copy_dma,
2135 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2136 : },
2137 : .surface = {
2138 : .set_reg = r600_set_surface_reg,
2139 : .clear_reg = r600_clear_surface_reg,
2140 : },
2141 : .hpd = {
2142 : .init = &evergreen_hpd_init,
2143 : .fini = &evergreen_hpd_fini,
2144 : .sense = &evergreen_hpd_sense,
2145 : .set_polarity = &evergreen_hpd_set_polarity,
2146 : },
2147 : .pm = {
2148 : .misc = &evergreen_pm_misc,
2149 : .prepare = &evergreen_pm_prepare,
2150 : .finish = &evergreen_pm_finish,
2151 : .init_profile = &sumo_pm_init_profile,
2152 : .get_dynpm_state = &r600_pm_get_dynpm_state,
2153 : .get_engine_clock = &radeon_atom_get_engine_clock,
2154 : .set_engine_clock = &radeon_atom_set_engine_clock,
2155 : .get_memory_clock = &radeon_atom_get_memory_clock,
2156 : .set_memory_clock = &radeon_atom_set_memory_clock,
2157 : .get_pcie_lanes = NULL,
2158 : .set_pcie_lanes = NULL,
2159 : .set_clock_gating = NULL,
2160 : .set_uvd_clocks = &cik_set_uvd_clocks,
2161 : .set_vce_clocks = &cik_set_vce_clocks,
2162 : .get_temperature = &ci_get_temp,
2163 : },
2164 : .dpm = {
2165 : .init = &ci_dpm_init,
2166 : .setup_asic = &ci_dpm_setup_asic,
2167 : .enable = &ci_dpm_enable,
2168 : .late_enable = &ci_dpm_late_enable,
2169 : .disable = &ci_dpm_disable,
2170 : .pre_set_power_state = &ci_dpm_pre_set_power_state,
2171 : .set_power_state = &ci_dpm_set_power_state,
2172 : .post_set_power_state = &ci_dpm_post_set_power_state,
2173 : .display_configuration_changed = &ci_dpm_display_configuration_changed,
2174 : .fini = &ci_dpm_fini,
2175 : .get_sclk = &ci_dpm_get_sclk,
2176 : .get_mclk = &ci_dpm_get_mclk,
2177 : .print_power_state = &ci_dpm_print_power_state,
2178 : .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2179 : .force_performance_level = &ci_dpm_force_performance_level,
2180 : .vblank_too_short = &ci_dpm_vblank_too_short,
2181 : .powergate_uvd = &ci_dpm_powergate_uvd,
2182 : .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2183 : .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2184 : .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2185 : .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
2186 : .get_current_sclk = &ci_dpm_get_current_sclk,
2187 : .get_current_mclk = &ci_dpm_get_current_mclk,
2188 : },
2189 : .pflip = {
2190 : .page_flip = &evergreen_page_flip,
2191 : .page_flip_pending = &evergreen_page_flip_pending,
2192 : },
2193 : };
2194 :
2195 : static struct radeon_asic kv_asic = {
2196 : .init = &cik_init,
2197 : .fini = &cik_fini,
2198 : .suspend = &cik_suspend,
2199 : .resume = &cik_resume,
2200 : .asic_reset = &cik_asic_reset,
2201 : .vga_set_state = &r600_vga_set_state,
2202 : .mmio_hdp_flush = &r600_mmio_hdp_flush,
2203 : .gui_idle = &r600_gui_idle,
2204 : .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2205 : .get_xclk = &cik_get_xclk,
2206 : .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2207 : .get_allowed_info_register = cik_get_allowed_info_register,
2208 : .gart = {
2209 : .tlb_flush = &cik_pcie_gart_tlb_flush,
2210 : .get_page_entry = &rs600_gart_get_page_entry,
2211 : .set_page = &rs600_gart_set_page,
2212 : },
2213 : .vm = {
2214 : .init = &cik_vm_init,
2215 : .fini = &cik_vm_fini,
2216 : .copy_pages = &cik_sdma_vm_copy_pages,
2217 : .write_pages = &cik_sdma_vm_write_pages,
2218 : .set_pages = &cik_sdma_vm_set_pages,
2219 : .pad_ib = &cik_sdma_vm_pad_ib,
2220 : },
2221 : .ring = {
2222 : [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2223 : [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2224 : [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2225 : [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2226 : [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2227 : [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2228 : [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2229 : [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2230 : },
2231 : .irq = {
2232 : .set = &cik_irq_set,
2233 : .process = &cik_irq_process,
2234 : },
2235 : .display = {
2236 : .bandwidth_update = &dce8_bandwidth_update,
2237 : .get_vblank_counter = &evergreen_get_vblank_counter,
2238 : .wait_for_vblank = &dce4_wait_for_vblank,
2239 : .set_backlight_level = &atombios_set_backlight_level,
2240 : .get_backlight_level = &atombios_get_backlight_level,
2241 : },
2242 : .copy = {
2243 : .blit = &cik_copy_cpdma,
2244 : .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2245 : .dma = &cik_copy_dma,
2246 : .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2247 : .copy = &cik_copy_dma,
2248 : .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2249 : },
2250 : .surface = {
2251 : .set_reg = r600_set_surface_reg,
2252 : .clear_reg = r600_clear_surface_reg,
2253 : },
2254 : .hpd = {
2255 : .init = &evergreen_hpd_init,
2256 : .fini = &evergreen_hpd_fini,
2257 : .sense = &evergreen_hpd_sense,
2258 : .set_polarity = &evergreen_hpd_set_polarity,
2259 : },
2260 : .pm = {
2261 : .misc = &evergreen_pm_misc,
2262 : .prepare = &evergreen_pm_prepare,
2263 : .finish = &evergreen_pm_finish,
2264 : .init_profile = &sumo_pm_init_profile,
2265 : .get_dynpm_state = &r600_pm_get_dynpm_state,
2266 : .get_engine_clock = &radeon_atom_get_engine_clock,
2267 : .set_engine_clock = &radeon_atom_set_engine_clock,
2268 : .get_memory_clock = &radeon_atom_get_memory_clock,
2269 : .set_memory_clock = &radeon_atom_set_memory_clock,
2270 : .get_pcie_lanes = NULL,
2271 : .set_pcie_lanes = NULL,
2272 : .set_clock_gating = NULL,
2273 : .set_uvd_clocks = &cik_set_uvd_clocks,
2274 : .set_vce_clocks = &cik_set_vce_clocks,
2275 : .get_temperature = &kv_get_temp,
2276 : },
2277 : .dpm = {
2278 : .init = &kv_dpm_init,
2279 : .setup_asic = &kv_dpm_setup_asic,
2280 : .enable = &kv_dpm_enable,
2281 : .late_enable = &kv_dpm_late_enable,
2282 : .disable = &kv_dpm_disable,
2283 : .pre_set_power_state = &kv_dpm_pre_set_power_state,
2284 : .set_power_state = &kv_dpm_set_power_state,
2285 : .post_set_power_state = &kv_dpm_post_set_power_state,
2286 : .display_configuration_changed = &kv_dpm_display_configuration_changed,
2287 : .fini = &kv_dpm_fini,
2288 : .get_sclk = &kv_dpm_get_sclk,
2289 : .get_mclk = &kv_dpm_get_mclk,
2290 : .print_power_state = &kv_dpm_print_power_state,
2291 : .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2292 : .force_performance_level = &kv_dpm_force_performance_level,
2293 : .powergate_uvd = &kv_dpm_powergate_uvd,
2294 : .enable_bapm = &kv_dpm_enable_bapm,
2295 : .get_current_sclk = &kv_dpm_get_current_sclk,
2296 : .get_current_mclk = &kv_dpm_get_current_mclk,
2297 : },
2298 : .pflip = {
2299 : .page_flip = &evergreen_page_flip,
2300 : .page_flip_pending = &evergreen_page_flip_pending,
2301 : },
2302 : };
2303 :
2304 : /**
2305 : * radeon_asic_init - register asic specific callbacks
2306 : *
2307 : * @rdev: radeon device pointer
2308 : *
2309 : * Registers the appropriate asic specific callbacks for each
2310 : * chip family. Also sets other asics specific info like the number
2311 : * of crtcs and the register aperture accessors (all asics).
2312 : * Returns 0 for success.
2313 : */
2314 0 : int radeon_asic_init(struct radeon_device *rdev)
2315 : {
2316 0 : radeon_register_accessor_init(rdev);
2317 :
2318 : /* set the number of crtcs */
2319 0 : if (rdev->flags & RADEON_SINGLE_CRTC)
2320 0 : rdev->num_crtc = 1;
2321 : else
2322 0 : rdev->num_crtc = 2;
2323 :
2324 0 : rdev->has_uvd = false;
2325 :
2326 0 : switch (rdev->family) {
2327 : case CHIP_R100:
2328 : case CHIP_RV100:
2329 : case CHIP_RS100:
2330 : case CHIP_RV200:
2331 : case CHIP_RS200:
2332 0 : rdev->asic = &r100_asic;
2333 0 : break;
2334 : case CHIP_R200:
2335 : case CHIP_RV250:
2336 : case CHIP_RS300:
2337 : case CHIP_RV280:
2338 0 : rdev->asic = &r200_asic;
2339 0 : break;
2340 : case CHIP_R300:
2341 : case CHIP_R350:
2342 : case CHIP_RV350:
2343 : case CHIP_RV380:
2344 0 : if (rdev->flags & RADEON_IS_PCIE)
2345 0 : rdev->asic = &r300_asic_pcie;
2346 : else
2347 0 : rdev->asic = &r300_asic;
2348 : break;
2349 : case CHIP_R420:
2350 : case CHIP_R423:
2351 : case CHIP_RV410:
2352 0 : rdev->asic = &r420_asic;
2353 : /* handle macs */
2354 0 : if (rdev->bios == NULL) {
2355 0 : rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2356 0 : rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2357 0 : rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2358 0 : rdev->asic->pm.set_memory_clock = NULL;
2359 0 : rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2360 0 : }
2361 : break;
2362 : case CHIP_RS400:
2363 : case CHIP_RS480:
2364 0 : rdev->asic = &rs400_asic;
2365 0 : break;
2366 : case CHIP_RS600:
2367 0 : rdev->asic = &rs600_asic;
2368 0 : break;
2369 : case CHIP_RS690:
2370 : case CHIP_RS740:
2371 0 : rdev->asic = &rs690_asic;
2372 0 : break;
2373 : case CHIP_RV515:
2374 0 : rdev->asic = &rv515_asic;
2375 0 : break;
2376 : case CHIP_R520:
2377 : case CHIP_RV530:
2378 : case CHIP_RV560:
2379 : case CHIP_RV570:
2380 : case CHIP_R580:
2381 0 : rdev->asic = &r520_asic;
2382 0 : break;
2383 : case CHIP_R600:
2384 0 : rdev->asic = &r600_asic;
2385 0 : break;
2386 : case CHIP_RV610:
2387 : case CHIP_RV630:
2388 : case CHIP_RV620:
2389 : case CHIP_RV635:
2390 : case CHIP_RV670:
2391 0 : rdev->asic = &rv6xx_asic;
2392 0 : rdev->has_uvd = true;
2393 0 : break;
2394 : case CHIP_RS780:
2395 : case CHIP_RS880:
2396 0 : rdev->asic = &rs780_asic;
2397 : /* 760G/780V/880V don't have UVD */
2398 0 : if ((rdev->pdev->device == 0x9616)||
2399 0 : (rdev->pdev->device == 0x9611)||
2400 0 : (rdev->pdev->device == 0x9613)||
2401 0 : (rdev->pdev->device == 0x9711)||
2402 0 : (rdev->pdev->device == 0x9713))
2403 0 : rdev->has_uvd = false;
2404 : else
2405 0 : rdev->has_uvd = true;
2406 : break;
2407 : case CHIP_RV770:
2408 : case CHIP_RV730:
2409 : case CHIP_RV710:
2410 : case CHIP_RV740:
2411 0 : rdev->asic = &rv770_asic;
2412 0 : rdev->has_uvd = true;
2413 0 : break;
2414 : case CHIP_CEDAR:
2415 : case CHIP_REDWOOD:
2416 : case CHIP_JUNIPER:
2417 : case CHIP_CYPRESS:
2418 : case CHIP_HEMLOCK:
2419 : /* set num crtcs */
2420 0 : if (rdev->family == CHIP_CEDAR)
2421 0 : rdev->num_crtc = 4;
2422 : else
2423 0 : rdev->num_crtc = 6;
2424 0 : rdev->asic = &evergreen_asic;
2425 0 : rdev->has_uvd = true;
2426 0 : break;
2427 : case CHIP_PALM:
2428 : case CHIP_SUMO:
2429 : case CHIP_SUMO2:
2430 0 : rdev->asic = &sumo_asic;
2431 0 : rdev->has_uvd = true;
2432 0 : break;
2433 : case CHIP_BARTS:
2434 : case CHIP_TURKS:
2435 : case CHIP_CAICOS:
2436 : /* set num crtcs */
2437 0 : if (rdev->family == CHIP_CAICOS)
2438 0 : rdev->num_crtc = 4;
2439 : else
2440 0 : rdev->num_crtc = 6;
2441 0 : rdev->asic = &btc_asic;
2442 0 : rdev->has_uvd = true;
2443 0 : break;
2444 : case CHIP_CAYMAN:
2445 0 : rdev->asic = &cayman_asic;
2446 : /* set num crtcs */
2447 0 : rdev->num_crtc = 6;
2448 0 : rdev->has_uvd = true;
2449 0 : break;
2450 : case CHIP_ARUBA:
2451 0 : rdev->asic = &trinity_asic;
2452 : /* set num crtcs */
2453 0 : rdev->num_crtc = 4;
2454 0 : rdev->has_uvd = true;
2455 0 : rdev->cg_flags =
2456 : RADEON_CG_SUPPORT_VCE_MGCG;
2457 0 : break;
2458 : case CHIP_TAHITI:
2459 : case CHIP_PITCAIRN:
2460 : case CHIP_VERDE:
2461 : case CHIP_OLAND:
2462 : case CHIP_HAINAN:
2463 0 : rdev->asic = &si_asic;
2464 : /* set num crtcs */
2465 0 : if (rdev->family == CHIP_HAINAN)
2466 0 : rdev->num_crtc = 0;
2467 0 : else if (rdev->family == CHIP_OLAND)
2468 0 : rdev->num_crtc = 2;
2469 : else
2470 0 : rdev->num_crtc = 6;
2471 0 : if (rdev->family == CHIP_HAINAN)
2472 0 : rdev->has_uvd = false;
2473 : else
2474 0 : rdev->has_uvd = true;
2475 0 : switch (rdev->family) {
2476 : case CHIP_TAHITI:
2477 0 : rdev->cg_flags =
2478 : RADEON_CG_SUPPORT_GFX_MGCG |
2479 : RADEON_CG_SUPPORT_GFX_MGLS |
2480 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2481 : RADEON_CG_SUPPORT_GFX_CGLS |
2482 : RADEON_CG_SUPPORT_GFX_CGTS |
2483 : RADEON_CG_SUPPORT_GFX_CP_LS |
2484 : RADEON_CG_SUPPORT_MC_MGCG |
2485 : RADEON_CG_SUPPORT_SDMA_MGCG |
2486 : RADEON_CG_SUPPORT_BIF_LS |
2487 : RADEON_CG_SUPPORT_VCE_MGCG |
2488 : RADEON_CG_SUPPORT_UVD_MGCG |
2489 : RADEON_CG_SUPPORT_HDP_LS |
2490 : RADEON_CG_SUPPORT_HDP_MGCG;
2491 0 : rdev->pg_flags = 0;
2492 0 : break;
2493 : case CHIP_PITCAIRN:
2494 0 : rdev->cg_flags =
2495 : RADEON_CG_SUPPORT_GFX_MGCG |
2496 : RADEON_CG_SUPPORT_GFX_MGLS |
2497 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2498 : RADEON_CG_SUPPORT_GFX_CGLS |
2499 : RADEON_CG_SUPPORT_GFX_CGTS |
2500 : RADEON_CG_SUPPORT_GFX_CP_LS |
2501 : RADEON_CG_SUPPORT_GFX_RLC_LS |
2502 : RADEON_CG_SUPPORT_MC_LS |
2503 : RADEON_CG_SUPPORT_MC_MGCG |
2504 : RADEON_CG_SUPPORT_SDMA_MGCG |
2505 : RADEON_CG_SUPPORT_BIF_LS |
2506 : RADEON_CG_SUPPORT_VCE_MGCG |
2507 : RADEON_CG_SUPPORT_UVD_MGCG |
2508 : RADEON_CG_SUPPORT_HDP_LS |
2509 : RADEON_CG_SUPPORT_HDP_MGCG;
2510 0 : rdev->pg_flags = 0;
2511 0 : break;
2512 : case CHIP_VERDE:
2513 0 : rdev->cg_flags =
2514 : RADEON_CG_SUPPORT_GFX_MGCG |
2515 : RADEON_CG_SUPPORT_GFX_MGLS |
2516 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2517 : RADEON_CG_SUPPORT_GFX_CGLS |
2518 : RADEON_CG_SUPPORT_GFX_CGTS |
2519 : RADEON_CG_SUPPORT_GFX_CP_LS |
2520 : RADEON_CG_SUPPORT_GFX_RLC_LS |
2521 : RADEON_CG_SUPPORT_MC_LS |
2522 : RADEON_CG_SUPPORT_MC_MGCG |
2523 : RADEON_CG_SUPPORT_SDMA_MGCG |
2524 : RADEON_CG_SUPPORT_BIF_LS |
2525 : RADEON_CG_SUPPORT_VCE_MGCG |
2526 : RADEON_CG_SUPPORT_UVD_MGCG |
2527 : RADEON_CG_SUPPORT_HDP_LS |
2528 : RADEON_CG_SUPPORT_HDP_MGCG;
2529 0 : rdev->pg_flags = 0 |
2530 : /*RADEON_PG_SUPPORT_GFX_PG | */
2531 : RADEON_PG_SUPPORT_SDMA;
2532 0 : break;
2533 : case CHIP_OLAND:
2534 0 : rdev->cg_flags =
2535 : RADEON_CG_SUPPORT_GFX_MGCG |
2536 : RADEON_CG_SUPPORT_GFX_MGLS |
2537 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2538 : RADEON_CG_SUPPORT_GFX_CGLS |
2539 : RADEON_CG_SUPPORT_GFX_CGTS |
2540 : RADEON_CG_SUPPORT_GFX_CP_LS |
2541 : RADEON_CG_SUPPORT_GFX_RLC_LS |
2542 : RADEON_CG_SUPPORT_MC_LS |
2543 : RADEON_CG_SUPPORT_MC_MGCG |
2544 : RADEON_CG_SUPPORT_SDMA_MGCG |
2545 : RADEON_CG_SUPPORT_BIF_LS |
2546 : RADEON_CG_SUPPORT_UVD_MGCG |
2547 : RADEON_CG_SUPPORT_HDP_LS |
2548 : RADEON_CG_SUPPORT_HDP_MGCG;
2549 0 : rdev->pg_flags = 0;
2550 0 : break;
2551 : case CHIP_HAINAN:
2552 0 : rdev->cg_flags =
2553 : RADEON_CG_SUPPORT_GFX_MGCG |
2554 : RADEON_CG_SUPPORT_GFX_MGLS |
2555 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2556 : RADEON_CG_SUPPORT_GFX_CGLS |
2557 : RADEON_CG_SUPPORT_GFX_CGTS |
2558 : RADEON_CG_SUPPORT_GFX_CP_LS |
2559 : RADEON_CG_SUPPORT_GFX_RLC_LS |
2560 : RADEON_CG_SUPPORT_MC_LS |
2561 : RADEON_CG_SUPPORT_MC_MGCG |
2562 : RADEON_CG_SUPPORT_SDMA_MGCG |
2563 : RADEON_CG_SUPPORT_BIF_LS |
2564 : RADEON_CG_SUPPORT_HDP_LS |
2565 : RADEON_CG_SUPPORT_HDP_MGCG;
2566 0 : rdev->pg_flags = 0;
2567 0 : break;
2568 : default:
2569 0 : rdev->cg_flags = 0;
2570 0 : rdev->pg_flags = 0;
2571 0 : break;
2572 : }
2573 : break;
2574 : case CHIP_BONAIRE:
2575 : case CHIP_HAWAII:
2576 0 : rdev->asic = &ci_asic;
2577 0 : rdev->num_crtc = 6;
2578 0 : rdev->has_uvd = true;
2579 0 : if (rdev->family == CHIP_BONAIRE) {
2580 0 : rdev->cg_flags =
2581 : RADEON_CG_SUPPORT_GFX_MGCG |
2582 : RADEON_CG_SUPPORT_GFX_MGLS |
2583 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2584 : RADEON_CG_SUPPORT_GFX_CGLS |
2585 : RADEON_CG_SUPPORT_GFX_CGTS |
2586 : RADEON_CG_SUPPORT_GFX_CGTS_LS |
2587 : RADEON_CG_SUPPORT_GFX_CP_LS |
2588 : RADEON_CG_SUPPORT_MC_LS |
2589 : RADEON_CG_SUPPORT_MC_MGCG |
2590 : RADEON_CG_SUPPORT_SDMA_MGCG |
2591 : RADEON_CG_SUPPORT_SDMA_LS |
2592 : RADEON_CG_SUPPORT_BIF_LS |
2593 : RADEON_CG_SUPPORT_VCE_MGCG |
2594 : RADEON_CG_SUPPORT_UVD_MGCG |
2595 : RADEON_CG_SUPPORT_HDP_LS |
2596 : RADEON_CG_SUPPORT_HDP_MGCG;
2597 0 : rdev->pg_flags = 0;
2598 0 : } else {
2599 0 : rdev->cg_flags =
2600 : RADEON_CG_SUPPORT_GFX_MGCG |
2601 : RADEON_CG_SUPPORT_GFX_MGLS |
2602 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2603 : RADEON_CG_SUPPORT_GFX_CGLS |
2604 : RADEON_CG_SUPPORT_GFX_CGTS |
2605 : RADEON_CG_SUPPORT_GFX_CP_LS |
2606 : RADEON_CG_SUPPORT_MC_LS |
2607 : RADEON_CG_SUPPORT_MC_MGCG |
2608 : RADEON_CG_SUPPORT_SDMA_MGCG |
2609 : RADEON_CG_SUPPORT_SDMA_LS |
2610 : RADEON_CG_SUPPORT_BIF_LS |
2611 : RADEON_CG_SUPPORT_VCE_MGCG |
2612 : RADEON_CG_SUPPORT_UVD_MGCG |
2613 : RADEON_CG_SUPPORT_HDP_LS |
2614 : RADEON_CG_SUPPORT_HDP_MGCG;
2615 0 : rdev->pg_flags = 0;
2616 : }
2617 : break;
2618 : case CHIP_KAVERI:
2619 : case CHIP_KABINI:
2620 : case CHIP_MULLINS:
2621 0 : rdev->asic = &kv_asic;
2622 : /* set num crtcs */
2623 0 : if (rdev->family == CHIP_KAVERI) {
2624 0 : rdev->num_crtc = 4;
2625 0 : rdev->cg_flags =
2626 : RADEON_CG_SUPPORT_GFX_MGCG |
2627 : RADEON_CG_SUPPORT_GFX_MGLS |
2628 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2629 : RADEON_CG_SUPPORT_GFX_CGLS |
2630 : RADEON_CG_SUPPORT_GFX_CGTS |
2631 : RADEON_CG_SUPPORT_GFX_CGTS_LS |
2632 : RADEON_CG_SUPPORT_GFX_CP_LS |
2633 : RADEON_CG_SUPPORT_SDMA_MGCG |
2634 : RADEON_CG_SUPPORT_SDMA_LS |
2635 : RADEON_CG_SUPPORT_BIF_LS |
2636 : RADEON_CG_SUPPORT_VCE_MGCG |
2637 : RADEON_CG_SUPPORT_UVD_MGCG |
2638 : RADEON_CG_SUPPORT_HDP_LS |
2639 : RADEON_CG_SUPPORT_HDP_MGCG;
2640 0 : rdev->pg_flags = 0;
2641 : /*RADEON_PG_SUPPORT_GFX_PG |
2642 : RADEON_PG_SUPPORT_GFX_SMG |
2643 : RADEON_PG_SUPPORT_GFX_DMG |
2644 : RADEON_PG_SUPPORT_UVD |
2645 : RADEON_PG_SUPPORT_VCE |
2646 : RADEON_PG_SUPPORT_CP |
2647 : RADEON_PG_SUPPORT_GDS |
2648 : RADEON_PG_SUPPORT_RLC_SMU_HS |
2649 : RADEON_PG_SUPPORT_ACP |
2650 : RADEON_PG_SUPPORT_SAMU;*/
2651 0 : } else {
2652 0 : rdev->num_crtc = 2;
2653 0 : rdev->cg_flags =
2654 : RADEON_CG_SUPPORT_GFX_MGCG |
2655 : RADEON_CG_SUPPORT_GFX_MGLS |
2656 : /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2657 : RADEON_CG_SUPPORT_GFX_CGLS |
2658 : RADEON_CG_SUPPORT_GFX_CGTS |
2659 : RADEON_CG_SUPPORT_GFX_CGTS_LS |
2660 : RADEON_CG_SUPPORT_GFX_CP_LS |
2661 : RADEON_CG_SUPPORT_SDMA_MGCG |
2662 : RADEON_CG_SUPPORT_SDMA_LS |
2663 : RADEON_CG_SUPPORT_BIF_LS |
2664 : RADEON_CG_SUPPORT_VCE_MGCG |
2665 : RADEON_CG_SUPPORT_UVD_MGCG |
2666 : RADEON_CG_SUPPORT_HDP_LS |
2667 : RADEON_CG_SUPPORT_HDP_MGCG;
2668 0 : rdev->pg_flags = 0;
2669 : /*RADEON_PG_SUPPORT_GFX_PG |
2670 : RADEON_PG_SUPPORT_GFX_SMG |
2671 : RADEON_PG_SUPPORT_UVD |
2672 : RADEON_PG_SUPPORT_VCE |
2673 : RADEON_PG_SUPPORT_CP |
2674 : RADEON_PG_SUPPORT_GDS |
2675 : RADEON_PG_SUPPORT_RLC_SMU_HS |
2676 : RADEON_PG_SUPPORT_SAMU;*/
2677 : }
2678 0 : rdev->has_uvd = true;
2679 0 : break;
2680 : default:
2681 : /* FIXME: not supported yet */
2682 0 : return -EINVAL;
2683 : }
2684 :
2685 0 : if (rdev->flags & RADEON_IS_IGP) {
2686 0 : rdev->asic->pm.get_memory_clock = NULL;
2687 0 : rdev->asic->pm.set_memory_clock = NULL;
2688 0 : }
2689 :
2690 0 : return 0;
2691 0 : }
2692 :
|
