Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #include <dev/pci/drm/drmP.h>
29 : #include "radeon_reg.h"
30 : #include "radeon.h"
31 : #include "atom.h"
32 :
33 : #if defined(__amd64__) || defined(__i386__)
34 : #include <dev/isa/isareg.h>
35 : #include <dev/isa/isavar.h>
36 : #endif
37 :
38 : #if defined (__loongson__)
39 : #include <machine/autoconf.h>
40 : #endif
41 :
42 : #ifdef __HAVE_ACPI
43 : #include "acpi.h"
44 : #endif
45 :
46 : /*
47 : * BIOS.
48 : */
49 :
50 : /* If you boot an IGP board with a discrete card as the primary,
51 : * the IGP rom is not accessible via the rom bar as the IGP rom is
52 : * part of the system bios. On boot, the system bios puts a
53 : * copy of the igp rom at the start of vram if a discrete card is
54 : * present.
55 : */
56 : #ifdef __linux__
57 : static bool igp_read_bios_from_vram(struct radeon_device *rdev)
58 : {
59 : uint8_t __iomem *bios;
60 : resource_size_t vram_base;
61 : resource_size_t size = 256 * 1024; /* ??? */
62 :
63 : if (!(rdev->flags & RADEON_IS_IGP))
64 : if (!radeon_card_posted(rdev))
65 : return false;
66 :
67 : rdev->bios = NULL;
68 : vram_base = pci_resource_start(rdev->pdev, 0);
69 : bios = ioremap(vram_base, size);
70 : if (!bios) {
71 : return false;
72 : }
73 :
74 : if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
75 : iounmap(bios);
76 : return false;
77 : }
78 : rdev->bios = kmalloc(size, GFP_KERNEL);
79 : if (rdev->bios == NULL) {
80 : iounmap(bios);
81 : return false;
82 : }
83 : memcpy_fromio(rdev->bios, bios, size);
84 : iounmap(bios);
85 : return true;
86 : }
87 : #else
88 0 : static bool igp_read_bios_from_vram(struct radeon_device *rdev)
89 : {
90 : uint8_t __iomem *bios;
91 : bus_size_t size = 256 * 1024; /* ??? */
92 0 : bus_space_handle_t bsh;
93 0 : bus_space_tag_t bst = rdev->memt;
94 :
95 0 : if (!(rdev->flags & RADEON_IS_IGP))
96 0 : if (!radeon_card_posted(rdev))
97 0 : return false;
98 :
99 0 : rdev->bios = NULL;
100 :
101 0 : if (bus_space_map(bst, rdev->fb_aper_offset, size, BUS_SPACE_MAP_LINEAR, &bsh) != 0)
102 0 : return false;
103 :
104 0 : bios = bus_space_vaddr(rdev->memt, bsh);
105 0 : if (bios == NULL) {
106 0 : bus_space_unmap(bst, bsh, size);
107 0 : return false;
108 : }
109 0 : if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
110 0 : bus_space_unmap(bst, bsh, size);
111 0 : return false;
112 : }
113 :
114 0 : rdev->bios = kmalloc(size, GFP_KERNEL);
115 0 : if (rdev->bios == NULL) {
116 0 : bus_space_unmap(bst, bsh, size);
117 0 : return false;
118 : }
119 0 : memcpy_fromio(rdev->bios, bios, size);
120 0 : bus_space_unmap(bst, bsh, size);
121 0 : return true;
122 0 : }
123 : #endif
124 :
125 : #ifdef __linux__
126 : static bool radeon_read_bios(struct radeon_device *rdev)
127 : {
128 : uint8_t __iomem *bios, val1, val2;
129 : size_t size;
130 :
131 : rdev->bios = NULL;
132 : /* XXX: some cards may return 0 for rom size? ddx has a workaround */
133 : bios = pci_map_rom(rdev->pdev, &size);
134 : if (!bios) {
135 : return false;
136 : }
137 :
138 : val1 = readb(&bios[0]);
139 : val2 = readb(&bios[1]);
140 :
141 : if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
142 : pci_unmap_rom(rdev->pdev, bios);
143 : return false;
144 : }
145 : rdev->bios = kzalloc(size, GFP_KERNEL);
146 : if (rdev->bios == NULL) {
147 : pci_unmap_rom(rdev->pdev, bios);
148 : return false;
149 : }
150 : memcpy_fromio(rdev->bios, bios, size);
151 : pci_unmap_rom(rdev->pdev, bios);
152 : return true;
153 : }
154 : #else
155 0 : static bool radeon_read_bios(struct radeon_device *rdev)
156 : {
157 : uint8_t __iomem *bios;
158 : bus_size_t size;
159 : pcireg_t address, mask;
160 0 : bus_space_handle_t romh;
161 : int rc;
162 :
163 0 : rdev->bios = NULL;
164 : /* XXX: some cards may return 0 for rom size? ddx has a workaround */
165 :
166 0 : address = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG);
167 0 : pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE);
168 0 : mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG);
169 0 : address |= PCI_ROM_ENABLE;
170 0 : pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, address);
171 :
172 0 : size = PCI_ROM_SIZE(mask);
173 0 : if (size == 0)
174 0 : return false;
175 0 : rc = bus_space_map(rdev->memt, PCI_ROM_ADDR(address), size,
176 : BUS_SPACE_MAP_LINEAR, &romh);
177 0 : if (rc != 0) {
178 0 : printf(": can't map PCI ROM (%d)\n", rc);
179 0 : return false;
180 : }
181 0 : bios = (uint8_t *)bus_space_vaddr(rdev->memt, romh);
182 0 : if (!bios) {
183 0 : printf(": bus_space_vaddr failed\n");
184 0 : return false;
185 : }
186 :
187 0 : if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa)
188 : goto fail;
189 0 : rdev->bios = kmalloc(size, GFP_KERNEL);
190 0 : memcpy(rdev->bios, bios, size);
191 0 : bus_space_unmap(rdev->memt, romh, size);
192 0 : return true;
193 : fail:
194 0 : bus_space_unmap(rdev->memt, romh, size);
195 0 : return false;
196 0 : }
197 :
198 : #endif
199 :
200 : #ifdef __linux__
201 : static bool radeon_read_platform_bios(struct radeon_device *rdev)
202 : {
203 : uint8_t __iomem *bios;
204 : size_t size;
205 :
206 : rdev->bios = NULL;
207 :
208 : bios = pci_platform_rom(rdev->pdev, &size);
209 : if (!bios) {
210 : return false;
211 : }
212 :
213 : if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
214 : return false;
215 : }
216 : rdev->bios = kmemdup(bios, size, GFP_KERNEL);
217 : if (rdev->bios == NULL) {
218 : return false;
219 : }
220 :
221 : return true;
222 : }
223 : #else
224 0 : static bool radeon_read_platform_bios(struct radeon_device *rdev)
225 : {
226 : #if defined(__amd64__) || defined(__i386__) || defined(__loongson__)
227 : uint8_t __iomem *bios;
228 : bus_size_t size = 256 * 1024; /* ??? */
229 : uint8_t *found = NULL;
230 : int i;
231 :
232 0 : if (!(rdev->flags & RADEON_IS_IGP))
233 0 : if (!radeon_card_posted(rdev))
234 0 : return false;
235 :
236 0 : rdev->bios = NULL;
237 :
238 : #if defined(__loongson__)
239 : if (loongson_videobios == NULL)
240 : return false;
241 : bios = loongson_videobios;
242 : #else
243 0 : bios = (u8 *)ISA_HOLE_VADDR(0xc0000);
244 : #endif
245 :
246 0 : for (i = 0; i + 2 < size; i++) {
247 0 : if (bios[i] == 0x55 && bios[i + 1] == 0xaa) {
248 : found = bios + i;
249 0 : break;
250 : }
251 :
252 : }
253 0 : if (found == NULL) {
254 0 : DRM_ERROR("bios size zero or checksum mismatch\n");
255 0 : return false;
256 : }
257 :
258 0 : rdev->bios = kmalloc(size, GFP_KERNEL);
259 0 : if (rdev->bios == NULL)
260 0 : return false;
261 :
262 0 : memcpy(rdev->bios, found, size);
263 :
264 0 : return true;
265 : #endif
266 : return false;
267 0 : }
268 : #endif
269 :
270 : #ifdef CONFIG_ACPI
271 : /* ATRM is used to get the BIOS on the discrete cards in
272 : * dual-gpu systems.
273 : */
274 : /* retrieve the ROM in 4k blocks */
275 : #define ATRM_BIOS_PAGE 4096
276 : /**
277 : * radeon_atrm_call - fetch a chunk of the vbios
278 : *
279 : * @atrm_handle: acpi ATRM handle
280 : * @bios: vbios image pointer
281 : * @offset: offset of vbios image data to fetch
282 : * @len: length of vbios image data to fetch
283 : *
284 : * Executes ATRM to fetch a chunk of the discrete
285 : * vbios image on PX systems (all asics).
286 : * Returns the length of the buffer fetched.
287 : */
288 : static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
289 : int offset, int len)
290 : {
291 : acpi_status status;
292 : union acpi_object atrm_arg_elements[2], *obj;
293 : struct acpi_object_list atrm_arg;
294 : struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
295 :
296 : atrm_arg.count = 2;
297 : atrm_arg.pointer = &atrm_arg_elements[0];
298 :
299 : atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
300 : atrm_arg_elements[0].integer.value = offset;
301 :
302 : atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
303 : atrm_arg_elements[1].integer.value = len;
304 :
305 : status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
306 : if (ACPI_FAILURE(status)) {
307 : printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
308 : return -ENODEV;
309 : }
310 :
311 : obj = (union acpi_object *)buffer.pointer;
312 : memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
313 : len = obj->buffer.length;
314 : kfree(buffer.pointer);
315 : return len;
316 : }
317 :
318 : static bool radeon_atrm_get_bios(struct radeon_device *rdev)
319 : {
320 : int ret;
321 : int size = 256 * 1024;
322 : int i;
323 : struct pci_dev *pdev = NULL;
324 : acpi_handle dhandle, atrm_handle;
325 : acpi_status status;
326 : bool found = false;
327 :
328 : /* ATRM is for the discrete card only */
329 : if (rdev->flags & RADEON_IS_IGP)
330 : return false;
331 :
332 : while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
333 : dhandle = ACPI_HANDLE(&pdev->dev);
334 : if (!dhandle)
335 : continue;
336 :
337 : status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
338 : if (!ACPI_FAILURE(status)) {
339 : found = true;
340 : break;
341 : }
342 : }
343 :
344 : if (!found) {
345 : while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
346 : dhandle = ACPI_HANDLE(&pdev->dev);
347 : if (!dhandle)
348 : continue;
349 :
350 : status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
351 : if (!ACPI_FAILURE(status)) {
352 : found = true;
353 : break;
354 : }
355 : }
356 : }
357 :
358 : if (!found)
359 : return false;
360 :
361 : rdev->bios = kmalloc(size, GFP_KERNEL);
362 : if (!rdev->bios) {
363 : DRM_ERROR("Unable to allocate bios\n");
364 : return false;
365 : }
366 :
367 : for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
368 : ret = radeon_atrm_call(atrm_handle,
369 : rdev->bios,
370 : (i * ATRM_BIOS_PAGE),
371 : ATRM_BIOS_PAGE);
372 : if (ret < ATRM_BIOS_PAGE)
373 : break;
374 : }
375 :
376 : if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
377 : kfree(rdev->bios);
378 : return false;
379 : }
380 : return true;
381 : }
382 : #else
383 0 : static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
384 : {
385 0 : return false;
386 : }
387 : #endif
388 :
389 0 : static bool ni_read_disabled_bios(struct radeon_device *rdev)
390 : {
391 : u32 bus_cntl;
392 : u32 d1vga_control;
393 : u32 d2vga_control;
394 : u32 vga_render_control;
395 : u32 rom_cntl;
396 : bool r;
397 :
398 0 : bus_cntl = RREG32(R600_BUS_CNTL);
399 0 : d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
400 0 : d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
401 0 : vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
402 0 : rom_cntl = RREG32(R600_ROM_CNTL);
403 :
404 : /* enable the rom */
405 0 : WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
406 0 : if (!ASIC_IS_NODCE(rdev)) {
407 : /* Disable VGA mode */
408 0 : WREG32(AVIVO_D1VGA_CONTROL,
409 : (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
410 : AVIVO_DVGA_CONTROL_TIMING_SELECT)));
411 0 : WREG32(AVIVO_D2VGA_CONTROL,
412 : (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
413 : AVIVO_DVGA_CONTROL_TIMING_SELECT)));
414 0 : WREG32(AVIVO_VGA_RENDER_CONTROL,
415 : (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
416 0 : }
417 0 : WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
418 :
419 0 : r = radeon_read_bios(rdev);
420 :
421 : /* restore regs */
422 0 : WREG32(R600_BUS_CNTL, bus_cntl);
423 0 : if (!ASIC_IS_NODCE(rdev)) {
424 0 : WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
425 0 : WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
426 0 : WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
427 0 : }
428 0 : WREG32(R600_ROM_CNTL, rom_cntl);
429 0 : return r;
430 : }
431 :
432 0 : static bool r700_read_disabled_bios(struct radeon_device *rdev)
433 : {
434 : uint32_t viph_control;
435 : uint32_t bus_cntl;
436 : uint32_t d1vga_control;
437 : uint32_t d2vga_control;
438 : uint32_t vga_render_control;
439 : uint32_t rom_cntl;
440 : uint32_t cg_spll_func_cntl = 0;
441 : uint32_t cg_spll_status;
442 : bool r;
443 :
444 0 : viph_control = RREG32(RADEON_VIPH_CONTROL);
445 0 : bus_cntl = RREG32(R600_BUS_CNTL);
446 0 : d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
447 0 : d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
448 0 : vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
449 0 : rom_cntl = RREG32(R600_ROM_CNTL);
450 :
451 : /* disable VIP */
452 0 : WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
453 : /* enable the rom */
454 0 : WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
455 : /* Disable VGA mode */
456 0 : WREG32(AVIVO_D1VGA_CONTROL,
457 : (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
458 : AVIVO_DVGA_CONTROL_TIMING_SELECT)));
459 0 : WREG32(AVIVO_D2VGA_CONTROL,
460 : (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
461 : AVIVO_DVGA_CONTROL_TIMING_SELECT)));
462 0 : WREG32(AVIVO_VGA_RENDER_CONTROL,
463 : (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
464 :
465 0 : if (rdev->family == CHIP_RV730) {
466 0 : cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
467 :
468 : /* enable bypass mode */
469 0 : WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
470 : R600_SPLL_BYPASS_EN));
471 :
472 : /* wait for SPLL_CHG_STATUS to change to 1 */
473 : cg_spll_status = 0;
474 0 : while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
475 0 : cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
476 :
477 0 : WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
478 0 : } else
479 0 : WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
480 :
481 0 : r = radeon_read_bios(rdev);
482 :
483 : /* restore regs */
484 0 : if (rdev->family == CHIP_RV730) {
485 0 : WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
486 :
487 : /* wait for SPLL_CHG_STATUS to change to 1 */
488 : cg_spll_status = 0;
489 0 : while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
490 0 : cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
491 : }
492 0 : WREG32(RADEON_VIPH_CONTROL, viph_control);
493 0 : WREG32(R600_BUS_CNTL, bus_cntl);
494 0 : WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
495 0 : WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
496 0 : WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
497 0 : WREG32(R600_ROM_CNTL, rom_cntl);
498 0 : return r;
499 : }
500 :
501 0 : static bool r600_read_disabled_bios(struct radeon_device *rdev)
502 : {
503 : uint32_t viph_control;
504 : uint32_t bus_cntl;
505 : uint32_t d1vga_control;
506 : uint32_t d2vga_control;
507 : uint32_t vga_render_control;
508 : uint32_t rom_cntl;
509 : uint32_t general_pwrmgt;
510 : uint32_t low_vid_lower_gpio_cntl;
511 : uint32_t medium_vid_lower_gpio_cntl;
512 : uint32_t high_vid_lower_gpio_cntl;
513 : uint32_t ctxsw_vid_lower_gpio_cntl;
514 : uint32_t lower_gpio_enable;
515 : bool r;
516 :
517 0 : viph_control = RREG32(RADEON_VIPH_CONTROL);
518 0 : bus_cntl = RREG32(R600_BUS_CNTL);
519 0 : d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
520 0 : d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
521 0 : vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
522 0 : rom_cntl = RREG32(R600_ROM_CNTL);
523 0 : general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
524 0 : low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
525 0 : medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
526 0 : high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
527 0 : ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
528 0 : lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
529 :
530 : /* disable VIP */
531 0 : WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
532 : /* enable the rom */
533 0 : WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
534 : /* Disable VGA mode */
535 0 : WREG32(AVIVO_D1VGA_CONTROL,
536 : (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
537 : AVIVO_DVGA_CONTROL_TIMING_SELECT)));
538 0 : WREG32(AVIVO_D2VGA_CONTROL,
539 : (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
540 : AVIVO_DVGA_CONTROL_TIMING_SELECT)));
541 0 : WREG32(AVIVO_VGA_RENDER_CONTROL,
542 : (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
543 :
544 0 : WREG32(R600_ROM_CNTL,
545 : ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
546 : (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
547 : R600_SCK_OVERWRITE));
548 :
549 0 : WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
550 0 : WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
551 : (low_vid_lower_gpio_cntl & ~0x400));
552 0 : WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
553 : (medium_vid_lower_gpio_cntl & ~0x400));
554 0 : WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
555 : (high_vid_lower_gpio_cntl & ~0x400));
556 0 : WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
557 : (ctxsw_vid_lower_gpio_cntl & ~0x400));
558 0 : WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
559 :
560 0 : r = radeon_read_bios(rdev);
561 :
562 : /* restore regs */
563 0 : WREG32(RADEON_VIPH_CONTROL, viph_control);
564 0 : WREG32(R600_BUS_CNTL, bus_cntl);
565 0 : WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
566 0 : WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
567 0 : WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
568 0 : WREG32(R600_ROM_CNTL, rom_cntl);
569 0 : WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
570 0 : WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
571 0 : WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
572 0 : WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
573 0 : WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
574 0 : WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
575 0 : return r;
576 : }
577 :
578 0 : static bool avivo_read_disabled_bios(struct radeon_device *rdev)
579 : {
580 : uint32_t seprom_cntl1;
581 : uint32_t viph_control;
582 : uint32_t bus_cntl;
583 : uint32_t d1vga_control;
584 : uint32_t d2vga_control;
585 : uint32_t vga_render_control;
586 : uint32_t gpiopad_a;
587 : uint32_t gpiopad_en;
588 : uint32_t gpiopad_mask;
589 : bool r;
590 :
591 0 : seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
592 0 : viph_control = RREG32(RADEON_VIPH_CONTROL);
593 0 : bus_cntl = RREG32(RV370_BUS_CNTL);
594 0 : d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
595 0 : d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
596 0 : vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
597 0 : gpiopad_a = RREG32(RADEON_GPIOPAD_A);
598 0 : gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
599 0 : gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
600 :
601 0 : WREG32(RADEON_SEPROM_CNTL1,
602 : ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
603 : (0xc << RADEON_SCK_PRESCALE_SHIFT)));
604 0 : WREG32(RADEON_GPIOPAD_A, 0);
605 0 : WREG32(RADEON_GPIOPAD_EN, 0);
606 0 : WREG32(RADEON_GPIOPAD_MASK, 0);
607 :
608 : /* disable VIP */
609 0 : WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
610 :
611 : /* enable the rom */
612 0 : WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
613 :
614 : /* Disable VGA mode */
615 0 : WREG32(AVIVO_D1VGA_CONTROL,
616 : (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
617 : AVIVO_DVGA_CONTROL_TIMING_SELECT)));
618 0 : WREG32(AVIVO_D2VGA_CONTROL,
619 : (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
620 : AVIVO_DVGA_CONTROL_TIMING_SELECT)));
621 0 : WREG32(AVIVO_VGA_RENDER_CONTROL,
622 : (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
623 :
624 0 : r = radeon_read_bios(rdev);
625 :
626 : /* restore regs */
627 0 : WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
628 0 : WREG32(RADEON_VIPH_CONTROL, viph_control);
629 0 : WREG32(RV370_BUS_CNTL, bus_cntl);
630 0 : WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
631 0 : WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
632 0 : WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
633 0 : WREG32(RADEON_GPIOPAD_A, gpiopad_a);
634 0 : WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
635 0 : WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
636 0 : return r;
637 : }
638 :
639 0 : static bool legacy_read_disabled_bios(struct radeon_device *rdev)
640 : {
641 : uint32_t seprom_cntl1;
642 : uint32_t viph_control;
643 : uint32_t bus_cntl;
644 : uint32_t crtc_gen_cntl;
645 : uint32_t crtc2_gen_cntl;
646 : uint32_t crtc_ext_cntl;
647 : uint32_t fp2_gen_cntl;
648 : bool r;
649 :
650 0 : seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
651 0 : viph_control = RREG32(RADEON_VIPH_CONTROL);
652 0 : if (rdev->flags & RADEON_IS_PCIE)
653 0 : bus_cntl = RREG32(RV370_BUS_CNTL);
654 : else
655 0 : bus_cntl = RREG32(RADEON_BUS_CNTL);
656 0 : crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
657 : crtc2_gen_cntl = 0;
658 0 : crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
659 : fp2_gen_cntl = 0;
660 :
661 0 : if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
662 0 : fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
663 0 : }
664 :
665 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
666 0 : crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
667 0 : }
668 :
669 0 : WREG32(RADEON_SEPROM_CNTL1,
670 : ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
671 : (0xc << RADEON_SCK_PRESCALE_SHIFT)));
672 :
673 : /* disable VIP */
674 0 : WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
675 :
676 : /* enable the rom */
677 0 : if (rdev->flags & RADEON_IS_PCIE)
678 0 : WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
679 : else
680 0 : WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
681 :
682 : /* Turn off mem requests and CRTC for both controllers */
683 0 : WREG32(RADEON_CRTC_GEN_CNTL,
684 : ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
685 : (RADEON_CRTC_DISP_REQ_EN_B |
686 : RADEON_CRTC_EXT_DISP_EN)));
687 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
688 0 : WREG32(RADEON_CRTC2_GEN_CNTL,
689 : ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
690 : RADEON_CRTC2_DISP_REQ_EN_B));
691 0 : }
692 : /* Turn off CRTC */
693 0 : WREG32(RADEON_CRTC_EXT_CNTL,
694 : ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
695 : (RADEON_CRTC_SYNC_TRISTAT |
696 : RADEON_CRTC_DISPLAY_DIS)));
697 :
698 0 : if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
699 0 : WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
700 0 : }
701 :
702 0 : r = radeon_read_bios(rdev);
703 :
704 : /* restore regs */
705 0 : WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
706 0 : WREG32(RADEON_VIPH_CONTROL, viph_control);
707 0 : if (rdev->flags & RADEON_IS_PCIE)
708 0 : WREG32(RV370_BUS_CNTL, bus_cntl);
709 : else
710 0 : WREG32(RADEON_BUS_CNTL, bus_cntl);
711 0 : WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
712 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
713 0 : WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
714 0 : }
715 0 : WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
716 0 : if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
717 0 : WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
718 0 : }
719 0 : return r;
720 : }
721 :
722 0 : static bool radeon_read_disabled_bios(struct radeon_device *rdev)
723 : {
724 0 : if (rdev->flags & RADEON_IS_IGP)
725 0 : return igp_read_bios_from_vram(rdev);
726 0 : else if (rdev->family >= CHIP_BARTS)
727 0 : return ni_read_disabled_bios(rdev);
728 0 : else if (rdev->family >= CHIP_RV770)
729 0 : return r700_read_disabled_bios(rdev);
730 0 : else if (rdev->family >= CHIP_R600)
731 0 : return r600_read_disabled_bios(rdev);
732 0 : else if (rdev->family >= CHIP_RS600)
733 0 : return avivo_read_disabled_bios(rdev);
734 : else
735 0 : return legacy_read_disabled_bios(rdev);
736 0 : }
737 :
738 : #if NACPI > 0
739 : #define CONFIG_ACPI
740 : #endif
741 :
742 : #ifdef CONFIG_ACPI
743 0 : static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
744 : {
745 : bool ret = false;
746 0 : struct acpi_table_header *hdr;
747 0 : acpi_size tbl_size;
748 : UEFI_ACPI_VFCT *vfct;
749 : GOP_VBIOS_CONTENT *vbios;
750 : VFCT_IMAGE_HEADER *vhdr;
751 :
752 0 : if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
753 0 : return false;
754 0 : if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
755 0 : DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
756 0 : goto out_unmap;
757 : }
758 :
759 0 : vfct = (UEFI_ACPI_VFCT *)hdr;
760 0 : if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
761 0 : DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
762 0 : goto out_unmap;
763 : }
764 :
765 0 : vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
766 0 : vhdr = &vbios->VbiosHeader;
767 : DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
768 : vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
769 : vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
770 :
771 0 : if (vhdr->PCIBus != rdev->pdev->bus->number ||
772 0 : vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
773 0 : vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
774 0 : vhdr->VendorID != rdev->pdev->vendor ||
775 0 : vhdr->DeviceID != rdev->pdev->device) {
776 : DRM_INFO("ACPI VFCT table is not for this card\n");
777 : goto out_unmap;
778 : }
779 :
780 0 : if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
781 0 : DRM_ERROR("ACPI VFCT image truncated\n");
782 0 : goto out_unmap;
783 : }
784 :
785 0 : rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
786 0 : ret = !!rdev->bios;
787 :
788 : out_unmap:
789 0 : return ret;
790 0 : }
791 : #else
792 : static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
793 : {
794 : return false;
795 : }
796 : #endif
797 :
798 0 : bool radeon_get_bios(struct radeon_device *rdev)
799 : {
800 : bool r;
801 : uint16_t tmp;
802 :
803 0 : r = radeon_atrm_get_bios(rdev);
804 0 : if (r == false)
805 0 : r = radeon_acpi_vfct_bios(rdev);
806 0 : if (r == false)
807 0 : r = igp_read_bios_from_vram(rdev);
808 0 : if (r == false)
809 0 : r = radeon_read_bios(rdev);
810 0 : if (r == false)
811 0 : r = radeon_read_disabled_bios(rdev);
812 0 : if (r == false)
813 0 : r = radeon_read_platform_bios(rdev);
814 0 : if (r == false || rdev->bios == NULL) {
815 0 : DRM_ERROR("Unable to locate a BIOS ROM\n");
816 0 : rdev->bios = NULL;
817 0 : return false;
818 : }
819 0 : if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
820 0 : printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
821 0 : goto free_bios;
822 : }
823 :
824 0 : tmp = RBIOS16(0x18);
825 0 : if (RBIOS8(tmp + 0x14) != 0x0) {
826 : DRM_INFO("Not an x86 BIOS ROM, not using.\n");
827 : goto free_bios;
828 : }
829 :
830 0 : rdev->bios_header_start = RBIOS16(0x48);
831 0 : if (!rdev->bios_header_start) {
832 : goto free_bios;
833 : }
834 0 : tmp = rdev->bios_header_start + 4;
835 0 : if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
836 0 : !memcmp(rdev->bios + tmp, "MOTA", 4)) {
837 0 : rdev->is_atom_bios = true;
838 0 : } else {
839 0 : rdev->is_atom_bios = false;
840 : }
841 :
842 : DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
843 0 : return true;
844 : free_bios:
845 0 : kfree(rdev->bios);
846 0 : rdev->bios = NULL;
847 0 : return false;
848 0 : }
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