Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #include <dev/pci/drm/drmP.h>
29 : #include <dev/pci/drm/radeon_drm.h>
30 : #include "radeon_reg.h"
31 : #include "radeon.h"
32 : #include "atom.h"
33 :
34 : #if defined(__macppc__) || defined(__sparc64__)
35 : #include <dev/ofw/openfirm.h>
36 : #endif
37 :
38 : /* 10 khz */
39 0 : uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
40 : {
41 0 : struct radeon_pll *spll = &rdev->clock.spll;
42 : uint32_t fb_div, ref_div, post_div, sclk;
43 :
44 0 : fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
45 0 : fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
46 0 : fb_div <<= 1;
47 0 : fb_div *= spll->reference_freq;
48 :
49 : ref_div =
50 0 : RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
51 :
52 0 : if (ref_div == 0)
53 0 : return 0;
54 :
55 0 : sclk = fb_div / ref_div;
56 :
57 0 : post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
58 0 : if (post_div == 2)
59 0 : sclk >>= 1;
60 0 : else if (post_div == 3)
61 0 : sclk >>= 2;
62 0 : else if (post_div == 4)
63 0 : sclk >>= 3;
64 :
65 0 : return sclk;
66 0 : }
67 :
68 : /* 10 khz */
69 0 : uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
70 : {
71 0 : struct radeon_pll *mpll = &rdev->clock.mpll;
72 : uint32_t fb_div, ref_div, post_div, mclk;
73 :
74 0 : fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
75 0 : fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
76 0 : fb_div <<= 1;
77 0 : fb_div *= mpll->reference_freq;
78 :
79 : ref_div =
80 0 : RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
81 :
82 0 : if (ref_div == 0)
83 0 : return 0;
84 :
85 0 : mclk = fb_div / ref_div;
86 :
87 0 : post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
88 0 : if (post_div == 2)
89 0 : mclk >>= 1;
90 0 : else if (post_div == 3)
91 0 : mclk >>= 2;
92 0 : else if (post_div == 4)
93 0 : mclk >>= 3;
94 :
95 0 : return mclk;
96 0 : }
97 :
98 : #ifdef __linux__
99 :
100 : #ifdef CONFIG_OF
101 : /*
102 : * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
103 : * tree. Hopefully, ATI OF driver is kind enough to fill these
104 : */
105 : static bool radeon_read_clocks_OF(struct drm_device *dev)
106 : {
107 : struct radeon_device *rdev = dev->dev_private;
108 : struct device_node *dp = rdev->pdev->dev.of_node;
109 : const u32 *val;
110 : struct radeon_pll *p1pll = &rdev->clock.p1pll;
111 : struct radeon_pll *p2pll = &rdev->clock.p2pll;
112 : struct radeon_pll *spll = &rdev->clock.spll;
113 : struct radeon_pll *mpll = &rdev->clock.mpll;
114 :
115 : if (dp == NULL)
116 : return false;
117 : val = of_get_property(dp, "ATY,RefCLK", NULL);
118 : if (!val || !*val) {
119 : printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
120 : return false;
121 : }
122 : p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
123 : p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
124 : if (p1pll->reference_div < 2)
125 : p1pll->reference_div = 12;
126 : p2pll->reference_div = p1pll->reference_div;
127 :
128 : /* These aren't in the device-tree */
129 : if (rdev->family >= CHIP_R420) {
130 : p1pll->pll_in_min = 100;
131 : p1pll->pll_in_max = 1350;
132 : p1pll->pll_out_min = 20000;
133 : p1pll->pll_out_max = 50000;
134 : p2pll->pll_in_min = 100;
135 : p2pll->pll_in_max = 1350;
136 : p2pll->pll_out_min = 20000;
137 : p2pll->pll_out_max = 50000;
138 : } else {
139 : p1pll->pll_in_min = 40;
140 : p1pll->pll_in_max = 500;
141 : p1pll->pll_out_min = 12500;
142 : p1pll->pll_out_max = 35000;
143 : p2pll->pll_in_min = 40;
144 : p2pll->pll_in_max = 500;
145 : p2pll->pll_out_min = 12500;
146 : p2pll->pll_out_max = 35000;
147 : }
148 : /* not sure what the max should be in all cases */
149 : rdev->clock.max_pixel_clock = 35000;
150 :
151 : spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
152 : spll->reference_div = mpll->reference_div =
153 : RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
154 : RADEON_M_SPLL_REF_DIV_MASK;
155 :
156 : val = of_get_property(dp, "ATY,SCLK", NULL);
157 : if (val && *val)
158 : rdev->clock.default_sclk = (*val) / 10;
159 : else
160 : rdev->clock.default_sclk =
161 : radeon_legacy_get_engine_clock(rdev);
162 :
163 : val = of_get_property(dp, "ATY,MCLK", NULL);
164 : if (val && *val)
165 : rdev->clock.default_mclk = (*val) / 10;
166 : else
167 : rdev->clock.default_mclk =
168 : radeon_legacy_get_memory_clock(rdev);
169 :
170 : DRM_INFO("Using device-tree clock info\n");
171 :
172 : return true;
173 : }
174 : #else
175 : static bool radeon_read_clocks_OF(struct drm_device *dev)
176 : {
177 : return false;
178 : }
179 : #endif /* CONFIG_OF */
180 :
181 : #else
182 :
183 : #if defined(__macppc__) || defined(__sparc64__)
184 : /*
185 : * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
186 : * tree. Hopefully, ATI OF driver is kind enough to fill these
187 : */
188 : static bool radeon_read_clocks_OF(struct drm_device *dev)
189 : {
190 : struct radeon_device *rdev = dev->dev_private;
191 : int node = PCITAG_NODE(rdev->pa_tag);
192 : uint32_t val;
193 : struct radeon_pll *p1pll = &rdev->clock.p1pll;
194 : struct radeon_pll *p2pll = &rdev->clock.p2pll;
195 : struct radeon_pll *spll = &rdev->clock.spll;
196 : struct radeon_pll *mpll = &rdev->clock.mpll;
197 :
198 : if (OF_getprop(node, "ATY,RefCLK", &val, sizeof(val)) != sizeof(val) || !val)
199 : return false;
200 : p1pll->reference_freq = p2pll->reference_freq = (val) / 10;
201 : p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
202 : if (p1pll->reference_div < 2)
203 : p1pll->reference_div = 12;
204 : p2pll->reference_div = p1pll->reference_div;
205 :
206 : /* These aren't in the device-tree */
207 : if (rdev->family >= CHIP_R420) {
208 : p1pll->pll_in_min = 100;
209 : p1pll->pll_in_max = 1350;
210 : p1pll->pll_out_min = 20000;
211 : p1pll->pll_out_max = 50000;
212 : p2pll->pll_in_min = 100;
213 : p2pll->pll_in_max = 1350;
214 : p2pll->pll_out_min = 20000;
215 : p2pll->pll_out_max = 50000;
216 : } else {
217 : p1pll->pll_in_min = 40;
218 : p1pll->pll_in_max = 500;
219 : p1pll->pll_out_min = 12500;
220 : p1pll->pll_out_max = 35000;
221 : p2pll->pll_in_min = 40;
222 : p2pll->pll_in_max = 500;
223 : p2pll->pll_out_min = 12500;
224 : p2pll->pll_out_max = 35000;
225 : }
226 : /* not sure what the max should be in all cases */
227 : rdev->clock.max_pixel_clock = 35000;
228 :
229 : spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
230 : spll->reference_div = mpll->reference_div =
231 : RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
232 : RADEON_M_SPLL_REF_DIV_MASK;
233 :
234 : if (OF_getprop(node, "ATY,SCLK", &val, sizeof(val)) == sizeof(val) && val)
235 : rdev->clock.default_sclk = (val) / 10;
236 : else
237 : rdev->clock.default_sclk =
238 : radeon_legacy_get_engine_clock(rdev);
239 :
240 : if (OF_getprop(node, "ATY,MCLK", &val, sizeof(val)) == sizeof(val) && val)
241 : rdev->clock.default_mclk = (val) / 10;
242 : else
243 : rdev->clock.default_mclk =
244 : radeon_legacy_get_memory_clock(rdev);
245 :
246 : DRM_INFO("Using device-tree clock info\n");
247 :
248 : return true;
249 : }
250 : #else
251 0 : static bool radeon_read_clocks_OF(struct drm_device *dev)
252 : {
253 0 : return false;
254 : }
255 : #endif /* CONFIG_OF */
256 :
257 : #endif
258 :
259 0 : void radeon_get_clock_info(struct drm_device *dev)
260 : {
261 0 : struct radeon_device *rdev = dev->dev_private;
262 0 : struct radeon_pll *p1pll = &rdev->clock.p1pll;
263 0 : struct radeon_pll *p2pll = &rdev->clock.p2pll;
264 0 : struct radeon_pll *dcpll = &rdev->clock.dcpll;
265 0 : struct radeon_pll *spll = &rdev->clock.spll;
266 0 : struct radeon_pll *mpll = &rdev->clock.mpll;
267 : int ret;
268 :
269 0 : if (rdev->is_atom_bios)
270 0 : ret = radeon_atom_get_clock_info(dev);
271 : else
272 0 : ret = radeon_combios_get_clock_info(dev);
273 0 : if (!ret)
274 0 : ret = radeon_read_clocks_OF(dev);
275 :
276 0 : if (ret) {
277 0 : if (p1pll->reference_div < 2) {
278 0 : if (!ASIC_IS_AVIVO(rdev)) {
279 0 : u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV);
280 0 : if (ASIC_IS_R300(rdev))
281 0 : p1pll->reference_div =
282 0 : (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
283 : else
284 0 : p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
285 0 : if (p1pll->reference_div < 2)
286 0 : p1pll->reference_div = 12;
287 0 : } else
288 0 : p1pll->reference_div = 12;
289 : }
290 0 : if (p2pll->reference_div < 2)
291 0 : p2pll->reference_div = 12;
292 0 : if (rdev->family < CHIP_RS600) {
293 0 : if (spll->reference_div < 2)
294 0 : spll->reference_div =
295 0 : RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
296 : RADEON_M_SPLL_REF_DIV_MASK;
297 : }
298 0 : if (mpll->reference_div < 2)
299 0 : mpll->reference_div = spll->reference_div;
300 : } else {
301 0 : if (ASIC_IS_AVIVO(rdev)) {
302 : /* TODO FALLBACK */
303 : } else {
304 : DRM_INFO("Using generic clock info\n");
305 :
306 : /* may need to be per card */
307 0 : rdev->clock.max_pixel_clock = 35000;
308 :
309 0 : if (rdev->flags & RADEON_IS_IGP) {
310 0 : p1pll->reference_freq = 1432;
311 0 : p2pll->reference_freq = 1432;
312 0 : spll->reference_freq = 1432;
313 0 : mpll->reference_freq = 1432;
314 0 : } else {
315 0 : p1pll->reference_freq = 2700;
316 0 : p2pll->reference_freq = 2700;
317 0 : spll->reference_freq = 2700;
318 0 : mpll->reference_freq = 2700;
319 : }
320 0 : p1pll->reference_div =
321 0 : RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
322 0 : if (p1pll->reference_div < 2)
323 0 : p1pll->reference_div = 12;
324 0 : p2pll->reference_div = p1pll->reference_div;
325 :
326 0 : if (rdev->family >= CHIP_R420) {
327 0 : p1pll->pll_in_min = 100;
328 0 : p1pll->pll_in_max = 1350;
329 0 : p1pll->pll_out_min = 20000;
330 0 : p1pll->pll_out_max = 50000;
331 0 : p2pll->pll_in_min = 100;
332 0 : p2pll->pll_in_max = 1350;
333 0 : p2pll->pll_out_min = 20000;
334 0 : p2pll->pll_out_max = 50000;
335 0 : } else {
336 0 : p1pll->pll_in_min = 40;
337 0 : p1pll->pll_in_max = 500;
338 0 : p1pll->pll_out_min = 12500;
339 0 : p1pll->pll_out_max = 35000;
340 0 : p2pll->pll_in_min = 40;
341 0 : p2pll->pll_in_max = 500;
342 0 : p2pll->pll_out_min = 12500;
343 0 : p2pll->pll_out_max = 35000;
344 : }
345 :
346 0 : spll->reference_div =
347 0 : RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
348 : RADEON_M_SPLL_REF_DIV_MASK;
349 0 : mpll->reference_div = spll->reference_div;
350 0 : rdev->clock.default_sclk =
351 0 : radeon_legacy_get_engine_clock(rdev);
352 0 : rdev->clock.default_mclk =
353 0 : radeon_legacy_get_memory_clock(rdev);
354 : }
355 : }
356 :
357 : /* pixel clocks */
358 0 : if (ASIC_IS_AVIVO(rdev)) {
359 0 : p1pll->min_post_div = 2;
360 0 : p1pll->max_post_div = 0x7f;
361 0 : p1pll->min_frac_feedback_div = 0;
362 0 : p1pll->max_frac_feedback_div = 9;
363 0 : p2pll->min_post_div = 2;
364 0 : p2pll->max_post_div = 0x7f;
365 0 : p2pll->min_frac_feedback_div = 0;
366 0 : p2pll->max_frac_feedback_div = 9;
367 0 : } else {
368 0 : p1pll->min_post_div = 1;
369 0 : p1pll->max_post_div = 16;
370 0 : p1pll->min_frac_feedback_div = 0;
371 0 : p1pll->max_frac_feedback_div = 0;
372 0 : p2pll->min_post_div = 1;
373 0 : p2pll->max_post_div = 12;
374 0 : p2pll->min_frac_feedback_div = 0;
375 0 : p2pll->max_frac_feedback_div = 0;
376 : }
377 :
378 : /* dcpll is DCE4 only */
379 0 : dcpll->min_post_div = 2;
380 0 : dcpll->max_post_div = 0x7f;
381 0 : dcpll->min_frac_feedback_div = 0;
382 0 : dcpll->max_frac_feedback_div = 9;
383 0 : dcpll->min_ref_div = 2;
384 0 : dcpll->max_ref_div = 0x3ff;
385 0 : dcpll->min_feedback_div = 4;
386 0 : dcpll->max_feedback_div = 0xfff;
387 0 : dcpll->best_vco = 0;
388 :
389 0 : p1pll->min_ref_div = 2;
390 0 : p1pll->max_ref_div = 0x3ff;
391 0 : p1pll->min_feedback_div = 4;
392 0 : p1pll->max_feedback_div = 0x7ff;
393 0 : p1pll->best_vco = 0;
394 :
395 0 : p2pll->min_ref_div = 2;
396 0 : p2pll->max_ref_div = 0x3ff;
397 0 : p2pll->min_feedback_div = 4;
398 0 : p2pll->max_feedback_div = 0x7ff;
399 0 : p2pll->best_vco = 0;
400 :
401 : /* system clock */
402 0 : spll->min_post_div = 1;
403 0 : spll->max_post_div = 1;
404 0 : spll->min_ref_div = 2;
405 0 : spll->max_ref_div = 0xff;
406 0 : spll->min_feedback_div = 4;
407 0 : spll->max_feedback_div = 0xff;
408 0 : spll->best_vco = 0;
409 :
410 : /* memory clock */
411 0 : mpll->min_post_div = 1;
412 0 : mpll->max_post_div = 1;
413 0 : mpll->min_ref_div = 2;
414 0 : mpll->max_ref_div = 0xff;
415 0 : mpll->min_feedback_div = 4;
416 0 : mpll->max_feedback_div = 0xff;
417 0 : mpll->best_vco = 0;
418 :
419 0 : if (!rdev->clock.default_sclk)
420 0 : rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
421 0 : if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)
422 0 : rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
423 :
424 0 : rdev->pm.current_sclk = rdev->clock.default_sclk;
425 0 : rdev->pm.current_mclk = rdev->clock.default_mclk;
426 :
427 0 : }
428 :
429 : /* 10 khz */
430 0 : static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
431 : uint32_t req_clock,
432 : int *fb_div, int *post_div)
433 : {
434 0 : struct radeon_pll *spll = &rdev->clock.spll;
435 0 : int ref_div = spll->reference_div;
436 :
437 0 : if (!ref_div)
438 0 : ref_div =
439 0 : RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
440 : RADEON_M_SPLL_REF_DIV_MASK;
441 :
442 0 : if (req_clock < 15000) {
443 0 : *post_div = 8;
444 0 : req_clock *= 8;
445 0 : } else if (req_clock < 30000) {
446 0 : *post_div = 4;
447 0 : req_clock *= 4;
448 0 : } else if (req_clock < 60000) {
449 0 : *post_div = 2;
450 0 : req_clock *= 2;
451 0 : } else
452 0 : *post_div = 1;
453 :
454 0 : req_clock *= ref_div;
455 0 : req_clock += spll->reference_freq;
456 0 : req_clock /= (2 * spll->reference_freq);
457 :
458 0 : *fb_div = req_clock & 0xff;
459 :
460 0 : req_clock = (req_clock & 0xffff) << 1;
461 0 : req_clock *= spll->reference_freq;
462 0 : req_clock /= ref_div;
463 0 : req_clock /= *post_div;
464 :
465 0 : return req_clock;
466 : }
467 :
468 : /* 10 khz */
469 0 : void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
470 : uint32_t eng_clock)
471 : {
472 : uint32_t tmp;
473 0 : int fb_div, post_div;
474 :
475 : /* XXX: wait for idle */
476 :
477 0 : eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
478 :
479 0 : tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
480 0 : tmp &= ~RADEON_DONT_USE_XTALIN;
481 0 : WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
482 :
483 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
484 0 : tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
485 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
486 :
487 0 : udelay(10);
488 :
489 0 : tmp = RREG32_PLL(RADEON_SPLL_CNTL);
490 0 : tmp |= RADEON_SPLL_SLEEP;
491 0 : WREG32_PLL(RADEON_SPLL_CNTL, tmp);
492 :
493 0 : udelay(2);
494 :
495 0 : tmp = RREG32_PLL(RADEON_SPLL_CNTL);
496 0 : tmp |= RADEON_SPLL_RESET;
497 0 : WREG32_PLL(RADEON_SPLL_CNTL, tmp);
498 :
499 0 : udelay(200);
500 :
501 0 : tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
502 0 : tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
503 0 : tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
504 0 : WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
505 :
506 : /* XXX: verify on different asics */
507 0 : tmp = RREG32_PLL(RADEON_SPLL_CNTL);
508 0 : tmp &= ~RADEON_SPLL_PVG_MASK;
509 0 : if ((eng_clock * post_div) >= 90000)
510 0 : tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
511 : else
512 0 : tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
513 0 : WREG32_PLL(RADEON_SPLL_CNTL, tmp);
514 :
515 0 : tmp = RREG32_PLL(RADEON_SPLL_CNTL);
516 0 : tmp &= ~RADEON_SPLL_SLEEP;
517 0 : WREG32_PLL(RADEON_SPLL_CNTL, tmp);
518 :
519 0 : udelay(2);
520 :
521 0 : tmp = RREG32_PLL(RADEON_SPLL_CNTL);
522 0 : tmp &= ~RADEON_SPLL_RESET;
523 0 : WREG32_PLL(RADEON_SPLL_CNTL, tmp);
524 :
525 0 : udelay(200);
526 :
527 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
528 0 : tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
529 0 : switch (post_div) {
530 : case 1:
531 : default:
532 0 : tmp |= 1;
533 0 : break;
534 : case 2:
535 0 : tmp |= 2;
536 0 : break;
537 : case 4:
538 0 : tmp |= 3;
539 0 : break;
540 : case 8:
541 0 : tmp |= 4;
542 0 : break;
543 : }
544 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
545 :
546 0 : udelay(20);
547 :
548 0 : tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
549 0 : tmp |= RADEON_DONT_USE_XTALIN;
550 0 : WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
551 :
552 0 : udelay(10);
553 0 : }
554 :
555 0 : void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
556 : {
557 : uint32_t tmp;
558 :
559 0 : if (enable) {
560 0 : if (rdev->flags & RADEON_SINGLE_CRTC) {
561 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
562 0 : if ((RREG32(RADEON_CONFIG_CNTL) &
563 0 : RADEON_CFG_ATI_REV_ID_MASK) >
564 : RADEON_CFG_ATI_REV_A13) {
565 0 : tmp &=
566 : ~(RADEON_SCLK_FORCE_CP |
567 : RADEON_SCLK_FORCE_RB);
568 0 : }
569 0 : tmp &=
570 : ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
571 : RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
572 : RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
573 : RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
574 : RADEON_SCLK_FORCE_TDM);
575 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
576 0 : } else if (ASIC_IS_R300(rdev)) {
577 0 : if ((rdev->family == CHIP_RS400) ||
578 0 : (rdev->family == CHIP_RS480)) {
579 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
580 0 : tmp &=
581 : ~(RADEON_SCLK_FORCE_DISP2 |
582 : RADEON_SCLK_FORCE_CP |
583 : RADEON_SCLK_FORCE_HDP |
584 : RADEON_SCLK_FORCE_DISP1 |
585 : RADEON_SCLK_FORCE_TOP |
586 : RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
587 : | RADEON_SCLK_FORCE_IDCT |
588 : RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
589 : | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
590 : | R300_SCLK_FORCE_US |
591 : RADEON_SCLK_FORCE_TV_SCLK |
592 : R300_SCLK_FORCE_SU |
593 : RADEON_SCLK_FORCE_OV0);
594 0 : tmp |= RADEON_DYN_STOP_LAT_MASK;
595 0 : tmp |=
596 : RADEON_SCLK_FORCE_TOP |
597 : RADEON_SCLK_FORCE_VIP;
598 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
599 :
600 0 : tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
601 0 : tmp &= ~RADEON_SCLK_MORE_FORCEON;
602 0 : tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
603 0 : WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
604 :
605 0 : tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
606 0 : tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
607 : RADEON_PIXCLK_DAC_ALWAYS_ONb);
608 0 : WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
609 :
610 0 : tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
611 0 : tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
612 : RADEON_PIX2CLK_DAC_ALWAYS_ONb |
613 : RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
614 : R300_DVOCLK_ALWAYS_ONb |
615 : RADEON_PIXCLK_BLEND_ALWAYS_ONb |
616 : RADEON_PIXCLK_GV_ALWAYS_ONb |
617 : R300_PIXCLK_DVO_ALWAYS_ONb |
618 : RADEON_PIXCLK_LVDS_ALWAYS_ONb |
619 : RADEON_PIXCLK_TMDS_ALWAYS_ONb |
620 : R300_PIXCLK_TRANS_ALWAYS_ONb |
621 : R300_PIXCLK_TVO_ALWAYS_ONb |
622 : R300_P2G2CLK_ALWAYS_ONb |
623 : R300_P2G2CLK_DAC_ALWAYS_ONb);
624 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
625 0 : } else if (rdev->family >= CHIP_RV350) {
626 0 : tmp = RREG32_PLL(R300_SCLK_CNTL2);
627 0 : tmp &= ~(R300_SCLK_FORCE_TCL |
628 : R300_SCLK_FORCE_GA |
629 : R300_SCLK_FORCE_CBA);
630 0 : tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
631 : R300_SCLK_GA_MAX_DYN_STOP_LAT |
632 : R300_SCLK_CBA_MAX_DYN_STOP_LAT);
633 0 : WREG32_PLL(R300_SCLK_CNTL2, tmp);
634 :
635 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
636 0 : tmp &=
637 : ~(RADEON_SCLK_FORCE_DISP2 |
638 : RADEON_SCLK_FORCE_CP |
639 : RADEON_SCLK_FORCE_HDP |
640 : RADEON_SCLK_FORCE_DISP1 |
641 : RADEON_SCLK_FORCE_TOP |
642 : RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
643 : | RADEON_SCLK_FORCE_IDCT |
644 : RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
645 : | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
646 : | R300_SCLK_FORCE_US |
647 : RADEON_SCLK_FORCE_TV_SCLK |
648 : R300_SCLK_FORCE_SU |
649 : RADEON_SCLK_FORCE_OV0);
650 0 : tmp |= RADEON_DYN_STOP_LAT_MASK;
651 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
652 :
653 0 : tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
654 0 : tmp &= ~RADEON_SCLK_MORE_FORCEON;
655 0 : tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
656 0 : WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
657 :
658 0 : tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
659 0 : tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
660 : RADEON_PIXCLK_DAC_ALWAYS_ONb);
661 0 : WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
662 :
663 0 : tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
664 0 : tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
665 : RADEON_PIX2CLK_DAC_ALWAYS_ONb |
666 : RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
667 : R300_DVOCLK_ALWAYS_ONb |
668 : RADEON_PIXCLK_BLEND_ALWAYS_ONb |
669 : RADEON_PIXCLK_GV_ALWAYS_ONb |
670 : R300_PIXCLK_DVO_ALWAYS_ONb |
671 : RADEON_PIXCLK_LVDS_ALWAYS_ONb |
672 : RADEON_PIXCLK_TMDS_ALWAYS_ONb |
673 : R300_PIXCLK_TRANS_ALWAYS_ONb |
674 : R300_PIXCLK_TVO_ALWAYS_ONb |
675 : R300_P2G2CLK_ALWAYS_ONb |
676 : R300_P2G2CLK_DAC_ALWAYS_ONb);
677 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
678 :
679 0 : tmp = RREG32_PLL(RADEON_MCLK_MISC);
680 0 : tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
681 : RADEON_IO_MCLK_DYN_ENABLE);
682 0 : WREG32_PLL(RADEON_MCLK_MISC, tmp);
683 :
684 0 : tmp = RREG32_PLL(RADEON_MCLK_CNTL);
685 0 : tmp |= (RADEON_FORCEON_MCLKA |
686 : RADEON_FORCEON_MCLKB);
687 :
688 0 : tmp &= ~(RADEON_FORCEON_YCLKA |
689 : RADEON_FORCEON_YCLKB |
690 : RADEON_FORCEON_MC);
691 :
692 : /* Some releases of vbios have set DISABLE_MC_MCLKA
693 : and DISABLE_MC_MCLKB bits in the vbios table. Setting these
694 : bits will cause H/W hang when reading video memory with dynamic clocking
695 : enabled. */
696 0 : if ((tmp & R300_DISABLE_MC_MCLKA) &&
697 : (tmp & R300_DISABLE_MC_MCLKB)) {
698 : /* If both bits are set, then check the active channels */
699 0 : tmp = RREG32_PLL(RADEON_MCLK_CNTL);
700 0 : if (rdev->mc.vram_width == 64) {
701 0 : if (RREG32(RADEON_MEM_CNTL) &
702 : R300_MEM_USE_CD_CH_ONLY)
703 : tmp &=
704 : ~R300_DISABLE_MC_MCLKB;
705 : else
706 : tmp &=
707 : ~R300_DISABLE_MC_MCLKA;
708 0 : } else {
709 0 : tmp &= ~(R300_DISABLE_MC_MCLKA |
710 : R300_DISABLE_MC_MCLKB);
711 : }
712 : }
713 :
714 0 : WREG32_PLL(RADEON_MCLK_CNTL, tmp);
715 0 : } else {
716 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
717 0 : tmp &= ~(R300_SCLK_FORCE_VAP);
718 0 : tmp |= RADEON_SCLK_FORCE_CP;
719 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
720 0 : mdelay(15);
721 :
722 0 : tmp = RREG32_PLL(R300_SCLK_CNTL2);
723 0 : tmp &= ~(R300_SCLK_FORCE_TCL |
724 : R300_SCLK_FORCE_GA |
725 : R300_SCLK_FORCE_CBA);
726 0 : WREG32_PLL(R300_SCLK_CNTL2, tmp);
727 : }
728 : } else {
729 0 : tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
730 :
731 0 : tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
732 : RADEON_DISP_DYN_STOP_LAT_MASK |
733 : RADEON_DYN_STOP_MODE_MASK);
734 :
735 0 : tmp |= (RADEON_ENGIN_DYNCLK_MODE |
736 : (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
737 0 : WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
738 0 : mdelay(15);
739 :
740 0 : tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
741 0 : tmp |= RADEON_SCLK_DYN_START_CNTL;
742 0 : WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
743 0 : mdelay(15);
744 :
745 : /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
746 : to lockup randomly, leave them as set by BIOS.
747 : */
748 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
749 : /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
750 0 : tmp &= ~RADEON_SCLK_FORCEON_MASK;
751 :
752 : /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
753 0 : if (((rdev->family == CHIP_RV250) &&
754 0 : ((RREG32(RADEON_CONFIG_CNTL) &
755 0 : RADEON_CFG_ATI_REV_ID_MASK) <
756 : RADEON_CFG_ATI_REV_A13))
757 0 : || ((rdev->family == CHIP_RV100)
758 0 : &&
759 0 : ((RREG32(RADEON_CONFIG_CNTL) &
760 0 : RADEON_CFG_ATI_REV_ID_MASK) <=
761 : RADEON_CFG_ATI_REV_A13))) {
762 0 : tmp |= RADEON_SCLK_FORCE_CP;
763 0 : tmp |= RADEON_SCLK_FORCE_VIP;
764 0 : }
765 :
766 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
767 :
768 0 : if ((rdev->family == CHIP_RV200) ||
769 0 : (rdev->family == CHIP_RV250) ||
770 0 : (rdev->family == CHIP_RV280)) {
771 0 : tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
772 0 : tmp &= ~RADEON_SCLK_MORE_FORCEON;
773 :
774 : /* RV200::A11 A12 RV250::A11 A12 */
775 0 : if (((rdev->family == CHIP_RV200) ||
776 0 : (rdev->family == CHIP_RV250)) &&
777 0 : ((RREG32(RADEON_CONFIG_CNTL) &
778 0 : RADEON_CFG_ATI_REV_ID_MASK) <
779 : RADEON_CFG_ATI_REV_A13)) {
780 0 : tmp |= RADEON_SCLK_MORE_FORCEON;
781 0 : }
782 0 : WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
783 0 : mdelay(15);
784 0 : }
785 :
786 : /* RV200::A11 A12, RV250::A11 A12 */
787 0 : if (((rdev->family == CHIP_RV200) ||
788 0 : (rdev->family == CHIP_RV250)) &&
789 0 : ((RREG32(RADEON_CONFIG_CNTL) &
790 0 : RADEON_CFG_ATI_REV_ID_MASK) <
791 : RADEON_CFG_ATI_REV_A13)) {
792 0 : tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
793 0 : tmp |= RADEON_TCL_BYPASS_DISABLE;
794 0 : WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
795 0 : }
796 0 : mdelay(15);
797 :
798 : /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
799 0 : tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
800 0 : tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
801 : RADEON_PIX2CLK_DAC_ALWAYS_ONb |
802 : RADEON_PIXCLK_BLEND_ALWAYS_ONb |
803 : RADEON_PIXCLK_GV_ALWAYS_ONb |
804 : RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
805 : RADEON_PIXCLK_LVDS_ALWAYS_ONb |
806 : RADEON_PIXCLK_TMDS_ALWAYS_ONb);
807 :
808 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
809 0 : mdelay(15);
810 :
811 0 : tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
812 0 : tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
813 : RADEON_PIXCLK_DAC_ALWAYS_ONb);
814 :
815 0 : WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
816 0 : mdelay(15);
817 : }
818 : } else {
819 : /* Turn everything OFF (ForceON to everything) */
820 0 : if (rdev->flags & RADEON_SINGLE_CRTC) {
821 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
822 0 : tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
823 : RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
824 : | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
825 : RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
826 : RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
827 : RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
828 : RADEON_SCLK_FORCE_RB);
829 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
830 0 : } else if ((rdev->family == CHIP_RS400) ||
831 0 : (rdev->family == CHIP_RS480)) {
832 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
833 0 : tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
834 : RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
835 : | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
836 : R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
837 : RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
838 : R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
839 : R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
840 : R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
841 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
842 :
843 0 : tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
844 0 : tmp |= RADEON_SCLK_MORE_FORCEON;
845 0 : WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
846 :
847 0 : tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
848 0 : tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
849 : RADEON_PIXCLK_DAC_ALWAYS_ONb |
850 : R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
851 0 : WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
852 :
853 0 : tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
854 0 : tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
855 : RADEON_PIX2CLK_DAC_ALWAYS_ONb |
856 : RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
857 : R300_DVOCLK_ALWAYS_ONb |
858 : RADEON_PIXCLK_BLEND_ALWAYS_ONb |
859 : RADEON_PIXCLK_GV_ALWAYS_ONb |
860 : R300_PIXCLK_DVO_ALWAYS_ONb |
861 : RADEON_PIXCLK_LVDS_ALWAYS_ONb |
862 : RADEON_PIXCLK_TMDS_ALWAYS_ONb |
863 : R300_PIXCLK_TRANS_ALWAYS_ONb |
864 : R300_PIXCLK_TVO_ALWAYS_ONb |
865 : R300_P2G2CLK_ALWAYS_ONb |
866 : R300_P2G2CLK_DAC_ALWAYS_ONb |
867 : R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
868 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
869 0 : } else if (rdev->family >= CHIP_RV350) {
870 : /* for RV350/M10, no delays are required. */
871 0 : tmp = RREG32_PLL(R300_SCLK_CNTL2);
872 0 : tmp |= (R300_SCLK_FORCE_TCL |
873 : R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
874 0 : WREG32_PLL(R300_SCLK_CNTL2, tmp);
875 :
876 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
877 0 : tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
878 : RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
879 : | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
880 : R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
881 : RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
882 : R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
883 : R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
884 : R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
885 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
886 :
887 0 : tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
888 0 : tmp |= RADEON_SCLK_MORE_FORCEON;
889 0 : WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
890 :
891 0 : tmp = RREG32_PLL(RADEON_MCLK_CNTL);
892 0 : tmp |= (RADEON_FORCEON_MCLKA |
893 : RADEON_FORCEON_MCLKB |
894 : RADEON_FORCEON_YCLKA |
895 : RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
896 0 : WREG32_PLL(RADEON_MCLK_CNTL, tmp);
897 :
898 0 : tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
899 0 : tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
900 : RADEON_PIXCLK_DAC_ALWAYS_ONb |
901 : R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
902 0 : WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
903 :
904 0 : tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
905 0 : tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
906 : RADEON_PIX2CLK_DAC_ALWAYS_ONb |
907 : RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
908 : R300_DVOCLK_ALWAYS_ONb |
909 : RADEON_PIXCLK_BLEND_ALWAYS_ONb |
910 : RADEON_PIXCLK_GV_ALWAYS_ONb |
911 : R300_PIXCLK_DVO_ALWAYS_ONb |
912 : RADEON_PIXCLK_LVDS_ALWAYS_ONb |
913 : RADEON_PIXCLK_TMDS_ALWAYS_ONb |
914 : R300_PIXCLK_TRANS_ALWAYS_ONb |
915 : R300_PIXCLK_TVO_ALWAYS_ONb |
916 : R300_P2G2CLK_ALWAYS_ONb |
917 : R300_P2G2CLK_DAC_ALWAYS_ONb |
918 : R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
919 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
920 0 : } else {
921 0 : tmp = RREG32_PLL(RADEON_SCLK_CNTL);
922 0 : tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
923 0 : tmp |= RADEON_SCLK_FORCE_SE;
924 :
925 0 : if (rdev->flags & RADEON_SINGLE_CRTC) {
926 0 : tmp |= (RADEON_SCLK_FORCE_RB |
927 : RADEON_SCLK_FORCE_TDM |
928 : RADEON_SCLK_FORCE_TAM |
929 : RADEON_SCLK_FORCE_PB |
930 : RADEON_SCLK_FORCE_RE |
931 : RADEON_SCLK_FORCE_VIP |
932 : RADEON_SCLK_FORCE_IDCT |
933 : RADEON_SCLK_FORCE_TOP |
934 : RADEON_SCLK_FORCE_DISP1 |
935 : RADEON_SCLK_FORCE_DISP2 |
936 : RADEON_SCLK_FORCE_HDP);
937 0 : } else if ((rdev->family == CHIP_R300) ||
938 0 : (rdev->family == CHIP_R350)) {
939 0 : tmp |= (RADEON_SCLK_FORCE_HDP |
940 : RADEON_SCLK_FORCE_DISP1 |
941 : RADEON_SCLK_FORCE_DISP2 |
942 : RADEON_SCLK_FORCE_TOP |
943 : RADEON_SCLK_FORCE_IDCT |
944 : RADEON_SCLK_FORCE_VIP);
945 0 : }
946 0 : WREG32_PLL(RADEON_SCLK_CNTL, tmp);
947 :
948 0 : mdelay(16);
949 :
950 0 : if ((rdev->family == CHIP_R300) ||
951 0 : (rdev->family == CHIP_R350)) {
952 0 : tmp = RREG32_PLL(R300_SCLK_CNTL2);
953 0 : tmp |= (R300_SCLK_FORCE_TCL |
954 : R300_SCLK_FORCE_GA |
955 : R300_SCLK_FORCE_CBA);
956 0 : WREG32_PLL(R300_SCLK_CNTL2, tmp);
957 0 : mdelay(16);
958 0 : }
959 :
960 0 : if (rdev->flags & RADEON_IS_IGP) {
961 0 : tmp = RREG32_PLL(RADEON_MCLK_CNTL);
962 0 : tmp &= ~(RADEON_FORCEON_MCLKA |
963 : RADEON_FORCEON_YCLKA);
964 0 : WREG32_PLL(RADEON_MCLK_CNTL, tmp);
965 0 : mdelay(16);
966 0 : }
967 :
968 0 : if ((rdev->family == CHIP_RV200) ||
969 0 : (rdev->family == CHIP_RV250) ||
970 0 : (rdev->family == CHIP_RV280)) {
971 0 : tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
972 0 : tmp |= RADEON_SCLK_MORE_FORCEON;
973 0 : WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
974 0 : mdelay(16);
975 0 : }
976 :
977 0 : tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
978 0 : tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
979 : RADEON_PIX2CLK_DAC_ALWAYS_ONb |
980 : RADEON_PIXCLK_BLEND_ALWAYS_ONb |
981 : RADEON_PIXCLK_GV_ALWAYS_ONb |
982 : RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
983 : RADEON_PIXCLK_LVDS_ALWAYS_ONb |
984 : RADEON_PIXCLK_TMDS_ALWAYS_ONb);
985 :
986 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
987 0 : mdelay(16);
988 :
989 0 : tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
990 0 : tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
991 : RADEON_PIXCLK_DAC_ALWAYS_ONb);
992 0 : WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
993 : }
994 : }
995 0 : }
996 :
|
