Line data Source code
1 : /*
2 : * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 : * Copyright 2007-8 Advanced Micro Devices, Inc.
4 : * Copyright 2008 Red Hat Inc.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : */
27 : #include <dev/pci/drm/drmP.h>
28 : #include <dev/pci/drm/radeon_drm.h>
29 : #include "radeon.h"
30 : #include "atom.h"
31 :
32 : #ifdef CONFIG_PPC_PMAC
33 : /* not sure which of these are needed */
34 : #include <asm/machdep.h>
35 : #include <asm/pmac_feature.h>
36 : #include <asm/prom.h>
37 : #include <asm/pci-bridge.h>
38 : #endif /* CONFIG_PPC_PMAC */
39 :
40 : /* from radeon_legacy_encoder.c */
41 : extern void
42 : radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
43 : uint32_t supported_device);
44 :
45 : /* old legacy ATI BIOS routines */
46 :
47 : /* COMBIOS table offsets */
48 : enum radeon_combios_table_offset {
49 : /* absolute offset tables */
50 : COMBIOS_ASIC_INIT_1_TABLE,
51 : COMBIOS_BIOS_SUPPORT_TABLE,
52 : COMBIOS_DAC_PROGRAMMING_TABLE,
53 : COMBIOS_MAX_COLOR_DEPTH_TABLE,
54 : COMBIOS_CRTC_INFO_TABLE,
55 : COMBIOS_PLL_INFO_TABLE,
56 : COMBIOS_TV_INFO_TABLE,
57 : COMBIOS_DFP_INFO_TABLE,
58 : COMBIOS_HW_CONFIG_INFO_TABLE,
59 : COMBIOS_MULTIMEDIA_INFO_TABLE,
60 : COMBIOS_TV_STD_PATCH_TABLE,
61 : COMBIOS_LCD_INFO_TABLE,
62 : COMBIOS_MOBILE_INFO_TABLE,
63 : COMBIOS_PLL_INIT_TABLE,
64 : COMBIOS_MEM_CONFIG_TABLE,
65 : COMBIOS_SAVE_MASK_TABLE,
66 : COMBIOS_HARDCODED_EDID_TABLE,
67 : COMBIOS_ASIC_INIT_2_TABLE,
68 : COMBIOS_CONNECTOR_INFO_TABLE,
69 : COMBIOS_DYN_CLK_1_TABLE,
70 : COMBIOS_RESERVED_MEM_TABLE,
71 : COMBIOS_EXT_TMDS_INFO_TABLE,
72 : COMBIOS_MEM_CLK_INFO_TABLE,
73 : COMBIOS_EXT_DAC_INFO_TABLE,
74 : COMBIOS_MISC_INFO_TABLE,
75 : COMBIOS_CRT_INFO_TABLE,
76 : COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
77 : COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
78 : COMBIOS_FAN_SPEED_INFO_TABLE,
79 : COMBIOS_OVERDRIVE_INFO_TABLE,
80 : COMBIOS_OEM_INFO_TABLE,
81 : COMBIOS_DYN_CLK_2_TABLE,
82 : COMBIOS_POWER_CONNECTOR_INFO_TABLE,
83 : COMBIOS_I2C_INFO_TABLE,
84 : /* relative offset tables */
85 : COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
86 : COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
87 : COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
88 : COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
89 : COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
90 : COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
91 : COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
92 : COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
93 : COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
94 : COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
95 : COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
96 : };
97 :
98 : enum radeon_combios_ddc {
99 : DDC_NONE_DETECTED,
100 : DDC_MONID,
101 : DDC_DVI,
102 : DDC_VGA,
103 : DDC_CRT2,
104 : DDC_LCD,
105 : DDC_GPIO,
106 : };
107 :
108 : enum radeon_combios_connector {
109 : CONNECTOR_NONE_LEGACY,
110 : CONNECTOR_PROPRIETARY_LEGACY,
111 : CONNECTOR_CRT_LEGACY,
112 : CONNECTOR_DVI_I_LEGACY,
113 : CONNECTOR_DVI_D_LEGACY,
114 : CONNECTOR_CTV_LEGACY,
115 : CONNECTOR_STV_LEGACY,
116 : CONNECTOR_UNSUPPORTED_LEGACY
117 : };
118 :
119 : static const int legacy_connector_convert[] = {
120 : DRM_MODE_CONNECTOR_Unknown,
121 : DRM_MODE_CONNECTOR_DVID,
122 : DRM_MODE_CONNECTOR_VGA,
123 : DRM_MODE_CONNECTOR_DVII,
124 : DRM_MODE_CONNECTOR_DVID,
125 : DRM_MODE_CONNECTOR_Composite,
126 : DRM_MODE_CONNECTOR_SVIDEO,
127 : DRM_MODE_CONNECTOR_Unknown,
128 : };
129 :
130 0 : static uint16_t combios_get_table_offset(struct drm_device *dev,
131 : enum radeon_combios_table_offset table)
132 : {
133 0 : struct radeon_device *rdev = dev->dev_private;
134 : int rev, size;
135 : uint16_t offset = 0, check_offset;
136 :
137 0 : if (!rdev->bios)
138 0 : return 0;
139 :
140 0 : switch (table) {
141 : /* absolute offset tables */
142 : case COMBIOS_ASIC_INIT_1_TABLE:
143 : check_offset = 0xc;
144 0 : break;
145 : case COMBIOS_BIOS_SUPPORT_TABLE:
146 : check_offset = 0x14;
147 0 : break;
148 : case COMBIOS_DAC_PROGRAMMING_TABLE:
149 : check_offset = 0x2a;
150 0 : break;
151 : case COMBIOS_MAX_COLOR_DEPTH_TABLE:
152 : check_offset = 0x2c;
153 0 : break;
154 : case COMBIOS_CRTC_INFO_TABLE:
155 : check_offset = 0x2e;
156 0 : break;
157 : case COMBIOS_PLL_INFO_TABLE:
158 : check_offset = 0x30;
159 0 : break;
160 : case COMBIOS_TV_INFO_TABLE:
161 : check_offset = 0x32;
162 0 : break;
163 : case COMBIOS_DFP_INFO_TABLE:
164 : check_offset = 0x34;
165 0 : break;
166 : case COMBIOS_HW_CONFIG_INFO_TABLE:
167 : check_offset = 0x36;
168 0 : break;
169 : case COMBIOS_MULTIMEDIA_INFO_TABLE:
170 : check_offset = 0x38;
171 0 : break;
172 : case COMBIOS_TV_STD_PATCH_TABLE:
173 : check_offset = 0x3e;
174 0 : break;
175 : case COMBIOS_LCD_INFO_TABLE:
176 : check_offset = 0x40;
177 0 : break;
178 : case COMBIOS_MOBILE_INFO_TABLE:
179 : check_offset = 0x42;
180 0 : break;
181 : case COMBIOS_PLL_INIT_TABLE:
182 : check_offset = 0x46;
183 0 : break;
184 : case COMBIOS_MEM_CONFIG_TABLE:
185 : check_offset = 0x48;
186 0 : break;
187 : case COMBIOS_SAVE_MASK_TABLE:
188 : check_offset = 0x4a;
189 0 : break;
190 : case COMBIOS_HARDCODED_EDID_TABLE:
191 : check_offset = 0x4c;
192 0 : break;
193 : case COMBIOS_ASIC_INIT_2_TABLE:
194 : check_offset = 0x4e;
195 0 : break;
196 : case COMBIOS_CONNECTOR_INFO_TABLE:
197 : check_offset = 0x50;
198 0 : break;
199 : case COMBIOS_DYN_CLK_1_TABLE:
200 : check_offset = 0x52;
201 0 : break;
202 : case COMBIOS_RESERVED_MEM_TABLE:
203 : check_offset = 0x54;
204 0 : break;
205 : case COMBIOS_EXT_TMDS_INFO_TABLE:
206 : check_offset = 0x58;
207 0 : break;
208 : case COMBIOS_MEM_CLK_INFO_TABLE:
209 : check_offset = 0x5a;
210 0 : break;
211 : case COMBIOS_EXT_DAC_INFO_TABLE:
212 : check_offset = 0x5c;
213 0 : break;
214 : case COMBIOS_MISC_INFO_TABLE:
215 : check_offset = 0x5e;
216 0 : break;
217 : case COMBIOS_CRT_INFO_TABLE:
218 : check_offset = 0x60;
219 0 : break;
220 : case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
221 : check_offset = 0x62;
222 0 : break;
223 : case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
224 : check_offset = 0x64;
225 0 : break;
226 : case COMBIOS_FAN_SPEED_INFO_TABLE:
227 : check_offset = 0x66;
228 0 : break;
229 : case COMBIOS_OVERDRIVE_INFO_TABLE:
230 : check_offset = 0x68;
231 0 : break;
232 : case COMBIOS_OEM_INFO_TABLE:
233 : check_offset = 0x6a;
234 0 : break;
235 : case COMBIOS_DYN_CLK_2_TABLE:
236 : check_offset = 0x6c;
237 0 : break;
238 : case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
239 : check_offset = 0x6e;
240 0 : break;
241 : case COMBIOS_I2C_INFO_TABLE:
242 : check_offset = 0x70;
243 0 : break;
244 : /* relative offset tables */
245 : case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
246 : check_offset =
247 0 : combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
248 0 : if (check_offset) {
249 0 : rev = RBIOS8(check_offset);
250 0 : if (rev > 0) {
251 0 : check_offset = RBIOS16(check_offset + 0x3);
252 0 : if (check_offset)
253 0 : offset = check_offset;
254 : }
255 : }
256 : break;
257 : case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
258 : check_offset =
259 0 : combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
260 0 : if (check_offset) {
261 0 : rev = RBIOS8(check_offset);
262 0 : if (rev > 0) {
263 0 : check_offset = RBIOS16(check_offset + 0x5);
264 0 : if (check_offset)
265 0 : offset = check_offset;
266 : }
267 : }
268 : break;
269 : case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
270 : check_offset =
271 0 : combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
272 0 : if (check_offset) {
273 0 : rev = RBIOS8(check_offset);
274 0 : if (rev > 0) {
275 0 : check_offset = RBIOS16(check_offset + 0x7);
276 0 : if (check_offset)
277 0 : offset = check_offset;
278 : }
279 : }
280 : break;
281 : case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
282 : check_offset =
283 0 : combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
284 0 : if (check_offset) {
285 0 : rev = RBIOS8(check_offset);
286 0 : if (rev == 2) {
287 0 : check_offset = RBIOS16(check_offset + 0x9);
288 0 : if (check_offset)
289 0 : offset = check_offset;
290 : }
291 : }
292 : break;
293 : case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
294 : check_offset =
295 0 : combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
296 0 : if (check_offset) {
297 0 : while (RBIOS8(check_offset++));
298 0 : check_offset += 2;
299 0 : if (check_offset)
300 0 : offset = check_offset;
301 : }
302 : break;
303 : case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
304 : check_offset =
305 0 : combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
306 0 : if (check_offset) {
307 0 : check_offset = RBIOS16(check_offset + 0x11);
308 0 : if (check_offset)
309 0 : offset = check_offset;
310 : }
311 : break;
312 : case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
313 : check_offset =
314 0 : combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
315 0 : if (check_offset) {
316 0 : check_offset = RBIOS16(check_offset + 0x13);
317 0 : if (check_offset)
318 0 : offset = check_offset;
319 : }
320 : break;
321 : case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
322 : check_offset =
323 0 : combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
324 0 : if (check_offset) {
325 0 : check_offset = RBIOS16(check_offset + 0x15);
326 0 : if (check_offset)
327 0 : offset = check_offset;
328 : }
329 : break;
330 : case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
331 : check_offset =
332 0 : combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
333 0 : if (check_offset) {
334 0 : check_offset = RBIOS16(check_offset + 0x17);
335 0 : if (check_offset)
336 0 : offset = check_offset;
337 : }
338 : break;
339 : case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
340 : check_offset =
341 0 : combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
342 0 : if (check_offset) {
343 0 : check_offset = RBIOS16(check_offset + 0x2);
344 0 : if (check_offset)
345 0 : offset = check_offset;
346 : }
347 : break;
348 : case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
349 : check_offset =
350 0 : combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
351 0 : if (check_offset) {
352 0 : check_offset = RBIOS16(check_offset + 0x4);
353 0 : if (check_offset)
354 0 : offset = check_offset;
355 : }
356 : break;
357 : default:
358 : check_offset = 0;
359 0 : break;
360 : }
361 :
362 0 : size = RBIOS8(rdev->bios_header_start + 0x6);
363 : /* check absolute offset tables */
364 0 : if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
365 0 : offset = RBIOS16(rdev->bios_header_start + check_offset);
366 :
367 0 : return offset;
368 0 : }
369 :
370 0 : bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
371 : {
372 : int edid_info, size;
373 : struct edid *edid;
374 : unsigned char *raw;
375 0 : edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
376 0 : if (!edid_info)
377 0 : return false;
378 :
379 0 : raw = rdev->bios + edid_info;
380 0 : size = EDID_LENGTH * (raw[0x7e] + 1);
381 0 : edid = kmalloc(size, GFP_KERNEL);
382 0 : if (edid == NULL)
383 0 : return false;
384 :
385 0 : memcpy((unsigned char *)edid, raw, size);
386 :
387 0 : if (!drm_edid_is_valid(edid)) {
388 0 : kfree(edid);
389 0 : return false;
390 : }
391 :
392 0 : rdev->mode_info.bios_hardcoded_edid = edid;
393 0 : rdev->mode_info.bios_hardcoded_edid_size = size;
394 0 : return true;
395 0 : }
396 :
397 : /* this is used for atom LCDs as well */
398 : struct edid *
399 0 : radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
400 : {
401 : struct edid *edid;
402 :
403 0 : if (rdev->mode_info.bios_hardcoded_edid) {
404 0 : edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
405 0 : if (edid) {
406 0 : memcpy((unsigned char *)edid,
407 : (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
408 : rdev->mode_info.bios_hardcoded_edid_size);
409 0 : return edid;
410 : }
411 : }
412 0 : return NULL;
413 0 : }
414 :
415 : #ifdef __clang__
416 0 : static inline struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
417 : enum radeon_combios_ddc ddc,
418 : u32 clk_mask,
419 : u32 data_mask)
420 : #else
421 : static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
422 : enum radeon_combios_ddc ddc,
423 : u32 clk_mask,
424 : u32 data_mask)
425 : #endif
426 : {
427 : struct radeon_i2c_bus_rec i2c;
428 : int ddc_line = 0;
429 :
430 : /* ddc id = mask reg
431 : * DDC_NONE_DETECTED = none
432 : * DDC_DVI = RADEON_GPIO_DVI_DDC
433 : * DDC_VGA = RADEON_GPIO_VGA_DDC
434 : * DDC_LCD = RADEON_GPIOPAD_MASK
435 : * DDC_GPIO = RADEON_MDGPIO_MASK
436 : * r1xx
437 : * DDC_MONID = RADEON_GPIO_MONID
438 : * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
439 : * r200
440 : * DDC_MONID = RADEON_GPIO_MONID
441 : * DDC_CRT2 = RADEON_GPIO_DVI_DDC
442 : * r300/r350
443 : * DDC_MONID = RADEON_GPIO_DVI_DDC
444 : * DDC_CRT2 = RADEON_GPIO_DVI_DDC
445 : * rv2xx/rv3xx
446 : * DDC_MONID = RADEON_GPIO_MONID
447 : * DDC_CRT2 = RADEON_GPIO_MONID
448 : * rs3xx/rs4xx
449 : * DDC_MONID = RADEON_GPIOPAD_MASK
450 : * DDC_CRT2 = RADEON_GPIO_MONID
451 : */
452 0 : switch (ddc) {
453 : case DDC_NONE_DETECTED:
454 : default:
455 : ddc_line = 0;
456 0 : break;
457 : case DDC_DVI:
458 : ddc_line = RADEON_GPIO_DVI_DDC;
459 0 : break;
460 : case DDC_VGA:
461 : ddc_line = RADEON_GPIO_VGA_DDC;
462 0 : break;
463 : case DDC_LCD:
464 : ddc_line = RADEON_GPIOPAD_MASK;
465 0 : break;
466 : case DDC_GPIO:
467 : ddc_line = RADEON_MDGPIO_MASK;
468 0 : break;
469 : case DDC_MONID:
470 0 : if (rdev->family == CHIP_RS300 ||
471 0 : rdev->family == CHIP_RS400 ||
472 0 : rdev->family == CHIP_RS480)
473 0 : ddc_line = RADEON_GPIOPAD_MASK;
474 0 : else if (rdev->family == CHIP_R300 ||
475 0 : rdev->family == CHIP_R350) {
476 : ddc_line = RADEON_GPIO_DVI_DDC;
477 : ddc = DDC_DVI;
478 0 : } else
479 : ddc_line = RADEON_GPIO_MONID;
480 : break;
481 : case DDC_CRT2:
482 0 : if (rdev->family == CHIP_R200 ||
483 0 : rdev->family == CHIP_R300 ||
484 0 : rdev->family == CHIP_R350) {
485 : ddc_line = RADEON_GPIO_DVI_DDC;
486 : ddc = DDC_DVI;
487 0 : } else if (rdev->family == CHIP_RS300 ||
488 0 : rdev->family == CHIP_RS400 ||
489 0 : rdev->family == CHIP_RS480)
490 0 : ddc_line = RADEON_GPIO_MONID;
491 0 : else if (rdev->family >= CHIP_RV350) {
492 : ddc_line = RADEON_GPIO_MONID;
493 : ddc = DDC_MONID;
494 0 : } else
495 : ddc_line = RADEON_GPIO_CRT2_DDC;
496 : break;
497 : }
498 :
499 0 : if (ddc_line == RADEON_GPIOPAD_MASK) {
500 : i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
501 : i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
502 : i2c.a_clk_reg = RADEON_GPIOPAD_A;
503 : i2c.a_data_reg = RADEON_GPIOPAD_A;
504 : i2c.en_clk_reg = RADEON_GPIOPAD_EN;
505 : i2c.en_data_reg = RADEON_GPIOPAD_EN;
506 : i2c.y_clk_reg = RADEON_GPIOPAD_Y;
507 : i2c.y_data_reg = RADEON_GPIOPAD_Y;
508 0 : } else if (ddc_line == RADEON_MDGPIO_MASK) {
509 : i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
510 : i2c.mask_data_reg = RADEON_MDGPIO_MASK;
511 : i2c.a_clk_reg = RADEON_MDGPIO_A;
512 : i2c.a_data_reg = RADEON_MDGPIO_A;
513 : i2c.en_clk_reg = RADEON_MDGPIO_EN;
514 : i2c.en_data_reg = RADEON_MDGPIO_EN;
515 : i2c.y_clk_reg = RADEON_MDGPIO_Y;
516 : i2c.y_data_reg = RADEON_MDGPIO_Y;
517 0 : } else {
518 : i2c.mask_clk_reg = ddc_line;
519 : i2c.mask_data_reg = ddc_line;
520 : i2c.a_clk_reg = ddc_line;
521 : i2c.a_data_reg = ddc_line;
522 : i2c.en_clk_reg = ddc_line;
523 : i2c.en_data_reg = ddc_line;
524 : i2c.y_clk_reg = ddc_line;
525 : i2c.y_data_reg = ddc_line;
526 : }
527 :
528 0 : if (clk_mask && data_mask) {
529 : /* system specific masks */
530 : i2c.mask_clk_mask = clk_mask;
531 : i2c.mask_data_mask = data_mask;
532 : i2c.a_clk_mask = clk_mask;
533 : i2c.a_data_mask = data_mask;
534 : i2c.en_clk_mask = clk_mask;
535 : i2c.en_data_mask = data_mask;
536 : i2c.y_clk_mask = clk_mask;
537 : i2c.y_data_mask = data_mask;
538 0 : } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
539 0 : (ddc_line == RADEON_MDGPIO_MASK)) {
540 : /* default gpiopad masks */
541 : i2c.mask_clk_mask = (0x20 << 8);
542 : i2c.mask_data_mask = 0x80;
543 : i2c.a_clk_mask = (0x20 << 8);
544 : i2c.a_data_mask = 0x80;
545 : i2c.en_clk_mask = (0x20 << 8);
546 : i2c.en_data_mask = 0x80;
547 : i2c.y_clk_mask = (0x20 << 8);
548 : i2c.y_data_mask = 0x80;
549 0 : } else {
550 : /* default masks for ddc pads */
551 : i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
552 : i2c.mask_data_mask = RADEON_GPIO_MASK_0;
553 : i2c.a_clk_mask = RADEON_GPIO_A_1;
554 : i2c.a_data_mask = RADEON_GPIO_A_0;
555 : i2c.en_clk_mask = RADEON_GPIO_EN_1;
556 : i2c.en_data_mask = RADEON_GPIO_EN_0;
557 : i2c.y_clk_mask = RADEON_GPIO_Y_1;
558 : i2c.y_data_mask = RADEON_GPIO_Y_0;
559 : }
560 :
561 0 : switch (rdev->family) {
562 : case CHIP_R100:
563 : case CHIP_RV100:
564 : case CHIP_RS100:
565 : case CHIP_RV200:
566 : case CHIP_RS200:
567 : case CHIP_RS300:
568 0 : switch (ddc_line) {
569 : case RADEON_GPIO_DVI_DDC:
570 : i2c.hw_capable = true;
571 0 : break;
572 : default:
573 : i2c.hw_capable = false;
574 0 : break;
575 : }
576 : break;
577 : case CHIP_R200:
578 0 : switch (ddc_line) {
579 : case RADEON_GPIO_DVI_DDC:
580 : case RADEON_GPIO_MONID:
581 : i2c.hw_capable = true;
582 0 : break;
583 : default:
584 : i2c.hw_capable = false;
585 0 : break;
586 : }
587 : break;
588 : case CHIP_RV250:
589 : case CHIP_RV280:
590 0 : switch (ddc_line) {
591 : case RADEON_GPIO_VGA_DDC:
592 : case RADEON_GPIO_DVI_DDC:
593 : case RADEON_GPIO_CRT2_DDC:
594 : i2c.hw_capable = true;
595 0 : break;
596 : default:
597 : i2c.hw_capable = false;
598 0 : break;
599 : }
600 : break;
601 : case CHIP_R300:
602 : case CHIP_R350:
603 0 : switch (ddc_line) {
604 : case RADEON_GPIO_VGA_DDC:
605 : case RADEON_GPIO_DVI_DDC:
606 : i2c.hw_capable = true;
607 0 : break;
608 : default:
609 : i2c.hw_capable = false;
610 0 : break;
611 : }
612 : break;
613 : case CHIP_RV350:
614 : case CHIP_RV380:
615 : case CHIP_RS400:
616 : case CHIP_RS480:
617 0 : switch (ddc_line) {
618 : case RADEON_GPIO_VGA_DDC:
619 : case RADEON_GPIO_DVI_DDC:
620 : i2c.hw_capable = true;
621 0 : break;
622 : case RADEON_GPIO_MONID:
623 : /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
624 : * reliably on some pre-r4xx hardware; not sure why.
625 : */
626 : i2c.hw_capable = false;
627 0 : break;
628 : default:
629 : i2c.hw_capable = false;
630 0 : break;
631 : }
632 : break;
633 : default:
634 : i2c.hw_capable = false;
635 0 : break;
636 : }
637 : i2c.mm_i2c = false;
638 :
639 0 : i2c.i2c_id = ddc;
640 : i2c.hpd = RADEON_HPD_NONE;
641 :
642 0 : if (ddc_line)
643 0 : i2c.valid = true;
644 : else
645 : i2c.valid = false;
646 :
647 0 : return i2c;
648 0 : }
649 :
650 0 : static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
651 : {
652 0 : struct drm_device *dev = rdev->ddev;
653 0 : struct radeon_i2c_bus_rec i2c;
654 : u16 offset;
655 : u8 id, blocks, clk, data;
656 : int i;
657 :
658 : i2c.valid = false;
659 :
660 0 : offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
661 0 : if (offset) {
662 0 : blocks = RBIOS8(offset + 2);
663 0 : for (i = 0; i < blocks; i++) {
664 0 : id = RBIOS8(offset + 3 + (i * 5) + 0);
665 0 : if (id == 136) {
666 0 : clk = RBIOS8(offset + 3 + (i * 5) + 3);
667 0 : data = RBIOS8(offset + 3 + (i * 5) + 4);
668 : /* gpiopad */
669 0 : i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
670 0 : (1 << clk), (1 << data));
671 0 : break;
672 : }
673 : }
674 : }
675 0 : return i2c;
676 0 : }
677 :
678 0 : void radeon_combios_i2c_init(struct radeon_device *rdev)
679 : {
680 0 : struct drm_device *dev = rdev->ddev;
681 0 : struct radeon_i2c_bus_rec i2c;
682 :
683 : /* actual hw pads
684 : * r1xx/rs2xx/rs3xx
685 : * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
686 : * r200
687 : * 0x60, 0x64, 0x68, mm
688 : * r300/r350
689 : * 0x60, 0x64, mm
690 : * rv2xx/rv3xx/rs4xx
691 : * 0x60, 0x64, 0x68, gpiopads, mm
692 : */
693 :
694 : /* 0x60 */
695 0 : i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
696 0 : rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
697 : /* 0x64 */
698 0 : i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
699 0 : rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
700 :
701 : /* mm i2c */
702 0 : i2c.valid = true;
703 0 : i2c.hw_capable = true;
704 0 : i2c.mm_i2c = true;
705 0 : i2c.i2c_id = 0xa0;
706 0 : rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
707 :
708 0 : if (rdev->family == CHIP_R300 ||
709 0 : rdev->family == CHIP_R350) {
710 : /* only 2 sw i2c pads */
711 0 : } else if (rdev->family == CHIP_RS300 ||
712 0 : rdev->family == CHIP_RS400 ||
713 0 : rdev->family == CHIP_RS480) {
714 : /* 0x68 */
715 0 : i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
716 0 : rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
717 :
718 : /* gpiopad */
719 0 : i2c = radeon_combios_get_i2c_info_from_table(rdev);
720 0 : if (i2c.valid)
721 0 : rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
722 0 : } else if ((rdev->family == CHIP_R200) ||
723 0 : (rdev->family >= CHIP_R300)) {
724 : /* 0x68 */
725 0 : i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
726 0 : rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
727 0 : } else {
728 : /* 0x68 */
729 0 : i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
730 0 : rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
731 : /* 0x6c */
732 0 : i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
733 0 : rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
734 : }
735 0 : }
736 :
737 0 : bool radeon_combios_get_clock_info(struct drm_device *dev)
738 : {
739 0 : struct radeon_device *rdev = dev->dev_private;
740 : uint16_t pll_info;
741 0 : struct radeon_pll *p1pll = &rdev->clock.p1pll;
742 0 : struct radeon_pll *p2pll = &rdev->clock.p2pll;
743 0 : struct radeon_pll *spll = &rdev->clock.spll;
744 0 : struct radeon_pll *mpll = &rdev->clock.mpll;
745 : int8_t rev;
746 : uint16_t sclk, mclk;
747 :
748 0 : pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
749 0 : if (pll_info) {
750 0 : rev = RBIOS8(pll_info);
751 :
752 : /* pixel clocks */
753 0 : p1pll->reference_freq = RBIOS16(pll_info + 0xe);
754 0 : p1pll->reference_div = RBIOS16(pll_info + 0x10);
755 0 : p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
756 0 : p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
757 0 : p1pll->lcd_pll_out_min = p1pll->pll_out_min;
758 0 : p1pll->lcd_pll_out_max = p1pll->pll_out_max;
759 :
760 0 : if (rev > 9) {
761 0 : p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
762 0 : p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
763 0 : } else {
764 0 : p1pll->pll_in_min = 40;
765 0 : p1pll->pll_in_max = 500;
766 : }
767 0 : *p2pll = *p1pll;
768 :
769 : /* system clock */
770 0 : spll->reference_freq = RBIOS16(pll_info + 0x1a);
771 0 : spll->reference_div = RBIOS16(pll_info + 0x1c);
772 0 : spll->pll_out_min = RBIOS32(pll_info + 0x1e);
773 0 : spll->pll_out_max = RBIOS32(pll_info + 0x22);
774 :
775 0 : if (rev > 10) {
776 0 : spll->pll_in_min = RBIOS32(pll_info + 0x48);
777 0 : spll->pll_in_max = RBIOS32(pll_info + 0x4c);
778 0 : } else {
779 : /* ??? */
780 0 : spll->pll_in_min = 40;
781 0 : spll->pll_in_max = 500;
782 : }
783 :
784 : /* memory clock */
785 0 : mpll->reference_freq = RBIOS16(pll_info + 0x26);
786 0 : mpll->reference_div = RBIOS16(pll_info + 0x28);
787 0 : mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
788 0 : mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
789 :
790 0 : if (rev > 10) {
791 0 : mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
792 0 : mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
793 0 : } else {
794 : /* ??? */
795 0 : mpll->pll_in_min = 40;
796 0 : mpll->pll_in_max = 500;
797 : }
798 :
799 : /* default sclk/mclk */
800 0 : sclk = RBIOS16(pll_info + 0xa);
801 0 : mclk = RBIOS16(pll_info + 0x8);
802 0 : if (sclk == 0)
803 0 : sclk = 200 * 100;
804 0 : if (mclk == 0)
805 0 : mclk = 200 * 100;
806 :
807 0 : rdev->clock.default_sclk = sclk;
808 0 : rdev->clock.default_mclk = mclk;
809 :
810 0 : if (RBIOS32(pll_info + 0x16))
811 0 : rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
812 : else
813 0 : rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
814 :
815 0 : return true;
816 : }
817 0 : return false;
818 0 : }
819 :
820 0 : bool radeon_combios_sideport_present(struct radeon_device *rdev)
821 : {
822 0 : struct drm_device *dev = rdev->ddev;
823 : u16 igp_info;
824 :
825 : /* sideport is AMD only */
826 0 : if (rdev->family == CHIP_RS400)
827 0 : return false;
828 :
829 0 : igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
830 :
831 0 : if (igp_info) {
832 0 : if (RBIOS16(igp_info + 0x4))
833 0 : return true;
834 : }
835 0 : return false;
836 0 : }
837 :
838 : static const uint32_t default_primarydac_adj[CHIP_LAST] = {
839 : 0x00000808, /* r100 */
840 : 0x00000808, /* rv100 */
841 : 0x00000808, /* rs100 */
842 : 0x00000808, /* rv200 */
843 : 0x00000808, /* rs200 */
844 : 0x00000808, /* r200 */
845 : 0x00000808, /* rv250 */
846 : 0x00000000, /* rs300 */
847 : 0x00000808, /* rv280 */
848 : 0x00000808, /* r300 */
849 : 0x00000808, /* r350 */
850 : 0x00000808, /* rv350 */
851 : 0x00000808, /* rv380 */
852 : 0x00000808, /* r420 */
853 : 0x00000808, /* r423 */
854 : 0x00000808, /* rv410 */
855 : 0x00000000, /* rs400 */
856 : 0x00000000, /* rs480 */
857 : };
858 :
859 0 : static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
860 : struct radeon_encoder_primary_dac *p_dac)
861 : {
862 0 : p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
863 0 : return;
864 : }
865 :
866 0 : struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
867 : radeon_encoder
868 : *encoder)
869 : {
870 0 : struct drm_device *dev = encoder->base.dev;
871 0 : struct radeon_device *rdev = dev->dev_private;
872 : uint16_t dac_info;
873 : uint8_t rev, bg, dac;
874 : struct radeon_encoder_primary_dac *p_dac = NULL;
875 : int found = 0;
876 :
877 0 : p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
878 : GFP_KERNEL);
879 :
880 0 : if (!p_dac)
881 0 : return NULL;
882 :
883 : /* check CRT table */
884 0 : dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
885 0 : if (dac_info) {
886 0 : rev = RBIOS8(dac_info) & 0x3;
887 0 : if (rev < 2) {
888 : bg = RBIOS8(dac_info + 0x2) & 0xf;
889 0 : dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
890 0 : p_dac->ps2_pdac_adj = (bg << 8) | (dac);
891 0 : } else {
892 : bg = RBIOS8(dac_info + 0x2) & 0xf;
893 0 : dac = RBIOS8(dac_info + 0x3) & 0xf;
894 0 : p_dac->ps2_pdac_adj = (bg << 8) | (dac);
895 : }
896 : /* if the values are zeros, use the table */
897 0 : if ((dac == 0) || (bg == 0))
898 0 : found = 0;
899 : else
900 : found = 1;
901 : }
902 :
903 : /* quirks */
904 : /* Radeon 7000 (RV100) */
905 0 : if (((dev->pdev->device == 0x5159) &&
906 0 : (dev->pdev->subsystem_vendor == 0x174B) &&
907 0 : (dev->pdev->subsystem_device == 0x7c28)) ||
908 : /* Radeon 9100 (R200) */
909 0 : ((dev->pdev->device == 0x514D) &&
910 0 : (dev->pdev->subsystem_vendor == 0x174B) &&
911 0 : (dev->pdev->subsystem_device == 0x7149))) {
912 : /* vbios value is bad, use the default */
913 : found = 0;
914 0 : }
915 :
916 0 : if (!found) /* fallback to defaults */
917 0 : radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
918 :
919 0 : return p_dac;
920 0 : }
921 :
922 : enum radeon_tv_std
923 0 : radeon_combios_get_tv_info(struct radeon_device *rdev)
924 : {
925 0 : struct drm_device *dev = rdev->ddev;
926 : uint16_t tv_info;
927 : enum radeon_tv_std tv_std = TV_STD_NTSC;
928 :
929 0 : tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
930 0 : if (tv_info) {
931 0 : if (RBIOS8(tv_info + 6) == 'T') {
932 0 : switch (RBIOS8(tv_info + 7) & 0xf) {
933 : case 1:
934 : tv_std = TV_STD_NTSC;
935 : DRM_DEBUG_KMS("Default TV standard: NTSC\n");
936 0 : break;
937 : case 2:
938 : tv_std = TV_STD_PAL;
939 : DRM_DEBUG_KMS("Default TV standard: PAL\n");
940 0 : break;
941 : case 3:
942 : tv_std = TV_STD_PAL_M;
943 : DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
944 0 : break;
945 : case 4:
946 : tv_std = TV_STD_PAL_60;
947 : DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
948 0 : break;
949 : case 5:
950 : tv_std = TV_STD_NTSC_J;
951 : DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
952 0 : break;
953 : case 6:
954 : tv_std = TV_STD_SCART_PAL;
955 : DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
956 0 : break;
957 : default:
958 : tv_std = TV_STD_NTSC;
959 : DRM_DEBUG_KMS
960 : ("Unknown TV standard; defaulting to NTSC\n");
961 0 : break;
962 : }
963 :
964 : switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
965 : case 0:
966 : DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
967 : break;
968 : case 1:
969 : DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
970 : break;
971 : case 2:
972 : DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
973 : break;
974 : case 3:
975 : DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
976 : break;
977 : default:
978 : break;
979 : }
980 : }
981 : }
982 0 : return tv_std;
983 : }
984 :
985 : static const uint32_t default_tvdac_adj[CHIP_LAST] = {
986 : 0x00000000, /* r100 */
987 : 0x00280000, /* rv100 */
988 : 0x00000000, /* rs100 */
989 : 0x00880000, /* rv200 */
990 : 0x00000000, /* rs200 */
991 : 0x00000000, /* r200 */
992 : 0x00770000, /* rv250 */
993 : 0x00290000, /* rs300 */
994 : 0x00560000, /* rv280 */
995 : 0x00780000, /* r300 */
996 : 0x00770000, /* r350 */
997 : 0x00780000, /* rv350 */
998 : 0x00780000, /* rv380 */
999 : 0x01080000, /* r420 */
1000 : 0x01080000, /* r423 */
1001 : 0x01080000, /* rv410 */
1002 : 0x00780000, /* rs400 */
1003 : 0x00780000, /* rs480 */
1004 : };
1005 :
1006 0 : static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1007 : struct radeon_encoder_tv_dac *tv_dac)
1008 : {
1009 0 : tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1010 0 : if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1011 0 : tv_dac->ps2_tvdac_adj = 0x00880000;
1012 0 : tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1013 0 : tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1014 0 : return;
1015 : }
1016 :
1017 0 : struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1018 : radeon_encoder
1019 : *encoder)
1020 : {
1021 0 : struct drm_device *dev = encoder->base.dev;
1022 0 : struct radeon_device *rdev = dev->dev_private;
1023 : uint16_t dac_info;
1024 : uint8_t rev, bg, dac;
1025 : struct radeon_encoder_tv_dac *tv_dac = NULL;
1026 : int found = 0;
1027 :
1028 0 : tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1029 0 : if (!tv_dac)
1030 0 : return NULL;
1031 :
1032 : /* first check TV table */
1033 0 : dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1034 0 : if (dac_info) {
1035 0 : rev = RBIOS8(dac_info + 0x3);
1036 0 : if (rev > 4) {
1037 0 : bg = RBIOS8(dac_info + 0xc) & 0xf;
1038 0 : dac = RBIOS8(dac_info + 0xd) & 0xf;
1039 0 : tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1040 :
1041 0 : bg = RBIOS8(dac_info + 0xe) & 0xf;
1042 0 : dac = RBIOS8(dac_info + 0xf) & 0xf;
1043 0 : tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1044 :
1045 0 : bg = RBIOS8(dac_info + 0x10) & 0xf;
1046 0 : dac = RBIOS8(dac_info + 0x11) & 0xf;
1047 0 : tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1048 : /* if the values are all zeros, use the table */
1049 0 : if (tv_dac->ps2_tvdac_adj)
1050 0 : found = 1;
1051 0 : } else if (rev > 1) {
1052 0 : bg = RBIOS8(dac_info + 0xc) & 0xf;
1053 0 : dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1054 0 : tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1055 :
1056 0 : bg = RBIOS8(dac_info + 0xd) & 0xf;
1057 0 : dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1058 0 : tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1059 :
1060 0 : bg = RBIOS8(dac_info + 0xe) & 0xf;
1061 0 : dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1062 0 : tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1063 : /* if the values are all zeros, use the table */
1064 0 : if (tv_dac->ps2_tvdac_adj)
1065 0 : found = 1;
1066 : }
1067 0 : tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1068 0 : }
1069 0 : if (!found) {
1070 : /* then check CRT table */
1071 : dac_info =
1072 0 : combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1073 0 : if (dac_info) {
1074 0 : rev = RBIOS8(dac_info) & 0x3;
1075 0 : if (rev < 2) {
1076 0 : bg = RBIOS8(dac_info + 0x3) & 0xf;
1077 0 : dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1078 0 : tv_dac->ps2_tvdac_adj =
1079 0 : (bg << 16) | (dac << 20);
1080 0 : tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1081 0 : tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1082 : /* if the values are all zeros, use the table */
1083 0 : if (tv_dac->ps2_tvdac_adj)
1084 0 : found = 1;
1085 : } else {
1086 0 : bg = RBIOS8(dac_info + 0x4) & 0xf;
1087 0 : dac = RBIOS8(dac_info + 0x5) & 0xf;
1088 0 : tv_dac->ps2_tvdac_adj =
1089 0 : (bg << 16) | (dac << 20);
1090 0 : tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1091 0 : tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1092 : /* if the values are all zeros, use the table */
1093 0 : if (tv_dac->ps2_tvdac_adj)
1094 0 : found = 1;
1095 : }
1096 : } else {
1097 : DRM_INFO("No TV DAC info found in BIOS\n");
1098 : }
1099 : }
1100 :
1101 0 : if (!found) /* fallback to defaults */
1102 0 : radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1103 :
1104 0 : return tv_dac;
1105 0 : }
1106 :
1107 0 : static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1108 : radeon_device
1109 : *rdev)
1110 : {
1111 : struct radeon_encoder_lvds *lvds = NULL;
1112 : uint32_t fp_vert_stretch, fp_horz_stretch;
1113 : uint32_t ppll_div_sel, ppll_val;
1114 0 : uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1115 :
1116 0 : lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1117 :
1118 0 : if (!lvds)
1119 0 : return NULL;
1120 :
1121 0 : fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1122 0 : fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1123 :
1124 : /* These should be fail-safe defaults, fingers crossed */
1125 0 : lvds->panel_pwr_delay = 200;
1126 0 : lvds->panel_vcc_delay = 2000;
1127 :
1128 0 : lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1129 0 : lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1130 0 : lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1131 :
1132 0 : if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1133 0 : lvds->native_mode.vdisplay =
1134 0 : ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1135 0 : RADEON_VERT_PANEL_SHIFT) + 1;
1136 : else
1137 0 : lvds->native_mode.vdisplay =
1138 0 : (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1139 :
1140 0 : if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1141 0 : lvds->native_mode.hdisplay =
1142 0 : (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1143 0 : RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1144 : else
1145 0 : lvds->native_mode.hdisplay =
1146 0 : ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1147 :
1148 0 : if ((lvds->native_mode.hdisplay < 640) ||
1149 0 : (lvds->native_mode.vdisplay < 480)) {
1150 0 : lvds->native_mode.hdisplay = 640;
1151 0 : lvds->native_mode.vdisplay = 480;
1152 0 : }
1153 :
1154 0 : ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1155 0 : ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1156 0 : if ((ppll_val & 0x000707ff) == 0x1bb)
1157 0 : lvds->use_bios_dividers = false;
1158 : else {
1159 0 : lvds->panel_ref_divider =
1160 0 : RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1161 0 : lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1162 0 : lvds->panel_fb_divider = ppll_val & 0x7ff;
1163 :
1164 0 : if ((lvds->panel_ref_divider != 0) &&
1165 0 : (lvds->panel_fb_divider > 3))
1166 0 : lvds->use_bios_dividers = true;
1167 : }
1168 0 : lvds->panel_vcc_delay = 200;
1169 :
1170 : DRM_INFO("Panel info derived from registers\n");
1171 : DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1172 : lvds->native_mode.vdisplay);
1173 :
1174 0 : return lvds;
1175 0 : }
1176 :
1177 0 : struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1178 : *encoder)
1179 : {
1180 0 : struct drm_device *dev = encoder->base.dev;
1181 0 : struct radeon_device *rdev = dev->dev_private;
1182 : uint16_t lcd_info;
1183 : uint32_t panel_setup;
1184 0 : char stmp[30];
1185 : int tmp, i;
1186 : struct radeon_encoder_lvds *lvds = NULL;
1187 :
1188 0 : lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1189 :
1190 0 : if (lcd_info) {
1191 0 : lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1192 :
1193 0 : if (!lvds)
1194 0 : return NULL;
1195 :
1196 0 : for (i = 0; i < 24; i++)
1197 0 : stmp[i] = RBIOS8(lcd_info + i + 1);
1198 0 : stmp[24] = 0;
1199 :
1200 : DRM_INFO("Panel ID String: %s\n", stmp);
1201 :
1202 0 : lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1203 0 : lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1204 :
1205 : DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1206 : lvds->native_mode.vdisplay);
1207 :
1208 0 : lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1209 0 : lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1210 :
1211 0 : lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1212 0 : lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1213 0 : lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1214 :
1215 0 : lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1216 0 : lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1217 0 : lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1218 0 : if ((lvds->panel_ref_divider != 0) &&
1219 0 : (lvds->panel_fb_divider > 3))
1220 0 : lvds->use_bios_dividers = true;
1221 :
1222 0 : panel_setup = RBIOS32(lcd_info + 0x39);
1223 0 : lvds->lvds_gen_cntl = 0xff00;
1224 0 : if (panel_setup & 0x1)
1225 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1226 :
1227 0 : if ((panel_setup >> 4) & 0x1)
1228 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1229 :
1230 0 : switch ((panel_setup >> 8) & 0x7) {
1231 : case 0:
1232 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1233 0 : break;
1234 : case 1:
1235 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1236 0 : break;
1237 : case 2:
1238 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1239 0 : break;
1240 : default:
1241 : break;
1242 : }
1243 :
1244 0 : if ((panel_setup >> 16) & 0x1)
1245 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1246 :
1247 0 : if ((panel_setup >> 17) & 0x1)
1248 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1249 :
1250 0 : if ((panel_setup >> 18) & 0x1)
1251 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1252 :
1253 0 : if ((panel_setup >> 23) & 0x1)
1254 0 : lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1255 :
1256 0 : lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1257 :
1258 0 : for (i = 0; i < 32; i++) {
1259 0 : tmp = RBIOS16(lcd_info + 64 + i * 2);
1260 0 : if (tmp == 0)
1261 : break;
1262 :
1263 0 : if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1264 0 : (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1265 0 : u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1266 :
1267 0 : if (hss > lvds->native_mode.hdisplay)
1268 : hss = (10 - 1) * 8;
1269 :
1270 0 : lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1271 0 : (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1272 0 : lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1273 : hss;
1274 0 : lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1275 0 : (RBIOS8(tmp + 23) * 8);
1276 :
1277 0 : lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1278 0 : (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1279 0 : lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1280 0 : ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1281 0 : lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1282 0 : ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1283 :
1284 0 : lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1285 0 : lvds->native_mode.flags = 0;
1286 : /* set crtc values */
1287 0 : drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1288 :
1289 0 : }
1290 : }
1291 : } else {
1292 : DRM_INFO("No panel info found in BIOS\n");
1293 0 : lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1294 : }
1295 :
1296 0 : if (lvds)
1297 0 : encoder->native_mode = lvds->native_mode;
1298 0 : return lvds;
1299 0 : }
1300 :
1301 : static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1302 : {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1303 : {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1304 : {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1305 : {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1306 : {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1307 : {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1308 : {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1309 : {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1310 : {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1311 : {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1312 : {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1313 : {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1314 : {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1315 : {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1316 : {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1317 : {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1318 : { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1319 : { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1320 : };
1321 :
1322 0 : bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1323 : struct radeon_encoder_int_tmds *tmds)
1324 : {
1325 0 : struct drm_device *dev = encoder->base.dev;
1326 0 : struct radeon_device *rdev = dev->dev_private;
1327 : int i;
1328 :
1329 0 : for (i = 0; i < 4; i++) {
1330 0 : tmds->tmds_pll[i].value =
1331 0 : default_tmds_pll[rdev->family][i].value;
1332 0 : tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1333 : }
1334 :
1335 0 : return true;
1336 : }
1337 :
1338 0 : bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1339 : struct radeon_encoder_int_tmds *tmds)
1340 : {
1341 0 : struct drm_device *dev = encoder->base.dev;
1342 0 : struct radeon_device *rdev = dev->dev_private;
1343 : uint16_t tmds_info;
1344 : int i, n;
1345 : uint8_t ver;
1346 :
1347 0 : tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1348 :
1349 0 : if (tmds_info) {
1350 0 : ver = RBIOS8(tmds_info);
1351 : DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1352 0 : if (ver == 3) {
1353 0 : n = RBIOS8(tmds_info + 5) + 1;
1354 0 : if (n > 4)
1355 : n = 4;
1356 0 : for (i = 0; i < n; i++) {
1357 0 : tmds->tmds_pll[i].value =
1358 0 : RBIOS32(tmds_info + i * 10 + 0x08);
1359 0 : tmds->tmds_pll[i].freq =
1360 0 : RBIOS16(tmds_info + i * 10 + 0x10);
1361 : DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1362 : tmds->tmds_pll[i].freq,
1363 : tmds->tmds_pll[i].value);
1364 : }
1365 0 : } else if (ver == 4) {
1366 : int stride = 0;
1367 0 : n = RBIOS8(tmds_info + 5) + 1;
1368 0 : if (n > 4)
1369 : n = 4;
1370 0 : for (i = 0; i < n; i++) {
1371 0 : tmds->tmds_pll[i].value =
1372 0 : RBIOS32(tmds_info + stride + 0x08);
1373 0 : tmds->tmds_pll[i].freq =
1374 0 : RBIOS16(tmds_info + stride + 0x10);
1375 0 : if (i == 0)
1376 0 : stride += 10;
1377 : else
1378 0 : stride += 6;
1379 : DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1380 : tmds->tmds_pll[i].freq,
1381 : tmds->tmds_pll[i].value);
1382 : }
1383 0 : }
1384 : } else {
1385 : DRM_INFO("No TMDS info found in BIOS\n");
1386 0 : return false;
1387 : }
1388 0 : return true;
1389 0 : }
1390 :
1391 0 : bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1392 : struct radeon_encoder_ext_tmds *tmds)
1393 : {
1394 0 : struct drm_device *dev = encoder->base.dev;
1395 0 : struct radeon_device *rdev = dev->dev_private;
1396 0 : struct radeon_i2c_bus_rec i2c_bus;
1397 :
1398 : /* default for macs */
1399 0 : i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1400 0 : tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1401 :
1402 : /* XXX some macs have duallink chips */
1403 0 : switch (rdev->mode_info.connector_table) {
1404 : case CT_POWERBOOK_EXTERNAL:
1405 : case CT_MINI_EXTERNAL:
1406 : default:
1407 0 : tmds->dvo_chip = DVO_SIL164;
1408 0 : tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1409 : break;
1410 : }
1411 :
1412 0 : return true;
1413 0 : }
1414 :
1415 0 : bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1416 : struct radeon_encoder_ext_tmds *tmds)
1417 : {
1418 0 : struct drm_device *dev = encoder->base.dev;
1419 0 : struct radeon_device *rdev = dev->dev_private;
1420 : uint16_t offset;
1421 : uint8_t ver;
1422 : enum radeon_combios_ddc gpio;
1423 0 : struct radeon_i2c_bus_rec i2c_bus;
1424 :
1425 0 : tmds->i2c_bus = NULL;
1426 0 : if (rdev->flags & RADEON_IS_IGP) {
1427 0 : i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1428 0 : tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1429 0 : tmds->dvo_chip = DVO_SIL164;
1430 0 : tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1431 0 : } else {
1432 0 : offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1433 0 : if (offset) {
1434 0 : ver = RBIOS8(offset);
1435 : DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1436 0 : tmds->slave_addr = RBIOS8(offset + 4 + 2);
1437 0 : tmds->slave_addr >>= 1; /* 7 bit addressing */
1438 0 : gpio = RBIOS8(offset + 4 + 3);
1439 0 : if (gpio == DDC_LCD) {
1440 : /* MM i2c */
1441 0 : i2c_bus.valid = true;
1442 0 : i2c_bus.hw_capable = true;
1443 0 : i2c_bus.mm_i2c = true;
1444 0 : i2c_bus.i2c_id = 0xa0;
1445 0 : } else
1446 0 : i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1447 0 : tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1448 0 : }
1449 : }
1450 :
1451 0 : if (!tmds->i2c_bus) {
1452 : DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1453 0 : return false;
1454 : }
1455 :
1456 0 : return true;
1457 0 : }
1458 :
1459 0 : bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1460 : {
1461 0 : struct radeon_device *rdev = dev->dev_private;
1462 0 : struct radeon_i2c_bus_rec ddc_i2c;
1463 0 : struct radeon_hpd hpd;
1464 :
1465 0 : rdev->mode_info.connector_table = radeon_connector_table;
1466 0 : if (rdev->mode_info.connector_table == CT_NONE) {
1467 : #ifdef __macppc__
1468 : if (of_machine_is_compatible("PowerBook3,3")) {
1469 : /* powerbook with VGA */
1470 : rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1471 : } else if (of_machine_is_compatible("PowerBook3,4") ||
1472 : of_machine_is_compatible("PowerBook3,5")) {
1473 : /* powerbook with internal tmds */
1474 : rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1475 : } else if (of_machine_is_compatible("PowerBook5,1") ||
1476 : of_machine_is_compatible("PowerBook5,2") ||
1477 : of_machine_is_compatible("PowerBook5,3") ||
1478 : of_machine_is_compatible("PowerBook5,4") ||
1479 : of_machine_is_compatible("PowerBook5,5")) {
1480 : /* powerbook with external single link tmds (sil164) */
1481 : rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1482 : } else if (of_machine_is_compatible("PowerBook5,6")) {
1483 : /* powerbook with external dual or single link tmds */
1484 : rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1485 : } else if (of_machine_is_compatible("PowerBook5,7") ||
1486 : of_machine_is_compatible("PowerBook5,8") ||
1487 : of_machine_is_compatible("PowerBook5,9")) {
1488 : /* PowerBook6,2 ? */
1489 : /* powerbook with external dual link tmds (sil1178?) */
1490 : rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1491 : } else if (of_machine_is_compatible("PowerBook4,1") ||
1492 : of_machine_is_compatible("PowerBook4,2") ||
1493 : of_machine_is_compatible("PowerBook4,3") ||
1494 : of_machine_is_compatible("PowerBook6,3") ||
1495 : of_machine_is_compatible("PowerBook6,5") ||
1496 : of_machine_is_compatible("PowerBook6,7")) {
1497 : /* ibook */
1498 : rdev->mode_info.connector_table = CT_IBOOK;
1499 : } else if (of_machine_is_compatible("PowerMac3,5")) {
1500 : /* PowerMac G4 Silver radeon 7500 */
1501 : rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1502 : } else if (of_machine_is_compatible("PowerMac4,4")) {
1503 : /* emac */
1504 : rdev->mode_info.connector_table = CT_EMAC;
1505 : } else if (of_machine_is_compatible("PowerMac10,1")) {
1506 : /* mini with internal tmds */
1507 : rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1508 : } else if (of_machine_is_compatible("PowerMac10,2")) {
1509 : /* mini with external tmds */
1510 : rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1511 : } else if (of_machine_is_compatible("PowerMac12,1")) {
1512 : /* PowerMac8,1 ? */
1513 : /* imac g5 isight */
1514 : rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1515 : } else if ((rdev->pdev->device == 0x4a48) &&
1516 : (rdev->pdev->subsystem_vendor == 0x1002) &&
1517 : (rdev->pdev->subsystem_device == 0x4a48)) {
1518 : /* Mac X800 */
1519 : rdev->mode_info.connector_table = CT_MAC_X800;
1520 : } else if ((of_machine_is_compatible("PowerMac7,2") ||
1521 : of_machine_is_compatible("PowerMac7,3")) &&
1522 : (rdev->pdev->device == 0x4150) &&
1523 : (rdev->pdev->subsystem_vendor == 0x1002) &&
1524 : (rdev->pdev->subsystem_device == 0x4150)) {
1525 : /* Mac G5 tower 9600 */
1526 : rdev->mode_info.connector_table = CT_MAC_G5_9600;
1527 : } else if ((rdev->pdev->device == 0x4c66) &&
1528 : (rdev->pdev->subsystem_vendor == 0x1002) &&
1529 : (rdev->pdev->subsystem_device == 0x4c66)) {
1530 : /* SAM440ep RV250 embedded board */
1531 : rdev->mode_info.connector_table = CT_SAM440EP;
1532 : } else
1533 : #endif /* __macppc__ */
1534 : #ifdef CONFIG_PPC64
1535 : if (ASIC_IS_RN50(rdev))
1536 : rdev->mode_info.connector_table = CT_RN50_POWER;
1537 : else
1538 : #endif
1539 0 : rdev->mode_info.connector_table = CT_GENERIC;
1540 0 : }
1541 :
1542 0 : switch (rdev->mode_info.connector_table) {
1543 : case CT_GENERIC:
1544 : DRM_INFO("Connector Table: %d (generic)\n",
1545 : rdev->mode_info.connector_table);
1546 : /* these are the most common settings */
1547 0 : if (rdev->flags & RADEON_SINGLE_CRTC) {
1548 : /* VGA - primary dac */
1549 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1550 0 : hpd.hpd = RADEON_HPD_NONE;
1551 0 : radeon_add_legacy_encoder(dev,
1552 0 : radeon_get_encoder_enum(dev,
1553 : ATOM_DEVICE_CRT1_SUPPORT,
1554 : 1),
1555 : ATOM_DEVICE_CRT1_SUPPORT);
1556 0 : radeon_add_legacy_connector(dev, 0,
1557 : ATOM_DEVICE_CRT1_SUPPORT,
1558 : DRM_MODE_CONNECTOR_VGA,
1559 : &ddc_i2c,
1560 : CONNECTOR_OBJECT_ID_VGA,
1561 : &hpd);
1562 0 : } else if (rdev->flags & RADEON_IS_MOBILITY) {
1563 : /* LVDS */
1564 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1565 0 : hpd.hpd = RADEON_HPD_NONE;
1566 0 : radeon_add_legacy_encoder(dev,
1567 0 : radeon_get_encoder_enum(dev,
1568 : ATOM_DEVICE_LCD1_SUPPORT,
1569 : 0),
1570 : ATOM_DEVICE_LCD1_SUPPORT);
1571 0 : radeon_add_legacy_connector(dev, 0,
1572 : ATOM_DEVICE_LCD1_SUPPORT,
1573 : DRM_MODE_CONNECTOR_LVDS,
1574 : &ddc_i2c,
1575 : CONNECTOR_OBJECT_ID_LVDS,
1576 : &hpd);
1577 :
1578 : /* VGA - primary dac */
1579 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1580 0 : hpd.hpd = RADEON_HPD_NONE;
1581 0 : radeon_add_legacy_encoder(dev,
1582 0 : radeon_get_encoder_enum(dev,
1583 : ATOM_DEVICE_CRT1_SUPPORT,
1584 : 1),
1585 : ATOM_DEVICE_CRT1_SUPPORT);
1586 0 : radeon_add_legacy_connector(dev, 1,
1587 : ATOM_DEVICE_CRT1_SUPPORT,
1588 : DRM_MODE_CONNECTOR_VGA,
1589 : &ddc_i2c,
1590 : CONNECTOR_OBJECT_ID_VGA,
1591 : &hpd);
1592 0 : } else {
1593 : /* DVI-I - tv dac, int tmds */
1594 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1595 0 : hpd.hpd = RADEON_HPD_1;
1596 0 : radeon_add_legacy_encoder(dev,
1597 0 : radeon_get_encoder_enum(dev,
1598 : ATOM_DEVICE_DFP1_SUPPORT,
1599 : 0),
1600 : ATOM_DEVICE_DFP1_SUPPORT);
1601 0 : radeon_add_legacy_encoder(dev,
1602 0 : radeon_get_encoder_enum(dev,
1603 : ATOM_DEVICE_CRT2_SUPPORT,
1604 : 2),
1605 : ATOM_DEVICE_CRT2_SUPPORT);
1606 0 : radeon_add_legacy_connector(dev, 0,
1607 : ATOM_DEVICE_DFP1_SUPPORT |
1608 : ATOM_DEVICE_CRT2_SUPPORT,
1609 : DRM_MODE_CONNECTOR_DVII,
1610 : &ddc_i2c,
1611 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1612 : &hpd);
1613 :
1614 : /* VGA - primary dac */
1615 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1616 0 : hpd.hpd = RADEON_HPD_NONE;
1617 0 : radeon_add_legacy_encoder(dev,
1618 0 : radeon_get_encoder_enum(dev,
1619 : ATOM_DEVICE_CRT1_SUPPORT,
1620 : 1),
1621 : ATOM_DEVICE_CRT1_SUPPORT);
1622 0 : radeon_add_legacy_connector(dev, 1,
1623 : ATOM_DEVICE_CRT1_SUPPORT,
1624 : DRM_MODE_CONNECTOR_VGA,
1625 : &ddc_i2c,
1626 : CONNECTOR_OBJECT_ID_VGA,
1627 : &hpd);
1628 : }
1629 :
1630 0 : if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1631 : /* TV - tv dac */
1632 0 : ddc_i2c.valid = false;
1633 0 : hpd.hpd = RADEON_HPD_NONE;
1634 0 : radeon_add_legacy_encoder(dev,
1635 0 : radeon_get_encoder_enum(dev,
1636 : ATOM_DEVICE_TV1_SUPPORT,
1637 : 2),
1638 : ATOM_DEVICE_TV1_SUPPORT);
1639 0 : radeon_add_legacy_connector(dev, 2,
1640 : ATOM_DEVICE_TV1_SUPPORT,
1641 : DRM_MODE_CONNECTOR_SVIDEO,
1642 : &ddc_i2c,
1643 : CONNECTOR_OBJECT_ID_SVIDEO,
1644 : &hpd);
1645 0 : }
1646 : break;
1647 : case CT_IBOOK:
1648 : DRM_INFO("Connector Table: %d (ibook)\n",
1649 : rdev->mode_info.connector_table);
1650 : /* LVDS */
1651 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1652 0 : hpd.hpd = RADEON_HPD_NONE;
1653 0 : radeon_add_legacy_encoder(dev,
1654 0 : radeon_get_encoder_enum(dev,
1655 : ATOM_DEVICE_LCD1_SUPPORT,
1656 : 0),
1657 : ATOM_DEVICE_LCD1_SUPPORT);
1658 0 : radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1659 : DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1660 : CONNECTOR_OBJECT_ID_LVDS,
1661 : &hpd);
1662 : /* VGA - TV DAC */
1663 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1664 0 : hpd.hpd = RADEON_HPD_NONE;
1665 0 : radeon_add_legacy_encoder(dev,
1666 0 : radeon_get_encoder_enum(dev,
1667 : ATOM_DEVICE_CRT2_SUPPORT,
1668 : 2),
1669 : ATOM_DEVICE_CRT2_SUPPORT);
1670 0 : radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1671 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1672 : CONNECTOR_OBJECT_ID_VGA,
1673 : &hpd);
1674 : /* TV - TV DAC */
1675 0 : ddc_i2c.valid = false;
1676 0 : hpd.hpd = RADEON_HPD_NONE;
1677 0 : radeon_add_legacy_encoder(dev,
1678 0 : radeon_get_encoder_enum(dev,
1679 : ATOM_DEVICE_TV1_SUPPORT,
1680 : 2),
1681 : ATOM_DEVICE_TV1_SUPPORT);
1682 0 : radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1683 : DRM_MODE_CONNECTOR_SVIDEO,
1684 : &ddc_i2c,
1685 : CONNECTOR_OBJECT_ID_SVIDEO,
1686 : &hpd);
1687 0 : break;
1688 : case CT_POWERBOOK_EXTERNAL:
1689 : DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1690 : rdev->mode_info.connector_table);
1691 : /* LVDS */
1692 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1693 0 : hpd.hpd = RADEON_HPD_NONE;
1694 0 : radeon_add_legacy_encoder(dev,
1695 0 : radeon_get_encoder_enum(dev,
1696 : ATOM_DEVICE_LCD1_SUPPORT,
1697 : 0),
1698 : ATOM_DEVICE_LCD1_SUPPORT);
1699 0 : radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1700 : DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1701 : CONNECTOR_OBJECT_ID_LVDS,
1702 : &hpd);
1703 : /* DVI-I - primary dac, ext tmds */
1704 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1705 0 : hpd.hpd = RADEON_HPD_2; /* ??? */
1706 0 : radeon_add_legacy_encoder(dev,
1707 0 : radeon_get_encoder_enum(dev,
1708 : ATOM_DEVICE_DFP2_SUPPORT,
1709 : 0),
1710 : ATOM_DEVICE_DFP2_SUPPORT);
1711 0 : radeon_add_legacy_encoder(dev,
1712 0 : radeon_get_encoder_enum(dev,
1713 : ATOM_DEVICE_CRT1_SUPPORT,
1714 : 1),
1715 : ATOM_DEVICE_CRT1_SUPPORT);
1716 : /* XXX some are SL */
1717 0 : radeon_add_legacy_connector(dev, 1,
1718 : ATOM_DEVICE_DFP2_SUPPORT |
1719 : ATOM_DEVICE_CRT1_SUPPORT,
1720 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1721 : CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1722 : &hpd);
1723 : /* TV - TV DAC */
1724 0 : ddc_i2c.valid = false;
1725 0 : hpd.hpd = RADEON_HPD_NONE;
1726 0 : radeon_add_legacy_encoder(dev,
1727 0 : radeon_get_encoder_enum(dev,
1728 : ATOM_DEVICE_TV1_SUPPORT,
1729 : 2),
1730 : ATOM_DEVICE_TV1_SUPPORT);
1731 0 : radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1732 : DRM_MODE_CONNECTOR_SVIDEO,
1733 : &ddc_i2c,
1734 : CONNECTOR_OBJECT_ID_SVIDEO,
1735 : &hpd);
1736 0 : break;
1737 : case CT_POWERBOOK_INTERNAL:
1738 : DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1739 : rdev->mode_info.connector_table);
1740 : /* LVDS */
1741 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1742 0 : hpd.hpd = RADEON_HPD_NONE;
1743 0 : radeon_add_legacy_encoder(dev,
1744 0 : radeon_get_encoder_enum(dev,
1745 : ATOM_DEVICE_LCD1_SUPPORT,
1746 : 0),
1747 : ATOM_DEVICE_LCD1_SUPPORT);
1748 0 : radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1749 : DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1750 : CONNECTOR_OBJECT_ID_LVDS,
1751 : &hpd);
1752 : /* DVI-I - primary dac, int tmds */
1753 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1754 0 : hpd.hpd = RADEON_HPD_1; /* ??? */
1755 0 : radeon_add_legacy_encoder(dev,
1756 0 : radeon_get_encoder_enum(dev,
1757 : ATOM_DEVICE_DFP1_SUPPORT,
1758 : 0),
1759 : ATOM_DEVICE_DFP1_SUPPORT);
1760 0 : radeon_add_legacy_encoder(dev,
1761 0 : radeon_get_encoder_enum(dev,
1762 : ATOM_DEVICE_CRT1_SUPPORT,
1763 : 1),
1764 : ATOM_DEVICE_CRT1_SUPPORT);
1765 0 : radeon_add_legacy_connector(dev, 1,
1766 : ATOM_DEVICE_DFP1_SUPPORT |
1767 : ATOM_DEVICE_CRT1_SUPPORT,
1768 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1769 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1770 : &hpd);
1771 : /* TV - TV DAC */
1772 0 : ddc_i2c.valid = false;
1773 0 : hpd.hpd = RADEON_HPD_NONE;
1774 0 : radeon_add_legacy_encoder(dev,
1775 0 : radeon_get_encoder_enum(dev,
1776 : ATOM_DEVICE_TV1_SUPPORT,
1777 : 2),
1778 : ATOM_DEVICE_TV1_SUPPORT);
1779 0 : radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1780 : DRM_MODE_CONNECTOR_SVIDEO,
1781 : &ddc_i2c,
1782 : CONNECTOR_OBJECT_ID_SVIDEO,
1783 : &hpd);
1784 0 : break;
1785 : case CT_POWERBOOK_VGA:
1786 : DRM_INFO("Connector Table: %d (powerbook vga)\n",
1787 : rdev->mode_info.connector_table);
1788 : /* LVDS */
1789 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1790 0 : hpd.hpd = RADEON_HPD_NONE;
1791 0 : radeon_add_legacy_encoder(dev,
1792 0 : radeon_get_encoder_enum(dev,
1793 : ATOM_DEVICE_LCD1_SUPPORT,
1794 : 0),
1795 : ATOM_DEVICE_LCD1_SUPPORT);
1796 0 : radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1797 : DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1798 : CONNECTOR_OBJECT_ID_LVDS,
1799 : &hpd);
1800 : /* VGA - primary dac */
1801 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1802 0 : hpd.hpd = RADEON_HPD_NONE;
1803 0 : radeon_add_legacy_encoder(dev,
1804 0 : radeon_get_encoder_enum(dev,
1805 : ATOM_DEVICE_CRT1_SUPPORT,
1806 : 1),
1807 : ATOM_DEVICE_CRT1_SUPPORT);
1808 0 : radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1809 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1810 : CONNECTOR_OBJECT_ID_VGA,
1811 : &hpd);
1812 : /* TV - TV DAC */
1813 0 : ddc_i2c.valid = false;
1814 0 : hpd.hpd = RADEON_HPD_NONE;
1815 0 : radeon_add_legacy_encoder(dev,
1816 0 : radeon_get_encoder_enum(dev,
1817 : ATOM_DEVICE_TV1_SUPPORT,
1818 : 2),
1819 : ATOM_DEVICE_TV1_SUPPORT);
1820 0 : radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1821 : DRM_MODE_CONNECTOR_SVIDEO,
1822 : &ddc_i2c,
1823 : CONNECTOR_OBJECT_ID_SVIDEO,
1824 : &hpd);
1825 0 : break;
1826 : case CT_MINI_EXTERNAL:
1827 : DRM_INFO("Connector Table: %d (mini external tmds)\n",
1828 : rdev->mode_info.connector_table);
1829 : /* DVI-I - tv dac, ext tmds */
1830 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1831 0 : hpd.hpd = RADEON_HPD_2; /* ??? */
1832 0 : radeon_add_legacy_encoder(dev,
1833 0 : radeon_get_encoder_enum(dev,
1834 : ATOM_DEVICE_DFP2_SUPPORT,
1835 : 0),
1836 : ATOM_DEVICE_DFP2_SUPPORT);
1837 0 : radeon_add_legacy_encoder(dev,
1838 0 : radeon_get_encoder_enum(dev,
1839 : ATOM_DEVICE_CRT2_SUPPORT,
1840 : 2),
1841 : ATOM_DEVICE_CRT2_SUPPORT);
1842 : /* XXX are any DL? */
1843 0 : radeon_add_legacy_connector(dev, 0,
1844 : ATOM_DEVICE_DFP2_SUPPORT |
1845 : ATOM_DEVICE_CRT2_SUPPORT,
1846 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1847 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1848 : &hpd);
1849 : /* TV - TV DAC */
1850 0 : ddc_i2c.valid = false;
1851 0 : hpd.hpd = RADEON_HPD_NONE;
1852 0 : radeon_add_legacy_encoder(dev,
1853 0 : radeon_get_encoder_enum(dev,
1854 : ATOM_DEVICE_TV1_SUPPORT,
1855 : 2),
1856 : ATOM_DEVICE_TV1_SUPPORT);
1857 0 : radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1858 : DRM_MODE_CONNECTOR_SVIDEO,
1859 : &ddc_i2c,
1860 : CONNECTOR_OBJECT_ID_SVIDEO,
1861 : &hpd);
1862 0 : break;
1863 : case CT_MINI_INTERNAL:
1864 : DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1865 : rdev->mode_info.connector_table);
1866 : /* DVI-I - tv dac, int tmds */
1867 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1868 0 : hpd.hpd = RADEON_HPD_1; /* ??? */
1869 0 : radeon_add_legacy_encoder(dev,
1870 0 : radeon_get_encoder_enum(dev,
1871 : ATOM_DEVICE_DFP1_SUPPORT,
1872 : 0),
1873 : ATOM_DEVICE_DFP1_SUPPORT);
1874 0 : radeon_add_legacy_encoder(dev,
1875 0 : radeon_get_encoder_enum(dev,
1876 : ATOM_DEVICE_CRT2_SUPPORT,
1877 : 2),
1878 : ATOM_DEVICE_CRT2_SUPPORT);
1879 0 : radeon_add_legacy_connector(dev, 0,
1880 : ATOM_DEVICE_DFP1_SUPPORT |
1881 : ATOM_DEVICE_CRT2_SUPPORT,
1882 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1883 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1884 : &hpd);
1885 : /* TV - TV DAC */
1886 0 : ddc_i2c.valid = false;
1887 0 : hpd.hpd = RADEON_HPD_NONE;
1888 0 : radeon_add_legacy_encoder(dev,
1889 0 : radeon_get_encoder_enum(dev,
1890 : ATOM_DEVICE_TV1_SUPPORT,
1891 : 2),
1892 : ATOM_DEVICE_TV1_SUPPORT);
1893 0 : radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1894 : DRM_MODE_CONNECTOR_SVIDEO,
1895 : &ddc_i2c,
1896 : CONNECTOR_OBJECT_ID_SVIDEO,
1897 : &hpd);
1898 0 : break;
1899 : case CT_IMAC_G5_ISIGHT:
1900 : DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1901 : rdev->mode_info.connector_table);
1902 : /* DVI-D - int tmds */
1903 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1904 0 : hpd.hpd = RADEON_HPD_1; /* ??? */
1905 0 : radeon_add_legacy_encoder(dev,
1906 0 : radeon_get_encoder_enum(dev,
1907 : ATOM_DEVICE_DFP1_SUPPORT,
1908 : 0),
1909 : ATOM_DEVICE_DFP1_SUPPORT);
1910 0 : radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1911 : DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1912 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1913 : &hpd);
1914 : /* VGA - tv dac */
1915 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1916 0 : hpd.hpd = RADEON_HPD_NONE;
1917 0 : radeon_add_legacy_encoder(dev,
1918 0 : radeon_get_encoder_enum(dev,
1919 : ATOM_DEVICE_CRT2_SUPPORT,
1920 : 2),
1921 : ATOM_DEVICE_CRT2_SUPPORT);
1922 0 : radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1923 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1924 : CONNECTOR_OBJECT_ID_VGA,
1925 : &hpd);
1926 : /* TV - TV DAC */
1927 0 : ddc_i2c.valid = false;
1928 0 : hpd.hpd = RADEON_HPD_NONE;
1929 0 : radeon_add_legacy_encoder(dev,
1930 0 : radeon_get_encoder_enum(dev,
1931 : ATOM_DEVICE_TV1_SUPPORT,
1932 : 2),
1933 : ATOM_DEVICE_TV1_SUPPORT);
1934 0 : radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1935 : DRM_MODE_CONNECTOR_SVIDEO,
1936 : &ddc_i2c,
1937 : CONNECTOR_OBJECT_ID_SVIDEO,
1938 : &hpd);
1939 0 : break;
1940 : case CT_EMAC:
1941 : DRM_INFO("Connector Table: %d (emac)\n",
1942 : rdev->mode_info.connector_table);
1943 : /* VGA - primary dac */
1944 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1945 0 : hpd.hpd = RADEON_HPD_NONE;
1946 0 : radeon_add_legacy_encoder(dev,
1947 0 : radeon_get_encoder_enum(dev,
1948 : ATOM_DEVICE_CRT1_SUPPORT,
1949 : 1),
1950 : ATOM_DEVICE_CRT1_SUPPORT);
1951 0 : radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1952 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1953 : CONNECTOR_OBJECT_ID_VGA,
1954 : &hpd);
1955 : /* VGA - tv dac */
1956 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1957 0 : hpd.hpd = RADEON_HPD_NONE;
1958 0 : radeon_add_legacy_encoder(dev,
1959 0 : radeon_get_encoder_enum(dev,
1960 : ATOM_DEVICE_CRT2_SUPPORT,
1961 : 2),
1962 : ATOM_DEVICE_CRT2_SUPPORT);
1963 0 : radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1964 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1965 : CONNECTOR_OBJECT_ID_VGA,
1966 : &hpd);
1967 : /* TV - TV DAC */
1968 0 : ddc_i2c.valid = false;
1969 0 : hpd.hpd = RADEON_HPD_NONE;
1970 0 : radeon_add_legacy_encoder(dev,
1971 0 : radeon_get_encoder_enum(dev,
1972 : ATOM_DEVICE_TV1_SUPPORT,
1973 : 2),
1974 : ATOM_DEVICE_TV1_SUPPORT);
1975 0 : radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1976 : DRM_MODE_CONNECTOR_SVIDEO,
1977 : &ddc_i2c,
1978 : CONNECTOR_OBJECT_ID_SVIDEO,
1979 : &hpd);
1980 0 : break;
1981 : case CT_RN50_POWER:
1982 : DRM_INFO("Connector Table: %d (rn50-power)\n",
1983 : rdev->mode_info.connector_table);
1984 : /* VGA - primary dac */
1985 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1986 0 : hpd.hpd = RADEON_HPD_NONE;
1987 0 : radeon_add_legacy_encoder(dev,
1988 0 : radeon_get_encoder_enum(dev,
1989 : ATOM_DEVICE_CRT1_SUPPORT,
1990 : 1),
1991 : ATOM_DEVICE_CRT1_SUPPORT);
1992 0 : radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1993 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1994 : CONNECTOR_OBJECT_ID_VGA,
1995 : &hpd);
1996 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1997 0 : hpd.hpd = RADEON_HPD_NONE;
1998 0 : radeon_add_legacy_encoder(dev,
1999 0 : radeon_get_encoder_enum(dev,
2000 : ATOM_DEVICE_CRT2_SUPPORT,
2001 : 2),
2002 : ATOM_DEVICE_CRT2_SUPPORT);
2003 0 : radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2004 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2005 : CONNECTOR_OBJECT_ID_VGA,
2006 : &hpd);
2007 0 : break;
2008 : case CT_MAC_X800:
2009 : DRM_INFO("Connector Table: %d (mac x800)\n",
2010 : rdev->mode_info.connector_table);
2011 : /* DVI - primary dac, internal tmds */
2012 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2013 0 : hpd.hpd = RADEON_HPD_1; /* ??? */
2014 0 : radeon_add_legacy_encoder(dev,
2015 0 : radeon_get_encoder_enum(dev,
2016 : ATOM_DEVICE_DFP1_SUPPORT,
2017 : 0),
2018 : ATOM_DEVICE_DFP1_SUPPORT);
2019 0 : radeon_add_legacy_encoder(dev,
2020 0 : radeon_get_encoder_enum(dev,
2021 : ATOM_DEVICE_CRT1_SUPPORT,
2022 : 1),
2023 : ATOM_DEVICE_CRT1_SUPPORT);
2024 0 : radeon_add_legacy_connector(dev, 0,
2025 : ATOM_DEVICE_DFP1_SUPPORT |
2026 : ATOM_DEVICE_CRT1_SUPPORT,
2027 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2028 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2029 : &hpd);
2030 : /* DVI - tv dac, dvo */
2031 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2032 0 : hpd.hpd = RADEON_HPD_2; /* ??? */
2033 0 : radeon_add_legacy_encoder(dev,
2034 0 : radeon_get_encoder_enum(dev,
2035 : ATOM_DEVICE_DFP2_SUPPORT,
2036 : 0),
2037 : ATOM_DEVICE_DFP2_SUPPORT);
2038 0 : radeon_add_legacy_encoder(dev,
2039 0 : radeon_get_encoder_enum(dev,
2040 : ATOM_DEVICE_CRT2_SUPPORT,
2041 : 2),
2042 : ATOM_DEVICE_CRT2_SUPPORT);
2043 0 : radeon_add_legacy_connector(dev, 1,
2044 : ATOM_DEVICE_DFP2_SUPPORT |
2045 : ATOM_DEVICE_CRT2_SUPPORT,
2046 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2047 : CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2048 : &hpd);
2049 0 : break;
2050 : case CT_MAC_G5_9600:
2051 : DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2052 : rdev->mode_info.connector_table);
2053 : /* DVI - tv dac, dvo */
2054 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2055 0 : hpd.hpd = RADEON_HPD_1; /* ??? */
2056 0 : radeon_add_legacy_encoder(dev,
2057 0 : radeon_get_encoder_enum(dev,
2058 : ATOM_DEVICE_DFP2_SUPPORT,
2059 : 0),
2060 : ATOM_DEVICE_DFP2_SUPPORT);
2061 0 : radeon_add_legacy_encoder(dev,
2062 0 : radeon_get_encoder_enum(dev,
2063 : ATOM_DEVICE_CRT2_SUPPORT,
2064 : 2),
2065 : ATOM_DEVICE_CRT2_SUPPORT);
2066 0 : radeon_add_legacy_connector(dev, 0,
2067 : ATOM_DEVICE_DFP2_SUPPORT |
2068 : ATOM_DEVICE_CRT2_SUPPORT,
2069 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2070 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2071 : &hpd);
2072 : /* ADC - primary dac, internal tmds */
2073 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2074 0 : hpd.hpd = RADEON_HPD_2; /* ??? */
2075 0 : radeon_add_legacy_encoder(dev,
2076 0 : radeon_get_encoder_enum(dev,
2077 : ATOM_DEVICE_DFP1_SUPPORT,
2078 : 0),
2079 : ATOM_DEVICE_DFP1_SUPPORT);
2080 0 : radeon_add_legacy_encoder(dev,
2081 0 : radeon_get_encoder_enum(dev,
2082 : ATOM_DEVICE_CRT1_SUPPORT,
2083 : 1),
2084 : ATOM_DEVICE_CRT1_SUPPORT);
2085 0 : radeon_add_legacy_connector(dev, 1,
2086 : ATOM_DEVICE_DFP1_SUPPORT |
2087 : ATOM_DEVICE_CRT1_SUPPORT,
2088 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2089 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2090 : &hpd);
2091 : /* TV - TV DAC */
2092 0 : ddc_i2c.valid = false;
2093 0 : hpd.hpd = RADEON_HPD_NONE;
2094 0 : radeon_add_legacy_encoder(dev,
2095 0 : radeon_get_encoder_enum(dev,
2096 : ATOM_DEVICE_TV1_SUPPORT,
2097 : 2),
2098 : ATOM_DEVICE_TV1_SUPPORT);
2099 0 : radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2100 : DRM_MODE_CONNECTOR_SVIDEO,
2101 : &ddc_i2c,
2102 : CONNECTOR_OBJECT_ID_SVIDEO,
2103 : &hpd);
2104 0 : break;
2105 : case CT_SAM440EP:
2106 : DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2107 : rdev->mode_info.connector_table);
2108 : /* LVDS */
2109 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2110 0 : hpd.hpd = RADEON_HPD_NONE;
2111 0 : radeon_add_legacy_encoder(dev,
2112 0 : radeon_get_encoder_enum(dev,
2113 : ATOM_DEVICE_LCD1_SUPPORT,
2114 : 0),
2115 : ATOM_DEVICE_LCD1_SUPPORT);
2116 0 : radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2117 : DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2118 : CONNECTOR_OBJECT_ID_LVDS,
2119 : &hpd);
2120 : /* DVI-I - secondary dac, int tmds */
2121 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2122 0 : hpd.hpd = RADEON_HPD_1; /* ??? */
2123 0 : radeon_add_legacy_encoder(dev,
2124 0 : radeon_get_encoder_enum(dev,
2125 : ATOM_DEVICE_DFP1_SUPPORT,
2126 : 0),
2127 : ATOM_DEVICE_DFP1_SUPPORT);
2128 0 : radeon_add_legacy_encoder(dev,
2129 0 : radeon_get_encoder_enum(dev,
2130 : ATOM_DEVICE_CRT2_SUPPORT,
2131 : 2),
2132 : ATOM_DEVICE_CRT2_SUPPORT);
2133 0 : radeon_add_legacy_connector(dev, 1,
2134 : ATOM_DEVICE_DFP1_SUPPORT |
2135 : ATOM_DEVICE_CRT2_SUPPORT,
2136 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2137 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2138 : &hpd);
2139 : /* VGA - primary dac */
2140 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2141 0 : hpd.hpd = RADEON_HPD_NONE;
2142 0 : radeon_add_legacy_encoder(dev,
2143 0 : radeon_get_encoder_enum(dev,
2144 : ATOM_DEVICE_CRT1_SUPPORT,
2145 : 1),
2146 : ATOM_DEVICE_CRT1_SUPPORT);
2147 0 : radeon_add_legacy_connector(dev, 2,
2148 : ATOM_DEVICE_CRT1_SUPPORT,
2149 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2150 : CONNECTOR_OBJECT_ID_VGA,
2151 : &hpd);
2152 : /* TV - TV DAC */
2153 0 : ddc_i2c.valid = false;
2154 0 : hpd.hpd = RADEON_HPD_NONE;
2155 0 : radeon_add_legacy_encoder(dev,
2156 0 : radeon_get_encoder_enum(dev,
2157 : ATOM_DEVICE_TV1_SUPPORT,
2158 : 2),
2159 : ATOM_DEVICE_TV1_SUPPORT);
2160 0 : radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2161 : DRM_MODE_CONNECTOR_SVIDEO,
2162 : &ddc_i2c,
2163 : CONNECTOR_OBJECT_ID_SVIDEO,
2164 : &hpd);
2165 0 : break;
2166 : case CT_MAC_G4_SILVER:
2167 : DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2168 : rdev->mode_info.connector_table);
2169 : /* DVI-I - tv dac, int tmds */
2170 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2171 0 : hpd.hpd = RADEON_HPD_1; /* ??? */
2172 0 : radeon_add_legacy_encoder(dev,
2173 0 : radeon_get_encoder_enum(dev,
2174 : ATOM_DEVICE_DFP1_SUPPORT,
2175 : 0),
2176 : ATOM_DEVICE_DFP1_SUPPORT);
2177 0 : radeon_add_legacy_encoder(dev,
2178 0 : radeon_get_encoder_enum(dev,
2179 : ATOM_DEVICE_CRT2_SUPPORT,
2180 : 2),
2181 : ATOM_DEVICE_CRT2_SUPPORT);
2182 0 : radeon_add_legacy_connector(dev, 0,
2183 : ATOM_DEVICE_DFP1_SUPPORT |
2184 : ATOM_DEVICE_CRT2_SUPPORT,
2185 : DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2186 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2187 : &hpd);
2188 : /* VGA - primary dac */
2189 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2190 0 : hpd.hpd = RADEON_HPD_NONE;
2191 0 : radeon_add_legacy_encoder(dev,
2192 0 : radeon_get_encoder_enum(dev,
2193 : ATOM_DEVICE_CRT1_SUPPORT,
2194 : 1),
2195 : ATOM_DEVICE_CRT1_SUPPORT);
2196 0 : radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2197 : DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2198 : CONNECTOR_OBJECT_ID_VGA,
2199 : &hpd);
2200 : /* TV - TV DAC */
2201 0 : ddc_i2c.valid = false;
2202 0 : hpd.hpd = RADEON_HPD_NONE;
2203 0 : radeon_add_legacy_encoder(dev,
2204 0 : radeon_get_encoder_enum(dev,
2205 : ATOM_DEVICE_TV1_SUPPORT,
2206 : 2),
2207 : ATOM_DEVICE_TV1_SUPPORT);
2208 0 : radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2209 : DRM_MODE_CONNECTOR_SVIDEO,
2210 : &ddc_i2c,
2211 : CONNECTOR_OBJECT_ID_SVIDEO,
2212 : &hpd);
2213 0 : break;
2214 : default:
2215 : DRM_INFO("Connector table: %d (invalid)\n",
2216 : rdev->mode_info.connector_table);
2217 0 : return false;
2218 : }
2219 :
2220 0 : radeon_link_encoder_connector(dev);
2221 :
2222 0 : return true;
2223 0 : }
2224 :
2225 0 : static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2226 : int bios_index,
2227 : enum radeon_combios_connector
2228 : *legacy_connector,
2229 : struct radeon_i2c_bus_rec *ddc_i2c,
2230 : struct radeon_hpd *hpd)
2231 : {
2232 :
2233 : /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2234 : one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2235 0 : if (dev->pdev->device == 0x515e &&
2236 0 : dev->pdev->subsystem_vendor == 0x1014) {
2237 0 : if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2238 0 : ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2239 0 : return false;
2240 : }
2241 :
2242 : /* X300 card with extra non-existent DVI port */
2243 0 : if (dev->pdev->device == 0x5B60 &&
2244 0 : dev->pdev->subsystem_vendor == 0x17af &&
2245 0 : dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2246 0 : if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2247 0 : return false;
2248 : }
2249 :
2250 0 : return true;
2251 0 : }
2252 :
2253 0 : static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2254 : {
2255 : /* Acer 5102 has non-existent TV port */
2256 0 : if (dev->pdev->device == 0x5975 &&
2257 0 : dev->pdev->subsystem_vendor == 0x1025 &&
2258 0 : dev->pdev->subsystem_device == 0x009f)
2259 0 : return false;
2260 :
2261 : /* HP dc5750 has non-existent TV port */
2262 0 : if (dev->pdev->device == 0x5974 &&
2263 0 : dev->pdev->subsystem_vendor == 0x103c &&
2264 0 : dev->pdev->subsystem_device == 0x280a)
2265 0 : return false;
2266 :
2267 : /* MSI S270 has non-existent TV port */
2268 0 : if (dev->pdev->device == 0x5955 &&
2269 0 : dev->pdev->subsystem_vendor == 0x1462 &&
2270 0 : dev->pdev->subsystem_device == 0x0131)
2271 0 : return false;
2272 :
2273 0 : return true;
2274 0 : }
2275 :
2276 0 : static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2277 : {
2278 0 : struct radeon_device *rdev = dev->dev_private;
2279 : uint32_t ext_tmds_info;
2280 :
2281 0 : if (rdev->flags & RADEON_IS_IGP) {
2282 0 : if (is_dvi_d)
2283 0 : return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2284 : else
2285 0 : return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2286 : }
2287 0 : ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2288 0 : if (ext_tmds_info) {
2289 0 : uint8_t rev = RBIOS8(ext_tmds_info);
2290 0 : uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2291 0 : if (rev >= 3) {
2292 0 : if (is_dvi_d)
2293 0 : return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2294 : else
2295 0 : return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2296 : } else {
2297 0 : if (flags & 1) {
2298 0 : if (is_dvi_d)
2299 0 : return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2300 : else
2301 0 : return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2302 : }
2303 : }
2304 0 : }
2305 0 : if (is_dvi_d)
2306 0 : return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2307 : else
2308 0 : return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2309 0 : }
2310 :
2311 0 : bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2312 : {
2313 0 : struct radeon_device *rdev = dev->dev_private;
2314 : uint32_t conn_info, entry, devices;
2315 : uint16_t tmp, connector_object_id;
2316 : enum radeon_combios_ddc ddc_type;
2317 0 : enum radeon_combios_connector connector;
2318 : int i = 0;
2319 0 : struct radeon_i2c_bus_rec ddc_i2c;
2320 0 : struct radeon_hpd hpd;
2321 :
2322 0 : conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2323 0 : if (conn_info) {
2324 0 : for (i = 0; i < 4; i++) {
2325 0 : entry = conn_info + 2 + i * 2;
2326 :
2327 0 : if (!RBIOS16(entry))
2328 : break;
2329 :
2330 0 : tmp = RBIOS16(entry);
2331 :
2332 0 : connector = (tmp >> 12) & 0xf;
2333 :
2334 0 : ddc_type = (tmp >> 8) & 0xf;
2335 0 : if (ddc_type == 5)
2336 0 : ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2337 : else
2338 0 : ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2339 :
2340 0 : switch (connector) {
2341 : case CONNECTOR_PROPRIETARY_LEGACY:
2342 : case CONNECTOR_DVI_I_LEGACY:
2343 : case CONNECTOR_DVI_D_LEGACY:
2344 0 : if ((tmp >> 4) & 0x1)
2345 0 : hpd.hpd = RADEON_HPD_2;
2346 : else
2347 0 : hpd.hpd = RADEON_HPD_1;
2348 : break;
2349 : default:
2350 0 : hpd.hpd = RADEON_HPD_NONE;
2351 0 : break;
2352 : }
2353 :
2354 0 : if (!radeon_apply_legacy_quirks(dev, i, &connector,
2355 : &ddc_i2c, &hpd))
2356 : continue;
2357 :
2358 0 : switch (connector) {
2359 : case CONNECTOR_PROPRIETARY_LEGACY:
2360 0 : if ((tmp >> 4) & 0x1)
2361 0 : devices = ATOM_DEVICE_DFP2_SUPPORT;
2362 : else
2363 : devices = ATOM_DEVICE_DFP1_SUPPORT;
2364 0 : radeon_add_legacy_encoder(dev,
2365 0 : radeon_get_encoder_enum
2366 : (dev, devices, 0),
2367 : devices);
2368 0 : radeon_add_legacy_connector(dev, i, devices,
2369 0 : legacy_connector_convert
2370 0 : [connector],
2371 : &ddc_i2c,
2372 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2373 : &hpd);
2374 0 : break;
2375 : case CONNECTOR_CRT_LEGACY:
2376 0 : if (tmp & 0x1) {
2377 : devices = ATOM_DEVICE_CRT2_SUPPORT;
2378 0 : radeon_add_legacy_encoder(dev,
2379 0 : radeon_get_encoder_enum
2380 : (dev,
2381 : ATOM_DEVICE_CRT2_SUPPORT,
2382 : 2),
2383 : ATOM_DEVICE_CRT2_SUPPORT);
2384 0 : } else {
2385 : devices = ATOM_DEVICE_CRT1_SUPPORT;
2386 0 : radeon_add_legacy_encoder(dev,
2387 0 : radeon_get_encoder_enum
2388 : (dev,
2389 : ATOM_DEVICE_CRT1_SUPPORT,
2390 : 1),
2391 : ATOM_DEVICE_CRT1_SUPPORT);
2392 : }
2393 0 : radeon_add_legacy_connector(dev,
2394 : i,
2395 : devices,
2396 0 : legacy_connector_convert
2397 0 : [connector],
2398 : &ddc_i2c,
2399 : CONNECTOR_OBJECT_ID_VGA,
2400 : &hpd);
2401 0 : break;
2402 : case CONNECTOR_DVI_I_LEGACY:
2403 : devices = 0;
2404 0 : if (tmp & 0x1) {
2405 : devices |= ATOM_DEVICE_CRT2_SUPPORT;
2406 0 : radeon_add_legacy_encoder(dev,
2407 0 : radeon_get_encoder_enum
2408 : (dev,
2409 : ATOM_DEVICE_CRT2_SUPPORT,
2410 : 2),
2411 : ATOM_DEVICE_CRT2_SUPPORT);
2412 0 : } else {
2413 : devices |= ATOM_DEVICE_CRT1_SUPPORT;
2414 0 : radeon_add_legacy_encoder(dev,
2415 0 : radeon_get_encoder_enum
2416 : (dev,
2417 : ATOM_DEVICE_CRT1_SUPPORT,
2418 : 1),
2419 : ATOM_DEVICE_CRT1_SUPPORT);
2420 : }
2421 : /* RV100 board with external TDMS bit mis-set.
2422 : * Actually uses internal TMDS, clear the bit.
2423 : */
2424 0 : if (dev->pdev->device == 0x5159 &&
2425 0 : dev->pdev->subsystem_vendor == 0x1014 &&
2426 0 : dev->pdev->subsystem_device == 0x029A) {
2427 0 : tmp &= ~(1 << 4);
2428 0 : }
2429 0 : if ((tmp >> 4) & 0x1) {
2430 0 : devices |= ATOM_DEVICE_DFP2_SUPPORT;
2431 0 : radeon_add_legacy_encoder(dev,
2432 0 : radeon_get_encoder_enum
2433 : (dev,
2434 : ATOM_DEVICE_DFP2_SUPPORT,
2435 : 0),
2436 : ATOM_DEVICE_DFP2_SUPPORT);
2437 0 : connector_object_id = combios_check_dl_dvi(dev, 0);
2438 0 : } else {
2439 0 : devices |= ATOM_DEVICE_DFP1_SUPPORT;
2440 0 : radeon_add_legacy_encoder(dev,
2441 0 : radeon_get_encoder_enum
2442 : (dev,
2443 : ATOM_DEVICE_DFP1_SUPPORT,
2444 : 0),
2445 : ATOM_DEVICE_DFP1_SUPPORT);
2446 : connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2447 : }
2448 0 : radeon_add_legacy_connector(dev,
2449 : i,
2450 : devices,
2451 0 : legacy_connector_convert
2452 0 : [connector],
2453 : &ddc_i2c,
2454 : connector_object_id,
2455 : &hpd);
2456 0 : break;
2457 : case CONNECTOR_DVI_D_LEGACY:
2458 0 : if ((tmp >> 4) & 0x1) {
2459 : devices = ATOM_DEVICE_DFP2_SUPPORT;
2460 0 : connector_object_id = combios_check_dl_dvi(dev, 1);
2461 0 : } else {
2462 : devices = ATOM_DEVICE_DFP1_SUPPORT;
2463 : connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2464 : }
2465 0 : radeon_add_legacy_encoder(dev,
2466 0 : radeon_get_encoder_enum
2467 : (dev, devices, 0),
2468 : devices);
2469 0 : radeon_add_legacy_connector(dev, i, devices,
2470 0 : legacy_connector_convert
2471 0 : [connector],
2472 : &ddc_i2c,
2473 : connector_object_id,
2474 : &hpd);
2475 0 : break;
2476 : case CONNECTOR_CTV_LEGACY:
2477 : case CONNECTOR_STV_LEGACY:
2478 0 : radeon_add_legacy_encoder(dev,
2479 0 : radeon_get_encoder_enum
2480 : (dev,
2481 : ATOM_DEVICE_TV1_SUPPORT,
2482 : 2),
2483 : ATOM_DEVICE_TV1_SUPPORT);
2484 0 : radeon_add_legacy_connector(dev, i,
2485 : ATOM_DEVICE_TV1_SUPPORT,
2486 0 : legacy_connector_convert
2487 0 : [connector],
2488 : &ddc_i2c,
2489 : CONNECTOR_OBJECT_ID_SVIDEO,
2490 : &hpd);
2491 0 : break;
2492 : default:
2493 0 : DRM_ERROR("Unknown connector type: %d\n",
2494 : connector);
2495 0 : continue;
2496 : }
2497 :
2498 : }
2499 : } else {
2500 : uint16_t tmds_info =
2501 0 : combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2502 0 : if (tmds_info) {
2503 : DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2504 :
2505 0 : radeon_add_legacy_encoder(dev,
2506 0 : radeon_get_encoder_enum(dev,
2507 : ATOM_DEVICE_CRT1_SUPPORT,
2508 : 1),
2509 : ATOM_DEVICE_CRT1_SUPPORT);
2510 0 : radeon_add_legacy_encoder(dev,
2511 0 : radeon_get_encoder_enum(dev,
2512 : ATOM_DEVICE_DFP1_SUPPORT,
2513 : 0),
2514 : ATOM_DEVICE_DFP1_SUPPORT);
2515 :
2516 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2517 0 : hpd.hpd = RADEON_HPD_1;
2518 0 : radeon_add_legacy_connector(dev,
2519 : 0,
2520 : ATOM_DEVICE_CRT1_SUPPORT |
2521 : ATOM_DEVICE_DFP1_SUPPORT,
2522 : DRM_MODE_CONNECTOR_DVII,
2523 : &ddc_i2c,
2524 : CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2525 : &hpd);
2526 0 : } else {
2527 : uint16_t crt_info =
2528 0 : combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2529 : DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2530 0 : if (crt_info) {
2531 0 : radeon_add_legacy_encoder(dev,
2532 0 : radeon_get_encoder_enum(dev,
2533 : ATOM_DEVICE_CRT1_SUPPORT,
2534 : 1),
2535 : ATOM_DEVICE_CRT1_SUPPORT);
2536 0 : ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2537 0 : hpd.hpd = RADEON_HPD_NONE;
2538 0 : radeon_add_legacy_connector(dev,
2539 : 0,
2540 : ATOM_DEVICE_CRT1_SUPPORT,
2541 : DRM_MODE_CONNECTOR_VGA,
2542 : &ddc_i2c,
2543 : CONNECTOR_OBJECT_ID_VGA,
2544 : &hpd);
2545 : } else {
2546 : DRM_DEBUG_KMS("No connector info found\n");
2547 0 : return false;
2548 : }
2549 0 : }
2550 0 : }
2551 :
2552 0 : if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2553 : uint16_t lcd_info =
2554 0 : combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2555 0 : if (lcd_info) {
2556 : uint16_t lcd_ddc_info =
2557 0 : combios_get_table_offset(dev,
2558 : COMBIOS_LCD_DDC_INFO_TABLE);
2559 :
2560 0 : radeon_add_legacy_encoder(dev,
2561 0 : radeon_get_encoder_enum(dev,
2562 : ATOM_DEVICE_LCD1_SUPPORT,
2563 : 0),
2564 : ATOM_DEVICE_LCD1_SUPPORT);
2565 :
2566 0 : if (lcd_ddc_info) {
2567 0 : ddc_type = RBIOS8(lcd_ddc_info + 2);
2568 0 : switch (ddc_type) {
2569 : case DDC_LCD:
2570 : ddc_i2c =
2571 0 : combios_setup_i2c_bus(rdev,
2572 : DDC_LCD,
2573 0 : RBIOS32(lcd_ddc_info + 3),
2574 0 : RBIOS32(lcd_ddc_info + 7));
2575 0 : radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2576 0 : break;
2577 : case DDC_GPIO:
2578 : ddc_i2c =
2579 0 : combios_setup_i2c_bus(rdev,
2580 : DDC_GPIO,
2581 0 : RBIOS32(lcd_ddc_info + 3),
2582 0 : RBIOS32(lcd_ddc_info + 7));
2583 0 : radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2584 0 : break;
2585 : default:
2586 : ddc_i2c =
2587 0 : combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2588 0 : break;
2589 : }
2590 : DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2591 : } else
2592 0 : ddc_i2c.valid = false;
2593 :
2594 0 : hpd.hpd = RADEON_HPD_NONE;
2595 0 : radeon_add_legacy_connector(dev,
2596 : 5,
2597 : ATOM_DEVICE_LCD1_SUPPORT,
2598 : DRM_MODE_CONNECTOR_LVDS,
2599 : &ddc_i2c,
2600 : CONNECTOR_OBJECT_ID_LVDS,
2601 : &hpd);
2602 0 : }
2603 0 : }
2604 :
2605 : /* check TV table */
2606 0 : if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2607 : uint32_t tv_info =
2608 0 : combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2609 0 : if (tv_info) {
2610 0 : if (RBIOS8(tv_info + 6) == 'T') {
2611 0 : if (radeon_apply_legacy_tv_quirks(dev)) {
2612 0 : hpd.hpd = RADEON_HPD_NONE;
2613 0 : ddc_i2c.valid = false;
2614 0 : radeon_add_legacy_encoder(dev,
2615 0 : radeon_get_encoder_enum
2616 : (dev,
2617 : ATOM_DEVICE_TV1_SUPPORT,
2618 : 2),
2619 : ATOM_DEVICE_TV1_SUPPORT);
2620 0 : radeon_add_legacy_connector(dev, 6,
2621 : ATOM_DEVICE_TV1_SUPPORT,
2622 : DRM_MODE_CONNECTOR_SVIDEO,
2623 : &ddc_i2c,
2624 : CONNECTOR_OBJECT_ID_SVIDEO,
2625 : &hpd);
2626 0 : }
2627 : }
2628 : }
2629 0 : }
2630 :
2631 0 : radeon_link_encoder_connector(dev);
2632 :
2633 0 : return true;
2634 0 : }
2635 :
2636 : #ifdef DRMDEBUG
2637 : static const char *thermal_controller_names[] = {
2638 : "NONE",
2639 : "lm63",
2640 : "adm1032",
2641 : };
2642 : #endif
2643 :
2644 0 : void radeon_combios_get_power_modes(struct radeon_device *rdev)
2645 : {
2646 0 : struct drm_device *dev = rdev->ddev;
2647 : u16 offset, misc, misc2 = 0;
2648 : u8 rev, blocks, tmp;
2649 : int state_index = 0;
2650 0 : struct radeon_i2c_bus_rec i2c_bus;
2651 :
2652 0 : rdev->pm.default_power_state_index = -1;
2653 :
2654 : /* allocate 2 power states */
2655 0 : rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2656 0 : if (rdev->pm.power_state) {
2657 : /* allocate 1 clock mode per state */
2658 0 : rdev->pm.power_state[0].clock_info =
2659 0 : kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2660 0 : rdev->pm.power_state[1].clock_info =
2661 0 : kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2662 0 : if (!rdev->pm.power_state[0].clock_info ||
2663 0 : !rdev->pm.power_state[1].clock_info)
2664 : goto pm_failed;
2665 : } else
2666 : goto pm_failed;
2667 :
2668 : /* check for a thermal chip */
2669 0 : offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2670 0 : if (offset) {
2671 : u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2672 :
2673 0 : rev = RBIOS8(offset);
2674 :
2675 0 : if (rev == 0) {
2676 0 : thermal_controller = RBIOS8(offset + 3);
2677 0 : gpio = RBIOS8(offset + 4) & 0x3f;
2678 0 : i2c_addr = RBIOS8(offset + 5);
2679 0 : } else if (rev == 1) {
2680 0 : thermal_controller = RBIOS8(offset + 4);
2681 0 : gpio = RBIOS8(offset + 5) & 0x3f;
2682 0 : i2c_addr = RBIOS8(offset + 6);
2683 0 : } else if (rev == 2) {
2684 0 : thermal_controller = RBIOS8(offset + 4);
2685 0 : gpio = RBIOS8(offset + 5) & 0x3f;
2686 0 : i2c_addr = RBIOS8(offset + 6);
2687 0 : clk_bit = RBIOS8(offset + 0xa);
2688 0 : data_bit = RBIOS8(offset + 0xb);
2689 0 : }
2690 0 : if ((thermal_controller > 0) && (thermal_controller < 3)) {
2691 : DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2692 : thermal_controller_names[thermal_controller],
2693 : i2c_addr >> 1);
2694 0 : if (gpio == DDC_LCD) {
2695 : /* MM i2c */
2696 0 : i2c_bus.valid = true;
2697 0 : i2c_bus.hw_capable = true;
2698 0 : i2c_bus.mm_i2c = true;
2699 0 : i2c_bus.i2c_id = 0xa0;
2700 0 : } else if (gpio == DDC_GPIO)
2701 0 : i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2702 : else
2703 0 : i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2704 0 : rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2705 : #ifdef notyet
2706 : if (rdev->pm.i2c_bus) {
2707 : struct i2c_board_info info = { };
2708 : const char *name = thermal_controller_names[thermal_controller];
2709 : info.addr = i2c_addr >> 1;
2710 : strlcpy(info.type, name, sizeof(info.type));
2711 : i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2712 : }
2713 : #endif
2714 0 : }
2715 0 : } else {
2716 : /* boards with a thermal chip, but no overdrive table */
2717 :
2718 : /* Asus 9600xt has an f75375 on the monid bus */
2719 0 : if ((dev->pdev->device == 0x4152) &&
2720 0 : (dev->pdev->subsystem_vendor == 0x1043) &&
2721 0 : (dev->pdev->subsystem_device == 0xc002)) {
2722 0 : i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2723 0 : rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2724 : #ifdef notyet
2725 : if (rdev->pm.i2c_bus) {
2726 : struct i2c_board_info info = { };
2727 : const char *name = "f75375";
2728 : info.addr = 0x28;
2729 : strlcpy(info.type, name, sizeof(info.type));
2730 : i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2731 : DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2732 : name, info.addr);
2733 : }
2734 : #endif
2735 0 : }
2736 : }
2737 :
2738 0 : if (rdev->flags & RADEON_IS_MOBILITY) {
2739 0 : offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2740 0 : if (offset) {
2741 0 : rev = RBIOS8(offset);
2742 0 : blocks = RBIOS8(offset + 0x2);
2743 : /* power mode 0 tends to be the only valid one */
2744 0 : rdev->pm.power_state[state_index].num_clock_modes = 1;
2745 0 : rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2746 0 : rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2747 0 : if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2748 0 : (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2749 : goto default_mode;
2750 0 : rdev->pm.power_state[state_index].type =
2751 : POWER_STATE_TYPE_BATTERY;
2752 0 : misc = RBIOS16(offset + 0x5 + 0x0);
2753 0 : if (rev > 4)
2754 0 : misc2 = RBIOS16(offset + 0x5 + 0xe);
2755 0 : rdev->pm.power_state[state_index].misc = misc;
2756 0 : rdev->pm.power_state[state_index].misc2 = misc2;
2757 0 : if (misc & 0x4) {
2758 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2759 0 : if (misc & 0x8)
2760 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2761 : true;
2762 : else
2763 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2764 : false;
2765 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2766 0 : if (rev < 6) {
2767 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2768 0 : RBIOS16(offset + 0x5 + 0xb) * 4;
2769 0 : tmp = RBIOS8(offset + 0x5 + 0xd);
2770 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2771 0 : } else {
2772 0 : u8 entries = RBIOS8(offset + 0x5 + 0xb);
2773 0 : u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2774 0 : if (entries && voltage_table_offset) {
2775 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2776 0 : RBIOS16(voltage_table_offset) * 4;
2777 0 : tmp = RBIOS8(voltage_table_offset + 0x2);
2778 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2779 0 : } else
2780 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2781 : }
2782 0 : switch ((misc2 & 0x700) >> 8) {
2783 : case 0:
2784 : default:
2785 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2786 0 : break;
2787 : case 1:
2788 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2789 0 : break;
2790 : case 2:
2791 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2792 0 : break;
2793 : case 3:
2794 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2795 0 : break;
2796 : case 4:
2797 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2798 0 : break;
2799 : }
2800 : } else
2801 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2802 0 : if (rev > 6)
2803 0 : rdev->pm.power_state[state_index].pcie_lanes =
2804 0 : RBIOS8(offset + 0x5 + 0x10);
2805 0 : rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2806 : state_index++;
2807 0 : } else {
2808 : /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2809 : }
2810 : } else {
2811 : /* XXX figure out some good default low power mode for desktop cards */
2812 : }
2813 :
2814 : default_mode:
2815 : /* add the default mode */
2816 0 : rdev->pm.power_state[state_index].type =
2817 : POWER_STATE_TYPE_DEFAULT;
2818 0 : rdev->pm.power_state[state_index].num_clock_modes = 1;
2819 0 : rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2820 0 : rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2821 0 : rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2822 0 : if ((state_index > 0) &&
2823 0 : (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2824 0 : rdev->pm.power_state[state_index].clock_info[0].voltage =
2825 0 : rdev->pm.power_state[0].clock_info[0].voltage;
2826 : else
2827 0 : rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2828 0 : rdev->pm.power_state[state_index].pcie_lanes = 16;
2829 0 : rdev->pm.power_state[state_index].flags = 0;
2830 0 : rdev->pm.default_power_state_index = state_index;
2831 0 : rdev->pm.num_power_states = state_index + 1;
2832 :
2833 0 : rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2834 0 : rdev->pm.current_clock_mode_index = 0;
2835 0 : return;
2836 :
2837 : pm_failed:
2838 0 : rdev->pm.default_power_state_index = state_index;
2839 0 : rdev->pm.num_power_states = 0;
2840 :
2841 0 : rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2842 0 : rdev->pm.current_clock_mode_index = 0;
2843 0 : }
2844 :
2845 0 : void radeon_external_tmds_setup(struct drm_encoder *encoder)
2846 : {
2847 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2848 0 : struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2849 :
2850 0 : if (!tmds)
2851 0 : return;
2852 :
2853 0 : switch (tmds->dvo_chip) {
2854 : case DVO_SIL164:
2855 : /* sil 164 */
2856 0 : radeon_i2c_put_byte(tmds->i2c_bus,
2857 0 : tmds->slave_addr,
2858 : 0x08, 0x30);
2859 0 : radeon_i2c_put_byte(tmds->i2c_bus,
2860 0 : tmds->slave_addr,
2861 : 0x09, 0x00);
2862 0 : radeon_i2c_put_byte(tmds->i2c_bus,
2863 0 : tmds->slave_addr,
2864 : 0x0a, 0x90);
2865 0 : radeon_i2c_put_byte(tmds->i2c_bus,
2866 0 : tmds->slave_addr,
2867 : 0x0c, 0x89);
2868 0 : radeon_i2c_put_byte(tmds->i2c_bus,
2869 0 : tmds->slave_addr,
2870 : 0x08, 0x3b);
2871 0 : break;
2872 : case DVO_SIL1178:
2873 : /* sil 1178 - untested */
2874 : /*
2875 : * 0x0f, 0x44
2876 : * 0x0f, 0x4c
2877 : * 0x0e, 0x01
2878 : * 0x0a, 0x80
2879 : * 0x09, 0x30
2880 : * 0x0c, 0xc9
2881 : * 0x0d, 0x70
2882 : * 0x08, 0x32
2883 : * 0x08, 0x33
2884 : */
2885 : break;
2886 : default:
2887 : break;
2888 : }
2889 :
2890 0 : }
2891 :
2892 0 : bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2893 : {
2894 0 : struct drm_device *dev = encoder->dev;
2895 0 : struct radeon_device *rdev = dev->dev_private;
2896 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2897 : uint16_t offset;
2898 : uint8_t blocks, slave_addr, rev;
2899 : uint32_t index, id;
2900 : uint32_t reg, val, and_mask, or_mask;
2901 0 : struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2902 :
2903 0 : if (!tmds)
2904 0 : return false;
2905 :
2906 0 : if (rdev->flags & RADEON_IS_IGP) {
2907 0 : offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2908 0 : rev = RBIOS8(offset);
2909 0 : if (offset) {
2910 0 : rev = RBIOS8(offset);
2911 0 : if (rev > 1) {
2912 0 : blocks = RBIOS8(offset + 3);
2913 0 : index = offset + 4;
2914 0 : while (blocks > 0) {
2915 0 : id = RBIOS16(index);
2916 0 : index += 2;
2917 0 : switch (id >> 13) {
2918 : case 0:
2919 0 : reg = (id & 0x1fff) * 4;
2920 0 : val = RBIOS32(index);
2921 0 : index += 4;
2922 0 : WREG32(reg, val);
2923 0 : break;
2924 : case 2:
2925 0 : reg = (id & 0x1fff) * 4;
2926 0 : and_mask = RBIOS32(index);
2927 0 : index += 4;
2928 0 : or_mask = RBIOS32(index);
2929 0 : index += 4;
2930 0 : val = RREG32(reg);
2931 0 : val = (val & and_mask) | or_mask;
2932 0 : WREG32(reg, val);
2933 0 : break;
2934 : case 3:
2935 0 : val = RBIOS16(index);
2936 0 : index += 2;
2937 0 : udelay(val);
2938 0 : break;
2939 : case 4:
2940 0 : val = RBIOS16(index);
2941 0 : index += 2;
2942 0 : mdelay(val);
2943 0 : break;
2944 : case 6:
2945 0 : slave_addr = id & 0xff;
2946 0 : slave_addr >>= 1; /* 7 bit addressing */
2947 0 : index++;
2948 0 : reg = RBIOS8(index);
2949 0 : index++;
2950 0 : val = RBIOS8(index);
2951 0 : index++;
2952 0 : radeon_i2c_put_byte(tmds->i2c_bus,
2953 : slave_addr,
2954 : reg, val);
2955 0 : break;
2956 : default:
2957 0 : DRM_ERROR("Unknown id %d\n", id >> 13);
2958 0 : break;
2959 : }
2960 0 : blocks--;
2961 : }
2962 0 : return true;
2963 : }
2964 : }
2965 : } else {
2966 0 : offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2967 0 : if (offset) {
2968 0 : index = offset + 10;
2969 0 : id = RBIOS16(index);
2970 0 : while (id != 0xffff) {
2971 0 : index += 2;
2972 0 : switch (id >> 13) {
2973 : case 0:
2974 0 : reg = (id & 0x1fff) * 4;
2975 0 : val = RBIOS32(index);
2976 0 : WREG32(reg, val);
2977 0 : break;
2978 : case 2:
2979 0 : reg = (id & 0x1fff) * 4;
2980 0 : and_mask = RBIOS32(index);
2981 0 : index += 4;
2982 0 : or_mask = RBIOS32(index);
2983 0 : index += 4;
2984 0 : val = RREG32(reg);
2985 0 : val = (val & and_mask) | or_mask;
2986 0 : WREG32(reg, val);
2987 0 : break;
2988 : case 4:
2989 0 : val = RBIOS16(index);
2990 0 : index += 2;
2991 0 : udelay(val);
2992 0 : break;
2993 : case 5:
2994 0 : reg = id & 0x1fff;
2995 0 : and_mask = RBIOS32(index);
2996 0 : index += 4;
2997 0 : or_mask = RBIOS32(index);
2998 0 : index += 4;
2999 0 : val = RREG32_PLL(reg);
3000 0 : val = (val & and_mask) | or_mask;
3001 0 : WREG32_PLL(reg, val);
3002 0 : break;
3003 : case 6:
3004 0 : reg = id & 0x1fff;
3005 0 : val = RBIOS8(index);
3006 0 : index += 1;
3007 0 : radeon_i2c_put_byte(tmds->i2c_bus,
3008 0 : tmds->slave_addr,
3009 0 : reg, val);
3010 0 : break;
3011 : default:
3012 0 : DRM_ERROR("Unknown id %d\n", id >> 13);
3013 0 : break;
3014 : }
3015 0 : id = RBIOS16(index);
3016 : }
3017 0 : return true;
3018 : }
3019 : }
3020 0 : return false;
3021 0 : }
3022 :
3023 0 : static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3024 : {
3025 0 : struct radeon_device *rdev = dev->dev_private;
3026 :
3027 0 : if (offset) {
3028 0 : while (RBIOS16(offset)) {
3029 0 : uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3030 0 : uint32_t addr = (RBIOS16(offset) & 0x1fff);
3031 : uint32_t val, and_mask, or_mask;
3032 : uint32_t tmp;
3033 :
3034 0 : offset += 2;
3035 0 : switch (cmd) {
3036 : case 0:
3037 0 : val = RBIOS32(offset);
3038 0 : offset += 4;
3039 0 : WREG32(addr, val);
3040 0 : break;
3041 : case 1:
3042 0 : val = RBIOS32(offset);
3043 0 : offset += 4;
3044 0 : WREG32(addr, val);
3045 0 : break;
3046 : case 2:
3047 0 : and_mask = RBIOS32(offset);
3048 0 : offset += 4;
3049 0 : or_mask = RBIOS32(offset);
3050 0 : offset += 4;
3051 0 : tmp = RREG32(addr);
3052 0 : tmp &= and_mask;
3053 0 : tmp |= or_mask;
3054 0 : WREG32(addr, tmp);
3055 0 : break;
3056 : case 3:
3057 0 : and_mask = RBIOS32(offset);
3058 0 : offset += 4;
3059 0 : or_mask = RBIOS32(offset);
3060 0 : offset += 4;
3061 0 : tmp = RREG32(addr);
3062 0 : tmp &= and_mask;
3063 0 : tmp |= or_mask;
3064 0 : WREG32(addr, tmp);
3065 0 : break;
3066 : case 4:
3067 0 : val = RBIOS16(offset);
3068 0 : offset += 2;
3069 0 : udelay(val);
3070 0 : break;
3071 : case 5:
3072 0 : val = RBIOS16(offset);
3073 0 : offset += 2;
3074 0 : switch (addr) {
3075 : case 8:
3076 0 : while (val--) {
3077 0 : if (!
3078 0 : (RREG32_PLL
3079 0 : (RADEON_CLK_PWRMGT_CNTL) &
3080 : RADEON_MC_BUSY))
3081 : break;
3082 : }
3083 : break;
3084 : case 9:
3085 0 : while (val--) {
3086 0 : if ((RREG32(RADEON_MC_STATUS) &
3087 : RADEON_MC_IDLE))
3088 : break;
3089 : }
3090 : break;
3091 : default:
3092 : break;
3093 : }
3094 : break;
3095 : default:
3096 : break;
3097 : }
3098 : }
3099 : }
3100 0 : }
3101 :
3102 0 : static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3103 : {
3104 0 : struct radeon_device *rdev = dev->dev_private;
3105 :
3106 0 : if (offset) {
3107 0 : while (RBIOS8(offset)) {
3108 0 : uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3109 0 : uint8_t addr = (RBIOS8(offset) & 0x3f);
3110 : uint32_t val, shift, tmp;
3111 : uint32_t and_mask, or_mask;
3112 :
3113 0 : offset++;
3114 0 : switch (cmd) {
3115 : case 0:
3116 0 : val = RBIOS32(offset);
3117 0 : offset += 4;
3118 0 : WREG32_PLL(addr, val);
3119 0 : break;
3120 : case 1:
3121 0 : shift = RBIOS8(offset) * 8;
3122 0 : offset++;
3123 0 : and_mask = RBIOS8(offset) << shift;
3124 0 : and_mask |= ~(0xff << shift);
3125 0 : offset++;
3126 0 : or_mask = RBIOS8(offset) << shift;
3127 0 : offset++;
3128 0 : tmp = RREG32_PLL(addr);
3129 0 : tmp &= and_mask;
3130 0 : tmp |= or_mask;
3131 0 : WREG32_PLL(addr, tmp);
3132 0 : break;
3133 : case 2:
3134 : case 3:
3135 : tmp = 1000;
3136 0 : switch (addr) {
3137 : case 1:
3138 0 : udelay(150);
3139 0 : break;
3140 : case 2:
3141 0 : mdelay(1);
3142 0 : break;
3143 : case 3:
3144 0 : while (tmp--) {
3145 0 : if (!
3146 0 : (RREG32_PLL
3147 0 : (RADEON_CLK_PWRMGT_CNTL) &
3148 : RADEON_MC_BUSY))
3149 : break;
3150 : }
3151 : break;
3152 : case 4:
3153 0 : while (tmp--) {
3154 0 : if (RREG32_PLL
3155 0 : (RADEON_CLK_PWRMGT_CNTL) &
3156 : RADEON_DLL_READY)
3157 : break;
3158 : }
3159 : break;
3160 : case 5:
3161 : tmp =
3162 0 : RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3163 0 : if (tmp & RADEON_CG_NO1_DEBUG_0) {
3164 : #if 0
3165 : uint32_t mclk_cntl =
3166 : RREG32_PLL
3167 : (RADEON_MCLK_CNTL);
3168 : mclk_cntl &= 0xffff0000;
3169 : /*mclk_cntl |= 0x00001111;*//* ??? */
3170 : WREG32_PLL(RADEON_MCLK_CNTL,
3171 : mclk_cntl);
3172 : mdelay(10);
3173 : #endif
3174 0 : WREG32_PLL
3175 : (RADEON_CLK_PWRMGT_CNTL,
3176 : tmp &
3177 : ~RADEON_CG_NO1_DEBUG_0);
3178 0 : mdelay(10);
3179 0 : }
3180 : break;
3181 : default:
3182 : break;
3183 : }
3184 : break;
3185 : default:
3186 : break;
3187 : }
3188 : }
3189 : }
3190 0 : }
3191 :
3192 0 : static void combios_parse_ram_reset_table(struct drm_device *dev,
3193 : uint16_t offset)
3194 : {
3195 0 : struct radeon_device *rdev = dev->dev_private;
3196 : uint32_t tmp;
3197 :
3198 0 : if (offset) {
3199 0 : uint8_t val = RBIOS8(offset);
3200 0 : while (val != 0xff) {
3201 0 : offset++;
3202 :
3203 0 : if (val == 0x0f) {
3204 : uint32_t channel_complete_mask;
3205 :
3206 0 : if (ASIC_IS_R300(rdev))
3207 0 : channel_complete_mask =
3208 : R300_MEM_PWRUP_COMPLETE;
3209 : else
3210 : channel_complete_mask =
3211 : RADEON_MEM_PWRUP_COMPLETE;
3212 : tmp = 20000;
3213 0 : while (tmp--) {
3214 0 : if ((RREG32(RADEON_MEM_STR_CNTL) &
3215 0 : channel_complete_mask) ==
3216 : channel_complete_mask)
3217 : break;
3218 : }
3219 0 : } else {
3220 0 : uint32_t or_mask = RBIOS16(offset);
3221 0 : offset += 2;
3222 :
3223 0 : tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3224 0 : tmp &= RADEON_SDRAM_MODE_MASK;
3225 0 : tmp |= or_mask;
3226 0 : WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3227 :
3228 0 : or_mask = val << 24;
3229 0 : tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3230 0 : tmp &= RADEON_B3MEM_RESET_MASK;
3231 0 : tmp |= or_mask;
3232 0 : WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3233 : }
3234 0 : val = RBIOS8(offset);
3235 : }
3236 0 : }
3237 0 : }
3238 :
3239 0 : static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3240 : int mem_addr_mapping)
3241 : {
3242 0 : struct radeon_device *rdev = dev->dev_private;
3243 : uint32_t mem_cntl;
3244 : uint32_t mem_size;
3245 : uint32_t addr = 0;
3246 :
3247 0 : mem_cntl = RREG32(RADEON_MEM_CNTL);
3248 0 : if (mem_cntl & RV100_HALF_MODE)
3249 0 : ram /= 2;
3250 : mem_size = ram;
3251 0 : mem_cntl &= ~(0xff << 8);
3252 0 : mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3253 0 : WREG32(RADEON_MEM_CNTL, mem_cntl);
3254 0 : RREG32(RADEON_MEM_CNTL);
3255 :
3256 : /* sdram reset ? */
3257 :
3258 : /* something like this???? */
3259 0 : while (ram--) {
3260 0 : addr = ram * 1024 * 1024;
3261 : /* write to each page */
3262 0 : WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3263 : /* read back and verify */
3264 0 : if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3265 0 : return 0;
3266 : }
3267 :
3268 0 : return mem_size;
3269 0 : }
3270 :
3271 0 : static void combios_write_ram_size(struct drm_device *dev)
3272 : {
3273 0 : struct radeon_device *rdev = dev->dev_private;
3274 : uint8_t rev;
3275 : uint16_t offset;
3276 : uint32_t mem_size = 0;
3277 : uint32_t mem_cntl = 0;
3278 :
3279 : /* should do something smarter here I guess... */
3280 0 : if (rdev->flags & RADEON_IS_IGP)
3281 0 : return;
3282 :
3283 : /* first check detected mem table */
3284 0 : offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3285 0 : if (offset) {
3286 0 : rev = RBIOS8(offset);
3287 0 : if (rev < 3) {
3288 0 : mem_cntl = RBIOS32(offset + 1);
3289 0 : mem_size = RBIOS16(offset + 5);
3290 0 : if ((rdev->family < CHIP_R200) &&
3291 0 : !ASIC_IS_RN50(rdev))
3292 0 : WREG32(RADEON_MEM_CNTL, mem_cntl);
3293 : }
3294 : }
3295 :
3296 0 : if (!mem_size) {
3297 : offset =
3298 0 : combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3299 0 : if (offset) {
3300 0 : rev = RBIOS8(offset - 1);
3301 0 : if (rev < 1) {
3302 0 : if ((rdev->family < CHIP_R200)
3303 0 : && !ASIC_IS_RN50(rdev)) {
3304 : int ram = 0;
3305 : int mem_addr_mapping = 0;
3306 :
3307 0 : while (RBIOS8(offset)) {
3308 0 : ram = RBIOS8(offset);
3309 : mem_addr_mapping =
3310 0 : RBIOS8(offset + 1);
3311 0 : if (mem_addr_mapping != 0x25)
3312 0 : ram *= 2;
3313 : mem_size =
3314 0 : combios_detect_ram(dev, ram,
3315 : mem_addr_mapping);
3316 0 : if (mem_size)
3317 : break;
3318 0 : offset += 2;
3319 : }
3320 0 : } else
3321 0 : mem_size = RBIOS8(offset);
3322 : } else {
3323 0 : mem_size = RBIOS8(offset);
3324 0 : mem_size *= 2; /* convert to MB */
3325 : }
3326 : }
3327 : }
3328 :
3329 0 : mem_size *= (1024 * 1024); /* convert to bytes */
3330 0 : WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3331 0 : }
3332 :
3333 0 : void radeon_combios_asic_init(struct drm_device *dev)
3334 : {
3335 0 : struct radeon_device *rdev = dev->dev_private;
3336 : uint16_t table;
3337 :
3338 : /* port hardcoded mac stuff from radeonfb */
3339 0 : if (rdev->bios == NULL)
3340 0 : return;
3341 :
3342 : /* ASIC INIT 1 */
3343 0 : table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3344 0 : if (table)
3345 0 : combios_parse_mmio_table(dev, table);
3346 :
3347 : /* PLL INIT */
3348 0 : table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3349 0 : if (table)
3350 0 : combios_parse_pll_table(dev, table);
3351 :
3352 : /* ASIC INIT 2 */
3353 0 : table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3354 0 : if (table)
3355 0 : combios_parse_mmio_table(dev, table);
3356 :
3357 0 : if (!(rdev->flags & RADEON_IS_IGP)) {
3358 : /* ASIC INIT 4 */
3359 : table =
3360 0 : combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3361 0 : if (table)
3362 0 : combios_parse_mmio_table(dev, table);
3363 :
3364 : /* RAM RESET */
3365 0 : table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3366 0 : if (table)
3367 0 : combios_parse_ram_reset_table(dev, table);
3368 :
3369 : /* ASIC INIT 3 */
3370 : table =
3371 0 : combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3372 0 : if (table)
3373 0 : combios_parse_mmio_table(dev, table);
3374 :
3375 : /* write CONFIG_MEMSIZE */
3376 0 : combios_write_ram_size(dev);
3377 0 : }
3378 :
3379 : /* quirk for rs4xx HP nx6125 laptop to make it resume
3380 : * - it hangs on resume inside the dynclk 1 table.
3381 : */
3382 0 : if (rdev->family == CHIP_RS480 &&
3383 0 : rdev->pdev->subsystem_vendor == 0x103c &&
3384 0 : rdev->pdev->subsystem_device == 0x308b)
3385 0 : return;
3386 :
3387 : /* quirk for rs4xx HP dv5000 laptop to make it resume
3388 : * - it hangs on resume inside the dynclk 1 table.
3389 : */
3390 0 : if (rdev->family == CHIP_RS480 &&
3391 0 : rdev->pdev->subsystem_vendor == 0x103c &&
3392 0 : rdev->pdev->subsystem_device == 0x30a4)
3393 0 : return;
3394 :
3395 : /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3396 : * - it hangs on resume inside the dynclk 1 table.
3397 : */
3398 0 : if (rdev->family == CHIP_RS480 &&
3399 0 : rdev->pdev->subsystem_vendor == 0x103c &&
3400 0 : rdev->pdev->subsystem_device == 0x30ae)
3401 0 : return;
3402 :
3403 : /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume
3404 : * - it hangs on resume inside the dynclk 1 table.
3405 : */
3406 0 : if (rdev->family == CHIP_RS480 &&
3407 0 : rdev->pdev->subsystem_vendor == 0x103c &&
3408 0 : rdev->pdev->subsystem_device == 0x280a)
3409 0 : return;
3410 : /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume
3411 : * - it hangs on resume inside the dynclk 1 table.
3412 : */
3413 0 : if (rdev->family == CHIP_RS400 &&
3414 0 : rdev->pdev->subsystem_vendor == 0x1179 &&
3415 0 : rdev->pdev->subsystem_device == 0xff31)
3416 0 : return;
3417 :
3418 : /* DYN CLK 1 */
3419 0 : table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3420 0 : if (table)
3421 0 : combios_parse_pll_table(dev, table);
3422 :
3423 0 : }
3424 :
3425 0 : void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3426 : {
3427 0 : struct radeon_device *rdev = dev->dev_private;
3428 : uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3429 :
3430 0 : bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3431 0 : bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3432 0 : bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3433 :
3434 : /* let the bios control the backlight */
3435 0 : bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3436 :
3437 : /* tell the bios not to handle mode switching */
3438 0 : bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3439 : RADEON_ACC_MODE_CHANGE);
3440 :
3441 : /* tell the bios a driver is loaded */
3442 0 : bios_7_scratch |= RADEON_DRV_LOADED;
3443 :
3444 0 : WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3445 0 : WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3446 0 : WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3447 0 : }
3448 :
3449 0 : void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3450 : {
3451 0 : struct drm_device *dev = encoder->dev;
3452 0 : struct radeon_device *rdev = dev->dev_private;
3453 : uint32_t bios_6_scratch;
3454 :
3455 0 : bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3456 :
3457 0 : if (lock)
3458 0 : bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3459 : else
3460 0 : bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3461 :
3462 0 : WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3463 0 : }
3464 :
3465 : void
3466 0 : radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3467 : struct drm_encoder *encoder,
3468 : bool connected)
3469 : {
3470 0 : struct drm_device *dev = connector->dev;
3471 0 : struct radeon_device *rdev = dev->dev_private;
3472 : struct radeon_connector *radeon_connector =
3473 0 : to_radeon_connector(connector);
3474 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3475 0 : uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3476 0 : uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3477 :
3478 0 : if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3479 0 : (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3480 0 : if (connected) {
3481 : DRM_DEBUG_KMS("TV1 connected\n");
3482 : /* fix me */
3483 0 : bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3484 : /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3485 0 : bios_5_scratch |= RADEON_TV1_ON;
3486 0 : bios_5_scratch |= RADEON_ACC_REQ_TV1;
3487 0 : } else {
3488 : DRM_DEBUG_KMS("TV1 disconnected\n");
3489 0 : bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3490 0 : bios_5_scratch &= ~RADEON_TV1_ON;
3491 0 : bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3492 : }
3493 : }
3494 0 : if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3495 0 : (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3496 0 : if (connected) {
3497 : DRM_DEBUG_KMS("LCD1 connected\n");
3498 0 : bios_4_scratch |= RADEON_LCD1_ATTACHED;
3499 0 : bios_5_scratch |= RADEON_LCD1_ON;
3500 0 : bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3501 0 : } else {
3502 : DRM_DEBUG_KMS("LCD1 disconnected\n");
3503 0 : bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3504 0 : bios_5_scratch &= ~RADEON_LCD1_ON;
3505 0 : bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3506 : }
3507 : }
3508 0 : if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3509 0 : (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3510 0 : if (connected) {
3511 : DRM_DEBUG_KMS("CRT1 connected\n");
3512 0 : bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3513 0 : bios_5_scratch |= RADEON_CRT1_ON;
3514 0 : bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3515 0 : } else {
3516 : DRM_DEBUG_KMS("CRT1 disconnected\n");
3517 0 : bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3518 0 : bios_5_scratch &= ~RADEON_CRT1_ON;
3519 0 : bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3520 : }
3521 : }
3522 0 : if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3523 0 : (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3524 0 : if (connected) {
3525 : DRM_DEBUG_KMS("CRT2 connected\n");
3526 0 : bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3527 0 : bios_5_scratch |= RADEON_CRT2_ON;
3528 0 : bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3529 0 : } else {
3530 : DRM_DEBUG_KMS("CRT2 disconnected\n");
3531 0 : bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3532 0 : bios_5_scratch &= ~RADEON_CRT2_ON;
3533 0 : bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3534 : }
3535 : }
3536 0 : if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3537 0 : (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3538 0 : if (connected) {
3539 : DRM_DEBUG_KMS("DFP1 connected\n");
3540 0 : bios_4_scratch |= RADEON_DFP1_ATTACHED;
3541 0 : bios_5_scratch |= RADEON_DFP1_ON;
3542 0 : bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3543 0 : } else {
3544 : DRM_DEBUG_KMS("DFP1 disconnected\n");
3545 0 : bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3546 0 : bios_5_scratch &= ~RADEON_DFP1_ON;
3547 0 : bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3548 : }
3549 : }
3550 0 : if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3551 0 : (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3552 0 : if (connected) {
3553 : DRM_DEBUG_KMS("DFP2 connected\n");
3554 0 : bios_4_scratch |= RADEON_DFP2_ATTACHED;
3555 0 : bios_5_scratch |= RADEON_DFP2_ON;
3556 0 : bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3557 0 : } else {
3558 : DRM_DEBUG_KMS("DFP2 disconnected\n");
3559 0 : bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3560 0 : bios_5_scratch &= ~RADEON_DFP2_ON;
3561 0 : bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3562 : }
3563 : }
3564 0 : WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3565 0 : WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3566 0 : }
3567 :
3568 : void
3569 0 : radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3570 : {
3571 0 : struct drm_device *dev = encoder->dev;
3572 0 : struct radeon_device *rdev = dev->dev_private;
3573 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3574 0 : uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3575 :
3576 0 : if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3577 0 : bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3578 0 : bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3579 0 : }
3580 0 : if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3581 0 : bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3582 0 : bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3583 0 : }
3584 0 : if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3585 0 : bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3586 0 : bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3587 0 : }
3588 0 : if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3589 0 : bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3590 0 : bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3591 0 : }
3592 0 : if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3593 0 : bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3594 0 : bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3595 0 : }
3596 0 : if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3597 0 : bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3598 0 : bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3599 0 : }
3600 0 : WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3601 0 : }
3602 :
3603 : void
3604 0 : radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3605 : {
3606 0 : struct drm_device *dev = encoder->dev;
3607 0 : struct radeon_device *rdev = dev->dev_private;
3608 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3609 0 : uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3610 :
3611 0 : if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3612 0 : if (on)
3613 0 : bios_6_scratch |= RADEON_TV_DPMS_ON;
3614 : else
3615 0 : bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3616 : }
3617 0 : if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3618 0 : if (on)
3619 0 : bios_6_scratch |= RADEON_CRT_DPMS_ON;
3620 : else
3621 0 : bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3622 : }
3623 0 : if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3624 0 : if (on)
3625 0 : bios_6_scratch |= RADEON_LCD_DPMS_ON;
3626 : else
3627 0 : bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3628 : }
3629 0 : if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3630 0 : if (on)
3631 0 : bios_6_scratch |= RADEON_DFP_DPMS_ON;
3632 : else
3633 0 : bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3634 : }
3635 0 : WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3636 0 : }
|
