Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #include <dev/pci/drm/drmP.h>
29 : #include <dev/pci/drm/drm_crtc_helper.h>
30 : #include <dev/pci/drm/radeon_drm.h>
31 : #include "radeon_reg.h"
32 : #include "radeon.h"
33 : #include "atom.h"
34 :
35 : static const char radeon_family_name[][16] = {
36 : "R100",
37 : "RV100",
38 : "RS100",
39 : "RV200",
40 : "RS200",
41 : "R200",
42 : "RV250",
43 : "RS300",
44 : "RV280",
45 : "R300",
46 : "R350",
47 : "RV350",
48 : "RV380",
49 : "R420",
50 : "R423",
51 : "RV410",
52 : "RS400",
53 : "RS480",
54 : "RS600",
55 : "RS690",
56 : "RS740",
57 : "RV515",
58 : "R520",
59 : "RV530",
60 : "RV560",
61 : "RV570",
62 : "R580",
63 : "R600",
64 : "RV610",
65 : "RV630",
66 : "RV670",
67 : "RV620",
68 : "RV635",
69 : "RS780",
70 : "RS880",
71 : "RV770",
72 : "RV730",
73 : "RV710",
74 : "RV740",
75 : "CEDAR",
76 : "REDWOOD",
77 : "JUNIPER",
78 : "CYPRESS",
79 : "HEMLOCK",
80 : "PALM",
81 : "SUMO",
82 : "SUMO2",
83 : "BARTS",
84 : "TURKS",
85 : "CAICOS",
86 : "CAYMAN",
87 : "ARUBA",
88 : "TAHITI",
89 : "PITCAIRN",
90 : "VERDE",
91 : "OLAND",
92 : "HAINAN",
93 : "BONAIRE",
94 : "KAVERI",
95 : "KABINI",
96 : "HAWAII",
97 : "MULLINS",
98 : "LAST",
99 : };
100 :
101 : #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
102 : #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
103 :
104 : struct radeon_px_quirk {
105 : u32 chip_vendor;
106 : u32 chip_device;
107 : u32 subsys_vendor;
108 : u32 subsys_device;
109 : u32 px_quirk_flags;
110 : };
111 :
112 : static struct radeon_px_quirk radeon_px_quirk_list[] = {
113 : /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
114 : * https://bugzilla.kernel.org/show_bug.cgi?id=74551
115 : */
116 : { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
117 : /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
118 : * https://bugzilla.kernel.org/show_bug.cgi?id=51381
119 : */
120 : { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
121 : /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
122 : * https://bugzilla.kernel.org/show_bug.cgi?id=51381
123 : */
124 : { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
125 : /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
126 : * https://bugs.freedesktop.org/show_bug.cgi?id=101491
127 : */
128 : { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
129 : /* macbook pro 8.2 */
130 : { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
131 : { 0, 0, 0, 0, 0 },
132 : };
133 :
134 0 : bool radeon_is_px(struct drm_device *dev)
135 : {
136 0 : struct radeon_device *rdev = dev->dev_private;
137 :
138 0 : if (rdev->flags & RADEON_IS_PX)
139 0 : return true;
140 0 : return false;
141 0 : }
142 :
143 0 : static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
144 : {
145 : struct radeon_px_quirk *p = radeon_px_quirk_list;
146 :
147 : /* Apply PX quirks */
148 0 : while (p && p->chip_device != 0) {
149 0 : if (rdev->pdev->vendor == p->chip_vendor &&
150 0 : rdev->pdev->device == p->chip_device &&
151 0 : rdev->pdev->subsystem_vendor == p->subsys_vendor &&
152 0 : rdev->pdev->subsystem_device == p->subsys_device) {
153 0 : rdev->px_quirk_flags = p->px_quirk_flags;
154 0 : break;
155 : }
156 0 : ++p;
157 : }
158 :
159 0 : if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
160 0 : rdev->flags &= ~RADEON_IS_PX;
161 0 : }
162 :
163 : /**
164 : * radeon_program_register_sequence - program an array of registers.
165 : *
166 : * @rdev: radeon_device pointer
167 : * @registers: pointer to the register array
168 : * @array_size: size of the register array
169 : *
170 : * Programs an array or registers with and and or masks.
171 : * This is a helper for setting golden registers.
172 : */
173 0 : void radeon_program_register_sequence(struct radeon_device *rdev,
174 : const u32 *registers,
175 : const u32 array_size)
176 : {
177 : u32 tmp, reg, and_mask, or_mask;
178 : int i;
179 :
180 0 : if (array_size % 3)
181 0 : return;
182 :
183 0 : for (i = 0; i < array_size; i +=3) {
184 0 : reg = registers[i + 0];
185 0 : and_mask = registers[i + 1];
186 0 : or_mask = registers[i + 2];
187 :
188 0 : if (and_mask == 0xffffffff) {
189 : tmp = or_mask;
190 0 : } else {
191 0 : tmp = RREG32(reg);
192 0 : tmp &= ~and_mask;
193 0 : tmp |= or_mask;
194 : }
195 0 : WREG32(reg, tmp);
196 : }
197 0 : }
198 :
199 0 : void radeon_pci_config_reset(struct radeon_device *rdev)
200 : {
201 0 : pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
202 0 : }
203 :
204 : /**
205 : * radeon_surface_init - Clear GPU surface registers.
206 : *
207 : * @rdev: radeon_device pointer
208 : *
209 : * Clear GPU surface registers (r1xx-r5xx).
210 : */
211 0 : void radeon_surface_init(struct radeon_device *rdev)
212 : {
213 : /* FIXME: check this out */
214 0 : if (rdev->family < CHIP_R600) {
215 : int i;
216 :
217 0 : for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
218 0 : if (rdev->surface_regs[i].bo)
219 0 : radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
220 : else
221 0 : radeon_clear_surface_reg(rdev, i);
222 : }
223 : /* enable surfaces */
224 0 : WREG32(RADEON_SURFACE_CNTL, 0);
225 0 : }
226 0 : }
227 :
228 : /*
229 : * GPU scratch registers helpers function.
230 : */
231 : /**
232 : * radeon_scratch_init - Init scratch register driver information.
233 : *
234 : * @rdev: radeon_device pointer
235 : *
236 : * Init CP scratch register driver information (r1xx-r5xx)
237 : */
238 0 : void radeon_scratch_init(struct radeon_device *rdev)
239 : {
240 : int i;
241 :
242 : /* FIXME: check this out */
243 0 : if (rdev->family < CHIP_R300) {
244 0 : rdev->scratch.num_reg = 5;
245 0 : } else {
246 0 : rdev->scratch.num_reg = 7;
247 : }
248 0 : rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
249 0 : for (i = 0; i < rdev->scratch.num_reg; i++) {
250 0 : rdev->scratch.free[i] = true;
251 0 : rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
252 : }
253 0 : }
254 :
255 : /**
256 : * radeon_scratch_get - Allocate a scratch register
257 : *
258 : * @rdev: radeon_device pointer
259 : * @reg: scratch register mmio offset
260 : *
261 : * Allocate a CP scratch register for use by the driver (all asics).
262 : * Returns 0 on success or -EINVAL on failure.
263 : */
264 0 : int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
265 : {
266 : int i;
267 :
268 0 : for (i = 0; i < rdev->scratch.num_reg; i++) {
269 0 : if (rdev->scratch.free[i]) {
270 0 : rdev->scratch.free[i] = false;
271 0 : *reg = rdev->scratch.reg[i];
272 0 : return 0;
273 : }
274 : }
275 0 : return -EINVAL;
276 0 : }
277 :
278 : /**
279 : * radeon_scratch_free - Free a scratch register
280 : *
281 : * @rdev: radeon_device pointer
282 : * @reg: scratch register mmio offset
283 : *
284 : * Free a CP scratch register allocated for use by the driver (all asics)
285 : */
286 0 : void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
287 : {
288 : int i;
289 :
290 0 : for (i = 0; i < rdev->scratch.num_reg; i++) {
291 0 : if (rdev->scratch.reg[i] == reg) {
292 0 : rdev->scratch.free[i] = true;
293 0 : return;
294 : }
295 : }
296 0 : }
297 :
298 : /*
299 : * GPU doorbell aperture helpers function.
300 : */
301 : /**
302 : * radeon_doorbell_init - Init doorbell driver information.
303 : *
304 : * @rdev: radeon_device pointer
305 : *
306 : * Init doorbell driver information (CIK)
307 : * Returns 0 on success, error on failure.
308 : */
309 0 : static int radeon_doorbell_init(struct radeon_device *rdev)
310 : {
311 : /* doorbell bar mapping */
312 : #ifdef __linux__
313 : rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
314 : rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
315 : #endif
316 :
317 0 : rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
318 0 : if (rdev->doorbell.num_doorbells == 0)
319 0 : return -EINVAL;
320 :
321 : #ifdef __linux__
322 : rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
323 : if (rdev->doorbell.ptr == NULL) {
324 : return -ENOMEM;
325 : }
326 : #endif
327 : DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
328 : DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
329 :
330 0 : memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
331 :
332 0 : return 0;
333 0 : }
334 :
335 : /**
336 : * radeon_doorbell_fini - Tear down doorbell driver information.
337 : *
338 : * @rdev: radeon_device pointer
339 : *
340 : * Tear down doorbell driver information (CIK)
341 : */
342 0 : static void radeon_doorbell_fini(struct radeon_device *rdev)
343 : {
344 : #ifdef __linux__
345 : iounmap(rdev->doorbell.ptr);
346 : rdev->doorbell.ptr = NULL;
347 : #else
348 0 : if (rdev->doorbell.size > 0)
349 0 : bus_space_unmap(rdev->memt, rdev->doorbell.bsh,
350 : rdev->doorbell.size);
351 0 : rdev->doorbell.size = 0;
352 : #endif
353 0 : }
354 :
355 : /**
356 : * radeon_doorbell_get - Allocate a doorbell entry
357 : *
358 : * @rdev: radeon_device pointer
359 : * @doorbell: doorbell index
360 : *
361 : * Allocate a doorbell for use by the driver (all asics).
362 : * Returns 0 on success or -EINVAL on failure.
363 : */
364 0 : int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
365 : {
366 0 : unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
367 0 : if (offset < rdev->doorbell.num_doorbells) {
368 0 : __set_bit(offset, rdev->doorbell.used);
369 0 : *doorbell = offset;
370 0 : return 0;
371 : } else {
372 0 : return -EINVAL;
373 : }
374 0 : }
375 :
376 : /**
377 : * radeon_doorbell_free - Free a doorbell entry
378 : *
379 : * @rdev: radeon_device pointer
380 : * @doorbell: doorbell index
381 : *
382 : * Free a doorbell allocated for use by the driver (all asics)
383 : */
384 0 : void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
385 : {
386 0 : if (doorbell < rdev->doorbell.num_doorbells)
387 0 : __clear_bit(doorbell, rdev->doorbell.used);
388 0 : }
389 :
390 : /**
391 : * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
392 : * setup KFD
393 : *
394 : * @rdev: radeon_device pointer
395 : * @aperture_base: output returning doorbell aperture base physical address
396 : * @aperture_size: output returning doorbell aperture size in bytes
397 : * @start_offset: output returning # of doorbell bytes reserved for radeon.
398 : *
399 : * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
400 : * takes doorbells required for its own rings and reports the setup to KFD.
401 : * Radeon reserved doorbells are at the start of the doorbell aperture.
402 : */
403 0 : void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
404 : phys_addr_t *aperture_base,
405 : size_t *aperture_size,
406 : size_t *start_offset)
407 : {
408 : /* The first num_doorbells are used by radeon.
409 : * KFD takes whatever's left in the aperture. */
410 0 : if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) {
411 0 : *aperture_base = rdev->doorbell.base;
412 0 : *aperture_size = rdev->doorbell.size;
413 0 : *start_offset = rdev->doorbell.num_doorbells * sizeof(u32);
414 0 : } else {
415 0 : *aperture_base = 0;
416 0 : *aperture_size = 0;
417 0 : *start_offset = 0;
418 : }
419 0 : }
420 :
421 : /*
422 : * radeon_wb_*()
423 : * Writeback is the the method by which the the GPU updates special pages
424 : * in memory with the status of certain GPU events (fences, ring pointers,
425 : * etc.).
426 : */
427 :
428 : /**
429 : * radeon_wb_disable - Disable Writeback
430 : *
431 : * @rdev: radeon_device pointer
432 : *
433 : * Disables Writeback (all asics). Used for suspend.
434 : */
435 0 : void radeon_wb_disable(struct radeon_device *rdev)
436 : {
437 0 : rdev->wb.enabled = false;
438 0 : }
439 :
440 : /**
441 : * radeon_wb_fini - Disable Writeback and free memory
442 : *
443 : * @rdev: radeon_device pointer
444 : *
445 : * Disables Writeback and frees the Writeback memory (all asics).
446 : * Used at driver shutdown.
447 : */
448 0 : void radeon_wb_fini(struct radeon_device *rdev)
449 : {
450 0 : radeon_wb_disable(rdev);
451 0 : if (rdev->wb.wb_obj) {
452 0 : if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
453 0 : radeon_bo_kunmap(rdev->wb.wb_obj);
454 0 : radeon_bo_unpin(rdev->wb.wb_obj);
455 0 : radeon_bo_unreserve(rdev->wb.wb_obj);
456 0 : }
457 0 : radeon_bo_unref(&rdev->wb.wb_obj);
458 0 : rdev->wb.wb = NULL;
459 0 : rdev->wb.wb_obj = NULL;
460 0 : }
461 0 : }
462 :
463 : /**
464 : * radeon_wb_init- Init Writeback driver info and allocate memory
465 : *
466 : * @rdev: radeon_device pointer
467 : *
468 : * Disables Writeback and frees the Writeback memory (all asics).
469 : * Used at driver startup.
470 : * Returns 0 on success or an -error on failure.
471 : */
472 0 : int radeon_wb_init(struct radeon_device *rdev)
473 : {
474 : int r;
475 :
476 0 : if (rdev->wb.wb_obj == NULL) {
477 0 : r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
478 : RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
479 : &rdev->wb.wb_obj);
480 0 : if (r) {
481 0 : dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
482 0 : return r;
483 : }
484 0 : r = radeon_bo_reserve(rdev->wb.wb_obj, false);
485 0 : if (unlikely(r != 0)) {
486 0 : radeon_wb_fini(rdev);
487 0 : return r;
488 : }
489 0 : r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
490 0 : &rdev->wb.gpu_addr);
491 0 : if (r) {
492 0 : radeon_bo_unreserve(rdev->wb.wb_obj);
493 0 : dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
494 0 : radeon_wb_fini(rdev);
495 0 : return r;
496 : }
497 0 : r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
498 0 : radeon_bo_unreserve(rdev->wb.wb_obj);
499 0 : if (r) {
500 0 : dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
501 0 : radeon_wb_fini(rdev);
502 0 : return r;
503 : }
504 : }
505 :
506 : /* clear wb memory */
507 0 : memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
508 : /* disable event_write fences */
509 0 : rdev->wb.use_event = false;
510 : /* disabled via module param */
511 0 : if (radeon_no_wb == 1) {
512 0 : rdev->wb.enabled = false;
513 0 : } else {
514 0 : if (rdev->flags & RADEON_IS_AGP) {
515 : /* often unreliable on AGP */
516 0 : rdev->wb.enabled = false;
517 0 : } else if (rdev->family < CHIP_R300) {
518 : /* often unreliable on pre-r300 */
519 0 : rdev->wb.enabled = false;
520 0 : } else {
521 0 : rdev->wb.enabled = true;
522 : /* event_write fences are only available on r600+ */
523 0 : if (rdev->family >= CHIP_R600) {
524 0 : rdev->wb.use_event = true;
525 0 : }
526 : }
527 : }
528 : /* always use writeback/events on NI, APUs */
529 0 : if (rdev->family >= CHIP_PALM) {
530 0 : rdev->wb.enabled = true;
531 0 : rdev->wb.use_event = true;
532 0 : }
533 :
534 : dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
535 :
536 0 : return 0;
537 0 : }
538 :
539 : /**
540 : * radeon_vram_location - try to find VRAM location
541 : * @rdev: radeon device structure holding all necessary informations
542 : * @mc: memory controller structure holding memory informations
543 : * @base: base address at which to put VRAM
544 : *
545 : * Function will place try to place VRAM at base address provided
546 : * as parameter (which is so far either PCI aperture address or
547 : * for IGP TOM base address).
548 : *
549 : * If there is not enough space to fit the unvisible VRAM in the 32bits
550 : * address space then we limit the VRAM size to the aperture.
551 : *
552 : * If we are using AGP and if the AGP aperture doesn't allow us to have
553 : * room for all the VRAM than we restrict the VRAM to the PCI aperture
554 : * size and print a warning.
555 : *
556 : * This function will never fails, worst case are limiting VRAM.
557 : *
558 : * Note: GTT start, end, size should be initialized before calling this
559 : * function on AGP platform.
560 : *
561 : * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
562 : * this shouldn't be a problem as we are using the PCI aperture as a reference.
563 : * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
564 : * not IGP.
565 : *
566 : * Note: we use mc_vram_size as on some board we need to program the mc to
567 : * cover the whole aperture even if VRAM size is inferior to aperture size
568 : * Novell bug 204882 + along with lots of ubuntu ones
569 : *
570 : * Note: when limiting vram it's safe to overwritte real_vram_size because
571 : * we are not in case where real_vram_size is inferior to mc_vram_size (ie
572 : * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
573 : * ones)
574 : *
575 : * Note: IGP TOM addr should be the same as the aperture addr, we don't
576 : * explicitly check for that thought.
577 : *
578 : * FIXME: when reducing VRAM size align new size on power of 2.
579 : */
580 0 : void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
581 : {
582 0 : uint64_t limit = (uint64_t)radeon_vram_limit << 20;
583 :
584 0 : mc->vram_start = base;
585 0 : if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
586 0 : dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
587 0 : mc->real_vram_size = mc->aper_size;
588 0 : mc->mc_vram_size = mc->aper_size;
589 0 : }
590 0 : mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
591 0 : if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
592 0 : dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
593 0 : mc->real_vram_size = mc->aper_size;
594 0 : mc->mc_vram_size = mc->aper_size;
595 0 : }
596 0 : mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
597 0 : if (limit && limit < mc->real_vram_size)
598 0 : mc->real_vram_size = limit;
599 : dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
600 : mc->mc_vram_size >> 20, mc->vram_start,
601 : mc->vram_end, mc->real_vram_size >> 20);
602 0 : }
603 :
604 : /**
605 : * radeon_gtt_location - try to find GTT location
606 : * @rdev: radeon device structure holding all necessary informations
607 : * @mc: memory controller structure holding memory informations
608 : *
609 : * Function will place try to place GTT before or after VRAM.
610 : *
611 : * If GTT size is bigger than space left then we ajust GTT size.
612 : * Thus function will never fails.
613 : *
614 : * FIXME: when reducing GTT size align new size on power of 2.
615 : */
616 0 : void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
617 : {
618 : u64 size_af, size_bf;
619 :
620 0 : size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
621 0 : size_bf = mc->vram_start & ~mc->gtt_base_align;
622 0 : if (size_bf > size_af) {
623 0 : if (mc->gtt_size > size_bf) {
624 0 : dev_warn(rdev->dev, "limiting GTT\n");
625 0 : mc->gtt_size = size_bf;
626 0 : }
627 0 : mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
628 0 : } else {
629 0 : if (mc->gtt_size > size_af) {
630 0 : dev_warn(rdev->dev, "limiting GTT\n");
631 0 : mc->gtt_size = size_af;
632 0 : }
633 0 : mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
634 : }
635 0 : mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
636 : dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
637 : mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
638 0 : }
639 :
640 : /*
641 : * GPU helpers function.
642 : */
643 :
644 : /**
645 : * radeon_device_is_virtual - check if we are running is a virtual environment
646 : *
647 : * Check if the asic has been passed through to a VM (all asics).
648 : * Used at driver startup.
649 : * Returns true if virtual or false if not.
650 : */
651 0 : static bool radeon_device_is_virtual(void)
652 : {
653 : #if defined(__amd64__) || defined(__i386__)
654 0 : return (cpu_ecxfeature & CPUIDECX_HV);
655 : #else
656 : return false;
657 : #endif
658 : }
659 :
660 : /**
661 : * radeon_card_posted - check if the hw has already been initialized
662 : *
663 : * @rdev: radeon_device pointer
664 : *
665 : * Check if the asic has been initialized (all asics).
666 : * Used at driver startup.
667 : * Returns true if initialized or false if not.
668 : */
669 0 : bool radeon_card_posted(struct radeon_device *rdev)
670 : {
671 : uint32_t reg;
672 :
673 : /* for pass through, always force asic_init for CI */
674 0 : if (rdev->family >= CHIP_BONAIRE &&
675 0 : radeon_device_is_virtual())
676 0 : return false;
677 :
678 : /* required for EFI mode on macbook2,1 which uses an r5xx asic */
679 : #ifdef notyet
680 : if (efi_enabled(EFI_BOOT) &&
681 : (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
682 : (rdev->family < CHIP_R600))
683 : return false;
684 : #endif
685 :
686 0 : if (ASIC_IS_NODCE(rdev))
687 : goto check_memsize;
688 :
689 : /* first check CRTCs */
690 0 : if (ASIC_IS_DCE4(rdev)) {
691 0 : reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
692 0 : RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
693 0 : if (rdev->num_crtc >= 4) {
694 0 : reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
695 0 : RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
696 0 : }
697 0 : if (rdev->num_crtc >= 6) {
698 0 : reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
699 0 : RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
700 0 : }
701 0 : if (reg & EVERGREEN_CRTC_MASTER_EN)
702 0 : return true;
703 0 : } else if (ASIC_IS_AVIVO(rdev)) {
704 0 : reg = RREG32(AVIVO_D1CRTC_CONTROL) |
705 0 : RREG32(AVIVO_D2CRTC_CONTROL);
706 0 : if (reg & AVIVO_CRTC_EN) {
707 0 : return true;
708 : }
709 : } else {
710 0 : reg = RREG32(RADEON_CRTC_GEN_CNTL) |
711 0 : RREG32(RADEON_CRTC2_GEN_CNTL);
712 0 : if (reg & RADEON_CRTC_EN) {
713 0 : return true;
714 : }
715 : }
716 :
717 : check_memsize:
718 : /* then check MEM_SIZE, in case the crtcs are off */
719 0 : if (rdev->family >= CHIP_R600)
720 0 : reg = RREG32(R600_CONFIG_MEMSIZE);
721 : else
722 0 : reg = RREG32(RADEON_CONFIG_MEMSIZE);
723 :
724 0 : if (reg)
725 0 : return true;
726 :
727 0 : return false;
728 :
729 0 : }
730 :
731 : /**
732 : * radeon_update_bandwidth_info - update display bandwidth params
733 : *
734 : * @rdev: radeon_device pointer
735 : *
736 : * Used when sclk/mclk are switched or display modes are set.
737 : * params are used to calculate display watermarks (all asics)
738 : */
739 0 : void radeon_update_bandwidth_info(struct radeon_device *rdev)
740 : {
741 : fixed20_12 a;
742 0 : u32 sclk = rdev->pm.current_sclk;
743 0 : u32 mclk = rdev->pm.current_mclk;
744 :
745 : /* sclk/mclk in Mhz */
746 : a.full = dfixed_const(100);
747 0 : rdev->pm.sclk.full = dfixed_const(sclk);
748 0 : rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
749 0 : rdev->pm.mclk.full = dfixed_const(mclk);
750 0 : rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
751 :
752 0 : if (rdev->flags & RADEON_IS_IGP) {
753 : a.full = dfixed_const(16);
754 : /* core_bandwidth = sclk(Mhz) * 16 */
755 0 : rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
756 0 : }
757 0 : }
758 :
759 : /**
760 : * radeon_boot_test_post_card - check and possibly initialize the hw
761 : *
762 : * @rdev: radeon_device pointer
763 : *
764 : * Check if the asic is initialized and if not, attempt to initialize
765 : * it (all asics).
766 : * Returns true if initialized or false if not.
767 : */
768 0 : bool radeon_boot_test_post_card(struct radeon_device *rdev)
769 : {
770 0 : if (radeon_card_posted(rdev))
771 0 : return true;
772 :
773 0 : if (rdev->bios) {
774 : DRM_INFO("GPU not posted. posting now...\n");
775 0 : if (rdev->is_atom_bios)
776 0 : atom_asic_init(rdev->mode_info.atom_context);
777 : else
778 0 : radeon_combios_asic_init(rdev->ddev);
779 0 : return true;
780 : } else {
781 0 : dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
782 0 : return false;
783 : }
784 0 : }
785 :
786 : /**
787 : * radeon_dummy_page_init - init dummy page used by the driver
788 : *
789 : * @rdev: radeon_device pointer
790 : *
791 : * Allocate the dummy page used by the driver (all asics).
792 : * This dummy page is used by the driver as a filler for gart entries
793 : * when pages are taken out of the GART
794 : * Returns 0 on sucess, -ENOMEM on failure.
795 : */
796 0 : int radeon_dummy_page_init(struct radeon_device *rdev)
797 : {
798 0 : if (rdev->dummy_page.dmah)
799 0 : return 0;
800 0 : rdev->dummy_page.dmah = drm_dmamem_alloc(rdev->dmat, PAGE_SIZE, PAGE_SIZE, 1,
801 : PAGE_SIZE, 0, BUS_DMA_WAITOK);
802 0 : if (!rdev->dummy_page.dmah)
803 0 : return -ENOMEM;
804 0 : rdev->dummy_page.addr = (bus_addr_t)rdev->dummy_page.dmah->map->dm_segs[0].ds_addr;
805 0 : rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
806 : RADEON_GART_PAGE_DUMMY);
807 0 : return 0;
808 0 : }
809 :
810 : /**
811 : * radeon_dummy_page_fini - free dummy page used by the driver
812 : *
813 : * @rdev: radeon_device pointer
814 : *
815 : * Frees the dummy page used by the driver (all asics).
816 : */
817 0 : void radeon_dummy_page_fini(struct radeon_device *rdev)
818 : {
819 0 : if (rdev->dummy_page.dmah == NULL)
820 : return;
821 :
822 0 : drm_dmamem_free(rdev->dmat, rdev->dummy_page.dmah);
823 0 : rdev->dummy_page.dmah = NULL;
824 0 : rdev->dummy_page.addr = 0;
825 0 : }
826 :
827 :
828 : /* ATOM accessor methods */
829 : /*
830 : * ATOM is an interpreted byte code stored in tables in the vbios. The
831 : * driver registers callbacks to access registers and the interpreter
832 : * in the driver parses the tables and executes then to program specific
833 : * actions (set display modes, asic init, etc.). See radeon_atombios.c,
834 : * atombios.h, and atom.c
835 : */
836 :
837 : /**
838 : * cail_pll_read - read PLL register
839 : *
840 : * @info: atom card_info pointer
841 : * @reg: PLL register offset
842 : *
843 : * Provides a PLL register accessor for the atom interpreter (r4xx+).
844 : * Returns the value of the PLL register.
845 : */
846 0 : static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
847 : {
848 0 : struct radeon_device *rdev = info->dev->dev_private;
849 : uint32_t r;
850 :
851 0 : r = rdev->pll_rreg(rdev, reg);
852 0 : return r;
853 : }
854 :
855 : /**
856 : * cail_pll_write - write PLL register
857 : *
858 : * @info: atom card_info pointer
859 : * @reg: PLL register offset
860 : * @val: value to write to the pll register
861 : *
862 : * Provides a PLL register accessor for the atom interpreter (r4xx+).
863 : */
864 0 : static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
865 : {
866 0 : struct radeon_device *rdev = info->dev->dev_private;
867 :
868 0 : rdev->pll_wreg(rdev, reg, val);
869 0 : }
870 :
871 : /**
872 : * cail_mc_read - read MC (Memory Controller) register
873 : *
874 : * @info: atom card_info pointer
875 : * @reg: MC register offset
876 : *
877 : * Provides an MC register accessor for the atom interpreter (r4xx+).
878 : * Returns the value of the MC register.
879 : */
880 0 : static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
881 : {
882 0 : struct radeon_device *rdev = info->dev->dev_private;
883 : uint32_t r;
884 :
885 0 : r = rdev->mc_rreg(rdev, reg);
886 0 : return r;
887 : }
888 :
889 : /**
890 : * cail_mc_write - write MC (Memory Controller) register
891 : *
892 : * @info: atom card_info pointer
893 : * @reg: MC register offset
894 : * @val: value to write to the pll register
895 : *
896 : * Provides a MC register accessor for the atom interpreter (r4xx+).
897 : */
898 0 : static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
899 : {
900 0 : struct radeon_device *rdev = info->dev->dev_private;
901 :
902 0 : rdev->mc_wreg(rdev, reg, val);
903 0 : }
904 :
905 : /**
906 : * cail_reg_write - write MMIO register
907 : *
908 : * @info: atom card_info pointer
909 : * @reg: MMIO register offset
910 : * @val: value to write to the pll register
911 : *
912 : * Provides a MMIO register accessor for the atom interpreter (r4xx+).
913 : */
914 0 : static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
915 : {
916 0 : struct radeon_device *rdev = info->dev->dev_private;
917 :
918 0 : WREG32(reg*4, val);
919 0 : }
920 :
921 : /**
922 : * cail_reg_read - read MMIO register
923 : *
924 : * @info: atom card_info pointer
925 : * @reg: MMIO register offset
926 : *
927 : * Provides an MMIO register accessor for the atom interpreter (r4xx+).
928 : * Returns the value of the MMIO register.
929 : */
930 0 : static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
931 : {
932 0 : struct radeon_device *rdev = info->dev->dev_private;
933 : uint32_t r;
934 :
935 0 : r = RREG32(reg*4);
936 0 : return r;
937 : }
938 :
939 : /**
940 : * cail_ioreg_write - write IO register
941 : *
942 : * @info: atom card_info pointer
943 : * @reg: IO register offset
944 : * @val: value to write to the pll register
945 : *
946 : * Provides a IO register accessor for the atom interpreter (r4xx+).
947 : */
948 0 : static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
949 : {
950 0 : struct radeon_device *rdev = info->dev->dev_private;
951 :
952 0 : WREG32_IO(reg*4, val);
953 0 : }
954 :
955 : /**
956 : * cail_ioreg_read - read IO register
957 : *
958 : * @info: atom card_info pointer
959 : * @reg: IO register offset
960 : *
961 : * Provides an IO register accessor for the atom interpreter (r4xx+).
962 : * Returns the value of the IO register.
963 : */
964 0 : static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
965 : {
966 0 : struct radeon_device *rdev = info->dev->dev_private;
967 : uint32_t r;
968 :
969 0 : r = RREG32_IO(reg*4);
970 0 : return r;
971 : }
972 :
973 : /**
974 : * radeon_atombios_init - init the driver info and callbacks for atombios
975 : *
976 : * @rdev: radeon_device pointer
977 : *
978 : * Initializes the driver info and register access callbacks for the
979 : * ATOM interpreter (r4xx+).
980 : * Returns 0 on sucess, -ENOMEM on failure.
981 : * Called at driver startup.
982 : */
983 0 : int radeon_atombios_init(struct radeon_device *rdev)
984 : {
985 : struct card_info *atom_card_info =
986 0 : kzalloc(sizeof(struct card_info), GFP_KERNEL);
987 :
988 0 : if (!atom_card_info)
989 0 : return -ENOMEM;
990 :
991 0 : rdev->mode_info.atom_card_info = atom_card_info;
992 0 : atom_card_info->dev = rdev->ddev;
993 0 : atom_card_info->reg_read = cail_reg_read;
994 0 : atom_card_info->reg_write = cail_reg_write;
995 : /* needed for iio ops */
996 0 : if (rdev->rio_mem_size > 0) {
997 0 : atom_card_info->ioreg_read = cail_ioreg_read;
998 0 : atom_card_info->ioreg_write = cail_ioreg_write;
999 0 : } else {
1000 0 : DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
1001 0 : atom_card_info->ioreg_read = cail_reg_read;
1002 0 : atom_card_info->ioreg_write = cail_reg_write;
1003 : }
1004 0 : atom_card_info->mc_read = cail_mc_read;
1005 0 : atom_card_info->mc_write = cail_mc_write;
1006 0 : atom_card_info->pll_read = cail_pll_read;
1007 0 : atom_card_info->pll_write = cail_pll_write;
1008 :
1009 0 : rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
1010 0 : if (!rdev->mode_info.atom_context) {
1011 0 : radeon_atombios_fini(rdev);
1012 0 : return -ENOMEM;
1013 : }
1014 :
1015 0 : rw_init(&rdev->mode_info.atom_context->mutex, "atomcon");
1016 0 : rw_init(&rdev->mode_info.atom_context->scratch_mutex, "atomscr");
1017 0 : radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1018 0 : atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1019 0 : return 0;
1020 0 : }
1021 :
1022 : /**
1023 : * radeon_atombios_fini - free the driver info and callbacks for atombios
1024 : *
1025 : * @rdev: radeon_device pointer
1026 : *
1027 : * Frees the driver info and register access callbacks for the ATOM
1028 : * interpreter (r4xx+).
1029 : * Called at driver shutdown.
1030 : */
1031 0 : void radeon_atombios_fini(struct radeon_device *rdev)
1032 : {
1033 0 : if (rdev->mode_info.atom_context) {
1034 0 : kfree(rdev->mode_info.atom_context->scratch);
1035 0 : }
1036 0 : kfree(rdev->mode_info.atom_context);
1037 0 : rdev->mode_info.atom_context = NULL;
1038 0 : kfree(rdev->mode_info.atom_card_info);
1039 0 : rdev->mode_info.atom_card_info = NULL;
1040 0 : }
1041 :
1042 : /* COMBIOS */
1043 : /*
1044 : * COMBIOS is the bios format prior to ATOM. It provides
1045 : * command tables similar to ATOM, but doesn't have a unified
1046 : * parser. See radeon_combios.c
1047 : */
1048 :
1049 : /**
1050 : * radeon_combios_init - init the driver info for combios
1051 : *
1052 : * @rdev: radeon_device pointer
1053 : *
1054 : * Initializes the driver info for combios (r1xx-r3xx).
1055 : * Returns 0 on sucess.
1056 : * Called at driver startup.
1057 : */
1058 0 : int radeon_combios_init(struct radeon_device *rdev)
1059 : {
1060 0 : radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1061 0 : return 0;
1062 : }
1063 :
1064 : /**
1065 : * radeon_combios_fini - free the driver info for combios
1066 : *
1067 : * @rdev: radeon_device pointer
1068 : *
1069 : * Frees the driver info for combios (r1xx-r3xx).
1070 : * Called at driver shutdown.
1071 : */
1072 0 : void radeon_combios_fini(struct radeon_device *rdev)
1073 : {
1074 0 : }
1075 :
1076 : /* if we get transitioned to only one device, take VGA back */
1077 : /**
1078 : * radeon_vga_set_decode - enable/disable vga decode
1079 : *
1080 : * @cookie: radeon_device pointer
1081 : * @state: enable/disable vga decode
1082 : *
1083 : * Enable/disable vga decode (all asics).
1084 : * Returns VGA resource flags.
1085 : */
1086 : #ifdef notyet
1087 : static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1088 : {
1089 : struct radeon_device *rdev = cookie;
1090 : radeon_vga_set_state(rdev, state);
1091 : if (state)
1092 : return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1093 : VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1094 : else
1095 : return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1096 : }
1097 : #endif
1098 :
1099 : /**
1100 : * radeon_check_pot_argument - check that argument is a power of two
1101 : *
1102 : * @arg: value to check
1103 : *
1104 : * Validates that a certain argument is a power of two (all asics).
1105 : * Returns true if argument is valid.
1106 : */
1107 0 : static bool radeon_check_pot_argument(int arg)
1108 : {
1109 0 : return (arg & (arg - 1)) == 0;
1110 : }
1111 :
1112 : /**
1113 : * Determine a sensible default GART size according to ASIC family.
1114 : *
1115 : * @family ASIC family name
1116 : */
1117 0 : static int radeon_gart_size_auto(enum radeon_family family)
1118 : {
1119 : /* default to a larger gart size on newer asics */
1120 0 : if (family >= CHIP_TAHITI)
1121 0 : return 2048;
1122 0 : else if (family >= CHIP_RV770)
1123 0 : return 1024;
1124 : else
1125 0 : return 512;
1126 0 : }
1127 :
1128 : /**
1129 : * radeon_check_arguments - validate module params
1130 : *
1131 : * @rdev: radeon_device pointer
1132 : *
1133 : * Validates certain module parameters and updates
1134 : * the associated values used by the driver (all asics).
1135 : */
1136 0 : static void radeon_check_arguments(struct radeon_device *rdev)
1137 : {
1138 : /* vramlimit must be a power of two */
1139 0 : if (!radeon_check_pot_argument(radeon_vram_limit)) {
1140 0 : dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1141 : radeon_vram_limit);
1142 0 : radeon_vram_limit = 0;
1143 0 : }
1144 :
1145 0 : if (radeon_gart_size == -1) {
1146 0 : radeon_gart_size = radeon_gart_size_auto(rdev->family);
1147 0 : }
1148 : /* gtt size must be power of two and greater or equal to 32M */
1149 0 : if (radeon_gart_size < 32) {
1150 0 : dev_warn(rdev->dev, "gart size (%d) too small\n",
1151 : radeon_gart_size);
1152 0 : radeon_gart_size = radeon_gart_size_auto(rdev->family);
1153 0 : } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1154 0 : dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1155 : radeon_gart_size);
1156 0 : radeon_gart_size = radeon_gart_size_auto(rdev->family);
1157 0 : }
1158 0 : rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1159 :
1160 : /* AGP mode can only be -1, 1, 2, 4, 8 */
1161 0 : switch (radeon_agpmode) {
1162 : case -1:
1163 : case 0:
1164 : case 1:
1165 : case 2:
1166 : case 4:
1167 : case 8:
1168 : break;
1169 : default:
1170 0 : dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1171 : "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1172 0 : radeon_agpmode = 0;
1173 0 : break;
1174 : }
1175 :
1176 0 : if (!radeon_check_pot_argument(radeon_vm_size)) {
1177 0 : dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1178 : radeon_vm_size);
1179 0 : radeon_vm_size = 4;
1180 0 : }
1181 :
1182 0 : if (radeon_vm_size < 1) {
1183 0 : dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n",
1184 : radeon_vm_size);
1185 0 : radeon_vm_size = 4;
1186 0 : }
1187 :
1188 : /*
1189 : * Max GPUVM size for Cayman, SI and CI are 40 bits.
1190 : */
1191 0 : if (radeon_vm_size > 1024) {
1192 0 : dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1193 : radeon_vm_size);
1194 0 : radeon_vm_size = 4;
1195 0 : }
1196 :
1197 : /* defines number of bits in page table versus page directory,
1198 : * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1199 : * page table and the remaining bits are in the page directory */
1200 0 : if (radeon_vm_block_size == -1) {
1201 :
1202 : /* Total bits covered by PD + PTs */
1203 0 : unsigned bits = ilog2(radeon_vm_size) + 18;
1204 :
1205 : /* Make sure the PD is 4K in size up to 8GB address space.
1206 : Above that split equal between PD and PTs */
1207 0 : if (radeon_vm_size <= 8)
1208 0 : radeon_vm_block_size = bits - 9;
1209 : else
1210 0 : radeon_vm_block_size = (bits + 3) / 2;
1211 :
1212 0 : } else if (radeon_vm_block_size < 9) {
1213 0 : dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1214 : radeon_vm_block_size);
1215 0 : radeon_vm_block_size = 9;
1216 0 : }
1217 :
1218 0 : if (radeon_vm_block_size > 24 ||
1219 0 : (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1220 0 : dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1221 : radeon_vm_block_size);
1222 0 : radeon_vm_block_size = 9;
1223 0 : }
1224 0 : }
1225 :
1226 : /**
1227 : * radeon_switcheroo_set_state - set switcheroo state
1228 : *
1229 : * @pdev: pci dev pointer
1230 : * @state: vga_switcheroo state
1231 : *
1232 : * Callback for the switcheroo driver. Suspends or resumes the
1233 : * the asics before or after it is powered up using ACPI methods.
1234 : */
1235 : #ifdef notyet
1236 : static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1237 : {
1238 : struct drm_device *dev = pci_get_drvdata(pdev);
1239 : struct radeon_device *rdev = dev->dev_private;
1240 :
1241 : if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1242 : return;
1243 :
1244 : if (state == VGA_SWITCHEROO_ON) {
1245 : unsigned d3_delay = dev->pdev->d3_delay;
1246 :
1247 : printk(KERN_INFO "radeon: switched on\n");
1248 : /* don't suspend or resume card normally */
1249 : dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1250 :
1251 : if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP))
1252 : dev->pdev->d3_delay = 20;
1253 :
1254 : radeon_resume_kms(dev, true, true);
1255 :
1256 : dev->pdev->d3_delay = d3_delay;
1257 :
1258 : dev->switch_power_state = DRM_SWITCH_POWER_ON;
1259 : drm_kms_helper_poll_enable(dev);
1260 : } else {
1261 : printk(KERN_INFO "radeon: switched off\n");
1262 : drm_kms_helper_poll_disable(dev);
1263 : dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1264 : radeon_suspend_kms(dev, true, true);
1265 : dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1266 : }
1267 : }
1268 :
1269 : /**
1270 : * radeon_switcheroo_can_switch - see if switcheroo state can change
1271 : *
1272 : * @pdev: pci dev pointer
1273 : *
1274 : * Callback for the switcheroo driver. Check of the switcheroo
1275 : * state can be changed.
1276 : * Returns true if the state can be changed, false if not.
1277 : */
1278 : static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1279 : {
1280 : struct drm_device *dev = pci_get_drvdata(pdev);
1281 :
1282 : /*
1283 : * FIXME: open_count is protected by drm_global_mutex but that would lead to
1284 : * locking inversion with the driver load path. And the access here is
1285 : * completely racy anyway. So don't bother with locking for now.
1286 : */
1287 : return dev->open_count == 0;
1288 : }
1289 :
1290 : static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1291 : .set_gpu_state = radeon_switcheroo_set_state,
1292 : .reprobe = NULL,
1293 : .can_switch = radeon_switcheroo_can_switch,
1294 : };
1295 : #endif
1296 :
1297 : /**
1298 : * radeon_device_init - initialize the driver
1299 : *
1300 : * @rdev: radeon_device pointer
1301 : * @pdev: drm dev pointer
1302 : * @pdev: pci dev pointer
1303 : * @flags: driver flags
1304 : *
1305 : * Initializes the driver info and hw (all asics).
1306 : * Returns 0 for success or an error on failure.
1307 : * Called at driver startup.
1308 : */
1309 0 : int radeon_device_init(struct radeon_device *rdev,
1310 : struct drm_device *ddev,
1311 : struct pci_dev *pdev,
1312 : uint32_t flags)
1313 : {
1314 : int r, i;
1315 : int dma_bits;
1316 : bool runtime = false;
1317 :
1318 0 : rdev->shutdown = false;
1319 0 : rdev->ddev = ddev;
1320 0 : rdev->pdev = pdev;
1321 0 : rdev->flags = flags;
1322 0 : rdev->family = flags & RADEON_FAMILY_MASK;
1323 0 : rdev->is_atom_bios = false;
1324 0 : rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1325 0 : rdev->mc.gtt_size = 512 * 1024 * 1024;
1326 0 : rdev->accel_working = false;
1327 : /* set up ring ids */
1328 0 : for (i = 0; i < RADEON_NUM_RINGS; i++) {
1329 0 : rdev->ring[i].idx = i;
1330 : }
1331 0 : rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
1332 :
1333 0 : printf("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1334 0 : radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1335 0 : pdev->subsystem_vendor, pdev->subsystem_device);
1336 :
1337 : /* mutex initialization are all done here so we
1338 : * can recall function without having locking issues */
1339 0 : rw_init(&rdev->ring_lock, "ring");
1340 0 : rw_init(&rdev->dc_hw_i2c_mutex, "dciic");
1341 0 : atomic_set(&rdev->ih.lock, 0);
1342 0 : rw_init(&rdev->gem.mutex, "gem");
1343 0 : rw_init(&rdev->pm.mutex, "pm");
1344 0 : rw_init(&rdev->gpu_clock_mutex, "gpuclk");
1345 0 : rw_init(&rdev->srbm_mutex, "srbm");
1346 0 : rw_init(&rdev->grbm_idx_mutex, "grbm");
1347 0 : rw_init(&rdev->pm.mclk_lock, "mclk");
1348 0 : rw_init(&rdev->exclusive_lock, "rdnexc");
1349 0 : init_waitqueue_head(&rdev->irq.vblank_queue);
1350 0 : rw_init(&rdev->mn_lock, "mnlk");
1351 0 : hash_init(rdev->mn_hash);
1352 0 : r = radeon_gem_init(rdev);
1353 0 : if (r)
1354 0 : return r;
1355 :
1356 0 : radeon_check_arguments(rdev);
1357 : /* Adjust VM size here.
1358 : * Max GPUVM size for cayman+ is 40 bits.
1359 : */
1360 0 : rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1361 :
1362 : /* Set asic functions */
1363 0 : r = radeon_asic_init(rdev);
1364 0 : if (r)
1365 0 : return r;
1366 :
1367 : /* all of the newer IGP chips have an internal gart
1368 : * However some rs4xx report as AGP, so remove that here.
1369 : */
1370 0 : if ((rdev->family >= CHIP_RS400) &&
1371 0 : (rdev->flags & RADEON_IS_IGP)) {
1372 0 : rdev->flags &= ~RADEON_IS_AGP;
1373 0 : }
1374 :
1375 0 : if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1376 0 : radeon_agp_disable(rdev);
1377 0 : }
1378 :
1379 : /* Set the internal MC address mask
1380 : * This is the max address of the GPU's
1381 : * internal address space.
1382 : */
1383 0 : if (rdev->family >= CHIP_CAYMAN)
1384 0 : rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1385 0 : else if (rdev->family >= CHIP_CEDAR)
1386 0 : rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1387 : else
1388 0 : rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1389 :
1390 : /* set DMA mask + need_dma32 flags.
1391 : * PCIE - can handle 40-bits.
1392 : * IGP - can handle 40-bits
1393 : * AGP - generally dma32 is safest
1394 : * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1395 : */
1396 0 : rdev->need_dma32 = false;
1397 0 : if (rdev->flags & RADEON_IS_AGP)
1398 0 : rdev->need_dma32 = true;
1399 0 : if ((rdev->flags & RADEON_IS_PCI) &&
1400 0 : (rdev->family <= CHIP_RS740))
1401 0 : rdev->need_dma32 = true;
1402 :
1403 0 : dma_bits = rdev->need_dma32 ? 32 : 40;
1404 : #ifdef notyet
1405 : r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1406 : if (r) {
1407 : rdev->need_dma32 = true;
1408 : dma_bits = 32;
1409 : printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1410 : }
1411 : r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1412 : if (r) {
1413 : pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1414 : printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1415 : }
1416 : #endif
1417 :
1418 : /* Registers mapping */
1419 : /* TODO: block userspace mapping of io register */
1420 0 : mtx_init(&rdev->mmio_idx_lock, IPL_TTY);
1421 0 : mtx_init(&rdev->smc_idx_lock, IPL_TTY);
1422 0 : mtx_init(&rdev->pll_idx_lock, IPL_TTY);
1423 0 : mtx_init(&rdev->mc_idx_lock, IPL_TTY);
1424 0 : mtx_init(&rdev->pcie_idx_lock, IPL_TTY);
1425 0 : mtx_init(&rdev->pciep_idx_lock, IPL_TTY);
1426 0 : mtx_init(&rdev->pif_idx_lock, IPL_TTY);
1427 0 : mtx_init(&rdev->cg_idx_lock, IPL_TTY);
1428 0 : mtx_init(&rdev->uvd_idx_lock, IPL_TTY);
1429 0 : mtx_init(&rdev->rcu_idx_lock, IPL_TTY);
1430 0 : mtx_init(&rdev->didt_idx_lock, IPL_TTY);
1431 0 : mtx_init(&rdev->end_idx_lock, IPL_TTY);
1432 : #ifdef __linux__
1433 : if (rdev->family >= CHIP_BONAIRE) {
1434 : rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1435 : rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1436 : } else {
1437 : rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1438 : rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1439 : }
1440 : rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1441 : if (rdev->rmmio == NULL) {
1442 : return -ENOMEM;
1443 : }
1444 : #endif
1445 : DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1446 : DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1447 :
1448 : /* doorbell bar mapping */
1449 0 : if (rdev->family >= CHIP_BONAIRE)
1450 0 : radeon_doorbell_init(rdev);
1451 :
1452 : /* io port mapping */
1453 : #ifdef linux
1454 : for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1455 : if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1456 : rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1457 : rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1458 : break;
1459 : }
1460 : }
1461 : if (rdev->rio_mem == NULL)
1462 : DRM_ERROR("Unable to find PCI I/O BAR\n");
1463 : #endif
1464 :
1465 0 : if (rdev->flags & RADEON_IS_PX)
1466 0 : radeon_device_handle_px_quirks(rdev);
1467 :
1468 : /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1469 : /* this will fail for cards that aren't VGA class devices, just
1470 : * ignore it */
1471 : #ifdef notyet
1472 : vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1473 : #endif
1474 :
1475 0 : if (rdev->flags & RADEON_IS_PX)
1476 0 : runtime = true;
1477 : #ifdef notyet
1478 : vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
1479 : if (runtime)
1480 : vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1481 : #endif
1482 :
1483 0 : r = radeon_init(rdev);
1484 0 : if (r)
1485 : goto failed;
1486 :
1487 0 : r = radeon_gem_debugfs_init(rdev);
1488 0 : if (r) {
1489 0 : DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1490 0 : }
1491 :
1492 0 : r = radeon_mst_debugfs_init(rdev);
1493 0 : if (r) {
1494 0 : DRM_ERROR("registering mst debugfs failed (%d).\n", r);
1495 0 : }
1496 :
1497 0 : if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1498 : /* Acceleration not working on AGP card try again
1499 : * with fallback to PCI or PCIE GART
1500 : */
1501 0 : radeon_asic_reset(rdev);
1502 0 : radeon_fini(rdev);
1503 0 : radeon_agp_disable(rdev);
1504 0 : r = radeon_init(rdev);
1505 0 : if (r)
1506 : goto failed;
1507 : }
1508 :
1509 0 : r = radeon_ib_ring_tests(rdev);
1510 0 : if (r)
1511 0 : DRM_ERROR("ib ring test failed (%d).\n", r);
1512 :
1513 : /*
1514 : * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1515 : * after the CP ring have chew one packet at least. Hence here we stop
1516 : * and restart DPM after the radeon_ib_ring_tests().
1517 : */
1518 0 : if (rdev->pm.dpm_enabled &&
1519 0 : (rdev->pm.pm_method == PM_METHOD_DPM) &&
1520 0 : (rdev->family == CHIP_TURKS) &&
1521 0 : (rdev->flags & RADEON_IS_MOBILITY)) {
1522 0 : mutex_lock(&rdev->pm.mutex);
1523 0 : radeon_dpm_disable(rdev);
1524 0 : radeon_dpm_enable(rdev);
1525 0 : mutex_unlock(&rdev->pm.mutex);
1526 0 : }
1527 :
1528 0 : if ((radeon_testing & 1)) {
1529 0 : if (rdev->accel_working)
1530 0 : radeon_test_moves(rdev);
1531 : else
1532 : DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1533 : }
1534 0 : if ((radeon_testing & 2)) {
1535 0 : if (rdev->accel_working)
1536 0 : radeon_test_syncing(rdev);
1537 : else
1538 : DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1539 : }
1540 0 : if (radeon_benchmarking) {
1541 0 : if (rdev->accel_working)
1542 0 : radeon_benchmark(rdev, radeon_benchmarking);
1543 : else
1544 : DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1545 : }
1546 0 : return 0;
1547 :
1548 : failed:
1549 : #ifdef notyet
1550 : if (runtime)
1551 : vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1552 : #endif
1553 0 : return r;
1554 0 : }
1555 :
1556 : static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1557 :
1558 : /**
1559 : * radeon_device_fini - tear down the driver
1560 : *
1561 : * @rdev: radeon_device pointer
1562 : *
1563 : * Tear down the driver info (all asics).
1564 : * Called at driver shutdown.
1565 : */
1566 0 : void radeon_device_fini(struct radeon_device *rdev)
1567 : {
1568 : DRM_INFO("radeon: finishing device.\n");
1569 0 : rdev->shutdown = true;
1570 : /* evict vram memory */
1571 0 : radeon_bo_evict_vram(rdev);
1572 0 : radeon_fini(rdev);
1573 : vga_switcheroo_unregister_client(rdev->pdev);
1574 0 : if (rdev->flags & RADEON_IS_PX)
1575 : vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1576 0 : vga_client_register(rdev->pdev, NULL, NULL, NULL);
1577 : #ifdef __linux__
1578 : if (rdev->rio_mem)
1579 : pci_iounmap(rdev->pdev, rdev->rio_mem);
1580 : rdev->rio_mem = NULL;
1581 : iounmap(rdev->rmmio);
1582 : rdev->rmmio = NULL;
1583 : #else
1584 0 : if (rdev->rio_mem_size > 0)
1585 0 : bus_space_unmap(rdev->iot, rdev->rio_mem, rdev->rio_mem_size);
1586 0 : rdev->rio_mem_size = 0;
1587 :
1588 0 : if (rdev->rmmio_size > 0)
1589 0 : bus_space_unmap(rdev->memt, rdev->rmmio_bsh, rdev->rmmio_size);
1590 0 : rdev->rmmio_size = 0;
1591 : #endif
1592 0 : if (rdev->family >= CHIP_BONAIRE)
1593 0 : radeon_doorbell_fini(rdev);
1594 0 : radeon_debugfs_remove_files(rdev);
1595 0 : }
1596 :
1597 :
1598 : /*
1599 : * Suspend & resume.
1600 : */
1601 : /**
1602 : * radeon_suspend_kms - initiate device suspend
1603 : *
1604 : * @pdev: drm dev pointer
1605 : * @state: suspend state
1606 : *
1607 : * Puts the hw in the suspend state (all asics).
1608 : * Returns 0 for success or an error on failure.
1609 : * Called at driver suspend.
1610 : */
1611 0 : int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1612 : {
1613 : struct radeon_device *rdev;
1614 : struct drm_crtc *crtc;
1615 : struct drm_connector *connector;
1616 : int i, r;
1617 :
1618 0 : if (dev == NULL || dev->dev_private == NULL) {
1619 0 : return -ENODEV;
1620 : }
1621 :
1622 0 : rdev = dev->dev_private;
1623 0 : if (rdev->shutdown)
1624 0 : return 0;
1625 :
1626 : #ifdef notyet
1627 : if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1628 : return 0;
1629 : #endif
1630 :
1631 0 : drm_kms_helper_poll_disable(dev);
1632 :
1633 0 : drm_modeset_lock_all(dev);
1634 : /* turn off display hw */
1635 0 : list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1636 0 : drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1637 : }
1638 0 : drm_modeset_unlock_all(dev);
1639 :
1640 : /* unpin the front buffers and cursors */
1641 0 : list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1642 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1643 0 : struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1644 : struct radeon_bo *robj;
1645 :
1646 0 : if (radeon_crtc->cursor_bo) {
1647 0 : struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1648 0 : r = radeon_bo_reserve(robj, false);
1649 0 : if (r == 0) {
1650 0 : radeon_bo_unpin(robj);
1651 0 : radeon_bo_unreserve(robj);
1652 0 : }
1653 0 : }
1654 :
1655 0 : if (rfb == NULL || rfb->obj == NULL) {
1656 0 : continue;
1657 : }
1658 0 : robj = gem_to_radeon_bo(rfb->obj);
1659 : /* don't unpin kernel fb objects */
1660 0 : if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1661 0 : r = radeon_bo_reserve(robj, false);
1662 0 : if (r == 0) {
1663 0 : radeon_bo_unpin(robj);
1664 0 : radeon_bo_unreserve(robj);
1665 0 : }
1666 : }
1667 0 : }
1668 : /* evict vram memory */
1669 0 : radeon_bo_evict_vram(rdev);
1670 :
1671 : /* wait for gpu to finish processing current batch */
1672 0 : for (i = 0; i < RADEON_NUM_RINGS; i++) {
1673 0 : r = radeon_fence_wait_empty(rdev, i);
1674 0 : if (r) {
1675 : /* delay GPU reset to resume */
1676 0 : radeon_fence_driver_force_completion(rdev, i);
1677 0 : }
1678 : }
1679 :
1680 0 : radeon_save_bios_scratch_regs(rdev);
1681 :
1682 0 : radeon_suspend(rdev);
1683 0 : radeon_hpd_fini(rdev);
1684 : /* evict remaining vram memory */
1685 0 : radeon_bo_evict_vram(rdev);
1686 :
1687 0 : radeon_agp_suspend(rdev);
1688 :
1689 : pci_save_state(dev->pdev);
1690 : if (suspend) {
1691 : /* Shut down the device */
1692 : pci_disable_device(dev->pdev);
1693 : pci_set_power_state(dev->pdev, PCI_D3hot);
1694 : }
1695 :
1696 0 : if (fbcon) {
1697 : console_lock();
1698 0 : radeon_fbdev_set_suspend(rdev, 1);
1699 : console_unlock();
1700 0 : }
1701 0 : return 0;
1702 0 : }
1703 :
1704 : /**
1705 : * radeon_resume_kms - initiate device resume
1706 : *
1707 : * @pdev: drm dev pointer
1708 : *
1709 : * Bring the hw back to operating state (all asics).
1710 : * Returns 0 for success or an error on failure.
1711 : * Called at driver resume.
1712 : */
1713 0 : int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1714 : {
1715 : struct drm_connector *connector;
1716 0 : struct radeon_device *rdev = dev->dev_private;
1717 : struct drm_crtc *crtc;
1718 : int r;
1719 :
1720 : #ifdef notyet
1721 : if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1722 : return 0;
1723 : #endif
1724 :
1725 : if (fbcon) {
1726 : console_lock();
1727 : }
1728 : if (resume) {
1729 : pci_set_power_state(dev->pdev, PCI_D0);
1730 : pci_restore_state(dev->pdev);
1731 : if (pci_enable_device(dev->pdev)) {
1732 : if (fbcon)
1733 : console_unlock();
1734 : return -1;
1735 : }
1736 : }
1737 : /* resume AGP if in use */
1738 0 : radeon_agp_resume(rdev);
1739 0 : radeon_resume(rdev);
1740 :
1741 0 : r = radeon_ib_ring_tests(rdev);
1742 0 : if (r)
1743 0 : DRM_ERROR("ib ring test failed (%d).\n", r);
1744 :
1745 0 : if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1746 : /* do dpm late init */
1747 0 : r = radeon_pm_late_init(rdev);
1748 0 : if (r) {
1749 0 : rdev->pm.dpm_enabled = false;
1750 0 : DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1751 0 : }
1752 : } else {
1753 : /* resume old pm late */
1754 0 : radeon_pm_resume(rdev);
1755 : }
1756 :
1757 0 : radeon_restore_bios_scratch_regs(rdev);
1758 :
1759 : /* pin cursors */
1760 0 : list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1761 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1762 :
1763 0 : if (radeon_crtc->cursor_bo) {
1764 0 : struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1765 0 : r = radeon_bo_reserve(robj, false);
1766 0 : if (r == 0) {
1767 : /* Only 27 bit offset for legacy cursor */
1768 0 : r = radeon_bo_pin_restricted(robj,
1769 : RADEON_GEM_DOMAIN_VRAM,
1770 0 : ASIC_IS_AVIVO(rdev) ?
1771 : 0 : 1 << 27,
1772 0 : &radeon_crtc->cursor_addr);
1773 0 : if (r != 0)
1774 0 : DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1775 0 : radeon_bo_unreserve(robj);
1776 0 : }
1777 0 : }
1778 : }
1779 :
1780 : /* init dig PHYs, disp eng pll */
1781 0 : if (rdev->is_atom_bios) {
1782 0 : radeon_atom_encoder_init(rdev);
1783 0 : radeon_atom_disp_eng_pll_init(rdev);
1784 : /* turn on the BL */
1785 0 : if (rdev->mode_info.bl_encoder) {
1786 0 : u8 bl_level = radeon_get_backlight_level(rdev,
1787 : rdev->mode_info.bl_encoder);
1788 0 : radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1789 : bl_level);
1790 0 : }
1791 : }
1792 : /* reset hpd state */
1793 0 : radeon_hpd_init(rdev);
1794 : /* blat the mode back in */
1795 0 : if (fbcon) {
1796 0 : drm_helper_resume_force_mode(dev);
1797 : /* turn on display hw */
1798 0 : drm_modeset_lock_all(dev);
1799 0 : list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1800 0 : drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1801 : }
1802 0 : drm_modeset_unlock_all(dev);
1803 0 : }
1804 :
1805 0 : drm_kms_helper_poll_enable(dev);
1806 :
1807 : /* set the power state here in case we are a PX system or headless */
1808 0 : if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1809 0 : radeon_pm_compute_clocks(rdev);
1810 :
1811 0 : if (fbcon) {
1812 0 : radeon_fbdev_set_suspend(rdev, 0);
1813 : console_unlock();
1814 0 : }
1815 :
1816 0 : return 0;
1817 : }
1818 :
1819 : /**
1820 : * radeon_gpu_reset - reset the asic
1821 : *
1822 : * @rdev: radeon device pointer
1823 : *
1824 : * Attempt the reset the GPU if it has hung (all asics).
1825 : * Returns 0 for success or an error on failure.
1826 : */
1827 0 : int radeon_gpu_reset(struct radeon_device *rdev)
1828 : {
1829 0 : unsigned ring_sizes[RADEON_NUM_RINGS];
1830 0 : uint32_t *ring_data[RADEON_NUM_RINGS];
1831 :
1832 : bool saved = false;
1833 :
1834 : int i, r;
1835 : int resched;
1836 :
1837 0 : down_write(&rdev->exclusive_lock);
1838 :
1839 0 : if (!rdev->needs_reset) {
1840 0 : up_write(&rdev->exclusive_lock);
1841 0 : return 0;
1842 : }
1843 :
1844 0 : atomic_inc(&rdev->gpu_reset_counter);
1845 :
1846 0 : radeon_save_bios_scratch_regs(rdev);
1847 : /* block TTM */
1848 0 : resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1849 0 : radeon_suspend(rdev);
1850 0 : radeon_hpd_fini(rdev);
1851 :
1852 0 : for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1853 0 : ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1854 0 : &ring_data[i]);
1855 0 : if (ring_sizes[i]) {
1856 : saved = true;
1857 : dev_info(rdev->dev, "Saved %d dwords of commands "
1858 : "on ring %d.\n", ring_sizes[i], i);
1859 0 : }
1860 : }
1861 :
1862 0 : r = radeon_asic_reset(rdev);
1863 0 : if (!r) {
1864 : dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1865 0 : radeon_resume(rdev);
1866 0 : }
1867 :
1868 0 : radeon_restore_bios_scratch_regs(rdev);
1869 :
1870 0 : for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1871 0 : if (!r && ring_data[i]) {
1872 0 : radeon_ring_restore(rdev, &rdev->ring[i],
1873 0 : ring_sizes[i], ring_data[i]);
1874 0 : } else {
1875 0 : radeon_fence_driver_force_completion(rdev, i);
1876 0 : kfree(ring_data[i]);
1877 : }
1878 : }
1879 :
1880 0 : if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1881 : /* do dpm late init */
1882 0 : r = radeon_pm_late_init(rdev);
1883 0 : if (r) {
1884 0 : rdev->pm.dpm_enabled = false;
1885 0 : DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1886 0 : }
1887 : } else {
1888 : /* resume old pm late */
1889 0 : radeon_pm_resume(rdev);
1890 : }
1891 :
1892 : /* init dig PHYs, disp eng pll */
1893 0 : if (rdev->is_atom_bios) {
1894 0 : radeon_atom_encoder_init(rdev);
1895 0 : radeon_atom_disp_eng_pll_init(rdev);
1896 : /* turn on the BL */
1897 0 : if (rdev->mode_info.bl_encoder) {
1898 0 : u8 bl_level = radeon_get_backlight_level(rdev,
1899 : rdev->mode_info.bl_encoder);
1900 0 : radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1901 : bl_level);
1902 0 : }
1903 : }
1904 : /* reset hpd state */
1905 0 : radeon_hpd_init(rdev);
1906 :
1907 0 : ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1908 :
1909 0 : rdev->in_reset = true;
1910 0 : rdev->needs_reset = false;
1911 :
1912 : #ifdef notyet
1913 : downgrade_write(&rdev->exclusive_lock);
1914 : #endif
1915 :
1916 0 : drm_helper_resume_force_mode(rdev->ddev);
1917 :
1918 : /* set the power state here in case we are a PX system or headless */
1919 0 : if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1920 0 : radeon_pm_compute_clocks(rdev);
1921 :
1922 0 : if (!r) {
1923 0 : r = radeon_ib_ring_tests(rdev);
1924 0 : if (r && saved)
1925 0 : r = -EAGAIN;
1926 : } else {
1927 : /* bad news, how to tell it to userspace ? */
1928 : dev_info(rdev->dev, "GPU reset failed\n");
1929 : }
1930 :
1931 0 : rdev->needs_reset = r == -EAGAIN;
1932 0 : rdev->in_reset = false;
1933 :
1934 0 : up_read(&rdev->exclusive_lock);
1935 0 : return r;
1936 0 : }
1937 :
1938 :
1939 : /*
1940 : * Debugfs
1941 : */
1942 0 : int radeon_debugfs_add_files(struct radeon_device *rdev,
1943 : struct drm_info_list *files,
1944 : unsigned nfiles)
1945 : {
1946 : unsigned i;
1947 :
1948 0 : for (i = 0; i < rdev->debugfs_count; i++) {
1949 0 : if (rdev->debugfs[i].files == files) {
1950 : /* Already registered */
1951 0 : return 0;
1952 : }
1953 : }
1954 :
1955 0 : i = rdev->debugfs_count + 1;
1956 0 : if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1957 0 : DRM_ERROR("Reached maximum number of debugfs components.\n");
1958 0 : DRM_ERROR("Report so we increase "
1959 : "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1960 0 : return -EINVAL;
1961 : }
1962 0 : rdev->debugfs[rdev->debugfs_count].files = files;
1963 0 : rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1964 0 : rdev->debugfs_count = i;
1965 : #if defined(CONFIG_DEBUG_FS)
1966 : drm_debugfs_create_files(files, nfiles,
1967 : rdev->ddev->control->debugfs_root,
1968 : rdev->ddev->control);
1969 : drm_debugfs_create_files(files, nfiles,
1970 : rdev->ddev->primary->debugfs_root,
1971 : rdev->ddev->primary);
1972 : #endif
1973 0 : return 0;
1974 0 : }
1975 :
1976 0 : static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1977 : {
1978 : #if defined(CONFIG_DEBUG_FS)
1979 : unsigned i;
1980 :
1981 : for (i = 0; i < rdev->debugfs_count; i++) {
1982 : drm_debugfs_remove_files(rdev->debugfs[i].files,
1983 : rdev->debugfs[i].num_files,
1984 : rdev->ddev->control);
1985 : drm_debugfs_remove_files(rdev->debugfs[i].files,
1986 : rdev->debugfs[i].num_files,
1987 : rdev->ddev->primary);
1988 : }
1989 : #endif
1990 0 : }
1991 :
1992 : #if defined(CONFIG_DEBUG_FS)
1993 : int radeon_debugfs_init(struct drm_minor *minor)
1994 : {
1995 : return 0;
1996 : }
1997 :
1998 : void radeon_debugfs_cleanup(struct drm_minor *minor)
1999 : {
2000 : }
2001 : #endif
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