Line data Source code
1 : /*
2 : * Copyright 2007-8 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: Dave Airlie
24 : * Alex Deucher
25 : */
26 :
27 : #include <dev/pci/drm/drmP.h>
28 : #include <dev/pci/drm/drm_edid.h>
29 : #include <dev/pci/drm/radeon_drm.h>
30 : #include "radeon.h"
31 : #include "atom.h"
32 :
33 : #include <dev/i2c/i2cvar.h>
34 : #include <dev/i2c/i2c_bitbang.h>
35 :
36 : extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
37 : struct i2c_msg *msgs, int num);
38 : extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap);
39 :
40 : /**
41 : * radeon_ddc_probe
42 : *
43 : */
44 0 : bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
45 : {
46 0 : u8 out = 0x0;
47 0 : u8 buf[8];
48 : int ret;
49 0 : struct i2c_msg msgs[] = {
50 0 : {
51 : .addr = DDC_ADDR,
52 : .flags = 0,
53 : .len = 1,
54 : .buf = &out,
55 : },
56 0 : {
57 : .addr = DDC_ADDR,
58 : .flags = I2C_M_RD,
59 : .len = 8,
60 0 : .buf = buf,
61 : }
62 : };
63 :
64 : /* on hw with routers, select right port */
65 0 : if (radeon_connector->router.ddc_valid)
66 0 : radeon_router_select_ddc_port(radeon_connector);
67 :
68 0 : if (use_aux) {
69 0 : ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2);
70 0 : } else {
71 0 : ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
72 : }
73 :
74 0 : if (ret != 2)
75 : /* Couldn't find an accessible DDC on this connector */
76 0 : return false;
77 : /* Probe also for valid EDID header
78 : * EDID header starts with:
79 : * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
80 : * Only the first 6 bytes must be valid as
81 : * drm_edid_block_valid() can fix the last 2 bytes */
82 0 : if (drm_edid_header_is_valid(buf) < 6) {
83 : /* Couldn't find an accessible EDID on this
84 : * connector */
85 0 : return false;
86 : }
87 0 : return true;
88 0 : }
89 :
90 : /* bit banging i2c */
91 :
92 0 : static int pre_xfer(struct i2c_adapter *i2c_adap)
93 : {
94 0 : struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
95 0 : struct radeon_device *rdev = i2c->dev->dev_private;
96 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
97 : uint32_t temp;
98 :
99 0 : mutex_lock(&i2c->mutex);
100 :
101 : /* RV410 appears to have a bug where the hw i2c in reset
102 : * holds the i2c port in a bad state - switch hw i2c away before
103 : * doing DDC - do this for all r200s/r300s/r400s for safety sake
104 : */
105 0 : if (rec->hw_capable) {
106 0 : if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
107 : u32 reg;
108 :
109 0 : if (rdev->family >= CHIP_RV350)
110 0 : reg = RADEON_GPIO_MONID;
111 0 : else if ((rdev->family == CHIP_R300) ||
112 0 : (rdev->family == CHIP_R350))
113 0 : reg = RADEON_GPIO_DVI_DDC;
114 : else
115 : reg = RADEON_GPIO_CRT2_DDC;
116 :
117 0 : mutex_lock(&rdev->dc_hw_i2c_mutex);
118 0 : if (rec->a_clk_reg == reg) {
119 0 : WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
120 : R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
121 0 : } else {
122 0 : WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
123 : R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
124 : }
125 0 : mutex_unlock(&rdev->dc_hw_i2c_mutex);
126 0 : }
127 : }
128 :
129 : /* switch the pads to ddc mode */
130 0 : if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
131 0 : temp = RREG32(rec->mask_clk_reg);
132 0 : temp &= ~(1 << 16);
133 0 : WREG32(rec->mask_clk_reg, temp);
134 0 : }
135 :
136 : /* clear the output pin values */
137 0 : temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
138 0 : WREG32(rec->a_clk_reg, temp);
139 :
140 0 : temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
141 0 : WREG32(rec->a_data_reg, temp);
142 :
143 : /* set the pins to input */
144 0 : temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
145 0 : WREG32(rec->en_clk_reg, temp);
146 :
147 0 : temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
148 0 : WREG32(rec->en_data_reg, temp);
149 :
150 : /* mask the gpio pins for software use */
151 0 : temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
152 0 : WREG32(rec->mask_clk_reg, temp);
153 0 : temp = RREG32(rec->mask_clk_reg);
154 :
155 0 : temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
156 0 : WREG32(rec->mask_data_reg, temp);
157 0 : temp = RREG32(rec->mask_data_reg);
158 :
159 0 : return 0;
160 : }
161 :
162 0 : static void post_xfer(struct i2c_adapter *i2c_adap)
163 : {
164 0 : struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
165 0 : struct radeon_device *rdev = i2c->dev->dev_private;
166 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
167 : uint32_t temp;
168 :
169 : /* unmask the gpio pins for software use */
170 0 : temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
171 0 : WREG32(rec->mask_clk_reg, temp);
172 0 : temp = RREG32(rec->mask_clk_reg);
173 :
174 0 : temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
175 0 : WREG32(rec->mask_data_reg, temp);
176 0 : temp = RREG32(rec->mask_data_reg);
177 :
178 0 : mutex_unlock(&i2c->mutex);
179 0 : }
180 :
181 0 : static int get_clock(void *i2c_priv)
182 : {
183 0 : struct radeon_i2c_chan *i2c = i2c_priv;
184 0 : struct radeon_device *rdev = i2c->dev->dev_private;
185 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
186 : uint32_t val;
187 :
188 : /* read the value off the pin */
189 0 : val = RREG32(rec->y_clk_reg);
190 0 : val &= rec->y_clk_mask;
191 :
192 0 : return (val != 0);
193 : }
194 :
195 :
196 0 : static int get_data(void *i2c_priv)
197 : {
198 0 : struct radeon_i2c_chan *i2c = i2c_priv;
199 0 : struct radeon_device *rdev = i2c->dev->dev_private;
200 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
201 : uint32_t val;
202 :
203 : /* read the value off the pin */
204 0 : val = RREG32(rec->y_data_reg);
205 0 : val &= rec->y_data_mask;
206 :
207 0 : return (val != 0);
208 : }
209 :
210 0 : static void set_clock(void *i2c_priv, int clock)
211 : {
212 0 : struct radeon_i2c_chan *i2c = i2c_priv;
213 0 : struct radeon_device *rdev = i2c->dev->dev_private;
214 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
215 : uint32_t val;
216 :
217 : /* set pin direction */
218 0 : val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
219 0 : val |= clock ? 0 : rec->en_clk_mask;
220 0 : WREG32(rec->en_clk_reg, val);
221 0 : }
222 :
223 0 : static void set_data(void *i2c_priv, int data)
224 : {
225 0 : struct radeon_i2c_chan *i2c = i2c_priv;
226 0 : struct radeon_device *rdev = i2c->dev->dev_private;
227 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
228 : uint32_t val;
229 :
230 : /* set pin direction */
231 0 : val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
232 0 : val |= data ? 0 : rec->en_data_mask;
233 0 : WREG32(rec->en_data_reg, val);
234 0 : }
235 :
236 : void radeon_bb_set_bits(void *, uint32_t);
237 : void radeon_bb_set_dir(void *, uint32_t);
238 : uint32_t radeon_bb_read_bits(void *);
239 :
240 : int radeon_acquire_bus(void *, int);
241 : void radeon_release_bus(void *, int);
242 : int radeon_send_start(void *, int);
243 : int radeon_send_stop(void *, int);
244 : int radeon_initiate_xfer(void *, i2c_addr_t, int);
245 : int radeon_read_byte(void *, u_int8_t *, int);
246 : int radeon_write_byte(void *, u_int8_t, int);
247 :
248 : #define RADEON_BB_SDA (1 << I2C_BIT_SDA)
249 : #define RADEON_BB_SCL (1 << I2C_BIT_SCL)
250 :
251 : struct i2c_bitbang_ops radeon_bbops = {
252 : radeon_bb_set_bits,
253 : radeon_bb_set_dir,
254 : radeon_bb_read_bits,
255 : { RADEON_BB_SDA, RADEON_BB_SCL, 0, 0 }
256 : };
257 :
258 : void
259 0 : radeon_bb_set_bits(void *cookie, uint32_t bits)
260 : {
261 0 : set_clock(cookie, bits & RADEON_BB_SCL);
262 0 : set_data(cookie, bits & RADEON_BB_SDA);
263 0 : }
264 :
265 : void
266 0 : radeon_bb_set_dir(void *cookie, uint32_t bits)
267 : {
268 0 : }
269 :
270 : uint32_t
271 0 : radeon_bb_read_bits(void *cookie)
272 : {
273 : uint32_t bits = 0;
274 :
275 0 : if (get_clock(cookie))
276 0 : bits |= RADEON_BB_SCL;
277 0 : if (get_data(cookie))
278 0 : bits |= RADEON_BB_SDA;
279 :
280 0 : return bits;
281 : }
282 :
283 : int
284 0 : radeon_acquire_bus(void *cookie, int flags)
285 : {
286 0 : struct radeon_i2c_chan *i2c = cookie;
287 0 : pre_xfer(&i2c->adapter);
288 0 : return (0);
289 : }
290 :
291 : void
292 0 : radeon_release_bus(void *cookie, int flags)
293 : {
294 0 : struct radeon_i2c_chan *i2c = cookie;
295 0 : post_xfer(&i2c->adapter);
296 0 : }
297 :
298 : int
299 0 : radeon_send_start(void *cookie, int flags)
300 : {
301 0 : return (i2c_bitbang_send_start(cookie, flags, &radeon_bbops));
302 : }
303 :
304 : int
305 0 : radeon_send_stop(void *cookie, int flags)
306 : {
307 0 : return (i2c_bitbang_send_stop(cookie, flags, &radeon_bbops));
308 : }
309 :
310 : int
311 0 : radeon_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
312 : {
313 0 : return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &radeon_bbops));
314 : }
315 :
316 : int
317 0 : radeon_read_byte(void *cookie, u_int8_t *bytep, int flags)
318 : {
319 0 : return (i2c_bitbang_read_byte(cookie, bytep, flags, &radeon_bbops));
320 : }
321 :
322 : int
323 0 : radeon_write_byte(void *cookie, u_int8_t byte, int flags)
324 : {
325 0 : return (i2c_bitbang_write_byte(cookie, byte, flags, &radeon_bbops));
326 : }
327 :
328 :
329 : /* hw i2c */
330 :
331 0 : static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
332 : {
333 0 : u32 sclk = rdev->pm.current_sclk;
334 : u32 prescale = 0;
335 : u32 nm;
336 : u8 n, m, loop;
337 : int i2c_clock;
338 :
339 0 : switch (rdev->family) {
340 : case CHIP_R100:
341 : case CHIP_RV100:
342 : case CHIP_RS100:
343 : case CHIP_RV200:
344 : case CHIP_RS200:
345 : case CHIP_R200:
346 : case CHIP_RV250:
347 : case CHIP_RS300:
348 : case CHIP_RV280:
349 : case CHIP_R300:
350 : case CHIP_R350:
351 : case CHIP_RV350:
352 : i2c_clock = 60;
353 0 : nm = (sclk * 10) / (i2c_clock * 4);
354 0 : for (loop = 1; loop < 255; loop++) {
355 0 : if ((nm / loop) < loop)
356 : break;
357 : }
358 0 : n = loop - 1;
359 0 : m = loop - 2;
360 0 : prescale = m | (n << 8);
361 0 : break;
362 : case CHIP_RV380:
363 : case CHIP_RS400:
364 : case CHIP_RS480:
365 : case CHIP_R420:
366 : case CHIP_R423:
367 : case CHIP_RV410:
368 0 : prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
369 0 : break;
370 : case CHIP_RS600:
371 : case CHIP_RS690:
372 : case CHIP_RS740:
373 : /* todo */
374 : break;
375 : case CHIP_RV515:
376 : case CHIP_R520:
377 : case CHIP_RV530:
378 : case CHIP_RV560:
379 : case CHIP_RV570:
380 : case CHIP_R580:
381 : i2c_clock = 50;
382 0 : if (rdev->family == CHIP_R520)
383 0 : prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
384 : else
385 0 : prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
386 : break;
387 : case CHIP_R600:
388 : case CHIP_RV610:
389 : case CHIP_RV630:
390 : case CHIP_RV670:
391 : /* todo */
392 : break;
393 : case CHIP_RV620:
394 : case CHIP_RV635:
395 : case CHIP_RS780:
396 : case CHIP_RS880:
397 : case CHIP_RV770:
398 : case CHIP_RV730:
399 : case CHIP_RV710:
400 : case CHIP_RV740:
401 : /* todo */
402 : break;
403 : case CHIP_CEDAR:
404 : case CHIP_REDWOOD:
405 : case CHIP_JUNIPER:
406 : case CHIP_CYPRESS:
407 : case CHIP_HEMLOCK:
408 : /* todo */
409 : break;
410 : default:
411 0 : DRM_ERROR("i2c: unhandled radeon chip\n");
412 0 : break;
413 : }
414 0 : return prescale;
415 : }
416 :
417 :
418 : /* hw i2c engine for r1xx-4xx hardware
419 : * hw can buffer up to 15 bytes
420 : */
421 0 : static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
422 : struct i2c_msg *msgs, int num)
423 : {
424 0 : struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
425 0 : struct radeon_device *rdev = i2c->dev->dev_private;
426 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
427 : struct i2c_msg *p;
428 : int i, j, k, ret = num;
429 : u32 prescale;
430 : u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
431 : u32 tmp, reg;
432 :
433 0 : mutex_lock(&rdev->dc_hw_i2c_mutex);
434 : /* take the pm lock since we need a constant sclk */
435 0 : mutex_lock(&rdev->pm.mutex);
436 :
437 0 : prescale = radeon_get_i2c_prescale(rdev);
438 :
439 0 : reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
440 0 : RADEON_I2C_DRIVE_EN |
441 0 : RADEON_I2C_START |
442 0 : RADEON_I2C_STOP |
443 : RADEON_I2C_GO);
444 :
445 0 : if (rdev->is_atom_bios) {
446 0 : tmp = RREG32(RADEON_BIOS_6_SCRATCH);
447 0 : WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
448 0 : }
449 :
450 0 : if (rec->mm_i2c) {
451 : i2c_cntl_0 = RADEON_I2C_CNTL_0;
452 : i2c_cntl_1 = RADEON_I2C_CNTL_1;
453 : i2c_data = RADEON_I2C_DATA;
454 0 : } else {
455 : i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
456 : i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
457 : i2c_data = RADEON_DVI_I2C_DATA;
458 :
459 0 : switch (rdev->family) {
460 : case CHIP_R100:
461 : case CHIP_RV100:
462 : case CHIP_RS100:
463 : case CHIP_RV200:
464 : case CHIP_RS200:
465 : case CHIP_RS300:
466 0 : switch (rec->mask_clk_reg) {
467 : case RADEON_GPIO_DVI_DDC:
468 : /* no gpio select bit */
469 : break;
470 : default:
471 0 : DRM_ERROR("gpio not supported with hw i2c\n");
472 : ret = -EINVAL;
473 0 : goto done;
474 : }
475 : break;
476 : case CHIP_R200:
477 : /* only bit 4 on r200 */
478 0 : switch (rec->mask_clk_reg) {
479 : case RADEON_GPIO_DVI_DDC:
480 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
481 0 : break;
482 : case RADEON_GPIO_MONID:
483 0 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
484 0 : break;
485 : default:
486 0 : DRM_ERROR("gpio not supported with hw i2c\n");
487 : ret = -EINVAL;
488 0 : goto done;
489 : }
490 : break;
491 : case CHIP_RV250:
492 : case CHIP_RV280:
493 : /* bits 3 and 4 */
494 0 : switch (rec->mask_clk_reg) {
495 : case RADEON_GPIO_DVI_DDC:
496 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
497 0 : break;
498 : case RADEON_GPIO_VGA_DDC:
499 0 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
500 0 : break;
501 : case RADEON_GPIO_CRT2_DDC:
502 0 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
503 0 : break;
504 : default:
505 0 : DRM_ERROR("gpio not supported with hw i2c\n");
506 : ret = -EINVAL;
507 0 : goto done;
508 : }
509 : break;
510 : case CHIP_R300:
511 : case CHIP_R350:
512 : /* only bit 4 on r300/r350 */
513 0 : switch (rec->mask_clk_reg) {
514 : case RADEON_GPIO_VGA_DDC:
515 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
516 0 : break;
517 : case RADEON_GPIO_DVI_DDC:
518 0 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
519 0 : break;
520 : default:
521 0 : DRM_ERROR("gpio not supported with hw i2c\n");
522 : ret = -EINVAL;
523 0 : goto done;
524 : }
525 : break;
526 : case CHIP_RV350:
527 : case CHIP_RV380:
528 : case CHIP_R420:
529 : case CHIP_R423:
530 : case CHIP_RV410:
531 : case CHIP_RS400:
532 : case CHIP_RS480:
533 : /* bits 3 and 4 */
534 0 : switch (rec->mask_clk_reg) {
535 : case RADEON_GPIO_VGA_DDC:
536 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
537 0 : break;
538 : case RADEON_GPIO_DVI_DDC:
539 0 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
540 0 : break;
541 : case RADEON_GPIO_MONID:
542 0 : reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
543 0 : break;
544 : default:
545 0 : DRM_ERROR("gpio not supported with hw i2c\n");
546 : ret = -EINVAL;
547 0 : goto done;
548 : }
549 : break;
550 : default:
551 0 : DRM_ERROR("unsupported asic\n");
552 : ret = -EINVAL;
553 0 : goto done;
554 : break;
555 : }
556 : }
557 :
558 : /* check for bus probe */
559 : p = &msgs[0];
560 0 : if ((num == 1) && (p->len == 0)) {
561 0 : WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
562 : RADEON_I2C_NACK |
563 : RADEON_I2C_HALT |
564 : RADEON_I2C_SOFT_RST));
565 0 : WREG32(i2c_data, (p->addr << 1) & 0xff);
566 0 : WREG32(i2c_data, 0);
567 0 : WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
568 : (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
569 : RADEON_I2C_EN |
570 : (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
571 0 : WREG32(i2c_cntl_0, reg);
572 0 : for (k = 0; k < 32; k++) {
573 0 : udelay(10);
574 0 : tmp = RREG32(i2c_cntl_0);
575 0 : if (tmp & RADEON_I2C_GO)
576 : continue;
577 0 : tmp = RREG32(i2c_cntl_0);
578 0 : if (tmp & RADEON_I2C_DONE)
579 : break;
580 : else {
581 : DRM_DEBUG("i2c write error 0x%08x\n", tmp);
582 0 : WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
583 : ret = -EIO;
584 0 : goto done;
585 : }
586 : }
587 : goto done;
588 : }
589 :
590 0 : for (i = 0; i < num; i++) {
591 0 : p = &msgs[i];
592 0 : for (j = 0; j < p->len; j++) {
593 0 : if (p->flags & I2C_M_RD) {
594 : WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
595 : RADEON_I2C_NACK |
596 : RADEON_I2C_HALT |
597 : RADEON_I2C_SOFT_RST));
598 0 : WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);
599 0 : WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
600 : (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
601 : RADEON_I2C_EN |
602 : (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
603 0 : WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
604 0 : for (k = 0; k < 32; k++) {
605 0 : udelay(10);
606 0 : tmp = RREG32(i2c_cntl_0);
607 0 : if (tmp & RADEON_I2C_GO)
608 : continue;
609 0 : tmp = RREG32(i2c_cntl_0);
610 0 : if (tmp & RADEON_I2C_DONE)
611 : break;
612 : else {
613 : DRM_DEBUG("i2c read error 0x%08x\n", tmp);
614 0 : WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
615 : ret = -EIO;
616 0 : goto done;
617 : }
618 : }
619 0 : p->buf[j] = RREG32(i2c_data) & 0xff;
620 0 : } else {
621 : WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
622 : RADEON_I2C_NACK |
623 : RADEON_I2C_HALT |
624 : RADEON_I2C_SOFT_RST));
625 0 : WREG32(i2c_data, (p->addr << 1) & 0xff);
626 0 : WREG32(i2c_data, p->buf[j]);
627 0 : WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
628 : (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
629 : RADEON_I2C_EN |
630 : (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
631 0 : WREG32(i2c_cntl_0, reg);
632 0 : for (k = 0; k < 32; k++) {
633 0 : udelay(10);
634 0 : tmp = RREG32(i2c_cntl_0);
635 0 : if (tmp & RADEON_I2C_GO)
636 : continue;
637 0 : tmp = RREG32(i2c_cntl_0);
638 0 : if (tmp & RADEON_I2C_DONE)
639 : break;
640 : else {
641 : DRM_DEBUG("i2c write error 0x%08x\n", tmp);
642 0 : WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
643 : ret = -EIO;
644 0 : goto done;
645 : }
646 : }
647 : }
648 : }
649 : }
650 :
651 : done:
652 0 : WREG32(i2c_cntl_0, 0);
653 0 : WREG32(i2c_cntl_1, 0);
654 0 : WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
655 : RADEON_I2C_NACK |
656 : RADEON_I2C_HALT |
657 : RADEON_I2C_SOFT_RST));
658 :
659 0 : if (rdev->is_atom_bios) {
660 0 : tmp = RREG32(RADEON_BIOS_6_SCRATCH);
661 0 : tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
662 0 : WREG32(RADEON_BIOS_6_SCRATCH, tmp);
663 0 : }
664 :
665 0 : mutex_unlock(&rdev->pm.mutex);
666 0 : mutex_unlock(&rdev->dc_hw_i2c_mutex);
667 :
668 0 : return ret;
669 : }
670 :
671 : /* hw i2c engine for r5xx hardware
672 : * hw can buffer up to 15 bytes
673 : */
674 0 : static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
675 : struct i2c_msg *msgs, int num)
676 : {
677 0 : struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
678 0 : struct radeon_device *rdev = i2c->dev->dev_private;
679 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
680 : struct i2c_msg *p;
681 : int i, j, remaining, current_count, buffer_offset, ret = num;
682 : u32 prescale;
683 : u32 tmp, reg;
684 : u32 saved1, saved2;
685 :
686 0 : mutex_lock(&rdev->dc_hw_i2c_mutex);
687 : /* take the pm lock since we need a constant sclk */
688 0 : mutex_lock(&rdev->pm.mutex);
689 :
690 0 : prescale = radeon_get_i2c_prescale(rdev);
691 :
692 : /* clear gpio mask bits */
693 0 : tmp = RREG32(rec->mask_clk_reg);
694 0 : tmp &= ~rec->mask_clk_mask;
695 0 : WREG32(rec->mask_clk_reg, tmp);
696 0 : tmp = RREG32(rec->mask_clk_reg);
697 :
698 0 : tmp = RREG32(rec->mask_data_reg);
699 0 : tmp &= ~rec->mask_data_mask;
700 0 : WREG32(rec->mask_data_reg, tmp);
701 0 : tmp = RREG32(rec->mask_data_reg);
702 :
703 : /* clear pin values */
704 0 : tmp = RREG32(rec->a_clk_reg);
705 0 : tmp &= ~rec->a_clk_mask;
706 0 : WREG32(rec->a_clk_reg, tmp);
707 0 : tmp = RREG32(rec->a_clk_reg);
708 :
709 0 : tmp = RREG32(rec->a_data_reg);
710 0 : tmp &= ~rec->a_data_mask;
711 0 : WREG32(rec->a_data_reg, tmp);
712 0 : tmp = RREG32(rec->a_data_reg);
713 :
714 : /* set the pins to input */
715 0 : tmp = RREG32(rec->en_clk_reg);
716 0 : tmp &= ~rec->en_clk_mask;
717 0 : WREG32(rec->en_clk_reg, tmp);
718 0 : tmp = RREG32(rec->en_clk_reg);
719 :
720 0 : tmp = RREG32(rec->en_data_reg);
721 0 : tmp &= ~rec->en_data_mask;
722 0 : WREG32(rec->en_data_reg, tmp);
723 0 : tmp = RREG32(rec->en_data_reg);
724 :
725 : /* */
726 0 : tmp = RREG32(RADEON_BIOS_6_SCRATCH);
727 0 : WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
728 0 : saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
729 0 : saved2 = RREG32(0x494);
730 0 : WREG32(0x494, saved2 | 0x1);
731 :
732 0 : WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
733 0 : for (i = 0; i < 50; i++) {
734 0 : udelay(1);
735 0 : if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
736 : break;
737 : }
738 0 : if (i == 50) {
739 0 : DRM_ERROR("failed to get i2c bus\n");
740 : ret = -EBUSY;
741 0 : goto done;
742 : }
743 :
744 : reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
745 0 : switch (rec->mask_clk_reg) {
746 : case AVIVO_DC_GPIO_DDC1_MASK:
747 : reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
748 0 : break;
749 : case AVIVO_DC_GPIO_DDC2_MASK:
750 : reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
751 0 : break;
752 : case AVIVO_DC_GPIO_DDC3_MASK:
753 : reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
754 0 : break;
755 : default:
756 0 : DRM_ERROR("gpio not supported with hw i2c\n");
757 : ret = -EINVAL;
758 0 : goto done;
759 : }
760 :
761 : /* check for bus probe */
762 : p = &msgs[0];
763 0 : if ((num == 1) && (p->len == 0)) {
764 0 : WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
765 : AVIVO_DC_I2C_NACK |
766 : AVIVO_DC_I2C_HALT));
767 0 : WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
768 0 : udelay(1);
769 0 : WREG32(AVIVO_DC_I2C_RESET, 0);
770 :
771 0 : WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
772 0 : WREG32(AVIVO_DC_I2C_DATA, 0);
773 :
774 0 : WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
775 0 : WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
776 : AVIVO_DC_I2C_DATA_COUNT(1) |
777 : (prescale << 16)));
778 0 : WREG32(AVIVO_DC_I2C_CONTROL1, reg);
779 0 : WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
780 0 : for (j = 0; j < 200; j++) {
781 0 : udelay(50);
782 0 : tmp = RREG32(AVIVO_DC_I2C_STATUS1);
783 0 : if (tmp & AVIVO_DC_I2C_GO)
784 : continue;
785 0 : tmp = RREG32(AVIVO_DC_I2C_STATUS1);
786 0 : if (tmp & AVIVO_DC_I2C_DONE)
787 : break;
788 : else {
789 : DRM_DEBUG("i2c write error 0x%08x\n", tmp);
790 0 : WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
791 : ret = -EIO;
792 0 : goto done;
793 : }
794 : }
795 : goto done;
796 : }
797 :
798 0 : for (i = 0; i < num; i++) {
799 0 : p = &msgs[i];
800 0 : remaining = p->len;
801 : buffer_offset = 0;
802 0 : if (p->flags & I2C_M_RD) {
803 0 : while (remaining) {
804 0 : if (remaining > 15)
805 0 : current_count = 15;
806 : else
807 : current_count = remaining;
808 0 : WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
809 : AVIVO_DC_I2C_NACK |
810 : AVIVO_DC_I2C_HALT));
811 0 : WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
812 0 : udelay(1);
813 0 : WREG32(AVIVO_DC_I2C_RESET, 0);
814 :
815 0 : WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);
816 0 : WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
817 0 : WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
818 : AVIVO_DC_I2C_DATA_COUNT(current_count) |
819 : (prescale << 16)));
820 0 : WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
821 0 : WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
822 0 : for (j = 0; j < 200; j++) {
823 0 : udelay(50);
824 0 : tmp = RREG32(AVIVO_DC_I2C_STATUS1);
825 0 : if (tmp & AVIVO_DC_I2C_GO)
826 : continue;
827 0 : tmp = RREG32(AVIVO_DC_I2C_STATUS1);
828 0 : if (tmp & AVIVO_DC_I2C_DONE)
829 : break;
830 : else {
831 : DRM_DEBUG("i2c read error 0x%08x\n", tmp);
832 0 : WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
833 : ret = -EIO;
834 0 : goto done;
835 : }
836 : }
837 0 : for (j = 0; j < current_count; j++)
838 0 : p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
839 0 : remaining -= current_count;
840 0 : buffer_offset += current_count;
841 : }
842 : } else {
843 0 : while (remaining) {
844 0 : if (remaining > 15)
845 0 : current_count = 15;
846 : else
847 : current_count = remaining;
848 0 : WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
849 : AVIVO_DC_I2C_NACK |
850 : AVIVO_DC_I2C_HALT));
851 0 : WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
852 0 : udelay(1);
853 0 : WREG32(AVIVO_DC_I2C_RESET, 0);
854 :
855 0 : WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);
856 0 : for (j = 0; j < current_count; j++)
857 0 : WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
858 :
859 0 : WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
860 0 : WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
861 : AVIVO_DC_I2C_DATA_COUNT(current_count) |
862 : (prescale << 16)));
863 0 : WREG32(AVIVO_DC_I2C_CONTROL1, reg);
864 0 : WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
865 0 : for (j = 0; j < 200; j++) {
866 0 : udelay(50);
867 0 : tmp = RREG32(AVIVO_DC_I2C_STATUS1);
868 0 : if (tmp & AVIVO_DC_I2C_GO)
869 : continue;
870 0 : tmp = RREG32(AVIVO_DC_I2C_STATUS1);
871 0 : if (tmp & AVIVO_DC_I2C_DONE)
872 : break;
873 : else {
874 : DRM_DEBUG("i2c write error 0x%08x\n", tmp);
875 0 : WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
876 : ret = -EIO;
877 0 : goto done;
878 : }
879 : }
880 0 : remaining -= current_count;
881 0 : buffer_offset += current_count;
882 : }
883 : }
884 : }
885 :
886 : done:
887 0 : WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
888 : AVIVO_DC_I2C_NACK |
889 : AVIVO_DC_I2C_HALT));
890 0 : WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
891 0 : udelay(1);
892 0 : WREG32(AVIVO_DC_I2C_RESET, 0);
893 :
894 0 : WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
895 0 : WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
896 0 : WREG32(0x494, saved2);
897 0 : tmp = RREG32(RADEON_BIOS_6_SCRATCH);
898 0 : tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
899 0 : WREG32(RADEON_BIOS_6_SCRATCH, tmp);
900 :
901 0 : mutex_unlock(&rdev->pm.mutex);
902 0 : mutex_unlock(&rdev->dc_hw_i2c_mutex);
903 :
904 0 : return ret;
905 : }
906 :
907 0 : static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
908 : struct i2c_msg *msgs, int num)
909 : {
910 0 : struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
911 0 : struct radeon_device *rdev = i2c->dev->dev_private;
912 0 : struct radeon_i2c_bus_rec *rec = &i2c->rec;
913 : int ret = 0;
914 :
915 0 : mutex_lock(&i2c->mutex);
916 :
917 0 : switch (rdev->family) {
918 : case CHIP_R100:
919 : case CHIP_RV100:
920 : case CHIP_RS100:
921 : case CHIP_RV200:
922 : case CHIP_RS200:
923 : case CHIP_R200:
924 : case CHIP_RV250:
925 : case CHIP_RS300:
926 : case CHIP_RV280:
927 : case CHIP_R300:
928 : case CHIP_R350:
929 : case CHIP_RV350:
930 : case CHIP_RV380:
931 : case CHIP_R420:
932 : case CHIP_R423:
933 : case CHIP_RV410:
934 : case CHIP_RS400:
935 : case CHIP_RS480:
936 0 : ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
937 0 : break;
938 : case CHIP_RS600:
939 : case CHIP_RS690:
940 : case CHIP_RS740:
941 : /* XXX fill in hw i2c implementation */
942 : break;
943 : case CHIP_RV515:
944 : case CHIP_R520:
945 : case CHIP_RV530:
946 : case CHIP_RV560:
947 : case CHIP_RV570:
948 : case CHIP_R580:
949 0 : if (rec->mm_i2c)
950 0 : ret = r100_hw_i2c_xfer(i2c_adap, msgs, num);
951 : else
952 0 : ret = r500_hw_i2c_xfer(i2c_adap, msgs, num);
953 : break;
954 : case CHIP_R600:
955 : case CHIP_RV610:
956 : case CHIP_RV630:
957 : case CHIP_RV670:
958 : /* XXX fill in hw i2c implementation */
959 : break;
960 : case CHIP_RV620:
961 : case CHIP_RV635:
962 : case CHIP_RS780:
963 : case CHIP_RS880:
964 : case CHIP_RV770:
965 : case CHIP_RV730:
966 : case CHIP_RV710:
967 : case CHIP_RV740:
968 : /* XXX fill in hw i2c implementation */
969 : break;
970 : case CHIP_CEDAR:
971 : case CHIP_REDWOOD:
972 : case CHIP_JUNIPER:
973 : case CHIP_CYPRESS:
974 : case CHIP_HEMLOCK:
975 : /* XXX fill in hw i2c implementation */
976 : break;
977 : default:
978 0 : DRM_ERROR("i2c: unhandled radeon chip\n");
979 : ret = -EIO;
980 0 : break;
981 : }
982 :
983 0 : mutex_unlock(&i2c->mutex);
984 :
985 0 : return ret;
986 : }
987 :
988 0 : static u32 radeon_hw_i2c_func(struct i2c_adapter *adap)
989 : {
990 0 : return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
991 : }
992 :
993 : static const struct i2c_algorithm radeon_i2c_algo = {
994 : .master_xfer = radeon_hw_i2c_xfer,
995 : .functionality = radeon_hw_i2c_func,
996 : };
997 :
998 : static const struct i2c_algorithm radeon_atom_i2c_algo = {
999 : .master_xfer = radeon_atom_hw_i2c_xfer,
1000 : .functionality = radeon_atom_hw_i2c_func,
1001 : };
1002 :
1003 0 : struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
1004 : struct radeon_i2c_bus_rec *rec,
1005 : const char *name)
1006 : {
1007 0 : struct radeon_device *rdev = dev->dev_private;
1008 : struct radeon_i2c_chan *i2c;
1009 : int ret;
1010 :
1011 : /* don't add the mm_i2c bus unless hw_i2c is enabled */
1012 0 : if (rec->mm_i2c && (radeon_hw_i2c == 0))
1013 0 : return NULL;
1014 :
1015 0 : i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL);
1016 0 : if (i2c == NULL)
1017 0 : return NULL;
1018 :
1019 0 : i2c->rec = *rec;
1020 : #ifdef __linux__
1021 : i2c->adapter.owner = THIS_MODULE;
1022 : i2c->adapter.class = I2C_CLASS_DDC;
1023 : i2c->adapter.dev.parent = &dev->pdev->dev;
1024 : #endif
1025 0 : i2c->dev = dev;
1026 0 : i2c_set_adapdata(&i2c->adapter, i2c);
1027 0 : rw_init(&i2c->mutex, "riic");
1028 0 : if (rec->mm_i2c ||
1029 0 : (rec->hw_capable &&
1030 0 : radeon_hw_i2c &&
1031 0 : ((rdev->family <= CHIP_RS480) ||
1032 0 : ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
1033 : /* set the radeon hw i2c adapter */
1034 0 : snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1035 : "Radeon i2c hw bus %s", name);
1036 0 : i2c->adapter.algo = &radeon_i2c_algo;
1037 : ret = i2c_add_adapter(&i2c->adapter);
1038 0 : if (ret) {
1039 0 : DRM_ERROR("Failed to register hw i2c %s\n", name);
1040 0 : goto out_free;
1041 : }
1042 0 : } else if (rec->hw_capable &&
1043 0 : radeon_hw_i2c &&
1044 0 : ASIC_IS_DCE3(rdev)) {
1045 : /* hw i2c using atom */
1046 0 : snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1047 : "Radeon i2c hw bus %s", name);
1048 0 : i2c->adapter.algo = &radeon_atom_i2c_algo;
1049 : ret = i2c_add_adapter(&i2c->adapter);
1050 0 : if (ret) {
1051 0 : DRM_ERROR("Failed to register hw i2c %s\n", name);
1052 0 : goto out_free;
1053 : }
1054 : } else {
1055 : /* set the radeon bit adapter */
1056 0 : snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1057 : "Radeon i2c bit bus %s", name);
1058 0 : i2c->adapter.algo_data = &i2c->bit;
1059 : #ifdef notyet
1060 : i2c->bit.pre_xfer = pre_xfer;
1061 : i2c->bit.post_xfer = post_xfer;
1062 : i2c->bit.setsda = set_data;
1063 : i2c->bit.setscl = set_clock;
1064 : i2c->bit.getsda = get_data;
1065 : i2c->bit.getscl = get_clock;
1066 : i2c->bit.udelay = 10;
1067 : i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
1068 : i2c->bit.data = i2c;
1069 : #else
1070 0 : i2c->bit.ic.ic_cookie = i2c;
1071 0 : i2c->bit.ic.ic_acquire_bus = radeon_acquire_bus;
1072 0 : i2c->bit.ic.ic_release_bus = radeon_release_bus;
1073 0 : i2c->bit.ic.ic_send_start = radeon_send_start;
1074 0 : i2c->bit.ic.ic_send_stop = radeon_send_stop;
1075 0 : i2c->bit.ic.ic_initiate_xfer = radeon_initiate_xfer;
1076 0 : i2c->bit.ic.ic_read_byte = radeon_read_byte;
1077 0 : i2c->bit.ic.ic_write_byte = radeon_write_byte;
1078 : #endif
1079 0 : ret = i2c_bit_add_bus(&i2c->adapter);
1080 0 : if (ret) {
1081 0 : DRM_ERROR("Failed to register bit i2c %s\n", name);
1082 0 : goto out_free;
1083 : }
1084 : }
1085 :
1086 0 : return i2c;
1087 : out_free:
1088 0 : kfree(i2c);
1089 0 : return NULL;
1090 :
1091 0 : }
1092 :
1093 0 : void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
1094 : {
1095 0 : if (!i2c)
1096 : return;
1097 : i2c_del_adapter(&i2c->adapter);
1098 0 : if (i2c->has_aux)
1099 0 : drm_dp_aux_unregister(&i2c->aux);
1100 0 : kfree(i2c);
1101 0 : }
1102 :
1103 : /* Add the default buses */
1104 0 : void radeon_i2c_init(struct radeon_device *rdev)
1105 : {
1106 0 : if (radeon_hw_i2c)
1107 : DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
1108 :
1109 0 : if (rdev->is_atom_bios)
1110 0 : radeon_atombios_i2c_init(rdev);
1111 : else
1112 0 : radeon_combios_i2c_init(rdev);
1113 0 : }
1114 :
1115 : /* remove all the buses */
1116 0 : void radeon_i2c_fini(struct radeon_device *rdev)
1117 : {
1118 : int i;
1119 :
1120 0 : for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1121 0 : if (rdev->i2c_bus[i]) {
1122 0 : radeon_i2c_destroy(rdev->i2c_bus[i]);
1123 0 : rdev->i2c_bus[i] = NULL;
1124 0 : }
1125 : }
1126 0 : }
1127 :
1128 : /* Add additional buses */
1129 0 : void radeon_i2c_add(struct radeon_device *rdev,
1130 : struct radeon_i2c_bus_rec *rec,
1131 : const char *name)
1132 : {
1133 0 : struct drm_device *dev = rdev->ddev;
1134 : int i;
1135 :
1136 0 : for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1137 0 : if (!rdev->i2c_bus[i]) {
1138 0 : rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1139 0 : return;
1140 : }
1141 : }
1142 0 : }
1143 :
1144 : /* looks up bus based on id */
1145 0 : struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1146 : struct radeon_i2c_bus_rec *i2c_bus)
1147 : {
1148 : int i;
1149 :
1150 0 : for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1151 0 : if (rdev->i2c_bus[i] &&
1152 0 : (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1153 0 : return rdev->i2c_bus[i];
1154 : }
1155 : }
1156 0 : return NULL;
1157 0 : }
1158 :
1159 0 : void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1160 : u8 slave_addr,
1161 : u8 addr,
1162 : u8 *val)
1163 : {
1164 0 : u8 out_buf[2];
1165 0 : u8 in_buf[2];
1166 0 : struct i2c_msg msgs[] = {
1167 0 : {
1168 0 : .addr = slave_addr,
1169 : .flags = 0,
1170 : .len = 1,
1171 0 : .buf = out_buf,
1172 : },
1173 0 : {
1174 : .addr = slave_addr,
1175 : .flags = I2C_M_RD,
1176 : .len = 1,
1177 0 : .buf = in_buf,
1178 : }
1179 : };
1180 :
1181 0 : out_buf[0] = addr;
1182 0 : out_buf[1] = 0;
1183 :
1184 0 : if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
1185 0 : *val = in_buf[0];
1186 : DRM_DEBUG("val = 0x%02x\n", *val);
1187 0 : } else {
1188 : DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1189 : addr, *val);
1190 : }
1191 0 : }
1192 :
1193 0 : void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1194 : u8 slave_addr,
1195 : u8 addr,
1196 : u8 val)
1197 : {
1198 0 : uint8_t out_buf[2];
1199 0 : struct i2c_msg msg = {
1200 0 : .addr = slave_addr,
1201 : .flags = 0,
1202 : .len = 2,
1203 0 : .buf = out_buf,
1204 : };
1205 :
1206 0 : out_buf[0] = addr;
1207 0 : out_buf[1] = val;
1208 :
1209 0 : if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
1210 : DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1211 : addr, val);
1212 0 : }
1213 :
1214 : /* ddc router switching */
1215 0 : void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1216 : {
1217 0 : u8 val;
1218 :
1219 0 : if (!radeon_connector->router.ddc_valid)
1220 0 : return;
1221 :
1222 0 : if (!radeon_connector->router_bus)
1223 0 : return;
1224 :
1225 0 : radeon_i2c_get_byte(radeon_connector->router_bus,
1226 0 : radeon_connector->router.i2c_addr,
1227 : 0x3, &val);
1228 0 : val &= ~radeon_connector->router.ddc_mux_control_pin;
1229 0 : radeon_i2c_put_byte(radeon_connector->router_bus,
1230 0 : radeon_connector->router.i2c_addr,
1231 : 0x3, val);
1232 0 : radeon_i2c_get_byte(radeon_connector->router_bus,
1233 0 : radeon_connector->router.i2c_addr,
1234 : 0x1, &val);
1235 0 : val &= ~radeon_connector->router.ddc_mux_control_pin;
1236 0 : val |= radeon_connector->router.ddc_mux_state;
1237 0 : radeon_i2c_put_byte(radeon_connector->router_bus,
1238 0 : radeon_connector->router.i2c_addr,
1239 : 0x1, val);
1240 0 : }
1241 :
1242 : /* clock/data router switching */
1243 0 : void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1244 : {
1245 0 : u8 val;
1246 :
1247 0 : if (!radeon_connector->router.cd_valid)
1248 0 : return;
1249 :
1250 0 : if (!radeon_connector->router_bus)
1251 0 : return;
1252 :
1253 0 : radeon_i2c_get_byte(radeon_connector->router_bus,
1254 0 : radeon_connector->router.i2c_addr,
1255 : 0x3, &val);
1256 0 : val &= ~radeon_connector->router.cd_mux_control_pin;
1257 0 : radeon_i2c_put_byte(radeon_connector->router_bus,
1258 0 : radeon_connector->router.i2c_addr,
1259 : 0x3, val);
1260 0 : radeon_i2c_get_byte(radeon_connector->router_bus,
1261 0 : radeon_connector->router.i2c_addr,
1262 : 0x1, &val);
1263 0 : val &= ~radeon_connector->router.cd_mux_control_pin;
1264 0 : val |= radeon_connector->router.cd_mux_state;
1265 0 : radeon_i2c_put_byte(radeon_connector->router_bus,
1266 0 : radeon_connector->router.i2c_addr,
1267 : 0x1, val);
1268 0 : }
1269 :
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