Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #include <dev/pci/drm/drmP.h>
29 : #include <dev/pci/drm/drm_fb_helper.h>
30 : #include "radeon.h"
31 : #include <dev/pci/drm/radeon_drm.h>
32 : #include "radeon_asic.h"
33 :
34 : #include "radeon_kfd.h"
35 :
36 : #if defined(CONFIG_VGA_SWITCHEROO)
37 : bool radeon_has_atpx(void);
38 : #else
39 0 : static inline bool radeon_has_atpx(void) { return false; }
40 : #endif
41 :
42 : #include "vga.h"
43 :
44 : #if NVGA > 0
45 : extern int vga_console_attached;
46 : #endif
47 :
48 : #ifdef __amd64__
49 : #include "efifb.h"
50 : #include <machine/biosvar.h>
51 : #endif
52 :
53 : #if NEFIFB > 0
54 : #include <machine/efifbvar.h>
55 : #endif
56 :
57 : int radeondrm_probe(struct device *, void *, void *);
58 : void radeondrm_attach_kms(struct device *, struct device *, void *);
59 : int radeondrm_detach_kms(struct device *, int);
60 : int radeondrm_activate_kms(struct device *, int);
61 : void radeondrm_attachhook(struct device *);
62 : int radeondrm_forcedetach(struct radeon_device *);
63 :
64 : bool radeon_msi_ok(struct radeon_device *);
65 : irqreturn_t radeon_driver_irq_handler_kms(void *);
66 :
67 : extern const struct drm_pcidev radeondrm_pciidlist[];
68 : extern struct drm_driver kms_driver;
69 : const struct drm_ioctl_desc radeon_ioctls_kms[];
70 : extern int radeon_max_kms_ioctl;
71 :
72 : /*
73 : * set if the mountroot hook has a fatal error
74 : * such as not being able to find the firmware on newer cards
75 : */
76 : int radeon_fatal_error;
77 :
78 : struct cfattach radeondrm_ca = {
79 : sizeof (struct radeon_device), radeondrm_probe, radeondrm_attach_kms,
80 : radeondrm_detach_kms, radeondrm_activate_kms
81 : };
82 :
83 : struct cfdriver radeondrm_cd = {
84 : NULL, "radeondrm", DV_DULL
85 : };
86 :
87 : int
88 0 : radeondrm_probe(struct device *parent, void *match, void *aux)
89 : {
90 0 : if (radeon_fatal_error)
91 0 : return 0;
92 0 : if (drm_pciprobe(aux, radeondrm_pciidlist))
93 0 : return 20;
94 0 : return 0;
95 0 : }
96 :
97 : /**
98 : * radeon_driver_unload_kms - Main unload function for KMS.
99 : *
100 : * @dev: drm dev pointer
101 : *
102 : * This is the main unload function for KMS (all asics).
103 : * It calls radeon_modeset_fini() to tear down the
104 : * displays, and radeon_device_fini() to tear down
105 : * the rest of the device (CP, writeback, etc.).
106 : * Returns 0 on success.
107 : */
108 : #ifdef __linux__
109 : int radeon_driver_unload_kms(struct drm_device *dev)
110 : {
111 : struct radeon_device *rdev = dev->dev_private;
112 :
113 : if (rdev == NULL)
114 : return 0;
115 :
116 : if (rdev->rmmio == NULL)
117 : goto done_free;
118 :
119 : pm_runtime_get_sync(dev->dev);
120 :
121 : radeon_kfd_device_fini(rdev);
122 :
123 : radeon_acpi_fini(rdev);
124 :
125 : radeon_modeset_fini(rdev);
126 : radeon_device_fini(rdev);
127 :
128 : done_free:
129 : kfree(rdev);
130 : dev->dev_private = NULL;
131 : return 0;
132 : }
133 : #else
134 : int
135 0 : radeondrm_detach_kms(struct device *self, int flags)
136 : {
137 0 : struct radeon_device *rdev = (struct radeon_device *)self;
138 :
139 0 : if (rdev == NULL)
140 0 : return 0;
141 :
142 0 : pci_intr_disestablish(rdev->pc, rdev->irqh);
143 :
144 : #ifdef notyet
145 : pm_runtime_get_sync(dev->dev);
146 :
147 : radeon_kfd_device_fini(rdev);
148 : #endif
149 :
150 0 : radeon_acpi_fini(rdev);
151 :
152 0 : radeon_modeset_fini(rdev);
153 0 : radeon_device_fini(rdev);
154 :
155 0 : if (rdev->ddev != NULL) {
156 0 : config_detach((struct device *)rdev->ddev, flags);
157 0 : rdev->ddev = NULL;
158 0 : }
159 :
160 0 : return 0;
161 0 : }
162 : #endif
163 :
164 : void radeondrm_burner(void *, u_int, u_int);
165 : int radeondrm_wsioctl(void *, u_long, caddr_t, int, struct proc *);
166 : paddr_t radeondrm_wsmmap(void *, off_t, int);
167 : int radeondrm_alloc_screen(void *, const struct wsscreen_descr *,
168 : void **, int *, int *, long *);
169 : void radeondrm_free_screen(void *, void *);
170 : int radeondrm_show_screen(void *, void *, int,
171 : void (*)(void *, int, int), void *);
172 : void radeondrm_doswitch(void *);
173 : void radeondrm_enter_ddb(void *, void *);
174 : #ifdef __sparc64__
175 : void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t);
176 : #endif
177 :
178 : struct wsscreen_descr radeondrm_stdscreen = {
179 : "std",
180 : 0, 0,
181 : 0,
182 : 0, 0,
183 : WSSCREEN_UNDERLINE | WSSCREEN_HILIT |
184 : WSSCREEN_REVERSE | WSSCREEN_WSCOLORS
185 : };
186 :
187 : const struct wsscreen_descr *radeondrm_scrlist[] = {
188 : &radeondrm_stdscreen,
189 : };
190 :
191 : struct wsscreen_list radeondrm_screenlist = {
192 : nitems(radeondrm_scrlist), radeondrm_scrlist
193 : };
194 :
195 : struct wsdisplay_accessops radeondrm_accessops = {
196 : .ioctl = radeondrm_wsioctl,
197 : .mmap = radeondrm_wsmmap,
198 : .alloc_screen = radeondrm_alloc_screen,
199 : .free_screen = radeondrm_free_screen,
200 : .show_screen = radeondrm_show_screen,
201 : .enter_ddb = radeondrm_enter_ddb,
202 : .getchar = rasops_getchar,
203 : .load_font = rasops_load_font,
204 : .list_font = rasops_list_font,
205 : .scrollback = rasops_scrollback,
206 : .burn_screen = radeondrm_burner
207 : };
208 :
209 : int
210 0 : radeondrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p)
211 : {
212 0 : struct rasops_info *ri = v;
213 : struct wsdisplay_fbinfo *wdf;
214 :
215 0 : switch (cmd) {
216 : case WSDISPLAYIO_GTYPE:
217 0 : *(int *)data = WSDISPLAY_TYPE_RADEONDRM;
218 0 : return 0;
219 : case WSDISPLAYIO_GINFO:
220 0 : wdf = (struct wsdisplay_fbinfo *)data;
221 0 : wdf->width = ri->ri_width;
222 0 : wdf->height = ri->ri_height;
223 0 : wdf->depth = ri->ri_depth;
224 0 : wdf->cmsize = 0;
225 0 : return 0;
226 : default:
227 0 : return -1;
228 : }
229 0 : }
230 :
231 : paddr_t
232 0 : radeondrm_wsmmap(void *v, off_t off, int prot)
233 : {
234 0 : return (-1);
235 : }
236 :
237 : int
238 0 : radeondrm_alloc_screen(void *v, const struct wsscreen_descr *type,
239 : void **cookiep, int *curxp, int *curyp, long *attrp)
240 : {
241 0 : return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp);
242 : }
243 :
244 : void
245 0 : radeondrm_free_screen(void *v, void *cookie)
246 : {
247 0 : return rasops_free_screen(v, cookie);
248 : }
249 :
250 : int
251 0 : radeondrm_show_screen(void *v, void *cookie, int waitok,
252 : void (*cb)(void *, int, int), void *cbarg)
253 : {
254 0 : struct rasops_info *ri = v;
255 0 : struct radeon_device *rdev = ri->ri_hw;
256 :
257 0 : if (cookie == ri->ri_active)
258 0 : return (0);
259 :
260 0 : rdev->switchcb = cb;
261 0 : rdev->switchcbarg = cbarg;
262 0 : rdev->switchcookie = cookie;
263 0 : if (cb) {
264 0 : task_add(systq, &rdev->switchtask);
265 0 : return (EAGAIN);
266 : }
267 :
268 0 : radeondrm_doswitch(v);
269 :
270 0 : return (0);
271 0 : }
272 :
273 : void
274 0 : radeondrm_doswitch(void *v)
275 : {
276 0 : struct rasops_info *ri = v;
277 0 : struct radeon_device *rdev = ri->ri_hw;
278 : struct radeon_crtc *radeon_crtc;
279 : int i, crtc;
280 :
281 0 : rasops_show_screen(ri, rdev->switchcookie, 0, NULL, NULL);
282 0 : for (crtc = 0; crtc < rdev->num_crtc; crtc++) {
283 0 : for (i = 0; i < 256; i++) {
284 0 : radeon_crtc = rdev->mode_info.crtcs[crtc];
285 0 : radeon_crtc->lut_r[i] = rasops_cmap[3 * i] << 2;
286 0 : radeon_crtc->lut_g[i] = rasops_cmap[(3 * i) + 1] << 2;
287 0 : radeon_crtc->lut_b[i] = rasops_cmap[(3 * i) + 2] << 2;
288 : }
289 : }
290 : #ifdef __sparc64__
291 : fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor);
292 : #endif
293 0 : drm_fb_helper_restore_fbdev_mode_unlocked((void *)rdev->mode_info.rfbdev);
294 :
295 0 : if (rdev->switchcb)
296 0 : (rdev->switchcb)(rdev->switchcbarg, 0, 0);
297 0 : }
298 :
299 : void
300 0 : radeondrm_enter_ddb(void *v, void *cookie)
301 : {
302 0 : struct rasops_info *ri = v;
303 0 : struct radeon_device *rdev = ri->ri_hw;
304 0 : struct drm_fb_helper *fb_helper = (void *)rdev->mode_info.rfbdev;
305 :
306 0 : if (cookie == ri->ri_active)
307 0 : return;
308 :
309 0 : rasops_show_screen(ri, cookie, 0, NULL, NULL);
310 0 : drm_fb_helper_debug_enter(fb_helper->fbdev);
311 0 : }
312 :
313 : #ifdef __sparc64__
314 : void
315 : radeondrm_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b)
316 : {
317 : struct sunfb *sf = v;
318 : struct radeon_device *rdev = sf->sf_ro.ri_hw;
319 : struct drm_fb_helper *fb_helper = (void *)rdev->mode_info.rfbdev;
320 : u_int16_t red, green, blue;
321 : struct drm_crtc *crtc;
322 : int i;
323 :
324 : for (i = 0; i < fb_helper->crtc_count; i++) {
325 : crtc = fb_helper->crtc_info[i].mode_set.crtc;
326 :
327 : red = (r << 8) | r;
328 : green = (g << 8) | g;
329 : blue = (b << 8) | b;
330 : fb_helper->funcs->gamma_set(crtc, red, green, blue, index);
331 : }
332 : }
333 : #endif
334 :
335 : #ifdef __linux__
336 : /**
337 : * radeon_driver_load_kms - Main load function for KMS.
338 : *
339 : * @dev: drm dev pointer
340 : * @flags: device flags
341 : *
342 : * This is the main load function for KMS (all asics).
343 : * It calls radeon_device_init() to set up the non-display
344 : * parts of the chip (asic init, CP, writeback, etc.), and
345 : * radeon_modeset_init() to set up the display parts
346 : * (crtcs, encoders, hotplug detect, etc.).
347 : * Returns 0 on success, error on failure.
348 : */
349 : int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
350 : {
351 : struct radeon_device *rdev;
352 : int r, acpi_status;
353 :
354 : rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
355 : if (rdev == NULL) {
356 : return -ENOMEM;
357 : }
358 : dev->dev_private = (void *)rdev;
359 :
360 : /* update BUS flag */
361 : if (drm_pci_device_is_agp(dev)) {
362 : flags |= RADEON_IS_AGP;
363 : } else if (pci_is_pcie(dev->pdev)) {
364 : flags |= RADEON_IS_PCIE;
365 : } else {
366 : flags |= RADEON_IS_PCI;
367 : }
368 :
369 : if ((radeon_runtime_pm != 0) &&
370 : radeon_has_atpx() &&
371 : ((flags & RADEON_IS_IGP) == 0))
372 : flags |= RADEON_IS_PX;
373 :
374 : /* radeon_device_init should report only fatal error
375 : * like memory allocation failure or iomapping failure,
376 : * or memory manager initialization failure, it must
377 : * properly initialize the GPU MC controller and permit
378 : * VRAM allocation
379 : */
380 : r = radeon_device_init(rdev, dev, dev->pdev, flags);
381 : if (r) {
382 : dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
383 : goto out;
384 : }
385 :
386 : /* Again modeset_init should fail only on fatal error
387 : * otherwise it should provide enough functionalities
388 : * for shadowfb to run
389 : */
390 : r = radeon_modeset_init(rdev);
391 : if (r)
392 : dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
393 :
394 : /* Call ACPI methods: require modeset init
395 : * but failure is not fatal
396 : */
397 : if (!r) {
398 : acpi_status = radeon_acpi_init(rdev);
399 : if (acpi_status)
400 : dev_dbg(&dev->pdev->dev,
401 : "Error during ACPI methods call\n");
402 : }
403 :
404 : #ifdef notyet
405 : radeon_kfd_device_probe(rdev);
406 : radeon_kfd_device_init(rdev);
407 : #endif
408 :
409 : if (radeon_is_px(dev)) {
410 : pm_runtime_use_autosuspend(dev->dev);
411 : pm_runtime_set_autosuspend_delay(dev->dev, 5000);
412 : pm_runtime_set_active(dev->dev);
413 : pm_runtime_allow(dev->dev);
414 : pm_runtime_mark_last_busy(dev->dev);
415 : pm_runtime_put_autosuspend(dev->dev);
416 : }
417 :
418 : out:
419 : if (r)
420 : radeon_driver_unload_kms(dev);
421 :
422 :
423 : return r;
424 : }
425 : #endif
426 :
427 : void
428 0 : radeondrm_attach_kms(struct device *parent, struct device *self, void *aux)
429 : {
430 0 : struct radeon_device *rdev = (struct radeon_device *)self;
431 : struct drm_device *dev;
432 0 : struct pci_attach_args *pa = aux;
433 : const struct drm_pcidev *id_entry;
434 : int is_agp;
435 : pcireg_t type;
436 : int i;
437 : uint8_t rmmio_bar;
438 : paddr_t fb_aper;
439 : #if !defined(__sparc64__)
440 : pcireg_t addr, mask;
441 : int s;
442 : #endif
443 :
444 : #if defined(__sparc64__) || defined(__macppc__)
445 : extern int fbnode;
446 : #endif
447 :
448 0 : id_entry = drm_find_description(PCI_VENDOR(pa->pa_id),
449 0 : PCI_PRODUCT(pa->pa_id), radeondrm_pciidlist);
450 0 : rdev->flags = id_entry->driver_data;
451 0 : rdev->family = rdev->flags & RADEON_FAMILY_MASK;
452 0 : rdev->pc = pa->pa_pc;
453 0 : rdev->pa_tag = pa->pa_tag;
454 0 : rdev->iot = pa->pa_iot;
455 0 : rdev->memt = pa->pa_memt;
456 0 : rdev->dmat = pa->pa_dmat;
457 :
458 : #if defined(__sparc64__) || defined(__macppc__)
459 : if (fbnode == PCITAG_NODE(rdev->pa_tag))
460 : rdev->console = 1;
461 : #else
462 0 : if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY &&
463 0 : PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA &&
464 0 : (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
465 0 : & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
466 0 : == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) {
467 0 : rdev->console = 1;
468 : #if NVGA > 0
469 0 : vga_console_attached = 1;
470 : #endif
471 0 : }
472 : #if NEFIFB > 0
473 0 : if (efifb_is_console(pa)) {
474 0 : rdev->console = 1;
475 0 : efifb_cndetach();
476 0 : }
477 : #endif
478 : #endif
479 :
480 : #define RADEON_PCI_MEM 0x10
481 :
482 0 : type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM);
483 0 : if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
484 0 : pci_mapreg_info(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM,
485 0 : type, &rdev->fb_aper_offset, &rdev->fb_aper_size, NULL)) {
486 0 : printf(": can't get frambuffer info\n");
487 0 : return;
488 : }
489 : #if !defined(__sparc64__)
490 0 : if (rdev->fb_aper_offset == 0) {
491 : bus_size_t start, end;
492 0 : bus_addr_t base;
493 :
494 0 : start = max(PCI_MEM_START, pa->pa_memex->ex_start);
495 0 : end = min(PCI_MEM_END, pa->pa_memex->ex_end);
496 0 : if (pa->pa_memex == NULL ||
497 0 : extent_alloc_subregion(pa->pa_memex, start, end,
498 0 : rdev->fb_aper_size, rdev->fb_aper_size, 0, 0, 0, &base)) {
499 0 : printf(": can't reserve framebuffer space\n");
500 0 : return;
501 : }
502 0 : pci_conf_write(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, base);
503 0 : if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT)
504 0 : pci_conf_write(pa->pa_pc, pa->pa_tag,
505 0 : RADEON_PCI_MEM + 4, (uint64_t)base >> 32);
506 0 : rdev->fb_aper_offset = base;
507 0 : }
508 : #endif
509 :
510 0 : for (i = PCI_MAPREG_START; i < PCI_MAPREG_END ; i+= 4) {
511 0 : type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i);
512 0 : if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_IO)
513 : continue;
514 0 : if (pci_mapreg_map(pa, i, type, 0, NULL,
515 0 : &rdev->rio_mem, NULL, &rdev->rio_mem_size, 0)) {
516 0 : printf(": can't map rio space\n");
517 0 : return;
518 : }
519 :
520 0 : if (type & PCI_MAPREG_MEM_TYPE_64BIT)
521 0 : i += 4;
522 : }
523 :
524 0 : if (rdev->family >= CHIP_BONAIRE) {
525 0 : type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18);
526 0 : if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
527 0 : pci_mapreg_map(pa, 0x18, type, 0, NULL,
528 0 : &rdev->doorbell.bsh, &rdev->doorbell.base,
529 0 : &rdev->doorbell.size, 0)) {
530 0 : printf(": can't map doorbell space\n");
531 0 : return;
532 : }
533 : }
534 :
535 0 : if (rdev->family >= CHIP_BONAIRE)
536 0 : rmmio_bar = 0x24;
537 : else
538 : rmmio_bar = 0x18;
539 :
540 0 : type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar);
541 0 : if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM ||
542 0 : pci_mapreg_map(pa, rmmio_bar, type, 0, NULL,
543 0 : &rdev->rmmio_bsh, &rdev->rmmio_base, &rdev->rmmio_size, 0)) {
544 0 : printf(": can't map rmmio space\n");
545 0 : return;
546 : }
547 :
548 : #if !defined(__sparc64__)
549 : /*
550 : * Make sure we have a base address for the ROM such that we
551 : * can map it later.
552 : */
553 0 : s = splhigh();
554 0 : addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
555 0 : pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE);
556 0 : mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
557 0 : pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr);
558 0 : splx(s);
559 :
560 0 : if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) {
561 : bus_size_t size, start, end;
562 0 : bus_addr_t base;
563 :
564 0 : size = PCI_ROM_SIZE(mask);
565 0 : start = max(PCI_MEM_START, pa->pa_memex->ex_start);
566 0 : end = min(PCI_MEM_END, pa->pa_memex->ex_end);
567 0 : if (extent_alloc_subregion(pa->pa_memex, start, end, size,
568 0 : size, 0, 0, 0, &base) == 0)
569 0 : pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base);
570 0 : }
571 : #endif
572 :
573 : #ifdef notyet
574 : mtx_init(&rdev->swi_lock, IPL_TTY);
575 : #endif
576 :
577 : /* update BUS flag */
578 0 : if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL)) {
579 0 : rdev->flags |= RADEON_IS_AGP;
580 0 : } else if (pci_get_capability(pa->pa_pc, pa->pa_tag,
581 : PCI_CAP_PCIEXPRESS, NULL, NULL)) {
582 0 : rdev->flags |= RADEON_IS_PCIE;
583 0 : } else {
584 0 : rdev->flags |= RADEON_IS_PCI;
585 : }
586 :
587 0 : if ((radeon_runtime_pm != 0) &&
588 0 : radeon_has_atpx() &&
589 0 : ((rdev->flags & RADEON_IS_IGP) == 0))
590 0 : rdev->flags |= RADEON_IS_PX;
591 :
592 : DRM_DEBUG("%s card detected\n",
593 : ((rdev->flags & RADEON_IS_AGP) ? "AGP" :
594 : (((rdev->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
595 :
596 0 : is_agp = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
597 : NULL, NULL);
598 :
599 0 : printf("\n");
600 :
601 0 : kms_driver.num_ioctls = radeon_max_kms_ioctl;
602 0 : kms_driver.driver_features |= DRIVER_MODESET;
603 :
604 0 : dev = (struct drm_device *)drm_attach_pci(&kms_driver, pa, is_agp,
605 0 : rdev->console, self);
606 0 : rdev->ddev = dev;
607 0 : rdev->pdev = dev->pdev;
608 :
609 0 : if (!radeon_msi_ok(rdev))
610 0 : pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED;
611 :
612 0 : rdev->msi_enabled = 0;
613 0 : if (pci_intr_map_msi(pa, &rdev->intrh) == 0)
614 0 : rdev->msi_enabled = 1;
615 0 : else if (pci_intr_map(pa, &rdev->intrh) != 0) {
616 0 : printf(": couldn't map interrupt\n");
617 0 : return;
618 : }
619 0 : printf("%s: %s\n", rdev->self.dv_xname,
620 0 : pci_intr_string(pa->pa_pc, rdev->intrh));
621 :
622 0 : rdev->irqh = pci_intr_establish(pa->pa_pc, rdev->intrh, IPL_TTY,
623 0 : radeon_driver_irq_handler_kms, rdev->ddev, rdev->self.dv_xname);
624 0 : if (rdev->irqh == NULL) {
625 0 : printf("%s: couldn't establish interrupt\n",
626 : rdev->self.dv_xname);
627 0 : return;
628 : }
629 0 : rdev->pdev->irq = -1;
630 :
631 : #ifdef __sparc64__
632 : {
633 : struct rasops_info *ri;
634 : int node, console;
635 :
636 : node = PCITAG_NODE(pa->pa_tag);
637 : console = (fbnode == node);
638 :
639 : fb_setsize(&rdev->sf, 8, 1152, 900, node, 0);
640 :
641 : /*
642 : * The firmware sets up the framebuffer such that at starts at
643 : * an offset from the start of video memory.
644 : */
645 : rdev->fb_offset =
646 : bus_space_read_4(rdev->memt, rdev->rmmio_bsh, RADEON_CRTC_OFFSET);
647 : if (bus_space_map(rdev->memt, rdev->fb_aper_offset + rdev->fb_offset,
648 : rdev->sf.sf_fbsize, BUS_SPACE_MAP_LINEAR, &rdev->memh)) {
649 : printf("%s: can't map video memory\n", rdev->self.dv_xname);
650 : return;
651 : }
652 :
653 : ri = &rdev->sf.sf_ro;
654 : ri->ri_bits = bus_space_vaddr(rdev->memt, rdev->memh);
655 : ri->ri_hw = rdev;
656 : ri->ri_updatecursor = NULL;
657 :
658 : fbwscons_init(&rdev->sf, RI_VCONS | RI_WRONLY | RI_BSWAP, console);
659 : if (console)
660 : fbwscons_console_init(&rdev->sf, -1);
661 : }
662 : #endif
663 :
664 0 : fb_aper = bus_space_mmap(rdev->memt, rdev->fb_aper_offset, 0, 0, 0);
665 0 : if (fb_aper != -1)
666 0 : rasops_claim_framebuffer(fb_aper, rdev->fb_aper_size, self);
667 :
668 0 : rdev->shutdown = true;
669 0 : config_mountroot(self, radeondrm_attachhook);
670 0 : }
671 :
672 : extern void mainbus_efifb_reattach(void);
673 :
674 : int
675 0 : radeondrm_forcedetach(struct radeon_device *rdev)
676 : {
677 0 : struct pci_softc *sc = (struct pci_softc *)rdev->self.dv_parent;
678 0 : pcitag_t tag = rdev->pa_tag;
679 :
680 : #if NVGA > 0
681 0 : if (rdev->console)
682 0 : vga_console_attached = 0;
683 : #endif
684 :
685 : /* reprobe pci device for non efi systems */
686 : #if NEFIFB > 0
687 0 : if (bios_efiinfo == NULL && !efifb_cb_found()) {
688 : #endif
689 0 : config_detach(&rdev->self, 0);
690 0 : return pci_probe_device(sc, tag, NULL, NULL);
691 : #if NEFIFB > 0
692 0 : } else if (rdev->console) {
693 0 : mainbus_efifb_reattach();
694 0 : }
695 : #endif
696 :
697 0 : return 0;
698 0 : }
699 :
700 : void
701 0 : radeondrm_attachhook(struct device *self)
702 : {
703 0 : struct radeon_device *rdev = (struct radeon_device *)self;
704 : int r, acpi_status;
705 :
706 : /* radeon_device_init should report only fatal error
707 : * like memory allocation failure or iomapping failure,
708 : * or memory manager initialization failure, it must
709 : * properly initialize the GPU MC controller and permit
710 : * VRAM allocation
711 : */
712 0 : r = radeon_device_init(rdev, rdev->ddev, rdev->ddev->pdev, rdev->flags);
713 0 : if (r) {
714 0 : dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
715 0 : radeon_fatal_error = 1;
716 0 : radeondrm_forcedetach(rdev);
717 0 : return;
718 : }
719 :
720 : /* Again modeset_init should fail only on fatal error
721 : * otherwise it should provide enough functionalities
722 : * for shadowfb to run
723 : */
724 0 : r = radeon_modeset_init(rdev);
725 0 : if (r)
726 0 : dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
727 :
728 : /* Call ACPI methods: require modeset init
729 : * but failure is not fatal
730 : */
731 0 : if (!r) {
732 0 : acpi_status = radeon_acpi_init(rdev);
733 : if (acpi_status)
734 : DRM_DEBUG("Error during ACPI methods call\n");
735 0 : }
736 :
737 : #ifdef notyet
738 : radeon_kfd_device_probe(rdev);
739 : radeon_kfd_device_init(rdev);
740 : #endif
741 :
742 0 : if (radeon_is_px(rdev->ddev)) {
743 : pm_runtime_use_autosuspend(dev->dev);
744 : pm_runtime_set_autosuspend_delay(dev->dev, 5000);
745 : pm_runtime_set_active(dev->dev);
746 : pm_runtime_allow(dev->dev);
747 : pm_runtime_mark_last_busy(dev->dev);
748 : pm_runtime_put_autosuspend(dev->dev);
749 : }
750 :
751 : {
752 0 : struct drm_fb_helper *fb_helper = (void *)rdev->mode_info.rfbdev;
753 0 : struct wsemuldisplaydev_attach_args aa;
754 0 : struct rasops_info *ri = &rdev->ro;
755 :
756 0 : task_set(&rdev->switchtask, radeondrm_doswitch, ri);
757 :
758 0 : if (ri->ri_bits == NULL)
759 0 : return;
760 :
761 : #ifdef __sparc64__
762 : fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor);
763 : #endif
764 0 : drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
765 :
766 : #ifndef __sparc64__
767 0 : ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY;
768 0 : rasops_init(ri, 160, 160);
769 :
770 0 : ri->ri_hw = rdev;
771 : #else
772 : ri = &rdev->sf.sf_ro;
773 : #endif
774 :
775 0 : radeondrm_stdscreen.capabilities = ri->ri_caps;
776 0 : radeondrm_stdscreen.nrows = ri->ri_rows;
777 0 : radeondrm_stdscreen.ncols = ri->ri_cols;
778 0 : radeondrm_stdscreen.textops = &ri->ri_ops;
779 0 : radeondrm_stdscreen.fontwidth = ri->ri_font->fontwidth;
780 0 : radeondrm_stdscreen.fontheight = ri->ri_font->fontheight;
781 :
782 0 : aa.console = rdev->console;
783 0 : aa.scrdata = &radeondrm_screenlist;
784 0 : aa.accessops = &radeondrm_accessops;
785 0 : aa.accesscookie = ri;
786 0 : aa.defaultscreens = 0;
787 :
788 0 : if (rdev->console) {
789 0 : long defattr;
790 :
791 0 : ri->ri_ops.alloc_attr(ri->ri_active, 0, 0, 0, &defattr);
792 0 : wsdisplay_cnattach(&radeondrm_stdscreen, ri->ri_active,
793 0 : ri->ri_ccol, ri->ri_crow, defattr);
794 0 : }
795 :
796 : /*
797 : * Now that we've taken over the console, disable decoding of
798 : * VGA legacy addresses, and opt out of arbitration.
799 : */
800 0 : radeon_vga_set_state(rdev, false);
801 0 : pci_disable_legacy_vga(&rdev->self);
802 :
803 0 : printf("%s: %dx%d, %dbpp\n", rdev->self.dv_xname,
804 0 : ri->ri_width, ri->ri_height, ri->ri_depth);
805 :
806 0 : config_found_sm(&rdev->self, &aa, wsemuldisplaydevprint,
807 : wsemuldisplaydevsubmatch);
808 0 : }
809 0 : }
810 :
811 : int
812 0 : radeondrm_activate_kms(struct device *self, int act)
813 : {
814 0 : struct radeon_device *rdev = (struct radeon_device *)self;
815 : int rv = 0;
816 :
817 0 : if (rdev->ddev == NULL)
818 0 : return (0);
819 :
820 0 : switch (act) {
821 : case DVACT_QUIESCE:
822 0 : rv = config_activate_children(self, act);
823 0 : radeon_suspend_kms(rdev->ddev, true, true);
824 0 : break;
825 : case DVACT_SUSPEND:
826 : break;
827 : case DVACT_RESUME:
828 : break;
829 : case DVACT_WAKEUP:
830 0 : radeon_resume_kms(rdev->ddev, true, true);
831 0 : rv = config_activate_children(self, act);
832 0 : break;
833 : }
834 :
835 0 : return (rv);
836 0 : }
837 :
838 :
839 : /**
840 : * radeon_set_filp_rights - Set filp right.
841 : *
842 : * @dev: drm dev pointer
843 : * @owner: drm file
844 : * @applier: drm file
845 : * @value: value
846 : *
847 : * Sets the filp rights for the device (all asics).
848 : */
849 0 : static void radeon_set_filp_rights(struct drm_device *dev,
850 : struct drm_file **owner,
851 : struct drm_file *applier,
852 : uint32_t *value)
853 : {
854 0 : struct radeon_device *rdev = dev->dev_private;
855 :
856 0 : mutex_lock(&rdev->gem.mutex);
857 0 : if (*value == 1) {
858 : /* wants rights */
859 0 : if (!*owner)
860 0 : *owner = applier;
861 0 : } else if (*value == 0) {
862 : /* revokes rights */
863 0 : if (*owner == applier)
864 0 : *owner = NULL;
865 : }
866 0 : *value = *owner == applier ? 1 : 0;
867 0 : mutex_unlock(&rdev->gem.mutex);
868 0 : }
869 :
870 : /*
871 : * Userspace get information ioctl
872 : */
873 : /**
874 : * radeon_info_ioctl - answer a device specific request.
875 : *
876 : * @rdev: radeon device pointer
877 : * @data: request object
878 : * @filp: drm filp
879 : *
880 : * This function is used to pass device specific parameters to the userspace
881 : * drivers. Examples include: pci device id, pipeline parms, tiling params,
882 : * etc. (all asics).
883 : * Returns 0 on success, -EINVAL on failure.
884 : */
885 0 : static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
886 : {
887 0 : struct radeon_device *rdev = dev->dev_private;
888 0 : struct drm_radeon_info *info = data;
889 0 : struct radeon_mode_info *minfo = &rdev->mode_info;
890 0 : uint32_t *value, value_tmp, *value_ptr, value_size;
891 0 : uint64_t value64;
892 : struct drm_crtc *crtc;
893 : int i, found;
894 :
895 0 : value_ptr = (uint32_t *)((unsigned long)info->value);
896 : value = &value_tmp;
897 : value_size = sizeof(uint32_t);
898 :
899 0 : switch (info->request) {
900 : case RADEON_INFO_DEVICE_ID:
901 0 : *value = dev->pdev->device;
902 0 : break;
903 : case RADEON_INFO_NUM_GB_PIPES:
904 0 : *value = rdev->num_gb_pipes;
905 0 : break;
906 : case RADEON_INFO_NUM_Z_PIPES:
907 0 : *value = rdev->num_z_pipes;
908 0 : break;
909 : case RADEON_INFO_ACCEL_WORKING:
910 : /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
911 0 : if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
912 0 : *value = false;
913 : else
914 0 : *value = rdev->accel_working;
915 : break;
916 : case RADEON_INFO_CRTC_FROM_ID:
917 0 : if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
918 0 : DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
919 0 : return -EFAULT;
920 : }
921 0 : for (i = 0, found = 0; i < rdev->num_crtc; i++) {
922 0 : crtc = (struct drm_crtc *)minfo->crtcs[i];
923 0 : if (crtc && crtc->base.id == *value) {
924 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
925 0 : *value = radeon_crtc->crtc_id;
926 : found = 1;
927 : break;
928 : }
929 : }
930 0 : if (!found) {
931 : DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
932 0 : return -EINVAL;
933 : }
934 : break;
935 : case RADEON_INFO_ACCEL_WORKING2:
936 0 : if (rdev->family == CHIP_HAWAII) {
937 0 : if (rdev->accel_working) {
938 0 : if (rdev->new_fw)
939 0 : *value = 3;
940 : else
941 0 : *value = 2;
942 : } else {
943 0 : *value = 0;
944 : }
945 : } else {
946 0 : *value = rdev->accel_working;
947 : }
948 : break;
949 : case RADEON_INFO_TILING_CONFIG:
950 0 : if (rdev->family >= CHIP_BONAIRE)
951 0 : *value = rdev->config.cik.tile_config;
952 0 : else if (rdev->family >= CHIP_TAHITI)
953 0 : *value = rdev->config.si.tile_config;
954 0 : else if (rdev->family >= CHIP_CAYMAN)
955 0 : *value = rdev->config.cayman.tile_config;
956 0 : else if (rdev->family >= CHIP_CEDAR)
957 0 : *value = rdev->config.evergreen.tile_config;
958 0 : else if (rdev->family >= CHIP_RV770)
959 0 : *value = rdev->config.rv770.tile_config;
960 0 : else if (rdev->family >= CHIP_R600)
961 0 : *value = rdev->config.r600.tile_config;
962 : else {
963 : DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
964 0 : return -EINVAL;
965 : }
966 : break;
967 : case RADEON_INFO_WANT_HYPERZ:
968 : /* The "value" here is both an input and output parameter.
969 : * If the input value is 1, filp requests hyper-z access.
970 : * If the input value is 0, filp revokes its hyper-z access.
971 : *
972 : * When returning, the value is 1 if filp owns hyper-z access,
973 : * 0 otherwise. */
974 0 : if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
975 0 : DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
976 0 : return -EFAULT;
977 : }
978 0 : if (*value >= 2) {
979 : DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
980 0 : return -EINVAL;
981 : }
982 0 : radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
983 0 : break;
984 : case RADEON_INFO_WANT_CMASK:
985 : /* The same logic as Hyper-Z. */
986 0 : if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
987 0 : DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
988 0 : return -EFAULT;
989 : }
990 0 : if (*value >= 2) {
991 : DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
992 0 : return -EINVAL;
993 : }
994 0 : radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
995 0 : break;
996 : case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
997 : /* return clock value in KHz */
998 0 : if (rdev->asic->get_xclk)
999 0 : *value = radeon_get_xclk(rdev) * 10;
1000 : else
1001 0 : *value = rdev->clock.spll.reference_freq * 10;
1002 : break;
1003 : case RADEON_INFO_NUM_BACKENDS:
1004 0 : if (rdev->family >= CHIP_BONAIRE)
1005 0 : *value = rdev->config.cik.max_backends_per_se *
1006 0 : rdev->config.cik.max_shader_engines;
1007 0 : else if (rdev->family >= CHIP_TAHITI)
1008 0 : *value = rdev->config.si.max_backends_per_se *
1009 0 : rdev->config.si.max_shader_engines;
1010 0 : else if (rdev->family >= CHIP_CAYMAN)
1011 0 : *value = rdev->config.cayman.max_backends_per_se *
1012 0 : rdev->config.cayman.max_shader_engines;
1013 0 : else if (rdev->family >= CHIP_CEDAR)
1014 0 : *value = rdev->config.evergreen.max_backends;
1015 0 : else if (rdev->family >= CHIP_RV770)
1016 0 : *value = rdev->config.rv770.max_backends;
1017 0 : else if (rdev->family >= CHIP_R600)
1018 0 : *value = rdev->config.r600.max_backends;
1019 : else {
1020 0 : return -EINVAL;
1021 : }
1022 : break;
1023 : case RADEON_INFO_NUM_TILE_PIPES:
1024 0 : if (rdev->family >= CHIP_BONAIRE)
1025 0 : *value = rdev->config.cik.max_tile_pipes;
1026 0 : else if (rdev->family >= CHIP_TAHITI)
1027 0 : *value = rdev->config.si.max_tile_pipes;
1028 0 : else if (rdev->family >= CHIP_CAYMAN)
1029 0 : *value = rdev->config.cayman.max_tile_pipes;
1030 0 : else if (rdev->family >= CHIP_CEDAR)
1031 0 : *value = rdev->config.evergreen.max_tile_pipes;
1032 0 : else if (rdev->family >= CHIP_RV770)
1033 0 : *value = rdev->config.rv770.max_tile_pipes;
1034 0 : else if (rdev->family >= CHIP_R600)
1035 0 : *value = rdev->config.r600.max_tile_pipes;
1036 : else {
1037 0 : return -EINVAL;
1038 : }
1039 : break;
1040 : case RADEON_INFO_FUSION_GART_WORKING:
1041 0 : *value = 1;
1042 0 : break;
1043 : case RADEON_INFO_BACKEND_MAP:
1044 0 : if (rdev->family >= CHIP_BONAIRE)
1045 0 : *value = rdev->config.cik.backend_map;
1046 0 : else if (rdev->family >= CHIP_TAHITI)
1047 0 : *value = rdev->config.si.backend_map;
1048 0 : else if (rdev->family >= CHIP_CAYMAN)
1049 0 : *value = rdev->config.cayman.backend_map;
1050 0 : else if (rdev->family >= CHIP_CEDAR)
1051 0 : *value = rdev->config.evergreen.backend_map;
1052 0 : else if (rdev->family >= CHIP_RV770)
1053 0 : *value = rdev->config.rv770.backend_map;
1054 0 : else if (rdev->family >= CHIP_R600)
1055 0 : *value = rdev->config.r600.backend_map;
1056 : else {
1057 0 : return -EINVAL;
1058 : }
1059 : break;
1060 : case RADEON_INFO_VA_START:
1061 : /* this is where we report if vm is supported or not */
1062 0 : if (rdev->family < CHIP_CAYMAN)
1063 0 : return -EINVAL;
1064 0 : *value = RADEON_VA_RESERVED_SIZE;
1065 0 : break;
1066 : case RADEON_INFO_IB_VM_MAX_SIZE:
1067 : /* this is where we report if vm is supported or not */
1068 0 : if (rdev->family < CHIP_CAYMAN)
1069 0 : return -EINVAL;
1070 0 : *value = RADEON_IB_VM_MAX_SIZE;
1071 0 : break;
1072 : case RADEON_INFO_MAX_PIPES:
1073 0 : if (rdev->family >= CHIP_BONAIRE)
1074 0 : *value = rdev->config.cik.max_cu_per_sh;
1075 0 : else if (rdev->family >= CHIP_TAHITI)
1076 0 : *value = rdev->config.si.max_cu_per_sh;
1077 0 : else if (rdev->family >= CHIP_CAYMAN)
1078 0 : *value = rdev->config.cayman.max_pipes_per_simd;
1079 0 : else if (rdev->family >= CHIP_CEDAR)
1080 0 : *value = rdev->config.evergreen.max_pipes;
1081 0 : else if (rdev->family >= CHIP_RV770)
1082 0 : *value = rdev->config.rv770.max_pipes;
1083 0 : else if (rdev->family >= CHIP_R600)
1084 0 : *value = rdev->config.r600.max_pipes;
1085 : else {
1086 0 : return -EINVAL;
1087 : }
1088 : break;
1089 : case RADEON_INFO_TIMESTAMP:
1090 0 : if (rdev->family < CHIP_R600) {
1091 : DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
1092 0 : return -EINVAL;
1093 : }
1094 0 : value = (uint32_t*)&value64;
1095 : value_size = sizeof(uint64_t);
1096 0 : value64 = radeon_get_gpu_clock_counter(rdev);
1097 0 : break;
1098 : case RADEON_INFO_MAX_SE:
1099 0 : if (rdev->family >= CHIP_BONAIRE)
1100 0 : *value = rdev->config.cik.max_shader_engines;
1101 0 : else if (rdev->family >= CHIP_TAHITI)
1102 0 : *value = rdev->config.si.max_shader_engines;
1103 0 : else if (rdev->family >= CHIP_CAYMAN)
1104 0 : *value = rdev->config.cayman.max_shader_engines;
1105 0 : else if (rdev->family >= CHIP_CEDAR)
1106 0 : *value = rdev->config.evergreen.num_ses;
1107 : else
1108 0 : *value = 1;
1109 : break;
1110 : case RADEON_INFO_MAX_SH_PER_SE:
1111 0 : if (rdev->family >= CHIP_BONAIRE)
1112 0 : *value = rdev->config.cik.max_sh_per_se;
1113 0 : else if (rdev->family >= CHIP_TAHITI)
1114 0 : *value = rdev->config.si.max_sh_per_se;
1115 : else
1116 0 : return -EINVAL;
1117 : break;
1118 : case RADEON_INFO_FASTFB_WORKING:
1119 0 : *value = rdev->fastfb_working;
1120 0 : break;
1121 : case RADEON_INFO_RING_WORKING:
1122 0 : if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
1123 0 : DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
1124 0 : return -EFAULT;
1125 : }
1126 0 : switch (*value) {
1127 : case RADEON_CS_RING_GFX:
1128 : case RADEON_CS_RING_COMPUTE:
1129 0 : *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
1130 0 : break;
1131 : case RADEON_CS_RING_DMA:
1132 0 : *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
1133 0 : *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
1134 0 : break;
1135 : case RADEON_CS_RING_UVD:
1136 0 : *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
1137 0 : break;
1138 : case RADEON_CS_RING_VCE:
1139 0 : *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
1140 0 : break;
1141 : default:
1142 0 : return -EINVAL;
1143 : }
1144 : break;
1145 : case RADEON_INFO_SI_TILE_MODE_ARRAY:
1146 0 : if (rdev->family >= CHIP_BONAIRE) {
1147 0 : value = rdev->config.cik.tile_mode_array;
1148 : value_size = sizeof(uint32_t)*32;
1149 0 : } else if (rdev->family >= CHIP_TAHITI) {
1150 0 : value = rdev->config.si.tile_mode_array;
1151 : value_size = sizeof(uint32_t)*32;
1152 : } else {
1153 : DRM_DEBUG_KMS("tile mode array is si+ only!\n");
1154 0 : return -EINVAL;
1155 : }
1156 : break;
1157 : case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
1158 0 : if (rdev->family >= CHIP_BONAIRE) {
1159 0 : value = rdev->config.cik.macrotile_mode_array;
1160 : value_size = sizeof(uint32_t)*16;
1161 : } else {
1162 : DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
1163 0 : return -EINVAL;
1164 : }
1165 0 : break;
1166 : case RADEON_INFO_SI_CP_DMA_COMPUTE:
1167 0 : *value = 1;
1168 0 : break;
1169 : case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
1170 0 : if (rdev->family >= CHIP_BONAIRE) {
1171 0 : *value = rdev->config.cik.backend_enable_mask;
1172 0 : } else if (rdev->family >= CHIP_TAHITI) {
1173 0 : *value = rdev->config.si.backend_enable_mask;
1174 0 : } else {
1175 : DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
1176 : }
1177 : break;
1178 : case RADEON_INFO_MAX_SCLK:
1179 0 : if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
1180 0 : rdev->pm.dpm_enabled)
1181 0 : *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
1182 : else
1183 0 : *value = rdev->pm.default_sclk * 10;
1184 : break;
1185 : case RADEON_INFO_VCE_FW_VERSION:
1186 0 : *value = rdev->vce.fw_version;
1187 0 : break;
1188 : case RADEON_INFO_VCE_FB_VERSION:
1189 0 : *value = rdev->vce.fb_version;
1190 0 : break;
1191 : case RADEON_INFO_NUM_BYTES_MOVED:
1192 0 : value = (uint32_t*)&value64;
1193 : value_size = sizeof(uint64_t);
1194 0 : value64 = atomic64_read(&rdev->num_bytes_moved);
1195 0 : break;
1196 : case RADEON_INFO_VRAM_USAGE:
1197 0 : value = (uint32_t*)&value64;
1198 : value_size = sizeof(uint64_t);
1199 0 : value64 = atomic64_read(&rdev->vram_usage);
1200 0 : break;
1201 : case RADEON_INFO_GTT_USAGE:
1202 0 : value = (uint32_t*)&value64;
1203 : value_size = sizeof(uint64_t);
1204 0 : value64 = atomic64_read(&rdev->gtt_usage);
1205 0 : break;
1206 : case RADEON_INFO_ACTIVE_CU_COUNT:
1207 0 : if (rdev->family >= CHIP_BONAIRE)
1208 0 : *value = rdev->config.cik.active_cus;
1209 0 : else if (rdev->family >= CHIP_TAHITI)
1210 0 : *value = rdev->config.si.active_cus;
1211 0 : else if (rdev->family >= CHIP_CAYMAN)
1212 0 : *value = rdev->config.cayman.active_simds;
1213 0 : else if (rdev->family >= CHIP_CEDAR)
1214 0 : *value = rdev->config.evergreen.active_simds;
1215 0 : else if (rdev->family >= CHIP_RV770)
1216 0 : *value = rdev->config.rv770.active_simds;
1217 0 : else if (rdev->family >= CHIP_R600)
1218 0 : *value = rdev->config.r600.active_simds;
1219 : else
1220 0 : *value = 1;
1221 : break;
1222 : case RADEON_INFO_CURRENT_GPU_TEMP:
1223 : /* get temperature in millidegrees C */
1224 0 : if (rdev->asic->pm.get_temperature)
1225 0 : *value = radeon_get_temperature(rdev);
1226 : else
1227 0 : *value = 0;
1228 : break;
1229 : case RADEON_INFO_CURRENT_GPU_SCLK:
1230 : /* get sclk in Mhz */
1231 0 : if (rdev->pm.dpm_enabled)
1232 0 : *value = radeon_dpm_get_current_sclk(rdev) / 100;
1233 : else
1234 0 : *value = rdev->pm.current_sclk / 100;
1235 : break;
1236 : case RADEON_INFO_CURRENT_GPU_MCLK:
1237 : /* get mclk in Mhz */
1238 0 : if (rdev->pm.dpm_enabled)
1239 0 : *value = radeon_dpm_get_current_mclk(rdev) / 100;
1240 : else
1241 0 : *value = rdev->pm.current_mclk / 100;
1242 : break;
1243 : case RADEON_INFO_READ_REG:
1244 0 : if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
1245 0 : DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
1246 0 : return -EFAULT;
1247 : }
1248 0 : if (radeon_get_allowed_info_register(rdev, *value, value))
1249 0 : return -EINVAL;
1250 : break;
1251 : case RADEON_INFO_VA_UNMAP_WORKING:
1252 0 : *value = true;
1253 0 : break;
1254 : case RADEON_INFO_GPU_RESET_COUNTER:
1255 0 : *value = atomic_read(&rdev->gpu_reset_counter);
1256 0 : break;
1257 : default:
1258 : DRM_DEBUG_KMS("Invalid request %d\n", info->request);
1259 0 : return -EINVAL;
1260 : }
1261 0 : if (copy_to_user(value_ptr, (char*)value, value_size)) {
1262 0 : DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
1263 0 : return -EFAULT;
1264 : }
1265 0 : return 0;
1266 0 : }
1267 :
1268 :
1269 : /*
1270 : * Outdated mess for old drm with Xorg being in charge (void function now).
1271 : */
1272 : /**
1273 : * radeon_driver_lastclose_kms - drm callback for last close
1274 : *
1275 : * @dev: drm dev pointer
1276 : *
1277 : * Switch vga_switcheroo state after last close (all asics).
1278 : */
1279 0 : void radeon_driver_lastclose_kms(struct drm_device *dev)
1280 : {
1281 0 : struct radeon_device *rdev = dev->dev_private;
1282 :
1283 : #ifdef __sparc64__
1284 : fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor);
1285 : #endif
1286 0 : if (rdev->mode_info.mode_config_initialized)
1287 0 : radeon_fbdev_restore_mode(rdev);
1288 : vga_switcheroo_process_delayed_switch();
1289 0 : }
1290 :
1291 : /**
1292 : * radeon_driver_open_kms - drm callback for open
1293 : *
1294 : * @dev: drm dev pointer
1295 : * @file_priv: drm file
1296 : *
1297 : * On device open, init vm on cayman+ (all asics).
1298 : * Returns 0 on success, error on failure.
1299 : */
1300 0 : int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1301 : {
1302 0 : struct radeon_device *rdev = dev->dev_private;
1303 : int r;
1304 :
1305 0 : file_priv->driver_priv = NULL;
1306 :
1307 0 : r = pm_runtime_get_sync(dev->dev);
1308 0 : if (r < 0)
1309 0 : return r;
1310 :
1311 : /* new gpu have virtual address space support */
1312 0 : if (rdev->family >= CHIP_CAYMAN) {
1313 : struct radeon_fpriv *fpriv;
1314 : struct radeon_vm *vm;
1315 : int r;
1316 :
1317 0 : fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1318 0 : if (unlikely(!fpriv)) {
1319 0 : return -ENOMEM;
1320 : }
1321 :
1322 0 : if (rdev->accel_working) {
1323 0 : vm = &fpriv->vm;
1324 0 : r = radeon_vm_init(rdev, vm);
1325 0 : if (r) {
1326 0 : kfree(fpriv);
1327 0 : return r;
1328 : }
1329 :
1330 0 : r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
1331 0 : if (r) {
1332 0 : radeon_vm_fini(rdev, vm);
1333 0 : kfree(fpriv);
1334 0 : return r;
1335 : }
1336 :
1337 : /* map the ib pool buffer read only into
1338 : * virtual address space */
1339 0 : vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
1340 0 : rdev->ring_tmp_bo.bo);
1341 0 : r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
1342 : RADEON_VA_IB_OFFSET,
1343 : RADEON_VM_PAGE_READABLE |
1344 : RADEON_VM_PAGE_SNOOPED);
1345 0 : if (r) {
1346 0 : radeon_vm_fini(rdev, vm);
1347 0 : kfree(fpriv);
1348 0 : return r;
1349 : }
1350 : }
1351 0 : file_priv->driver_priv = fpriv;
1352 0 : }
1353 :
1354 : pm_runtime_mark_last_busy(dev->dev);
1355 : pm_runtime_put_autosuspend(dev->dev);
1356 0 : return 0;
1357 0 : }
1358 :
1359 : /**
1360 : * radeon_driver_postclose_kms - drm callback for post close
1361 : *
1362 : * @dev: drm dev pointer
1363 : * @file_priv: drm file
1364 : *
1365 : * On device post close, tear down vm on cayman+ (all asics).
1366 : */
1367 0 : void radeon_driver_postclose_kms(struct drm_device *dev,
1368 : struct drm_file *file_priv)
1369 : {
1370 0 : struct radeon_device *rdev = dev->dev_private;
1371 :
1372 : /* new gpu have virtual address space support */
1373 0 : if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
1374 0 : struct radeon_fpriv *fpriv = file_priv->driver_priv;
1375 0 : struct radeon_vm *vm = &fpriv->vm;
1376 : int r;
1377 :
1378 0 : if (rdev->accel_working) {
1379 0 : r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
1380 0 : if (!r) {
1381 0 : if (vm->ib_bo_va)
1382 0 : radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
1383 0 : radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
1384 0 : }
1385 0 : radeon_vm_fini(rdev, vm);
1386 0 : }
1387 :
1388 0 : kfree(fpriv);
1389 0 : file_priv->driver_priv = NULL;
1390 0 : }
1391 0 : }
1392 :
1393 : /**
1394 : * radeon_driver_preclose_kms - drm callback for pre close
1395 : *
1396 : * @dev: drm dev pointer
1397 : * @file_priv: drm file
1398 : *
1399 : * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
1400 : * (all asics).
1401 : */
1402 0 : void radeon_driver_preclose_kms(struct drm_device *dev,
1403 : struct drm_file *file_priv)
1404 : {
1405 0 : struct radeon_device *rdev = dev->dev_private;
1406 :
1407 0 : mutex_lock(&rdev->gem.mutex);
1408 0 : if (rdev->hyperz_filp == file_priv)
1409 0 : rdev->hyperz_filp = NULL;
1410 0 : if (rdev->cmask_filp == file_priv)
1411 0 : rdev->cmask_filp = NULL;
1412 0 : mutex_unlock(&rdev->gem.mutex);
1413 :
1414 0 : radeon_uvd_free_handles(rdev, file_priv);
1415 0 : radeon_vce_free_handles(rdev, file_priv);
1416 0 : }
1417 :
1418 : /*
1419 : * VBlank related functions.
1420 : */
1421 : /**
1422 : * radeon_get_vblank_counter_kms - get frame count
1423 : *
1424 : * @dev: drm dev pointer
1425 : * @crtc: crtc to get the frame count from
1426 : *
1427 : * Gets the frame count on the requested crtc (all asics).
1428 : * Returns frame count on success, -EINVAL on failure.
1429 : */
1430 0 : u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
1431 : {
1432 0 : int vpos, hpos, stat;
1433 : u32 count;
1434 0 : struct radeon_device *rdev = dev->dev_private;
1435 :
1436 0 : if (crtc < 0 || crtc >= rdev->num_crtc) {
1437 0 : DRM_ERROR("Invalid crtc %d\n", crtc);
1438 0 : return -EINVAL;
1439 : }
1440 :
1441 : /* The hw increments its frame counter at start of vsync, not at start
1442 : * of vblank, as is required by DRM core vblank counter handling.
1443 : * Cook the hw count here to make it appear to the caller as if it
1444 : * incremented at start of vblank. We measure distance to start of
1445 : * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1446 : * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1447 : * result by 1 to give the proper appearance to caller.
1448 : */
1449 0 : if (rdev->mode_info.crtcs[crtc]) {
1450 : /* Repeat readout if needed to provide stable result if
1451 : * we cross start of vsync during the queries.
1452 : */
1453 0 : do {
1454 0 : count = radeon_get_vblank_counter(rdev, crtc);
1455 : /* Ask radeon_get_crtc_scanoutpos to return vpos as
1456 : * distance to start of vblank, instead of regular
1457 : * vertical scanout pos.
1458 : */
1459 0 : stat = radeon_get_crtc_scanoutpos(
1460 : dev, crtc, GET_DISTANCE_TO_VBLANKSTART,
1461 : &vpos, &hpos, NULL, NULL,
1462 0 : &rdev->mode_info.crtcs[crtc]->base.hwmode);
1463 0 : } while (count != radeon_get_vblank_counter(rdev, crtc));
1464 :
1465 0 : if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1466 : (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1467 : DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1468 : }
1469 : else {
1470 : DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1471 : crtc, vpos);
1472 :
1473 : /* Bump counter if we are at >= leading edge of vblank,
1474 : * but before vsync where vpos would turn negative and
1475 : * the hw counter really increments.
1476 : */
1477 0 : if (vpos >= 0)
1478 0 : count++;
1479 : }
1480 : }
1481 : else {
1482 : /* Fallback to use value as is. */
1483 0 : count = radeon_get_vblank_counter(rdev, crtc);
1484 : DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1485 : }
1486 :
1487 0 : return count;
1488 0 : }
1489 :
1490 : /**
1491 : * radeon_enable_vblank_kms - enable vblank interrupt
1492 : *
1493 : * @dev: drm dev pointer
1494 : * @crtc: crtc to enable vblank interrupt for
1495 : *
1496 : * Enable the interrupt on the requested crtc (all asics).
1497 : * Returns 0 on success, -EINVAL on failure.
1498 : */
1499 0 : int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
1500 : {
1501 0 : struct radeon_device *rdev = dev->dev_private;
1502 : unsigned long irqflags;
1503 : int r;
1504 :
1505 0 : if (crtc < 0 || crtc >= rdev->num_crtc) {
1506 0 : DRM_ERROR("Invalid crtc %d\n", crtc);
1507 0 : return -EINVAL;
1508 : }
1509 :
1510 0 : spin_lock_irqsave(&rdev->irq.lock, irqflags);
1511 0 : rdev->irq.crtc_vblank_int[crtc] = true;
1512 0 : r = radeon_irq_set(rdev);
1513 0 : spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
1514 0 : return r;
1515 0 : }
1516 :
1517 : /**
1518 : * radeon_disable_vblank_kms - disable vblank interrupt
1519 : *
1520 : * @dev: drm dev pointer
1521 : * @crtc: crtc to disable vblank interrupt for
1522 : *
1523 : * Disable the interrupt on the requested crtc (all asics).
1524 : */
1525 0 : void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
1526 : {
1527 0 : struct radeon_device *rdev = dev->dev_private;
1528 : unsigned long irqflags;
1529 :
1530 0 : if (crtc < 0 || crtc >= rdev->num_crtc) {
1531 0 : DRM_ERROR("Invalid crtc %d\n", crtc);
1532 0 : return;
1533 : }
1534 :
1535 0 : spin_lock_irqsave(&rdev->irq.lock, irqflags);
1536 0 : rdev->irq.crtc_vblank_int[crtc] = false;
1537 0 : radeon_irq_set(rdev);
1538 0 : spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
1539 0 : }
1540 :
1541 : /**
1542 : * radeon_get_vblank_timestamp_kms - get vblank timestamp
1543 : *
1544 : * @dev: drm dev pointer
1545 : * @crtc: crtc to get the timestamp for
1546 : * @max_error: max error
1547 : * @vblank_time: time value
1548 : * @flags: flags passed to the driver
1549 : *
1550 : * Gets the timestamp on the requested crtc based on the
1551 : * scanout position. (all asics).
1552 : * Returns postive status flags on success, negative error on failure.
1553 : */
1554 0 : int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
1555 : int *max_error,
1556 : struct timeval *vblank_time,
1557 : unsigned flags)
1558 : {
1559 : struct drm_crtc *drmcrtc;
1560 0 : struct radeon_device *rdev = dev->dev_private;
1561 :
1562 0 : if (crtc < 0 || crtc >= dev->num_crtcs) {
1563 0 : DRM_ERROR("Invalid crtc %d\n", crtc);
1564 0 : return -EINVAL;
1565 : }
1566 :
1567 : /* Get associated drm_crtc: */
1568 0 : drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
1569 0 : if (!drmcrtc)
1570 0 : return -EINVAL;
1571 :
1572 : /* Helper routine in DRM core does all the work: */
1573 0 : return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
1574 : vblank_time, flags,
1575 0 : &drmcrtc->hwmode);
1576 0 : }
1577 :
1578 : const struct drm_ioctl_desc radeon_ioctls_kms[] = {
1579 : DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1580 : DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1581 : DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1582 : DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1583 : DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
1584 : DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
1585 : DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
1586 : DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
1587 : DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
1588 : DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
1589 : DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
1590 : DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
1591 : DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
1592 : DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
1593 : DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1594 : DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
1595 : DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
1596 : DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
1597 : DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
1598 : DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
1599 : DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
1600 : DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1601 : DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
1602 : DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
1603 : DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
1604 : DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
1605 : DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
1606 : /* KMS */
1607 : DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1608 : DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1609 : DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1610 : DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1611 : DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
1612 : DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
1613 : DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1614 : DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1615 : DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1616 : DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1617 : DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1618 : DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1619 : DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1620 : DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1621 : DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1622 : };
1623 : int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);
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