Line data Source code
1 : /*
2 : * Copyright 2007-8 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : *
5 : * Permission is hereby granted, free of charge, to any person obtaining a
6 : * copy of this software and associated documentation files (the "Software"),
7 : * to deal in the Software without restriction, including without limitation
8 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 : * and/or sell copies of the Software, and to permit persons to whom the
10 : * Software is furnished to do so, subject to the following conditions:
11 : *
12 : * The above copyright notice and this permission notice shall be included in
13 : * all copies or substantial portions of the Software.
14 : *
15 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 : * OTHER DEALINGS IN THE SOFTWARE.
22 : *
23 : * Authors: Dave Airlie
24 : * Alex Deucher
25 : */
26 : #include <dev/pci/drm/drmP.h>
27 : #include <dev/pci/drm/drm_crtc_helper.h>
28 : #include <dev/pci/drm/radeon_drm.h>
29 : #include "radeon.h"
30 : #include "atom.h"
31 : #ifdef CONFIG_PMAC_BACKLIGHT
32 : #include <asm/backlight.h>
33 : #endif
34 :
35 0 : static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
36 : {
37 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
38 : const struct drm_encoder_helper_funcs *encoder_funcs;
39 :
40 0 : encoder_funcs = encoder->helper_private;
41 0 : encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
42 0 : radeon_encoder->active_device = 0;
43 0 : }
44 :
45 0 : static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
46 : {
47 0 : struct drm_device *dev = encoder->dev;
48 0 : struct radeon_device *rdev = dev->dev_private;
49 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
50 : uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
51 : int panel_pwr_delay = 2000;
52 : bool is_mac = false;
53 : uint8_t backlight_level;
54 : DRM_DEBUG_KMS("\n");
55 :
56 0 : lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
57 0 : backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
58 :
59 0 : if (radeon_encoder->enc_priv) {
60 0 : if (rdev->is_atom_bios) {
61 0 : struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
62 0 : panel_pwr_delay = lvds->panel_pwr_delay;
63 0 : if (lvds->bl_dev)
64 0 : backlight_level = lvds->backlight_level;
65 0 : } else {
66 0 : struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
67 0 : panel_pwr_delay = lvds->panel_pwr_delay;
68 0 : if (lvds->bl_dev)
69 0 : backlight_level = lvds->backlight_level;
70 : }
71 : }
72 :
73 : /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
74 : * Taken from radeonfb.
75 : */
76 0 : if ((rdev->mode_info.connector_table == CT_IBOOK) ||
77 0 : (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
78 0 : (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
79 0 : (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
80 0 : is_mac = true;
81 :
82 0 : switch (mode) {
83 : case DRM_MODE_DPMS_ON:
84 0 : disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
85 0 : disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
86 0 : WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
87 0 : lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
88 0 : lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
89 0 : WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
90 0 : mdelay(1);
91 :
92 0 : lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
93 0 : lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
94 0 : WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
95 :
96 0 : lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
97 : RADEON_LVDS_BL_MOD_LEVEL_MASK);
98 0 : lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
99 0 : RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
100 0 : (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
101 0 : if (is_mac)
102 0 : lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
103 0 : mdelay(panel_pwr_delay);
104 0 : WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
105 0 : break;
106 : case DRM_MODE_DPMS_STANDBY:
107 : case DRM_MODE_DPMS_SUSPEND:
108 : case DRM_MODE_DPMS_OFF:
109 0 : pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
110 0 : WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
111 0 : lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
112 0 : if (is_mac) {
113 0 : lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
114 0 : WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
115 0 : lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
116 0 : } else {
117 0 : WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
118 0 : lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
119 : }
120 0 : mdelay(panel_pwr_delay);
121 0 : WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
122 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
123 0 : mdelay(panel_pwr_delay);
124 0 : break;
125 : }
126 :
127 0 : if (rdev->is_atom_bios)
128 0 : radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
129 : else
130 0 : radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
131 :
132 0 : }
133 :
134 0 : static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
135 : {
136 0 : struct radeon_device *rdev = encoder->dev->dev_private;
137 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
138 : DRM_DEBUG("\n");
139 :
140 0 : if (radeon_encoder->enc_priv) {
141 0 : if (rdev->is_atom_bios) {
142 0 : struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
143 0 : lvds->dpms_mode = mode;
144 0 : } else {
145 0 : struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
146 0 : lvds->dpms_mode = mode;
147 : }
148 : }
149 :
150 0 : radeon_legacy_lvds_update(encoder, mode);
151 0 : }
152 :
153 0 : static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
154 : {
155 0 : struct radeon_device *rdev = encoder->dev->dev_private;
156 :
157 0 : if (rdev->is_atom_bios)
158 0 : radeon_atom_output_lock(encoder, true);
159 : else
160 0 : radeon_combios_output_lock(encoder, true);
161 0 : radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
162 0 : }
163 :
164 0 : static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
165 : {
166 0 : struct radeon_device *rdev = encoder->dev->dev_private;
167 :
168 0 : radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
169 0 : if (rdev->is_atom_bios)
170 0 : radeon_atom_output_lock(encoder, false);
171 : else
172 0 : radeon_combios_output_lock(encoder, false);
173 0 : }
174 :
175 0 : static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
176 : struct drm_display_mode *mode,
177 : struct drm_display_mode *adjusted_mode)
178 : {
179 0 : struct drm_device *dev = encoder->dev;
180 0 : struct radeon_device *rdev = dev->dev_private;
181 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
182 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
183 : uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
184 :
185 : DRM_DEBUG_KMS("\n");
186 :
187 0 : lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
188 0 : lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
189 :
190 0 : lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
191 0 : if (rdev->is_atom_bios) {
192 : /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
193 : * need to call that on resume to set up the reg properly.
194 : */
195 0 : radeon_encoder->pixel_clock = adjusted_mode->clock;
196 0 : atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
197 0 : lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
198 0 : } else {
199 0 : struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
200 0 : if (lvds) {
201 : DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
202 0 : lvds_gen_cntl = lvds->lvds_gen_cntl;
203 0 : lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
204 : (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
205 0 : lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
206 0 : (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
207 0 : } else
208 0 : lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
209 : }
210 0 : lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
211 0 : lvds_gen_cntl &= ~(RADEON_LVDS_ON |
212 : RADEON_LVDS_BLON |
213 : RADEON_LVDS_EN |
214 : RADEON_LVDS_RST_FM);
215 :
216 0 : if (ASIC_IS_R300(rdev))
217 0 : lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
218 :
219 0 : if (radeon_crtc->crtc_id == 0) {
220 0 : if (ASIC_IS_R300(rdev)) {
221 0 : if (radeon_encoder->rmx_type != RMX_OFF)
222 0 : lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
223 : } else
224 0 : lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
225 : } else {
226 0 : if (ASIC_IS_R300(rdev))
227 0 : lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
228 : else
229 0 : lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
230 : }
231 :
232 0 : WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
233 0 : WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
234 0 : WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
235 :
236 0 : if (rdev->family == CHIP_RV410)
237 0 : WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
238 :
239 0 : if (rdev->is_atom_bios)
240 0 : radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
241 : else
242 0 : radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
243 0 : }
244 :
245 0 : static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
246 : const struct drm_display_mode *mode,
247 : struct drm_display_mode *adjusted_mode)
248 : {
249 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
250 :
251 : /* set the active encoder to connector routing */
252 0 : radeon_encoder_set_active_device(encoder);
253 0 : drm_mode_set_crtcinfo(adjusted_mode, 0);
254 :
255 : /* get the native mode for LVDS */
256 0 : if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
257 0 : radeon_panel_mode_fixup(encoder, adjusted_mode);
258 :
259 0 : return true;
260 : }
261 :
262 : static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
263 : .dpms = radeon_legacy_lvds_dpms,
264 : .mode_fixup = radeon_legacy_mode_fixup,
265 : .prepare = radeon_legacy_lvds_prepare,
266 : .mode_set = radeon_legacy_lvds_mode_set,
267 : .commit = radeon_legacy_lvds_commit,
268 : .disable = radeon_legacy_encoder_disable,
269 : };
270 :
271 : u8
272 0 : radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
273 : {
274 0 : struct drm_device *dev = radeon_encoder->base.dev;
275 0 : struct radeon_device *rdev = dev->dev_private;
276 : u8 backlight_level;
277 :
278 0 : backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
279 0 : RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
280 :
281 0 : return backlight_level;
282 : }
283 :
284 : void
285 0 : radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
286 : {
287 0 : struct drm_device *dev = radeon_encoder->base.dev;
288 0 : struct radeon_device *rdev = dev->dev_private;
289 : int dpms_mode = DRM_MODE_DPMS_ON;
290 :
291 0 : if (radeon_encoder->enc_priv) {
292 0 : if (rdev->is_atom_bios) {
293 0 : struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
294 0 : if (lvds->backlight_level > 0)
295 0 : dpms_mode = lvds->dpms_mode;
296 : else
297 : dpms_mode = DRM_MODE_DPMS_OFF;
298 0 : lvds->backlight_level = level;
299 0 : } else {
300 0 : struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
301 0 : if (lvds->backlight_level > 0)
302 0 : dpms_mode = lvds->dpms_mode;
303 : else
304 : dpms_mode = DRM_MODE_DPMS_OFF;
305 0 : lvds->backlight_level = level;
306 : }
307 : }
308 :
309 0 : radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
310 0 : }
311 :
312 : #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
313 :
314 0 : static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
315 : {
316 0 : struct radeon_backlight_privdata *pdata = bl_get_data(bd);
317 : uint8_t level;
318 :
319 : /* Convert brightness to hardware level */
320 0 : if (bd->props.brightness < 0)
321 0 : level = 0;
322 0 : else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
323 0 : level = RADEON_MAX_BL_LEVEL;
324 : else
325 0 : level = bd->props.brightness;
326 :
327 0 : if (pdata->negative)
328 0 : level = RADEON_MAX_BL_LEVEL - level;
329 :
330 0 : return level;
331 : }
332 :
333 0 : static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
334 : {
335 0 : struct radeon_backlight_privdata *pdata = bl_get_data(bd);
336 0 : struct radeon_encoder *radeon_encoder = pdata->encoder;
337 :
338 0 : radeon_legacy_set_backlight_level(radeon_encoder,
339 0 : radeon_legacy_lvds_level(bd));
340 :
341 0 : return 0;
342 : }
343 :
344 0 : static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
345 : {
346 0 : struct radeon_backlight_privdata *pdata = bl_get_data(bd);
347 0 : struct radeon_encoder *radeon_encoder = pdata->encoder;
348 0 : struct drm_device *dev = radeon_encoder->base.dev;
349 0 : struct radeon_device *rdev = dev->dev_private;
350 : uint8_t backlight_level;
351 :
352 0 : backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
353 0 : RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
354 :
355 0 : return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
356 : }
357 :
358 : static const struct backlight_ops radeon_backlight_ops = {
359 : .get_brightness = radeon_legacy_backlight_get_brightness,
360 : .update_status = radeon_legacy_backlight_update_status,
361 : };
362 :
363 0 : void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
364 : struct drm_connector *drm_connector)
365 : {
366 0 : struct drm_device *dev = radeon_encoder->base.dev;
367 0 : struct radeon_device *rdev = dev->dev_private;
368 : struct backlight_device *bd;
369 0 : struct backlight_properties props;
370 : struct radeon_backlight_privdata *pdata;
371 : uint8_t backlight_level;
372 0 : char bl_name[16];
373 :
374 0 : if (!radeon_encoder->enc_priv)
375 0 : return;
376 :
377 : #ifdef CONFIG_PMAC_BACKLIGHT
378 : if (!pmac_has_backlight_type("ati") &&
379 : !pmac_has_backlight_type("mnca"))
380 : return;
381 : #endif
382 :
383 0 : pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
384 0 : if (!pdata) {
385 0 : DRM_ERROR("Memory allocation failed\n");
386 0 : goto error;
387 : }
388 :
389 0 : memset(&props, 0, sizeof(props));
390 0 : props.max_brightness = RADEON_MAX_BL_LEVEL;
391 0 : props.type = BACKLIGHT_RAW;
392 : #ifdef notyet
393 : snprintf(bl_name, sizeof(bl_name),
394 : "radeon_bl%d", dev->primary->index);
395 : #else
396 0 : snprintf(bl_name, sizeof(bl_name),
397 : "radeon_bl%d", 0);
398 : #endif
399 0 : bd = backlight_device_register(bl_name, drm_connector->kdev,
400 : pdata, &radeon_backlight_ops, &props);
401 0 : if (IS_ERR(bd)) {
402 0 : DRM_ERROR("Backlight registration failed\n");
403 0 : goto error;
404 : }
405 :
406 0 : pdata->encoder = radeon_encoder;
407 :
408 0 : backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
409 0 : RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
410 :
411 : /* First, try to detect backlight level sense based on the assumption
412 : * that firmware set it up at full brightness
413 : */
414 0 : if (backlight_level == 0)
415 0 : pdata->negative = true;
416 0 : else if (backlight_level == 0xff)
417 0 : pdata->negative = false;
418 : else {
419 : /* XXX hack... maybe some day we can figure out in what direction
420 : * backlight should work on a given panel?
421 : */
422 0 : pdata->negative = (rdev->family != CHIP_RV200 &&
423 0 : rdev->family != CHIP_RV250 &&
424 0 : rdev->family != CHIP_RV280 &&
425 0 : rdev->family != CHIP_RV350);
426 :
427 : #ifdef CONFIG_PMAC_BACKLIGHT
428 : pdata->negative = (pdata->negative ||
429 : of_machine_is_compatible("PowerBook4,3") ||
430 : of_machine_is_compatible("PowerBook6,3") ||
431 : of_machine_is_compatible("PowerBook6,5"));
432 : #endif
433 : }
434 :
435 0 : if (rdev->is_atom_bios) {
436 0 : struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
437 0 : lvds->bl_dev = bd;
438 0 : } else {
439 0 : struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
440 0 : lvds->bl_dev = bd;
441 : }
442 :
443 0 : bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
444 0 : bd->props.power = FB_BLANK_UNBLANK;
445 0 : backlight_update_status(bd);
446 :
447 : DRM_INFO("radeon legacy LVDS backlight initialized\n");
448 0 : rdev->mode_info.bl_encoder = radeon_encoder;
449 :
450 0 : return;
451 :
452 : error:
453 0 : kfree(pdata);
454 0 : return;
455 0 : }
456 :
457 0 : static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
458 : {
459 0 : struct drm_device *dev = radeon_encoder->base.dev;
460 0 : struct radeon_device *rdev = dev->dev_private;
461 : struct backlight_device *bd = NULL;
462 :
463 0 : if (!radeon_encoder->enc_priv)
464 0 : return;
465 :
466 0 : if (rdev->is_atom_bios) {
467 0 : struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
468 0 : bd = lvds->bl_dev;
469 0 : lvds->bl_dev = NULL;
470 0 : } else {
471 0 : struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
472 0 : bd = lvds->bl_dev;
473 0 : lvds->bl_dev = NULL;
474 : }
475 :
476 0 : if (bd) {
477 : struct radeon_backlight_privdata *pdata;
478 :
479 0 : pdata = bl_get_data(bd);
480 0 : backlight_device_unregister(bd);
481 0 : kfree(pdata);
482 :
483 : DRM_INFO("radeon legacy LVDS backlight unloaded\n");
484 0 : }
485 0 : }
486 :
487 : #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
488 :
489 : void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
490 : {
491 : }
492 :
493 : static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
494 : {
495 : }
496 :
497 : #endif
498 :
499 :
500 0 : static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
501 : {
502 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
503 :
504 0 : if (radeon_encoder->enc_priv) {
505 0 : radeon_legacy_backlight_exit(radeon_encoder);
506 0 : kfree(radeon_encoder->enc_priv);
507 0 : }
508 0 : drm_encoder_cleanup(encoder);
509 0 : kfree(radeon_encoder);
510 0 : }
511 :
512 : static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
513 : .destroy = radeon_lvds_enc_destroy,
514 : };
515 :
516 0 : static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
517 : {
518 0 : struct drm_device *dev = encoder->dev;
519 0 : struct radeon_device *rdev = dev->dev_private;
520 0 : uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
521 0 : uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
522 0 : uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
523 :
524 : DRM_DEBUG_KMS("\n");
525 :
526 0 : switch (mode) {
527 : case DRM_MODE_DPMS_ON:
528 0 : crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
529 0 : dac_cntl &= ~RADEON_DAC_PDWN;
530 0 : dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
531 : RADEON_DAC_PDWN_G |
532 : RADEON_DAC_PDWN_B);
533 0 : break;
534 : case DRM_MODE_DPMS_STANDBY:
535 : case DRM_MODE_DPMS_SUSPEND:
536 : case DRM_MODE_DPMS_OFF:
537 0 : crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
538 0 : dac_cntl |= RADEON_DAC_PDWN;
539 0 : dac_macro_cntl |= (RADEON_DAC_PDWN_R |
540 : RADEON_DAC_PDWN_G |
541 : RADEON_DAC_PDWN_B);
542 0 : break;
543 : }
544 :
545 : /* handled in radeon_crtc_dpms() */
546 0 : if (!(rdev->flags & RADEON_SINGLE_CRTC))
547 0 : WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
548 0 : WREG32(RADEON_DAC_CNTL, dac_cntl);
549 0 : WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
550 :
551 0 : if (rdev->is_atom_bios)
552 0 : radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
553 : else
554 0 : radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
555 :
556 0 : }
557 :
558 0 : static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
559 : {
560 0 : struct radeon_device *rdev = encoder->dev->dev_private;
561 :
562 0 : if (rdev->is_atom_bios)
563 0 : radeon_atom_output_lock(encoder, true);
564 : else
565 0 : radeon_combios_output_lock(encoder, true);
566 0 : radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
567 0 : }
568 :
569 0 : static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
570 : {
571 0 : struct radeon_device *rdev = encoder->dev->dev_private;
572 :
573 0 : radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
574 :
575 0 : if (rdev->is_atom_bios)
576 0 : radeon_atom_output_lock(encoder, false);
577 : else
578 0 : radeon_combios_output_lock(encoder, false);
579 0 : }
580 :
581 0 : static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
582 : struct drm_display_mode *mode,
583 : struct drm_display_mode *adjusted_mode)
584 : {
585 0 : struct drm_device *dev = encoder->dev;
586 0 : struct radeon_device *rdev = dev->dev_private;
587 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
588 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
589 : uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
590 :
591 : DRM_DEBUG_KMS("\n");
592 :
593 0 : if (radeon_crtc->crtc_id == 0) {
594 0 : if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
595 0 : disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
596 : ~(RADEON_DISP_DAC_SOURCE_MASK);
597 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
598 0 : } else {
599 0 : dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
600 0 : WREG32(RADEON_DAC_CNTL2, dac2_cntl);
601 : }
602 : } else {
603 0 : if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
604 0 : disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
605 : ~(RADEON_DISP_DAC_SOURCE_MASK);
606 0 : disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
607 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
608 0 : } else {
609 0 : dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
610 0 : WREG32(RADEON_DAC_CNTL2, dac2_cntl);
611 : }
612 : }
613 :
614 : dac_cntl = (RADEON_DAC_MASK_ALL |
615 : RADEON_DAC_VGA_ADR_EN |
616 : /* TODO 6-bits */
617 : RADEON_DAC_8BIT_EN);
618 :
619 0 : WREG32_P(RADEON_DAC_CNTL,
620 : dac_cntl,
621 : RADEON_DAC_RANGE_CNTL |
622 : RADEON_DAC_BLANKING);
623 :
624 0 : if (radeon_encoder->enc_priv) {
625 0 : struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
626 0 : dac_macro_cntl = p_dac->ps2_pdac_adj;
627 0 : } else
628 0 : dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
629 0 : dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
630 0 : WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
631 :
632 0 : if (rdev->is_atom_bios)
633 0 : radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
634 : else
635 0 : radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
636 0 : }
637 :
638 0 : static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
639 : struct drm_connector *connector)
640 : {
641 0 : struct drm_device *dev = encoder->dev;
642 0 : struct radeon_device *rdev = dev->dev_private;
643 : uint32_t vclk_ecp_cntl, crtc_ext_cntl;
644 : uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
645 : enum drm_connector_status found = connector_status_disconnected;
646 : bool color = true;
647 :
648 : /* just don't bother on RN50 those chip are often connected to remoting
649 : * console hw and often we get failure to load detect those. So to make
650 : * everyone happy report the encoder as always connected.
651 : */
652 0 : if (ASIC_IS_RN50(rdev)) {
653 0 : return connector_status_connected;
654 : }
655 :
656 : /* save the regs we need */
657 0 : vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
658 0 : crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
659 0 : dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
660 0 : dac_cntl = RREG32(RADEON_DAC_CNTL);
661 0 : dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
662 :
663 0 : tmp = vclk_ecp_cntl &
664 : ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
665 0 : WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
666 :
667 0 : tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
668 0 : WREG32(RADEON_CRTC_EXT_CNTL, tmp);
669 :
670 : tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
671 : RADEON_DAC_FORCE_DATA_EN;
672 :
673 0 : if (color)
674 0 : tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
675 : else
676 : tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
677 :
678 0 : if (ASIC_IS_R300(rdev))
679 0 : tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
680 0 : else if (ASIC_IS_RV100(rdev))
681 0 : tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
682 : else
683 0 : tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
684 :
685 0 : WREG32(RADEON_DAC_EXT_CNTL, tmp);
686 :
687 0 : tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
688 0 : tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
689 0 : WREG32(RADEON_DAC_CNTL, tmp);
690 :
691 : tmp = dac_macro_cntl;
692 0 : tmp &= ~(RADEON_DAC_PDWN_R |
693 : RADEON_DAC_PDWN_G |
694 : RADEON_DAC_PDWN_B);
695 :
696 0 : WREG32(RADEON_DAC_MACRO_CNTL, tmp);
697 :
698 0 : mdelay(2);
699 :
700 0 : if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
701 0 : found = connector_status_connected;
702 :
703 : /* restore the regs we used */
704 0 : WREG32(RADEON_DAC_CNTL, dac_cntl);
705 0 : WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
706 0 : WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
707 0 : WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
708 0 : WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
709 :
710 0 : return found;
711 0 : }
712 :
713 : static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
714 : .dpms = radeon_legacy_primary_dac_dpms,
715 : .mode_fixup = radeon_legacy_mode_fixup,
716 : .prepare = radeon_legacy_primary_dac_prepare,
717 : .mode_set = radeon_legacy_primary_dac_mode_set,
718 : .commit = radeon_legacy_primary_dac_commit,
719 : .detect = radeon_legacy_primary_dac_detect,
720 : .disable = radeon_legacy_encoder_disable,
721 : };
722 :
723 :
724 : static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
725 : .destroy = radeon_enc_destroy,
726 : };
727 :
728 0 : static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
729 : {
730 0 : struct drm_device *dev = encoder->dev;
731 0 : struct radeon_device *rdev = dev->dev_private;
732 0 : uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
733 : DRM_DEBUG_KMS("\n");
734 :
735 0 : switch (mode) {
736 : case DRM_MODE_DPMS_ON:
737 0 : fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
738 0 : break;
739 : case DRM_MODE_DPMS_STANDBY:
740 : case DRM_MODE_DPMS_SUSPEND:
741 : case DRM_MODE_DPMS_OFF:
742 0 : fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
743 0 : break;
744 : }
745 :
746 0 : WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
747 :
748 0 : if (rdev->is_atom_bios)
749 0 : radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
750 : else
751 0 : radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
752 :
753 0 : }
754 :
755 0 : static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
756 : {
757 0 : struct radeon_device *rdev = encoder->dev->dev_private;
758 :
759 0 : if (rdev->is_atom_bios)
760 0 : radeon_atom_output_lock(encoder, true);
761 : else
762 0 : radeon_combios_output_lock(encoder, true);
763 0 : radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
764 0 : }
765 :
766 0 : static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
767 : {
768 0 : struct radeon_device *rdev = encoder->dev->dev_private;
769 :
770 0 : radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
771 :
772 0 : if (rdev->is_atom_bios)
773 0 : radeon_atom_output_lock(encoder, true);
774 : else
775 0 : radeon_combios_output_lock(encoder, true);
776 0 : }
777 :
778 0 : static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
779 : struct drm_display_mode *mode,
780 : struct drm_display_mode *adjusted_mode)
781 : {
782 0 : struct drm_device *dev = encoder->dev;
783 0 : struct radeon_device *rdev = dev->dev_private;
784 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
785 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
786 : uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
787 : int i;
788 :
789 : DRM_DEBUG_KMS("\n");
790 :
791 0 : tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
792 0 : tmp &= 0xfffff;
793 0 : if (rdev->family == CHIP_RV280) {
794 : /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
795 0 : tmp ^= (1 << 22);
796 0 : tmds_pll_cntl ^= (1 << 22);
797 0 : }
798 :
799 0 : if (radeon_encoder->enc_priv) {
800 0 : struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
801 :
802 0 : for (i = 0; i < 4; i++) {
803 0 : if (tmds->tmds_pll[i].freq == 0)
804 : break;
805 0 : if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
806 0 : tmp = tmds->tmds_pll[i].value ;
807 0 : break;
808 : }
809 : }
810 0 : }
811 :
812 0 : if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
813 0 : if (tmp & 0xfff00000)
814 0 : tmds_pll_cntl = tmp;
815 : else {
816 0 : tmds_pll_cntl &= 0xfff00000;
817 0 : tmds_pll_cntl |= tmp;
818 : }
819 : } else
820 : tmds_pll_cntl = tmp;
821 :
822 0 : tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
823 : ~(RADEON_TMDS_TRANSMITTER_PLLRST);
824 :
825 0 : if (rdev->family == CHIP_R200 ||
826 0 : rdev->family == CHIP_R100 ||
827 0 : ASIC_IS_R300(rdev))
828 0 : tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
829 : else /* RV chips got this bit reversed */
830 0 : tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
831 :
832 0 : fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
833 : (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
834 : RADEON_FP_CRTC_DONT_SHADOW_HEND));
835 :
836 0 : fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
837 :
838 0 : fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
839 : RADEON_FP_DFP_SYNC_SEL |
840 : RADEON_FP_CRT_SYNC_SEL |
841 : RADEON_FP_CRTC_LOCK_8DOT |
842 : RADEON_FP_USE_SHADOW_EN |
843 : RADEON_FP_CRTC_USE_SHADOW_VEND |
844 : RADEON_FP_CRT_SYNC_ALT);
845 :
846 : if (1) /* FIXME rgbBits == 8 */
847 0 : fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
848 : else
849 : fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
850 :
851 0 : if (radeon_crtc->crtc_id == 0) {
852 0 : if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
853 0 : fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
854 0 : if (radeon_encoder->rmx_type != RMX_OFF)
855 0 : fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
856 : else
857 : fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
858 : } else
859 0 : fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
860 : } else {
861 0 : if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
862 0 : fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
863 0 : fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
864 0 : } else
865 0 : fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
866 : }
867 :
868 0 : WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
869 0 : WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
870 0 : WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
871 :
872 0 : if (rdev->is_atom_bios)
873 0 : radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
874 : else
875 0 : radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
876 0 : }
877 :
878 : static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
879 : .dpms = radeon_legacy_tmds_int_dpms,
880 : .mode_fixup = radeon_legacy_mode_fixup,
881 : .prepare = radeon_legacy_tmds_int_prepare,
882 : .mode_set = radeon_legacy_tmds_int_mode_set,
883 : .commit = radeon_legacy_tmds_int_commit,
884 : .disable = radeon_legacy_encoder_disable,
885 : };
886 :
887 :
888 : static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
889 : .destroy = radeon_enc_destroy,
890 : };
891 :
892 0 : static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
893 : {
894 0 : struct drm_device *dev = encoder->dev;
895 0 : struct radeon_device *rdev = dev->dev_private;
896 0 : uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
897 : DRM_DEBUG_KMS("\n");
898 :
899 0 : switch (mode) {
900 : case DRM_MODE_DPMS_ON:
901 0 : fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
902 0 : fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
903 0 : break;
904 : case DRM_MODE_DPMS_STANDBY:
905 : case DRM_MODE_DPMS_SUSPEND:
906 : case DRM_MODE_DPMS_OFF:
907 0 : fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
908 0 : fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
909 0 : break;
910 : }
911 :
912 0 : WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
913 :
914 0 : if (rdev->is_atom_bios)
915 0 : radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
916 : else
917 0 : radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
918 :
919 0 : }
920 :
921 0 : static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
922 : {
923 0 : struct radeon_device *rdev = encoder->dev->dev_private;
924 :
925 0 : if (rdev->is_atom_bios)
926 0 : radeon_atom_output_lock(encoder, true);
927 : else
928 0 : radeon_combios_output_lock(encoder, true);
929 0 : radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
930 0 : }
931 :
932 0 : static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
933 : {
934 0 : struct radeon_device *rdev = encoder->dev->dev_private;
935 0 : radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
936 :
937 0 : if (rdev->is_atom_bios)
938 0 : radeon_atom_output_lock(encoder, false);
939 : else
940 0 : radeon_combios_output_lock(encoder, false);
941 0 : }
942 :
943 0 : static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
944 : struct drm_display_mode *mode,
945 : struct drm_display_mode *adjusted_mode)
946 : {
947 0 : struct drm_device *dev = encoder->dev;
948 0 : struct radeon_device *rdev = dev->dev_private;
949 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
950 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
951 : uint32_t fp2_gen_cntl;
952 :
953 : DRM_DEBUG_KMS("\n");
954 :
955 0 : if (rdev->is_atom_bios) {
956 0 : radeon_encoder->pixel_clock = adjusted_mode->clock;
957 0 : atombios_dvo_setup(encoder, ATOM_ENABLE);
958 0 : fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
959 0 : } else {
960 0 : fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
961 :
962 : if (1) /* FIXME rgbBits == 8 */
963 0 : fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
964 : else
965 : fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
966 :
967 0 : fp2_gen_cntl &= ~(RADEON_FP2_ON |
968 : RADEON_FP2_DVO_EN |
969 : RADEON_FP2_DVO_RATE_SEL_SDR);
970 :
971 : /* XXX: these are oem specific */
972 0 : if (ASIC_IS_R300(rdev)) {
973 0 : if ((dev->pdev->device == 0x4850) &&
974 0 : (dev->pdev->subsystem_vendor == 0x1028) &&
975 0 : (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
976 0 : fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
977 : else
978 0 : fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
979 :
980 : /*if (mode->clock > 165000)
981 : fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
982 : }
983 0 : if (!radeon_combios_external_tmds_setup(encoder))
984 0 : radeon_external_tmds_setup(encoder);
985 : }
986 :
987 0 : if (radeon_crtc->crtc_id == 0) {
988 0 : if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
989 0 : fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
990 0 : if (radeon_encoder->rmx_type != RMX_OFF)
991 0 : fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
992 : else
993 : fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
994 : } else
995 0 : fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
996 : } else {
997 0 : if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
998 0 : fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
999 0 : fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1000 0 : } else
1001 0 : fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
1002 : }
1003 :
1004 0 : WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1005 :
1006 0 : if (rdev->is_atom_bios)
1007 0 : radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1008 : else
1009 0 : radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1010 0 : }
1011 :
1012 0 : static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1013 : {
1014 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1015 : /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1016 0 : kfree(radeon_encoder->enc_priv);
1017 0 : drm_encoder_cleanup(encoder);
1018 0 : kfree(radeon_encoder);
1019 0 : }
1020 :
1021 : static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1022 : .dpms = radeon_legacy_tmds_ext_dpms,
1023 : .mode_fixup = radeon_legacy_mode_fixup,
1024 : .prepare = radeon_legacy_tmds_ext_prepare,
1025 : .mode_set = radeon_legacy_tmds_ext_mode_set,
1026 : .commit = radeon_legacy_tmds_ext_commit,
1027 : .disable = radeon_legacy_encoder_disable,
1028 : };
1029 :
1030 :
1031 : static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1032 : .destroy = radeon_ext_tmds_enc_destroy,
1033 : };
1034 :
1035 0 : static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1036 : {
1037 0 : struct drm_device *dev = encoder->dev;
1038 0 : struct radeon_device *rdev = dev->dev_private;
1039 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1040 : uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1041 : uint32_t tv_master_cntl = 0;
1042 : bool is_tv;
1043 : DRM_DEBUG_KMS("\n");
1044 :
1045 0 : is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1046 :
1047 0 : if (rdev->family == CHIP_R200)
1048 0 : fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1049 : else {
1050 0 : if (is_tv)
1051 0 : tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1052 : else
1053 0 : crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1054 0 : tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1055 : }
1056 :
1057 0 : switch (mode) {
1058 : case DRM_MODE_DPMS_ON:
1059 0 : if (rdev->family == CHIP_R200) {
1060 0 : fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1061 0 : } else {
1062 0 : if (is_tv)
1063 0 : tv_master_cntl |= RADEON_TV_ON;
1064 : else
1065 0 : crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1066 :
1067 0 : if (rdev->family == CHIP_R420 ||
1068 0 : rdev->family == CHIP_R423 ||
1069 0 : rdev->family == CHIP_RV410)
1070 0 : tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1071 : R420_TV_DAC_GDACPD |
1072 : R420_TV_DAC_BDACPD |
1073 : RADEON_TV_DAC_BGSLEEP);
1074 : else
1075 0 : tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1076 : RADEON_TV_DAC_GDACPD |
1077 : RADEON_TV_DAC_BDACPD |
1078 : RADEON_TV_DAC_BGSLEEP);
1079 : }
1080 : break;
1081 : case DRM_MODE_DPMS_STANDBY:
1082 : case DRM_MODE_DPMS_SUSPEND:
1083 : case DRM_MODE_DPMS_OFF:
1084 0 : if (rdev->family == CHIP_R200)
1085 0 : fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1086 : else {
1087 0 : if (is_tv)
1088 0 : tv_master_cntl &= ~RADEON_TV_ON;
1089 : else
1090 0 : crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1091 :
1092 0 : if (rdev->family == CHIP_R420 ||
1093 0 : rdev->family == CHIP_R423 ||
1094 0 : rdev->family == CHIP_RV410)
1095 0 : tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1096 : R420_TV_DAC_GDACPD |
1097 : R420_TV_DAC_BDACPD |
1098 : RADEON_TV_DAC_BGSLEEP);
1099 : else
1100 0 : tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1101 : RADEON_TV_DAC_GDACPD |
1102 : RADEON_TV_DAC_BDACPD |
1103 : RADEON_TV_DAC_BGSLEEP);
1104 : }
1105 : break;
1106 : }
1107 :
1108 0 : if (rdev->family == CHIP_R200) {
1109 0 : WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1110 0 : } else {
1111 0 : if (is_tv)
1112 0 : WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1113 : /* handled in radeon_crtc_dpms() */
1114 0 : else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1115 0 : WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1116 0 : WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1117 : }
1118 :
1119 0 : if (rdev->is_atom_bios)
1120 0 : radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1121 : else
1122 0 : radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1123 :
1124 0 : }
1125 :
1126 0 : static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1127 : {
1128 0 : struct radeon_device *rdev = encoder->dev->dev_private;
1129 :
1130 0 : if (rdev->is_atom_bios)
1131 0 : radeon_atom_output_lock(encoder, true);
1132 : else
1133 0 : radeon_combios_output_lock(encoder, true);
1134 0 : radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1135 0 : }
1136 :
1137 0 : static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1138 : {
1139 0 : struct radeon_device *rdev = encoder->dev->dev_private;
1140 :
1141 0 : radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1142 :
1143 0 : if (rdev->is_atom_bios)
1144 0 : radeon_atom_output_lock(encoder, true);
1145 : else
1146 0 : radeon_combios_output_lock(encoder, true);
1147 0 : }
1148 :
1149 0 : static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1150 : struct drm_display_mode *mode,
1151 : struct drm_display_mode *adjusted_mode)
1152 : {
1153 0 : struct drm_device *dev = encoder->dev;
1154 0 : struct radeon_device *rdev = dev->dev_private;
1155 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1156 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1157 0 : struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1158 : uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1159 : uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1160 : bool is_tv = false;
1161 :
1162 : DRM_DEBUG_KMS("\n");
1163 :
1164 0 : is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1165 :
1166 0 : if (rdev->family != CHIP_R200) {
1167 0 : tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1168 0 : if (rdev->family == CHIP_R420 ||
1169 0 : rdev->family == CHIP_R423 ||
1170 0 : rdev->family == CHIP_RV410) {
1171 0 : tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1172 : RADEON_TV_DAC_BGADJ_MASK |
1173 : R420_TV_DAC_DACADJ_MASK |
1174 : R420_TV_DAC_RDACPD |
1175 : R420_TV_DAC_GDACPD |
1176 : R420_TV_DAC_BDACPD |
1177 : R420_TV_DAC_TVENABLE);
1178 0 : } else {
1179 0 : tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1180 : RADEON_TV_DAC_BGADJ_MASK |
1181 : RADEON_TV_DAC_DACADJ_MASK |
1182 : RADEON_TV_DAC_RDACPD |
1183 : RADEON_TV_DAC_GDACPD |
1184 : RADEON_TV_DAC_BDACPD);
1185 : }
1186 :
1187 0 : tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1188 :
1189 0 : if (is_tv) {
1190 0 : if (tv_dac->tv_std == TV_STD_NTSC ||
1191 0 : tv_dac->tv_std == TV_STD_NTSC_J ||
1192 0 : tv_dac->tv_std == TV_STD_PAL_M ||
1193 0 : tv_dac->tv_std == TV_STD_PAL_60)
1194 0 : tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1195 : else
1196 0 : tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1197 :
1198 0 : if (tv_dac->tv_std == TV_STD_NTSC ||
1199 0 : tv_dac->tv_std == TV_STD_NTSC_J)
1200 0 : tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1201 : else
1202 : tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1203 : } else
1204 0 : tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1205 0 : tv_dac->ps2_tvdac_adj);
1206 :
1207 0 : WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1208 0 : }
1209 :
1210 0 : if (ASIC_IS_R300(rdev)) {
1211 0 : gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1212 0 : disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1213 0 : } else if (rdev->family != CHIP_R200)
1214 0 : disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1215 0 : else if (rdev->family == CHIP_R200)
1216 0 : fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1217 :
1218 0 : if (rdev->family >= CHIP_R200)
1219 0 : disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1220 :
1221 0 : if (is_tv) {
1222 : uint32_t dac_cntl;
1223 :
1224 0 : dac_cntl = RREG32(RADEON_DAC_CNTL);
1225 0 : dac_cntl &= ~RADEON_DAC_TVO_EN;
1226 0 : WREG32(RADEON_DAC_CNTL, dac_cntl);
1227 :
1228 0 : if (ASIC_IS_R300(rdev))
1229 0 : gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1230 :
1231 0 : dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1232 0 : if (radeon_crtc->crtc_id == 0) {
1233 0 : if (ASIC_IS_R300(rdev)) {
1234 0 : disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1235 0 : disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1236 : RADEON_DISP_TV_SOURCE_CRTC);
1237 0 : }
1238 0 : if (rdev->family >= CHIP_R200) {
1239 0 : disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1240 0 : } else {
1241 0 : disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1242 : }
1243 : } else {
1244 0 : if (ASIC_IS_R300(rdev)) {
1245 0 : disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1246 0 : disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1247 0 : }
1248 0 : if (rdev->family >= CHIP_R200) {
1249 0 : disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1250 0 : } else {
1251 0 : disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1252 : }
1253 : }
1254 0 : WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1255 0 : } else {
1256 :
1257 0 : dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1258 :
1259 0 : if (radeon_crtc->crtc_id == 0) {
1260 0 : if (ASIC_IS_R300(rdev)) {
1261 0 : disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1262 : disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1263 0 : } else if (rdev->family == CHIP_R200) {
1264 0 : fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1265 : RADEON_FP2_DVO_RATE_SEL_SDR);
1266 0 : } else
1267 0 : disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1268 : } else {
1269 0 : if (ASIC_IS_R300(rdev)) {
1270 0 : disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1271 0 : disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1272 0 : } else if (rdev->family == CHIP_R200) {
1273 0 : fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1274 : RADEON_FP2_DVO_RATE_SEL_SDR);
1275 0 : fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1276 0 : } else
1277 0 : disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1278 : }
1279 0 : WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1280 : }
1281 :
1282 0 : if (ASIC_IS_R300(rdev)) {
1283 0 : WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1284 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1285 0 : } else if (rdev->family != CHIP_R200)
1286 0 : WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1287 0 : else if (rdev->family == CHIP_R200)
1288 0 : WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1289 :
1290 0 : if (rdev->family >= CHIP_R200)
1291 0 : WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1292 :
1293 0 : if (is_tv)
1294 0 : radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1295 :
1296 0 : if (rdev->is_atom_bios)
1297 0 : radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1298 : else
1299 0 : radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1300 :
1301 0 : }
1302 :
1303 0 : static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1304 : struct drm_connector *connector)
1305 : {
1306 0 : struct drm_device *dev = encoder->dev;
1307 0 : struct radeon_device *rdev = dev->dev_private;
1308 : uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1309 : uint32_t disp_output_cntl, gpiopad_a, tmp;
1310 : bool found = false;
1311 :
1312 : /* save regs needed */
1313 0 : gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1314 0 : dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1315 0 : crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1316 0 : dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1317 0 : tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1318 0 : disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1319 :
1320 0 : WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1321 :
1322 0 : WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1323 :
1324 0 : WREG32(RADEON_CRTC2_GEN_CNTL,
1325 : RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1326 :
1327 0 : tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1328 0 : tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1329 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1330 :
1331 0 : WREG32(RADEON_DAC_EXT_CNTL,
1332 : RADEON_DAC2_FORCE_BLANK_OFF_EN |
1333 : RADEON_DAC2_FORCE_DATA_EN |
1334 : RADEON_DAC_FORCE_DATA_SEL_RGB |
1335 : (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1336 :
1337 0 : WREG32(RADEON_TV_DAC_CNTL,
1338 : RADEON_TV_DAC_STD_NTSC |
1339 : (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1340 : (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1341 :
1342 0 : RREG32(RADEON_TV_DAC_CNTL);
1343 0 : mdelay(4);
1344 :
1345 0 : WREG32(RADEON_TV_DAC_CNTL,
1346 : RADEON_TV_DAC_NBLANK |
1347 : RADEON_TV_DAC_NHOLD |
1348 : RADEON_TV_MONITOR_DETECT_EN |
1349 : RADEON_TV_DAC_STD_NTSC |
1350 : (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1351 : (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1352 :
1353 0 : RREG32(RADEON_TV_DAC_CNTL);
1354 0 : mdelay(6);
1355 :
1356 0 : tmp = RREG32(RADEON_TV_DAC_CNTL);
1357 0 : if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1358 : found = true;
1359 : DRM_DEBUG_KMS("S-video TV connection detected\n");
1360 0 : } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1361 : found = true;
1362 : DRM_DEBUG_KMS("Composite TV connection detected\n");
1363 0 : }
1364 :
1365 0 : WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1366 0 : WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1367 0 : WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1368 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1369 0 : WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1370 0 : WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1371 0 : return found;
1372 : }
1373 :
1374 0 : static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1375 : struct drm_connector *connector)
1376 : {
1377 0 : struct drm_device *dev = encoder->dev;
1378 0 : struct radeon_device *rdev = dev->dev_private;
1379 : uint32_t tv_dac_cntl, dac_cntl2;
1380 : uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1381 : bool found = false;
1382 :
1383 0 : if (ASIC_IS_R300(rdev))
1384 0 : return r300_legacy_tv_detect(encoder, connector);
1385 :
1386 0 : dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1387 0 : tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1388 0 : tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1389 0 : config_cntl = RREG32(RADEON_CONFIG_CNTL);
1390 0 : tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1391 :
1392 0 : tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1393 0 : WREG32(RADEON_DAC_CNTL2, tmp);
1394 :
1395 0 : tmp = tv_master_cntl | RADEON_TV_ON;
1396 0 : tmp &= ~(RADEON_TV_ASYNC_RST |
1397 : RADEON_RESTART_PHASE_FIX |
1398 : RADEON_CRT_FIFO_CE_EN |
1399 : RADEON_TV_FIFO_CE_EN |
1400 : RADEON_RE_SYNC_NOW_SEL_MASK);
1401 0 : tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1402 0 : WREG32(RADEON_TV_MASTER_CNTL, tmp);
1403 :
1404 : tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1405 : RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1406 : (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1407 :
1408 0 : if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1409 0 : tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1410 : else
1411 : tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1412 0 : WREG32(RADEON_TV_DAC_CNTL, tmp);
1413 :
1414 : tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1415 : RADEON_RED_MX_FORCE_DAC_DATA |
1416 : RADEON_GRN_MX_FORCE_DAC_DATA |
1417 : RADEON_BLU_MX_FORCE_DAC_DATA |
1418 : (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1419 0 : WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1420 :
1421 0 : mdelay(3);
1422 0 : tmp = RREG32(RADEON_TV_DAC_CNTL);
1423 0 : if (tmp & RADEON_TV_DAC_GDACDET) {
1424 : found = true;
1425 : DRM_DEBUG_KMS("S-video TV connection detected\n");
1426 0 : } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1427 : found = true;
1428 : DRM_DEBUG_KMS("Composite TV connection detected\n");
1429 0 : }
1430 :
1431 0 : WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1432 0 : WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1433 0 : WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1434 0 : WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1435 0 : return found;
1436 0 : }
1437 :
1438 0 : static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1439 : struct drm_connector *connector)
1440 : {
1441 0 : struct drm_device *dev = encoder->dev;
1442 0 : struct radeon_device *rdev = dev->dev_private;
1443 : uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1444 : uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1445 : uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1446 : uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1447 : uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1448 : bool found = false;
1449 : int i;
1450 :
1451 : /* save the regs we need */
1452 0 : gpio_monid = RREG32(RADEON_GPIO_MONID);
1453 0 : fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1454 0 : disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1455 0 : crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1456 0 : disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1457 0 : disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1458 0 : disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1459 0 : disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1460 0 : disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1461 0 : disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1462 0 : crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1463 0 : crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1464 0 : crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1465 0 : crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1466 :
1467 0 : tmp = RREG32(RADEON_GPIO_MONID);
1468 0 : tmp &= ~RADEON_GPIO_A_0;
1469 0 : WREG32(RADEON_GPIO_MONID, tmp);
1470 :
1471 0 : WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1472 : RADEON_FP2_PANEL_FORMAT |
1473 : R200_FP2_SOURCE_SEL_TRANS_UNIT |
1474 : RADEON_FP2_DVO_EN |
1475 : R200_FP2_DVO_RATE_SEL_SDR));
1476 :
1477 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1478 : RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1479 :
1480 0 : WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1481 : RADEON_CRTC2_DISP_REQ_EN_B));
1482 :
1483 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1484 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1485 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1486 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1487 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1488 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1489 :
1490 0 : WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1491 0 : WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1492 0 : WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1493 0 : WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1494 :
1495 0 : for (i = 0; i < 200; i++) {
1496 0 : tmp = RREG32(RADEON_GPIO_MONID);
1497 0 : if (tmp & RADEON_GPIO_Y_0)
1498 0 : found = true;
1499 :
1500 0 : if (found)
1501 : break;
1502 :
1503 0 : if (!drm_can_sleep())
1504 : mdelay(1);
1505 : else
1506 : drm_msleep(1);
1507 : }
1508 :
1509 : /* restore the regs we used */
1510 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1511 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1512 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1513 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1514 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1515 0 : WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1516 0 : WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1517 0 : WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1518 0 : WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1519 0 : WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1520 0 : WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1521 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1522 0 : WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1523 0 : WREG32(RADEON_GPIO_MONID, gpio_monid);
1524 :
1525 0 : return found;
1526 : }
1527 :
1528 0 : static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1529 : struct drm_connector *connector)
1530 : {
1531 0 : struct drm_device *dev = encoder->dev;
1532 0 : struct radeon_device *rdev = dev->dev_private;
1533 : uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1534 : uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1535 : uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1536 : enum drm_connector_status found = connector_status_disconnected;
1537 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1538 0 : struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1539 : bool color = true;
1540 : struct drm_crtc *crtc;
1541 :
1542 : /* find out if crtc2 is in use or if this encoder is using it */
1543 0 : list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1544 0 : struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1545 0 : if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1546 0 : if (encoder->crtc != crtc) {
1547 0 : return connector_status_disconnected;
1548 : }
1549 : }
1550 0 : }
1551 :
1552 0 : if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1553 0 : connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1554 0 : connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1555 : bool tv_detect;
1556 :
1557 0 : if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1558 0 : return connector_status_disconnected;
1559 :
1560 0 : tv_detect = radeon_legacy_tv_detect(encoder, connector);
1561 0 : if (tv_detect && tv_dac)
1562 0 : found = connector_status_connected;
1563 0 : return found;
1564 : }
1565 :
1566 : /* don't probe if the encoder is being used for something else not CRT related */
1567 0 : if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1568 : DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1569 0 : return connector_status_disconnected;
1570 : }
1571 :
1572 : /* R200 uses an external DAC for secondary DAC */
1573 0 : if (rdev->family == CHIP_R200) {
1574 0 : if (radeon_legacy_ext_dac_detect(encoder, connector))
1575 0 : found = connector_status_connected;
1576 0 : return found;
1577 : }
1578 :
1579 : /* save the regs we need */
1580 0 : pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1581 :
1582 0 : if (rdev->flags & RADEON_SINGLE_CRTC) {
1583 0 : crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1584 0 : } else {
1585 0 : if (ASIC_IS_R300(rdev)) {
1586 0 : gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1587 0 : disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1588 0 : } else {
1589 0 : disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1590 : }
1591 0 : crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1592 : }
1593 0 : tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1594 0 : dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1595 0 : dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1596 :
1597 0 : tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1598 : | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1599 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1600 :
1601 0 : if (rdev->flags & RADEON_SINGLE_CRTC) {
1602 0 : tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1603 0 : WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1604 0 : } else {
1605 0 : tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1606 0 : tmp |= RADEON_CRTC2_CRT2_ON |
1607 : (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1608 0 : WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1609 :
1610 0 : if (ASIC_IS_R300(rdev)) {
1611 0 : WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1612 0 : tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1613 0 : tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1614 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1615 0 : } else {
1616 0 : tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1617 0 : WREG32(RADEON_DISP_HW_DEBUG, tmp);
1618 : }
1619 : }
1620 :
1621 : tmp = RADEON_TV_DAC_NBLANK |
1622 : RADEON_TV_DAC_NHOLD |
1623 : RADEON_TV_MONITOR_DETECT_EN |
1624 : RADEON_TV_DAC_STD_PS2;
1625 :
1626 0 : WREG32(RADEON_TV_DAC_CNTL, tmp);
1627 :
1628 : tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1629 : RADEON_DAC2_FORCE_DATA_EN;
1630 :
1631 0 : if (color)
1632 0 : tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1633 : else
1634 : tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1635 :
1636 0 : if (ASIC_IS_R300(rdev))
1637 0 : tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1638 : else
1639 0 : tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1640 :
1641 0 : WREG32(RADEON_DAC_EXT_CNTL, tmp);
1642 :
1643 0 : tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1644 0 : WREG32(RADEON_DAC_CNTL2, tmp);
1645 :
1646 0 : mdelay(10);
1647 :
1648 0 : if (ASIC_IS_R300(rdev)) {
1649 0 : if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1650 0 : found = connector_status_connected;
1651 : } else {
1652 0 : if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1653 0 : found = connector_status_connected;
1654 : }
1655 :
1656 : /* restore regs we used */
1657 0 : WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1658 0 : WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1659 0 : WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1660 :
1661 0 : if (rdev->flags & RADEON_SINGLE_CRTC) {
1662 0 : WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1663 0 : } else {
1664 0 : WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1665 0 : if (ASIC_IS_R300(rdev)) {
1666 0 : WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1667 0 : WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1668 0 : } else {
1669 0 : WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1670 : }
1671 : }
1672 :
1673 0 : WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1674 :
1675 0 : return found;
1676 :
1677 0 : }
1678 :
1679 : static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1680 : .dpms = radeon_legacy_tv_dac_dpms,
1681 : .mode_fixup = radeon_legacy_mode_fixup,
1682 : .prepare = radeon_legacy_tv_dac_prepare,
1683 : .mode_set = radeon_legacy_tv_dac_mode_set,
1684 : .commit = radeon_legacy_tv_dac_commit,
1685 : .detect = radeon_legacy_tv_dac_detect,
1686 : .disable = radeon_legacy_encoder_disable,
1687 : };
1688 :
1689 :
1690 : static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1691 : .destroy = radeon_enc_destroy,
1692 : };
1693 :
1694 :
1695 0 : static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1696 : {
1697 0 : struct drm_device *dev = encoder->base.dev;
1698 0 : struct radeon_device *rdev = dev->dev_private;
1699 : struct radeon_encoder_int_tmds *tmds = NULL;
1700 : bool ret;
1701 :
1702 0 : tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1703 :
1704 0 : if (!tmds)
1705 0 : return NULL;
1706 :
1707 0 : if (rdev->is_atom_bios)
1708 0 : ret = radeon_atombios_get_tmds_info(encoder, tmds);
1709 : else
1710 0 : ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1711 :
1712 0 : if (ret == false)
1713 0 : radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1714 :
1715 0 : return tmds;
1716 0 : }
1717 :
1718 0 : static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1719 : {
1720 0 : struct drm_device *dev = encoder->base.dev;
1721 0 : struct radeon_device *rdev = dev->dev_private;
1722 : struct radeon_encoder_ext_tmds *tmds = NULL;
1723 : bool ret;
1724 :
1725 0 : if (rdev->is_atom_bios)
1726 0 : return NULL;
1727 :
1728 0 : tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1729 :
1730 0 : if (!tmds)
1731 0 : return NULL;
1732 :
1733 0 : ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1734 :
1735 0 : if (ret == false)
1736 0 : radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1737 :
1738 0 : return tmds;
1739 0 : }
1740 :
1741 : void
1742 0 : radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1743 : {
1744 0 : struct radeon_device *rdev = dev->dev_private;
1745 : struct drm_encoder *encoder;
1746 : struct radeon_encoder *radeon_encoder;
1747 :
1748 : /* see if we already added it */
1749 0 : list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1750 0 : radeon_encoder = to_radeon_encoder(encoder);
1751 0 : if (radeon_encoder->encoder_enum == encoder_enum) {
1752 0 : radeon_encoder->devices |= supported_device;
1753 0 : return;
1754 : }
1755 :
1756 : }
1757 :
1758 : /* add a new one */
1759 0 : radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1760 0 : if (!radeon_encoder)
1761 0 : return;
1762 :
1763 0 : encoder = &radeon_encoder->base;
1764 0 : if (rdev->flags & RADEON_SINGLE_CRTC)
1765 0 : encoder->possible_crtcs = 0x1;
1766 : else
1767 0 : encoder->possible_crtcs = 0x3;
1768 :
1769 0 : radeon_encoder->enc_priv = NULL;
1770 :
1771 0 : radeon_encoder->encoder_enum = encoder_enum;
1772 0 : radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1773 0 : radeon_encoder->devices = supported_device;
1774 0 : radeon_encoder->rmx_type = RMX_OFF;
1775 :
1776 0 : switch (radeon_encoder->encoder_id) {
1777 : case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1778 0 : encoder->possible_crtcs = 0x1;
1779 0 : drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1780 0 : drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1781 0 : if (rdev->is_atom_bios)
1782 0 : radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1783 : else
1784 0 : radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1785 0 : radeon_encoder->rmx_type = RMX_FULL;
1786 0 : break;
1787 : case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1788 0 : drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1789 0 : drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1790 0 : radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1791 0 : break;
1792 : case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1793 0 : drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1794 0 : drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1795 0 : if (rdev->is_atom_bios)
1796 0 : radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1797 : else
1798 0 : radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1799 : break;
1800 : case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1801 0 : drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1802 0 : drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1803 0 : if (rdev->is_atom_bios)
1804 0 : radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1805 : else
1806 0 : radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1807 : break;
1808 : case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1809 0 : drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1810 0 : drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1811 0 : if (!rdev->is_atom_bios)
1812 0 : radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1813 : break;
1814 : }
1815 0 : }
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