Line data Source code
1 : /*
2 : * Copyright 2014 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <dev/pci/drm/drmP.h>
25 : #include "radeon.h"
26 : #include "radeon_ucode.h"
27 :
28 0 : static void radeon_ucode_print_common_hdr(const struct common_firmware_header *hdr)
29 : {
30 : DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
31 : DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
32 : DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
33 : DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
34 : DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
35 : DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
36 : DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
37 : DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
38 : DRM_DEBUG("ucode_array_offset_bytes: %u\n",
39 : le32_to_cpu(hdr->ucode_array_offset_bytes));
40 : DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
41 0 : }
42 :
43 0 : void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
44 : {
45 0 : uint16_t version_major = le16_to_cpu(hdr->header_version_major);
46 0 : uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
47 :
48 : DRM_DEBUG("MC\n");
49 0 : radeon_ucode_print_common_hdr(hdr);
50 :
51 0 : if (version_major == 1) {
52 : #ifdef DRMDEBUG
53 : const struct mc_firmware_header_v1_0 *mc_hdr =
54 : container_of(hdr, struct mc_firmware_header_v1_0, header);
55 : #endif
56 :
57 : DRM_DEBUG("io_debug_size_bytes: %u\n",
58 : le32_to_cpu(mc_hdr->io_debug_size_bytes));
59 : DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
60 : le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
61 : } else {
62 0 : DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
63 : }
64 0 : }
65 :
66 0 : void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
67 : {
68 0 : uint16_t version_major = le16_to_cpu(hdr->header_version_major);
69 0 : uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
70 :
71 : DRM_DEBUG("SMC\n");
72 0 : radeon_ucode_print_common_hdr(hdr);
73 :
74 0 : if (version_major == 1) {
75 : #ifdef DRMDEBUG
76 : const struct smc_firmware_header_v1_0 *smc_hdr =
77 : container_of(hdr, struct smc_firmware_header_v1_0, header);
78 : #endif
79 :
80 : DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr));
81 : } else {
82 0 : DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
83 : }
84 0 : }
85 :
86 0 : void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
87 : {
88 0 : uint16_t version_major = le16_to_cpu(hdr->header_version_major);
89 0 : uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
90 :
91 : DRM_DEBUG("GFX\n");
92 0 : radeon_ucode_print_common_hdr(hdr);
93 :
94 0 : if (version_major == 1) {
95 : #ifdef DRMDEBUG
96 : const struct gfx_firmware_header_v1_0 *gfx_hdr =
97 : container_of(hdr, struct gfx_firmware_header_v1_0, header);
98 : #endif
99 :
100 : DRM_DEBUG("ucode_feature_version: %u\n",
101 : le32_to_cpu(gfx_hdr->ucode_feature_version));
102 : DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
103 : DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
104 : } else {
105 0 : DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
106 : }
107 0 : }
108 :
109 0 : void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
110 : {
111 0 : uint16_t version_major = le16_to_cpu(hdr->header_version_major);
112 0 : uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
113 :
114 : DRM_DEBUG("RLC\n");
115 0 : radeon_ucode_print_common_hdr(hdr);
116 :
117 0 : if (version_major == 1) {
118 : #ifdef DRMDEBUG
119 : const struct rlc_firmware_header_v1_0 *rlc_hdr =
120 : container_of(hdr, struct rlc_firmware_header_v1_0, header);
121 : #endif
122 :
123 : DRM_DEBUG("ucode_feature_version: %u\n",
124 : le32_to_cpu(rlc_hdr->ucode_feature_version));
125 : DRM_DEBUG("save_and_restore_offset: %u\n",
126 : le32_to_cpu(rlc_hdr->save_and_restore_offset));
127 : DRM_DEBUG("clear_state_descriptor_offset: %u\n",
128 : le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
129 : DRM_DEBUG("avail_scratch_ram_locations: %u\n",
130 : le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
131 : DRM_DEBUG("master_pkt_description_offset: %u\n",
132 : le32_to_cpu(rlc_hdr->master_pkt_description_offset));
133 : } else {
134 0 : DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
135 : }
136 0 : }
137 :
138 0 : void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
139 : {
140 0 : uint16_t version_major = le16_to_cpu(hdr->header_version_major);
141 0 : uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
142 :
143 : DRM_DEBUG("SDMA\n");
144 0 : radeon_ucode_print_common_hdr(hdr);
145 :
146 0 : if (version_major == 1) {
147 : #ifdef DRMDEBUG
148 : const struct sdma_firmware_header_v1_0 *sdma_hdr =
149 : container_of(hdr, struct sdma_firmware_header_v1_0, header);
150 : #endif
151 :
152 : DRM_DEBUG("ucode_feature_version: %u\n",
153 : le32_to_cpu(sdma_hdr->ucode_feature_version));
154 : DRM_DEBUG("ucode_change_version: %u\n",
155 : le32_to_cpu(sdma_hdr->ucode_change_version));
156 : DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
157 : DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
158 : } else {
159 0 : DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
160 : version_major, version_minor);
161 : }
162 0 : }
163 :
164 0 : int radeon_ucode_validate(const struct firmware *fw)
165 : {
166 : const struct common_firmware_header *hdr =
167 0 : (const struct common_firmware_header *)fw->data;
168 :
169 0 : if (fw->size == le32_to_cpu(hdr->size_bytes))
170 0 : return 0;
171 :
172 0 : return -EINVAL;
173 0 : }
174 :
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