Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #include <dev/pci/drm/drmP.h>
29 : #include "radeon.h"
30 : #include "radeon_asic.h"
31 : #include "rs400d.h"
32 :
33 : /* This files gather functions specifics to : rs400,rs480 */
34 : static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
35 :
36 0 : void rs400_gart_adjust_size(struct radeon_device *rdev)
37 : {
38 : /* Check gart size */
39 0 : switch (rdev->mc.gtt_size/(1024*1024)) {
40 : case 32:
41 : case 64:
42 : case 128:
43 : case 256:
44 : case 512:
45 : case 1024:
46 : case 2048:
47 : break;
48 : default:
49 0 : DRM_ERROR("Unable to use IGP GART size %uM\n",
50 : (unsigned)(rdev->mc.gtt_size >> 20));
51 0 : DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
52 0 : DRM_ERROR("Forcing to 32M GART size\n");
53 0 : rdev->mc.gtt_size = 32 * 1024 * 1024;
54 0 : return;
55 : }
56 0 : }
57 :
58 0 : void rs400_gart_tlb_flush(struct radeon_device *rdev)
59 : {
60 : uint32_t tmp;
61 0 : unsigned int timeout = rdev->usec_timeout;
62 :
63 0 : WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
64 0 : do {
65 0 : tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
66 0 : if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
67 : break;
68 0 : DRM_UDELAY(1);
69 0 : timeout--;
70 0 : } while (timeout > 0);
71 0 : WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
72 0 : }
73 :
74 0 : int rs400_gart_init(struct radeon_device *rdev)
75 : {
76 : int r;
77 :
78 0 : if (rdev->gart.ptr) {
79 0 : WARN(1, "RS400 GART already initialized\n");
80 0 : return 0;
81 : }
82 : /* Check gart size */
83 0 : switch(rdev->mc.gtt_size / (1024 * 1024)) {
84 : case 32:
85 : case 64:
86 : case 128:
87 : case 256:
88 : case 512:
89 : case 1024:
90 : case 2048:
91 : break;
92 : default:
93 0 : return -EINVAL;
94 : }
95 : /* Initialize common gart structure */
96 0 : r = radeon_gart_init(rdev);
97 0 : if (r)
98 0 : return r;
99 0 : if (rs400_debugfs_pcie_gart_info_init(rdev))
100 0 : DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
101 0 : rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
102 0 : return radeon_gart_table_ram_alloc(rdev);
103 0 : }
104 :
105 0 : int rs400_gart_enable(struct radeon_device *rdev)
106 : {
107 : uint32_t size_reg;
108 : uint32_t tmp;
109 :
110 0 : tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
111 0 : tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
112 0 : WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
113 : /* Check gart size */
114 0 : switch(rdev->mc.gtt_size / (1024 * 1024)) {
115 : case 32:
116 : size_reg = RS480_VA_SIZE_32MB;
117 0 : break;
118 : case 64:
119 : size_reg = RS480_VA_SIZE_64MB;
120 0 : break;
121 : case 128:
122 : size_reg = RS480_VA_SIZE_128MB;
123 0 : break;
124 : case 256:
125 : size_reg = RS480_VA_SIZE_256MB;
126 0 : break;
127 : case 512:
128 : size_reg = RS480_VA_SIZE_512MB;
129 0 : break;
130 : case 1024:
131 : size_reg = RS480_VA_SIZE_1GB;
132 0 : break;
133 : case 2048:
134 : size_reg = RS480_VA_SIZE_2GB;
135 0 : break;
136 : default:
137 0 : return -EINVAL;
138 : }
139 : /* It should be fine to program it to max value */
140 0 : if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
141 0 : WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
142 0 : WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
143 0 : } else {
144 0 : WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
145 0 : WREG32(RS480_AGP_BASE_2, 0);
146 : }
147 0 : tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
148 0 : tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
149 0 : if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
150 0 : WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
151 0 : tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
152 0 : WREG32(RADEON_BUS_CNTL, tmp);
153 0 : } else {
154 0 : WREG32(RADEON_MC_AGP_LOCATION, tmp);
155 0 : tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
156 0 : WREG32(RADEON_BUS_CNTL, tmp);
157 : }
158 : /* Table should be in 32bits address space so ignore bits above. */
159 0 : tmp = (u32)rdev->gart.table_addr & 0xfffff000;
160 0 : tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
161 :
162 0 : WREG32_MC(RS480_GART_BASE, tmp);
163 : /* TODO: more tweaking here */
164 0 : WREG32_MC(RS480_GART_FEATURE_ID,
165 : (RS480_TLB_ENABLE |
166 : RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
167 : /* Disable snooping */
168 0 : WREG32_MC(RS480_AGP_MODE_CNTL,
169 : (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
170 : /* Disable AGP mode */
171 : /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
172 : * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
173 0 : if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
174 0 : tmp = RREG32_MC(RS480_MC_MISC_CNTL);
175 0 : tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
176 0 : WREG32_MC(RS480_MC_MISC_CNTL, tmp);
177 0 : } else {
178 0 : tmp = RREG32_MC(RS480_MC_MISC_CNTL);
179 0 : tmp |= RS480_GART_INDEX_REG_EN;
180 0 : WREG32_MC(RS480_MC_MISC_CNTL, tmp);
181 : }
182 : /* Enable gart */
183 0 : WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
184 0 : rs400_gart_tlb_flush(rdev);
185 : DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
186 : (unsigned)(rdev->mc.gtt_size >> 20),
187 : (unsigned long long)rdev->gart.table_addr);
188 0 : rdev->gart.ready = true;
189 0 : return 0;
190 0 : }
191 :
192 0 : void rs400_gart_disable(struct radeon_device *rdev)
193 : {
194 : uint32_t tmp;
195 :
196 0 : tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
197 0 : tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
198 0 : WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
199 0 : WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
200 0 : }
201 :
202 0 : void rs400_gart_fini(struct radeon_device *rdev)
203 : {
204 0 : radeon_gart_fini(rdev);
205 0 : rs400_gart_disable(rdev);
206 0 : radeon_gart_table_ram_free(rdev);
207 0 : }
208 :
209 : #define RS400_PTE_UNSNOOPED (1 << 0)
210 : #define RS400_PTE_WRITEABLE (1 << 2)
211 : #define RS400_PTE_READABLE (1 << 3)
212 :
213 0 : uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags)
214 : {
215 : uint32_t entry;
216 :
217 0 : entry = (lower_32_bits(addr) & ~PAGE_MASK) |
218 0 : ((upper_32_bits(addr) & 0xff) << 4);
219 0 : if (flags & RADEON_GART_PAGE_READ)
220 0 : entry |= RS400_PTE_READABLE;
221 0 : if (flags & RADEON_GART_PAGE_WRITE)
222 0 : entry |= RS400_PTE_WRITEABLE;
223 0 : if (!(flags & RADEON_GART_PAGE_SNOOP))
224 0 : entry |= RS400_PTE_UNSNOOPED;
225 0 : return entry;
226 : }
227 :
228 0 : void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
229 : uint64_t entry)
230 : {
231 0 : u32 *gtt = rdev->gart.ptr;
232 0 : gtt[i] = cpu_to_le32(lower_32_bits(entry));
233 0 : }
234 :
235 0 : int rs400_mc_wait_for_idle(struct radeon_device *rdev)
236 : {
237 : unsigned i;
238 : uint32_t tmp;
239 :
240 0 : for (i = 0; i < rdev->usec_timeout; i++) {
241 : /* read MC_STATUS */
242 0 : tmp = RREG32(RADEON_MC_STATUS);
243 0 : if (tmp & RADEON_MC_IDLE) {
244 0 : return 0;
245 : }
246 0 : DRM_UDELAY(1);
247 : }
248 0 : return -1;
249 0 : }
250 :
251 0 : static void rs400_gpu_init(struct radeon_device *rdev)
252 : {
253 : /* FIXME: is this correct ? */
254 0 : r420_pipes_init(rdev);
255 0 : if (rs400_mc_wait_for_idle(rdev)) {
256 0 : printk(KERN_WARNING "rs400: Failed to wait MC idle while "
257 : "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
258 0 : }
259 0 : }
260 :
261 0 : static void rs400_mc_init(struct radeon_device *rdev)
262 : {
263 : u64 base;
264 :
265 0 : rs400_gart_adjust_size(rdev);
266 0 : rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
267 : /* DDR for all card after R300 & IGP */
268 0 : rdev->mc.vram_is_ddr = true;
269 0 : rdev->mc.vram_width = 128;
270 0 : r100_vram_init_sizes(rdev);
271 0 : base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
272 0 : radeon_vram_location(rdev, &rdev->mc, base);
273 0 : rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
274 0 : radeon_gtt_location(rdev, &rdev->mc);
275 0 : radeon_update_bandwidth_info(rdev);
276 0 : }
277 :
278 0 : uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
279 : {
280 : unsigned long flags;
281 : uint32_t r;
282 :
283 0 : spin_lock_irqsave(&rdev->mc_idx_lock, flags);
284 0 : WREG32(RS480_NB_MC_INDEX, reg & 0xff);
285 0 : r = RREG32(RS480_NB_MC_DATA);
286 0 : WREG32(RS480_NB_MC_INDEX, 0xff);
287 0 : spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
288 0 : return r;
289 : }
290 :
291 0 : void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
292 : {
293 : unsigned long flags;
294 :
295 0 : spin_lock_irqsave(&rdev->mc_idx_lock, flags);
296 0 : WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
297 0 : WREG32(RS480_NB_MC_DATA, (v));
298 0 : WREG32(RS480_NB_MC_INDEX, 0xff);
299 0 : spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
300 0 : }
301 :
302 : #if defined(CONFIG_DEBUG_FS)
303 : static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
304 : {
305 : struct drm_info_node *node = (struct drm_info_node *) m->private;
306 : struct drm_device *dev = node->minor->dev;
307 : struct radeon_device *rdev = dev->dev_private;
308 : uint32_t tmp;
309 :
310 : tmp = RREG32(RADEON_HOST_PATH_CNTL);
311 : seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
312 : tmp = RREG32(RADEON_BUS_CNTL);
313 : seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
314 : tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
315 : seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
316 : if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
317 : tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
318 : seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
319 : tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
320 : seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
321 : tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
322 : seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
323 : tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
324 : seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
325 : tmp = RREG32(RS690_HDP_FB_LOCATION);
326 : seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
327 : } else {
328 : tmp = RREG32(RADEON_AGP_BASE);
329 : seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
330 : tmp = RREG32(RS480_AGP_BASE_2);
331 : seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
332 : tmp = RREG32(RADEON_MC_AGP_LOCATION);
333 : seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
334 : }
335 : tmp = RREG32_MC(RS480_GART_BASE);
336 : seq_printf(m, "GART_BASE 0x%08x\n", tmp);
337 : tmp = RREG32_MC(RS480_GART_FEATURE_ID);
338 : seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
339 : tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
340 : seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
341 : tmp = RREG32_MC(RS480_MC_MISC_CNTL);
342 : seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
343 : tmp = RREG32_MC(0x5F);
344 : seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
345 : tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
346 : seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
347 : tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
348 : seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
349 : tmp = RREG32_MC(0x3B);
350 : seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
351 : tmp = RREG32_MC(0x3C);
352 : seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
353 : tmp = RREG32_MC(0x30);
354 : seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
355 : tmp = RREG32_MC(0x31);
356 : seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
357 : tmp = RREG32_MC(0x32);
358 : seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
359 : tmp = RREG32_MC(0x33);
360 : seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
361 : tmp = RREG32_MC(0x34);
362 : seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
363 : tmp = RREG32_MC(0x35);
364 : seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
365 : tmp = RREG32_MC(0x36);
366 : seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
367 : tmp = RREG32_MC(0x37);
368 : seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
369 : return 0;
370 : }
371 :
372 : static struct drm_info_list rs400_gart_info_list[] = {
373 : {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
374 : };
375 : #endif
376 :
377 0 : static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
378 : {
379 : #if defined(CONFIG_DEBUG_FS)
380 : return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
381 : #else
382 0 : return 0;
383 : #endif
384 : }
385 :
386 0 : static void rs400_mc_program(struct radeon_device *rdev)
387 : {
388 0 : struct r100_mc_save save;
389 :
390 : /* Stops all mc clients */
391 0 : r100_mc_stop(rdev, &save);
392 :
393 : /* Wait for mc idle */
394 0 : if (rs400_mc_wait_for_idle(rdev))
395 0 : dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
396 0 : WREG32(R_000148_MC_FB_LOCATION,
397 : S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
398 : S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
399 :
400 0 : r100_mc_resume(rdev, &save);
401 0 : }
402 :
403 0 : static int rs400_startup(struct radeon_device *rdev)
404 : {
405 : int r;
406 :
407 0 : r100_set_common_regs(rdev);
408 :
409 0 : rs400_mc_program(rdev);
410 : /* Resume clock */
411 0 : r300_clock_startup(rdev);
412 : /* Initialize GPU configuration (# pipes, ...) */
413 0 : rs400_gpu_init(rdev);
414 0 : r100_enable_bm(rdev);
415 : /* Initialize GART (initialize after TTM so we can allocate
416 : * memory through TTM but finalize after TTM) */
417 0 : r = rs400_gart_enable(rdev);
418 0 : if (r)
419 0 : return r;
420 :
421 : /* allocate wb buffer */
422 0 : r = radeon_wb_init(rdev);
423 0 : if (r)
424 0 : return r;
425 :
426 0 : r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
427 0 : if (r) {
428 0 : dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
429 0 : return r;
430 : }
431 :
432 : /* Enable IRQ */
433 0 : if (!rdev->irq.installed) {
434 0 : r = radeon_irq_kms_init(rdev);
435 0 : if (r)
436 0 : return r;
437 : }
438 :
439 0 : r100_irq_set(rdev);
440 0 : rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
441 : /* 1M ring buffer */
442 0 : r = r100_cp_init(rdev, 1024 * 1024);
443 0 : if (r) {
444 0 : dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
445 0 : return r;
446 : }
447 :
448 0 : r = radeon_ib_pool_init(rdev);
449 0 : if (r) {
450 0 : dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
451 0 : return r;
452 : }
453 :
454 0 : return 0;
455 0 : }
456 :
457 0 : int rs400_resume(struct radeon_device *rdev)
458 : {
459 : int r;
460 :
461 : /* Make sur GART are not working */
462 0 : rs400_gart_disable(rdev);
463 : /* Resume clock before doing reset */
464 0 : r300_clock_startup(rdev);
465 : /* setup MC before calling post tables */
466 0 : rs400_mc_program(rdev);
467 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
468 0 : if (radeon_asic_reset(rdev)) {
469 0 : dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
470 : RREG32(R_000E40_RBBM_STATUS),
471 : RREG32(R_0007C0_CP_STAT));
472 0 : }
473 : /* post */
474 0 : radeon_combios_asic_init(rdev->ddev);
475 : /* Resume clock after posting */
476 0 : r300_clock_startup(rdev);
477 : /* Initialize surface registers */
478 0 : radeon_surface_init(rdev);
479 :
480 0 : rdev->accel_working = true;
481 0 : r = rs400_startup(rdev);
482 0 : if (r) {
483 0 : rdev->accel_working = false;
484 0 : }
485 0 : return r;
486 : }
487 :
488 0 : int rs400_suspend(struct radeon_device *rdev)
489 : {
490 0 : radeon_pm_suspend(rdev);
491 0 : r100_cp_disable(rdev);
492 0 : radeon_wb_disable(rdev);
493 0 : r100_irq_disable(rdev);
494 0 : rs400_gart_disable(rdev);
495 0 : return 0;
496 : }
497 :
498 0 : void rs400_fini(struct radeon_device *rdev)
499 : {
500 0 : radeon_pm_fini(rdev);
501 0 : r100_cp_fini(rdev);
502 0 : radeon_wb_fini(rdev);
503 0 : radeon_ib_pool_fini(rdev);
504 0 : radeon_gem_fini(rdev);
505 0 : rs400_gart_fini(rdev);
506 0 : radeon_irq_kms_fini(rdev);
507 0 : radeon_fence_driver_fini(rdev);
508 0 : radeon_bo_fini(rdev);
509 0 : radeon_atombios_fini(rdev);
510 0 : kfree(rdev->bios);
511 0 : rdev->bios = NULL;
512 0 : }
513 :
514 0 : int rs400_init(struct radeon_device *rdev)
515 : {
516 : int r;
517 :
518 : /* Disable VGA */
519 0 : r100_vga_render_disable(rdev);
520 : /* Initialize scratch registers */
521 0 : radeon_scratch_init(rdev);
522 : /* Initialize surface registers */
523 0 : radeon_surface_init(rdev);
524 : /* TODO: disable VGA need to use VGA request */
525 : /* restore some register to sane defaults */
526 0 : r100_restore_sanity(rdev);
527 : /* BIOS*/
528 0 : if (!radeon_get_bios(rdev)) {
529 0 : if (ASIC_IS_AVIVO(rdev))
530 0 : return -EINVAL;
531 : }
532 0 : if (rdev->is_atom_bios) {
533 0 : dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
534 0 : return -EINVAL;
535 : } else {
536 0 : r = radeon_combios_init(rdev);
537 0 : if (r)
538 0 : return r;
539 : }
540 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
541 0 : if (radeon_asic_reset(rdev)) {
542 0 : dev_warn(rdev->dev,
543 : "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
544 : RREG32(R_000E40_RBBM_STATUS),
545 : RREG32(R_0007C0_CP_STAT));
546 0 : }
547 : /* check if cards are posted or not */
548 0 : if (radeon_boot_test_post_card(rdev) == false)
549 0 : return -EINVAL;
550 :
551 : /* Initialize clocks */
552 0 : radeon_get_clock_info(rdev->ddev);
553 : /* initialize memory controller */
554 0 : rs400_mc_init(rdev);
555 : /* Fence driver */
556 0 : r = radeon_fence_driver_init(rdev);
557 0 : if (r)
558 0 : return r;
559 : /* Memory manager */
560 0 : r = radeon_bo_init(rdev);
561 0 : if (r)
562 0 : return r;
563 0 : r = rs400_gart_init(rdev);
564 0 : if (r)
565 0 : return r;
566 0 : r300_set_reg_safe(rdev);
567 :
568 : /* Initialize power management */
569 0 : radeon_pm_init(rdev);
570 :
571 0 : rdev->accel_working = true;
572 0 : r = rs400_startup(rdev);
573 0 : if (r) {
574 : /* Somethings want wront with the accel init stop accel */
575 0 : dev_err(rdev->dev, "Disabling GPU acceleration\n");
576 0 : r100_cp_fini(rdev);
577 0 : radeon_wb_fini(rdev);
578 0 : radeon_ib_pool_fini(rdev);
579 0 : rs400_gart_fini(rdev);
580 0 : radeon_irq_kms_fini(rdev);
581 0 : rdev->accel_working = false;
582 0 : }
583 0 : return 0;
584 0 : }
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