Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : /* RS600 / Radeon X1250/X1270 integrated GPU
29 : *
30 : * This file gather function specific to RS600 which is the IGP of
31 : * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 : * is the X1250/X1270 supporting AMD CPU). The display engine are
33 : * the avivo one, bios is an atombios, 3D block are the one of the
34 : * R4XX family. The GART is different from the RS400 one and is very
35 : * close to the one of the R600 family (R600 likely being an evolution
36 : * of the RS600 GART block).
37 : */
38 : #include <dev/pci/drm/drmP.h>
39 : #include "radeon.h"
40 : #include "radeon_asic.h"
41 : #include "radeon_audio.h"
42 : #include "atom.h"
43 : #include "rs600d.h"
44 :
45 : #include "rs600_reg_safe.h"
46 :
47 : static void rs600_gpu_init(struct radeon_device *rdev);
48 : int rs600_mc_wait_for_idle(struct radeon_device *rdev);
49 :
50 : static const u32 crtc_offsets[2] =
51 : {
52 : 0,
53 : AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
54 : };
55 :
56 0 : static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
57 : {
58 0 : if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
59 0 : return true;
60 : else
61 0 : return false;
62 0 : }
63 :
64 0 : static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
65 : {
66 : u32 pos1, pos2;
67 :
68 0 : pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
69 0 : pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
70 :
71 0 : if (pos1 != pos2)
72 0 : return true;
73 : else
74 0 : return false;
75 0 : }
76 :
77 : /**
78 : * avivo_wait_for_vblank - vblank wait asic callback.
79 : *
80 : * @rdev: radeon_device pointer
81 : * @crtc: crtc to wait for vblank on
82 : *
83 : * Wait for vblank on the requested crtc (r5xx-r7xx).
84 : */
85 0 : void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
86 : {
87 : unsigned i = 0;
88 :
89 0 : if (crtc >= rdev->num_crtc)
90 0 : return;
91 :
92 0 : if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
93 0 : return;
94 :
95 : /* depending on when we hit vblank, we may be close to active; if so,
96 : * wait for another frame.
97 : */
98 0 : while (avivo_is_in_vblank(rdev, crtc)) {
99 0 : if (i++ % 100 == 0) {
100 0 : if (!avivo_is_counter_moving(rdev, crtc))
101 : break;
102 : }
103 : }
104 :
105 0 : while (!avivo_is_in_vblank(rdev, crtc)) {
106 0 : if (i++ % 100 == 0) {
107 0 : if (!avivo_is_counter_moving(rdev, crtc))
108 : break;
109 : }
110 : }
111 0 : }
112 :
113 0 : void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
114 : {
115 0 : struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
116 0 : u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
117 : int i;
118 :
119 : /* Lock the graphics update lock */
120 0 : tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
121 0 : WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
122 :
123 : /* update the scanout addresses */
124 0 : WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
125 : (u32)crtc_base);
126 0 : WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
127 : (u32)crtc_base);
128 :
129 : /* Wait for update_pending to go high. */
130 0 : for (i = 0; i < rdev->usec_timeout; i++) {
131 0 : if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
132 : break;
133 0 : udelay(1);
134 : }
135 : DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
136 :
137 : /* Unlock the lock, so double-buffering can take place inside vblank */
138 0 : tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
139 0 : WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
140 0 : }
141 :
142 0 : bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
143 : {
144 0 : struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
145 :
146 : /* Return current update_pending status: */
147 0 : return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
148 : AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
149 : }
150 :
151 0 : void avivo_program_fmt(struct drm_encoder *encoder)
152 : {
153 0 : struct drm_device *dev = encoder->dev;
154 0 : struct radeon_device *rdev = dev->dev_private;
155 0 : struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
156 0 : struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
157 : int bpc = 0;
158 : u32 tmp = 0;
159 : enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
160 :
161 0 : if (connector) {
162 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
163 0 : bpc = radeon_get_monitor_bpc(connector);
164 0 : dither = radeon_connector->dither;
165 0 : }
166 :
167 : /* LVDS FMT is set up by atom */
168 0 : if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
169 0 : return;
170 :
171 0 : if (bpc == 0)
172 0 : return;
173 :
174 0 : switch (bpc) {
175 : case 6:
176 0 : if (dither == RADEON_FMT_DITHER_ENABLE)
177 : /* XXX sort out optimal dither settings */
178 0 : tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
179 : else
180 : tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
181 : break;
182 : case 8:
183 0 : if (dither == RADEON_FMT_DITHER_ENABLE)
184 : /* XXX sort out optimal dither settings */
185 0 : tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
186 : AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
187 : else
188 : tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
189 : AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
190 : break;
191 : case 10:
192 : default:
193 : /* not needed */
194 : break;
195 : }
196 :
197 0 : switch (radeon_encoder->encoder_id) {
198 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
199 0 : WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
200 0 : break;
201 : case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
202 0 : WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
203 0 : break;
204 : case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
205 0 : WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
206 0 : break;
207 : case ENCODER_OBJECT_ID_INTERNAL_DDI:
208 0 : WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
209 0 : break;
210 : default:
211 : break;
212 : }
213 0 : }
214 :
215 0 : void rs600_pm_misc(struct radeon_device *rdev)
216 : {
217 0 : int requested_index = rdev->pm.requested_power_state_index;
218 0 : struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
219 0 : struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
220 : u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
221 : u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
222 :
223 0 : if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
224 0 : if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
225 : tmp = RREG32(voltage->gpio.reg);
226 0 : if (voltage->active_high)
227 0 : tmp |= voltage->gpio.mask;
228 : else
229 0 : tmp &= ~(voltage->gpio.mask);
230 0 : WREG32(voltage->gpio.reg, tmp);
231 0 : if (voltage->delay)
232 0 : udelay(voltage->delay);
233 : } else {
234 : tmp = RREG32(voltage->gpio.reg);
235 0 : if (voltage->active_high)
236 0 : tmp &= ~voltage->gpio.mask;
237 : else
238 0 : tmp |= voltage->gpio.mask;
239 0 : WREG32(voltage->gpio.reg, tmp);
240 0 : if (voltage->delay)
241 0 : udelay(voltage->delay);
242 : }
243 0 : } else if (voltage->type == VOLTAGE_VDDC)
244 0 : radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
245 :
246 0 : dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
247 0 : dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
248 0 : dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
249 0 : if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
250 0 : if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
251 0 : dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
252 0 : dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
253 0 : } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
254 0 : dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
255 0 : dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
256 0 : }
257 : } else {
258 0 : dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
259 0 : dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
260 : }
261 0 : WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
262 :
263 0 : dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
264 0 : if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
265 0 : dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
266 0 : if (voltage->delay) {
267 0 : dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
268 0 : dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
269 0 : } else
270 0 : dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
271 : } else
272 0 : dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
273 0 : WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
274 :
275 0 : hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
276 0 : if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
277 0 : hdp_dyn_cntl &= ~HDP_FORCEON;
278 : else
279 0 : hdp_dyn_cntl |= HDP_FORCEON;
280 0 : WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
281 : #if 0
282 : /* mc_host_dyn seems to cause hangs from time to time */
283 : mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
284 : if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
285 : mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
286 : else
287 : mc_host_dyn_cntl |= MC_HOST_FORCEON;
288 : WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
289 : #endif
290 0 : dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
291 0 : if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
292 0 : dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
293 : else
294 0 : dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
295 0 : WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
296 :
297 : /* set pcie lanes */
298 0 : if ((rdev->flags & RADEON_IS_PCIE) &&
299 0 : !(rdev->flags & RADEON_IS_IGP) &&
300 0 : rdev->asic->pm.set_pcie_lanes &&
301 0 : (ps->pcie_lanes !=
302 0 : rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
303 0 : radeon_set_pcie_lanes(rdev,
304 : ps->pcie_lanes);
305 : DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
306 0 : }
307 0 : }
308 :
309 0 : void rs600_pm_prepare(struct radeon_device *rdev)
310 : {
311 0 : struct drm_device *ddev = rdev->ddev;
312 : struct drm_crtc *crtc;
313 : struct radeon_crtc *radeon_crtc;
314 : u32 tmp;
315 :
316 : /* disable any active CRTCs */
317 0 : list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
318 0 : radeon_crtc = to_radeon_crtc(crtc);
319 0 : if (radeon_crtc->enabled) {
320 0 : tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
321 0 : tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
322 0 : WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
323 0 : }
324 : }
325 0 : }
326 :
327 0 : void rs600_pm_finish(struct radeon_device *rdev)
328 : {
329 0 : struct drm_device *ddev = rdev->ddev;
330 : struct drm_crtc *crtc;
331 : struct radeon_crtc *radeon_crtc;
332 : u32 tmp;
333 :
334 : /* enable any active CRTCs */
335 0 : list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
336 0 : radeon_crtc = to_radeon_crtc(crtc);
337 0 : if (radeon_crtc->enabled) {
338 0 : tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
339 0 : tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
340 0 : WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
341 0 : }
342 : }
343 0 : }
344 :
345 : /* hpd for digital panel detect/disconnect */
346 0 : bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
347 : {
348 : u32 tmp;
349 : bool connected = false;
350 :
351 0 : switch (hpd) {
352 : case RADEON_HPD_1:
353 0 : tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
354 0 : if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
355 0 : connected = true;
356 : break;
357 : case RADEON_HPD_2:
358 0 : tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
359 0 : if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
360 0 : connected = true;
361 : break;
362 : default:
363 : break;
364 : }
365 0 : return connected;
366 : }
367 :
368 0 : void rs600_hpd_set_polarity(struct radeon_device *rdev,
369 : enum radeon_hpd_id hpd)
370 : {
371 : u32 tmp;
372 0 : bool connected = rs600_hpd_sense(rdev, hpd);
373 :
374 0 : switch (hpd) {
375 : case RADEON_HPD_1:
376 0 : tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
377 0 : if (connected)
378 0 : tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
379 : else
380 0 : tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
381 0 : WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
382 0 : break;
383 : case RADEON_HPD_2:
384 0 : tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
385 0 : if (connected)
386 0 : tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
387 : else
388 0 : tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
389 0 : WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
390 0 : break;
391 : default:
392 : break;
393 : }
394 0 : }
395 :
396 0 : void rs600_hpd_init(struct radeon_device *rdev)
397 : {
398 0 : struct drm_device *dev = rdev->ddev;
399 : struct drm_connector *connector;
400 : unsigned enable = 0;
401 :
402 0 : list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
403 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
404 0 : switch (radeon_connector->hpd.hpd) {
405 : case RADEON_HPD_1:
406 0 : WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
407 : S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
408 0 : break;
409 : case RADEON_HPD_2:
410 0 : WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
411 : S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
412 0 : break;
413 : default:
414 : break;
415 : }
416 0 : enable |= 1 << radeon_connector->hpd.hpd;
417 0 : radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
418 : }
419 0 : radeon_irq_kms_enable_hpd(rdev, enable);
420 0 : }
421 :
422 0 : void rs600_hpd_fini(struct radeon_device *rdev)
423 : {
424 0 : struct drm_device *dev = rdev->ddev;
425 : struct drm_connector *connector;
426 : unsigned disable = 0;
427 :
428 0 : list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
429 0 : struct radeon_connector *radeon_connector = to_radeon_connector(connector);
430 0 : switch (radeon_connector->hpd.hpd) {
431 : case RADEON_HPD_1:
432 0 : WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
433 : S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
434 0 : break;
435 : case RADEON_HPD_2:
436 0 : WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
437 : S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
438 0 : break;
439 : default:
440 : break;
441 : }
442 0 : disable |= 1 << radeon_connector->hpd.hpd;
443 : }
444 0 : radeon_irq_kms_disable_hpd(rdev, disable);
445 0 : }
446 :
447 0 : int rs600_asic_reset(struct radeon_device *rdev)
448 : {
449 0 : struct rv515_mc_save save;
450 : u32 status, tmp;
451 : int ret = 0;
452 :
453 0 : status = RREG32(R_000E40_RBBM_STATUS);
454 0 : if (!G_000E40_GUI_ACTIVE(status)) {
455 0 : return 0;
456 : }
457 : /* Stops all mc clients */
458 0 : rv515_mc_stop(rdev, &save);
459 0 : status = RREG32(R_000E40_RBBM_STATUS);
460 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
461 : /* stop CP */
462 0 : WREG32(RADEON_CP_CSQ_CNTL, 0);
463 0 : tmp = RREG32(RADEON_CP_RB_CNTL);
464 0 : WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
465 0 : WREG32(RADEON_CP_RB_RPTR_WR, 0);
466 0 : WREG32(RADEON_CP_RB_WPTR, 0);
467 0 : WREG32(RADEON_CP_RB_CNTL, tmp);
468 : pci_save_state(rdev->pdev);
469 : /* disable bus mastering */
470 : pci_clear_master(rdev->pdev);
471 0 : mdelay(1);
472 : /* reset GA+VAP */
473 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
474 : S_0000F0_SOFT_RESET_GA(1));
475 0 : RREG32(R_0000F0_RBBM_SOFT_RESET);
476 0 : mdelay(500);
477 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
478 0 : mdelay(1);
479 0 : status = RREG32(R_000E40_RBBM_STATUS);
480 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
481 : /* reset CP */
482 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
483 0 : RREG32(R_0000F0_RBBM_SOFT_RESET);
484 0 : mdelay(500);
485 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
486 0 : mdelay(1);
487 0 : status = RREG32(R_000E40_RBBM_STATUS);
488 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
489 : /* reset MC */
490 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
491 0 : RREG32(R_0000F0_RBBM_SOFT_RESET);
492 0 : mdelay(500);
493 0 : WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
494 0 : mdelay(1);
495 0 : status = RREG32(R_000E40_RBBM_STATUS);
496 : dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
497 : /* restore PCI & busmastering */
498 : pci_restore_state(rdev->pdev);
499 : /* Check if GPU is idle */
500 0 : if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
501 0 : dev_err(rdev->dev, "failed to reset GPU\n");
502 : ret = -1;
503 0 : } else
504 : dev_info(rdev->dev, "GPU reset succeed\n");
505 0 : rv515_mc_resume(rdev, &save);
506 0 : return ret;
507 0 : }
508 :
509 : /*
510 : * GART.
511 : */
512 0 : void rs600_gart_tlb_flush(struct radeon_device *rdev)
513 : {
514 : uint32_t tmp;
515 :
516 0 : tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
517 0 : tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
518 0 : WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
519 :
520 0 : tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
521 0 : tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
522 0 : WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
523 :
524 0 : tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
525 0 : tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
526 0 : WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
527 0 : tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
528 0 : }
529 :
530 0 : static int rs600_gart_init(struct radeon_device *rdev)
531 : {
532 : int r;
533 :
534 0 : if (rdev->gart.robj) {
535 0 : WARN(1, "RS600 GART already initialized\n");
536 0 : return 0;
537 : }
538 : /* Initialize common gart structure */
539 0 : r = radeon_gart_init(rdev);
540 0 : if (r) {
541 0 : return r;
542 : }
543 0 : rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
544 0 : return radeon_gart_table_vram_alloc(rdev);
545 0 : }
546 :
547 0 : static int rs600_gart_enable(struct radeon_device *rdev)
548 : {
549 : u32 tmp;
550 : int r, i;
551 :
552 0 : if (rdev->gart.robj == NULL) {
553 0 : dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
554 0 : return -EINVAL;
555 : }
556 0 : r = radeon_gart_table_vram_pin(rdev);
557 0 : if (r)
558 0 : return r;
559 : /* Enable bus master */
560 0 : tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
561 0 : WREG32(RADEON_BUS_CNTL, tmp);
562 : /* FIXME: setup default page */
563 0 : WREG32_MC(R_000100_MC_PT0_CNTL,
564 : (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
565 : S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
566 :
567 0 : for (i = 0; i < 19; i++) {
568 0 : WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
569 : S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
570 : S_00016C_SYSTEM_ACCESS_MODE_MASK(
571 : V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
572 : S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
573 : V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
574 : S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
575 : S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
576 : S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
577 : }
578 : /* enable first context */
579 0 : WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
580 : S_000102_ENABLE_PAGE_TABLE(1) |
581 : S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
582 :
583 : /* disable all other contexts */
584 0 : for (i = 1; i < 8; i++)
585 0 : WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
586 :
587 : /* setup the page table */
588 0 : WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
589 : rdev->gart.table_addr);
590 0 : WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
591 0 : WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
592 0 : WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
593 :
594 : /* System context maps to VRAM space */
595 0 : WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
596 0 : WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
597 :
598 : /* enable page tables */
599 0 : tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
600 0 : WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
601 0 : tmp = RREG32_MC(R_000009_MC_CNTL1);
602 0 : WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
603 0 : rs600_gart_tlb_flush(rdev);
604 : DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
605 : (unsigned)(rdev->mc.gtt_size >> 20),
606 : (unsigned long long)rdev->gart.table_addr);
607 0 : rdev->gart.ready = true;
608 0 : return 0;
609 0 : }
610 :
611 0 : static void rs600_gart_disable(struct radeon_device *rdev)
612 : {
613 : u32 tmp;
614 :
615 : /* FIXME: disable out of gart access */
616 0 : WREG32_MC(R_000100_MC_PT0_CNTL, 0);
617 0 : tmp = RREG32_MC(R_000009_MC_CNTL1);
618 0 : WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
619 0 : radeon_gart_table_vram_unpin(rdev);
620 0 : }
621 :
622 0 : static void rs600_gart_fini(struct radeon_device *rdev)
623 : {
624 0 : radeon_gart_fini(rdev);
625 0 : rs600_gart_disable(rdev);
626 0 : radeon_gart_table_vram_free(rdev);
627 0 : }
628 :
629 0 : uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
630 : {
631 0 : addr = addr & 0xFFFFFFFFFFFFF000ULL;
632 0 : addr |= R600_PTE_SYSTEM;
633 0 : if (flags & RADEON_GART_PAGE_VALID)
634 0 : addr |= R600_PTE_VALID;
635 0 : if (flags & RADEON_GART_PAGE_READ)
636 0 : addr |= R600_PTE_READABLE;
637 0 : if (flags & RADEON_GART_PAGE_WRITE)
638 0 : addr |= R600_PTE_WRITEABLE;
639 0 : if (flags & RADEON_GART_PAGE_SNOOP)
640 0 : addr |= R600_PTE_SNOOPED;
641 0 : return addr;
642 : }
643 :
644 0 : void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
645 : uint64_t entry)
646 : {
647 0 : void __iomem *ptr = (void *)rdev->gart.ptr;
648 0 : writeq(entry, ptr + (i * 8));
649 0 : }
650 :
651 0 : int rs600_irq_set(struct radeon_device *rdev)
652 : {
653 : uint32_t tmp = 0;
654 : uint32_t mode_int = 0;
655 0 : u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
656 : ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
657 0 : u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
658 : ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
659 : u32 hdmi0;
660 0 : if (ASIC_IS_DCE2(rdev))
661 0 : hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
662 : ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
663 : else
664 : hdmi0 = 0;
665 :
666 0 : if (!rdev->irq.installed) {
667 0 : WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
668 0 : WREG32(R_000040_GEN_INT_CNTL, 0);
669 0 : return -EINVAL;
670 : }
671 0 : if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
672 : tmp |= S_000040_SW_INT_EN(1);
673 0 : }
674 0 : if (rdev->irq.crtc_vblank_int[0] ||
675 0 : atomic_read(&rdev->irq.pflip[0])) {
676 : mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
677 0 : }
678 0 : if (rdev->irq.crtc_vblank_int[1] ||
679 0 : atomic_read(&rdev->irq.pflip[1])) {
680 0 : mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
681 0 : }
682 0 : if (rdev->irq.hpd[0]) {
683 0 : hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
684 0 : }
685 0 : if (rdev->irq.hpd[1]) {
686 0 : hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
687 0 : }
688 0 : if (rdev->irq.afmt[0]) {
689 0 : hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
690 0 : }
691 0 : WREG32(R_000040_GEN_INT_CNTL, tmp);
692 0 : WREG32(R_006540_DxMODE_INT_MASK, mode_int);
693 0 : WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
694 0 : WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
695 0 : if (ASIC_IS_DCE2(rdev))
696 0 : WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
697 :
698 : /* posting read */
699 0 : RREG32(R_000040_GEN_INT_CNTL);
700 :
701 0 : return 0;
702 0 : }
703 :
704 0 : static inline u32 rs600_irq_ack(struct radeon_device *rdev)
705 : {
706 0 : uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
707 : uint32_t irq_mask = S_000044_SW_INT(1);
708 : u32 tmp;
709 :
710 0 : if (G_000044_DISPLAY_INT_STAT(irqs)) {
711 0 : rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
712 0 : if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
713 0 : WREG32(R_006534_D1MODE_VBLANK_STATUS,
714 : S_006534_D1MODE_VBLANK_ACK(1));
715 0 : }
716 0 : if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
717 0 : WREG32(R_006D34_D2MODE_VBLANK_STATUS,
718 : S_006D34_D2MODE_VBLANK_ACK(1));
719 0 : }
720 0 : if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
721 0 : tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
722 0 : tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
723 0 : WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
724 0 : }
725 0 : if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
726 0 : tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
727 0 : tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
728 0 : WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
729 0 : }
730 : } else {
731 0 : rdev->irq.stat_regs.r500.disp_int = 0;
732 : }
733 :
734 0 : if (ASIC_IS_DCE2(rdev)) {
735 0 : rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
736 : S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
737 0 : if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
738 0 : tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
739 0 : tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
740 0 : WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
741 0 : }
742 : } else
743 0 : rdev->irq.stat_regs.r500.hdmi0_status = 0;
744 :
745 0 : if (irqs) {
746 0 : WREG32(R_000044_GEN_INT_STATUS, irqs);
747 0 : }
748 0 : return irqs & irq_mask;
749 : }
750 :
751 0 : void rs600_irq_disable(struct radeon_device *rdev)
752 : {
753 0 : u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
754 : ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
755 0 : WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
756 0 : WREG32(R_000040_GEN_INT_CNTL, 0);
757 0 : WREG32(R_006540_DxMODE_INT_MASK, 0);
758 : /* Wait and acknowledge irq */
759 0 : mdelay(1);
760 0 : rs600_irq_ack(rdev);
761 0 : }
762 :
763 0 : int rs600_irq_process(struct radeon_device *rdev)
764 : {
765 : u32 status, msi_rearm;
766 : bool queue_hotplug = false;
767 : bool queue_hdmi = false;
768 :
769 0 : status = rs600_irq_ack(rdev);
770 0 : if (!status &&
771 0 : !rdev->irq.stat_regs.r500.disp_int &&
772 0 : !rdev->irq.stat_regs.r500.hdmi0_status) {
773 0 : return IRQ_NONE;
774 : }
775 0 : while (status ||
776 0 : rdev->irq.stat_regs.r500.disp_int ||
777 0 : rdev->irq.stat_regs.r500.hdmi0_status) {
778 : /* SW interrupt */
779 0 : if (G_000044_SW_INT(status)) {
780 0 : radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
781 0 : }
782 : /* Vertical blank interrupts */
783 0 : if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
784 0 : if (rdev->irq.crtc_vblank_int[0]) {
785 0 : drm_handle_vblank(rdev->ddev, 0);
786 0 : rdev->pm.vblank_sync = true;
787 0 : wake_up(&rdev->irq.vblank_queue);
788 0 : }
789 0 : if (atomic_read(&rdev->irq.pflip[0]))
790 0 : radeon_crtc_handle_vblank(rdev, 0);
791 : }
792 0 : if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
793 0 : if (rdev->irq.crtc_vblank_int[1]) {
794 0 : drm_handle_vblank(rdev->ddev, 1);
795 0 : rdev->pm.vblank_sync = true;
796 0 : wake_up(&rdev->irq.vblank_queue);
797 0 : }
798 0 : if (atomic_read(&rdev->irq.pflip[1]))
799 0 : radeon_crtc_handle_vblank(rdev, 1);
800 : }
801 0 : if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
802 : queue_hotplug = true;
803 : DRM_DEBUG("HPD1\n");
804 0 : }
805 0 : if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
806 : queue_hotplug = true;
807 : DRM_DEBUG("HPD2\n");
808 0 : }
809 0 : if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
810 : queue_hdmi = true;
811 : DRM_DEBUG("HDMI0\n");
812 0 : }
813 0 : status = rs600_irq_ack(rdev);
814 : }
815 0 : if (queue_hotplug)
816 0 : schedule_delayed_work(&rdev->hotplug_work, 0);
817 0 : if (queue_hdmi)
818 0 : schedule_work(&rdev->audio_work);
819 0 : if (rdev->msi_enabled) {
820 0 : switch (rdev->family) {
821 : case CHIP_RS600:
822 : case CHIP_RS690:
823 : case CHIP_RS740:
824 0 : msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
825 0 : WREG32(RADEON_BUS_CNTL, msi_rearm);
826 0 : WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
827 0 : break;
828 : default:
829 0 : WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
830 0 : break;
831 : }
832 : }
833 0 : return IRQ_HANDLED;
834 0 : }
835 :
836 0 : u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
837 : {
838 0 : if (crtc == 0)
839 0 : return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
840 : else
841 0 : return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
842 0 : }
843 :
844 0 : int rs600_mc_wait_for_idle(struct radeon_device *rdev)
845 : {
846 : unsigned i;
847 :
848 0 : for (i = 0; i < rdev->usec_timeout; i++) {
849 0 : if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
850 0 : return 0;
851 0 : udelay(1);
852 : }
853 0 : return -1;
854 0 : }
855 :
856 0 : static void rs600_gpu_init(struct radeon_device *rdev)
857 : {
858 0 : r420_pipes_init(rdev);
859 : /* Wait for mc idle */
860 0 : if (rs600_mc_wait_for_idle(rdev))
861 0 : dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
862 0 : }
863 :
864 0 : static void rs600_mc_init(struct radeon_device *rdev)
865 : {
866 : u64 base;
867 :
868 0 : rdev->mc.aper_base = rdev->fb_aper_offset;
869 0 : rdev->mc.aper_size = rdev->fb_aper_size;
870 0 : rdev->mc.vram_is_ddr = true;
871 0 : rdev->mc.vram_width = 128;
872 0 : rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
873 0 : rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
874 0 : rdev->mc.visible_vram_size = rdev->mc.aper_size;
875 0 : rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
876 0 : base = RREG32_MC(R_000004_MC_FB_LOCATION);
877 0 : base = G_000004_MC_FB_START(base) << 16;
878 0 : radeon_vram_location(rdev, &rdev->mc, base);
879 0 : rdev->mc.gtt_base_align = 0;
880 0 : radeon_gtt_location(rdev, &rdev->mc);
881 0 : radeon_update_bandwidth_info(rdev);
882 0 : }
883 :
884 0 : void rs600_bandwidth_update(struct radeon_device *rdev)
885 : {
886 : struct drm_display_mode *mode0 = NULL;
887 : struct drm_display_mode *mode1 = NULL;
888 : u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
889 : /* FIXME: implement full support */
890 :
891 0 : if (!rdev->mode_info.mode_config_initialized)
892 0 : return;
893 :
894 0 : radeon_update_display_priority(rdev);
895 :
896 0 : if (rdev->mode_info.crtcs[0]->base.enabled)
897 0 : mode0 = &rdev->mode_info.crtcs[0]->base.mode;
898 0 : if (rdev->mode_info.crtcs[1]->base.enabled)
899 0 : mode1 = &rdev->mode_info.crtcs[1]->base.mode;
900 :
901 0 : rs690_line_buffer_adjust(rdev, mode0, mode1);
902 :
903 0 : if (rdev->disp_priority == 2) {
904 0 : d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
905 0 : d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
906 0 : d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
907 0 : d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
908 0 : WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
909 0 : WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
910 0 : WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
911 0 : WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
912 0 : }
913 0 : }
914 :
915 0 : uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
916 : {
917 : unsigned long flags;
918 : u32 r;
919 :
920 0 : spin_lock_irqsave(&rdev->mc_idx_lock, flags);
921 0 : WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
922 : S_000070_MC_IND_CITF_ARB0(1));
923 0 : r = RREG32(R_000074_MC_IND_DATA);
924 0 : spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
925 0 : return r;
926 : }
927 :
928 0 : void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
929 : {
930 : unsigned long flags;
931 :
932 0 : spin_lock_irqsave(&rdev->mc_idx_lock, flags);
933 0 : WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
934 : S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
935 0 : WREG32(R_000074_MC_IND_DATA, v);
936 0 : spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
937 0 : }
938 :
939 0 : static void rs600_debugfs(struct radeon_device *rdev)
940 : {
941 0 : if (r100_debugfs_rbbm_init(rdev))
942 0 : DRM_ERROR("Failed to register debugfs file for RBBM !\n");
943 0 : }
944 :
945 0 : void rs600_set_safe_registers(struct radeon_device *rdev)
946 : {
947 0 : rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
948 0 : rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
949 0 : }
950 :
951 0 : static void rs600_mc_program(struct radeon_device *rdev)
952 : {
953 0 : struct rv515_mc_save save;
954 :
955 : /* Stops all mc clients */
956 0 : rv515_mc_stop(rdev, &save);
957 :
958 : /* Wait for mc idle */
959 0 : if (rs600_mc_wait_for_idle(rdev))
960 0 : dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
961 :
962 : /* FIXME: What does AGP means for such chipset ? */
963 0 : WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
964 0 : WREG32_MC(R_000006_AGP_BASE, 0);
965 0 : WREG32_MC(R_000007_AGP_BASE_2, 0);
966 : /* Program MC */
967 0 : WREG32_MC(R_000004_MC_FB_LOCATION,
968 : S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
969 : S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
970 0 : WREG32(R_000134_HDP_FB_LOCATION,
971 : S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
972 :
973 0 : rv515_mc_resume(rdev, &save);
974 0 : }
975 :
976 0 : static int rs600_startup(struct radeon_device *rdev)
977 : {
978 : int r;
979 :
980 0 : rs600_mc_program(rdev);
981 : /* Resume clock */
982 0 : rv515_clock_startup(rdev);
983 : /* Initialize GPU configuration (# pipes, ...) */
984 0 : rs600_gpu_init(rdev);
985 : /* Initialize GART (initialize after TTM so we can allocate
986 : * memory through TTM but finalize after TTM) */
987 0 : r = rs600_gart_enable(rdev);
988 0 : if (r)
989 0 : return r;
990 :
991 : /* allocate wb buffer */
992 0 : r = radeon_wb_init(rdev);
993 0 : if (r)
994 0 : return r;
995 :
996 0 : r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
997 0 : if (r) {
998 0 : dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
999 0 : return r;
1000 : }
1001 :
1002 : /* Enable IRQ */
1003 0 : if (!rdev->irq.installed) {
1004 0 : r = radeon_irq_kms_init(rdev);
1005 0 : if (r)
1006 0 : return r;
1007 : }
1008 :
1009 0 : rs600_irq_set(rdev);
1010 0 : rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1011 : /* 1M ring buffer */
1012 0 : r = r100_cp_init(rdev, 1024 * 1024);
1013 0 : if (r) {
1014 0 : dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1015 0 : return r;
1016 : }
1017 :
1018 0 : r = radeon_ib_pool_init(rdev);
1019 0 : if (r) {
1020 0 : dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1021 0 : return r;
1022 : }
1023 :
1024 0 : r = radeon_audio_init(rdev);
1025 0 : if (r) {
1026 0 : dev_err(rdev->dev, "failed initializing audio\n");
1027 0 : return r;
1028 : }
1029 :
1030 0 : return 0;
1031 0 : }
1032 :
1033 0 : int rs600_resume(struct radeon_device *rdev)
1034 : {
1035 : int r;
1036 :
1037 : /* Make sur GART are not working */
1038 0 : rs600_gart_disable(rdev);
1039 : /* Resume clock before doing reset */
1040 0 : rv515_clock_startup(rdev);
1041 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1042 0 : if (radeon_asic_reset(rdev)) {
1043 0 : dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1044 : RREG32(R_000E40_RBBM_STATUS),
1045 : RREG32(R_0007C0_CP_STAT));
1046 0 : }
1047 : /* post */
1048 0 : atom_asic_init(rdev->mode_info.atom_context);
1049 : /* Resume clock after posting */
1050 0 : rv515_clock_startup(rdev);
1051 : /* Initialize surface registers */
1052 0 : radeon_surface_init(rdev);
1053 :
1054 0 : rdev->accel_working = true;
1055 0 : r = rs600_startup(rdev);
1056 0 : if (r) {
1057 0 : rdev->accel_working = false;
1058 0 : }
1059 0 : return r;
1060 : }
1061 :
1062 0 : int rs600_suspend(struct radeon_device *rdev)
1063 : {
1064 0 : radeon_pm_suspend(rdev);
1065 0 : radeon_audio_fini(rdev);
1066 0 : r100_cp_disable(rdev);
1067 0 : radeon_wb_disable(rdev);
1068 0 : rs600_irq_disable(rdev);
1069 0 : rs600_gart_disable(rdev);
1070 0 : return 0;
1071 : }
1072 :
1073 0 : void rs600_fini(struct radeon_device *rdev)
1074 : {
1075 0 : radeon_pm_fini(rdev);
1076 0 : radeon_audio_fini(rdev);
1077 0 : r100_cp_fini(rdev);
1078 0 : radeon_wb_fini(rdev);
1079 0 : radeon_ib_pool_fini(rdev);
1080 0 : radeon_gem_fini(rdev);
1081 0 : rs600_gart_fini(rdev);
1082 0 : radeon_irq_kms_fini(rdev);
1083 0 : radeon_fence_driver_fini(rdev);
1084 0 : radeon_bo_fini(rdev);
1085 0 : radeon_atombios_fini(rdev);
1086 0 : kfree(rdev->bios);
1087 0 : rdev->bios = NULL;
1088 0 : }
1089 :
1090 0 : int rs600_init(struct radeon_device *rdev)
1091 : {
1092 : int r;
1093 :
1094 : /* Disable VGA */
1095 0 : rv515_vga_render_disable(rdev);
1096 : /* Initialize scratch registers */
1097 0 : radeon_scratch_init(rdev);
1098 : /* Initialize surface registers */
1099 0 : radeon_surface_init(rdev);
1100 : /* restore some register to sane defaults */
1101 0 : r100_restore_sanity(rdev);
1102 : /* BIOS */
1103 0 : if (!radeon_get_bios(rdev)) {
1104 0 : if (ASIC_IS_AVIVO(rdev))
1105 0 : return -EINVAL;
1106 : }
1107 0 : if (rdev->is_atom_bios) {
1108 0 : r = radeon_atombios_init(rdev);
1109 0 : if (r)
1110 0 : return r;
1111 : } else {
1112 0 : dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1113 0 : return -EINVAL;
1114 : }
1115 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1116 0 : if (radeon_asic_reset(rdev)) {
1117 0 : dev_warn(rdev->dev,
1118 : "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1119 : RREG32(R_000E40_RBBM_STATUS),
1120 : RREG32(R_0007C0_CP_STAT));
1121 0 : }
1122 : /* check if cards are posted or not */
1123 0 : if (radeon_boot_test_post_card(rdev) == false)
1124 0 : return -EINVAL;
1125 :
1126 : /* Initialize clocks */
1127 0 : radeon_get_clock_info(rdev->ddev);
1128 : /* initialize memory controller */
1129 0 : rs600_mc_init(rdev);
1130 0 : rs600_debugfs(rdev);
1131 : /* Fence driver */
1132 0 : r = radeon_fence_driver_init(rdev);
1133 0 : if (r)
1134 0 : return r;
1135 : /* Memory manager */
1136 0 : r = radeon_bo_init(rdev);
1137 0 : if (r)
1138 0 : return r;
1139 0 : r = rs600_gart_init(rdev);
1140 0 : if (r)
1141 0 : return r;
1142 0 : rs600_set_safe_registers(rdev);
1143 :
1144 : /* Initialize power management */
1145 0 : radeon_pm_init(rdev);
1146 :
1147 0 : rdev->accel_working = true;
1148 0 : r = rs600_startup(rdev);
1149 0 : if (r) {
1150 : /* Somethings want wront with the accel init stop accel */
1151 0 : dev_err(rdev->dev, "Disabling GPU acceleration\n");
1152 0 : r100_cp_fini(rdev);
1153 0 : radeon_wb_fini(rdev);
1154 0 : radeon_ib_pool_fini(rdev);
1155 0 : rs600_gart_fini(rdev);
1156 0 : radeon_irq_kms_fini(rdev);
1157 0 : rdev->accel_working = false;
1158 0 : }
1159 0 : return 0;
1160 0 : }
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