Line data Source code
1 : /*
2 : * Copyright 2008 Advanced Micro Devices, Inc.
3 : * Copyright 2008 Red Hat Inc.
4 : * Copyright 2009 Jerome Glisse.
5 : *
6 : * Permission is hereby granted, free of charge, to any person obtaining a
7 : * copy of this software and associated documentation files (the "Software"),
8 : * to deal in the Software without restriction, including without limitation
9 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 : * and/or sell copies of the Software, and to permit persons to whom the
11 : * Software is furnished to do so, subject to the following conditions:
12 : *
13 : * The above copyright notice and this permission notice shall be included in
14 : * all copies or substantial portions of the Software.
15 : *
16 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 : * OTHER DEALINGS IN THE SOFTWARE.
23 : *
24 : * Authors: Dave Airlie
25 : * Alex Deucher
26 : * Jerome Glisse
27 : */
28 : #include <dev/pci/drm/drmP.h>
29 : #include "rv515d.h"
30 : #include "radeon.h"
31 : #include "radeon_asic.h"
32 : #include "atom.h"
33 : #include "rv515_reg_safe.h"
34 :
35 : /* This files gather functions specifics to: rv515 */
36 : static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37 : static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38 : static void rv515_gpu_init(struct radeon_device *rdev);
39 : int rv515_mc_wait_for_idle(struct radeon_device *rdev);
40 :
41 : static const u32 crtc_offsets[2] =
42 : {
43 : 0,
44 : AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
45 : };
46 :
47 0 : void rv515_debugfs(struct radeon_device *rdev)
48 : {
49 0 : if (r100_debugfs_rbbm_init(rdev)) {
50 0 : DRM_ERROR("Failed to register debugfs file for RBBM !\n");
51 0 : }
52 0 : if (rv515_debugfs_pipes_info_init(rdev)) {
53 0 : DRM_ERROR("Failed to register debugfs file for pipes !\n");
54 0 : }
55 0 : if (rv515_debugfs_ga_info_init(rdev)) {
56 0 : DRM_ERROR("Failed to register debugfs file for pipes !\n");
57 0 : }
58 0 : }
59 :
60 0 : void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
61 : {
62 : int r;
63 :
64 0 : r = radeon_ring_lock(rdev, ring, 64);
65 0 : if (r) {
66 0 : return;
67 : }
68 0 : radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
69 0 : radeon_ring_write(ring,
70 : ISYNC_ANY2D_IDLE3D |
71 : ISYNC_ANY3D_IDLE2D |
72 : ISYNC_WAIT_IDLEGUI |
73 : ISYNC_CPSCRATCH_IDLEGUI);
74 0 : radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
75 0 : radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
76 0 : radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
77 0 : radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
78 0 : radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
79 0 : radeon_ring_write(ring, 0);
80 0 : radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
81 0 : radeon_ring_write(ring, 0);
82 0 : radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
83 0 : radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
84 0 : radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
85 0 : radeon_ring_write(ring, 0);
86 0 : radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
87 0 : radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
88 0 : radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
89 0 : radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
90 0 : radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
91 0 : radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
92 0 : radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
93 0 : radeon_ring_write(ring, 0);
94 0 : radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
95 0 : radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
96 0 : radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
97 0 : radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
98 0 : radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
99 0 : radeon_ring_write(ring,
100 : ((6 << MS_X0_SHIFT) |
101 : (6 << MS_Y0_SHIFT) |
102 : (6 << MS_X1_SHIFT) |
103 : (6 << MS_Y1_SHIFT) |
104 : (6 << MS_X2_SHIFT) |
105 : (6 << MS_Y2_SHIFT) |
106 : (6 << MSBD0_Y_SHIFT) |
107 : (6 << MSBD0_X_SHIFT)));
108 0 : radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
109 0 : radeon_ring_write(ring,
110 : ((6 << MS_X3_SHIFT) |
111 : (6 << MS_Y3_SHIFT) |
112 : (6 << MS_X4_SHIFT) |
113 : (6 << MS_Y4_SHIFT) |
114 : (6 << MS_X5_SHIFT) |
115 : (6 << MS_Y5_SHIFT) |
116 : (6 << MSBD1_SHIFT)));
117 0 : radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
118 0 : radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
119 0 : radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
120 0 : radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
121 0 : radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
122 0 : radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
123 0 : radeon_ring_write(ring, PACKET0(0x20C8, 0));
124 0 : radeon_ring_write(ring, 0);
125 0 : radeon_ring_unlock_commit(rdev, ring, false);
126 0 : }
127 :
128 0 : int rv515_mc_wait_for_idle(struct radeon_device *rdev)
129 : {
130 : unsigned i;
131 : uint32_t tmp;
132 :
133 0 : for (i = 0; i < rdev->usec_timeout; i++) {
134 : /* read MC_STATUS */
135 0 : tmp = RREG32_MC(MC_STATUS);
136 0 : if (tmp & MC_STATUS_IDLE) {
137 0 : return 0;
138 : }
139 0 : DRM_UDELAY(1);
140 : }
141 0 : return -1;
142 0 : }
143 :
144 0 : void rv515_vga_render_disable(struct radeon_device *rdev)
145 : {
146 0 : WREG32(R_000300_VGA_RENDER_CONTROL,
147 : RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
148 0 : }
149 :
150 0 : static void rv515_gpu_init(struct radeon_device *rdev)
151 : {
152 : unsigned pipe_select_current, gb_pipe_select, tmp;
153 :
154 0 : if (r100_gui_wait_for_idle(rdev)) {
155 0 : printk(KERN_WARNING "Failed to wait GUI idle while "
156 : "resetting GPU. Bad things might happen.\n");
157 0 : }
158 0 : rv515_vga_render_disable(rdev);
159 0 : r420_pipes_init(rdev);
160 0 : gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
161 0 : tmp = RREG32(R300_DST_PIPE_CONFIG);
162 0 : pipe_select_current = (tmp >> 2) & 3;
163 0 : tmp = (1 << pipe_select_current) |
164 0 : (((gb_pipe_select >> 8) & 0xF) << 4);
165 0 : WREG32_PLL(0x000D, tmp);
166 0 : if (r100_gui_wait_for_idle(rdev)) {
167 0 : printk(KERN_WARNING "Failed to wait GUI idle while "
168 : "resetting GPU. Bad things might happen.\n");
169 0 : }
170 0 : if (rv515_mc_wait_for_idle(rdev)) {
171 0 : printk(KERN_WARNING "Failed to wait MC idle while "
172 : "programming pipes. Bad things might happen.\n");
173 0 : }
174 0 : }
175 :
176 0 : static void rv515_vram_get_type(struct radeon_device *rdev)
177 : {
178 : uint32_t tmp;
179 :
180 0 : rdev->mc.vram_width = 128;
181 0 : rdev->mc.vram_is_ddr = true;
182 0 : tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
183 0 : switch (tmp) {
184 : case 0:
185 0 : rdev->mc.vram_width = 64;
186 0 : break;
187 : case 1:
188 0 : rdev->mc.vram_width = 128;
189 0 : break;
190 : default:
191 0 : rdev->mc.vram_width = 128;
192 0 : break;
193 : }
194 0 : }
195 :
196 0 : static void rv515_mc_init(struct radeon_device *rdev)
197 : {
198 :
199 0 : rv515_vram_get_type(rdev);
200 0 : r100_vram_init_sizes(rdev);
201 0 : radeon_vram_location(rdev, &rdev->mc, 0);
202 0 : rdev->mc.gtt_base_align = 0;
203 0 : if (!(rdev->flags & RADEON_IS_AGP))
204 0 : radeon_gtt_location(rdev, &rdev->mc);
205 0 : radeon_update_bandwidth_info(rdev);
206 0 : }
207 :
208 0 : uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
209 : {
210 : unsigned long flags;
211 : uint32_t r;
212 :
213 0 : spin_lock_irqsave(&rdev->mc_idx_lock, flags);
214 0 : WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
215 0 : r = RREG32(MC_IND_DATA);
216 0 : WREG32(MC_IND_INDEX, 0);
217 0 : spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
218 :
219 0 : return r;
220 : }
221 :
222 0 : void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
223 : {
224 : unsigned long flags;
225 :
226 0 : spin_lock_irqsave(&rdev->mc_idx_lock, flags);
227 0 : WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
228 0 : WREG32(MC_IND_DATA, (v));
229 0 : WREG32(MC_IND_INDEX, 0);
230 0 : spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
231 0 : }
232 :
233 : #if defined(CONFIG_DEBUG_FS)
234 : static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
235 : {
236 : struct drm_info_node *node = (struct drm_info_node *) m->private;
237 : struct drm_device *dev = node->minor->dev;
238 : struct radeon_device *rdev = dev->dev_private;
239 : uint32_t tmp;
240 :
241 : tmp = RREG32(GB_PIPE_SELECT);
242 : seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
243 : tmp = RREG32(SU_REG_DEST);
244 : seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
245 : tmp = RREG32(GB_TILE_CONFIG);
246 : seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
247 : tmp = RREG32(DST_PIPE_CONFIG);
248 : seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
249 : return 0;
250 : }
251 :
252 : static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
253 : {
254 : struct drm_info_node *node = (struct drm_info_node *) m->private;
255 : struct drm_device *dev = node->minor->dev;
256 : struct radeon_device *rdev = dev->dev_private;
257 : uint32_t tmp;
258 :
259 : tmp = RREG32(0x2140);
260 : seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
261 : radeon_asic_reset(rdev);
262 : tmp = RREG32(0x425C);
263 : seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
264 : return 0;
265 : }
266 :
267 : static struct drm_info_list rv515_pipes_info_list[] = {
268 : {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
269 : };
270 :
271 : static struct drm_info_list rv515_ga_info_list[] = {
272 : {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
273 : };
274 : #endif
275 :
276 0 : static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
277 : {
278 : #if defined(CONFIG_DEBUG_FS)
279 : return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
280 : #else
281 0 : return 0;
282 : #endif
283 : }
284 :
285 0 : static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
286 : {
287 : #if defined(CONFIG_DEBUG_FS)
288 : return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
289 : #else
290 0 : return 0;
291 : #endif
292 : }
293 :
294 0 : void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
295 : {
296 : u32 crtc_enabled, tmp, frame_count, blackout;
297 : int i, j;
298 :
299 0 : save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
300 0 : save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
301 :
302 : /* disable VGA render */
303 0 : WREG32(R_000300_VGA_RENDER_CONTROL, 0);
304 : /* blank the display controllers */
305 0 : for (i = 0; i < rdev->num_crtc; i++) {
306 0 : crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
307 0 : if (crtc_enabled) {
308 0 : save->crtc_enabled[i] = true;
309 0 : tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
310 0 : if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
311 0 : radeon_wait_for_vblank(rdev, i);
312 0 : WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
313 0 : tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
314 0 : WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
315 0 : WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
316 0 : }
317 : /* wait for the next frame */
318 0 : frame_count = radeon_get_vblank_counter(rdev, i);
319 0 : for (j = 0; j < rdev->usec_timeout; j++) {
320 0 : if (radeon_get_vblank_counter(rdev, i) != frame_count)
321 : break;
322 0 : udelay(1);
323 : }
324 :
325 : /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
326 0 : WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
327 0 : tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
328 0 : tmp &= ~AVIVO_CRTC_EN;
329 0 : WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
330 0 : WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
331 0 : save->crtc_enabled[i] = false;
332 : /* ***** */
333 0 : } else {
334 0 : save->crtc_enabled[i] = false;
335 : }
336 : }
337 :
338 0 : radeon_mc_wait_for_idle(rdev);
339 :
340 0 : if (rdev->family >= CHIP_R600) {
341 0 : if (rdev->family >= CHIP_RV770)
342 0 : blackout = RREG32(R700_MC_CITF_CNTL);
343 : else
344 0 : blackout = RREG32(R600_CITF_CNTL);
345 0 : if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
346 : /* Block CPU access */
347 0 : WREG32(R600_BIF_FB_EN, 0);
348 : /* blackout the MC */
349 0 : blackout |= R600_BLACKOUT_MASK;
350 0 : if (rdev->family >= CHIP_RV770)
351 0 : WREG32(R700_MC_CITF_CNTL, blackout);
352 : else
353 0 : WREG32(R600_CITF_CNTL, blackout);
354 : }
355 : }
356 : /* wait for the MC to settle */
357 0 : udelay(100);
358 :
359 : /* lock double buffered regs */
360 0 : for (i = 0; i < rdev->num_crtc; i++) {
361 0 : if (save->crtc_enabled[i]) {
362 0 : tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
363 0 : if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
364 0 : tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
365 0 : WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
366 0 : }
367 0 : tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
368 0 : if (!(tmp & 1)) {
369 0 : tmp |= 1;
370 0 : WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
371 0 : }
372 : }
373 : }
374 0 : }
375 :
376 0 : void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
377 : {
378 : u32 tmp, frame_count;
379 : int i, j;
380 :
381 : /* update crtc base addresses */
382 0 : for (i = 0; i < rdev->num_crtc; i++) {
383 0 : if (rdev->family >= CHIP_RV770) {
384 0 : if (i == 0) {
385 0 : WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
386 : upper_32_bits(rdev->mc.vram_start));
387 0 : WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
388 : upper_32_bits(rdev->mc.vram_start));
389 0 : } else {
390 0 : WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
391 : upper_32_bits(rdev->mc.vram_start));
392 0 : WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
393 : upper_32_bits(rdev->mc.vram_start));
394 : }
395 : }
396 0 : WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
397 : (u32)rdev->mc.vram_start);
398 0 : WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
399 : (u32)rdev->mc.vram_start);
400 : }
401 0 : WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
402 :
403 : /* unlock regs and wait for update */
404 0 : for (i = 0; i < rdev->num_crtc; i++) {
405 0 : if (save->crtc_enabled[i]) {
406 0 : tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
407 0 : if ((tmp & 0x7) != 3) {
408 0 : tmp &= ~0x7;
409 0 : tmp |= 0x3;
410 0 : WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
411 0 : }
412 0 : tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
413 0 : if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
414 0 : tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
415 0 : WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
416 0 : }
417 0 : tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
418 0 : if (tmp & 1) {
419 0 : tmp &= ~1;
420 0 : WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
421 0 : }
422 0 : for (j = 0; j < rdev->usec_timeout; j++) {
423 0 : tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
424 0 : if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
425 : break;
426 0 : udelay(1);
427 : }
428 : }
429 : }
430 :
431 0 : if (rdev->family >= CHIP_R600) {
432 : /* unblackout the MC */
433 0 : if (rdev->family >= CHIP_RV770)
434 0 : tmp = RREG32(R700_MC_CITF_CNTL);
435 : else
436 0 : tmp = RREG32(R600_CITF_CNTL);
437 0 : tmp &= ~R600_BLACKOUT_MASK;
438 0 : if (rdev->family >= CHIP_RV770)
439 0 : WREG32(R700_MC_CITF_CNTL, tmp);
440 : else
441 0 : WREG32(R600_CITF_CNTL, tmp);
442 : /* allow CPU access */
443 0 : WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
444 0 : }
445 :
446 0 : for (i = 0; i < rdev->num_crtc; i++) {
447 0 : if (save->crtc_enabled[i]) {
448 0 : tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
449 0 : tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
450 0 : WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
451 : /* wait for the next frame */
452 0 : frame_count = radeon_get_vblank_counter(rdev, i);
453 0 : for (j = 0; j < rdev->usec_timeout; j++) {
454 0 : if (radeon_get_vblank_counter(rdev, i) != frame_count)
455 : break;
456 0 : udelay(1);
457 : }
458 : }
459 : }
460 : /* Unlock vga access */
461 0 : WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
462 0 : mdelay(1);
463 0 : WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
464 0 : }
465 :
466 0 : static void rv515_mc_program(struct radeon_device *rdev)
467 : {
468 0 : struct rv515_mc_save save;
469 :
470 : /* Stops all mc clients */
471 0 : rv515_mc_stop(rdev, &save);
472 :
473 : /* Wait for mc idle */
474 0 : if (rv515_mc_wait_for_idle(rdev))
475 0 : dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
476 : /* Write VRAM size in case we are limiting it */
477 0 : WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
478 : /* Program MC, should be a 32bits limited address space */
479 0 : WREG32_MC(R_000001_MC_FB_LOCATION,
480 : S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
481 : S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
482 0 : WREG32(R_000134_HDP_FB_LOCATION,
483 : S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
484 0 : if (rdev->flags & RADEON_IS_AGP) {
485 0 : WREG32_MC(R_000002_MC_AGP_LOCATION,
486 : S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
487 : S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
488 0 : WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
489 0 : WREG32_MC(R_000004_MC_AGP_BASE_2,
490 : S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
491 0 : } else {
492 0 : WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
493 0 : WREG32_MC(R_000003_MC_AGP_BASE, 0);
494 0 : WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
495 : }
496 :
497 0 : rv515_mc_resume(rdev, &save);
498 0 : }
499 :
500 0 : void rv515_clock_startup(struct radeon_device *rdev)
501 : {
502 0 : if (radeon_dynclks != -1 && radeon_dynclks)
503 0 : radeon_atom_set_clock_gating(rdev, 1);
504 : /* We need to force on some of the block */
505 0 : WREG32_PLL(R_00000F_CP_DYN_CNTL,
506 : RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
507 0 : WREG32_PLL(R_000011_E2_DYN_CNTL,
508 : RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
509 0 : WREG32_PLL(R_000013_IDCT_DYN_CNTL,
510 : RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
511 0 : }
512 :
513 0 : static int rv515_startup(struct radeon_device *rdev)
514 : {
515 : int r;
516 :
517 0 : rv515_mc_program(rdev);
518 : /* Resume clock */
519 0 : rv515_clock_startup(rdev);
520 : /* Initialize GPU configuration (# pipes, ...) */
521 0 : rv515_gpu_init(rdev);
522 : /* Initialize GART (initialize after TTM so we can allocate
523 : * memory through TTM but finalize after TTM) */
524 0 : if (rdev->flags & RADEON_IS_PCIE) {
525 0 : r = rv370_pcie_gart_enable(rdev);
526 0 : if (r)
527 0 : return r;
528 : }
529 :
530 : /* allocate wb buffer */
531 0 : r = radeon_wb_init(rdev);
532 0 : if (r)
533 0 : return r;
534 :
535 0 : r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
536 0 : if (r) {
537 0 : dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
538 0 : return r;
539 : }
540 :
541 : /* Enable IRQ */
542 0 : if (!rdev->irq.installed) {
543 0 : r = radeon_irq_kms_init(rdev);
544 0 : if (r)
545 0 : return r;
546 : }
547 :
548 0 : rs600_irq_set(rdev);
549 0 : rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
550 : /* 1M ring buffer */
551 0 : r = r100_cp_init(rdev, 1024 * 1024);
552 0 : if (r) {
553 0 : dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
554 0 : return r;
555 : }
556 :
557 0 : r = radeon_ib_pool_init(rdev);
558 0 : if (r) {
559 0 : dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
560 0 : return r;
561 : }
562 :
563 0 : return 0;
564 0 : }
565 :
566 0 : int rv515_resume(struct radeon_device *rdev)
567 : {
568 : int r;
569 :
570 : /* Make sur GART are not working */
571 0 : if (rdev->flags & RADEON_IS_PCIE)
572 0 : rv370_pcie_gart_disable(rdev);
573 : /* Resume clock before doing reset */
574 0 : rv515_clock_startup(rdev);
575 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
576 0 : if (radeon_asic_reset(rdev)) {
577 0 : dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
578 : RREG32(R_000E40_RBBM_STATUS),
579 : RREG32(R_0007C0_CP_STAT));
580 0 : }
581 : /* post */
582 0 : atom_asic_init(rdev->mode_info.atom_context);
583 : /* Resume clock after posting */
584 0 : rv515_clock_startup(rdev);
585 : /* Initialize surface registers */
586 0 : radeon_surface_init(rdev);
587 :
588 0 : rdev->accel_working = true;
589 0 : r = rv515_startup(rdev);
590 0 : if (r) {
591 0 : rdev->accel_working = false;
592 0 : }
593 0 : return r;
594 : }
595 :
596 0 : int rv515_suspend(struct radeon_device *rdev)
597 : {
598 0 : radeon_pm_suspend(rdev);
599 0 : r100_cp_disable(rdev);
600 0 : radeon_wb_disable(rdev);
601 0 : rs600_irq_disable(rdev);
602 0 : if (rdev->flags & RADEON_IS_PCIE)
603 0 : rv370_pcie_gart_disable(rdev);
604 0 : return 0;
605 : }
606 :
607 0 : void rv515_set_safe_registers(struct radeon_device *rdev)
608 : {
609 0 : rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
610 0 : rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
611 0 : }
612 :
613 0 : void rv515_fini(struct radeon_device *rdev)
614 : {
615 0 : radeon_pm_fini(rdev);
616 0 : r100_cp_fini(rdev);
617 0 : radeon_wb_fini(rdev);
618 0 : radeon_ib_pool_fini(rdev);
619 0 : radeon_gem_fini(rdev);
620 0 : rv370_pcie_gart_fini(rdev);
621 0 : radeon_agp_fini(rdev);
622 0 : radeon_irq_kms_fini(rdev);
623 0 : radeon_fence_driver_fini(rdev);
624 0 : radeon_bo_fini(rdev);
625 0 : radeon_atombios_fini(rdev);
626 0 : kfree(rdev->bios);
627 0 : rdev->bios = NULL;
628 0 : }
629 :
630 0 : int rv515_init(struct radeon_device *rdev)
631 : {
632 : int r;
633 :
634 : /* Initialize scratch registers */
635 0 : radeon_scratch_init(rdev);
636 : /* Initialize surface registers */
637 0 : radeon_surface_init(rdev);
638 : /* TODO: disable VGA need to use VGA request */
639 : /* restore some register to sane defaults */
640 0 : r100_restore_sanity(rdev);
641 : /* BIOS*/
642 0 : if (!radeon_get_bios(rdev)) {
643 0 : if (ASIC_IS_AVIVO(rdev))
644 0 : return -EINVAL;
645 : }
646 0 : if (rdev->is_atom_bios) {
647 0 : r = radeon_atombios_init(rdev);
648 0 : if (r)
649 0 : return r;
650 : } else {
651 0 : dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
652 0 : return -EINVAL;
653 : }
654 : /* Reset gpu before posting otherwise ATOM will enter infinite loop */
655 0 : if (radeon_asic_reset(rdev)) {
656 0 : dev_warn(rdev->dev,
657 : "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
658 : RREG32(R_000E40_RBBM_STATUS),
659 : RREG32(R_0007C0_CP_STAT));
660 0 : }
661 : /* check if cards are posted or not */
662 0 : if (radeon_boot_test_post_card(rdev) == false)
663 0 : return -EINVAL;
664 : /* Initialize clocks */
665 0 : radeon_get_clock_info(rdev->ddev);
666 : /* initialize AGP */
667 0 : if (rdev->flags & RADEON_IS_AGP) {
668 0 : r = radeon_agp_init(rdev);
669 0 : if (r) {
670 0 : radeon_agp_disable(rdev);
671 0 : }
672 : }
673 : /* initialize memory controller */
674 0 : rv515_mc_init(rdev);
675 0 : rv515_debugfs(rdev);
676 : /* Fence driver */
677 0 : r = radeon_fence_driver_init(rdev);
678 0 : if (r)
679 0 : return r;
680 : /* Memory manager */
681 0 : r = radeon_bo_init(rdev);
682 0 : if (r)
683 0 : return r;
684 0 : r = rv370_pcie_gart_init(rdev);
685 0 : if (r)
686 0 : return r;
687 0 : rv515_set_safe_registers(rdev);
688 :
689 : /* Initialize power management */
690 0 : radeon_pm_init(rdev);
691 :
692 0 : rdev->accel_working = true;
693 0 : r = rv515_startup(rdev);
694 0 : if (r) {
695 : /* Somethings want wront with the accel init stop accel */
696 0 : dev_err(rdev->dev, "Disabling GPU acceleration\n");
697 0 : r100_cp_fini(rdev);
698 0 : radeon_wb_fini(rdev);
699 0 : radeon_ib_pool_fini(rdev);
700 0 : radeon_irq_kms_fini(rdev);
701 0 : rv370_pcie_gart_fini(rdev);
702 0 : radeon_agp_fini(rdev);
703 0 : rdev->accel_working = false;
704 0 : }
705 0 : return 0;
706 0 : }
707 :
708 0 : void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
709 : {
710 0 : int index_reg = 0x6578 + crtc->crtc_offset;
711 0 : int data_reg = 0x657c + crtc->crtc_offset;
712 :
713 0 : WREG32(0x659C + crtc->crtc_offset, 0x0);
714 0 : WREG32(0x6594 + crtc->crtc_offset, 0x705);
715 0 : WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
716 0 : WREG32(0x65D8 + crtc->crtc_offset, 0x0);
717 0 : WREG32(0x65B0 + crtc->crtc_offset, 0x0);
718 0 : WREG32(0x65C0 + crtc->crtc_offset, 0x0);
719 0 : WREG32(0x65D4 + crtc->crtc_offset, 0x0);
720 0 : WREG32(index_reg, 0x0);
721 0 : WREG32(data_reg, 0x841880A8);
722 0 : WREG32(index_reg, 0x1);
723 0 : WREG32(data_reg, 0x84208680);
724 0 : WREG32(index_reg, 0x2);
725 0 : WREG32(data_reg, 0xBFF880B0);
726 0 : WREG32(index_reg, 0x100);
727 0 : WREG32(data_reg, 0x83D88088);
728 0 : WREG32(index_reg, 0x101);
729 0 : WREG32(data_reg, 0x84608680);
730 0 : WREG32(index_reg, 0x102);
731 0 : WREG32(data_reg, 0xBFF080D0);
732 0 : WREG32(index_reg, 0x200);
733 0 : WREG32(data_reg, 0x83988068);
734 0 : WREG32(index_reg, 0x201);
735 0 : WREG32(data_reg, 0x84A08680);
736 0 : WREG32(index_reg, 0x202);
737 0 : WREG32(data_reg, 0xBFF080F8);
738 0 : WREG32(index_reg, 0x300);
739 0 : WREG32(data_reg, 0x83588058);
740 0 : WREG32(index_reg, 0x301);
741 0 : WREG32(data_reg, 0x84E08660);
742 0 : WREG32(index_reg, 0x302);
743 0 : WREG32(data_reg, 0xBFF88120);
744 0 : WREG32(index_reg, 0x400);
745 0 : WREG32(data_reg, 0x83188040);
746 0 : WREG32(index_reg, 0x401);
747 0 : WREG32(data_reg, 0x85008660);
748 0 : WREG32(index_reg, 0x402);
749 0 : WREG32(data_reg, 0xBFF88150);
750 0 : WREG32(index_reg, 0x500);
751 0 : WREG32(data_reg, 0x82D88030);
752 0 : WREG32(index_reg, 0x501);
753 0 : WREG32(data_reg, 0x85408640);
754 0 : WREG32(index_reg, 0x502);
755 0 : WREG32(data_reg, 0xBFF88180);
756 0 : WREG32(index_reg, 0x600);
757 0 : WREG32(data_reg, 0x82A08018);
758 0 : WREG32(index_reg, 0x601);
759 0 : WREG32(data_reg, 0x85808620);
760 0 : WREG32(index_reg, 0x602);
761 0 : WREG32(data_reg, 0xBFF081B8);
762 0 : WREG32(index_reg, 0x700);
763 0 : WREG32(data_reg, 0x82608010);
764 0 : WREG32(index_reg, 0x701);
765 0 : WREG32(data_reg, 0x85A08600);
766 0 : WREG32(index_reg, 0x702);
767 0 : WREG32(data_reg, 0x800081F0);
768 0 : WREG32(index_reg, 0x800);
769 0 : WREG32(data_reg, 0x8228BFF8);
770 0 : WREG32(index_reg, 0x801);
771 0 : WREG32(data_reg, 0x85E085E0);
772 0 : WREG32(index_reg, 0x802);
773 0 : WREG32(data_reg, 0xBFF88228);
774 0 : WREG32(index_reg, 0x10000);
775 0 : WREG32(data_reg, 0x82A8BF00);
776 0 : WREG32(index_reg, 0x10001);
777 0 : WREG32(data_reg, 0x82A08CC0);
778 0 : WREG32(index_reg, 0x10002);
779 0 : WREG32(data_reg, 0x8008BEF8);
780 0 : WREG32(index_reg, 0x10100);
781 0 : WREG32(data_reg, 0x81F0BF28);
782 0 : WREG32(index_reg, 0x10101);
783 0 : WREG32(data_reg, 0x83608CA0);
784 0 : WREG32(index_reg, 0x10102);
785 0 : WREG32(data_reg, 0x8018BED0);
786 0 : WREG32(index_reg, 0x10200);
787 0 : WREG32(data_reg, 0x8148BF38);
788 0 : WREG32(index_reg, 0x10201);
789 0 : WREG32(data_reg, 0x84408C80);
790 0 : WREG32(index_reg, 0x10202);
791 0 : WREG32(data_reg, 0x8008BEB8);
792 0 : WREG32(index_reg, 0x10300);
793 0 : WREG32(data_reg, 0x80B0BF78);
794 0 : WREG32(index_reg, 0x10301);
795 0 : WREG32(data_reg, 0x85008C20);
796 0 : WREG32(index_reg, 0x10302);
797 0 : WREG32(data_reg, 0x8020BEA0);
798 0 : WREG32(index_reg, 0x10400);
799 0 : WREG32(data_reg, 0x8028BF90);
800 0 : WREG32(index_reg, 0x10401);
801 0 : WREG32(data_reg, 0x85E08BC0);
802 0 : WREG32(index_reg, 0x10402);
803 0 : WREG32(data_reg, 0x8018BE90);
804 0 : WREG32(index_reg, 0x10500);
805 0 : WREG32(data_reg, 0xBFB8BFB0);
806 0 : WREG32(index_reg, 0x10501);
807 0 : WREG32(data_reg, 0x86C08B40);
808 0 : WREG32(index_reg, 0x10502);
809 0 : WREG32(data_reg, 0x8010BE90);
810 0 : WREG32(index_reg, 0x10600);
811 0 : WREG32(data_reg, 0xBF58BFC8);
812 0 : WREG32(index_reg, 0x10601);
813 0 : WREG32(data_reg, 0x87A08AA0);
814 0 : WREG32(index_reg, 0x10602);
815 0 : WREG32(data_reg, 0x8010BE98);
816 0 : WREG32(index_reg, 0x10700);
817 0 : WREG32(data_reg, 0xBF10BFF0);
818 0 : WREG32(index_reg, 0x10701);
819 0 : WREG32(data_reg, 0x886089E0);
820 0 : WREG32(index_reg, 0x10702);
821 0 : WREG32(data_reg, 0x8018BEB0);
822 0 : WREG32(index_reg, 0x10800);
823 0 : WREG32(data_reg, 0xBED8BFE8);
824 0 : WREG32(index_reg, 0x10801);
825 0 : WREG32(data_reg, 0x89408940);
826 0 : WREG32(index_reg, 0x10802);
827 0 : WREG32(data_reg, 0xBFE8BED8);
828 0 : WREG32(index_reg, 0x20000);
829 0 : WREG32(data_reg, 0x80008000);
830 0 : WREG32(index_reg, 0x20001);
831 0 : WREG32(data_reg, 0x90008000);
832 0 : WREG32(index_reg, 0x20002);
833 0 : WREG32(data_reg, 0x80008000);
834 0 : WREG32(index_reg, 0x20003);
835 0 : WREG32(data_reg, 0x80008000);
836 0 : WREG32(index_reg, 0x20100);
837 0 : WREG32(data_reg, 0x80108000);
838 0 : WREG32(index_reg, 0x20101);
839 0 : WREG32(data_reg, 0x8FE0BF70);
840 0 : WREG32(index_reg, 0x20102);
841 0 : WREG32(data_reg, 0xBFE880C0);
842 0 : WREG32(index_reg, 0x20103);
843 0 : WREG32(data_reg, 0x80008000);
844 0 : WREG32(index_reg, 0x20200);
845 0 : WREG32(data_reg, 0x8018BFF8);
846 0 : WREG32(index_reg, 0x20201);
847 0 : WREG32(data_reg, 0x8F80BF08);
848 0 : WREG32(index_reg, 0x20202);
849 0 : WREG32(data_reg, 0xBFD081A0);
850 0 : WREG32(index_reg, 0x20203);
851 0 : WREG32(data_reg, 0xBFF88000);
852 0 : WREG32(index_reg, 0x20300);
853 0 : WREG32(data_reg, 0x80188000);
854 0 : WREG32(index_reg, 0x20301);
855 0 : WREG32(data_reg, 0x8EE0BEC0);
856 0 : WREG32(index_reg, 0x20302);
857 0 : WREG32(data_reg, 0xBFB082A0);
858 0 : WREG32(index_reg, 0x20303);
859 0 : WREG32(data_reg, 0x80008000);
860 0 : WREG32(index_reg, 0x20400);
861 0 : WREG32(data_reg, 0x80188000);
862 0 : WREG32(index_reg, 0x20401);
863 0 : WREG32(data_reg, 0x8E00BEA0);
864 0 : WREG32(index_reg, 0x20402);
865 0 : WREG32(data_reg, 0xBF8883C0);
866 0 : WREG32(index_reg, 0x20403);
867 0 : WREG32(data_reg, 0x80008000);
868 0 : WREG32(index_reg, 0x20500);
869 0 : WREG32(data_reg, 0x80188000);
870 0 : WREG32(index_reg, 0x20501);
871 0 : WREG32(data_reg, 0x8D00BE90);
872 0 : WREG32(index_reg, 0x20502);
873 0 : WREG32(data_reg, 0xBF588500);
874 0 : WREG32(index_reg, 0x20503);
875 0 : WREG32(data_reg, 0x80008008);
876 0 : WREG32(index_reg, 0x20600);
877 0 : WREG32(data_reg, 0x80188000);
878 0 : WREG32(index_reg, 0x20601);
879 0 : WREG32(data_reg, 0x8BC0BE98);
880 0 : WREG32(index_reg, 0x20602);
881 0 : WREG32(data_reg, 0xBF308660);
882 0 : WREG32(index_reg, 0x20603);
883 0 : WREG32(data_reg, 0x80008008);
884 0 : WREG32(index_reg, 0x20700);
885 0 : WREG32(data_reg, 0x80108000);
886 0 : WREG32(index_reg, 0x20701);
887 0 : WREG32(data_reg, 0x8A80BEB0);
888 0 : WREG32(index_reg, 0x20702);
889 0 : WREG32(data_reg, 0xBF0087C0);
890 0 : WREG32(index_reg, 0x20703);
891 0 : WREG32(data_reg, 0x80008008);
892 0 : WREG32(index_reg, 0x20800);
893 0 : WREG32(data_reg, 0x80108000);
894 0 : WREG32(index_reg, 0x20801);
895 0 : WREG32(data_reg, 0x8920BED0);
896 0 : WREG32(index_reg, 0x20802);
897 0 : WREG32(data_reg, 0xBED08920);
898 0 : WREG32(index_reg, 0x20803);
899 0 : WREG32(data_reg, 0x80008010);
900 0 : WREG32(index_reg, 0x30000);
901 0 : WREG32(data_reg, 0x90008000);
902 0 : WREG32(index_reg, 0x30001);
903 0 : WREG32(data_reg, 0x80008000);
904 0 : WREG32(index_reg, 0x30100);
905 0 : WREG32(data_reg, 0x8FE0BF90);
906 0 : WREG32(index_reg, 0x30101);
907 0 : WREG32(data_reg, 0xBFF880A0);
908 0 : WREG32(index_reg, 0x30200);
909 0 : WREG32(data_reg, 0x8F60BF40);
910 0 : WREG32(index_reg, 0x30201);
911 0 : WREG32(data_reg, 0xBFE88180);
912 0 : WREG32(index_reg, 0x30300);
913 0 : WREG32(data_reg, 0x8EC0BF00);
914 0 : WREG32(index_reg, 0x30301);
915 0 : WREG32(data_reg, 0xBFC88280);
916 0 : WREG32(index_reg, 0x30400);
917 0 : WREG32(data_reg, 0x8DE0BEE0);
918 0 : WREG32(index_reg, 0x30401);
919 0 : WREG32(data_reg, 0xBFA083A0);
920 0 : WREG32(index_reg, 0x30500);
921 0 : WREG32(data_reg, 0x8CE0BED0);
922 0 : WREG32(index_reg, 0x30501);
923 0 : WREG32(data_reg, 0xBF7884E0);
924 0 : WREG32(index_reg, 0x30600);
925 0 : WREG32(data_reg, 0x8BA0BED8);
926 0 : WREG32(index_reg, 0x30601);
927 0 : WREG32(data_reg, 0xBF508640);
928 0 : WREG32(index_reg, 0x30700);
929 0 : WREG32(data_reg, 0x8A60BEE8);
930 0 : WREG32(index_reg, 0x30701);
931 0 : WREG32(data_reg, 0xBF2087A0);
932 0 : WREG32(index_reg, 0x30800);
933 0 : WREG32(data_reg, 0x8900BF00);
934 0 : WREG32(index_reg, 0x30801);
935 0 : WREG32(data_reg, 0xBF008900);
936 0 : }
937 :
938 : struct rv515_watermark {
939 : u32 lb_request_fifo_depth;
940 : fixed20_12 num_line_pair;
941 : fixed20_12 estimated_width;
942 : fixed20_12 worst_case_latency;
943 : fixed20_12 consumption_rate;
944 : fixed20_12 active_time;
945 : fixed20_12 dbpp;
946 : fixed20_12 priority_mark_max;
947 : fixed20_12 priority_mark;
948 : fixed20_12 sclk;
949 : };
950 :
951 0 : static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
952 : struct radeon_crtc *crtc,
953 : struct rv515_watermark *wm,
954 : bool low)
955 : {
956 0 : struct drm_display_mode *mode = &crtc->base.mode;
957 : fixed20_12 a, b, c;
958 : fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
959 : fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
960 : fixed20_12 sclk;
961 : u32 selected_sclk;
962 :
963 0 : if (!crtc->base.enabled) {
964 : /* FIXME: wouldn't it better to set priority mark to maximum */
965 0 : wm->lb_request_fifo_depth = 4;
966 0 : return;
967 : }
968 :
969 : /* rv6xx, rv7xx */
970 0 : if ((rdev->family >= CHIP_RV610) &&
971 0 : (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
972 0 : selected_sclk = radeon_dpm_get_sclk(rdev, low);
973 : else
974 0 : selected_sclk = rdev->pm.current_sclk;
975 :
976 : /* sclk in Mhz */
977 : a.full = dfixed_const(100);
978 0 : sclk.full = dfixed_const(selected_sclk);
979 0 : sclk.full = dfixed_div(sclk, a);
980 :
981 0 : if (crtc->vsc.full > dfixed_const(2))
982 0 : wm->num_line_pair.full = dfixed_const(2);
983 : else
984 0 : wm->num_line_pair.full = dfixed_const(1);
985 :
986 0 : b.full = dfixed_const(mode->crtc_hdisplay);
987 : c.full = dfixed_const(256);
988 0 : a.full = dfixed_div(b, c);
989 0 : request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
990 0 : request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
991 0 : if (a.full < dfixed_const(4)) {
992 0 : wm->lb_request_fifo_depth = 4;
993 0 : } else {
994 0 : wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
995 : }
996 :
997 : /* Determine consumption rate
998 : * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
999 : * vtaps = number of vertical taps,
1000 : * vsc = vertical scaling ratio, defined as source/destination
1001 : * hsc = horizontal scaling ration, defined as source/destination
1002 : */
1003 0 : a.full = dfixed_const(mode->clock);
1004 : b.full = dfixed_const(1000);
1005 0 : a.full = dfixed_div(a, b);
1006 0 : pclk.full = dfixed_div(b, a);
1007 0 : if (crtc->rmx_type != RMX_OFF) {
1008 : b.full = dfixed_const(2);
1009 0 : if (crtc->vsc.full > b.full)
1010 0 : b.full = crtc->vsc.full;
1011 0 : b.full = dfixed_mul(b, crtc->hsc);
1012 : c.full = dfixed_const(2);
1013 0 : b.full = dfixed_div(b, c);
1014 0 : consumption_time.full = dfixed_div(pclk, b);
1015 0 : } else {
1016 : consumption_time.full = pclk.full;
1017 : }
1018 : a.full = dfixed_const(1);
1019 0 : wm->consumption_rate.full = dfixed_div(a, consumption_time);
1020 :
1021 :
1022 : /* Determine line time
1023 : * LineTime = total time for one line of displayhtotal
1024 : * LineTime = total number of horizontal pixels
1025 : * pclk = pixel clock period(ns)
1026 : */
1027 0 : a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1028 0 : line_time.full = dfixed_mul(a, pclk);
1029 :
1030 : /* Determine active time
1031 : * ActiveTime = time of active region of display within one line,
1032 : * hactive = total number of horizontal active pixels
1033 : * htotal = total number of horizontal pixels
1034 : */
1035 : a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1036 0 : b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1037 0 : wm->active_time.full = dfixed_mul(line_time, b);
1038 0 : wm->active_time.full = dfixed_div(wm->active_time, a);
1039 :
1040 : /* Determine chunk time
1041 : * ChunkTime = the time it takes the DCP to send one chunk of data
1042 : * to the LB which consists of pipeline delay and inter chunk gap
1043 : * sclk = system clock(Mhz)
1044 : */
1045 : a.full = dfixed_const(600 * 1000);
1046 0 : chunk_time.full = dfixed_div(a, sclk);
1047 : read_delay_latency.full = dfixed_const(1000);
1048 :
1049 : /* Determine the worst case latency
1050 : * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1051 : * WorstCaseLatency = worst case time from urgent to when the MC starts
1052 : * to return data
1053 : * READ_DELAY_IDLE_MAX = constant of 1us
1054 : * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1055 : * which consists of pipeline delay and inter chunk gap
1056 : */
1057 0 : if (dfixed_trunc(wm->num_line_pair) > 1) {
1058 : a.full = dfixed_const(3);
1059 0 : wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1060 0 : wm->worst_case_latency.full += read_delay_latency.full;
1061 0 : } else {
1062 0 : wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1063 : }
1064 :
1065 : /* Determine the tolerable latency
1066 : * TolerableLatency = Any given request has only 1 line time
1067 : * for the data to be returned
1068 : * LBRequestFifoDepth = Number of chunk requests the LB can
1069 : * put into the request FIFO for a display
1070 : * LineTime = total time for one line of display
1071 : * ChunkTime = the time it takes the DCP to send one chunk
1072 : * of data to the LB which consists of
1073 : * pipeline delay and inter chunk gap
1074 : */
1075 0 : if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1076 : tolerable_latency.full = line_time.full;
1077 0 : } else {
1078 0 : tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1079 0 : tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1080 0 : tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1081 0 : tolerable_latency.full = line_time.full - tolerable_latency.full;
1082 : }
1083 : /* We assume worst case 32bits (4 bytes) */
1084 0 : wm->dbpp.full = dfixed_const(2 * 16);
1085 :
1086 : /* Determine the maximum priority mark
1087 : * width = viewport width in pixels
1088 : */
1089 : a.full = dfixed_const(16);
1090 0 : wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1091 0 : wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1092 0 : wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1093 :
1094 : /* Determine estimated width */
1095 0 : estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1096 0 : estimated_width.full = dfixed_div(estimated_width, consumption_time);
1097 0 : if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1098 0 : wm->priority_mark.full = wm->priority_mark_max.full;
1099 0 : } else {
1100 : a.full = dfixed_const(16);
1101 0 : wm->priority_mark.full = dfixed_div(estimated_width, a);
1102 0 : wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1103 0 : wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1104 : }
1105 0 : }
1106 :
1107 0 : static void rv515_compute_mode_priority(struct radeon_device *rdev,
1108 : struct rv515_watermark *wm0,
1109 : struct rv515_watermark *wm1,
1110 : struct drm_display_mode *mode0,
1111 : struct drm_display_mode *mode1,
1112 : u32 *d1mode_priority_a_cnt,
1113 : u32 *d2mode_priority_a_cnt)
1114 : {
1115 : fixed20_12 priority_mark02, priority_mark12, fill_rate;
1116 : fixed20_12 a, b;
1117 :
1118 0 : *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1119 0 : *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1120 :
1121 0 : if (mode0 && mode1) {
1122 0 : if (dfixed_trunc(wm0->dbpp) > 64)
1123 0 : a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1124 : else
1125 0 : a.full = wm0->num_line_pair.full;
1126 0 : if (dfixed_trunc(wm1->dbpp) > 64)
1127 0 : b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1128 : else
1129 0 : b.full = wm1->num_line_pair.full;
1130 0 : a.full += b.full;
1131 0 : fill_rate.full = dfixed_div(wm0->sclk, a);
1132 0 : if (wm0->consumption_rate.full > fill_rate.full) {
1133 0 : b.full = wm0->consumption_rate.full - fill_rate.full;
1134 0 : b.full = dfixed_mul(b, wm0->active_time);
1135 : a.full = dfixed_const(16);
1136 0 : b.full = dfixed_div(b, a);
1137 0 : a.full = dfixed_mul(wm0->worst_case_latency,
1138 : wm0->consumption_rate);
1139 0 : priority_mark02.full = a.full + b.full;
1140 0 : } else {
1141 0 : a.full = dfixed_mul(wm0->worst_case_latency,
1142 : wm0->consumption_rate);
1143 : b.full = dfixed_const(16 * 1000);
1144 0 : priority_mark02.full = dfixed_div(a, b);
1145 : }
1146 0 : if (wm1->consumption_rate.full > fill_rate.full) {
1147 0 : b.full = wm1->consumption_rate.full - fill_rate.full;
1148 0 : b.full = dfixed_mul(b, wm1->active_time);
1149 : a.full = dfixed_const(16);
1150 0 : b.full = dfixed_div(b, a);
1151 0 : a.full = dfixed_mul(wm1->worst_case_latency,
1152 : wm1->consumption_rate);
1153 0 : priority_mark12.full = a.full + b.full;
1154 0 : } else {
1155 0 : a.full = dfixed_mul(wm1->worst_case_latency,
1156 : wm1->consumption_rate);
1157 : b.full = dfixed_const(16 * 1000);
1158 0 : priority_mark12.full = dfixed_div(a, b);
1159 : }
1160 0 : if (wm0->priority_mark.full > priority_mark02.full)
1161 0 : priority_mark02.full = wm0->priority_mark.full;
1162 0 : if (wm0->priority_mark_max.full > priority_mark02.full)
1163 0 : priority_mark02.full = wm0->priority_mark_max.full;
1164 0 : if (wm1->priority_mark.full > priority_mark12.full)
1165 0 : priority_mark12.full = wm1->priority_mark.full;
1166 0 : if (wm1->priority_mark_max.full > priority_mark12.full)
1167 0 : priority_mark12.full = wm1->priority_mark_max.full;
1168 0 : *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1169 0 : *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1170 0 : if (rdev->disp_priority == 2) {
1171 0 : *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1172 0 : *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1173 0 : }
1174 0 : } else if (mode0) {
1175 0 : if (dfixed_trunc(wm0->dbpp) > 64)
1176 0 : a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1177 : else
1178 0 : a.full = wm0->num_line_pair.full;
1179 0 : fill_rate.full = dfixed_div(wm0->sclk, a);
1180 0 : if (wm0->consumption_rate.full > fill_rate.full) {
1181 0 : b.full = wm0->consumption_rate.full - fill_rate.full;
1182 0 : b.full = dfixed_mul(b, wm0->active_time);
1183 : a.full = dfixed_const(16);
1184 0 : b.full = dfixed_div(b, a);
1185 0 : a.full = dfixed_mul(wm0->worst_case_latency,
1186 : wm0->consumption_rate);
1187 0 : priority_mark02.full = a.full + b.full;
1188 0 : } else {
1189 0 : a.full = dfixed_mul(wm0->worst_case_latency,
1190 : wm0->consumption_rate);
1191 : b.full = dfixed_const(16);
1192 0 : priority_mark02.full = dfixed_div(a, b);
1193 : }
1194 0 : if (wm0->priority_mark.full > priority_mark02.full)
1195 0 : priority_mark02.full = wm0->priority_mark.full;
1196 0 : if (wm0->priority_mark_max.full > priority_mark02.full)
1197 0 : priority_mark02.full = wm0->priority_mark_max.full;
1198 0 : *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1199 0 : if (rdev->disp_priority == 2)
1200 0 : *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1201 0 : } else if (mode1) {
1202 0 : if (dfixed_trunc(wm1->dbpp) > 64)
1203 0 : a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1204 : else
1205 0 : a.full = wm1->num_line_pair.full;
1206 0 : fill_rate.full = dfixed_div(wm1->sclk, a);
1207 0 : if (wm1->consumption_rate.full > fill_rate.full) {
1208 0 : b.full = wm1->consumption_rate.full - fill_rate.full;
1209 0 : b.full = dfixed_mul(b, wm1->active_time);
1210 : a.full = dfixed_const(16);
1211 0 : b.full = dfixed_div(b, a);
1212 0 : a.full = dfixed_mul(wm1->worst_case_latency,
1213 : wm1->consumption_rate);
1214 0 : priority_mark12.full = a.full + b.full;
1215 0 : } else {
1216 0 : a.full = dfixed_mul(wm1->worst_case_latency,
1217 : wm1->consumption_rate);
1218 : b.full = dfixed_const(16 * 1000);
1219 0 : priority_mark12.full = dfixed_div(a, b);
1220 : }
1221 0 : if (wm1->priority_mark.full > priority_mark12.full)
1222 0 : priority_mark12.full = wm1->priority_mark.full;
1223 0 : if (wm1->priority_mark_max.full > priority_mark12.full)
1224 0 : priority_mark12.full = wm1->priority_mark_max.full;
1225 0 : *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1226 0 : if (rdev->disp_priority == 2)
1227 0 : *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1228 : }
1229 0 : }
1230 :
1231 0 : void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1232 : {
1233 : struct drm_display_mode *mode0 = NULL;
1234 : struct drm_display_mode *mode1 = NULL;
1235 0 : struct rv515_watermark wm0_high, wm0_low;
1236 0 : struct rv515_watermark wm1_high, wm1_low;
1237 : u32 tmp;
1238 0 : u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1239 0 : u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1240 :
1241 0 : if (rdev->mode_info.crtcs[0]->base.enabled)
1242 0 : mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1243 0 : if (rdev->mode_info.crtcs[1]->base.enabled)
1244 0 : mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1245 0 : rs690_line_buffer_adjust(rdev, mode0, mode1);
1246 :
1247 0 : rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1248 0 : rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1249 :
1250 0 : rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1251 0 : rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1252 :
1253 0 : tmp = wm0_high.lb_request_fifo_depth;
1254 0 : tmp |= wm1_high.lb_request_fifo_depth << 16;
1255 0 : WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1256 :
1257 0 : rv515_compute_mode_priority(rdev,
1258 : &wm0_high, &wm1_high,
1259 : mode0, mode1,
1260 : &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1261 0 : rv515_compute_mode_priority(rdev,
1262 : &wm0_low, &wm1_low,
1263 : mode0, mode1,
1264 : &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1265 :
1266 0 : WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1267 0 : WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1268 0 : WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1269 0 : WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1270 0 : }
1271 :
1272 0 : void rv515_bandwidth_update(struct radeon_device *rdev)
1273 : {
1274 : uint32_t tmp;
1275 : struct drm_display_mode *mode0 = NULL;
1276 : struct drm_display_mode *mode1 = NULL;
1277 :
1278 0 : if (!rdev->mode_info.mode_config_initialized)
1279 0 : return;
1280 :
1281 0 : radeon_update_display_priority(rdev);
1282 :
1283 0 : if (rdev->mode_info.crtcs[0]->base.enabled)
1284 0 : mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1285 0 : if (rdev->mode_info.crtcs[1]->base.enabled)
1286 0 : mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1287 : /*
1288 : * Set display0/1 priority up in the memory controller for
1289 : * modes if the user specifies HIGH for displaypriority
1290 : * option.
1291 : */
1292 0 : if ((rdev->disp_priority == 2) &&
1293 0 : (rdev->family == CHIP_RV515)) {
1294 0 : tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1295 0 : tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1296 0 : tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1297 0 : if (mode1)
1298 0 : tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1299 0 : if (mode0)
1300 0 : tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1301 0 : WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1302 0 : }
1303 0 : rv515_bandwidth_avivo_update(rdev);
1304 0 : }
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