Line data Source code
1 : /*
2 : * Copyright 2011 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: Alex Deucher
23 : */
24 :
25 : #include <dev/pci/drm/drmP.h>
26 : #include "radeon.h"
27 : #include "radeon_asic.h"
28 : #include "rv6xxd.h"
29 : #include "r600_dpm.h"
30 : #include "rv6xx_dpm.h"
31 : #include "atom.h"
32 :
33 : static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
34 : u32 unscaled_count, u32 unit);
35 :
36 0 : static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps)
37 : {
38 0 : struct rv6xx_ps *ps = rps->ps_priv;
39 :
40 0 : return ps;
41 : }
42 :
43 0 : static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev)
44 : {
45 0 : struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
46 :
47 0 : return pi;
48 : }
49 :
50 0 : static void rv6xx_force_pcie_gen1(struct radeon_device *rdev)
51 : {
52 : u32 tmp;
53 : int i;
54 :
55 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
56 0 : tmp &= LC_GEN2_EN;
57 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
58 :
59 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
60 0 : tmp |= LC_INITIATE_LINK_SPEED_CHANGE;
61 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
62 :
63 0 : for (i = 0; i < rdev->usec_timeout; i++) {
64 0 : if (!(RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE))
65 : break;
66 0 : udelay(1);
67 : }
68 :
69 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
70 0 : tmp &= ~LC_INITIATE_LINK_SPEED_CHANGE;
71 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
72 0 : }
73 :
74 0 : static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev)
75 : {
76 : u32 tmp;
77 :
78 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
79 :
80 0 : if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
81 0 : (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
82 0 : tmp |= LC_GEN2_EN;
83 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
84 0 : }
85 0 : }
86 :
87 0 : static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
88 : bool enable)
89 : {
90 : u32 tmp;
91 :
92 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
93 0 : if (enable)
94 0 : tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
95 : else
96 : tmp |= LC_HW_VOLTAGE_IF_CONTROL(0);
97 0 : WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
98 0 : }
99 :
100 0 : static void rv6xx_enable_l0s(struct radeon_device *rdev)
101 : {
102 : u32 tmp;
103 :
104 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L0S_INACTIVITY_MASK;
105 0 : tmp |= LC_L0S_INACTIVITY(3);
106 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
107 0 : }
108 :
109 0 : static void rv6xx_enable_l1(struct radeon_device *rdev)
110 : {
111 : u32 tmp;
112 :
113 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL);
114 0 : tmp &= ~LC_L1_INACTIVITY_MASK;
115 0 : tmp |= LC_L1_INACTIVITY(4);
116 0 : tmp &= ~LC_PMI_TO_L1_DIS;
117 0 : tmp &= ~LC_ASPM_TO_L1_DIS;
118 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
119 0 : }
120 :
121 0 : static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev)
122 : {
123 : u32 tmp;
124 :
125 0 : tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL) & ~LC_L1_INACTIVITY_MASK;
126 0 : tmp |= LC_L1_INACTIVITY(8);
127 0 : WREG32_PCIE_PORT(PCIE_LC_CNTL, tmp);
128 :
129 : /* NOTE, this is a PCIE indirect reg, not PCIE PORT */
130 0 : tmp = RREG32_PCIE(PCIE_P_CNTL);
131 0 : tmp |= P_PLL_PWRDN_IN_L1L23;
132 0 : tmp &= ~P_PLL_BUF_PDNB;
133 0 : tmp &= ~P_PLL_PDNB;
134 0 : tmp |= P_ALLOW_PRX_FRONTEND_SHUTOFF;
135 0 : WREG32_PCIE(PCIE_P_CNTL, tmp);
136 0 : }
137 :
138 0 : static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev,
139 : u32 clock, struct rv6xx_sclk_stepping *step)
140 : {
141 : int ret;
142 0 : struct atom_clock_dividers dividers;
143 :
144 0 : ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
145 : clock, false, ÷rs);
146 0 : if (ret)
147 0 : return ret;
148 :
149 0 : if (dividers.enable_post_div)
150 0 : step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4);
151 : else
152 0 : step->post_divider = 1;
153 :
154 0 : step->vco_frequency = clock * step->post_divider;
155 :
156 0 : return 0;
157 0 : }
158 :
159 0 : static void rv6xx_output_stepping(struct radeon_device *rdev,
160 : u32 step_index, struct rv6xx_sclk_stepping *step)
161 : {
162 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
163 0 : u32 ref_clk = rdev->clock.spll.reference_freq;
164 : u32 fb_divider;
165 0 : u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,
166 0 : R600_SPLLSTEPTIME_DFLT *
167 0 : pi->spll_ref_div,
168 : R600_SPLLSTEPUNIT_DFLT);
169 :
170 0 : r600_engine_clock_entry_enable(rdev, step_index, true);
171 0 : r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
172 :
173 0 : if (step->post_divider == 1)
174 0 : r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
175 : else {
176 0 : u32 lo_len = (step->post_divider - 2) / 2;
177 0 : u32 hi_len = step->post_divider - 2 - lo_len;
178 :
179 0 : r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
180 0 : r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len);
181 : }
182 :
183 0 : fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >>
184 0 : pi->fb_div_scale;
185 :
186 0 : r600_engine_clock_entry_set_reference_divider(rdev, step_index,
187 0 : pi->spll_ref_div - 1);
188 0 : r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
189 0 : r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);
190 :
191 0 : }
192 :
193 0 : static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev,
194 : struct rv6xx_sclk_stepping *cur,
195 : bool increasing_vco, u32 step_size)
196 : {
197 : struct rv6xx_sclk_stepping next;
198 :
199 0 : next.post_divider = cur->post_divider;
200 :
201 0 : if (increasing_vco)
202 0 : next.vco_frequency = (cur->vco_frequency * (100 + step_size)) / 100;
203 : else
204 0 : next.vco_frequency = (cur->vco_frequency * 100 + 99 + step_size) / (100 + step_size);
205 :
206 : return next;
207 0 : }
208 :
209 0 : static bool rv6xx_can_step_post_div(struct radeon_device *rdev,
210 : struct rv6xx_sclk_stepping *cur,
211 : struct rv6xx_sclk_stepping *target)
212 : {
213 0 : return (cur->post_divider > target->post_divider) &&
214 0 : ((cur->vco_frequency * target->post_divider) <=
215 0 : (target->vco_frequency * (cur->post_divider - 1)));
216 : }
217 :
218 0 : static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev,
219 : struct rv6xx_sclk_stepping *cur,
220 : struct rv6xx_sclk_stepping *target)
221 : {
222 0 : struct rv6xx_sclk_stepping next = *cur;
223 :
224 0 : while (rv6xx_can_step_post_div(rdev, &next, target))
225 0 : next.post_divider--;
226 :
227 0 : return next;
228 0 : }
229 :
230 0 : static bool rv6xx_reached_stepping_target(struct radeon_device *rdev,
231 : struct rv6xx_sclk_stepping *cur,
232 : struct rv6xx_sclk_stepping *target,
233 : bool increasing_vco)
234 : {
235 0 : return (increasing_vco && (cur->vco_frequency >= target->vco_frequency)) ||
236 0 : (!increasing_vco && (cur->vco_frequency <= target->vco_frequency));
237 : }
238 :
239 0 : static void rv6xx_generate_steps(struct radeon_device *rdev,
240 : u32 low, u32 high,
241 : u32 start_index, u8 *end_index)
242 : {
243 0 : struct rv6xx_sclk_stepping cur;
244 0 : struct rv6xx_sclk_stepping target;
245 : bool increasing_vco;
246 : u32 step_index = start_index;
247 :
248 0 : rv6xx_convert_clock_to_stepping(rdev, low, &cur);
249 0 : rv6xx_convert_clock_to_stepping(rdev, high, &target);
250 :
251 0 : rv6xx_output_stepping(rdev, step_index++, &cur);
252 :
253 0 : increasing_vco = (target.vco_frequency >= cur.vco_frequency);
254 :
255 0 : if (target.post_divider > cur.post_divider)
256 0 : cur.post_divider = target.post_divider;
257 :
258 0 : while (1) {
259 0 : struct rv6xx_sclk_stepping next;
260 :
261 0 : if (rv6xx_can_step_post_div(rdev, &cur, &target))
262 0 : next = rv6xx_next_post_div_step(rdev, &cur, &target);
263 : else
264 0 : next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT);
265 :
266 0 : if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) {
267 0 : struct rv6xx_sclk_stepping tiny =
268 0 : rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT);
269 0 : tiny.post_divider = next.post_divider;
270 :
271 0 : if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco))
272 0 : rv6xx_output_stepping(rdev, step_index++, &tiny);
273 :
274 0 : if ((next.post_divider != target.post_divider) &&
275 0 : (next.vco_frequency != target.vco_frequency)) {
276 0 : struct rv6xx_sclk_stepping final_vco;
277 :
278 0 : final_vco.vco_frequency = target.vco_frequency;
279 0 : final_vco.post_divider = next.post_divider;
280 :
281 0 : rv6xx_output_stepping(rdev, step_index++, &final_vco);
282 0 : }
283 :
284 0 : rv6xx_output_stepping(rdev, step_index++, &target);
285 : break;
286 0 : } else
287 0 : rv6xx_output_stepping(rdev, step_index++, &next);
288 :
289 0 : cur = next;
290 0 : }
291 :
292 0 : *end_index = (u8)step_index - 1;
293 :
294 0 : }
295 :
296 0 : static void rv6xx_generate_single_step(struct radeon_device *rdev,
297 : u32 clock, u32 index)
298 : {
299 0 : struct rv6xx_sclk_stepping step;
300 :
301 0 : rv6xx_convert_clock_to_stepping(rdev, clock, &step);
302 0 : rv6xx_output_stepping(rdev, index, &step);
303 0 : }
304 :
305 0 : static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev,
306 : u32 start_index, u32 end_index)
307 : {
308 : u32 step_index;
309 :
310 0 : for (step_index = start_index + 1; step_index < end_index; step_index++)
311 0 : r600_engine_clock_entry_enable(rdev, step_index, false);
312 0 : }
313 :
314 0 : static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev,
315 : u32 index, u32 clk_s)
316 : {
317 0 : WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
318 : CLKS(clk_s), ~CLKS_MASK);
319 0 : }
320 :
321 0 : static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev,
322 : u32 index, u32 clk_v)
323 : {
324 0 : WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
325 : CLKV(clk_v), ~CLKV_MASK);
326 0 : }
327 :
328 0 : static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev,
329 : u32 index, bool enable)
330 : {
331 0 : if (enable)
332 0 : WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
333 : SSEN, ~SSEN);
334 : else
335 0 : WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4),
336 : 0, ~SSEN);
337 0 : }
338 :
339 0 : static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev,
340 : u32 clk_s)
341 : {
342 0 : WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);
343 0 : }
344 :
345 0 : static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev,
346 : u32 clk_v)
347 : {
348 0 : WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK);
349 0 : }
350 :
351 0 : static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev,
352 : bool enable)
353 : {
354 0 : if (enable)
355 0 : WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN);
356 : else
357 0 : WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN);
358 0 : }
359 :
360 0 : static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev,
361 : bool enable)
362 : {
363 0 : if (enable)
364 0 : WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
365 : else
366 0 : WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
367 0 : }
368 :
369 0 : static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev,
370 : u32 index, bool enable)
371 : {
372 0 : if (enable)
373 0 : WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
374 : LEVEL0_MPLL_DIV_EN, ~LEVEL0_MPLL_DIV_EN);
375 : else
376 0 : WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), 0, ~LEVEL0_MPLL_DIV_EN);
377 0 : }
378 :
379 0 : static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev,
380 : u32 index, u32 divider)
381 : {
382 0 : WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
383 : LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);
384 0 : }
385 :
386 0 : static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev,
387 : u32 index, u32 divider)
388 : {
389 0 : WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), LEVEL0_MPLL_FB_DIV(divider),
390 : ~LEVEL0_MPLL_FB_DIV_MASK);
391 0 : }
392 :
393 0 : static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev,
394 : u32 index, u32 divider)
395 : {
396 0 : WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4),
397 : LEVEL0_MPLL_REF_DIV(divider), ~LEVEL0_MPLL_REF_DIV_MASK);
398 0 : }
399 :
400 0 : static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)
401 : {
402 0 : WREG32_P(VID_RT, BRT(rt), ~BRT_MASK);
403 0 : }
404 :
405 0 : static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev)
406 : {
407 0 : WREG32_P(SPLL_CNTL_MODE, SPLL_DIV_SYNC, ~SPLL_DIV_SYNC);
408 0 : }
409 :
410 0 : static u32 rv6xx_clocks_per_unit(u32 unit)
411 : {
412 0 : u32 tmp = 1 << (2 * unit);
413 :
414 0 : return tmp;
415 : }
416 :
417 0 : static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
418 : u32 unscaled_count, u32 unit)
419 : {
420 0 : u32 count_per_unit = rv6xx_clocks_per_unit(unit);
421 :
422 0 : return (unscaled_count + count_per_unit - 1) / count_per_unit;
423 : }
424 :
425 0 : static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,
426 : u32 delay_us, u32 unit)
427 : {
428 0 : u32 ref_clk = rdev->clock.spll.reference_freq;
429 :
430 0 : return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit);
431 : }
432 :
433 0 : static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev,
434 : struct rv6xx_ps *state)
435 : {
436 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
437 :
438 0 : pi->hw.sclks[R600_POWER_LEVEL_LOW] =
439 0 : state->low.sclk;
440 0 : pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] =
441 0 : state->medium.sclk;
442 0 : pi->hw.sclks[R600_POWER_LEVEL_HIGH] =
443 0 : state->high.sclk;
444 :
445 0 : pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;
446 0 : pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM;
447 0 : pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;
448 0 : }
449 :
450 0 : static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev,
451 : struct rv6xx_ps *state)
452 : {
453 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
454 :
455 0 : pi->hw.mclks[R600_POWER_LEVEL_CTXSW] =
456 0 : state->high.mclk;
457 0 : pi->hw.mclks[R600_POWER_LEVEL_HIGH] =
458 0 : state->high.mclk;
459 0 : pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] =
460 0 : state->medium.mclk;
461 0 : pi->hw.mclks[R600_POWER_LEVEL_LOW] =
462 0 : state->low.mclk;
463 :
464 0 : pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;
465 :
466 0 : if (state->high.mclk == state->medium.mclk)
467 0 : pi->hw.medium_mclk_index =
468 : pi->hw.high_mclk_index;
469 : else
470 0 : pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM;
471 :
472 :
473 0 : if (state->medium.mclk == state->low.mclk)
474 0 : pi->hw.low_mclk_index =
475 0 : pi->hw.medium_mclk_index;
476 : else
477 0 : pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;
478 0 : }
479 :
480 0 : static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev,
481 : struct rv6xx_ps *state)
482 : {
483 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
484 :
485 0 : pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;
486 0 : pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;
487 0 : pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;
488 0 : pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;
489 :
490 0 : pi->hw.backbias[R600_POWER_LEVEL_CTXSW] =
491 0 : (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
492 0 : pi->hw.backbias[R600_POWER_LEVEL_HIGH] =
493 0 : (state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
494 0 : pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =
495 0 : (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
496 0 : pi->hw.backbias[R600_POWER_LEVEL_LOW] =
497 0 : (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? true : false;
498 :
499 0 : pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =
500 0 : (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
501 0 : pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] =
502 0 : (state->medium.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
503 0 : pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] =
504 0 : (state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? true : false;
505 :
506 0 : pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;
507 :
508 0 : if ((state->high.vddc == state->medium.vddc) &&
509 0 : ((state->high.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
510 0 : (state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
511 0 : pi->hw.medium_vddc_index =
512 : pi->hw.high_vddc_index;
513 : else
514 0 : pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;
515 :
516 0 : if ((state->medium.vddc == state->low.vddc) &&
517 0 : ((state->medium.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ==
518 0 : (state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE)))
519 0 : pi->hw.low_vddc_index =
520 0 : pi->hw.medium_vddc_index;
521 : else
522 0 : pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;
523 0 : }
524 :
525 0 : static inline u32 rv6xx_calculate_vco_frequency(u32 ref_clock,
526 : struct atom_clock_dividers *dividers,
527 : u32 fb_divider_scale)
528 : {
529 0 : return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) /
530 0 : (dividers->ref_div + 1);
531 : }
532 :
533 0 : static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq,
534 : u32 ss_rate, u32 ss_percent,
535 : u32 fb_divider_scale)
536 : {
537 0 : u32 fb_divider = vco_freq / ref_freq;
538 :
539 0 : return (ss_percent * ss_rate * 4 * (fb_divider * fb_divider) /
540 0 : (5375 * ((vco_freq * 10) / (4096 >> fb_divider_scale))));
541 : }
542 :
543 0 : static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq)
544 : {
545 0 : return (((ref_freq * 10) / (ss_rate * 2)) - 1) / 4;
546 : }
547 :
548 0 : static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev,
549 : u32 clock, enum r600_power_level level)
550 : {
551 0 : u32 ref_clk = rdev->clock.spll.reference_freq;
552 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
553 0 : struct atom_clock_dividers dividers;
554 0 : struct radeon_atom_ss ss;
555 : u32 vco_freq, clk_v, clk_s;
556 :
557 0 : rv6xx_enable_engine_spread_spectrum(rdev, level, false);
558 :
559 0 : if (clock && pi->sclk_ss) {
560 0 : if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) {
561 0 : vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs,
562 0 : pi->fb_div_scale);
563 :
564 0 : if (radeon_atombios_get_asic_ss_info(rdev, &ss,
565 : ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
566 0 : clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
567 0 : (ref_clk / (dividers.ref_div + 1)),
568 0 : ss.rate,
569 0 : ss.percentage,
570 0 : pi->fb_div_scale);
571 :
572 0 : clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
573 0 : (ref_clk / (dividers.ref_div + 1)));
574 :
575 0 : rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v);
576 0 : rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
577 0 : rv6xx_enable_engine_spread_spectrum(rdev, level, true);
578 0 : }
579 : }
580 : }
581 0 : }
582 :
583 0 : static void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev)
584 : {
585 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
586 :
587 0 : rv6xx_program_engine_spread_spectrum(rdev,
588 0 : pi->hw.sclks[R600_POWER_LEVEL_HIGH],
589 : R600_POWER_LEVEL_HIGH);
590 :
591 0 : rv6xx_program_engine_spread_spectrum(rdev,
592 0 : pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],
593 : R600_POWER_LEVEL_MEDIUM);
594 :
595 0 : }
596 :
597 0 : static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev,
598 : u32 entry, u32 clock)
599 : {
600 0 : struct atom_clock_dividers dividers;
601 :
602 0 : if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, ÷rs))
603 0 : return -EINVAL;
604 :
605 :
606 0 : rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
607 0 : rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);
608 0 : rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);
609 :
610 0 : if (dividers.enable_post_div)
611 0 : rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true);
612 : else
613 0 : rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);
614 :
615 0 : return 0;
616 0 : }
617 :
618 0 : static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
619 : {
620 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
621 : int i;
622 :
623 0 : for (i = 1; i < R600_PM_NUMBER_OF_MCLKS; i++) {
624 0 : if (pi->hw.mclks[i])
625 0 : rv6xx_program_mclk_stepping_entry(rdev, i,
626 : pi->hw.mclks[i]);
627 : }
628 0 : }
629 :
630 0 : static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev,
631 : u32 requested_memory_clock,
632 : u32 ref_clk,
633 : struct atom_clock_dividers *dividers,
634 : u32 *vco_freq)
635 : {
636 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
637 0 : struct atom_clock_dividers req_dividers;
638 : u32 vco_freq_temp;
639 :
640 0 : if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
641 0 : requested_memory_clock, false, &req_dividers) == 0) {
642 0 : vco_freq_temp = rv6xx_calculate_vco_frequency(ref_clk, &req_dividers,
643 0 : pi->fb_div_scale);
644 :
645 0 : if (vco_freq_temp > *vco_freq) {
646 0 : *dividers = req_dividers;
647 0 : *vco_freq = vco_freq_temp;
648 0 : }
649 : }
650 0 : }
651 :
652 0 : static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev)
653 : {
654 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
655 0 : u32 ref_clk = rdev->clock.mpll.reference_freq;
656 0 : struct atom_clock_dividers dividers;
657 0 : struct radeon_atom_ss ss;
658 0 : u32 vco_freq = 0, clk_v, clk_s;
659 :
660 0 : rv6xx_enable_memory_spread_spectrum(rdev, false);
661 :
662 0 : if (pi->mclk_ss) {
663 0 : rv6xx_find_memory_clock_with_highest_vco(rdev,
664 0 : pi->hw.mclks[pi->hw.high_mclk_index],
665 : ref_clk,
666 : ÷rs,
667 : &vco_freq);
668 :
669 0 : rv6xx_find_memory_clock_with_highest_vco(rdev,
670 0 : pi->hw.mclks[pi->hw.medium_mclk_index],
671 : ref_clk,
672 : ÷rs,
673 : &vco_freq);
674 :
675 0 : rv6xx_find_memory_clock_with_highest_vco(rdev,
676 0 : pi->hw.mclks[pi->hw.low_mclk_index],
677 : ref_clk,
678 : ÷rs,
679 : &vco_freq);
680 :
681 0 : if (vco_freq) {
682 0 : if (radeon_atombios_get_asic_ss_info(rdev, &ss,
683 : ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
684 0 : clk_v = rv6xx_calculate_spread_spectrum_clk_v(vco_freq,
685 0 : (ref_clk / (dividers.ref_div + 1)),
686 0 : ss.rate,
687 0 : ss.percentage,
688 0 : pi->fb_div_scale);
689 :
690 0 : clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
691 0 : (ref_clk / (dividers.ref_div + 1)));
692 :
693 0 : rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
694 0 : rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s);
695 0 : rv6xx_enable_memory_spread_spectrum(rdev, true);
696 0 : }
697 : }
698 : }
699 0 : }
700 :
701 0 : static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev,
702 : u32 entry, u16 voltage)
703 : {
704 0 : u32 mask, set_pins;
705 : int ret;
706 :
707 0 : ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage,
708 : SET_VOLTAGE_TYPE_ASIC_VDDC,
709 : &set_pins, &mask);
710 0 : if (ret)
711 0 : return ret;
712 :
713 0 : r600_voltage_control_program_voltages(rdev, entry, set_pins);
714 :
715 0 : return 0;
716 0 : }
717 :
718 0 : static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
719 : {
720 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
721 : int i;
722 :
723 0 : for (i = 1; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++)
724 0 : rv6xx_program_voltage_stepping_entry(rdev, i,
725 0 : pi->hw.vddc[i]);
726 :
727 0 : }
728 :
729 0 : static void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
730 : {
731 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
732 :
733 0 : if (pi->hw.backbias[1])
734 0 : WREG32_P(VID_UPPER_GPIO_CNTL, MEDIUM_BACKBIAS_VALUE, ~MEDIUM_BACKBIAS_VALUE);
735 : else
736 0 : WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~MEDIUM_BACKBIAS_VALUE);
737 :
738 0 : if (pi->hw.backbias[2])
739 0 : WREG32_P(VID_UPPER_GPIO_CNTL, HIGH_BACKBIAS_VALUE, ~HIGH_BACKBIAS_VALUE);
740 : else
741 0 : WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~HIGH_BACKBIAS_VALUE);
742 0 : }
743 :
744 0 : static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev)
745 : {
746 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
747 :
748 0 : rv6xx_program_engine_spread_spectrum(rdev,
749 0 : pi->hw.sclks[R600_POWER_LEVEL_LOW],
750 : R600_POWER_LEVEL_LOW);
751 0 : }
752 :
753 0 : static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev)
754 : {
755 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
756 :
757 0 : if (pi->hw.mclks[0])
758 0 : rv6xx_program_mclk_stepping_entry(rdev, 0,
759 : pi->hw.mclks[0]);
760 0 : }
761 :
762 0 : static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev)
763 : {
764 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
765 :
766 0 : rv6xx_program_voltage_stepping_entry(rdev, 0,
767 0 : pi->hw.vddc[0]);
768 :
769 0 : }
770 :
771 0 : static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev)
772 : {
773 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
774 :
775 0 : if (pi->hw.backbias[0])
776 0 : WREG32_P(VID_UPPER_GPIO_CNTL, LOW_BACKBIAS_VALUE, ~LOW_BACKBIAS_VALUE);
777 : else
778 0 : WREG32_P(VID_UPPER_GPIO_CNTL, 0, ~LOW_BACKBIAS_VALUE);
779 0 : }
780 :
781 0 : static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,
782 : u32 engine_clock)
783 : {
784 : u32 dram_rows, dram_refresh_rate;
785 : u32 tmp;
786 :
787 0 : tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
788 0 : dram_rows = 1 << (tmp + 10);
789 0 : dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3);
790 :
791 0 : return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
792 : }
793 :
794 0 : static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
795 : {
796 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
797 : u32 sqm_ratio;
798 : u32 arb_refresh_rate;
799 : u32 high_clock;
800 :
801 0 : if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <
802 0 : (pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40))
803 0 : high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];
804 : else
805 : high_clock =
806 : pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40;
807 :
808 0 : radeon_atom_set_engine_dram_timings(rdev, high_clock, 0);
809 :
810 0 : sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) |
811 0 : STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) |
812 0 : STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) |
813 0 : STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));
814 0 : WREG32(SQM_RATIO, sqm_ratio);
815 :
816 : arb_refresh_rate =
817 0 : (POWERMODE0(calculate_memory_refresh_rate(rdev,
818 0 : pi->hw.sclks[R600_POWER_LEVEL_LOW])) |
819 0 : POWERMODE1(calculate_memory_refresh_rate(rdev,
820 0 : pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
821 0 : POWERMODE2(calculate_memory_refresh_rate(rdev,
822 0 : pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
823 0 : POWERMODE3(calculate_memory_refresh_rate(rdev,
824 : pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
825 0 : WREG32(ARB_RFSH_RATE, arb_refresh_rate);
826 0 : }
827 :
828 0 : static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev)
829 : {
830 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
831 :
832 0 : r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT *
833 0 : pi->mpll_ref_div);
834 0 : r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT);
835 0 : }
836 :
837 0 : static void rv6xx_program_bsp(struct radeon_device *rdev)
838 : {
839 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
840 0 : u32 ref_clk = rdev->clock.spll.reference_freq;
841 :
842 0 : r600_calculate_u_and_p(R600_ASI_DFLT,
843 : ref_clk, 16,
844 0 : &pi->bsp,
845 0 : &pi->bsu);
846 :
847 0 : r600_set_bsp(rdev, pi->bsu, pi->bsp);
848 0 : }
849 :
850 0 : static void rv6xx_program_at(struct radeon_device *rdev)
851 : {
852 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
853 :
854 0 : r600_set_at(rdev,
855 0 : (pi->hw.rp[0] * pi->bsp) / 200,
856 0 : (pi->hw.rp[1] * pi->bsp) / 200,
857 0 : (pi->hw.lp[2] * pi->bsp) / 200,
858 0 : (pi->hw.lp[1] * pi->bsp) / 200);
859 0 : }
860 :
861 0 : static void rv6xx_program_git(struct radeon_device *rdev)
862 : {
863 0 : r600_set_git(rdev, R600_GICST_DFLT);
864 0 : }
865 :
866 0 : static void rv6xx_program_tp(struct radeon_device *rdev)
867 : {
868 : int i;
869 :
870 0 : for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
871 0 : r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]);
872 :
873 0 : r600_select_td(rdev, R600_TD_DFLT);
874 0 : }
875 :
876 0 : static void rv6xx_program_vc(struct radeon_device *rdev)
877 : {
878 0 : r600_set_vrc(rdev, R600_VRC_DFLT);
879 0 : }
880 :
881 0 : static void rv6xx_clear_vc(struct radeon_device *rdev)
882 : {
883 0 : r600_set_vrc(rdev, 0);
884 0 : }
885 :
886 0 : static void rv6xx_program_tpp(struct radeon_device *rdev)
887 : {
888 0 : r600_set_tpu(rdev, R600_TPU_DFLT);
889 0 : r600_set_tpc(rdev, R600_TPC_DFLT);
890 0 : }
891 :
892 0 : static void rv6xx_program_sstp(struct radeon_device *rdev)
893 : {
894 0 : r600_set_sstu(rdev, R600_SSTU_DFLT);
895 0 : r600_set_sst(rdev, R600_SST_DFLT);
896 0 : }
897 :
898 0 : static void rv6xx_program_fcp(struct radeon_device *rdev)
899 : {
900 0 : r600_set_fctu(rdev, R600_FCTU_DFLT);
901 0 : r600_set_fct(rdev, R600_FCT_DFLT);
902 0 : }
903 :
904 0 : static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev)
905 : {
906 0 : r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
907 0 : r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
908 0 : r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
909 0 : r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
910 0 : r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
911 0 : }
912 :
913 0 : static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev)
914 : {
915 : u32 rt;
916 :
917 0 : r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
918 :
919 0 : r600_vid_rt_set_vrt(rdev,
920 0 : rv6xx_compute_count_for_delay(rdev,
921 0 : rdev->pm.dpm.voltage_response_time,
922 : R600_VRU_DFLT));
923 :
924 0 : rt = rv6xx_compute_count_for_delay(rdev,
925 0 : rdev->pm.dpm.backbias_response_time,
926 : R600_VRU_DFLT);
927 :
928 0 : rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5);
929 0 : }
930 :
931 0 : static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev)
932 : {
933 0 : r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
934 0 : rv6xx_enable_engine_feedback_and_reference_sync(rdev);
935 0 : }
936 :
937 0 : static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev)
938 : {
939 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
940 : u64 master_mask = 0;
941 : int i;
942 :
943 0 : for (i = 0; i < R600_PM_NUMBER_OF_VOLTAGE_LEVELS; i++) {
944 0 : u32 tmp_mask, tmp_set_pins;
945 : int ret;
946 :
947 0 : ret = radeon_atom_get_voltage_gpio_settings(rdev,
948 0 : pi->hw.vddc[i],
949 : SET_VOLTAGE_TYPE_ASIC_VDDC,
950 : &tmp_set_pins, &tmp_mask);
951 :
952 0 : if (ret == 0)
953 0 : master_mask |= tmp_mask;
954 0 : }
955 :
956 0 : return master_mask;
957 : }
958 :
959 0 : static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev)
960 : {
961 0 : r600_voltage_control_enable_pins(rdev,
962 0 : rv6xx_get_master_voltage_mask(rdev));
963 0 : }
964 :
965 0 : static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
966 : struct radeon_ps *new_ps,
967 : bool enable)
968 : {
969 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
970 :
971 0 : if (enable)
972 0 : radeon_atom_set_voltage(rdev,
973 0 : new_state->low.vddc,
974 : SET_VOLTAGE_TYPE_ASIC_VDDC);
975 : else
976 0 : r600_voltage_control_deactivate_static_control(rdev,
977 0 : rv6xx_get_master_voltage_mask(rdev));
978 0 : }
979 :
980 0 : static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
981 : {
982 0 : if (enable) {
983 : u32 tmp = (DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
984 : DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM) |
985 : DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
986 : DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE) |
987 : VBI_TIMER_COUNT(0x3FFF) |
988 : VBI_TIMER_UNIT(7));
989 0 : WREG32(CG_DISPLAY_GAP_CNTL, tmp);
990 :
991 0 : WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);
992 0 : } else
993 0 : WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);
994 0 : }
995 :
996 0 : static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev)
997 : {
998 0 : r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM);
999 0 : }
1000 :
1001 0 : static void rv6xx_calculate_t(u32 l_f, u32 h_f, int h,
1002 : int d_l, int d_r, u8 *l, u8 *r)
1003 : {
1004 : int a_n, a_d, h_r, l_r;
1005 :
1006 : h_r = d_l;
1007 0 : l_r = 100 - d_r;
1008 :
1009 0 : a_n = (int)h_f * d_l + (int)l_f * (h - d_r);
1010 0 : a_d = (int)l_f * l_r + (int)h_f * h_r;
1011 :
1012 0 : if (a_d != 0) {
1013 0 : *l = d_l - h_r * a_n / a_d;
1014 0 : *r = d_r + l_r * a_n / a_d;
1015 0 : }
1016 0 : }
1017 :
1018 0 : static void rv6xx_calculate_ap(struct radeon_device *rdev,
1019 : struct rv6xx_ps *state)
1020 : {
1021 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1022 :
1023 0 : pi->hw.lp[0] = 0;
1024 0 : pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS - 1]
1025 0 : = 100;
1026 :
1027 0 : rv6xx_calculate_t(state->low.sclk,
1028 0 : state->medium.sclk,
1029 : R600_AH_DFLT,
1030 : R600_LMP_DFLT,
1031 : R600_RLP_DFLT,
1032 0 : &pi->hw.lp[1],
1033 0 : &pi->hw.rp[0]);
1034 :
1035 0 : rv6xx_calculate_t(state->medium.sclk,
1036 0 : state->high.sclk,
1037 : R600_AH_DFLT,
1038 : R600_LHP_DFLT,
1039 : R600_RMP_DFLT,
1040 0 : &pi->hw.lp[2],
1041 0 : &pi->hw.rp[1]);
1042 :
1043 0 : }
1044 :
1045 0 : static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev,
1046 : struct radeon_ps *new_ps)
1047 : {
1048 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1049 :
1050 0 : rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
1051 0 : rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state);
1052 0 : rv6xx_calculate_voltage_stepping_parameters(rdev, new_state);
1053 0 : rv6xx_calculate_ap(rdev, new_state);
1054 0 : }
1055 :
1056 0 : static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
1057 : {
1058 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1059 :
1060 0 : rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev);
1061 0 : if (pi->voltage_control)
1062 0 : rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev);
1063 0 : rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev);
1064 0 : rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev);
1065 0 : rv6xx_program_mclk_spread_spectrum_parameters(rdev);
1066 0 : rv6xx_program_memory_timing_parameters(rdev);
1067 0 : }
1068 :
1069 0 : static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev)
1070 : {
1071 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1072 :
1073 0 : rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev);
1074 0 : if (pi->voltage_control)
1075 0 : rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev);
1076 0 : rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev);
1077 0 : rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev);
1078 0 : }
1079 :
1080 0 : static void rv6xx_program_power_level_low(struct radeon_device *rdev)
1081 : {
1082 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1083 :
1084 0 : r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,
1085 0 : pi->hw.low_vddc_index);
1086 0 : r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,
1087 0 : pi->hw.low_mclk_index);
1088 0 : r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,
1089 0 : pi->hw.low_sclk_index);
1090 0 : r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1091 : R600_DISPLAY_WATERMARK_LOW);
1092 0 : r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1093 0 : pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1094 0 : }
1095 :
1096 0 : static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev)
1097 : {
1098 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1099 :
1100 0 : r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
1101 0 : r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1102 0 : r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1103 :
1104 0 : r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1105 : R600_DISPLAY_WATERMARK_LOW);
1106 :
1107 0 : r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1108 0 : pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1109 :
1110 0 : }
1111 :
1112 0 : static void rv6xx_program_power_level_medium(struct radeon_device *rdev)
1113 : {
1114 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1115 :
1116 0 : r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,
1117 0 : pi->hw.medium_vddc_index);
1118 0 : r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1119 0 : pi->hw.medium_mclk_index);
1120 0 : r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1121 0 : pi->hw.medium_sclk_index);
1122 0 : r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1123 : R600_DISPLAY_WATERMARK_LOW);
1124 0 : r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1125 0 : pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);
1126 0 : }
1127 :
1128 0 : static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev)
1129 : {
1130 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1131 :
1132 0 : rv6xx_program_mclk_stepping_entry(rdev,
1133 : R600_POWER_LEVEL_CTXSW,
1134 0 : pi->hw.mclks[pi->hw.low_mclk_index]);
1135 :
1136 0 : r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1);
1137 :
1138 0 : r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1139 : R600_POWER_LEVEL_CTXSW);
1140 0 : r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1141 0 : pi->hw.medium_sclk_index);
1142 :
1143 0 : r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1144 : R600_DISPLAY_WATERMARK_LOW);
1145 :
1146 0 : rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1147 :
1148 0 : r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1149 0 : pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);
1150 0 : }
1151 :
1152 0 : static void rv6xx_program_power_level_high(struct radeon_device *rdev)
1153 : {
1154 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1155 :
1156 0 : r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,
1157 0 : pi->hw.high_vddc_index);
1158 0 : r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1159 0 : pi->hw.high_mclk_index);
1160 0 : r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1161 0 : pi->hw.high_sclk_index);
1162 :
1163 0 : r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
1164 : R600_DISPLAY_WATERMARK_HIGH);
1165 :
1166 0 : r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
1167 0 : pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);
1168 0 : }
1169 :
1170 0 : static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
1171 : {
1172 0 : if (enable)
1173 0 : WREG32_P(GENERAL_PWRMGT, BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL,
1174 : ~(BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
1175 : else
1176 0 : WREG32_P(GENERAL_PWRMGT, 0,
1177 : ~(BACKBIAS_VALUE | BACKBIAS_PAD_EN | BACKBIAS_DPM_CNTL));
1178 0 : }
1179 :
1180 0 : static void rv6xx_program_display_gap(struct radeon_device *rdev)
1181 : {
1182 0 : u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1183 :
1184 0 : tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1185 0 : if (rdev->pm.dpm.new_active_crtcs & 1) {
1186 0 : tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1187 0 : tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1188 0 : } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1189 : tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1190 0 : tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1191 0 : } else {
1192 : tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1193 0 : tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1194 : }
1195 0 : WREG32(CG_DISPLAY_GAP_CNTL, tmp);
1196 0 : }
1197 :
1198 0 : static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev,
1199 : struct radeon_ps *new_ps,
1200 : struct radeon_ps *old_ps)
1201 : {
1202 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1203 0 : struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1204 : u16 safe_voltage;
1205 :
1206 0 : safe_voltage = (new_state->low.vddc >= old_state->low.vddc) ?
1207 : new_state->low.vddc : old_state->low.vddc;
1208 :
1209 0 : rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1210 : safe_voltage);
1211 :
1212 0 : WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1213 : ~SW_GPIO_INDEX_MASK);
1214 0 : }
1215 :
1216 0 : static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev,
1217 : struct radeon_ps *old_ps)
1218 : {
1219 0 : struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1220 :
1221 0 : rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1222 0 : old_state->low.vddc);
1223 :
1224 0 : WREG32_P(GENERAL_PWRMGT, SW_GPIO_INDEX(R600_POWER_LEVEL_CTXSW),
1225 : ~SW_GPIO_INDEX_MASK);
1226 0 : }
1227 :
1228 0 : static void rv6xx_set_safe_backbias(struct radeon_device *rdev,
1229 : struct radeon_ps *new_ps,
1230 : struct radeon_ps *old_ps)
1231 : {
1232 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1233 0 : struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1234 :
1235 0 : if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) &&
1236 0 : (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))
1237 0 : WREG32_P(GENERAL_PWRMGT, BACKBIAS_VALUE, ~BACKBIAS_VALUE);
1238 : else
1239 0 : WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
1240 0 : }
1241 :
1242 0 : static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev,
1243 : struct radeon_ps *new_ps,
1244 : struct radeon_ps *old_ps)
1245 : {
1246 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1247 0 : struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1248 :
1249 0 : if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) !=
1250 0 : (old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1251 0 : rv6xx_force_pcie_gen1(rdev);
1252 0 : }
1253 :
1254 0 : static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev,
1255 : bool enable)
1256 : {
1257 0 : if (enable)
1258 0 : WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
1259 : else
1260 0 : WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
1261 0 : }
1262 :
1263 0 : static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev,
1264 : bool enable)
1265 : {
1266 0 : if (enable)
1267 0 : WREG32_P(GENERAL_PWRMGT, BACKBIAS_DPM_CNTL, ~BACKBIAS_DPM_CNTL);
1268 : else
1269 0 : WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_DPM_CNTL);
1270 0 : }
1271 :
1272 0 : static int rv6xx_step_sw_voltage(struct radeon_device *rdev,
1273 : u16 initial_voltage,
1274 : u16 target_voltage)
1275 : {
1276 0 : u16 current_voltage;
1277 0 : u16 true_target_voltage;
1278 0 : u16 voltage_step;
1279 : int signed_voltage_step;
1280 :
1281 0 : if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1282 0 : &voltage_step)) ||
1283 0 : (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1284 0 : initial_voltage, ¤t_voltage)) ||
1285 0 : (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1286 : target_voltage, &true_target_voltage)))
1287 0 : return -EINVAL;
1288 :
1289 0 : if (true_target_voltage < current_voltage)
1290 0 : signed_voltage_step = -(int)voltage_step;
1291 : else
1292 : signed_voltage_step = voltage_step;
1293 :
1294 0 : while (current_voltage != true_target_voltage) {
1295 0 : current_voltage += signed_voltage_step;
1296 0 : rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1297 : current_voltage);
1298 0 : drm_msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1299 : }
1300 :
1301 0 : return 0;
1302 0 : }
1303 :
1304 0 : static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev,
1305 : struct radeon_ps *new_ps,
1306 : struct radeon_ps *old_ps)
1307 : {
1308 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1309 0 : struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1310 :
1311 0 : if (new_state->low.vddc > old_state->low.vddc)
1312 0 : return rv6xx_step_sw_voltage(rdev,
1313 : old_state->low.vddc,
1314 : new_state->low.vddc);
1315 :
1316 0 : return 0;
1317 0 : }
1318 :
1319 0 : static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev,
1320 : struct radeon_ps *new_ps,
1321 : struct radeon_ps *old_ps)
1322 : {
1323 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1324 0 : struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1325 :
1326 0 : if (new_state->low.vddc < old_state->low.vddc)
1327 0 : return rv6xx_step_sw_voltage(rdev,
1328 : old_state->low.vddc,
1329 : new_state->low.vddc);
1330 : else
1331 0 : return 0;
1332 0 : }
1333 :
1334 0 : static void rv6xx_enable_high(struct radeon_device *rdev)
1335 : {
1336 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1337 :
1338 0 : if ((pi->restricted_levels < 1) ||
1339 0 : (pi->restricted_levels == 3))
1340 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1341 0 : }
1342 :
1343 0 : static void rv6xx_enable_medium(struct radeon_device *rdev)
1344 : {
1345 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1346 :
1347 0 : if (pi->restricted_levels < 2)
1348 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1349 0 : }
1350 :
1351 0 : static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1352 : {
1353 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1354 : bool want_thermal_protection;
1355 : enum radeon_dpm_event_src dpm_event_src;
1356 :
1357 0 : switch (sources) {
1358 : case 0:
1359 : default:
1360 : want_thermal_protection = false;
1361 0 : break;
1362 : case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1363 : want_thermal_protection = true;
1364 : dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1365 0 : break;
1366 :
1367 : case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1368 : want_thermal_protection = true;
1369 : dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1370 0 : break;
1371 :
1372 : case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1373 : (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1374 : want_thermal_protection = true;
1375 : dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1376 0 : break;
1377 : }
1378 :
1379 0 : if (want_thermal_protection) {
1380 0 : WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
1381 0 : if (pi->thermal_protection)
1382 0 : WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
1383 : } else {
1384 0 : WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
1385 : }
1386 0 : }
1387 :
1388 0 : static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev,
1389 : enum radeon_dpm_auto_throttle_src source,
1390 : bool enable)
1391 : {
1392 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1393 :
1394 0 : if (enable) {
1395 0 : if (!(pi->active_auto_throttle_sources & (1 << source))) {
1396 0 : pi->active_auto_throttle_sources |= 1 << source;
1397 0 : rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1398 0 : }
1399 : } else {
1400 0 : if (pi->active_auto_throttle_sources & (1 << source)) {
1401 0 : pi->active_auto_throttle_sources &= ~(1 << source);
1402 0 : rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1403 0 : }
1404 : }
1405 0 : }
1406 :
1407 :
1408 0 : static void rv6xx_enable_thermal_protection(struct radeon_device *rdev,
1409 : bool enable)
1410 : {
1411 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1412 :
1413 0 : if (pi->active_auto_throttle_sources)
1414 0 : r600_enable_thermal_protection(rdev, enable);
1415 0 : }
1416 :
1417 0 : static void rv6xx_generate_transition_stepping(struct radeon_device *rdev,
1418 : struct radeon_ps *new_ps,
1419 : struct radeon_ps *old_ps)
1420 : {
1421 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1422 0 : struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
1423 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1424 :
1425 0 : rv6xx_generate_steps(rdev,
1426 0 : old_state->low.sclk,
1427 0 : new_state->low.sclk,
1428 0 : 0, &pi->hw.medium_sclk_index);
1429 0 : }
1430 :
1431 0 : static void rv6xx_generate_low_step(struct radeon_device *rdev,
1432 : struct radeon_ps *new_ps)
1433 : {
1434 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1435 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1436 :
1437 0 : pi->hw.low_sclk_index = 0;
1438 0 : rv6xx_generate_single_step(rdev,
1439 0 : new_state->low.sclk,
1440 : 0);
1441 0 : }
1442 :
1443 0 : static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev)
1444 : {
1445 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1446 :
1447 0 : rv6xx_invalidate_intermediate_steps_range(rdev, 0,
1448 0 : pi->hw.medium_sclk_index);
1449 0 : }
1450 :
1451 0 : static void rv6xx_generate_stepping_table(struct radeon_device *rdev,
1452 : struct radeon_ps *new_ps)
1453 : {
1454 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1455 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1456 :
1457 0 : pi->hw.low_sclk_index = 0;
1458 :
1459 0 : rv6xx_generate_steps(rdev,
1460 0 : new_state->low.sclk,
1461 0 : new_state->medium.sclk,
1462 : 0,
1463 0 : &pi->hw.medium_sclk_index);
1464 0 : rv6xx_generate_steps(rdev,
1465 0 : new_state->medium.sclk,
1466 0 : new_state->high.sclk,
1467 0 : pi->hw.medium_sclk_index,
1468 0 : &pi->hw.high_sclk_index);
1469 0 : }
1470 :
1471 0 : static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev,
1472 : bool enable)
1473 : {
1474 0 : if (enable)
1475 0 : rv6xx_enable_dynamic_spread_spectrum(rdev, true);
1476 : else {
1477 0 : rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false);
1478 0 : rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1479 0 : rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
1480 0 : rv6xx_enable_dynamic_spread_spectrum(rdev, false);
1481 0 : rv6xx_enable_memory_spread_spectrum(rdev, false);
1482 : }
1483 0 : }
1484 :
1485 0 : static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev)
1486 : {
1487 0 : if (ASIC_IS_DCE3(rdev))
1488 0 : WREG32_P(DCE3_LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
1489 : else
1490 0 : WREG32_P(LVTMA_DATA_SYNCHRONIZATION, LVTMA_PFREQCHG, ~LVTMA_PFREQCHG);
1491 0 : }
1492 :
1493 0 : static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1494 : struct radeon_ps *new_ps,
1495 : bool enable)
1496 : {
1497 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1498 :
1499 0 : if (enable) {
1500 0 : rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true);
1501 0 : rv6xx_enable_pcie_gen2_support(rdev);
1502 0 : r600_enable_dynamic_pcie_gen2(rdev, true);
1503 0 : } else {
1504 0 : if (!(new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
1505 0 : rv6xx_force_pcie_gen1(rdev);
1506 0 : rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false);
1507 0 : r600_enable_dynamic_pcie_gen2(rdev, false);
1508 : }
1509 0 : }
1510 :
1511 0 : static void rv6xx_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
1512 : struct radeon_ps *new_ps,
1513 : struct radeon_ps *old_ps)
1514 : {
1515 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1516 0 : struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps);
1517 :
1518 0 : if ((new_ps->vclk == old_ps->vclk) &&
1519 0 : (new_ps->dclk == old_ps->dclk))
1520 0 : return;
1521 :
1522 0 : if (new_state->high.sclk >= current_state->high.sclk)
1523 0 : return;
1524 :
1525 0 : radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1526 0 : }
1527 :
1528 0 : static void rv6xx_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
1529 : struct radeon_ps *new_ps,
1530 : struct radeon_ps *old_ps)
1531 : {
1532 0 : struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
1533 0 : struct rv6xx_ps *current_state = rv6xx_get_ps(old_ps);
1534 :
1535 0 : if ((new_ps->vclk == old_ps->vclk) &&
1536 0 : (new_ps->dclk == old_ps->dclk))
1537 0 : return;
1538 :
1539 0 : if (new_state->high.sclk < current_state->high.sclk)
1540 0 : return;
1541 :
1542 0 : radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1543 0 : }
1544 :
1545 0 : int rv6xx_dpm_enable(struct radeon_device *rdev)
1546 : {
1547 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1548 0 : struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1549 :
1550 0 : if (r600_dynamicpm_enabled(rdev))
1551 0 : return -EINVAL;
1552 :
1553 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1554 0 : rv6xx_enable_backbias(rdev, true);
1555 :
1556 0 : if (pi->dynamic_ss)
1557 0 : rv6xx_enable_spread_spectrum(rdev, true);
1558 :
1559 0 : rv6xx_program_mpll_timing_parameters(rdev);
1560 0 : rv6xx_program_bsp(rdev);
1561 0 : rv6xx_program_git(rdev);
1562 0 : rv6xx_program_tp(rdev);
1563 0 : rv6xx_program_tpp(rdev);
1564 0 : rv6xx_program_sstp(rdev);
1565 0 : rv6xx_program_fcp(rdev);
1566 0 : rv6xx_program_vddc3d_parameters(rdev);
1567 0 : rv6xx_program_voltage_timing_parameters(rdev);
1568 0 : rv6xx_program_engine_speed_parameters(rdev);
1569 :
1570 0 : rv6xx_enable_display_gap(rdev, true);
1571 0 : if (pi->display_gap == false)
1572 0 : rv6xx_enable_display_gap(rdev, false);
1573 :
1574 0 : rv6xx_program_power_level_enter_state(rdev);
1575 :
1576 0 : rv6xx_calculate_stepping_parameters(rdev, boot_ps);
1577 :
1578 0 : if (pi->voltage_control)
1579 0 : rv6xx_program_voltage_gpio_pins(rdev);
1580 :
1581 0 : rv6xx_generate_stepping_table(rdev, boot_ps);
1582 :
1583 0 : rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1584 0 : rv6xx_program_stepping_parameters_lowest_entry(rdev);
1585 :
1586 0 : rv6xx_program_power_level_low(rdev);
1587 0 : rv6xx_program_power_level_medium(rdev);
1588 0 : rv6xx_program_power_level_high(rdev);
1589 0 : rv6xx_program_vc(rdev);
1590 0 : rv6xx_program_at(rdev);
1591 :
1592 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1593 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1594 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1595 :
1596 0 : rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1597 :
1598 0 : r600_start_dpm(rdev);
1599 :
1600 0 : if (pi->voltage_control)
1601 0 : rv6xx_enable_static_voltage_control(rdev, boot_ps, false);
1602 :
1603 0 : if (pi->dynamic_pcie_gen2)
1604 0 : rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true);
1605 :
1606 0 : if (pi->gfx_clock_gating)
1607 0 : r600_gfx_clockgating_enable(rdev, true);
1608 :
1609 0 : return 0;
1610 0 : }
1611 :
1612 0 : void rv6xx_dpm_disable(struct radeon_device *rdev)
1613 : {
1614 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1615 0 : struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1616 :
1617 0 : if (!r600_dynamicpm_enabled(rdev))
1618 0 : return;
1619 :
1620 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1621 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1622 0 : rv6xx_enable_display_gap(rdev, false);
1623 0 : rv6xx_clear_vc(rdev);
1624 0 : r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1625 :
1626 0 : if (pi->thermal_protection)
1627 0 : r600_enable_thermal_protection(rdev, false);
1628 :
1629 0 : r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1630 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1631 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1632 :
1633 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1634 0 : rv6xx_enable_backbias(rdev, false);
1635 :
1636 0 : rv6xx_enable_spread_spectrum(rdev, false);
1637 :
1638 0 : if (pi->voltage_control)
1639 0 : rv6xx_enable_static_voltage_control(rdev, boot_ps, true);
1640 :
1641 0 : if (pi->dynamic_pcie_gen2)
1642 0 : rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false);
1643 :
1644 0 : if (rdev->irq.installed &&
1645 0 : r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1646 0 : rdev->irq.dpm_thermal = false;
1647 0 : radeon_irq_set(rdev);
1648 0 : }
1649 :
1650 0 : if (pi->gfx_clock_gating)
1651 0 : r600_gfx_clockgating_enable(rdev, false);
1652 :
1653 0 : r600_stop_dpm(rdev);
1654 0 : }
1655 :
1656 0 : int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
1657 : {
1658 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1659 0 : struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1660 0 : struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1661 : int ret;
1662 :
1663 0 : pi->restricted_levels = 0;
1664 :
1665 0 : rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1666 :
1667 0 : rv6xx_clear_vc(rdev);
1668 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1669 0 : r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1670 :
1671 0 : if (pi->thermal_protection)
1672 0 : r600_enable_thermal_protection(rdev, false);
1673 :
1674 0 : r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1675 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1676 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1677 :
1678 0 : rv6xx_generate_transition_stepping(rdev, new_ps, old_ps);
1679 0 : rv6xx_program_power_level_medium_for_transition(rdev);
1680 :
1681 0 : if (pi->voltage_control) {
1682 0 : rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps);
1683 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1684 0 : rv6xx_set_sw_voltage_to_low(rdev, old_ps);
1685 : }
1686 :
1687 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1688 0 : rv6xx_set_safe_backbias(rdev, new_ps, old_ps);
1689 :
1690 0 : if (pi->dynamic_pcie_gen2)
1691 0 : rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps);
1692 :
1693 0 : if (pi->voltage_control)
1694 0 : rv6xx_enable_dynamic_voltage_control(rdev, false);
1695 :
1696 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1697 0 : rv6xx_enable_dynamic_backbias_control(rdev, false);
1698 :
1699 0 : if (pi->voltage_control) {
1700 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1701 0 : rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps);
1702 0 : drm_msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1703 0 : }
1704 :
1705 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1706 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
1707 0 : r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW);
1708 :
1709 0 : rv6xx_generate_low_step(rdev, new_ps);
1710 0 : rv6xx_invalidate_intermediate_steps(rdev);
1711 0 : rv6xx_calculate_stepping_parameters(rdev, new_ps);
1712 0 : rv6xx_program_stepping_parameters_lowest_entry(rdev);
1713 0 : rv6xx_program_power_level_low_to_lowest_state(rdev);
1714 :
1715 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1716 0 : r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1717 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1718 :
1719 0 : if (pi->voltage_control) {
1720 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) {
1721 0 : ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps);
1722 0 : if (ret)
1723 0 : return ret;
1724 : }
1725 0 : rv6xx_enable_dynamic_voltage_control(rdev, true);
1726 0 : }
1727 :
1728 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1729 0 : rv6xx_enable_dynamic_backbias_control(rdev, true);
1730 :
1731 0 : if (pi->dynamic_pcie_gen2)
1732 0 : rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true);
1733 :
1734 0 : rv6xx_reset_lvtm_data_sync(rdev);
1735 :
1736 0 : rv6xx_generate_stepping_table(rdev, new_ps);
1737 0 : rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1738 0 : rv6xx_program_power_level_low(rdev);
1739 0 : rv6xx_program_power_level_medium(rdev);
1740 0 : rv6xx_program_power_level_high(rdev);
1741 0 : rv6xx_enable_medium(rdev);
1742 0 : rv6xx_enable_high(rdev);
1743 :
1744 0 : if (pi->thermal_protection)
1745 0 : rv6xx_enable_thermal_protection(rdev, true);
1746 0 : rv6xx_program_vc(rdev);
1747 0 : rv6xx_program_at(rdev);
1748 :
1749 0 : rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1750 :
1751 0 : return 0;
1752 0 : }
1753 :
1754 0 : void rv6xx_setup_asic(struct radeon_device *rdev)
1755 : {
1756 0 : r600_enable_acpi_pm(rdev);
1757 :
1758 0 : if (radeon_aspm != 0) {
1759 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
1760 0 : rv6xx_enable_l0s(rdev);
1761 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
1762 0 : rv6xx_enable_l1(rdev);
1763 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
1764 0 : rv6xx_enable_pll_sleep_in_l1(rdev);
1765 : }
1766 0 : }
1767 :
1768 0 : void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)
1769 : {
1770 0 : rv6xx_program_display_gap(rdev);
1771 0 : }
1772 :
1773 : union power_info {
1774 : struct _ATOM_POWERPLAY_INFO info;
1775 : struct _ATOM_POWERPLAY_INFO_V2 info_2;
1776 : struct _ATOM_POWERPLAY_INFO_V3 info_3;
1777 : struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1778 : struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1779 : struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1780 : };
1781 :
1782 : union pplib_clock_info {
1783 : struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1784 : struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1785 : struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1786 : struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1787 : };
1788 :
1789 : union pplib_power_state {
1790 : struct _ATOM_PPLIB_STATE v1;
1791 : struct _ATOM_PPLIB_STATE_V2 v2;
1792 : };
1793 :
1794 0 : static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
1795 : struct radeon_ps *rps,
1796 : struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
1797 : {
1798 0 : rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1799 0 : rps->class = le16_to_cpu(non_clock_info->usClassification);
1800 0 : rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1801 :
1802 0 : if (r600_is_uvd_state(rps->class, rps->class2)) {
1803 0 : rps->vclk = RV6XX_DEFAULT_VCLK_FREQ;
1804 0 : rps->dclk = RV6XX_DEFAULT_DCLK_FREQ;
1805 0 : } else {
1806 0 : rps->vclk = 0;
1807 0 : rps->dclk = 0;
1808 : }
1809 :
1810 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
1811 0 : rdev->pm.dpm.boot_ps = rps;
1812 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1813 0 : rdev->pm.dpm.uvd_ps = rps;
1814 0 : }
1815 :
1816 0 : static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev,
1817 : struct radeon_ps *rps, int index,
1818 : union pplib_clock_info *clock_info)
1819 : {
1820 0 : struct rv6xx_ps *ps = rv6xx_get_ps(rps);
1821 : u32 sclk, mclk;
1822 0 : u16 vddc;
1823 : struct rv6xx_pl *pl;
1824 :
1825 0 : switch (index) {
1826 : case 0:
1827 0 : pl = &ps->low;
1828 0 : break;
1829 : case 1:
1830 0 : pl = &ps->medium;
1831 0 : break;
1832 : case 2:
1833 : default:
1834 0 : pl = &ps->high;
1835 0 : break;
1836 : }
1837 :
1838 0 : sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
1839 0 : sclk |= clock_info->r600.ucEngineClockHigh << 16;
1840 0 : mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
1841 0 : mclk |= clock_info->r600.ucMemoryClockHigh << 16;
1842 :
1843 0 : pl->mclk = mclk;
1844 0 : pl->sclk = sclk;
1845 0 : pl->vddc = le16_to_cpu(clock_info->r600.usVDDC);
1846 0 : pl->flags = le32_to_cpu(clock_info->r600.ulFlags);
1847 :
1848 : /* patch up vddc if necessary */
1849 0 : if (pl->vddc == 0xff01) {
1850 0 : if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
1851 0 : pl->vddc = vddc;
1852 : }
1853 :
1854 : /* fix up pcie gen2 */
1855 0 : if (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) {
1856 0 : if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) {
1857 0 : if (pl->vddc < 1100)
1858 0 : pl->flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
1859 : }
1860 : }
1861 :
1862 : /* patch up boot state */
1863 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1864 0 : u16 vddc, vddci, mvdd;
1865 0 : radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
1866 0 : pl->mclk = rdev->clock.default_mclk;
1867 0 : pl->sclk = rdev->clock.default_sclk;
1868 0 : pl->vddc = vddc;
1869 0 : }
1870 0 : }
1871 :
1872 0 : static int rv6xx_parse_power_table(struct radeon_device *rdev)
1873 : {
1874 0 : struct radeon_mode_info *mode_info = &rdev->mode_info;
1875 : struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1876 : union pplib_power_state *power_state;
1877 : int i, j;
1878 : union pplib_clock_info *clock_info;
1879 : union power_info *power_info;
1880 : int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1881 0 : u16 data_offset;
1882 0 : u8 frev, crev;
1883 : struct rv6xx_ps *ps;
1884 :
1885 0 : if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1886 : &frev, &crev, &data_offset))
1887 0 : return -EINVAL;
1888 0 : power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1889 :
1890 0 : rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1891 0 : power_info->pplib.ucNumStates, GFP_KERNEL);
1892 0 : if (!rdev->pm.dpm.ps)
1893 0 : return -ENOMEM;
1894 :
1895 0 : for (i = 0; i < power_info->pplib.ucNumStates; i++) {
1896 0 : power_state = (union pplib_power_state *)
1897 0 : (mode_info->atom_context->bios + data_offset +
1898 0 : le16_to_cpu(power_info->pplib.usStateArrayOffset) +
1899 0 : i * power_info->pplib.ucStateEntrySize);
1900 0 : non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1901 0 : (mode_info->atom_context->bios + data_offset +
1902 0 : le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
1903 0 : (power_state->v1.ucNonClockStateIndex *
1904 0 : power_info->pplib.ucNonClockSize));
1905 0 : if (power_info->pplib.ucStateEntrySize - 1) {
1906 : u8 *idx;
1907 0 : ps = kzalloc(sizeof(struct rv6xx_ps), GFP_KERNEL);
1908 0 : if (ps == NULL) {
1909 0 : kfree(rdev->pm.dpm.ps);
1910 0 : return -ENOMEM;
1911 : }
1912 0 : rdev->pm.dpm.ps[i].ps_priv = ps;
1913 0 : rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1914 : non_clock_info);
1915 0 : idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
1916 0 : for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
1917 0 : clock_info = (union pplib_clock_info *)
1918 0 : (mode_info->atom_context->bios + data_offset +
1919 0 : le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
1920 0 : (idx[j] * power_info->pplib.ucClockInfoSize));
1921 0 : rv6xx_parse_pplib_clock_info(rdev,
1922 0 : &rdev->pm.dpm.ps[i], j,
1923 : clock_info);
1924 : }
1925 0 : }
1926 : }
1927 0 : rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
1928 0 : return 0;
1929 0 : }
1930 :
1931 0 : int rv6xx_dpm_init(struct radeon_device *rdev)
1932 : {
1933 0 : struct radeon_atom_ss ss;
1934 0 : struct atom_clock_dividers dividers;
1935 : struct rv6xx_power_info *pi;
1936 : int ret;
1937 :
1938 0 : pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL);
1939 0 : if (pi == NULL)
1940 0 : return -ENOMEM;
1941 0 : rdev->pm.dpm.priv = pi;
1942 :
1943 0 : ret = r600_get_platform_caps(rdev);
1944 0 : if (ret)
1945 0 : return ret;
1946 :
1947 0 : ret = rv6xx_parse_power_table(rdev);
1948 0 : if (ret)
1949 0 : return ret;
1950 :
1951 0 : if (rdev->pm.dpm.voltage_response_time == 0)
1952 0 : rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
1953 0 : if (rdev->pm.dpm.backbias_response_time == 0)
1954 0 : rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
1955 :
1956 0 : ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1957 : 0, false, ÷rs);
1958 0 : if (ret)
1959 0 : pi->spll_ref_div = dividers.ref_div + 1;
1960 : else
1961 0 : pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1962 :
1963 0 : ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
1964 : 0, false, ÷rs);
1965 0 : if (ret)
1966 0 : pi->mpll_ref_div = dividers.ref_div + 1;
1967 : else
1968 0 : pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT;
1969 :
1970 0 : if (rdev->family >= CHIP_RV670)
1971 0 : pi->fb_div_scale = 1;
1972 : else
1973 0 : pi->fb_div_scale = 0;
1974 :
1975 0 : pi->voltage_control =
1976 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
1977 :
1978 0 : pi->gfx_clock_gating = true;
1979 :
1980 0 : pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1981 : ASIC_INTERNAL_ENGINE_SS, 0);
1982 0 : pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1983 : ASIC_INTERNAL_MEMORY_SS, 0);
1984 :
1985 : /* Disable sclk ss, causes hangs on a lot of systems */
1986 0 : pi->sclk_ss = false;
1987 :
1988 0 : if (pi->sclk_ss || pi->mclk_ss)
1989 0 : pi->dynamic_ss = true;
1990 : else
1991 0 : pi->dynamic_ss = false;
1992 :
1993 0 : pi->dynamic_pcie_gen2 = true;
1994 :
1995 0 : if (pi->gfx_clock_gating &&
1996 0 : (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
1997 0 : pi->thermal_protection = true;
1998 : else
1999 0 : pi->thermal_protection = false;
2000 :
2001 0 : pi->display_gap = true;
2002 :
2003 0 : return 0;
2004 0 : }
2005 :
2006 0 : void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
2007 : struct radeon_ps *rps)
2008 : {
2009 0 : struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2010 : struct rv6xx_pl *pl;
2011 :
2012 0 : r600_dpm_print_class_info(rps->class, rps->class2);
2013 0 : r600_dpm_print_cap_info(rps->caps);
2014 0 : printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2015 0 : pl = &ps->low;
2016 0 : printk("\t\tpower level 0 sclk: %u mclk: %u vddc: %u\n",
2017 : pl->sclk, pl->mclk, pl->vddc);
2018 0 : pl = &ps->medium;
2019 0 : printk("\t\tpower level 1 sclk: %u mclk: %u vddc: %u\n",
2020 : pl->sclk, pl->mclk, pl->vddc);
2021 0 : pl = &ps->high;
2022 0 : printk("\t\tpower level 2 sclk: %u mclk: %u vddc: %u\n",
2023 : pl->sclk, pl->mclk, pl->vddc);
2024 0 : r600_dpm_print_ps_status(rdev, rps);
2025 0 : }
2026 :
2027 0 : void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2028 : struct seq_file *m)
2029 : {
2030 0 : struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2031 0 : struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2032 : struct rv6xx_pl *pl;
2033 : u32 current_index =
2034 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2035 : CURRENT_PROFILE_INDEX_SHIFT;
2036 :
2037 0 : if (current_index > 2) {
2038 0 : seq_printf(m, "invalid dpm profile %d\n", current_index);
2039 0 : } else {
2040 0 : if (current_index == 0)
2041 0 : pl = &ps->low;
2042 0 : else if (current_index == 1)
2043 0 : pl = &ps->medium;
2044 : else /* current_index == 2 */
2045 0 : pl = &ps->high;
2046 0 : seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2047 0 : seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u\n",
2048 0 : current_index, pl->sclk, pl->mclk, pl->vddc);
2049 : }
2050 0 : }
2051 :
2052 : /* get the current sclk in 10 khz units */
2053 0 : u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev)
2054 : {
2055 0 : struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2056 0 : struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2057 : struct rv6xx_pl *pl;
2058 : u32 current_index =
2059 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2060 : CURRENT_PROFILE_INDEX_SHIFT;
2061 :
2062 0 : if (current_index > 2) {
2063 0 : return 0;
2064 : } else {
2065 0 : if (current_index == 0)
2066 0 : pl = &ps->low;
2067 0 : else if (current_index == 1)
2068 0 : pl = &ps->medium;
2069 : else /* current_index == 2 */
2070 0 : pl = &ps->high;
2071 0 : return pl->sclk;
2072 : }
2073 0 : }
2074 :
2075 : /* get the current mclk in 10 khz units */
2076 0 : u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev)
2077 : {
2078 0 : struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2079 0 : struct rv6xx_ps *ps = rv6xx_get_ps(rps);
2080 : struct rv6xx_pl *pl;
2081 : u32 current_index =
2082 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
2083 : CURRENT_PROFILE_INDEX_SHIFT;
2084 :
2085 0 : if (current_index > 2) {
2086 0 : return 0;
2087 : } else {
2088 0 : if (current_index == 0)
2089 0 : pl = &ps->low;
2090 0 : else if (current_index == 1)
2091 0 : pl = &ps->medium;
2092 : else /* current_index == 2 */
2093 0 : pl = &ps->high;
2094 0 : return pl->mclk;
2095 : }
2096 0 : }
2097 :
2098 0 : void rv6xx_dpm_fini(struct radeon_device *rdev)
2099 : {
2100 : int i;
2101 :
2102 0 : for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2103 0 : kfree(rdev->pm.dpm.ps[i].ps_priv);
2104 : }
2105 0 : kfree(rdev->pm.dpm.ps);
2106 0 : kfree(rdev->pm.dpm.priv);
2107 0 : }
2108 :
2109 0 : u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
2110 : {
2111 0 : struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2112 :
2113 0 : if (low)
2114 0 : return requested_state->low.sclk;
2115 : else
2116 0 : return requested_state->high.sclk;
2117 0 : }
2118 :
2119 0 : u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
2120 : {
2121 0 : struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2122 :
2123 0 : if (low)
2124 0 : return requested_state->low.mclk;
2125 : else
2126 0 : return requested_state->high.mclk;
2127 0 : }
2128 :
2129 0 : int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
2130 : enum radeon_dpm_forced_level level)
2131 : {
2132 0 : struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
2133 :
2134 0 : if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
2135 0 : pi->restricted_levels = 3;
2136 0 : } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
2137 0 : pi->restricted_levels = 2;
2138 0 : } else {
2139 0 : pi->restricted_levels = 0;
2140 : }
2141 :
2142 0 : rv6xx_clear_vc(rdev);
2143 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
2144 0 : r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
2145 0 : r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
2146 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
2147 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
2148 0 : rv6xx_enable_medium(rdev);
2149 0 : rv6xx_enable_high(rdev);
2150 0 : if (pi->restricted_levels == 3)
2151 0 : r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
2152 0 : rv6xx_program_vc(rdev);
2153 0 : rv6xx_program_at(rdev);
2154 :
2155 0 : rdev->pm.dpm.forced_level = level;
2156 :
2157 0 : return 0;
2158 : }
|
