Line data Source code
1 : /*
2 : * Copyright 2011 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: Alex Deucher
23 : */
24 :
25 : #include <dev/pci/drm/drmP.h>
26 : #include "radeon.h"
27 : #include "rv740d.h"
28 : #include "r600_dpm.h"
29 : #include "rv770_dpm.h"
30 : #include "atom.h"
31 :
32 : struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
33 :
34 0 : u32 rv740_get_decoded_reference_divider(u32 encoded_ref)
35 : {
36 : u32 ref = 0;
37 :
38 0 : switch (encoded_ref) {
39 : case 0:
40 : ref = 1;
41 0 : break;
42 : case 16:
43 : ref = 2;
44 0 : break;
45 : case 17:
46 : ref = 3;
47 0 : break;
48 : case 18:
49 : ref = 2;
50 0 : break;
51 : case 19:
52 : ref = 3;
53 0 : break;
54 : case 20:
55 : ref = 4;
56 0 : break;
57 : case 21:
58 : ref = 5;
59 0 : break;
60 : default:
61 0 : DRM_ERROR("Invalid encoded Reference Divider\n");
62 : ref = 0;
63 0 : break;
64 : }
65 :
66 0 : return ref;
67 : }
68 :
69 : struct dll_speed_setting {
70 : u16 min;
71 : u16 max;
72 : u32 dll_speed;
73 : };
74 :
75 : static struct dll_speed_setting dll_speed_table[16] =
76 : {
77 : { 270, 320, 0x0f },
78 : { 240, 270, 0x0e },
79 : { 200, 240, 0x0d },
80 : { 180, 200, 0x0c },
81 : { 160, 180, 0x0b },
82 : { 140, 160, 0x0a },
83 : { 120, 140, 0x09 },
84 : { 110, 120, 0x08 },
85 : { 95, 110, 0x07 },
86 : { 85, 95, 0x06 },
87 : { 78, 85, 0x05 },
88 : { 70, 78, 0x04 },
89 : { 65, 70, 0x03 },
90 : { 60, 65, 0x02 },
91 : { 42, 60, 0x01 },
92 : { 00, 42, 0x00 }
93 : };
94 :
95 0 : u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock)
96 : {
97 : int i;
98 : u32 factor;
99 : u16 data_rate;
100 :
101 0 : if (is_gddr5)
102 0 : factor = 4;
103 : else
104 : factor = 2;
105 :
106 0 : data_rate = (u16)(memory_clock * factor / 1000);
107 :
108 0 : if (data_rate < dll_speed_table[0].max) {
109 0 : for (i = 0; i < 16; i++) {
110 0 : if (data_rate > dll_speed_table[i].min &&
111 0 : data_rate <= dll_speed_table[i].max)
112 0 : return dll_speed_table[i].dll_speed;
113 : }
114 : }
115 :
116 : DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n");
117 :
118 0 : return 0x0f;
119 0 : }
120 :
121 0 : int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
122 : RV770_SMC_SCLK_VALUE *sclk)
123 : {
124 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
125 0 : struct atom_clock_dividers dividers;
126 0 : u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
127 0 : u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
128 0 : u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
129 0 : u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum;
130 0 : u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2;
131 : u64 tmp;
132 0 : u32 reference_clock = rdev->clock.spll.reference_freq;
133 : u32 reference_divider;
134 : u32 fbdiv;
135 : int ret;
136 :
137 0 : ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
138 : engine_clock, false, ÷rs);
139 0 : if (ret)
140 0 : return ret;
141 :
142 0 : reference_divider = 1 + dividers.ref_div;
143 :
144 0 : tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
145 0 : do_div(tmp, reference_clock);
146 0 : fbdiv = (u32) tmp;
147 :
148 0 : spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
149 0 : spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
150 0 : spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
151 :
152 0 : spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
153 0 : spll_func_cntl_2 |= SCLK_MUX_SEL(2);
154 :
155 0 : spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
156 0 : spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
157 0 : spll_func_cntl_3 |= SPLL_DITHEN;
158 :
159 0 : if (pi->sclk_ss) {
160 0 : struct radeon_atom_ss ss;
161 0 : u32 vco_freq = engine_clock * dividers.post_div;
162 :
163 0 : if (radeon_atombios_get_asic_ss_info(rdev, &ss,
164 : ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
165 0 : u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
166 0 : u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
167 :
168 0 : cg_spll_spread_spectrum &= ~CLK_S_MASK;
169 0 : cg_spll_spread_spectrum |= CLK_S(clk_s);
170 0 : cg_spll_spread_spectrum |= SSEN;
171 :
172 0 : cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
173 0 : cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
174 0 : }
175 0 : }
176 :
177 0 : sclk->sclk_value = cpu_to_be32(engine_clock);
178 0 : sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
179 0 : sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
180 0 : sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
181 0 : sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
182 0 : sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
183 :
184 0 : return 0;
185 0 : }
186 :
187 0 : int rv740_populate_mclk_value(struct radeon_device *rdev,
188 : u32 engine_clock, u32 memory_clock,
189 : RV7XX_SMC_MCLK_VALUE *mclk)
190 : {
191 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
192 0 : u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;
193 0 : u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;
194 0 : u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;
195 0 : u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;
196 0 : u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;
197 0 : u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;
198 0 : u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
199 0 : u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;
200 0 : struct atom_clock_dividers dividers;
201 : u32 ibias;
202 : u32 dll_speed;
203 : int ret;
204 :
205 0 : ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
206 : memory_clock, false, ÷rs);
207 0 : if (ret)
208 0 : return ret;
209 :
210 0 : ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
211 :
212 0 : mpll_ad_func_cntl &= ~(CLKR_MASK |
213 : YCLK_POST_DIV_MASK |
214 : CLKF_MASK |
215 : CLKFRAC_MASK |
216 : IBIAS_MASK);
217 0 : mpll_ad_func_cntl |= CLKR(dividers.ref_div);
218 0 : mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
219 0 : mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
220 0 : mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
221 0 : mpll_ad_func_cntl |= IBIAS(ibias);
222 :
223 0 : if (dividers.vco_mode)
224 0 : mpll_ad_func_cntl_2 |= VCO_MODE;
225 : else
226 0 : mpll_ad_func_cntl_2 &= ~VCO_MODE;
227 :
228 0 : if (pi->mem_gddr5) {
229 0 : mpll_dq_func_cntl &= ~(CLKR_MASK |
230 : YCLK_POST_DIV_MASK |
231 : CLKF_MASK |
232 : CLKFRAC_MASK |
233 : IBIAS_MASK);
234 0 : mpll_dq_func_cntl |= CLKR(dividers.ref_div);
235 0 : mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
236 0 : mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
237 0 : mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
238 0 : mpll_dq_func_cntl |= IBIAS(ibias);
239 :
240 0 : if (dividers.vco_mode)
241 0 : mpll_dq_func_cntl_2 |= VCO_MODE;
242 : else
243 0 : mpll_dq_func_cntl_2 &= ~VCO_MODE;
244 : }
245 :
246 0 : if (pi->mclk_ss) {
247 0 : struct radeon_atom_ss ss;
248 0 : u32 vco_freq = memory_clock * dividers.post_div;
249 :
250 0 : if (radeon_atombios_get_asic_ss_info(rdev, &ss,
251 : ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
252 0 : u32 reference_clock = rdev->clock.mpll.reference_freq;
253 0 : u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
254 0 : u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
255 0 : u32 clk_v = 0x40000 * ss.percentage *
256 0 : (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);
257 :
258 0 : mpll_ss1 &= ~CLKV_MASK;
259 0 : mpll_ss1 |= CLKV(clk_v);
260 :
261 0 : mpll_ss2 &= ~CLKS_MASK;
262 0 : mpll_ss2 |= CLKS(clk_s);
263 0 : }
264 0 : }
265 :
266 0 : dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
267 : memory_clock);
268 :
269 0 : mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
270 0 : mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
271 :
272 0 : mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
273 0 : mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
274 0 : mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
275 0 : mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
276 0 : mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
277 0 : mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
278 0 : mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
279 0 : mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
280 0 : mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
281 :
282 0 : return 0;
283 0 : }
284 :
285 0 : void rv740_read_clock_registers(struct radeon_device *rdev)
286 : {
287 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
288 :
289 0 : pi->clk_regs.rv770.cg_spll_func_cntl =
290 0 : RREG32(CG_SPLL_FUNC_CNTL);
291 0 : pi->clk_regs.rv770.cg_spll_func_cntl_2 =
292 0 : RREG32(CG_SPLL_FUNC_CNTL_2);
293 0 : pi->clk_regs.rv770.cg_spll_func_cntl_3 =
294 0 : RREG32(CG_SPLL_FUNC_CNTL_3);
295 0 : pi->clk_regs.rv770.cg_spll_spread_spectrum =
296 0 : RREG32(CG_SPLL_SPREAD_SPECTRUM);
297 0 : pi->clk_regs.rv770.cg_spll_spread_spectrum_2 =
298 0 : RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
299 :
300 0 : pi->clk_regs.rv770.mpll_ad_func_cntl =
301 0 : RREG32(MPLL_AD_FUNC_CNTL);
302 0 : pi->clk_regs.rv770.mpll_ad_func_cntl_2 =
303 0 : RREG32(MPLL_AD_FUNC_CNTL_2);
304 0 : pi->clk_regs.rv770.mpll_dq_func_cntl =
305 0 : RREG32(MPLL_DQ_FUNC_CNTL);
306 0 : pi->clk_regs.rv770.mpll_dq_func_cntl_2 =
307 0 : RREG32(MPLL_DQ_FUNC_CNTL_2);
308 0 : pi->clk_regs.rv770.mclk_pwrmgt_cntl =
309 0 : RREG32(MCLK_PWRMGT_CNTL);
310 0 : pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
311 0 : pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);
312 0 : pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2);
313 0 : }
314 :
315 0 : int rv740_populate_smc_acpi_state(struct radeon_device *rdev,
316 : RV770_SMC_STATETABLE *table)
317 : {
318 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
319 0 : u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;
320 0 : u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;
321 0 : u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;
322 0 : u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;
323 0 : u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;
324 0 : u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;
325 0 : u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;
326 0 : u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;
327 0 : u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;
328 :
329 0 : table->ACPIState = table->initialState;
330 :
331 0 : table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
332 :
333 0 : if (pi->acpi_vddc) {
334 0 : rv770_populate_vddc_value(rdev, pi->acpi_vddc,
335 0 : &table->ACPIState.levels[0].vddc);
336 0 : table->ACPIState.levels[0].gen2PCIE =
337 0 : pi->pcie_gen2 ?
338 0 : pi->acpi_pcie_gen2 : 0;
339 0 : table->ACPIState.levels[0].gen2XSP =
340 0 : pi->acpi_pcie_gen2;
341 0 : } else {
342 0 : rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
343 0 : &table->ACPIState.levels[0].vddc);
344 0 : table->ACPIState.levels[0].gen2PCIE = 0;
345 : }
346 :
347 0 : mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
348 :
349 0 : mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN;
350 :
351 0 : mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
352 : MRDCKA1_RESET |
353 : MRDCKB0_RESET |
354 : MRDCKB1_RESET |
355 : MRDCKC0_RESET |
356 : MRDCKC1_RESET |
357 : MRDCKD0_RESET |
358 : MRDCKD1_RESET);
359 :
360 0 : dll_cntl |= (MRDCKA0_BYPASS |
361 : MRDCKA1_BYPASS |
362 : MRDCKB0_BYPASS |
363 : MRDCKB1_BYPASS |
364 : MRDCKC0_BYPASS |
365 : MRDCKC1_BYPASS |
366 : MRDCKD0_BYPASS |
367 : MRDCKD1_BYPASS);
368 :
369 0 : spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
370 :
371 0 : spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
372 0 : spll_func_cntl_2 |= SCLK_MUX_SEL(4);
373 :
374 0 : table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
375 0 : table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
376 0 : table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
377 0 : table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
378 0 : table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
379 0 : table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
380 :
381 0 : table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
382 :
383 0 : table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
384 0 : table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
385 0 : table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
386 :
387 0 : table->ACPIState.levels[0].sclk.sclk_value = 0;
388 :
389 0 : table->ACPIState.levels[1] = table->ACPIState.levels[0];
390 0 : table->ACPIState.levels[2] = table->ACPIState.levels[0];
391 :
392 0 : rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
393 :
394 0 : return 0;
395 : }
396 :
397 0 : void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev,
398 : bool enable)
399 : {
400 0 : if (enable)
401 0 : WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
402 : else
403 0 : WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
404 0 : }
405 :
406 0 : u8 rv740_get_mclk_frequency_ratio(u32 memory_clock)
407 : {
408 : u8 mc_para_index;
409 :
410 0 : if ((memory_clock < 10000) || (memory_clock > 47500))
411 0 : mc_para_index = 0x00;
412 : else
413 0 : mc_para_index = (u8)((memory_clock - 10000) / 2500);
414 :
415 0 : return mc_para_index;
416 : }
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