Line data Source code
1 : /*
2 : * Copyright 2013 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <dev/pci/drm/drmP.h>
25 : #include "radeon.h"
26 : #include "radeon_asic.h"
27 : #include "sid.h"
28 : #include "r600_dpm.h"
29 : #include "si_dpm.h"
30 : #include "atom.h"
31 :
32 : #define MC_CG_ARB_FREQ_F0 0x0a
33 : #define MC_CG_ARB_FREQ_F1 0x0b
34 : #define MC_CG_ARB_FREQ_F2 0x0c
35 : #define MC_CG_ARB_FREQ_F3 0x0d
36 :
37 : #define SMC_RAM_END 0x20000
38 :
39 : #define SCLK_MIN_DEEPSLEEP_FREQ 1350
40 :
41 : static const struct si_cac_config_reg cac_weights_tahiti[] =
42 : {
43 : { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
44 : { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
45 : { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
46 : { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
47 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
48 : { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
49 : { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
50 : { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
51 : { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
52 : { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
53 : { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
54 : { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
55 : { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
56 : { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
57 : { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
58 : { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
59 : { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
60 : { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
61 : { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
62 : { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
63 : { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
64 : { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
65 : { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
66 : { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
67 : { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
68 : { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
69 : { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
70 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
71 : { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
72 : { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
73 : { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
74 : { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
75 : { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
76 : { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
77 : { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
78 : { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
79 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
80 : { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
81 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
82 : { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
83 : { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
84 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
85 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
86 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
87 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
88 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
89 : { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
90 : { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
91 : { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
92 : { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
93 : { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
94 : { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
95 : { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
96 : { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
97 : { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
98 : { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
99 : { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
100 : { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
101 : { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
102 : { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
103 : { 0xFFFFFFFF }
104 : };
105 :
106 : static const struct si_cac_config_reg lcac_tahiti[] =
107 : {
108 : { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
109 : { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
110 : { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
111 : { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
112 : { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
113 : { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
114 : { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
115 : { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
116 : { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
117 : { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
118 : { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
119 : { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
120 : { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
121 : { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
122 : { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
123 : { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
124 : { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
125 : { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
126 : { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
127 : { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
128 : { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
129 : { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
130 : { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
131 : { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
132 : { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
133 : { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
134 : { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
135 : { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
136 : { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
137 : { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
138 : { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
139 : { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
140 : { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
141 : { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
142 : { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
143 : { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
144 : { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
145 : { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
146 : { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
147 : { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
148 : { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
149 : { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
150 : { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
151 : { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
152 : { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
153 : { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
154 : { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
155 : { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
156 : { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
157 : { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
158 : { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
159 : { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
160 : { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
161 : { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
162 : { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
163 : { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
164 : { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
165 : { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
166 : { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
167 : { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
168 : { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
169 : { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
170 : { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
171 : { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
172 : { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
173 : { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
174 : { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
175 : { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
176 : { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
177 : { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
178 : { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
179 : { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
180 : { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
181 : { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
182 : { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
183 : { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
184 : { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
185 : { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
186 : { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
187 : { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
188 : { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
189 : { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
190 : { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
191 : { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
192 : { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
193 : { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
194 : { 0xFFFFFFFF }
195 :
196 : };
197 :
198 : static const struct si_cac_config_reg cac_override_tahiti[] =
199 : {
200 : { 0xFFFFFFFF }
201 : };
202 :
203 : static const struct si_powertune_data powertune_data_tahiti =
204 : {
205 : ((1 << 16) | 27027),
206 : 6,
207 : 0,
208 : 4,
209 : 95,
210 : {
211 : 0UL,
212 : 0UL,
213 : 4521550UL,
214 : 309631529UL,
215 : -1270850L,
216 : 4513710L,
217 : 40
218 : },
219 : 595000000UL,
220 : 12,
221 : {
222 : 0,
223 : 0,
224 : 0,
225 : 0,
226 : 0,
227 : 0,
228 : 0,
229 : 0
230 : },
231 : true
232 : };
233 :
234 : static const struct si_dte_data dte_data_tahiti =
235 : {
236 : { 1159409, 0, 0, 0, 0 },
237 : { 777, 0, 0, 0, 0 },
238 : 2,
239 : 54000,
240 : 127000,
241 : 25,
242 : 2,
243 : 10,
244 : 13,
245 : { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
246 : { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
247 : { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
248 : 85,
249 : false
250 : };
251 :
252 : static const struct si_dte_data dte_data_tahiti_le =
253 : {
254 : { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
255 : { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
256 : 0x5,
257 : 0xAFC8,
258 : 0x64,
259 : 0x32,
260 : 1,
261 : 0,
262 : 0x10,
263 : { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
264 : { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
265 : { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
266 : 85,
267 : true
268 : };
269 :
270 : static const struct si_dte_data dte_data_tahiti_pro =
271 : {
272 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
273 : { 0x0, 0x0, 0x0, 0x0, 0x0 },
274 : 5,
275 : 45000,
276 : 100,
277 : 0xA,
278 : 1,
279 : 0,
280 : 0x10,
281 : { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
282 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
283 : { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
284 : 90,
285 : true
286 : };
287 :
288 : static const struct si_dte_data dte_data_new_zealand =
289 : {
290 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
291 : { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
292 : 0x5,
293 : 0xAFC8,
294 : 0x69,
295 : 0x32,
296 : 1,
297 : 0,
298 : 0x10,
299 : { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
300 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
301 : { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
302 : 85,
303 : true
304 : };
305 :
306 : static const struct si_dte_data dte_data_aruba_pro =
307 : {
308 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
309 : { 0x0, 0x0, 0x0, 0x0, 0x0 },
310 : 5,
311 : 45000,
312 : 100,
313 : 0xA,
314 : 1,
315 : 0,
316 : 0x10,
317 : { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
318 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
319 : { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
320 : 90,
321 : true
322 : };
323 :
324 : static const struct si_dte_data dte_data_malta =
325 : {
326 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
327 : { 0x0, 0x0, 0x0, 0x0, 0x0 },
328 : 5,
329 : 45000,
330 : 100,
331 : 0xA,
332 : 1,
333 : 0,
334 : 0x10,
335 : { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
336 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
337 : { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
338 : 90,
339 : true
340 : };
341 :
342 : struct si_cac_config_reg cac_weights_pitcairn[] =
343 : {
344 : { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
345 : { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
346 : { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
347 : { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
348 : { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
349 : { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
350 : { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
351 : { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
352 : { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
353 : { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
354 : { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
355 : { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
356 : { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
357 : { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
358 : { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
359 : { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
360 : { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
361 : { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
362 : { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
363 : { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
364 : { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
365 : { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
366 : { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
367 : { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
368 : { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
369 : { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
370 : { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
371 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
372 : { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
373 : { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
374 : { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
375 : { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
376 : { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
377 : { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
378 : { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
379 : { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
380 : { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
381 : { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
382 : { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
383 : { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
384 : { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
385 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
386 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
387 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
388 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
389 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
390 : { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
391 : { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
392 : { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
393 : { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
394 : { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
395 : { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
396 : { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
397 : { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
398 : { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
399 : { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
400 : { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
401 : { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
402 : { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
403 : { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
404 : { 0xFFFFFFFF }
405 : };
406 :
407 : static const struct si_cac_config_reg lcac_pitcairn[] =
408 : {
409 : { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
410 : { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
411 : { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
412 : { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
413 : { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
414 : { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
415 : { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
416 : { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
417 : { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
418 : { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
419 : { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
420 : { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
421 : { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
422 : { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
423 : { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
424 : { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
425 : { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
426 : { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
427 : { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
428 : { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
429 : { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
430 : { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
431 : { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
432 : { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
433 : { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
434 : { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
435 : { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
436 : { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
437 : { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
438 : { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
439 : { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
440 : { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
441 : { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
442 : { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
443 : { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
444 : { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
445 : { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
446 : { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
447 : { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
448 : { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
449 : { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
450 : { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
451 : { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
452 : { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
453 : { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
454 : { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
455 : { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
456 : { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
457 : { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
458 : { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
459 : { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
460 : { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
461 : { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
462 : { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
463 : { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
464 : { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
465 : { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
466 : { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
467 : { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
468 : { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
469 : { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
470 : { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
471 : { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
472 : { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
473 : { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
474 : { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
475 : { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
476 : { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
477 : { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
478 : { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
479 : { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
480 : { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
481 : { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
482 : { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
483 : { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
484 : { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
485 : { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
486 : { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
487 : { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
488 : { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
489 : { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
490 : { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
491 : { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
492 : { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
493 : { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
494 : { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
495 : { 0xFFFFFFFF }
496 : };
497 :
498 : static const struct si_cac_config_reg cac_override_pitcairn[] =
499 : {
500 : { 0xFFFFFFFF }
501 : };
502 :
503 : static const struct si_powertune_data powertune_data_pitcairn =
504 : {
505 : ((1 << 16) | 27027),
506 : 5,
507 : 0,
508 : 6,
509 : 100,
510 : {
511 : 51600000UL,
512 : 1800000UL,
513 : 7194395UL,
514 : 309631529UL,
515 : -1270850L,
516 : 4513710L,
517 : 100
518 : },
519 : 117830498UL,
520 : 12,
521 : {
522 : 0,
523 : 0,
524 : 0,
525 : 0,
526 : 0,
527 : 0,
528 : 0,
529 : 0
530 : },
531 : true
532 : };
533 :
534 : static const struct si_dte_data dte_data_pitcairn =
535 : {
536 : { 0, 0, 0, 0, 0 },
537 : { 0, 0, 0, 0, 0 },
538 : 0,
539 : 0,
540 : 0,
541 : 0,
542 : 0,
543 : 0,
544 : 0,
545 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
546 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
547 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
548 : 0,
549 : false
550 : };
551 :
552 : static const struct si_dte_data dte_data_curacao_xt =
553 : {
554 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
555 : { 0x0, 0x0, 0x0, 0x0, 0x0 },
556 : 5,
557 : 45000,
558 : 100,
559 : 0xA,
560 : 1,
561 : 0,
562 : 0x10,
563 : { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
564 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
565 : { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
566 : 90,
567 : true
568 : };
569 :
570 : static const struct si_dte_data dte_data_curacao_pro =
571 : {
572 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
573 : { 0x0, 0x0, 0x0, 0x0, 0x0 },
574 : 5,
575 : 45000,
576 : 100,
577 : 0xA,
578 : 1,
579 : 0,
580 : 0x10,
581 : { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
582 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
583 : { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
584 : 90,
585 : true
586 : };
587 :
588 : static const struct si_dte_data dte_data_neptune_xt =
589 : {
590 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
591 : { 0x0, 0x0, 0x0, 0x0, 0x0 },
592 : 5,
593 : 45000,
594 : 100,
595 : 0xA,
596 : 1,
597 : 0,
598 : 0x10,
599 : { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
600 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
601 : { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
602 : 90,
603 : true
604 : };
605 :
606 : static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
607 : {
608 : { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
609 : { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
610 : { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
611 : { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
612 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
613 : { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
614 : { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
615 : { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
616 : { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
617 : { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
618 : { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
619 : { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
620 : { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
621 : { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
622 : { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
623 : { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
624 : { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
625 : { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
626 : { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
627 : { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
628 : { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
629 : { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
630 : { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
631 : { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
632 : { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
633 : { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
634 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
635 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
636 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
637 : { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
638 : { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
639 : { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
640 : { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
641 : { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
642 : { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
643 : { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
644 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
645 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
646 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
647 : { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
648 : { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
649 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
650 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
651 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
652 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
653 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
654 : { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
655 : { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
656 : { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
657 : { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
658 : { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
659 : { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
660 : { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
661 : { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
662 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
663 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
664 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
665 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
666 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
667 : { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
668 : { 0xFFFFFFFF }
669 : };
670 :
671 : static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
672 : {
673 : { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
674 : { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
675 : { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
676 : { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
677 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
678 : { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
679 : { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
680 : { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
681 : { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
682 : { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
683 : { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
684 : { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
685 : { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
686 : { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
687 : { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
688 : { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
689 : { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
690 : { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
691 : { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
692 : { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
693 : { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
694 : { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
695 : { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
696 : { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
697 : { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
698 : { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
699 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
700 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
701 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
702 : { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
703 : { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
704 : { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
705 : { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
706 : { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
707 : { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
708 : { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
709 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
710 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
711 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
712 : { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
713 : { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
714 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
715 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
716 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
717 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
718 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
719 : { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
720 : { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
721 : { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
722 : { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
723 : { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
724 : { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
725 : { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
726 : { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
727 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
728 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
729 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
730 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
731 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
732 : { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
733 : { 0xFFFFFFFF }
734 : };
735 :
736 : static const struct si_cac_config_reg cac_weights_heathrow[] =
737 : {
738 : { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
739 : { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
740 : { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
741 : { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
742 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
743 : { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
744 : { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
745 : { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
746 : { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
747 : { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
748 : { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
749 : { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
750 : { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
751 : { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
752 : { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
753 : { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
754 : { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
755 : { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
756 : { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
757 : { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
758 : { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
759 : { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
760 : { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
761 : { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
762 : { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
763 : { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
764 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
765 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
766 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
767 : { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
768 : { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
769 : { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
770 : { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
771 : { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
772 : { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
773 : { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
774 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
775 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
776 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
777 : { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
778 : { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
779 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
780 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
781 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
782 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
783 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
784 : { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
785 : { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
786 : { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
787 : { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
788 : { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
789 : { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
790 : { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
791 : { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
792 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
793 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
794 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
795 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
796 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
797 : { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
798 : { 0xFFFFFFFF }
799 : };
800 :
801 : static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
802 : {
803 : { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
804 : { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
805 : { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
806 : { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
807 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
808 : { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
809 : { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
810 : { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
811 : { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
812 : { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
813 : { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
814 : { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
815 : { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
816 : { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
817 : { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
818 : { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
819 : { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
820 : { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
821 : { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
822 : { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
823 : { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
824 : { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
825 : { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
826 : { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
827 : { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
828 : { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
829 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
830 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
831 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
832 : { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
833 : { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
834 : { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
835 : { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
836 : { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
837 : { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
838 : { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
839 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
840 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
841 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
842 : { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
843 : { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
844 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
845 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
846 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
847 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
848 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
849 : { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
850 : { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
851 : { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
852 : { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
853 : { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
854 : { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
855 : { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
856 : { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
857 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
858 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
859 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
860 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
861 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
862 : { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
863 : { 0xFFFFFFFF }
864 : };
865 :
866 : static const struct si_cac_config_reg cac_weights_cape_verde[] =
867 : {
868 : { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
869 : { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
870 : { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
871 : { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
872 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 : { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
874 : { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
875 : { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
876 : { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
877 : { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
878 : { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
879 : { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
880 : { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
881 : { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
882 : { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
883 : { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
884 : { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
885 : { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
886 : { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
887 : { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
888 : { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
889 : { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
890 : { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
891 : { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
892 : { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
893 : { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
894 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
895 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
896 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
897 : { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
898 : { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
899 : { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
900 : { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
901 : { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
902 : { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
903 : { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
904 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
905 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
906 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
907 : { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
908 : { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
909 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
910 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
911 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
912 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
913 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
914 : { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
915 : { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
916 : { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
917 : { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
918 : { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
919 : { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
920 : { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
921 : { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
922 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
923 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
924 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
925 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
926 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
927 : { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
928 : { 0xFFFFFFFF }
929 : };
930 :
931 : static const struct si_cac_config_reg lcac_cape_verde[] =
932 : {
933 : { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
934 : { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
935 : { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
936 : { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
937 : { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
938 : { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
939 : { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
940 : { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
941 : { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
942 : { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
943 : { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
944 : { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
945 : { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
946 : { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
947 : { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
948 : { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
949 : { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
950 : { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
951 : { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
952 : { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
953 : { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
954 : { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
955 : { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
956 : { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
957 : { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
958 : { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
959 : { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
960 : { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
961 : { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
962 : { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
963 : { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
964 : { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
965 : { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
966 : { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
967 : { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
968 : { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
969 : { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
970 : { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
971 : { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
972 : { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
973 : { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
974 : { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
975 : { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
976 : { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
977 : { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
978 : { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
979 : { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
980 : { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
981 : { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
982 : { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
983 : { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
984 : { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
985 : { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
986 : { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
987 : { 0xFFFFFFFF }
988 : };
989 :
990 : static const struct si_cac_config_reg cac_override_cape_verde[] =
991 : {
992 : { 0xFFFFFFFF }
993 : };
994 :
995 : static const struct si_powertune_data powertune_data_cape_verde =
996 : {
997 : ((1 << 16) | 0x6993),
998 : 5,
999 : 0,
1000 : 7,
1001 : 105,
1002 : {
1003 : 0UL,
1004 : 0UL,
1005 : 7194395UL,
1006 : 309631529UL,
1007 : -1270850L,
1008 : 4513710L,
1009 : 100
1010 : },
1011 : 117830498UL,
1012 : 12,
1013 : {
1014 : 0,
1015 : 0,
1016 : 0,
1017 : 0,
1018 : 0,
1019 : 0,
1020 : 0,
1021 : 0
1022 : },
1023 : true
1024 : };
1025 :
1026 : static const struct si_dte_data dte_data_cape_verde =
1027 : {
1028 : { 0, 0, 0, 0, 0 },
1029 : { 0, 0, 0, 0, 0 },
1030 : 0,
1031 : 0,
1032 : 0,
1033 : 0,
1034 : 0,
1035 : 0,
1036 : 0,
1037 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1038 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1039 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1040 : 0,
1041 : false
1042 : };
1043 :
1044 : static const struct si_dte_data dte_data_venus_xtx =
1045 : {
1046 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1047 : { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1048 : 5,
1049 : 55000,
1050 : 0x69,
1051 : 0xA,
1052 : 1,
1053 : 0,
1054 : 0x3,
1055 : { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1056 : { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1057 : { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1058 : 90,
1059 : true
1060 : };
1061 :
1062 : static const struct si_dte_data dte_data_venus_xt =
1063 : {
1064 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1065 : { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1066 : 5,
1067 : 55000,
1068 : 0x69,
1069 : 0xA,
1070 : 1,
1071 : 0,
1072 : 0x3,
1073 : { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1074 : { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1075 : { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1076 : 90,
1077 : true
1078 : };
1079 :
1080 : static const struct si_dte_data dte_data_venus_pro =
1081 : {
1082 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1083 : { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1084 : 5,
1085 : 55000,
1086 : 0x69,
1087 : 0xA,
1088 : 1,
1089 : 0,
1090 : 0x3,
1091 : { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1092 : { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1093 : { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1094 : 90,
1095 : true
1096 : };
1097 :
1098 : struct si_cac_config_reg cac_weights_oland[] =
1099 : {
1100 : { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1101 : { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1102 : { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1103 : { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1104 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1105 : { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1106 : { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1107 : { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1108 : { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1109 : { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1110 : { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1111 : { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1112 : { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1113 : { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1114 : { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1115 : { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1116 : { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1117 : { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1118 : { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1119 : { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1120 : { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1121 : { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1122 : { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1123 : { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1124 : { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1125 : { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1126 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1127 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1128 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1129 : { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1130 : { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1131 : { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1132 : { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1133 : { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1134 : { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1135 : { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1136 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1137 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1138 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1139 : { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1140 : { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1141 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1142 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1143 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1144 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1146 : { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1147 : { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1148 : { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1149 : { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1150 : { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1151 : { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1152 : { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1153 : { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1154 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1155 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1156 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1157 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1158 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1159 : { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1160 : { 0xFFFFFFFF }
1161 : };
1162 :
1163 : static const struct si_cac_config_reg cac_weights_mars_pro[] =
1164 : {
1165 : { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1166 : { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1167 : { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1168 : { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1169 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1170 : { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1171 : { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1172 : { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1173 : { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1174 : { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1175 : { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1176 : { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1177 : { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1178 : { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1179 : { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1180 : { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1181 : { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1182 : { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1183 : { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1184 : { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1185 : { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1186 : { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1187 : { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1188 : { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1189 : { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1190 : { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1191 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1192 : { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1193 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1194 : { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1195 : { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1196 : { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1197 : { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1198 : { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1199 : { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1200 : { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1201 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1202 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1203 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1204 : { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1205 : { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1206 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1207 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1208 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1209 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1211 : { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1212 : { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1213 : { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1214 : { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1215 : { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1216 : { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1217 : { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1218 : { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1219 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1220 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1221 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1222 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1223 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1224 : { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1225 : { 0xFFFFFFFF }
1226 : };
1227 :
1228 : static const struct si_cac_config_reg cac_weights_mars_xt[] =
1229 : {
1230 : { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1231 : { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1232 : { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1233 : { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1234 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 : { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1236 : { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1237 : { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1238 : { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1239 : { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1240 : { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1241 : { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1242 : { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1243 : { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1244 : { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1245 : { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1246 : { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1247 : { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1248 : { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1249 : { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1250 : { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1251 : { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1252 : { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1253 : { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1254 : { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1255 : { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1256 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1257 : { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1258 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1259 : { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1260 : { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1261 : { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1262 : { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1263 : { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1264 : { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1265 : { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1266 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1267 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1268 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1269 : { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1270 : { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1271 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1272 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1273 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1274 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1276 : { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1277 : { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1278 : { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1279 : { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1280 : { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1281 : { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1282 : { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1283 : { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1284 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1285 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1286 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1287 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1288 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1289 : { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1290 : { 0xFFFFFFFF }
1291 : };
1292 :
1293 : static const struct si_cac_config_reg cac_weights_oland_pro[] =
1294 : {
1295 : { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1296 : { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1297 : { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1298 : { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1299 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 : { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1301 : { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1302 : { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1303 : { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1304 : { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1305 : { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1306 : { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1307 : { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1308 : { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1309 : { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1310 : { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1311 : { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1312 : { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1313 : { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1314 : { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1315 : { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1316 : { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1317 : { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1318 : { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1319 : { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1320 : { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1321 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1322 : { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1323 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1324 : { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1325 : { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1326 : { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1327 : { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1328 : { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1329 : { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1330 : { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1331 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1332 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1333 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1334 : { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1335 : { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1336 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1337 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1338 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1339 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1341 : { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1342 : { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1343 : { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1344 : { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1345 : { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1346 : { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1347 : { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1348 : { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1349 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1350 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1351 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1352 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1353 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1354 : { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1355 : { 0xFFFFFFFF }
1356 : };
1357 :
1358 : static const struct si_cac_config_reg cac_weights_oland_xt[] =
1359 : {
1360 : { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1361 : { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1362 : { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1363 : { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1364 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 : { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1366 : { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1367 : { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1368 : { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1369 : { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1370 : { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1371 : { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1372 : { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1373 : { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1374 : { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1375 : { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1376 : { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1377 : { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1378 : { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1379 : { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1380 : { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1381 : { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1382 : { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1383 : { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1384 : { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1385 : { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1386 : { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1387 : { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1388 : { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1389 : { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1390 : { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1391 : { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1392 : { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1393 : { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1394 : { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1395 : { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1396 : { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1397 : { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1398 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1399 : { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1400 : { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1401 : { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1402 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1403 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1404 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1406 : { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1407 : { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1408 : { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1409 : { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1410 : { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1411 : { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1412 : { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1413 : { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1414 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1415 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1416 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1417 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1418 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1419 : { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1420 : { 0xFFFFFFFF }
1421 : };
1422 :
1423 : static const struct si_cac_config_reg lcac_oland[] =
1424 : {
1425 : { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1426 : { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1427 : { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1428 : { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1429 : { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1430 : { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1431 : { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1432 : { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1433 : { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1434 : { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1435 : { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1436 : { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1437 : { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1438 : { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1439 : { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1440 : { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1441 : { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1442 : { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1443 : { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1444 : { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1445 : { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1446 : { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1447 : { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1448 : { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1449 : { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1450 : { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1451 : { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1452 : { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1453 : { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1454 : { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1455 : { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1456 : { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1457 : { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1458 : { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1459 : { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1460 : { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1461 : { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1462 : { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1463 : { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1464 : { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1465 : { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1466 : { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467 : { 0xFFFFFFFF }
1468 : };
1469 :
1470 : static const struct si_cac_config_reg lcac_mars_pro[] =
1471 : {
1472 : { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1473 : { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1474 : { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1475 : { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1476 : { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1477 : { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1478 : { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1479 : { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1480 : { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1481 : { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 : { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1483 : { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1484 : { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1485 : { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1486 : { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1487 : { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1488 : { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1489 : { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1490 : { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1491 : { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1492 : { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1493 : { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1494 : { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1495 : { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1496 : { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1497 : { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1498 : { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1499 : { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1500 : { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1501 : { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1502 : { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1503 : { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1504 : { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1505 : { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1506 : { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1507 : { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1508 : { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1509 : { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1510 : { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1511 : { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1512 : { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1513 : { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1514 : { 0xFFFFFFFF }
1515 : };
1516 :
1517 : static const struct si_cac_config_reg cac_override_oland[] =
1518 : {
1519 : { 0xFFFFFFFF }
1520 : };
1521 :
1522 : static const struct si_powertune_data powertune_data_oland =
1523 : {
1524 : ((1 << 16) | 0x6993),
1525 : 5,
1526 : 0,
1527 : 7,
1528 : 105,
1529 : {
1530 : 0UL,
1531 : 0UL,
1532 : 7194395UL,
1533 : 309631529UL,
1534 : -1270850L,
1535 : 4513710L,
1536 : 100
1537 : },
1538 : 117830498UL,
1539 : 12,
1540 : {
1541 : 0,
1542 : 0,
1543 : 0,
1544 : 0,
1545 : 0,
1546 : 0,
1547 : 0,
1548 : 0
1549 : },
1550 : true
1551 : };
1552 :
1553 : static const struct si_powertune_data powertune_data_mars_pro =
1554 : {
1555 : ((1 << 16) | 0x6993),
1556 : 5,
1557 : 0,
1558 : 7,
1559 : 105,
1560 : {
1561 : 0UL,
1562 : 0UL,
1563 : 7194395UL,
1564 : 309631529UL,
1565 : -1270850L,
1566 : 4513710L,
1567 : 100
1568 : },
1569 : 117830498UL,
1570 : 12,
1571 : {
1572 : 0,
1573 : 0,
1574 : 0,
1575 : 0,
1576 : 0,
1577 : 0,
1578 : 0,
1579 : 0
1580 : },
1581 : true
1582 : };
1583 :
1584 : static const struct si_dte_data dte_data_oland =
1585 : {
1586 : { 0, 0, 0, 0, 0 },
1587 : { 0, 0, 0, 0, 0 },
1588 : 0,
1589 : 0,
1590 : 0,
1591 : 0,
1592 : 0,
1593 : 0,
1594 : 0,
1595 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1596 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1597 : { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1598 : 0,
1599 : false
1600 : };
1601 :
1602 : static const struct si_dte_data dte_data_mars_pro =
1603 : {
1604 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1605 : { 0x0, 0x0, 0x0, 0x0, 0x0 },
1606 : 5,
1607 : 55000,
1608 : 105,
1609 : 0xA,
1610 : 1,
1611 : 0,
1612 : 0x10,
1613 : { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1614 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1615 : { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1616 : 90,
1617 : true
1618 : };
1619 :
1620 : static const struct si_dte_data dte_data_sun_xt =
1621 : {
1622 : { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1623 : { 0x0, 0x0, 0x0, 0x0, 0x0 },
1624 : 5,
1625 : 55000,
1626 : 105,
1627 : 0xA,
1628 : 1,
1629 : 0,
1630 : 0x10,
1631 : { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1632 : { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1633 : { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1634 : 90,
1635 : true
1636 : };
1637 :
1638 :
1639 : static const struct si_cac_config_reg cac_weights_hainan[] =
1640 : {
1641 : { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1642 : { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1643 : { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1644 : { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1645 : { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1646 : { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1647 : { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1648 : { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1649 : { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1650 : { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1651 : { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1652 : { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1653 : { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1654 : { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1655 : { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1656 : { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1657 : { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1658 : { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1659 : { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1660 : { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1661 : { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1662 : { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1663 : { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1664 : { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1665 : { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1666 : { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1667 : { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1668 : { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1669 : { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1670 : { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1671 : { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1672 : { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1673 : { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1674 : { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1675 : { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1676 : { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1677 : { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1678 : { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1679 : { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1680 : { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1681 : { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1682 : { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1683 : { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1684 : { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1685 : { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1686 : { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1687 : { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1688 : { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1689 : { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1690 : { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1691 : { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1692 : { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1693 : { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1694 : { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1695 : { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1696 : { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1697 : { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1698 : { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1699 : { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1700 : { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1701 : { 0xFFFFFFFF }
1702 : };
1703 :
1704 : static const struct si_powertune_data powertune_data_hainan =
1705 : {
1706 : ((1 << 16) | 0x6993),
1707 : 5,
1708 : 0,
1709 : 9,
1710 : 105,
1711 : {
1712 : 0UL,
1713 : 0UL,
1714 : 7194395UL,
1715 : 309631529UL,
1716 : -1270850L,
1717 : 4513710L,
1718 : 100
1719 : },
1720 : 117830498UL,
1721 : 12,
1722 : {
1723 : 0,
1724 : 0,
1725 : 0,
1726 : 0,
1727 : 0,
1728 : 0,
1729 : 0,
1730 : 0
1731 : },
1732 : true
1733 : };
1734 :
1735 : struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1736 : struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1737 : struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1738 : struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1739 :
1740 : extern int si_mc_load_microcode(struct radeon_device *rdev);
1741 : extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable);
1742 :
1743 : static int si_populate_voltage_value(struct radeon_device *rdev,
1744 : const struct atom_voltage_table *table,
1745 : u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1746 : static int si_get_std_voltage_value(struct radeon_device *rdev,
1747 : SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1748 : u16 *std_voltage);
1749 : static int si_write_smc_soft_register(struct radeon_device *rdev,
1750 : u16 reg_offset, u32 value);
1751 : static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1752 : struct rv7xx_pl *pl,
1753 : SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1754 : static int si_calculate_sclk_params(struct radeon_device *rdev,
1755 : u32 engine_clock,
1756 : SISLANDS_SMC_SCLK_VALUE *sclk);
1757 :
1758 : static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1759 : static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1760 :
1761 0 : static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1762 : {
1763 0 : struct si_power_info *pi = rdev->pm.dpm.priv;
1764 :
1765 0 : return pi;
1766 : }
1767 :
1768 0 : static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1769 : u16 v, s32 t, u32 ileakage, u32 *leakage)
1770 : {
1771 : s64 kt, kv, leakage_w, i_leakage, vddc;
1772 : s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1773 : s64 tmp;
1774 :
1775 0 : i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1776 0 : vddc = div64_s64(drm_int2fixp(v), 1000);
1777 0 : temperature = div64_s64(drm_int2fixp(t), 1000);
1778 :
1779 0 : t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1780 0 : t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1781 0 : av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1782 0 : bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1783 0 : t_ref = drm_int2fixp(coeff->t_ref);
1784 :
1785 0 : tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1786 0 : kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1787 0 : kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1788 0 : kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1789 :
1790 0 : leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1791 :
1792 0 : *leakage = drm_fixp2int(leakage_w * 1000);
1793 0 : }
1794 :
1795 0 : static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1796 : const struct ni_leakage_coeffients *coeff,
1797 : u16 v,
1798 : s32 t,
1799 : u32 i_leakage,
1800 : u32 *leakage)
1801 : {
1802 0 : si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1803 0 : }
1804 :
1805 0 : static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1806 : const u32 fixed_kt, u16 v,
1807 : u32 ileakage, u32 *leakage)
1808 : {
1809 : s64 kt, kv, leakage_w, i_leakage, vddc;
1810 :
1811 0 : i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1812 0 : vddc = div64_s64(drm_int2fixp(v), 1000);
1813 :
1814 0 : kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1815 0 : kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1816 0 : drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1817 :
1818 0 : leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1819 :
1820 0 : *leakage = drm_fixp2int(leakage_w * 1000);
1821 0 : }
1822 :
1823 0 : static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1824 : const struct ni_leakage_coeffients *coeff,
1825 : const u32 fixed_kt,
1826 : u16 v,
1827 : u32 i_leakage,
1828 : u32 *leakage)
1829 : {
1830 0 : si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1831 0 : }
1832 :
1833 :
1834 0 : static void si_update_dte_from_pl2(struct radeon_device *rdev,
1835 : struct si_dte_data *dte_data)
1836 : {
1837 0 : u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1838 0 : u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1839 0 : u32 k = dte_data->k;
1840 0 : u32 t_max = dte_data->max_t;
1841 0 : u32 t_split[5] = { 10, 15, 20, 25, 30 };
1842 0 : u32 t_0 = dte_data->t0;
1843 : u32 i;
1844 :
1845 0 : if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1846 0 : dte_data->tdep_count = 3;
1847 :
1848 0 : for (i = 0; i < k; i++) {
1849 0 : dte_data->r[i] =
1850 0 : (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1851 0 : (p_limit2 * (u32)100);
1852 : }
1853 :
1854 0 : dte_data->tdep_r[1] = dte_data->r[4] * 2;
1855 :
1856 0 : for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1857 0 : dte_data->tdep_r[i] = dte_data->r[4];
1858 : }
1859 : } else {
1860 0 : DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1861 : }
1862 0 : }
1863 :
1864 0 : static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1865 : {
1866 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
1867 0 : struct si_power_info *si_pi = si_get_pi(rdev);
1868 : bool update_dte_from_pl2 = false;
1869 :
1870 0 : if (rdev->family == CHIP_TAHITI) {
1871 0 : si_pi->cac_weights = cac_weights_tahiti;
1872 0 : si_pi->lcac_config = lcac_tahiti;
1873 0 : si_pi->cac_override = cac_override_tahiti;
1874 0 : si_pi->powertune_data = &powertune_data_tahiti;
1875 0 : si_pi->dte_data = dte_data_tahiti;
1876 :
1877 0 : switch (rdev->pdev->device) {
1878 : case 0x6798:
1879 0 : si_pi->dte_data.enable_dte_by_default = true;
1880 0 : break;
1881 : case 0x6799:
1882 0 : si_pi->dte_data = dte_data_new_zealand;
1883 0 : break;
1884 : case 0x6790:
1885 : case 0x6791:
1886 : case 0x6792:
1887 : case 0x679E:
1888 0 : si_pi->dte_data = dte_data_aruba_pro;
1889 : update_dte_from_pl2 = true;
1890 0 : break;
1891 : case 0x679B:
1892 0 : si_pi->dte_data = dte_data_malta;
1893 : update_dte_from_pl2 = true;
1894 0 : break;
1895 : case 0x679A:
1896 0 : si_pi->dte_data = dte_data_tahiti_pro;
1897 : update_dte_from_pl2 = true;
1898 0 : break;
1899 : default:
1900 0 : if (si_pi->dte_data.enable_dte_by_default == true)
1901 0 : DRM_ERROR("DTE is not enabled!\n");
1902 : break;
1903 : }
1904 0 : } else if (rdev->family == CHIP_PITCAIRN) {
1905 0 : switch (rdev->pdev->device) {
1906 : case 0x6810:
1907 : case 0x6818:
1908 0 : si_pi->cac_weights = cac_weights_pitcairn;
1909 0 : si_pi->lcac_config = lcac_pitcairn;
1910 0 : si_pi->cac_override = cac_override_pitcairn;
1911 0 : si_pi->powertune_data = &powertune_data_pitcairn;
1912 0 : si_pi->dte_data = dte_data_curacao_xt;
1913 : update_dte_from_pl2 = true;
1914 0 : break;
1915 : case 0x6819:
1916 : case 0x6811:
1917 0 : si_pi->cac_weights = cac_weights_pitcairn;
1918 0 : si_pi->lcac_config = lcac_pitcairn;
1919 0 : si_pi->cac_override = cac_override_pitcairn;
1920 0 : si_pi->powertune_data = &powertune_data_pitcairn;
1921 0 : si_pi->dte_data = dte_data_curacao_pro;
1922 : update_dte_from_pl2 = true;
1923 0 : break;
1924 : case 0x6800:
1925 : case 0x6806:
1926 0 : si_pi->cac_weights = cac_weights_pitcairn;
1927 0 : si_pi->lcac_config = lcac_pitcairn;
1928 0 : si_pi->cac_override = cac_override_pitcairn;
1929 0 : si_pi->powertune_data = &powertune_data_pitcairn;
1930 0 : si_pi->dte_data = dte_data_neptune_xt;
1931 : update_dte_from_pl2 = true;
1932 0 : break;
1933 : default:
1934 0 : si_pi->cac_weights = cac_weights_pitcairn;
1935 0 : si_pi->lcac_config = lcac_pitcairn;
1936 0 : si_pi->cac_override = cac_override_pitcairn;
1937 0 : si_pi->powertune_data = &powertune_data_pitcairn;
1938 0 : si_pi->dte_data = dte_data_pitcairn;
1939 0 : break;
1940 : }
1941 0 : } else if (rdev->family == CHIP_VERDE) {
1942 0 : si_pi->lcac_config = lcac_cape_verde;
1943 0 : si_pi->cac_override = cac_override_cape_verde;
1944 0 : si_pi->powertune_data = &powertune_data_cape_verde;
1945 :
1946 0 : switch (rdev->pdev->device) {
1947 : case 0x683B:
1948 : case 0x683F:
1949 : case 0x6829:
1950 : case 0x6835:
1951 0 : si_pi->cac_weights = cac_weights_cape_verde_pro;
1952 0 : si_pi->dte_data = dte_data_cape_verde;
1953 0 : break;
1954 : case 0x682C:
1955 0 : si_pi->cac_weights = cac_weights_cape_verde_pro;
1956 0 : si_pi->dte_data = dte_data_sun_xt;
1957 0 : break;
1958 : case 0x6825:
1959 : case 0x6827:
1960 0 : si_pi->cac_weights = cac_weights_heathrow;
1961 0 : si_pi->dte_data = dte_data_cape_verde;
1962 0 : break;
1963 : case 0x6824:
1964 : case 0x682D:
1965 0 : si_pi->cac_weights = cac_weights_chelsea_xt;
1966 0 : si_pi->dte_data = dte_data_cape_verde;
1967 0 : break;
1968 : case 0x682F:
1969 0 : si_pi->cac_weights = cac_weights_chelsea_pro;
1970 0 : si_pi->dte_data = dte_data_cape_verde;
1971 0 : break;
1972 : case 0x6820:
1973 0 : si_pi->cac_weights = cac_weights_heathrow;
1974 0 : si_pi->dte_data = dte_data_venus_xtx;
1975 0 : break;
1976 : case 0x6821:
1977 0 : si_pi->cac_weights = cac_weights_heathrow;
1978 0 : si_pi->dte_data = dte_data_venus_xt;
1979 0 : break;
1980 : case 0x6823:
1981 : case 0x682B:
1982 : case 0x6822:
1983 : case 0x682A:
1984 0 : si_pi->cac_weights = cac_weights_chelsea_pro;
1985 0 : si_pi->dte_data = dte_data_venus_pro;
1986 0 : break;
1987 : default:
1988 0 : si_pi->cac_weights = cac_weights_cape_verde;
1989 0 : si_pi->dte_data = dte_data_cape_verde;
1990 0 : break;
1991 : }
1992 0 : } else if (rdev->family == CHIP_OLAND) {
1993 0 : switch (rdev->pdev->device) {
1994 : case 0x6601:
1995 : case 0x6621:
1996 : case 0x6603:
1997 : case 0x6605:
1998 0 : si_pi->cac_weights = cac_weights_mars_pro;
1999 0 : si_pi->lcac_config = lcac_mars_pro;
2000 0 : si_pi->cac_override = cac_override_oland;
2001 0 : si_pi->powertune_data = &powertune_data_mars_pro;
2002 0 : si_pi->dte_data = dte_data_mars_pro;
2003 : update_dte_from_pl2 = true;
2004 0 : break;
2005 : case 0x6600:
2006 : case 0x6606:
2007 : case 0x6620:
2008 : case 0x6604:
2009 0 : si_pi->cac_weights = cac_weights_mars_xt;
2010 0 : si_pi->lcac_config = lcac_mars_pro;
2011 0 : si_pi->cac_override = cac_override_oland;
2012 0 : si_pi->powertune_data = &powertune_data_mars_pro;
2013 0 : si_pi->dte_data = dte_data_mars_pro;
2014 : update_dte_from_pl2 = true;
2015 0 : break;
2016 : case 0x6611:
2017 : case 0x6613:
2018 : case 0x6608:
2019 0 : si_pi->cac_weights = cac_weights_oland_pro;
2020 0 : si_pi->lcac_config = lcac_mars_pro;
2021 0 : si_pi->cac_override = cac_override_oland;
2022 0 : si_pi->powertune_data = &powertune_data_mars_pro;
2023 0 : si_pi->dte_data = dte_data_mars_pro;
2024 : update_dte_from_pl2 = true;
2025 0 : break;
2026 : case 0x6610:
2027 0 : si_pi->cac_weights = cac_weights_oland_xt;
2028 0 : si_pi->lcac_config = lcac_mars_pro;
2029 0 : si_pi->cac_override = cac_override_oland;
2030 0 : si_pi->powertune_data = &powertune_data_mars_pro;
2031 0 : si_pi->dte_data = dte_data_mars_pro;
2032 : update_dte_from_pl2 = true;
2033 0 : break;
2034 : default:
2035 0 : si_pi->cac_weights = cac_weights_oland;
2036 0 : si_pi->lcac_config = lcac_oland;
2037 0 : si_pi->cac_override = cac_override_oland;
2038 0 : si_pi->powertune_data = &powertune_data_oland;
2039 0 : si_pi->dte_data = dte_data_oland;
2040 0 : break;
2041 : }
2042 0 : } else if (rdev->family == CHIP_HAINAN) {
2043 0 : si_pi->cac_weights = cac_weights_hainan;
2044 0 : si_pi->lcac_config = lcac_oland;
2045 0 : si_pi->cac_override = cac_override_oland;
2046 0 : si_pi->powertune_data = &powertune_data_hainan;
2047 0 : si_pi->dte_data = dte_data_sun_xt;
2048 : update_dte_from_pl2 = true;
2049 : } else {
2050 0 : DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2051 0 : return;
2052 : }
2053 :
2054 0 : ni_pi->enable_power_containment = false;
2055 0 : ni_pi->enable_cac = false;
2056 0 : ni_pi->enable_sq_ramping = false;
2057 0 : si_pi->enable_dte = false;
2058 :
2059 0 : if (si_pi->powertune_data->enable_powertune_by_default) {
2060 0 : ni_pi->enable_power_containment= true;
2061 0 : ni_pi->enable_cac = true;
2062 0 : if (si_pi->dte_data.enable_dte_by_default) {
2063 0 : si_pi->enable_dte = true;
2064 0 : if (update_dte_from_pl2)
2065 0 : si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2066 :
2067 : }
2068 0 : ni_pi->enable_sq_ramping = true;
2069 0 : }
2070 :
2071 0 : ni_pi->driver_calculate_cac_leakage = true;
2072 0 : ni_pi->cac_configuration_required = true;
2073 :
2074 0 : if (ni_pi->cac_configuration_required) {
2075 0 : ni_pi->support_cac_long_term_average = true;
2076 0 : si_pi->dyn_powertune_data.l2_lta_window_size =
2077 0 : si_pi->powertune_data->l2_lta_window_size_default;
2078 0 : si_pi->dyn_powertune_data.lts_truncate =
2079 0 : si_pi->powertune_data->lts_truncate_default;
2080 0 : } else {
2081 0 : ni_pi->support_cac_long_term_average = false;
2082 0 : si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2083 0 : si_pi->dyn_powertune_data.lts_truncate = 0;
2084 : }
2085 :
2086 0 : si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2087 0 : }
2088 :
2089 0 : static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2090 : {
2091 0 : return 1;
2092 : }
2093 :
2094 0 : static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2095 : {
2096 : u32 xclk;
2097 : u32 wintime;
2098 : u32 cac_window;
2099 : u32 cac_window_size;
2100 :
2101 0 : xclk = radeon_get_xclk(rdev);
2102 :
2103 0 : if (xclk == 0)
2104 0 : return 0;
2105 :
2106 0 : cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2107 0 : cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2108 :
2109 0 : wintime = (cac_window_size * 100) / xclk;
2110 :
2111 0 : return wintime;
2112 0 : }
2113 :
2114 0 : static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2115 : {
2116 0 : return power_in_watts;
2117 : }
2118 :
2119 0 : static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2120 : bool adjust_polarity,
2121 : u32 tdp_adjustment,
2122 : u32 *tdp_limit,
2123 : u32 *near_tdp_limit)
2124 : {
2125 : u32 adjustment_delta, max_tdp_limit;
2126 :
2127 0 : if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2128 0 : return -EINVAL;
2129 :
2130 0 : max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2131 :
2132 0 : if (adjust_polarity) {
2133 0 : *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2134 0 : *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2135 0 : } else {
2136 0 : *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2137 0 : adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2138 0 : if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2139 0 : *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2140 : else
2141 0 : *near_tdp_limit = 0;
2142 : }
2143 :
2144 0 : if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2145 0 : return -EINVAL;
2146 0 : if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2147 0 : return -EINVAL;
2148 :
2149 0 : return 0;
2150 0 : }
2151 :
2152 0 : static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2153 : struct radeon_ps *radeon_state)
2154 : {
2155 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2156 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2157 :
2158 0 : if (ni_pi->enable_power_containment) {
2159 0 : SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2160 : PP_SIslands_PAPMParameters *papm_parm;
2161 0 : struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2162 0 : u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2163 0 : u32 tdp_limit;
2164 0 : u32 near_tdp_limit;
2165 : int ret;
2166 :
2167 0 : if (scaling_factor == 0)
2168 0 : return -EINVAL;
2169 :
2170 0 : memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2171 :
2172 0 : ret = si_calculate_adjusted_tdp_limits(rdev,
2173 : false, /* ??? */
2174 0 : rdev->pm.dpm.tdp_adjustment,
2175 : &tdp_limit,
2176 : &near_tdp_limit);
2177 0 : if (ret)
2178 0 : return ret;
2179 :
2180 0 : smc_table->dpm2Params.TDPLimit =
2181 0 : cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2182 0 : smc_table->dpm2Params.NearTDPLimit =
2183 0 : cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2184 0 : smc_table->dpm2Params.SafePowerLimit =
2185 0 : cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2186 :
2187 0 : ret = si_copy_bytes_to_smc(rdev,
2188 0 : (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2189 : offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2190 0 : (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2191 : sizeof(u32) * 3,
2192 0 : si_pi->sram_end);
2193 0 : if (ret)
2194 0 : return ret;
2195 :
2196 0 : if (si_pi->enable_ppm) {
2197 0 : papm_parm = &si_pi->papm_parm;
2198 0 : memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2199 0 : papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2200 0 : papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2201 0 : papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2202 0 : papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2203 0 : papm_parm->PlatformPowerLimit = 0xffffffff;
2204 0 : papm_parm->NearTDPLimitPAPM = 0xffffffff;
2205 :
2206 0 : ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2207 : (u8 *)papm_parm,
2208 : sizeof(PP_SIslands_PAPMParameters),
2209 0 : si_pi->sram_end);
2210 0 : if (ret)
2211 0 : return ret;
2212 : }
2213 0 : }
2214 0 : return 0;
2215 0 : }
2216 :
2217 0 : static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2218 : struct radeon_ps *radeon_state)
2219 : {
2220 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2221 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2222 :
2223 0 : if (ni_pi->enable_power_containment) {
2224 0 : SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2225 0 : u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2226 : int ret;
2227 :
2228 0 : memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2229 :
2230 0 : smc_table->dpm2Params.NearTDPLimit =
2231 0 : cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2232 0 : smc_table->dpm2Params.SafePowerLimit =
2233 0 : cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2234 :
2235 0 : ret = si_copy_bytes_to_smc(rdev,
2236 0 : (si_pi->state_table_start +
2237 0 : offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2238 : offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2239 0 : (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2240 : sizeof(u32) * 2,
2241 0 : si_pi->sram_end);
2242 0 : if (ret)
2243 0 : return ret;
2244 0 : }
2245 :
2246 0 : return 0;
2247 0 : }
2248 :
2249 0 : static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2250 : const u16 prev_std_vddc,
2251 : const u16 curr_std_vddc)
2252 : {
2253 : u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2254 0 : u64 prev_vddc = (u64)prev_std_vddc;
2255 0 : u64 curr_vddc = (u64)curr_std_vddc;
2256 : u64 pwr_efficiency_ratio, n, d;
2257 :
2258 0 : if ((prev_vddc == 0) || (curr_vddc == 0))
2259 0 : return 0;
2260 :
2261 0 : n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2262 0 : d = prev_vddc * prev_vddc;
2263 0 : pwr_efficiency_ratio = div64_u64(n, d);
2264 :
2265 0 : if (pwr_efficiency_ratio > (u64)0xFFFF)
2266 0 : return 0;
2267 :
2268 0 : return (u16)pwr_efficiency_ratio;
2269 0 : }
2270 :
2271 0 : static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2272 : struct radeon_ps *radeon_state)
2273 : {
2274 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2275 :
2276 0 : if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2277 0 : radeon_state->vclk && radeon_state->dclk)
2278 0 : return true;
2279 :
2280 0 : return false;
2281 0 : }
2282 :
2283 0 : static int si_populate_power_containment_values(struct radeon_device *rdev,
2284 : struct radeon_ps *radeon_state,
2285 : SISLANDS_SMC_SWSTATE *smc_state)
2286 : {
2287 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2288 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2289 0 : struct ni_ps *state = ni_get_ps(radeon_state);
2290 0 : SISLANDS_SMC_VOLTAGE_VALUE vddc;
2291 : u32 prev_sclk;
2292 : u32 max_sclk;
2293 : u32 min_sclk;
2294 0 : u16 prev_std_vddc;
2295 0 : u16 curr_std_vddc;
2296 : int i;
2297 : u16 pwr_efficiency_ratio;
2298 : u8 max_ps_percent;
2299 : bool disable_uvd_power_tune;
2300 : int ret;
2301 :
2302 0 : if (ni_pi->enable_power_containment == false)
2303 0 : return 0;
2304 :
2305 0 : if (state->performance_level_count == 0)
2306 0 : return -EINVAL;
2307 :
2308 0 : if (smc_state->levelCount != state->performance_level_count)
2309 0 : return -EINVAL;
2310 :
2311 0 : disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2312 :
2313 0 : smc_state->levels[0].dpm2.MaxPS = 0;
2314 0 : smc_state->levels[0].dpm2.NearTDPDec = 0;
2315 0 : smc_state->levels[0].dpm2.AboveSafeInc = 0;
2316 0 : smc_state->levels[0].dpm2.BelowSafeInc = 0;
2317 0 : smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2318 :
2319 0 : for (i = 1; i < state->performance_level_count; i++) {
2320 0 : prev_sclk = state->performance_levels[i-1].sclk;
2321 0 : max_sclk = state->performance_levels[i].sclk;
2322 : if (i == 1)
2323 : max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2324 : else
2325 : max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2326 :
2327 0 : if (prev_sclk > max_sclk)
2328 0 : return -EINVAL;
2329 :
2330 0 : if ((max_ps_percent == 0) ||
2331 0 : (prev_sclk == max_sclk) ||
2332 : disable_uvd_power_tune) {
2333 : min_sclk = max_sclk;
2334 0 : } else if (i == 1) {
2335 : min_sclk = prev_sclk;
2336 0 : } else {
2337 0 : min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2338 : }
2339 :
2340 0 : if (min_sclk < state->performance_levels[0].sclk)
2341 0 : min_sclk = state->performance_levels[0].sclk;
2342 :
2343 0 : if (min_sclk == 0)
2344 0 : return -EINVAL;
2345 :
2346 0 : ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2347 0 : state->performance_levels[i-1].vddc, &vddc);
2348 0 : if (ret)
2349 0 : return ret;
2350 :
2351 0 : ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2352 0 : if (ret)
2353 0 : return ret;
2354 :
2355 0 : ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2356 0 : state->performance_levels[i].vddc, &vddc);
2357 0 : if (ret)
2358 0 : return ret;
2359 :
2360 0 : ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2361 0 : if (ret)
2362 0 : return ret;
2363 :
2364 0 : pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2365 0 : prev_std_vddc, curr_std_vddc);
2366 :
2367 0 : smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2368 0 : smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2369 0 : smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2370 0 : smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2371 0 : smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2372 : }
2373 :
2374 0 : return 0;
2375 0 : }
2376 :
2377 0 : static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2378 : struct radeon_ps *radeon_state,
2379 : SISLANDS_SMC_SWSTATE *smc_state)
2380 : {
2381 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2382 0 : struct ni_ps *state = ni_get_ps(radeon_state);
2383 : u32 sq_power_throttle, sq_power_throttle2;
2384 0 : bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2385 : int i;
2386 :
2387 0 : if (state->performance_level_count == 0)
2388 0 : return -EINVAL;
2389 :
2390 0 : if (smc_state->levelCount != state->performance_level_count)
2391 0 : return -EINVAL;
2392 :
2393 0 : if (rdev->pm.dpm.sq_ramping_threshold == 0)
2394 0 : return -EINVAL;
2395 :
2396 : if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2397 : enable_sq_ramping = false;
2398 :
2399 : if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2400 : enable_sq_ramping = false;
2401 :
2402 : if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2403 : enable_sq_ramping = false;
2404 :
2405 : if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2406 : enable_sq_ramping = false;
2407 :
2408 : if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2409 : enable_sq_ramping = false;
2410 :
2411 0 : for (i = 0; i < state->performance_level_count; i++) {
2412 : sq_power_throttle = 0;
2413 : sq_power_throttle2 = 0;
2414 :
2415 0 : if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2416 : enable_sq_ramping) {
2417 : sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2418 : sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2419 : sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2420 : sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2421 : sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2422 0 : } else {
2423 : sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2424 : sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2425 : }
2426 :
2427 0 : smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2428 0 : smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2429 : }
2430 :
2431 0 : return 0;
2432 0 : }
2433 :
2434 0 : static int si_enable_power_containment(struct radeon_device *rdev,
2435 : struct radeon_ps *radeon_new_state,
2436 : bool enable)
2437 : {
2438 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2439 : PPSMC_Result smc_result;
2440 : int ret = 0;
2441 :
2442 0 : if (ni_pi->enable_power_containment) {
2443 0 : if (enable) {
2444 0 : if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2445 0 : smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2446 0 : if (smc_result != PPSMC_Result_OK) {
2447 : ret = -EINVAL;
2448 0 : ni_pi->pc_enabled = false;
2449 0 : } else {
2450 0 : ni_pi->pc_enabled = true;
2451 : }
2452 : }
2453 : } else {
2454 0 : smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2455 0 : if (smc_result != PPSMC_Result_OK)
2456 0 : ret = -EINVAL;
2457 0 : ni_pi->pc_enabled = false;
2458 : }
2459 : }
2460 :
2461 0 : return ret;
2462 : }
2463 :
2464 0 : static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2465 : {
2466 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2467 : int ret = 0;
2468 0 : struct si_dte_data *dte_data = &si_pi->dte_data;
2469 : Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2470 : u32 table_size;
2471 : u8 tdep_count;
2472 : u32 i;
2473 :
2474 0 : if (dte_data == NULL)
2475 0 : si_pi->enable_dte = false;
2476 :
2477 0 : if (si_pi->enable_dte == false)
2478 0 : return 0;
2479 :
2480 0 : if (dte_data->k <= 0)
2481 0 : return -EINVAL;
2482 :
2483 0 : dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2484 0 : if (dte_tables == NULL) {
2485 0 : si_pi->enable_dte = false;
2486 0 : return -ENOMEM;
2487 : }
2488 :
2489 0 : table_size = dte_data->k;
2490 :
2491 0 : if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2492 : table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2493 :
2494 0 : tdep_count = dte_data->tdep_count;
2495 0 : if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2496 : tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2497 :
2498 0 : dte_tables->K = cpu_to_be32(table_size);
2499 0 : dte_tables->T0 = cpu_to_be32(dte_data->t0);
2500 0 : dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2501 0 : dte_tables->WindowSize = dte_data->window_size;
2502 0 : dte_tables->temp_select = dte_data->temp_select;
2503 0 : dte_tables->DTE_mode = dte_data->dte_mode;
2504 0 : dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2505 :
2506 0 : if (tdep_count > 0)
2507 0 : table_size--;
2508 :
2509 0 : for (i = 0; i < table_size; i++) {
2510 0 : dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2511 0 : dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2512 : }
2513 :
2514 0 : dte_tables->Tdep_count = tdep_count;
2515 :
2516 0 : for (i = 0; i < (u32)tdep_count; i++) {
2517 0 : dte_tables->T_limits[i] = dte_data->t_limits[i];
2518 0 : dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2519 0 : dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2520 : }
2521 :
2522 0 : ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2523 0 : sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2524 0 : kfree(dte_tables);
2525 :
2526 0 : return ret;
2527 0 : }
2528 :
2529 0 : static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2530 : u16 *max, u16 *min)
2531 : {
2532 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2533 : struct radeon_cac_leakage_table *table =
2534 0 : &rdev->pm.dpm.dyn_state.cac_leakage_table;
2535 : u32 i;
2536 : u32 v0_loadline;
2537 :
2538 :
2539 0 : if (table == NULL)
2540 0 : return -EINVAL;
2541 :
2542 0 : *max = 0;
2543 0 : *min = 0xFFFF;
2544 :
2545 0 : for (i = 0; i < table->count; i++) {
2546 0 : if (table->entries[i].vddc > *max)
2547 0 : *max = table->entries[i].vddc;
2548 0 : if (table->entries[i].vddc < *min)
2549 0 : *min = table->entries[i].vddc;
2550 : }
2551 :
2552 0 : if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2553 0 : return -EINVAL;
2554 :
2555 0 : v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2556 :
2557 0 : if (v0_loadline > 0xFFFFUL)
2558 0 : return -EINVAL;
2559 :
2560 0 : *min = (u16)v0_loadline;
2561 :
2562 0 : if ((*min > *max) || (*max == 0) || (*min == 0))
2563 0 : return -EINVAL;
2564 :
2565 0 : return 0;
2566 0 : }
2567 :
2568 0 : static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2569 : {
2570 0 : return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2571 : SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2572 : }
2573 :
2574 0 : static int si_init_dte_leakage_table(struct radeon_device *rdev,
2575 : PP_SIslands_CacConfig *cac_tables,
2576 : u16 vddc_max, u16 vddc_min, u16 vddc_step,
2577 : u16 t0, u16 t_step)
2578 : {
2579 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2580 0 : u32 leakage;
2581 : unsigned int i, j;
2582 : s32 t;
2583 : u32 smc_leakage;
2584 : u32 scaling_factor;
2585 : u16 voltage;
2586 :
2587 0 : scaling_factor = si_get_smc_power_scaling_factor(rdev);
2588 :
2589 0 : for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2590 0 : t = (1000 * (i * t_step + t0));
2591 :
2592 0 : for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2593 0 : voltage = vddc_max - (vddc_step * j);
2594 :
2595 0 : si_calculate_leakage_for_v_and_t(rdev,
2596 0 : &si_pi->powertune_data->leakage_coefficients,
2597 : voltage,
2598 : t,
2599 0 : si_pi->dyn_powertune_data.cac_leakage,
2600 : &leakage);
2601 :
2602 0 : smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2603 :
2604 0 : if (smc_leakage > 0xFFFF)
2605 : smc_leakage = 0xFFFF;
2606 :
2607 0 : cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2608 0 : cpu_to_be16((u16)smc_leakage);
2609 : }
2610 : }
2611 0 : return 0;
2612 0 : }
2613 :
2614 0 : static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2615 : PP_SIslands_CacConfig *cac_tables,
2616 : u16 vddc_max, u16 vddc_min, u16 vddc_step)
2617 : {
2618 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2619 0 : u32 leakage;
2620 : unsigned int i, j;
2621 : u32 smc_leakage;
2622 : u32 scaling_factor;
2623 : u16 voltage;
2624 :
2625 0 : scaling_factor = si_get_smc_power_scaling_factor(rdev);
2626 :
2627 0 : for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2628 0 : voltage = vddc_max - (vddc_step * j);
2629 :
2630 0 : si_calculate_leakage_for_v(rdev,
2631 0 : &si_pi->powertune_data->leakage_coefficients,
2632 0 : si_pi->powertune_data->fixed_kt,
2633 : voltage,
2634 0 : si_pi->dyn_powertune_data.cac_leakage,
2635 : &leakage);
2636 :
2637 0 : smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2638 :
2639 0 : if (smc_leakage > 0xFFFF)
2640 : smc_leakage = 0xFFFF;
2641 :
2642 0 : for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2643 0 : cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2644 0 : cpu_to_be16((u16)smc_leakage);
2645 : }
2646 0 : return 0;
2647 0 : }
2648 :
2649 0 : static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2650 : {
2651 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2652 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2653 : PP_SIslands_CacConfig *cac_tables = NULL;
2654 0 : u16 vddc_max, vddc_min, vddc_step;
2655 : u16 t0, t_step;
2656 : u32 load_line_slope, reg;
2657 : int ret = 0;
2658 0 : u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2659 :
2660 0 : if (ni_pi->enable_cac == false)
2661 0 : return 0;
2662 :
2663 0 : cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2664 0 : if (!cac_tables)
2665 0 : return -ENOMEM;
2666 :
2667 0 : reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2668 0 : reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2669 0 : WREG32(CG_CAC_CTRL, reg);
2670 :
2671 0 : si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2672 0 : si_pi->dyn_powertune_data.dc_pwr_value =
2673 0 : si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2674 0 : si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2675 0 : si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2676 :
2677 0 : si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2678 :
2679 0 : ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2680 0 : if (ret)
2681 : goto done_free;
2682 :
2683 0 : vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2684 0 : vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2685 : t_step = 4;
2686 : t0 = 60;
2687 :
2688 0 : if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2689 0 : ret = si_init_dte_leakage_table(rdev, cac_tables,
2690 0 : vddc_max, vddc_min, vddc_step,
2691 : t0, t_step);
2692 : else
2693 0 : ret = si_init_simplified_leakage_table(rdev, cac_tables,
2694 0 : vddc_max, vddc_min, vddc_step);
2695 0 : if (ret)
2696 : goto done_free;
2697 :
2698 0 : load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2699 :
2700 0 : cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2701 0 : cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2702 0 : cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2703 0 : cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2704 0 : cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2705 0 : cac_tables->R_LL = cpu_to_be32(load_line_slope);
2706 0 : cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2707 0 : cac_tables->calculation_repeats = cpu_to_be32(2);
2708 0 : cac_tables->dc_cac = cpu_to_be32(0);
2709 0 : cac_tables->log2_PG_LKG_SCALE = 12;
2710 0 : cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2711 0 : cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2712 0 : cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2713 :
2714 0 : ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2715 0 : sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2716 :
2717 0 : if (ret)
2718 : goto done_free;
2719 :
2720 0 : ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2721 :
2722 : done_free:
2723 0 : if (ret) {
2724 0 : ni_pi->enable_cac = false;
2725 0 : ni_pi->enable_power_containment = false;
2726 0 : }
2727 :
2728 0 : kfree(cac_tables);
2729 :
2730 0 : return 0;
2731 0 : }
2732 :
2733 0 : static int si_program_cac_config_registers(struct radeon_device *rdev,
2734 : const struct si_cac_config_reg *cac_config_regs)
2735 : {
2736 : const struct si_cac_config_reg *config_regs = cac_config_regs;
2737 : u32 data = 0, offset;
2738 :
2739 0 : if (!config_regs)
2740 0 : return -EINVAL;
2741 :
2742 0 : while (config_regs->offset != 0xFFFFFFFF) {
2743 0 : switch (config_regs->type) {
2744 : case SISLANDS_CACCONFIG_CGIND:
2745 0 : offset = SMC_CG_IND_START + config_regs->offset;
2746 0 : if (offset < SMC_CG_IND_END)
2747 0 : data = RREG32_SMC(offset);
2748 : break;
2749 : default:
2750 0 : data = RREG32(config_regs->offset << 2);
2751 0 : break;
2752 : }
2753 :
2754 0 : data &= ~config_regs->mask;
2755 0 : data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2756 :
2757 0 : switch (config_regs->type) {
2758 : case SISLANDS_CACCONFIG_CGIND:
2759 0 : offset = SMC_CG_IND_START + config_regs->offset;
2760 0 : if (offset < SMC_CG_IND_END)
2761 0 : WREG32_SMC(offset, data);
2762 : break;
2763 : default:
2764 0 : WREG32(config_regs->offset << 2, data);
2765 0 : break;
2766 : }
2767 0 : config_regs++;
2768 : }
2769 0 : return 0;
2770 0 : }
2771 :
2772 0 : static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2773 : {
2774 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2775 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2776 : int ret;
2777 :
2778 0 : if ((ni_pi->enable_cac == false) ||
2779 0 : (ni_pi->cac_configuration_required == false))
2780 0 : return 0;
2781 :
2782 0 : ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2783 0 : if (ret)
2784 0 : return ret;
2785 0 : ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2786 0 : if (ret)
2787 0 : return ret;
2788 0 : ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2789 0 : if (ret)
2790 0 : return ret;
2791 :
2792 0 : return 0;
2793 0 : }
2794 :
2795 0 : static int si_enable_smc_cac(struct radeon_device *rdev,
2796 : struct radeon_ps *radeon_new_state,
2797 : bool enable)
2798 : {
2799 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2800 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2801 : PPSMC_Result smc_result;
2802 : int ret = 0;
2803 :
2804 0 : if (ni_pi->enable_cac) {
2805 0 : if (enable) {
2806 0 : if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2807 0 : if (ni_pi->support_cac_long_term_average) {
2808 0 : smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2809 0 : if (smc_result != PPSMC_Result_OK)
2810 0 : ni_pi->support_cac_long_term_average = false;
2811 : }
2812 :
2813 0 : smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2814 0 : if (smc_result != PPSMC_Result_OK) {
2815 : ret = -EINVAL;
2816 0 : ni_pi->cac_enabled = false;
2817 0 : } else {
2818 0 : ni_pi->cac_enabled = true;
2819 : }
2820 :
2821 0 : if (si_pi->enable_dte) {
2822 0 : smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2823 0 : if (smc_result != PPSMC_Result_OK)
2824 0 : ret = -EINVAL;
2825 : }
2826 : }
2827 0 : } else if (ni_pi->cac_enabled) {
2828 0 : if (si_pi->enable_dte)
2829 0 : smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2830 :
2831 0 : smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2832 :
2833 0 : ni_pi->cac_enabled = false;
2834 :
2835 0 : if (ni_pi->support_cac_long_term_average)
2836 0 : smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2837 : }
2838 : }
2839 0 : return ret;
2840 : }
2841 :
2842 0 : static int si_init_smc_spll_table(struct radeon_device *rdev)
2843 : {
2844 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
2845 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2846 : SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2847 0 : SISLANDS_SMC_SCLK_VALUE sclk_params;
2848 : u32 fb_div, p_div;
2849 : u32 clk_s, clk_v;
2850 : u32 sclk = 0;
2851 : int ret = 0;
2852 : u32 tmp;
2853 : int i;
2854 :
2855 0 : if (si_pi->spll_table_start == 0)
2856 0 : return -EINVAL;
2857 :
2858 0 : spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2859 0 : if (spll_table == NULL)
2860 0 : return -ENOMEM;
2861 :
2862 0 : for (i = 0; i < 256; i++) {
2863 0 : ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2864 0 : if (ret)
2865 : break;
2866 :
2867 0 : p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2868 0 : fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2869 0 : clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2870 0 : clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2871 :
2872 0 : fb_div &= ~0x00001FFF;
2873 0 : fb_div >>= 1;
2874 0 : clk_v >>= 6;
2875 :
2876 0 : if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2877 0 : ret = -EINVAL;
2878 0 : if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2879 0 : ret = -EINVAL;
2880 0 : if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2881 0 : ret = -EINVAL;
2882 0 : if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2883 0 : ret = -EINVAL;
2884 :
2885 0 : if (ret)
2886 : break;
2887 :
2888 0 : tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2889 0 : ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2890 0 : spll_table->freq[i] = cpu_to_be32(tmp);
2891 :
2892 0 : tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2893 0 : ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2894 0 : spll_table->ss[i] = cpu_to_be32(tmp);
2895 :
2896 0 : sclk += 512;
2897 : }
2898 :
2899 :
2900 0 : if (!ret)
2901 0 : ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2902 : (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2903 0 : si_pi->sram_end);
2904 :
2905 0 : if (ret)
2906 0 : ni_pi->enable_power_containment = false;
2907 :
2908 0 : kfree(spll_table);
2909 :
2910 0 : return ret;
2911 0 : }
2912 :
2913 : struct si_dpm_quirk {
2914 : u32 chip_vendor;
2915 : u32 chip_device;
2916 : u32 subsys_vendor;
2917 : u32 subsys_device;
2918 : u32 max_sclk;
2919 : u32 max_mclk;
2920 : };
2921 :
2922 : /* cards with dpm stability problems */
2923 : static struct si_dpm_quirk si_dpm_quirk_list[] = {
2924 : /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
2925 : { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
2926 : { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
2927 : { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
2928 : { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
2929 : { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
2930 : { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
2931 : { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
2932 : { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
2933 : { 0, 0, 0, 0 },
2934 : };
2935 :
2936 0 : static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2937 : u16 vce_voltage)
2938 : {
2939 : u16 highest_leakage = 0;
2940 0 : struct si_power_info *si_pi = si_get_pi(rdev);
2941 : int i;
2942 :
2943 0 : for (i = 0; i < si_pi->leakage_voltage.count; i++){
2944 0 : if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
2945 0 : highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
2946 : }
2947 :
2948 0 : if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
2949 0 : return highest_leakage;
2950 :
2951 0 : return vce_voltage;
2952 0 : }
2953 :
2954 0 : static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2955 : u32 evclk, u32 ecclk, u16 *voltage)
2956 : {
2957 : u32 i;
2958 : int ret = -EINVAL;
2959 : struct radeon_vce_clock_voltage_dependency_table *table =
2960 0 : &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2961 :
2962 0 : if (((evclk == 0) && (ecclk == 0)) ||
2963 0 : (table && (table->count == 0))) {
2964 0 : *voltage = 0;
2965 0 : return 0;
2966 : }
2967 :
2968 0 : for (i = 0; i < table->count; i++) {
2969 0 : if ((evclk <= table->entries[i].evclk) &&
2970 0 : (ecclk <= table->entries[i].ecclk)) {
2971 0 : *voltage = table->entries[i].v;
2972 : ret = 0;
2973 0 : break;
2974 : }
2975 : }
2976 :
2977 : /* if no match return the highest voltage */
2978 0 : if (ret)
2979 0 : *voltage = table->entries[table->count - 1].v;
2980 :
2981 0 : *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2982 :
2983 0 : return ret;
2984 0 : }
2985 :
2986 0 : static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2987 : struct radeon_ps *rps)
2988 : {
2989 0 : struct ni_ps *ps = ni_get_ps(rps);
2990 : struct radeon_clock_and_voltage_limits *max_limits;
2991 : bool disable_mclk_switching = false;
2992 : bool disable_sclk_switching = false;
2993 : u32 mclk, sclk;
2994 0 : u16 vddc, vddci, min_vce_voltage = 0;
2995 0 : u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
2996 : u32 max_sclk = 0, max_mclk = 0;
2997 : int i;
2998 : struct si_dpm_quirk *p = si_dpm_quirk_list;
2999 :
3000 : /* limit all SI kickers */
3001 0 : if (rdev->family == CHIP_PITCAIRN) {
3002 0 : if ((rdev->pdev->revision == 0x81) ||
3003 0 : (rdev->pdev->device == 0x6810) ||
3004 0 : (rdev->pdev->device == 0x6811) ||
3005 0 : (rdev->pdev->device == 0x6816) ||
3006 0 : (rdev->pdev->device == 0x6817) ||
3007 0 : (rdev->pdev->device == 0x6806))
3008 0 : max_mclk = 120000;
3009 0 : } else if (rdev->family == CHIP_OLAND) {
3010 0 : if ((rdev->pdev->revision == 0xC7) ||
3011 0 : (rdev->pdev->revision == 0x80) ||
3012 0 : (rdev->pdev->revision == 0x81) ||
3013 0 : (rdev->pdev->revision == 0x83) ||
3014 0 : (rdev->pdev->revision == 0x87) ||
3015 0 : (rdev->pdev->device == 0x6604) ||
3016 0 : (rdev->pdev->device == 0x6605)) {
3017 : max_sclk = 75000;
3018 : max_mclk = 80000;
3019 0 : }
3020 0 : } else if (rdev->family == CHIP_HAINAN) {
3021 0 : if ((rdev->pdev->revision == 0x81) ||
3022 0 : (rdev->pdev->revision == 0x83) ||
3023 0 : (rdev->pdev->revision == 0xC3) ||
3024 0 : (rdev->pdev->device == 0x6664) ||
3025 0 : (rdev->pdev->device == 0x6665) ||
3026 0 : (rdev->pdev->device == 0x6667)) {
3027 : max_sclk = 75000;
3028 : max_mclk = 80000;
3029 0 : }
3030 0 : } else if (rdev->family == CHIP_OLAND) {
3031 0 : if ((rdev->pdev->revision == 0xC7) ||
3032 0 : (rdev->pdev->revision == 0x80) ||
3033 0 : (rdev->pdev->revision == 0x81) ||
3034 0 : (rdev->pdev->revision == 0x83) ||
3035 0 : (rdev->pdev->revision == 0x87) ||
3036 0 : (rdev->pdev->device == 0x6604) ||
3037 0 : (rdev->pdev->device == 0x6605)) {
3038 : max_sclk = 75000;
3039 0 : }
3040 : }
3041 : /* Apply dpm quirks */
3042 0 : while (p && p->chip_device != 0) {
3043 0 : if (rdev->pdev->vendor == p->chip_vendor &&
3044 0 : rdev->pdev->device == p->chip_device &&
3045 0 : rdev->pdev->subsystem_vendor == p->subsys_vendor &&
3046 0 : rdev->pdev->subsystem_device == p->subsys_device) {
3047 0 : max_sclk = p->max_sclk;
3048 0 : max_mclk = p->max_mclk;
3049 0 : break;
3050 : }
3051 0 : ++p;
3052 : }
3053 :
3054 0 : if (rps->vce_active) {
3055 0 : rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
3056 0 : rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
3057 0 : si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
3058 : &min_vce_voltage);
3059 0 : } else {
3060 0 : rps->evclk = 0;
3061 0 : rps->ecclk = 0;
3062 : }
3063 :
3064 0 : if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
3065 0 : ni_dpm_vblank_too_short(rdev))
3066 0 : disable_mclk_switching = true;
3067 :
3068 0 : if (rps->vclk || rps->dclk) {
3069 : disable_mclk_switching = true;
3070 : disable_sclk_switching = true;
3071 0 : }
3072 :
3073 0 : if (rdev->pm.dpm.ac_power)
3074 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3075 : else
3076 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3077 :
3078 0 : for (i = ps->performance_level_count - 2; i >= 0; i--) {
3079 0 : if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3080 0 : ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3081 : }
3082 0 : if (rdev->pm.dpm.ac_power == false) {
3083 0 : for (i = 0; i < ps->performance_level_count; i++) {
3084 0 : if (ps->performance_levels[i].mclk > max_limits->mclk)
3085 0 : ps->performance_levels[i].mclk = max_limits->mclk;
3086 0 : if (ps->performance_levels[i].sclk > max_limits->sclk)
3087 0 : ps->performance_levels[i].sclk = max_limits->sclk;
3088 0 : if (ps->performance_levels[i].vddc > max_limits->vddc)
3089 0 : ps->performance_levels[i].vddc = max_limits->vddc;
3090 0 : if (ps->performance_levels[i].vddci > max_limits->vddci)
3091 0 : ps->performance_levels[i].vddci = max_limits->vddci;
3092 : }
3093 : }
3094 :
3095 : /* limit clocks to max supported clocks based on voltage dependency tables */
3096 0 : btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3097 : &max_sclk_vddc);
3098 0 : btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3099 : &max_mclk_vddci);
3100 0 : btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3101 : &max_mclk_vddc);
3102 :
3103 0 : for (i = 0; i < ps->performance_level_count; i++) {
3104 0 : if (max_sclk_vddc) {
3105 0 : if (ps->performance_levels[i].sclk > max_sclk_vddc)
3106 0 : ps->performance_levels[i].sclk = max_sclk_vddc;
3107 : }
3108 0 : if (max_mclk_vddci) {
3109 0 : if (ps->performance_levels[i].mclk > max_mclk_vddci)
3110 0 : ps->performance_levels[i].mclk = max_mclk_vddci;
3111 : }
3112 0 : if (max_mclk_vddc) {
3113 0 : if (ps->performance_levels[i].mclk > max_mclk_vddc)
3114 0 : ps->performance_levels[i].mclk = max_mclk_vddc;
3115 : }
3116 0 : if (max_mclk) {
3117 0 : if (ps->performance_levels[i].mclk > max_mclk)
3118 0 : ps->performance_levels[i].mclk = max_mclk;
3119 : }
3120 0 : if (max_sclk) {
3121 0 : if (ps->performance_levels[i].sclk > max_sclk)
3122 0 : ps->performance_levels[i].sclk = max_sclk;
3123 : }
3124 : }
3125 :
3126 : /* XXX validate the min clocks required for display */
3127 :
3128 0 : if (disable_mclk_switching) {
3129 0 : mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3130 0 : vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3131 0 : } else {
3132 0 : mclk = ps->performance_levels[0].mclk;
3133 0 : vddci = ps->performance_levels[0].vddci;
3134 : }
3135 :
3136 0 : if (disable_sclk_switching) {
3137 0 : sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3138 0 : vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3139 0 : } else {
3140 0 : sclk = ps->performance_levels[0].sclk;
3141 0 : vddc = ps->performance_levels[0].vddc;
3142 : }
3143 :
3144 0 : if (rps->vce_active) {
3145 0 : if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3146 0 : sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3147 0 : if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3148 0 : mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3149 : }
3150 :
3151 : /* adjusted low state */
3152 0 : ps->performance_levels[0].sclk = sclk;
3153 0 : ps->performance_levels[0].mclk = mclk;
3154 0 : ps->performance_levels[0].vddc = vddc;
3155 0 : ps->performance_levels[0].vddci = vddci;
3156 :
3157 0 : if (disable_sclk_switching) {
3158 0 : sclk = ps->performance_levels[0].sclk;
3159 0 : for (i = 1; i < ps->performance_level_count; i++) {
3160 0 : if (sclk < ps->performance_levels[i].sclk)
3161 0 : sclk = ps->performance_levels[i].sclk;
3162 : }
3163 0 : for (i = 0; i < ps->performance_level_count; i++) {
3164 0 : ps->performance_levels[i].sclk = sclk;
3165 0 : ps->performance_levels[i].vddc = vddc;
3166 : }
3167 : } else {
3168 0 : for (i = 1; i < ps->performance_level_count; i++) {
3169 0 : if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3170 0 : ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3171 0 : if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3172 0 : ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3173 : }
3174 : }
3175 :
3176 0 : if (disable_mclk_switching) {
3177 0 : mclk = ps->performance_levels[0].mclk;
3178 0 : for (i = 1; i < ps->performance_level_count; i++) {
3179 0 : if (mclk < ps->performance_levels[i].mclk)
3180 0 : mclk = ps->performance_levels[i].mclk;
3181 : }
3182 0 : for (i = 0; i < ps->performance_level_count; i++) {
3183 0 : ps->performance_levels[i].mclk = mclk;
3184 0 : ps->performance_levels[i].vddci = vddci;
3185 : }
3186 : } else {
3187 0 : for (i = 1; i < ps->performance_level_count; i++) {
3188 0 : if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3189 0 : ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3190 0 : if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3191 0 : ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3192 : }
3193 : }
3194 :
3195 0 : for (i = 0; i < ps->performance_level_count; i++)
3196 0 : btc_adjust_clock_combinations(rdev, max_limits,
3197 0 : &ps->performance_levels[i]);
3198 :
3199 0 : for (i = 0; i < ps->performance_level_count; i++) {
3200 0 : if (ps->performance_levels[i].vddc < min_vce_voltage)
3201 0 : ps->performance_levels[i].vddc = min_vce_voltage;
3202 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3203 0 : ps->performance_levels[i].sclk,
3204 0 : max_limits->vddc, &ps->performance_levels[i].vddc);
3205 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3206 0 : ps->performance_levels[i].mclk,
3207 0 : max_limits->vddci, &ps->performance_levels[i].vddci);
3208 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3209 0 : ps->performance_levels[i].mclk,
3210 0 : max_limits->vddc, &ps->performance_levels[i].vddc);
3211 0 : btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3212 0 : rdev->clock.current_dispclk,
3213 0 : max_limits->vddc, &ps->performance_levels[i].vddc);
3214 : }
3215 :
3216 0 : for (i = 0; i < ps->performance_level_count; i++) {
3217 0 : btc_apply_voltage_delta_rules(rdev,
3218 0 : max_limits->vddc, max_limits->vddci,
3219 0 : &ps->performance_levels[i].vddc,
3220 0 : &ps->performance_levels[i].vddci);
3221 : }
3222 :
3223 0 : ps->dc_compatible = true;
3224 0 : for (i = 0; i < ps->performance_level_count; i++) {
3225 0 : if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3226 0 : ps->dc_compatible = false;
3227 : }
3228 0 : }
3229 :
3230 : #if 0
3231 : static int si_read_smc_soft_register(struct radeon_device *rdev,
3232 : u16 reg_offset, u32 *value)
3233 : {
3234 : struct si_power_info *si_pi = si_get_pi(rdev);
3235 :
3236 : return si_read_smc_sram_dword(rdev,
3237 : si_pi->soft_regs_start + reg_offset, value,
3238 : si_pi->sram_end);
3239 : }
3240 : #endif
3241 :
3242 0 : static int si_write_smc_soft_register(struct radeon_device *rdev,
3243 : u16 reg_offset, u32 value)
3244 : {
3245 0 : struct si_power_info *si_pi = si_get_pi(rdev);
3246 :
3247 0 : return si_write_smc_sram_dword(rdev,
3248 0 : si_pi->soft_regs_start + reg_offset,
3249 0 : value, si_pi->sram_end);
3250 : }
3251 :
3252 0 : static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3253 : {
3254 : bool ret = false;
3255 : u32 tmp, width, row, column, bank, density;
3256 : bool is_memory_gddr5, is_special;
3257 :
3258 0 : tmp = RREG32(MC_SEQ_MISC0);
3259 0 : is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3260 0 : is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3261 0 : & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3262 :
3263 0 : WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3264 0 : width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3265 :
3266 0 : tmp = RREG32(MC_ARB_RAMCFG);
3267 0 : row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3268 0 : column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3269 0 : bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3270 :
3271 0 : density = (1 << (row + column - 20 + bank)) * width;
3272 :
3273 0 : if ((rdev->pdev->device == 0x6819) &&
3274 0 : is_memory_gddr5 && is_special && (density == 0x400))
3275 0 : ret = true;
3276 :
3277 0 : return ret;
3278 : }
3279 :
3280 0 : static void si_get_leakage_vddc(struct radeon_device *rdev)
3281 : {
3282 0 : struct si_power_info *si_pi = si_get_pi(rdev);
3283 0 : u16 vddc, count = 0;
3284 : int i, ret;
3285 :
3286 0 : for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3287 0 : ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3288 :
3289 0 : if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3290 0 : si_pi->leakage_voltage.entries[count].voltage = vddc;
3291 0 : si_pi->leakage_voltage.entries[count].leakage_index =
3292 : SISLANDS_LEAKAGE_INDEX0 + i;
3293 0 : count++;
3294 0 : }
3295 : }
3296 0 : si_pi->leakage_voltage.count = count;
3297 0 : }
3298 :
3299 0 : static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3300 : u32 index, u16 *leakage_voltage)
3301 : {
3302 0 : struct si_power_info *si_pi = si_get_pi(rdev);
3303 : int i;
3304 :
3305 0 : if (leakage_voltage == NULL)
3306 0 : return -EINVAL;
3307 :
3308 0 : if ((index & 0xff00) != 0xff00)
3309 0 : return -EINVAL;
3310 :
3311 0 : if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3312 0 : return -EINVAL;
3313 :
3314 0 : if (index < SISLANDS_LEAKAGE_INDEX0)
3315 0 : return -EINVAL;
3316 :
3317 0 : for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3318 0 : if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3319 0 : *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3320 0 : return 0;
3321 : }
3322 : }
3323 0 : return -EAGAIN;
3324 0 : }
3325 :
3326 0 : static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3327 : {
3328 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3329 : bool want_thermal_protection;
3330 : enum radeon_dpm_event_src dpm_event_src;
3331 :
3332 0 : switch (sources) {
3333 : case 0:
3334 : default:
3335 : want_thermal_protection = false;
3336 0 : break;
3337 : case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3338 : want_thermal_protection = true;
3339 : dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3340 0 : break;
3341 : case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3342 : want_thermal_protection = true;
3343 : dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3344 0 : break;
3345 : case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3346 : (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3347 : want_thermal_protection = true;
3348 : dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3349 0 : break;
3350 : }
3351 :
3352 0 : if (want_thermal_protection) {
3353 0 : WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3354 0 : if (pi->thermal_protection)
3355 0 : WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3356 : } else {
3357 0 : WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3358 : }
3359 0 : }
3360 :
3361 0 : static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3362 : enum radeon_dpm_auto_throttle_src source,
3363 : bool enable)
3364 : {
3365 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3366 :
3367 0 : if (enable) {
3368 0 : if (!(pi->active_auto_throttle_sources & (1 << source))) {
3369 0 : pi->active_auto_throttle_sources |= 1 << source;
3370 0 : si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3371 0 : }
3372 : } else {
3373 0 : if (pi->active_auto_throttle_sources & (1 << source)) {
3374 0 : pi->active_auto_throttle_sources &= ~(1 << source);
3375 0 : si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3376 0 : }
3377 : }
3378 0 : }
3379 :
3380 0 : static void si_start_dpm(struct radeon_device *rdev)
3381 : {
3382 0 : WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3383 0 : }
3384 :
3385 0 : static void si_stop_dpm(struct radeon_device *rdev)
3386 : {
3387 0 : WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3388 0 : }
3389 :
3390 0 : static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3391 : {
3392 0 : if (enable)
3393 0 : WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3394 : else
3395 0 : WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3396 :
3397 0 : }
3398 :
3399 : #if 0
3400 : static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3401 : u32 thermal_level)
3402 : {
3403 : PPSMC_Result ret;
3404 :
3405 : if (thermal_level == 0) {
3406 : ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3407 : if (ret == PPSMC_Result_OK)
3408 : return 0;
3409 : else
3410 : return -EINVAL;
3411 : }
3412 : return 0;
3413 : }
3414 :
3415 : static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3416 : {
3417 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3418 : }
3419 : #endif
3420 :
3421 : #if 0
3422 : static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3423 : {
3424 : if (ac_power)
3425 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3426 : 0 : -EINVAL;
3427 :
3428 : return 0;
3429 : }
3430 : #endif
3431 :
3432 0 : static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3433 : PPSMC_Msg msg, u32 parameter)
3434 : {
3435 0 : WREG32(SMC_SCRATCH0, parameter);
3436 0 : return si_send_msg_to_smc(rdev, msg);
3437 : }
3438 :
3439 0 : static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3440 : {
3441 0 : if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3442 0 : return -EINVAL;
3443 :
3444 0 : return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3445 : 0 : -EINVAL;
3446 0 : }
3447 :
3448 0 : int si_dpm_force_performance_level(struct radeon_device *rdev,
3449 : enum radeon_dpm_forced_level level)
3450 : {
3451 0 : struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3452 0 : struct ni_ps *ps = ni_get_ps(rps);
3453 0 : u32 levels = ps->performance_level_count;
3454 :
3455 0 : if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3456 0 : if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3457 0 : return -EINVAL;
3458 :
3459 0 : if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3460 0 : return -EINVAL;
3461 0 : } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3462 0 : if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3463 0 : return -EINVAL;
3464 :
3465 0 : if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3466 0 : return -EINVAL;
3467 0 : } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3468 0 : if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3469 0 : return -EINVAL;
3470 :
3471 0 : if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3472 0 : return -EINVAL;
3473 : }
3474 :
3475 0 : rdev->pm.dpm.forced_level = level;
3476 :
3477 0 : return 0;
3478 0 : }
3479 :
3480 : #if 0
3481 : static int si_set_boot_state(struct radeon_device *rdev)
3482 : {
3483 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3484 : 0 : -EINVAL;
3485 : }
3486 : #endif
3487 :
3488 0 : static int si_set_sw_state(struct radeon_device *rdev)
3489 : {
3490 0 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3491 : 0 : -EINVAL;
3492 : }
3493 :
3494 0 : static int si_halt_smc(struct radeon_device *rdev)
3495 : {
3496 0 : if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3497 0 : return -EINVAL;
3498 :
3499 0 : return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3500 : 0 : -EINVAL;
3501 0 : }
3502 :
3503 0 : static int si_resume_smc(struct radeon_device *rdev)
3504 : {
3505 0 : if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3506 0 : return -EINVAL;
3507 :
3508 0 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3509 : 0 : -EINVAL;
3510 0 : }
3511 :
3512 0 : static void si_dpm_start_smc(struct radeon_device *rdev)
3513 : {
3514 0 : si_program_jump_on_start(rdev);
3515 0 : si_start_smc(rdev);
3516 0 : si_start_smc_clock(rdev);
3517 0 : }
3518 :
3519 0 : static void si_dpm_stop_smc(struct radeon_device *rdev)
3520 : {
3521 0 : si_reset_smc(rdev);
3522 0 : si_stop_smc_clock(rdev);
3523 0 : }
3524 :
3525 0 : static int si_process_firmware_header(struct radeon_device *rdev)
3526 : {
3527 0 : struct si_power_info *si_pi = si_get_pi(rdev);
3528 0 : u32 tmp;
3529 : int ret;
3530 :
3531 0 : ret = si_read_smc_sram_dword(rdev,
3532 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3533 : SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3534 0 : &tmp, si_pi->sram_end);
3535 0 : if (ret)
3536 0 : return ret;
3537 :
3538 0 : si_pi->state_table_start = tmp;
3539 :
3540 0 : ret = si_read_smc_sram_dword(rdev,
3541 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3542 : SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3543 0 : &tmp, si_pi->sram_end);
3544 0 : if (ret)
3545 0 : return ret;
3546 :
3547 0 : si_pi->soft_regs_start = tmp;
3548 :
3549 0 : ret = si_read_smc_sram_dword(rdev,
3550 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3551 : SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3552 0 : &tmp, si_pi->sram_end);
3553 0 : if (ret)
3554 0 : return ret;
3555 :
3556 0 : si_pi->mc_reg_table_start = tmp;
3557 :
3558 0 : ret = si_read_smc_sram_dword(rdev,
3559 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3560 : SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3561 0 : &tmp, si_pi->sram_end);
3562 0 : if (ret)
3563 0 : return ret;
3564 :
3565 0 : si_pi->fan_table_start = tmp;
3566 :
3567 0 : ret = si_read_smc_sram_dword(rdev,
3568 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3569 : SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3570 0 : &tmp, si_pi->sram_end);
3571 0 : if (ret)
3572 0 : return ret;
3573 :
3574 0 : si_pi->arb_table_start = tmp;
3575 :
3576 0 : ret = si_read_smc_sram_dword(rdev,
3577 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3578 : SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3579 0 : &tmp, si_pi->sram_end);
3580 0 : if (ret)
3581 0 : return ret;
3582 :
3583 0 : si_pi->cac_table_start = tmp;
3584 :
3585 0 : ret = si_read_smc_sram_dword(rdev,
3586 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3587 : SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3588 0 : &tmp, si_pi->sram_end);
3589 0 : if (ret)
3590 0 : return ret;
3591 :
3592 0 : si_pi->dte_table_start = tmp;
3593 :
3594 0 : ret = si_read_smc_sram_dword(rdev,
3595 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3596 : SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3597 0 : &tmp, si_pi->sram_end);
3598 0 : if (ret)
3599 0 : return ret;
3600 :
3601 0 : si_pi->spll_table_start = tmp;
3602 :
3603 0 : ret = si_read_smc_sram_dword(rdev,
3604 : SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3605 : SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3606 0 : &tmp, si_pi->sram_end);
3607 0 : if (ret)
3608 0 : return ret;
3609 :
3610 0 : si_pi->papm_cfg_table_start = tmp;
3611 :
3612 0 : return ret;
3613 0 : }
3614 :
3615 0 : static void si_read_clock_registers(struct radeon_device *rdev)
3616 : {
3617 0 : struct si_power_info *si_pi = si_get_pi(rdev);
3618 :
3619 0 : si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3620 0 : si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3621 0 : si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3622 0 : si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3623 0 : si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3624 0 : si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3625 0 : si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3626 0 : si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3627 0 : si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3628 0 : si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3629 0 : si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3630 0 : si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3631 0 : si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3632 0 : si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3633 0 : si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3634 0 : }
3635 :
3636 0 : static void si_enable_thermal_protection(struct radeon_device *rdev,
3637 : bool enable)
3638 : {
3639 0 : if (enable)
3640 0 : WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3641 : else
3642 0 : WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3643 0 : }
3644 :
3645 0 : static void si_enable_acpi_power_management(struct radeon_device *rdev)
3646 : {
3647 0 : WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3648 0 : }
3649 :
3650 : #if 0
3651 : static int si_enter_ulp_state(struct radeon_device *rdev)
3652 : {
3653 : WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3654 :
3655 : udelay(25000);
3656 :
3657 : return 0;
3658 : }
3659 :
3660 : static int si_exit_ulp_state(struct radeon_device *rdev)
3661 : {
3662 : int i;
3663 :
3664 : WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3665 :
3666 : udelay(7000);
3667 :
3668 : for (i = 0; i < rdev->usec_timeout; i++) {
3669 : if (RREG32(SMC_RESP_0) == 1)
3670 : break;
3671 : udelay(1000);
3672 : }
3673 :
3674 : return 0;
3675 : }
3676 : #endif
3677 :
3678 0 : static int si_notify_smc_display_change(struct radeon_device *rdev,
3679 : bool has_display)
3680 : {
3681 0 : PPSMC_Msg msg = has_display ?
3682 : PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3683 :
3684 0 : return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3685 : 0 : -EINVAL;
3686 : }
3687 :
3688 0 : static void si_program_response_times(struct radeon_device *rdev)
3689 : {
3690 : u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3691 : u32 vddc_dly, acpi_dly, vbi_dly;
3692 : u32 reference_clock;
3693 :
3694 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3695 :
3696 0 : voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3697 0 : backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3698 :
3699 0 : if (voltage_response_time == 0)
3700 0 : voltage_response_time = 1000;
3701 :
3702 : acpi_delay_time = 15000;
3703 : vbi_time_out = 100000;
3704 :
3705 0 : reference_clock = radeon_get_xclk(rdev);
3706 :
3707 0 : vddc_dly = (voltage_response_time * reference_clock) / 100;
3708 0 : acpi_dly = (acpi_delay_time * reference_clock) / 100;
3709 0 : vbi_dly = (vbi_time_out * reference_clock) / 100;
3710 :
3711 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3712 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3713 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3714 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3715 0 : }
3716 :
3717 0 : static void si_program_ds_registers(struct radeon_device *rdev)
3718 : {
3719 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3720 : u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3721 :
3722 0 : if (eg_pi->sclk_deep_sleep) {
3723 0 : WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3724 0 : WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3725 : ~AUTOSCALE_ON_SS_CLEAR);
3726 0 : }
3727 0 : }
3728 :
3729 0 : static void si_program_display_gap(struct radeon_device *rdev)
3730 : {
3731 : u32 tmp, pipe;
3732 : int i;
3733 :
3734 0 : tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3735 0 : if (rdev->pm.dpm.new_active_crtc_count > 0)
3736 0 : tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3737 : else
3738 0 : tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3739 :
3740 0 : if (rdev->pm.dpm.new_active_crtc_count > 1)
3741 0 : tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3742 : else
3743 0 : tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3744 :
3745 0 : WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3746 :
3747 0 : tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3748 0 : pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3749 :
3750 0 : if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3751 0 : (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3752 : /* find the first active crtc */
3753 0 : for (i = 0; i < rdev->num_crtc; i++) {
3754 0 : if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3755 : break;
3756 : }
3757 0 : if (i == rdev->num_crtc)
3758 0 : pipe = 0;
3759 : else
3760 : pipe = i;
3761 :
3762 0 : tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3763 0 : tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3764 0 : WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3765 0 : }
3766 :
3767 : /* Setting this to false forces the performance state to low if the crtcs are disabled.
3768 : * This can be a problem on PowerXpress systems or if you want to use the card
3769 : * for offscreen rendering or compute if there are no crtcs enabled.
3770 : */
3771 0 : si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3772 0 : }
3773 :
3774 0 : static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3775 : {
3776 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3777 :
3778 0 : if (enable) {
3779 0 : if (pi->sclk_ss)
3780 0 : WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3781 : } else {
3782 0 : WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3783 0 : WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3784 : }
3785 0 : }
3786 :
3787 0 : static void si_setup_bsp(struct radeon_device *rdev)
3788 : {
3789 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3790 0 : u32 xclk = radeon_get_xclk(rdev);
3791 :
3792 0 : r600_calculate_u_and_p(pi->asi,
3793 : xclk,
3794 : 16,
3795 0 : &pi->bsp,
3796 0 : &pi->bsu);
3797 :
3798 0 : r600_calculate_u_and_p(pi->pasi,
3799 : xclk,
3800 : 16,
3801 0 : &pi->pbsp,
3802 0 : &pi->pbsu);
3803 :
3804 :
3805 0 : pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3806 0 : pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3807 :
3808 0 : WREG32(CG_BSP, pi->dsp);
3809 0 : }
3810 :
3811 0 : static void si_program_git(struct radeon_device *rdev)
3812 : {
3813 0 : WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3814 0 : }
3815 :
3816 0 : static void si_program_tp(struct radeon_device *rdev)
3817 : {
3818 : int i;
3819 : enum r600_td td = R600_TD_DFLT;
3820 :
3821 0 : for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3822 0 : WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3823 :
3824 0 : if (td == R600_TD_AUTO)
3825 0 : WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3826 : else
3827 0 : WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3828 :
3829 0 : if (td == R600_TD_UP)
3830 0 : WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3831 :
3832 0 : if (td == R600_TD_DOWN)
3833 0 : WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3834 0 : }
3835 :
3836 0 : static void si_program_tpp(struct radeon_device *rdev)
3837 : {
3838 0 : WREG32(CG_TPC, R600_TPC_DFLT);
3839 0 : }
3840 :
3841 0 : static void si_program_sstp(struct radeon_device *rdev)
3842 : {
3843 0 : WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3844 0 : }
3845 :
3846 0 : static void si_enable_display_gap(struct radeon_device *rdev)
3847 : {
3848 0 : u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3849 :
3850 0 : tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3851 0 : tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3852 : DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3853 :
3854 0 : tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3855 0 : tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3856 : DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3857 0 : WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3858 0 : }
3859 :
3860 0 : static void si_program_vc(struct radeon_device *rdev)
3861 : {
3862 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3863 :
3864 0 : WREG32(CG_FTV, pi->vrc);
3865 0 : }
3866 :
3867 0 : static void si_clear_vc(struct radeon_device *rdev)
3868 : {
3869 0 : WREG32(CG_FTV, 0);
3870 0 : }
3871 :
3872 0 : u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3873 : {
3874 : u8 mc_para_index;
3875 :
3876 0 : if (memory_clock < 10000)
3877 0 : mc_para_index = 0;
3878 0 : else if (memory_clock >= 80000)
3879 0 : mc_para_index = 0x0f;
3880 : else
3881 0 : mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3882 0 : return mc_para_index;
3883 : }
3884 :
3885 0 : u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3886 : {
3887 : u8 mc_para_index;
3888 :
3889 0 : if (strobe_mode) {
3890 0 : if (memory_clock < 12500)
3891 0 : mc_para_index = 0x00;
3892 0 : else if (memory_clock > 47500)
3893 0 : mc_para_index = 0x0f;
3894 : else
3895 0 : mc_para_index = (u8)((memory_clock - 10000) / 2500);
3896 : } else {
3897 0 : if (memory_clock < 65000)
3898 0 : mc_para_index = 0x00;
3899 0 : else if (memory_clock > 135000)
3900 0 : mc_para_index = 0x0f;
3901 : else
3902 0 : mc_para_index = (u8)((memory_clock - 60000) / 5000);
3903 : }
3904 0 : return mc_para_index;
3905 : }
3906 :
3907 0 : static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3908 : {
3909 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3910 : bool strobe_mode = false;
3911 : u8 result = 0;
3912 :
3913 0 : if (mclk <= pi->mclk_strobe_mode_threshold)
3914 0 : strobe_mode = true;
3915 :
3916 0 : if (pi->mem_gddr5)
3917 0 : result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3918 : else
3919 0 : result = si_get_ddr3_mclk_frequency_ratio(mclk);
3920 :
3921 0 : if (strobe_mode)
3922 0 : result |= SISLANDS_SMC_STROBE_ENABLE;
3923 :
3924 0 : return result;
3925 : }
3926 :
3927 0 : static int si_upload_firmware(struct radeon_device *rdev)
3928 : {
3929 0 : struct si_power_info *si_pi = si_get_pi(rdev);
3930 : int ret;
3931 :
3932 0 : si_reset_smc(rdev);
3933 0 : si_stop_smc_clock(rdev);
3934 :
3935 0 : ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3936 :
3937 0 : return ret;
3938 : }
3939 :
3940 0 : static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3941 : const struct atom_voltage_table *table,
3942 : const struct radeon_phase_shedding_limits_table *limits)
3943 : {
3944 : u32 data, num_bits, num_levels;
3945 :
3946 0 : if ((table == NULL) || (limits == NULL))
3947 0 : return false;
3948 :
3949 0 : data = table->mask_low;
3950 :
3951 0 : num_bits = hweight32(data);
3952 :
3953 0 : if (num_bits == 0)
3954 0 : return false;
3955 :
3956 0 : num_levels = (1 << num_bits);
3957 :
3958 0 : if (table->count != num_levels)
3959 0 : return false;
3960 :
3961 0 : if (limits->count != (num_levels - 1))
3962 0 : return false;
3963 :
3964 0 : return true;
3965 0 : }
3966 :
3967 0 : void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3968 : u32 max_voltage_steps,
3969 : struct atom_voltage_table *voltage_table)
3970 : {
3971 : unsigned int i, diff;
3972 :
3973 0 : if (voltage_table->count <= max_voltage_steps)
3974 0 : return;
3975 :
3976 0 : diff = voltage_table->count - max_voltage_steps;
3977 :
3978 0 : for (i= 0; i < max_voltage_steps; i++)
3979 0 : voltage_table->entries[i] = voltage_table->entries[i + diff];
3980 :
3981 0 : voltage_table->count = max_voltage_steps;
3982 0 : }
3983 :
3984 0 : static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3985 : struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
3986 : struct atom_voltage_table *voltage_table)
3987 : {
3988 : u32 i;
3989 :
3990 0 : if (voltage_dependency_table == NULL)
3991 0 : return -EINVAL;
3992 :
3993 0 : voltage_table->mask_low = 0;
3994 0 : voltage_table->phase_delay = 0;
3995 :
3996 0 : voltage_table->count = voltage_dependency_table->count;
3997 0 : for (i = 0; i < voltage_table->count; i++) {
3998 0 : voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
3999 0 : voltage_table->entries[i].smio_low = 0;
4000 : }
4001 :
4002 0 : return 0;
4003 0 : }
4004 :
4005 0 : static int si_construct_voltage_tables(struct radeon_device *rdev)
4006 : {
4007 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4008 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4009 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4010 : int ret;
4011 :
4012 0 : if (pi->voltage_control) {
4013 0 : ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4014 0 : VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4015 0 : if (ret)
4016 0 : return ret;
4017 :
4018 0 : if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4019 0 : si_trim_voltage_table_to_fit_state_table(rdev,
4020 : SISLANDS_MAX_NO_VREG_STEPS,
4021 : &eg_pi->vddc_voltage_table);
4022 0 : } else if (si_pi->voltage_control_svi2) {
4023 0 : ret = si_get_svi2_voltage_table(rdev,
4024 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4025 0 : &eg_pi->vddc_voltage_table);
4026 0 : if (ret)
4027 0 : return ret;
4028 : } else {
4029 0 : return -EINVAL;
4030 : }
4031 :
4032 0 : if (eg_pi->vddci_control) {
4033 0 : ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
4034 0 : VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4035 0 : if (ret)
4036 0 : return ret;
4037 :
4038 0 : if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4039 0 : si_trim_voltage_table_to_fit_state_table(rdev,
4040 : SISLANDS_MAX_NO_VREG_STEPS,
4041 : &eg_pi->vddci_voltage_table);
4042 : }
4043 0 : if (si_pi->vddci_control_svi2) {
4044 0 : ret = si_get_svi2_voltage_table(rdev,
4045 0 : &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4046 0 : &eg_pi->vddci_voltage_table);
4047 0 : if (ret)
4048 0 : return ret;
4049 : }
4050 :
4051 0 : if (pi->mvdd_control) {
4052 0 : ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
4053 0 : VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4054 :
4055 0 : if (ret) {
4056 0 : pi->mvdd_control = false;
4057 0 : return ret;
4058 : }
4059 :
4060 0 : if (si_pi->mvdd_voltage_table.count == 0) {
4061 0 : pi->mvdd_control = false;
4062 0 : return -EINVAL;
4063 : }
4064 :
4065 0 : if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4066 0 : si_trim_voltage_table_to_fit_state_table(rdev,
4067 : SISLANDS_MAX_NO_VREG_STEPS,
4068 : &si_pi->mvdd_voltage_table);
4069 : }
4070 :
4071 0 : if (si_pi->vddc_phase_shed_control) {
4072 0 : ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4073 0 : VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4074 0 : if (ret)
4075 0 : si_pi->vddc_phase_shed_control = false;
4076 :
4077 0 : if ((si_pi->vddc_phase_shed_table.count == 0) ||
4078 0 : (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4079 0 : si_pi->vddc_phase_shed_control = false;
4080 : }
4081 :
4082 0 : return 0;
4083 0 : }
4084 :
4085 0 : static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4086 : const struct atom_voltage_table *voltage_table,
4087 : SISLANDS_SMC_STATETABLE *table)
4088 : {
4089 : unsigned int i;
4090 :
4091 0 : for (i = 0; i < voltage_table->count; i++)
4092 0 : table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4093 0 : }
4094 :
4095 0 : static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4096 : SISLANDS_SMC_STATETABLE *table)
4097 : {
4098 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4099 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4100 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4101 : u8 i;
4102 :
4103 0 : if (si_pi->voltage_control_svi2) {
4104 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4105 0 : si_pi->svc_gpio_id);
4106 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4107 0 : si_pi->svd_gpio_id);
4108 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4109 : 2);
4110 0 : } else {
4111 0 : if (eg_pi->vddc_voltage_table.count) {
4112 0 : si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4113 0 : table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4114 0 : cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4115 :
4116 0 : for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4117 0 : if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4118 0 : table->maxVDDCIndexInPPTable = i;
4119 0 : break;
4120 : }
4121 : }
4122 : }
4123 :
4124 0 : if (eg_pi->vddci_voltage_table.count) {
4125 0 : si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4126 :
4127 0 : table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4128 0 : cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4129 0 : }
4130 :
4131 :
4132 0 : if (si_pi->mvdd_voltage_table.count) {
4133 0 : si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4134 :
4135 0 : table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4136 0 : cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4137 0 : }
4138 :
4139 0 : if (si_pi->vddc_phase_shed_control) {
4140 0 : if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4141 0 : &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4142 0 : si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4143 :
4144 0 : table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4145 0 : cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4146 :
4147 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4148 0 : (u32)si_pi->vddc_phase_shed_table.phase_delay);
4149 0 : } else {
4150 0 : si_pi->vddc_phase_shed_control = false;
4151 : }
4152 : }
4153 : }
4154 :
4155 0 : return 0;
4156 : }
4157 :
4158 0 : static int si_populate_voltage_value(struct radeon_device *rdev,
4159 : const struct atom_voltage_table *table,
4160 : u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4161 : {
4162 : unsigned int i;
4163 :
4164 0 : for (i = 0; i < table->count; i++) {
4165 0 : if (value <= table->entries[i].value) {
4166 0 : voltage->index = (u8)i;
4167 0 : voltage->value = cpu_to_be16(table->entries[i].value);
4168 0 : break;
4169 : }
4170 : }
4171 :
4172 0 : if (i >= table->count)
4173 0 : return -EINVAL;
4174 :
4175 0 : return 0;
4176 0 : }
4177 :
4178 0 : static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4179 : SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4180 : {
4181 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4182 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4183 :
4184 0 : if (pi->mvdd_control) {
4185 0 : if (mclk <= pi->mvdd_split_frequency)
4186 0 : voltage->index = 0;
4187 : else
4188 0 : voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4189 :
4190 0 : voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4191 0 : }
4192 0 : return 0;
4193 : }
4194 :
4195 0 : static int si_get_std_voltage_value(struct radeon_device *rdev,
4196 : SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4197 : u16 *std_voltage)
4198 : {
4199 : u16 v_index;
4200 : bool voltage_found = false;
4201 0 : *std_voltage = be16_to_cpu(voltage->value);
4202 :
4203 0 : if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4204 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4205 0 : if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4206 0 : return -EINVAL;
4207 :
4208 0 : for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4209 0 : if (be16_to_cpu(voltage->value) ==
4210 0 : (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4211 : voltage_found = true;
4212 0 : if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4213 0 : *std_voltage =
4214 0 : rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4215 : else
4216 0 : *std_voltage =
4217 0 : rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4218 : break;
4219 : }
4220 : }
4221 :
4222 0 : if (!voltage_found) {
4223 0 : for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4224 0 : if (be16_to_cpu(voltage->value) <=
4225 0 : (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4226 : voltage_found = true;
4227 0 : if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4228 0 : *std_voltage =
4229 0 : rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4230 : else
4231 0 : *std_voltage =
4232 0 : rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4233 : break;
4234 : }
4235 : }
4236 : }
4237 : } else {
4238 0 : if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4239 0 : *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4240 : }
4241 : }
4242 :
4243 0 : return 0;
4244 0 : }
4245 :
4246 0 : static int si_populate_std_voltage_value(struct radeon_device *rdev,
4247 : u16 value, u8 index,
4248 : SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4249 : {
4250 0 : voltage->index = index;
4251 0 : voltage->value = cpu_to_be16(value);
4252 :
4253 0 : return 0;
4254 : }
4255 :
4256 0 : static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4257 : const struct radeon_phase_shedding_limits_table *limits,
4258 : u16 voltage, u32 sclk, u32 mclk,
4259 : SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4260 : {
4261 : unsigned int i;
4262 :
4263 0 : for (i = 0; i < limits->count; i++) {
4264 0 : if ((voltage <= limits->entries[i].voltage) &&
4265 0 : (sclk <= limits->entries[i].sclk) &&
4266 0 : (mclk <= limits->entries[i].mclk))
4267 : break;
4268 : }
4269 :
4270 0 : smc_voltage->phase_settings = (u8)i;
4271 :
4272 0 : return 0;
4273 : }
4274 :
4275 0 : static int si_init_arb_table_index(struct radeon_device *rdev)
4276 : {
4277 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4278 0 : u32 tmp;
4279 : int ret;
4280 :
4281 0 : ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4282 0 : if (ret)
4283 0 : return ret;
4284 :
4285 0 : tmp &= 0x00FFFFFF;
4286 0 : tmp |= MC_CG_ARB_FREQ_F1 << 24;
4287 :
4288 0 : return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4289 0 : }
4290 :
4291 0 : static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4292 : {
4293 0 : return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4294 : }
4295 :
4296 0 : static int si_reset_to_default(struct radeon_device *rdev)
4297 : {
4298 0 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4299 : 0 : -EINVAL;
4300 : }
4301 :
4302 0 : static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4303 : {
4304 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4305 0 : u32 tmp;
4306 : int ret;
4307 :
4308 0 : ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4309 0 : &tmp, si_pi->sram_end);
4310 0 : if (ret)
4311 0 : return ret;
4312 :
4313 0 : tmp = (tmp >> 24) & 0xff;
4314 :
4315 0 : if (tmp == MC_CG_ARB_FREQ_F0)
4316 0 : return 0;
4317 :
4318 0 : return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4319 0 : }
4320 :
4321 0 : static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4322 : u32 engine_clock)
4323 : {
4324 : u32 dram_rows;
4325 : u32 dram_refresh_rate;
4326 : u32 mc_arb_rfsh_rate;
4327 0 : u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4328 :
4329 0 : if (tmp >= 4)
4330 0 : dram_rows = 16384;
4331 : else
4332 0 : dram_rows = 1 << (tmp + 10);
4333 :
4334 0 : dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4335 0 : mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4336 :
4337 0 : return mc_arb_rfsh_rate;
4338 : }
4339 :
4340 0 : static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4341 : struct rv7xx_pl *pl,
4342 : SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4343 : {
4344 : u32 dram_timing;
4345 : u32 dram_timing2;
4346 : u32 burst_time;
4347 :
4348 0 : arb_regs->mc_arb_rfsh_rate =
4349 0 : (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4350 :
4351 0 : radeon_atom_set_engine_dram_timings(rdev,
4352 0 : pl->sclk,
4353 0 : pl->mclk);
4354 :
4355 0 : dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4356 0 : dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4357 0 : burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4358 :
4359 0 : arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4360 0 : arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4361 0 : arb_regs->mc_arb_burst_time = (u8)burst_time;
4362 :
4363 0 : return 0;
4364 : }
4365 :
4366 0 : static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4367 : struct radeon_ps *radeon_state,
4368 : unsigned int first_arb_set)
4369 : {
4370 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4371 0 : struct ni_ps *state = ni_get_ps(radeon_state);
4372 0 : SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4373 : int i, ret = 0;
4374 :
4375 0 : for (i = 0; i < state->performance_level_count; i++) {
4376 0 : ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4377 0 : if (ret)
4378 : break;
4379 0 : ret = si_copy_bytes_to_smc(rdev,
4380 0 : si_pi->arb_table_start +
4381 0 : offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4382 0 : sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4383 : (u8 *)&arb_regs,
4384 : sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4385 0 : si_pi->sram_end);
4386 0 : if (ret)
4387 : break;
4388 : }
4389 :
4390 0 : return ret;
4391 0 : }
4392 :
4393 0 : static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4394 : struct radeon_ps *radeon_new_state)
4395 : {
4396 0 : return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4397 : SISLANDS_DRIVER_STATE_ARB_INDEX);
4398 : }
4399 :
4400 0 : static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4401 : struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4402 : {
4403 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4404 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4405 :
4406 0 : if (pi->mvdd_control)
4407 0 : return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4408 0 : si_pi->mvdd_bootup_value, voltage);
4409 :
4410 0 : return 0;
4411 0 : }
4412 :
4413 0 : static int si_populate_smc_initial_state(struct radeon_device *rdev,
4414 : struct radeon_ps *radeon_initial_state,
4415 : SISLANDS_SMC_STATETABLE *table)
4416 : {
4417 0 : struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4418 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4419 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4420 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4421 : u32 reg;
4422 : int ret;
4423 :
4424 0 : table->initialState.levels[0].mclk.vDLL_CNTL =
4425 0 : cpu_to_be32(si_pi->clock_registers.dll_cntl);
4426 0 : table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4427 0 : cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4428 0 : table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4429 0 : cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4430 0 : table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4431 0 : cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4432 0 : table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4433 0 : cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4434 0 : table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4435 0 : cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4436 0 : table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4437 0 : cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4438 0 : table->initialState.levels[0].mclk.vMPLL_SS =
4439 0 : cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4440 0 : table->initialState.levels[0].mclk.vMPLL_SS2 =
4441 0 : cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4442 :
4443 0 : table->initialState.levels[0].mclk.mclk_value =
4444 0 : cpu_to_be32(initial_state->performance_levels[0].mclk);
4445 :
4446 0 : table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4447 0 : cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4448 0 : table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4449 0 : cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4450 0 : table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4451 0 : cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4452 0 : table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4453 0 : cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4454 0 : table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4455 0 : cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4456 0 : table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4457 0 : cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4458 :
4459 0 : table->initialState.levels[0].sclk.sclk_value =
4460 0 : cpu_to_be32(initial_state->performance_levels[0].sclk);
4461 :
4462 0 : table->initialState.levels[0].arbRefreshState =
4463 : SISLANDS_INITIAL_STATE_ARB_INDEX;
4464 :
4465 0 : table->initialState.levels[0].ACIndex = 0;
4466 :
4467 0 : ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4468 0 : initial_state->performance_levels[0].vddc,
4469 0 : &table->initialState.levels[0].vddc);
4470 :
4471 0 : if (!ret) {
4472 0 : u16 std_vddc;
4473 :
4474 0 : ret = si_get_std_voltage_value(rdev,
4475 : &table->initialState.levels[0].vddc,
4476 : &std_vddc);
4477 0 : if (!ret)
4478 0 : si_populate_std_voltage_value(rdev, std_vddc,
4479 0 : table->initialState.levels[0].vddc.index,
4480 0 : &table->initialState.levels[0].std_vddc);
4481 0 : }
4482 :
4483 0 : if (eg_pi->vddci_control)
4484 0 : si_populate_voltage_value(rdev,
4485 0 : &eg_pi->vddci_voltage_table,
4486 0 : initial_state->performance_levels[0].vddci,
4487 0 : &table->initialState.levels[0].vddci);
4488 :
4489 0 : if (si_pi->vddc_phase_shed_control)
4490 0 : si_populate_phase_shedding_value(rdev,
4491 0 : &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4492 0 : initial_state->performance_levels[0].vddc,
4493 0 : initial_state->performance_levels[0].sclk,
4494 0 : initial_state->performance_levels[0].mclk,
4495 : &table->initialState.levels[0].vddc);
4496 :
4497 0 : si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4498 :
4499 : reg = CG_R(0xffff) | CG_L(0);
4500 0 : table->initialState.levels[0].aT = cpu_to_be32(reg);
4501 :
4502 0 : table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4503 :
4504 0 : table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4505 :
4506 0 : if (pi->mem_gddr5) {
4507 0 : table->initialState.levels[0].strobeMode =
4508 0 : si_get_strobe_mode_settings(rdev,
4509 0 : initial_state->performance_levels[0].mclk);
4510 :
4511 0 : if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4512 0 : table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4513 : else
4514 0 : table->initialState.levels[0].mcFlags = 0;
4515 : }
4516 :
4517 0 : table->initialState.levelCount = 1;
4518 :
4519 0 : table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4520 :
4521 0 : table->initialState.levels[0].dpm2.MaxPS = 0;
4522 0 : table->initialState.levels[0].dpm2.NearTDPDec = 0;
4523 0 : table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4524 0 : table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4525 0 : table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4526 :
4527 : reg = MIN_POWER_MASK | MAX_POWER_MASK;
4528 0 : table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4529 :
4530 : reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4531 0 : table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4532 :
4533 0 : return 0;
4534 : }
4535 :
4536 0 : static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4537 : SISLANDS_SMC_STATETABLE *table)
4538 : {
4539 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4540 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4541 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4542 0 : u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4543 0 : u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4544 0 : u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4545 0 : u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4546 0 : u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4547 0 : u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4548 0 : u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4549 0 : u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4550 0 : u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4551 0 : u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4552 0 : u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4553 : u32 reg;
4554 : int ret;
4555 :
4556 0 : table->ACPIState = table->initialState;
4557 :
4558 0 : table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4559 :
4560 0 : if (pi->acpi_vddc) {
4561 0 : ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4562 0 : pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4563 0 : if (!ret) {
4564 0 : u16 std_vddc;
4565 :
4566 0 : ret = si_get_std_voltage_value(rdev,
4567 : &table->ACPIState.levels[0].vddc, &std_vddc);
4568 0 : if (!ret)
4569 0 : si_populate_std_voltage_value(rdev, std_vddc,
4570 0 : table->ACPIState.levels[0].vddc.index,
4571 0 : &table->ACPIState.levels[0].std_vddc);
4572 0 : }
4573 0 : table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4574 :
4575 0 : if (si_pi->vddc_phase_shed_control) {
4576 0 : si_populate_phase_shedding_value(rdev,
4577 0 : &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4578 0 : pi->acpi_vddc,
4579 : 0,
4580 : 0,
4581 : &table->ACPIState.levels[0].vddc);
4582 0 : }
4583 : } else {
4584 0 : ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4585 0 : pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4586 0 : if (!ret) {
4587 0 : u16 std_vddc;
4588 :
4589 0 : ret = si_get_std_voltage_value(rdev,
4590 : &table->ACPIState.levels[0].vddc, &std_vddc);
4591 :
4592 0 : if (!ret)
4593 0 : si_populate_std_voltage_value(rdev, std_vddc,
4594 0 : table->ACPIState.levels[0].vddc.index,
4595 0 : &table->ACPIState.levels[0].std_vddc);
4596 0 : }
4597 0 : table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4598 0 : si_pi->sys_pcie_mask,
4599 0 : si_pi->boot_pcie_gen,
4600 : RADEON_PCIE_GEN1);
4601 :
4602 0 : if (si_pi->vddc_phase_shed_control)
4603 0 : si_populate_phase_shedding_value(rdev,
4604 0 : &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4605 0 : pi->min_vddc_in_table,
4606 : 0,
4607 : 0,
4608 : &table->ACPIState.levels[0].vddc);
4609 : }
4610 :
4611 0 : if (pi->acpi_vddc) {
4612 0 : if (eg_pi->acpi_vddci)
4613 0 : si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4614 : eg_pi->acpi_vddci,
4615 0 : &table->ACPIState.levels[0].vddci);
4616 : }
4617 :
4618 0 : mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4619 0 : mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4620 :
4621 0 : dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4622 :
4623 0 : spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4624 0 : spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4625 :
4626 0 : table->ACPIState.levels[0].mclk.vDLL_CNTL =
4627 0 : cpu_to_be32(dll_cntl);
4628 0 : table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4629 0 : cpu_to_be32(mclk_pwrmgt_cntl);
4630 0 : table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4631 0 : cpu_to_be32(mpll_ad_func_cntl);
4632 0 : table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4633 0 : cpu_to_be32(mpll_dq_func_cntl);
4634 0 : table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4635 0 : cpu_to_be32(mpll_func_cntl);
4636 0 : table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4637 0 : cpu_to_be32(mpll_func_cntl_1);
4638 0 : table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4639 0 : cpu_to_be32(mpll_func_cntl_2);
4640 0 : table->ACPIState.levels[0].mclk.vMPLL_SS =
4641 0 : cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4642 0 : table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4643 0 : cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4644 :
4645 0 : table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4646 0 : cpu_to_be32(spll_func_cntl);
4647 0 : table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4648 0 : cpu_to_be32(spll_func_cntl_2);
4649 0 : table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4650 0 : cpu_to_be32(spll_func_cntl_3);
4651 0 : table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4652 0 : cpu_to_be32(spll_func_cntl_4);
4653 :
4654 0 : table->ACPIState.levels[0].mclk.mclk_value = 0;
4655 0 : table->ACPIState.levels[0].sclk.sclk_value = 0;
4656 :
4657 0 : si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4658 :
4659 0 : if (eg_pi->dynamic_ac_timing)
4660 0 : table->ACPIState.levels[0].ACIndex = 0;
4661 :
4662 0 : table->ACPIState.levels[0].dpm2.MaxPS = 0;
4663 0 : table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4664 0 : table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4665 0 : table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4666 0 : table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4667 :
4668 : reg = MIN_POWER_MASK | MAX_POWER_MASK;
4669 0 : table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4670 :
4671 : reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4672 0 : table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4673 :
4674 0 : return 0;
4675 : }
4676 :
4677 0 : static int si_populate_ulv_state(struct radeon_device *rdev,
4678 : SISLANDS_SMC_SWSTATE *state)
4679 : {
4680 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4681 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4682 0 : struct si_ulv_param *ulv = &si_pi->ulv;
4683 : u32 sclk_in_sr = 1350; /* ??? */
4684 : int ret;
4685 :
4686 0 : ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4687 0 : &state->levels[0]);
4688 0 : if (!ret) {
4689 0 : if (eg_pi->sclk_deep_sleep) {
4690 0 : if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4691 0 : state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4692 : else
4693 0 : state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4694 : }
4695 0 : if (ulv->one_pcie_lane_in_ulv)
4696 0 : state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4697 0 : state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4698 0 : state->levels[0].ACIndex = 1;
4699 0 : state->levels[0].std_vddc = state->levels[0].vddc;
4700 0 : state->levelCount = 1;
4701 :
4702 0 : state->flags |= PPSMC_SWSTATE_FLAG_DC;
4703 0 : }
4704 :
4705 0 : return ret;
4706 : }
4707 :
4708 0 : static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4709 : {
4710 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4711 0 : struct si_ulv_param *ulv = &si_pi->ulv;
4712 0 : SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4713 : int ret;
4714 :
4715 0 : ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4716 : &arb_regs);
4717 0 : if (ret)
4718 0 : return ret;
4719 :
4720 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4721 0 : ulv->volt_change_delay);
4722 :
4723 0 : ret = si_copy_bytes_to_smc(rdev,
4724 0 : si_pi->arb_table_start +
4725 0 : offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4726 : sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4727 : (u8 *)&arb_regs,
4728 : sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4729 0 : si_pi->sram_end);
4730 :
4731 0 : return ret;
4732 0 : }
4733 :
4734 0 : static void si_get_mvdd_configuration(struct radeon_device *rdev)
4735 : {
4736 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4737 :
4738 0 : pi->mvdd_split_frequency = 30000;
4739 0 : }
4740 :
4741 0 : static int si_init_smc_table(struct radeon_device *rdev)
4742 : {
4743 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4744 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4745 0 : struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4746 0 : const struct si_ulv_param *ulv = &si_pi->ulv;
4747 0 : SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
4748 : int ret;
4749 : u32 lane_width;
4750 : u32 vr_hot_gpio;
4751 :
4752 0 : si_populate_smc_voltage_tables(rdev, table);
4753 :
4754 0 : switch (rdev->pm.int_thermal_type) {
4755 : case THERMAL_TYPE_SI:
4756 : case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4757 0 : table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4758 0 : break;
4759 : case THERMAL_TYPE_NONE:
4760 0 : table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4761 0 : break;
4762 : default:
4763 0 : table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4764 0 : break;
4765 : }
4766 :
4767 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4768 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4769 :
4770 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4771 0 : if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4772 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4773 : }
4774 :
4775 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4776 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4777 :
4778 0 : if (pi->mem_gddr5)
4779 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4780 :
4781 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4782 0 : table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4783 :
4784 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4785 0 : table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4786 0 : vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4787 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4788 : vr_hot_gpio);
4789 0 : }
4790 :
4791 0 : ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4792 0 : if (ret)
4793 0 : return ret;
4794 :
4795 0 : ret = si_populate_smc_acpi_state(rdev, table);
4796 0 : if (ret)
4797 0 : return ret;
4798 :
4799 0 : table->driverState = table->initialState;
4800 :
4801 0 : ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4802 : SISLANDS_INITIAL_STATE_ARB_INDEX);
4803 0 : if (ret)
4804 0 : return ret;
4805 :
4806 0 : if (ulv->supported && ulv->pl.vddc) {
4807 0 : ret = si_populate_ulv_state(rdev, &table->ULVState);
4808 0 : if (ret)
4809 0 : return ret;
4810 :
4811 0 : ret = si_program_ulv_memory_timing_parameters(rdev);
4812 0 : if (ret)
4813 0 : return ret;
4814 :
4815 0 : WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4816 0 : WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4817 :
4818 0 : lane_width = radeon_get_pcie_lanes(rdev);
4819 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4820 0 : } else {
4821 0 : table->ULVState = table->initialState;
4822 : }
4823 :
4824 0 : return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4825 0 : (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4826 0 : si_pi->sram_end);
4827 0 : }
4828 :
4829 0 : static int si_calculate_sclk_params(struct radeon_device *rdev,
4830 : u32 engine_clock,
4831 : SISLANDS_SMC_SCLK_VALUE *sclk)
4832 : {
4833 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4834 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4835 0 : struct atom_clock_dividers dividers;
4836 0 : u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4837 0 : u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4838 0 : u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4839 0 : u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4840 0 : u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4841 0 : u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4842 : u64 tmp;
4843 0 : u32 reference_clock = rdev->clock.spll.reference_freq;
4844 : u32 reference_divider;
4845 : u32 fbdiv;
4846 : int ret;
4847 :
4848 0 : ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4849 : engine_clock, false, ÷rs);
4850 0 : if (ret)
4851 0 : return ret;
4852 :
4853 0 : reference_divider = 1 + dividers.ref_div;
4854 :
4855 0 : tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4856 0 : do_div(tmp, reference_clock);
4857 0 : fbdiv = (u32) tmp;
4858 :
4859 0 : spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4860 0 : spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4861 0 : spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4862 :
4863 0 : spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4864 0 : spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4865 :
4866 0 : spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4867 0 : spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4868 0 : spll_func_cntl_3 |= SPLL_DITHEN;
4869 :
4870 0 : if (pi->sclk_ss) {
4871 0 : struct radeon_atom_ss ss;
4872 0 : u32 vco_freq = engine_clock * dividers.post_div;
4873 :
4874 0 : if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4875 : ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4876 0 : u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4877 0 : u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4878 :
4879 0 : cg_spll_spread_spectrum &= ~CLK_S_MASK;
4880 0 : cg_spll_spread_spectrum |= CLK_S(clk_s);
4881 0 : cg_spll_spread_spectrum |= SSEN;
4882 :
4883 0 : cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4884 0 : cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4885 0 : }
4886 0 : }
4887 :
4888 0 : sclk->sclk_value = engine_clock;
4889 0 : sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4890 0 : sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4891 0 : sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4892 0 : sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4893 0 : sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4894 0 : sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4895 :
4896 0 : return 0;
4897 0 : }
4898 :
4899 0 : static int si_populate_sclk_value(struct radeon_device *rdev,
4900 : u32 engine_clock,
4901 : SISLANDS_SMC_SCLK_VALUE *sclk)
4902 : {
4903 0 : SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4904 : int ret;
4905 :
4906 0 : ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4907 0 : if (!ret) {
4908 0 : sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4909 0 : sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4910 0 : sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4911 0 : sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4912 0 : sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4913 0 : sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4914 0 : sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4915 0 : }
4916 :
4917 0 : return ret;
4918 0 : }
4919 :
4920 0 : static int si_populate_mclk_value(struct radeon_device *rdev,
4921 : u32 engine_clock,
4922 : u32 memory_clock,
4923 : SISLANDS_SMC_MCLK_VALUE *mclk,
4924 : bool strobe_mode,
4925 : bool dll_state_on)
4926 : {
4927 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4928 0 : struct si_power_info *si_pi = si_get_pi(rdev);
4929 0 : u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4930 0 : u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4931 0 : u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4932 0 : u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4933 0 : u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4934 0 : u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4935 0 : u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4936 0 : u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4937 0 : u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4938 0 : struct atom_mpll_param mpll_param;
4939 : int ret;
4940 :
4941 0 : ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4942 0 : if (ret)
4943 0 : return ret;
4944 :
4945 0 : mpll_func_cntl &= ~BWCTRL_MASK;
4946 0 : mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4947 :
4948 0 : mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4949 0 : mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4950 0 : CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4951 :
4952 0 : mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4953 0 : mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4954 :
4955 0 : if (pi->mem_gddr5) {
4956 0 : mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4957 0 : mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4958 : YCLK_POST_DIV(mpll_param.post_div);
4959 0 : }
4960 :
4961 0 : if (pi->mclk_ss) {
4962 0 : struct radeon_atom_ss ss;
4963 : u32 freq_nom;
4964 : u32 tmp;
4965 0 : u32 reference_clock = rdev->clock.mpll.reference_freq;
4966 :
4967 0 : if (pi->mem_gddr5)
4968 0 : freq_nom = memory_clock * 4;
4969 : else
4970 0 : freq_nom = memory_clock * 2;
4971 :
4972 0 : tmp = freq_nom / reference_clock;
4973 0 : tmp = tmp * tmp;
4974 0 : if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4975 : ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4976 0 : u32 clks = reference_clock * 5 / ss.rate;
4977 0 : u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4978 :
4979 0 : mpll_ss1 &= ~CLKV_MASK;
4980 0 : mpll_ss1 |= CLKV(clkv);
4981 :
4982 0 : mpll_ss2 &= ~CLKS_MASK;
4983 0 : mpll_ss2 |= CLKS(clks);
4984 0 : }
4985 0 : }
4986 :
4987 0 : mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4988 0 : mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4989 :
4990 0 : if (dll_state_on)
4991 0 : mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4992 : else
4993 0 : mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4994 :
4995 0 : mclk->mclk_value = cpu_to_be32(memory_clock);
4996 0 : mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4997 0 : mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4998 0 : mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4999 0 : mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5000 0 : mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5001 0 : mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5002 0 : mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5003 0 : mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5004 0 : mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5005 :
5006 0 : return 0;
5007 0 : }
5008 :
5009 0 : static void si_populate_smc_sp(struct radeon_device *rdev,
5010 : struct radeon_ps *radeon_state,
5011 : SISLANDS_SMC_SWSTATE *smc_state)
5012 : {
5013 0 : struct ni_ps *ps = ni_get_ps(radeon_state);
5014 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5015 : int i;
5016 :
5017 0 : for (i = 0; i < ps->performance_level_count - 1; i++)
5018 0 : smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5019 :
5020 0 : smc_state->levels[ps->performance_level_count - 1].bSP =
5021 0 : cpu_to_be32(pi->psp);
5022 0 : }
5023 :
5024 0 : static int si_convert_power_level_to_smc(struct radeon_device *rdev,
5025 : struct rv7xx_pl *pl,
5026 : SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5027 : {
5028 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5029 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5030 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5031 : int ret;
5032 : bool dll_state_on;
5033 0 : u16 std_vddc;
5034 : bool gmc_pg = false;
5035 :
5036 0 : if (eg_pi->pcie_performance_request &&
5037 0 : (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
5038 0 : level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5039 : else
5040 0 : level->gen2PCIE = (u8)pl->pcie_gen;
5041 :
5042 0 : ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
5043 0 : if (ret)
5044 0 : return ret;
5045 :
5046 0 : level->mcFlags = 0;
5047 :
5048 0 : if (pi->mclk_stutter_mode_threshold &&
5049 0 : (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5050 0 : !eg_pi->uvd_enabled &&
5051 0 : (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5052 0 : (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5053 0 : level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5054 :
5055 0 : if (gmc_pg)
5056 0 : level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5057 : }
5058 :
5059 0 : if (pi->mem_gddr5) {
5060 0 : if (pl->mclk > pi->mclk_edc_enable_threshold)
5061 0 : level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5062 :
5063 0 : if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5064 0 : level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5065 :
5066 0 : level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5067 :
5068 0 : if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5069 0 : if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5070 0 : ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5071 0 : dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5072 : else
5073 0 : dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5074 : } else {
5075 : dll_state_on = false;
5076 : }
5077 : } else {
5078 0 : level->strobeMode = si_get_strobe_mode_settings(rdev,
5079 0 : pl->mclk);
5080 :
5081 0 : dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5082 : }
5083 :
5084 0 : ret = si_populate_mclk_value(rdev,
5085 0 : pl->sclk,
5086 0 : pl->mclk,
5087 0 : &level->mclk,
5088 0 : (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5089 0 : if (ret)
5090 0 : return ret;
5091 :
5092 0 : ret = si_populate_voltage_value(rdev,
5093 0 : &eg_pi->vddc_voltage_table,
5094 0 : pl->vddc, &level->vddc);
5095 0 : if (ret)
5096 0 : return ret;
5097 :
5098 :
5099 0 : ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5100 0 : if (ret)
5101 0 : return ret;
5102 :
5103 0 : ret = si_populate_std_voltage_value(rdev, std_vddc,
5104 0 : level->vddc.index, &level->std_vddc);
5105 0 : if (ret)
5106 0 : return ret;
5107 :
5108 0 : if (eg_pi->vddci_control) {
5109 0 : ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5110 0 : pl->vddci, &level->vddci);
5111 0 : if (ret)
5112 0 : return ret;
5113 : }
5114 :
5115 0 : if (si_pi->vddc_phase_shed_control) {
5116 0 : ret = si_populate_phase_shedding_value(rdev,
5117 0 : &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5118 0 : pl->vddc,
5119 0 : pl->sclk,
5120 0 : pl->mclk,
5121 : &level->vddc);
5122 0 : if (ret)
5123 0 : return ret;
5124 : }
5125 :
5126 0 : level->MaxPoweredUpCU = si_pi->max_cu;
5127 :
5128 0 : ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5129 :
5130 0 : return ret;
5131 0 : }
5132 :
5133 0 : static int si_populate_smc_t(struct radeon_device *rdev,
5134 : struct radeon_ps *radeon_state,
5135 : SISLANDS_SMC_SWSTATE *smc_state)
5136 : {
5137 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5138 0 : struct ni_ps *state = ni_get_ps(radeon_state);
5139 : u32 a_t;
5140 0 : u32 t_l, t_h;
5141 : u32 high_bsp;
5142 : int i, ret;
5143 :
5144 0 : if (state->performance_level_count >= 9)
5145 0 : return -EINVAL;
5146 :
5147 0 : if (state->performance_level_count < 2) {
5148 : a_t = CG_R(0xffff) | CG_L(0);
5149 0 : smc_state->levels[0].aT = cpu_to_be32(a_t);
5150 0 : return 0;
5151 : }
5152 :
5153 0 : smc_state->levels[0].aT = cpu_to_be32(0);
5154 :
5155 0 : for (i = 0; i <= state->performance_level_count - 2; i++) {
5156 0 : ret = r600_calculate_at(
5157 0 : (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5158 : 100 * R600_AH_DFLT,
5159 0 : state->performance_levels[i + 1].sclk,
5160 0 : state->performance_levels[i].sclk,
5161 : &t_l,
5162 : &t_h);
5163 :
5164 0 : if (ret) {
5165 0 : t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5166 0 : t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5167 0 : }
5168 :
5169 0 : a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5170 0 : a_t |= CG_R(t_l * pi->bsp / 20000);
5171 0 : smc_state->levels[i].aT = cpu_to_be32(a_t);
5172 :
5173 0 : high_bsp = (i == state->performance_level_count - 2) ?
5174 0 : pi->pbsp : pi->bsp;
5175 0 : a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5176 0 : smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5177 : }
5178 :
5179 0 : return 0;
5180 0 : }
5181 :
5182 0 : static int si_disable_ulv(struct radeon_device *rdev)
5183 : {
5184 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5185 0 : struct si_ulv_param *ulv = &si_pi->ulv;
5186 :
5187 0 : if (ulv->supported)
5188 0 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5189 : 0 : -EINVAL;
5190 :
5191 0 : return 0;
5192 0 : }
5193 :
5194 0 : static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5195 : struct radeon_ps *radeon_state)
5196 : {
5197 0 : const struct si_power_info *si_pi = si_get_pi(rdev);
5198 0 : const struct si_ulv_param *ulv = &si_pi->ulv;
5199 0 : const struct ni_ps *state = ni_get_ps(radeon_state);
5200 : int i;
5201 :
5202 0 : if (state->performance_levels[0].mclk != ulv->pl.mclk)
5203 0 : return false;
5204 :
5205 : /* XXX validate against display requirements! */
5206 :
5207 0 : for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5208 0 : if (rdev->clock.current_dispclk <=
5209 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5210 0 : if (ulv->pl.vddc <
5211 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5212 0 : return false;
5213 : }
5214 : }
5215 :
5216 0 : if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
5217 0 : return false;
5218 :
5219 0 : return true;
5220 0 : }
5221 :
5222 0 : static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5223 : struct radeon_ps *radeon_new_state)
5224 : {
5225 0 : const struct si_power_info *si_pi = si_get_pi(rdev);
5226 0 : const struct si_ulv_param *ulv = &si_pi->ulv;
5227 :
5228 0 : if (ulv->supported) {
5229 0 : if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5230 0 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5231 : 0 : -EINVAL;
5232 : }
5233 0 : return 0;
5234 0 : }
5235 :
5236 0 : static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5237 : struct radeon_ps *radeon_state,
5238 : SISLANDS_SMC_SWSTATE *smc_state)
5239 : {
5240 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5241 0 : struct ni_power_info *ni_pi = ni_get_pi(rdev);
5242 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5243 0 : struct ni_ps *state = ni_get_ps(radeon_state);
5244 : int i, ret;
5245 : u32 threshold;
5246 : u32 sclk_in_sr = 1350; /* ??? */
5247 :
5248 0 : if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5249 0 : return -EINVAL;
5250 :
5251 0 : threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5252 :
5253 0 : if (radeon_state->vclk && radeon_state->dclk) {
5254 0 : eg_pi->uvd_enabled = true;
5255 0 : if (eg_pi->smu_uvd_hs)
5256 0 : smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5257 : } else {
5258 0 : eg_pi->uvd_enabled = false;
5259 : }
5260 :
5261 0 : if (state->dc_compatible)
5262 0 : smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5263 :
5264 0 : smc_state->levelCount = 0;
5265 0 : for (i = 0; i < state->performance_level_count; i++) {
5266 0 : if (eg_pi->sclk_deep_sleep) {
5267 0 : if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5268 0 : if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5269 0 : smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5270 : else
5271 0 : smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5272 : }
5273 : }
5274 :
5275 0 : ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5276 0 : &smc_state->levels[i]);
5277 0 : smc_state->levels[i].arbRefreshState =
5278 0 : (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5279 :
5280 0 : if (ret)
5281 0 : return ret;
5282 :
5283 0 : if (ni_pi->enable_power_containment)
5284 0 : smc_state->levels[i].displayWatermark =
5285 0 : (state->performance_levels[i].sclk < threshold) ?
5286 : PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5287 : else
5288 0 : smc_state->levels[i].displayWatermark = (i < 2) ?
5289 : PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5290 :
5291 0 : if (eg_pi->dynamic_ac_timing)
5292 0 : smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5293 : else
5294 0 : smc_state->levels[i].ACIndex = 0;
5295 :
5296 0 : smc_state->levelCount++;
5297 : }
5298 :
5299 0 : si_write_smc_soft_register(rdev,
5300 : SI_SMC_SOFT_REGISTER_watermark_threshold,
5301 0 : threshold / 512);
5302 :
5303 0 : si_populate_smc_sp(rdev, radeon_state, smc_state);
5304 :
5305 0 : ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5306 0 : if (ret)
5307 0 : ni_pi->enable_power_containment = false;
5308 :
5309 0 : ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5310 0 : if (ret)
5311 0 : ni_pi->enable_sq_ramping = false;
5312 :
5313 0 : return si_populate_smc_t(rdev, radeon_state, smc_state);
5314 0 : }
5315 :
5316 0 : static int si_upload_sw_state(struct radeon_device *rdev,
5317 : struct radeon_ps *radeon_new_state)
5318 : {
5319 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5320 0 : struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5321 : int ret;
5322 0 : u32 address = si_pi->state_table_start +
5323 : offsetof(SISLANDS_SMC_STATETABLE, driverState);
5324 0 : u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5325 0 : ((new_state->performance_level_count - 1) *
5326 : sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5327 0 : SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5328 :
5329 0 : memset(smc_state, 0, state_size);
5330 :
5331 0 : ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5332 0 : if (ret)
5333 0 : return ret;
5334 :
5335 0 : ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5336 0 : state_size, si_pi->sram_end);
5337 :
5338 0 : return ret;
5339 0 : }
5340 :
5341 0 : static int si_upload_ulv_state(struct radeon_device *rdev)
5342 : {
5343 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5344 0 : struct si_ulv_param *ulv = &si_pi->ulv;
5345 : int ret = 0;
5346 :
5347 0 : if (ulv->supported && ulv->pl.vddc) {
5348 0 : u32 address = si_pi->state_table_start +
5349 : offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5350 0 : SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5351 : u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5352 :
5353 0 : memset(smc_state, 0, state_size);
5354 :
5355 0 : ret = si_populate_ulv_state(rdev, smc_state);
5356 0 : if (!ret)
5357 0 : ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5358 0 : state_size, si_pi->sram_end);
5359 0 : }
5360 :
5361 0 : return ret;
5362 : }
5363 :
5364 0 : static int si_upload_smc_data(struct radeon_device *rdev)
5365 : {
5366 : struct radeon_crtc *radeon_crtc = NULL;
5367 : int i;
5368 :
5369 0 : if (rdev->pm.dpm.new_active_crtc_count == 0)
5370 0 : return 0;
5371 :
5372 0 : for (i = 0; i < rdev->num_crtc; i++) {
5373 0 : if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5374 0 : radeon_crtc = rdev->mode_info.crtcs[i];
5375 0 : break;
5376 : }
5377 : }
5378 :
5379 0 : if (radeon_crtc == NULL)
5380 0 : return 0;
5381 :
5382 0 : if (radeon_crtc->line_time <= 0)
5383 0 : return 0;
5384 :
5385 0 : if (si_write_smc_soft_register(rdev,
5386 : SI_SMC_SOFT_REGISTER_crtc_index,
5387 0 : radeon_crtc->crtc_id) != PPSMC_Result_OK)
5388 0 : return 0;
5389 :
5390 0 : if (si_write_smc_soft_register(rdev,
5391 : SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5392 0 : radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5393 0 : return 0;
5394 :
5395 0 : if (si_write_smc_soft_register(rdev,
5396 : SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5397 0 : radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5398 0 : return 0;
5399 :
5400 : return 0;
5401 0 : }
5402 :
5403 0 : static int si_set_mc_special_registers(struct radeon_device *rdev,
5404 : struct si_mc_reg_table *table)
5405 : {
5406 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5407 : u8 i, j, k;
5408 : u32 temp_reg;
5409 :
5410 0 : for (i = 0, j = table->last; i < table->last; i++) {
5411 0 : if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5412 0 : return -EINVAL;
5413 0 : switch (table->mc_reg_address[i].s1 << 2) {
5414 : case MC_SEQ_MISC1:
5415 0 : temp_reg = RREG32(MC_PMG_CMD_EMRS);
5416 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5417 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5418 0 : for (k = 0; k < table->num_entries; k++)
5419 0 : table->mc_reg_table_entry[k].mc_data[j] =
5420 0 : ((temp_reg & 0xffff0000)) |
5421 0 : ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5422 0 : j++;
5423 0 : if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5424 0 : return -EINVAL;
5425 :
5426 0 : temp_reg = RREG32(MC_PMG_CMD_MRS);
5427 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5428 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5429 0 : for (k = 0; k < table->num_entries; k++) {
5430 0 : table->mc_reg_table_entry[k].mc_data[j] =
5431 0 : (temp_reg & 0xffff0000) |
5432 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5433 0 : if (!pi->mem_gddr5)
5434 0 : table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5435 : }
5436 0 : j++;
5437 0 : if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5438 0 : return -EINVAL;
5439 :
5440 0 : if (!pi->mem_gddr5) {
5441 0 : table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5442 0 : table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5443 0 : for (k = 0; k < table->num_entries; k++)
5444 0 : table->mc_reg_table_entry[k].mc_data[j] =
5445 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5446 0 : j++;
5447 0 : if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5448 0 : return -EINVAL;
5449 : }
5450 : break;
5451 : case MC_SEQ_RESERVE_M:
5452 0 : temp_reg = RREG32(MC_PMG_CMD_MRS1);
5453 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5454 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5455 0 : for(k = 0; k < table->num_entries; k++)
5456 0 : table->mc_reg_table_entry[k].mc_data[j] =
5457 0 : (temp_reg & 0xffff0000) |
5458 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5459 0 : j++;
5460 0 : if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5461 0 : return -EINVAL;
5462 : break;
5463 : default:
5464 : break;
5465 : }
5466 : }
5467 :
5468 0 : table->last = j;
5469 :
5470 0 : return 0;
5471 0 : }
5472 :
5473 0 : static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5474 : {
5475 : bool result = true;
5476 :
5477 0 : switch (in_reg) {
5478 : case MC_SEQ_RAS_TIMING >> 2:
5479 0 : *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5480 0 : break;
5481 : case MC_SEQ_CAS_TIMING >> 2:
5482 0 : *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5483 0 : break;
5484 : case MC_SEQ_MISC_TIMING >> 2:
5485 0 : *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5486 0 : break;
5487 : case MC_SEQ_MISC_TIMING2 >> 2:
5488 0 : *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5489 0 : break;
5490 : case MC_SEQ_RD_CTL_D0 >> 2:
5491 0 : *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5492 0 : break;
5493 : case MC_SEQ_RD_CTL_D1 >> 2:
5494 0 : *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5495 0 : break;
5496 : case MC_SEQ_WR_CTL_D0 >> 2:
5497 0 : *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5498 0 : break;
5499 : case MC_SEQ_WR_CTL_D1 >> 2:
5500 0 : *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5501 0 : break;
5502 : case MC_PMG_CMD_EMRS >> 2:
5503 0 : *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5504 0 : break;
5505 : case MC_PMG_CMD_MRS >> 2:
5506 0 : *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5507 0 : break;
5508 : case MC_PMG_CMD_MRS1 >> 2:
5509 0 : *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5510 0 : break;
5511 : case MC_SEQ_PMG_TIMING >> 2:
5512 0 : *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5513 0 : break;
5514 : case MC_PMG_CMD_MRS2 >> 2:
5515 0 : *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5516 0 : break;
5517 : case MC_SEQ_WR_CTL_2 >> 2:
5518 0 : *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5519 0 : break;
5520 : default:
5521 : result = false;
5522 0 : break;
5523 : }
5524 :
5525 0 : return result;
5526 : }
5527 :
5528 0 : static void si_set_valid_flag(struct si_mc_reg_table *table)
5529 : {
5530 : u8 i, j;
5531 :
5532 0 : for (i = 0; i < table->last; i++) {
5533 0 : for (j = 1; j < table->num_entries; j++) {
5534 0 : if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5535 0 : table->valid_flag |= 1 << i;
5536 0 : break;
5537 : }
5538 : }
5539 : }
5540 0 : }
5541 :
5542 0 : static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5543 : {
5544 : u32 i;
5545 0 : u16 address;
5546 :
5547 0 : for (i = 0; i < table->last; i++)
5548 0 : table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5549 0 : address : table->mc_reg_address[i].s1;
5550 :
5551 0 : }
5552 :
5553 0 : static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5554 : struct si_mc_reg_table *si_table)
5555 : {
5556 : u8 i, j;
5557 :
5558 0 : if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5559 0 : return -EINVAL;
5560 0 : if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5561 0 : return -EINVAL;
5562 :
5563 0 : for (i = 0; i < table->last; i++)
5564 0 : si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5565 0 : si_table->last = table->last;
5566 :
5567 0 : for (i = 0; i < table->num_entries; i++) {
5568 0 : si_table->mc_reg_table_entry[i].mclk_max =
5569 0 : table->mc_reg_table_entry[i].mclk_max;
5570 0 : for (j = 0; j < table->last; j++) {
5571 0 : si_table->mc_reg_table_entry[i].mc_data[j] =
5572 0 : table->mc_reg_table_entry[i].mc_data[j];
5573 : }
5574 : }
5575 0 : si_table->num_entries = table->num_entries;
5576 :
5577 0 : return 0;
5578 0 : }
5579 :
5580 0 : static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5581 : {
5582 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5583 : struct atom_mc_reg_table *table;
5584 0 : struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5585 0 : u8 module_index = rv770_get_memory_module_index(rdev);
5586 : int ret;
5587 :
5588 0 : table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5589 0 : if (!table)
5590 0 : return -ENOMEM;
5591 :
5592 0 : WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5593 0 : WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5594 0 : WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5595 0 : WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5596 0 : WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5597 0 : WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5598 0 : WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5599 0 : WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5600 0 : WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5601 0 : WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5602 0 : WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5603 0 : WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5604 0 : WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5605 0 : WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5606 :
5607 0 : ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5608 0 : if (ret)
5609 : goto init_mc_done;
5610 :
5611 0 : ret = si_copy_vbios_mc_reg_table(table, si_table);
5612 0 : if (ret)
5613 : goto init_mc_done;
5614 :
5615 0 : si_set_s0_mc_reg_index(si_table);
5616 :
5617 0 : ret = si_set_mc_special_registers(rdev, si_table);
5618 0 : if (ret)
5619 : goto init_mc_done;
5620 :
5621 0 : si_set_valid_flag(si_table);
5622 :
5623 : init_mc_done:
5624 0 : kfree(table);
5625 :
5626 0 : return ret;
5627 :
5628 0 : }
5629 :
5630 0 : static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5631 : SMC_SIslands_MCRegisters *mc_reg_table)
5632 : {
5633 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5634 : u32 i, j;
5635 :
5636 0 : for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5637 0 : if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5638 0 : if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5639 : break;
5640 0 : mc_reg_table->address[i].s0 =
5641 0 : cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5642 0 : mc_reg_table->address[i].s1 =
5643 0 : cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5644 0 : i++;
5645 0 : }
5646 : }
5647 0 : mc_reg_table->last = (u8)i;
5648 0 : }
5649 :
5650 0 : static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5651 : SMC_SIslands_MCRegisterSet *data,
5652 : u32 num_entries, u32 valid_flag)
5653 : {
5654 : u32 i, j;
5655 :
5656 0 : for(i = 0, j = 0; j < num_entries; j++) {
5657 0 : if (valid_flag & (1 << j)) {
5658 0 : data->value[i] = cpu_to_be32(entry->mc_data[j]);
5659 0 : i++;
5660 0 : }
5661 : }
5662 0 : }
5663 :
5664 0 : static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5665 : struct rv7xx_pl *pl,
5666 : SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5667 : {
5668 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5669 : u32 i = 0;
5670 :
5671 0 : for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5672 0 : if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5673 : break;
5674 : }
5675 :
5676 0 : if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5677 0 : --i;
5678 :
5679 0 : si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5680 0 : mc_reg_table_data, si_pi->mc_reg_table.last,
5681 0 : si_pi->mc_reg_table.valid_flag);
5682 0 : }
5683 :
5684 0 : static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5685 : struct radeon_ps *radeon_state,
5686 : SMC_SIslands_MCRegisters *mc_reg_table)
5687 : {
5688 0 : struct ni_ps *state = ni_get_ps(radeon_state);
5689 : int i;
5690 :
5691 0 : for (i = 0; i < state->performance_level_count; i++) {
5692 0 : si_convert_mc_reg_table_entry_to_smc(rdev,
5693 0 : &state->performance_levels[i],
5694 0 : &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5695 : }
5696 0 : }
5697 :
5698 0 : static int si_populate_mc_reg_table(struct radeon_device *rdev,
5699 : struct radeon_ps *radeon_boot_state)
5700 : {
5701 0 : struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5702 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5703 0 : struct si_ulv_param *ulv = &si_pi->ulv;
5704 0 : SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5705 :
5706 0 : memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5707 :
5708 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5709 :
5710 0 : si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5711 :
5712 0 : si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5713 0 : &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5714 :
5715 0 : si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5716 0 : &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5717 0 : si_pi->mc_reg_table.last,
5718 0 : si_pi->mc_reg_table.valid_flag);
5719 :
5720 0 : if (ulv->supported && ulv->pl.vddc != 0)
5721 0 : si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5722 0 : &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5723 : else
5724 0 : si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5725 0 : &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5726 0 : si_pi->mc_reg_table.last,
5727 0 : si_pi->mc_reg_table.valid_flag);
5728 :
5729 0 : si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5730 :
5731 0 : return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5732 : (u8 *)smc_mc_reg_table,
5733 0 : sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5734 : }
5735 :
5736 0 : static int si_upload_mc_reg_table(struct radeon_device *rdev,
5737 : struct radeon_ps *radeon_new_state)
5738 : {
5739 0 : struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5740 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5741 0 : u32 address = si_pi->mc_reg_table_start +
5742 : offsetof(SMC_SIslands_MCRegisters,
5743 : data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5744 0 : SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5745 :
5746 0 : memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5747 :
5748 0 : si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5749 :
5750 :
5751 0 : return si_copy_bytes_to_smc(rdev, address,
5752 0 : (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5753 0 : sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5754 0 : si_pi->sram_end);
5755 :
5756 : }
5757 :
5758 0 : static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5759 : {
5760 0 : if (enable)
5761 0 : WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5762 : else
5763 0 : WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5764 0 : }
5765 :
5766 0 : static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5767 : struct radeon_ps *radeon_state)
5768 : {
5769 0 : struct ni_ps *state = ni_get_ps(radeon_state);
5770 : int i;
5771 : u16 pcie_speed, max_speed = 0;
5772 :
5773 0 : for (i = 0; i < state->performance_level_count; i++) {
5774 0 : pcie_speed = state->performance_levels[i].pcie_gen;
5775 0 : if (max_speed < pcie_speed)
5776 0 : max_speed = pcie_speed;
5777 : }
5778 0 : return max_speed;
5779 : }
5780 :
5781 0 : static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5782 : {
5783 : u32 speed_cntl;
5784 :
5785 0 : speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5786 0 : speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5787 :
5788 0 : return (u16)speed_cntl;
5789 : }
5790 :
5791 0 : static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5792 : struct radeon_ps *radeon_new_state,
5793 : struct radeon_ps *radeon_current_state)
5794 : {
5795 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5796 0 : enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5797 : enum radeon_pcie_gen current_link_speed;
5798 :
5799 0 : if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5800 0 : current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5801 : else
5802 : current_link_speed = si_pi->force_pcie_gen;
5803 :
5804 0 : si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5805 0 : si_pi->pspp_notify_required = false;
5806 0 : if (target_link_speed > current_link_speed) {
5807 : switch (target_link_speed) {
5808 : #if defined(CONFIG_ACPI)
5809 : case RADEON_PCIE_GEN3:
5810 : if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5811 : break;
5812 : si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5813 : if (current_link_speed == RADEON_PCIE_GEN2)
5814 : break;
5815 : case RADEON_PCIE_GEN2:
5816 : if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5817 : break;
5818 : #endif
5819 : default:
5820 0 : si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5821 : break;
5822 : }
5823 0 : } else {
5824 0 : if (target_link_speed < current_link_speed)
5825 0 : si_pi->pspp_notify_required = true;
5826 : }
5827 0 : }
5828 :
5829 0 : static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5830 : struct radeon_ps *radeon_new_state,
5831 : struct radeon_ps *radeon_current_state)
5832 : {
5833 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5834 0 : enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5835 : u8 request;
5836 :
5837 0 : if (si_pi->pspp_notify_required) {
5838 0 : if (target_link_speed == RADEON_PCIE_GEN3)
5839 0 : request = PCIE_PERF_REQ_PECI_GEN3;
5840 0 : else if (target_link_speed == RADEON_PCIE_GEN2)
5841 0 : request = PCIE_PERF_REQ_PECI_GEN2;
5842 : else
5843 : request = PCIE_PERF_REQ_PECI_GEN1;
5844 :
5845 0 : if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5846 0 : (si_get_current_pcie_speed(rdev) > 0))
5847 0 : return;
5848 :
5849 : #if defined(CONFIG_ACPI)
5850 : radeon_acpi_pcie_performance_request(rdev, request, false);
5851 : #endif
5852 : }
5853 0 : }
5854 :
5855 : #if 0
5856 : static int si_ds_request(struct radeon_device *rdev,
5857 : bool ds_status_on, u32 count_write)
5858 : {
5859 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5860 :
5861 : if (eg_pi->sclk_deep_sleep) {
5862 : if (ds_status_on)
5863 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5864 : PPSMC_Result_OK) ?
5865 : 0 : -EINVAL;
5866 : else
5867 : return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5868 : PPSMC_Result_OK) ? 0 : -EINVAL;
5869 : }
5870 : return 0;
5871 : }
5872 : #endif
5873 :
5874 0 : static void si_set_max_cu_value(struct radeon_device *rdev)
5875 : {
5876 0 : struct si_power_info *si_pi = si_get_pi(rdev);
5877 :
5878 0 : if (rdev->family == CHIP_VERDE) {
5879 0 : switch (rdev->pdev->device) {
5880 : case 0x6820:
5881 : case 0x6825:
5882 : case 0x6821:
5883 : case 0x6823:
5884 : case 0x6827:
5885 0 : si_pi->max_cu = 10;
5886 0 : break;
5887 : case 0x682D:
5888 : case 0x6824:
5889 : case 0x682F:
5890 : case 0x6826:
5891 0 : si_pi->max_cu = 8;
5892 0 : break;
5893 : case 0x6828:
5894 : case 0x6830:
5895 : case 0x6831:
5896 : case 0x6838:
5897 : case 0x6839:
5898 : case 0x683D:
5899 0 : si_pi->max_cu = 10;
5900 0 : break;
5901 : case 0x683B:
5902 : case 0x683F:
5903 : case 0x6829:
5904 0 : si_pi->max_cu = 8;
5905 0 : break;
5906 : default:
5907 0 : si_pi->max_cu = 0;
5908 0 : break;
5909 : }
5910 : } else {
5911 0 : si_pi->max_cu = 0;
5912 : }
5913 0 : }
5914 :
5915 0 : static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5916 : struct radeon_clock_voltage_dependency_table *table)
5917 : {
5918 : u32 i;
5919 : int j;
5920 0 : u16 leakage_voltage;
5921 :
5922 0 : if (table) {
5923 0 : for (i = 0; i < table->count; i++) {
5924 0 : switch (si_get_leakage_voltage_from_leakage_index(rdev,
5925 0 : table->entries[i].v,
5926 : &leakage_voltage)) {
5927 : case 0:
5928 0 : table->entries[i].v = leakage_voltage;
5929 0 : break;
5930 : case -EAGAIN:
5931 0 : return -EINVAL;
5932 : case -EINVAL:
5933 : default:
5934 : break;
5935 : }
5936 : }
5937 :
5938 0 : for (j = (table->count - 2); j >= 0; j--) {
5939 0 : table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5940 : table->entries[j].v : table->entries[j + 1].v;
5941 : }
5942 : }
5943 0 : return 0;
5944 0 : }
5945 :
5946 0 : static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5947 : {
5948 : int ret = 0;
5949 :
5950 0 : ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5951 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5952 0 : ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5953 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5954 0 : ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5955 0 : &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5956 0 : return ret;
5957 : }
5958 :
5959 0 : static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5960 : struct radeon_ps *radeon_new_state,
5961 : struct radeon_ps *radeon_current_state)
5962 : {
5963 : u32 lane_width;
5964 : u32 new_lane_width =
5965 0 : ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5966 : u32 current_lane_width =
5967 0 : ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
5968 :
5969 0 : if (new_lane_width != current_lane_width) {
5970 0 : radeon_set_pcie_lanes(rdev, new_lane_width);
5971 0 : lane_width = radeon_get_pcie_lanes(rdev);
5972 0 : si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5973 0 : }
5974 0 : }
5975 :
5976 0 : static void si_set_vce_clock(struct radeon_device *rdev,
5977 : struct radeon_ps *new_rps,
5978 : struct radeon_ps *old_rps)
5979 : {
5980 0 : if ((old_rps->evclk != new_rps->evclk) ||
5981 0 : (old_rps->ecclk != new_rps->ecclk)) {
5982 : /* turn the clocks on when encoding, off otherwise */
5983 0 : if (new_rps->evclk || new_rps->ecclk)
5984 0 : vce_v1_0_enable_mgcg(rdev, false);
5985 : else
5986 0 : vce_v1_0_enable_mgcg(rdev, true);
5987 0 : radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5988 0 : }
5989 0 : }
5990 :
5991 0 : void si_dpm_setup_asic(struct radeon_device *rdev)
5992 : {
5993 : int r;
5994 :
5995 0 : r = si_mc_load_microcode(rdev);
5996 0 : if (r)
5997 0 : DRM_ERROR("Failed to load MC firmware!\n");
5998 0 : rv770_get_memory_type(rdev);
5999 0 : si_read_clock_registers(rdev);
6000 0 : si_enable_acpi_power_management(rdev);
6001 0 : }
6002 :
6003 0 : static int si_thermal_enable_alert(struct radeon_device *rdev,
6004 : bool enable)
6005 : {
6006 0 : u32 thermal_int = RREG32(CG_THERMAL_INT);
6007 :
6008 0 : if (enable) {
6009 : PPSMC_Result result;
6010 :
6011 0 : thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6012 0 : WREG32(CG_THERMAL_INT, thermal_int);
6013 0 : rdev->irq.dpm_thermal = false;
6014 0 : result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
6015 0 : if (result != PPSMC_Result_OK) {
6016 : DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6017 0 : return -EINVAL;
6018 : }
6019 0 : } else {
6020 0 : thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6021 0 : WREG32(CG_THERMAL_INT, thermal_int);
6022 0 : rdev->irq.dpm_thermal = true;
6023 : }
6024 :
6025 0 : return 0;
6026 0 : }
6027 :
6028 0 : static int si_thermal_set_temperature_range(struct radeon_device *rdev,
6029 : int min_temp, int max_temp)
6030 : {
6031 : int low_temp = 0 * 1000;
6032 : int high_temp = 255 * 1000;
6033 :
6034 0 : if (low_temp < min_temp)
6035 0 : low_temp = min_temp;
6036 0 : if (high_temp > max_temp)
6037 0 : high_temp = max_temp;
6038 0 : if (high_temp < low_temp) {
6039 0 : DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6040 0 : return -EINVAL;
6041 : }
6042 :
6043 0 : WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6044 0 : WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6045 0 : WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6046 :
6047 0 : rdev->pm.dpm.thermal.min_temp = low_temp;
6048 0 : rdev->pm.dpm.thermal.max_temp = high_temp;
6049 :
6050 0 : return 0;
6051 0 : }
6052 :
6053 0 : static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
6054 : {
6055 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6056 : u32 tmp;
6057 :
6058 0 : if (si_pi->fan_ctrl_is_in_default_mode) {
6059 0 : tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6060 0 : si_pi->fan_ctrl_default_mode = tmp;
6061 0 : tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6062 0 : si_pi->t_min = tmp;
6063 0 : si_pi->fan_ctrl_is_in_default_mode = false;
6064 0 : }
6065 :
6066 0 : tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6067 : tmp |= TMIN(0);
6068 0 : WREG32(CG_FDO_CTRL2, tmp);
6069 :
6070 0 : tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6071 0 : tmp |= FDO_PWM_MODE(mode);
6072 0 : WREG32(CG_FDO_CTRL2, tmp);
6073 0 : }
6074 :
6075 0 : static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6076 : {
6077 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6078 0 : PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6079 : u32 duty100;
6080 : u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6081 : u16 fdo_min, slope1, slope2;
6082 : u32 reference_clock, tmp;
6083 : int ret;
6084 : u64 tmp64;
6085 :
6086 0 : if (!si_pi->fan_table_start) {
6087 0 : rdev->pm.dpm.fan.ucode_fan_control = false;
6088 0 : return 0;
6089 : }
6090 :
6091 0 : duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6092 :
6093 0 : if (duty100 == 0) {
6094 0 : rdev->pm.dpm.fan.ucode_fan_control = false;
6095 0 : return 0;
6096 : }
6097 :
6098 0 : tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6099 0 : do_div(tmp64, 10000);
6100 0 : fdo_min = (u16)tmp64;
6101 :
6102 0 : t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6103 0 : t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6104 :
6105 0 : pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6106 0 : pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6107 :
6108 0 : slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6109 0 : slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6110 :
6111 0 : fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6112 0 : fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6113 0 : fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6114 :
6115 0 : fan_table.slope1 = cpu_to_be16(slope1);
6116 0 : fan_table.slope2 = cpu_to_be16(slope2);
6117 :
6118 0 : fan_table.fdo_min = cpu_to_be16(fdo_min);
6119 :
6120 0 : fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6121 :
6122 0 : fan_table.hys_up = cpu_to_be16(1);
6123 :
6124 0 : fan_table.hys_slope = cpu_to_be16(1);
6125 :
6126 0 : fan_table.temp_resp_lim = cpu_to_be16(5);
6127 :
6128 0 : reference_clock = radeon_get_xclk(rdev);
6129 :
6130 0 : fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6131 : reference_clock) / 1600);
6132 :
6133 0 : fan_table.fdo_max = cpu_to_be16((u16)duty100);
6134 :
6135 0 : tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6136 0 : fan_table.temp_src = (uint8_t)tmp;
6137 :
6138 0 : ret = si_copy_bytes_to_smc(rdev,
6139 0 : si_pi->fan_table_start,
6140 : (u8 *)(&fan_table),
6141 : sizeof(fan_table),
6142 0 : si_pi->sram_end);
6143 :
6144 0 : if (ret) {
6145 0 : DRM_ERROR("Failed to load fan table to the SMC.");
6146 0 : rdev->pm.dpm.fan.ucode_fan_control = false;
6147 0 : }
6148 :
6149 0 : return 0;
6150 0 : }
6151 :
6152 0 : static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6153 : {
6154 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6155 : PPSMC_Result ret;
6156 :
6157 0 : ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6158 0 : if (ret == PPSMC_Result_OK) {
6159 0 : si_pi->fan_is_controlled_by_smc = true;
6160 0 : return 0;
6161 : } else {
6162 0 : return -EINVAL;
6163 : }
6164 0 : }
6165 :
6166 0 : static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6167 : {
6168 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6169 : PPSMC_Result ret;
6170 :
6171 0 : ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6172 :
6173 0 : if (ret == PPSMC_Result_OK) {
6174 0 : si_pi->fan_is_controlled_by_smc = false;
6175 0 : return 0;
6176 : } else {
6177 0 : return -EINVAL;
6178 : }
6179 0 : }
6180 :
6181 0 : int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6182 : u32 *speed)
6183 : {
6184 : u32 duty, duty100;
6185 : u64 tmp64;
6186 :
6187 0 : if (rdev->pm.no_fan)
6188 0 : return -ENOENT;
6189 :
6190 0 : duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6191 0 : duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6192 :
6193 0 : if (duty100 == 0)
6194 0 : return -EINVAL;
6195 :
6196 0 : tmp64 = (u64)duty * 100;
6197 0 : do_div(tmp64, duty100);
6198 0 : *speed = (u32)tmp64;
6199 :
6200 0 : if (*speed > 100)
6201 0 : *speed = 100;
6202 :
6203 0 : return 0;
6204 0 : }
6205 :
6206 0 : int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6207 : u32 speed)
6208 : {
6209 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6210 : u32 tmp;
6211 : u32 duty, duty100;
6212 : u64 tmp64;
6213 :
6214 0 : if (rdev->pm.no_fan)
6215 0 : return -ENOENT;
6216 :
6217 0 : if (si_pi->fan_is_controlled_by_smc)
6218 0 : return -EINVAL;
6219 :
6220 0 : if (speed > 100)
6221 0 : return -EINVAL;
6222 :
6223 0 : duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6224 :
6225 0 : if (duty100 == 0)
6226 0 : return -EINVAL;
6227 :
6228 0 : tmp64 = (u64)speed * duty100;
6229 0 : do_div(tmp64, 100);
6230 0 : duty = (u32)tmp64;
6231 :
6232 0 : tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6233 0 : tmp |= FDO_STATIC_DUTY(duty);
6234 0 : WREG32(CG_FDO_CTRL0, tmp);
6235 :
6236 0 : return 0;
6237 0 : }
6238 :
6239 0 : void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6240 : {
6241 0 : if (mode) {
6242 : /* stop auto-manage */
6243 0 : if (rdev->pm.dpm.fan.ucode_fan_control)
6244 0 : si_fan_ctrl_stop_smc_fan_control(rdev);
6245 0 : si_fan_ctrl_set_static_mode(rdev, mode);
6246 0 : } else {
6247 : /* restart auto-manage */
6248 0 : if (rdev->pm.dpm.fan.ucode_fan_control)
6249 0 : si_thermal_start_smc_fan_control(rdev);
6250 : else
6251 0 : si_fan_ctrl_set_default_mode(rdev);
6252 : }
6253 0 : }
6254 :
6255 0 : u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6256 : {
6257 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6258 : u32 tmp;
6259 :
6260 0 : if (si_pi->fan_is_controlled_by_smc)
6261 0 : return 0;
6262 :
6263 0 : tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6264 0 : return (tmp >> FDO_PWM_MODE_SHIFT);
6265 0 : }
6266 :
6267 : #if 0
6268 : static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6269 : u32 *speed)
6270 : {
6271 : u32 tach_period;
6272 : u32 xclk = radeon_get_xclk(rdev);
6273 :
6274 : if (rdev->pm.no_fan)
6275 : return -ENOENT;
6276 :
6277 : if (rdev->pm.fan_pulses_per_revolution == 0)
6278 : return -ENOENT;
6279 :
6280 : tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6281 : if (tach_period == 0)
6282 : return -ENOENT;
6283 :
6284 : *speed = 60 * xclk * 10000 / tach_period;
6285 :
6286 : return 0;
6287 : }
6288 :
6289 : static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6290 : u32 speed)
6291 : {
6292 : u32 tach_period, tmp;
6293 : u32 xclk = radeon_get_xclk(rdev);
6294 :
6295 : if (rdev->pm.no_fan)
6296 : return -ENOENT;
6297 :
6298 : if (rdev->pm.fan_pulses_per_revolution == 0)
6299 : return -ENOENT;
6300 :
6301 : if ((speed < rdev->pm.fan_min_rpm) ||
6302 : (speed > rdev->pm.fan_max_rpm))
6303 : return -EINVAL;
6304 :
6305 : if (rdev->pm.dpm.fan.ucode_fan_control)
6306 : si_fan_ctrl_stop_smc_fan_control(rdev);
6307 :
6308 : tach_period = 60 * xclk * 10000 / (8 * speed);
6309 : tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6310 : tmp |= TARGET_PERIOD(tach_period);
6311 : WREG32(CG_TACH_CTRL, tmp);
6312 :
6313 : si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6314 :
6315 : return 0;
6316 : }
6317 : #endif
6318 :
6319 0 : static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6320 : {
6321 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6322 : u32 tmp;
6323 :
6324 0 : if (!si_pi->fan_ctrl_is_in_default_mode) {
6325 0 : tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6326 0 : tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6327 0 : WREG32(CG_FDO_CTRL2, tmp);
6328 :
6329 0 : tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6330 0 : tmp |= TMIN(si_pi->t_min);
6331 0 : WREG32(CG_FDO_CTRL2, tmp);
6332 0 : si_pi->fan_ctrl_is_in_default_mode = true;
6333 0 : }
6334 0 : }
6335 :
6336 0 : static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6337 : {
6338 0 : if (rdev->pm.dpm.fan.ucode_fan_control) {
6339 0 : si_fan_ctrl_start_smc_fan_control(rdev);
6340 0 : si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6341 0 : }
6342 0 : }
6343 :
6344 0 : static void si_thermal_initialize(struct radeon_device *rdev)
6345 : {
6346 : u32 tmp;
6347 :
6348 0 : if (rdev->pm.fan_pulses_per_revolution) {
6349 0 : tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6350 0 : tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6351 0 : WREG32(CG_TACH_CTRL, tmp);
6352 0 : }
6353 :
6354 0 : tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6355 0 : tmp |= TACH_PWM_RESP_RATE(0x28);
6356 0 : WREG32(CG_FDO_CTRL2, tmp);
6357 0 : }
6358 :
6359 0 : static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6360 : {
6361 : int ret;
6362 :
6363 0 : si_thermal_initialize(rdev);
6364 0 : ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6365 0 : if (ret)
6366 0 : return ret;
6367 0 : ret = si_thermal_enable_alert(rdev, true);
6368 0 : if (ret)
6369 0 : return ret;
6370 0 : if (rdev->pm.dpm.fan.ucode_fan_control) {
6371 0 : ret = si_halt_smc(rdev);
6372 0 : if (ret)
6373 0 : return ret;
6374 0 : ret = si_thermal_setup_fan_table(rdev);
6375 0 : if (ret)
6376 0 : return ret;
6377 0 : ret = si_resume_smc(rdev);
6378 0 : if (ret)
6379 0 : return ret;
6380 0 : si_thermal_start_smc_fan_control(rdev);
6381 0 : }
6382 :
6383 0 : return 0;
6384 0 : }
6385 :
6386 0 : static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6387 : {
6388 0 : if (!rdev->pm.no_fan) {
6389 0 : si_fan_ctrl_set_default_mode(rdev);
6390 0 : si_fan_ctrl_stop_smc_fan_control(rdev);
6391 0 : }
6392 0 : }
6393 :
6394 0 : int si_dpm_enable(struct radeon_device *rdev)
6395 : {
6396 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6397 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6398 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6399 0 : struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6400 : int ret;
6401 :
6402 0 : if (si_is_smc_running(rdev))
6403 0 : return -EINVAL;
6404 0 : if (pi->voltage_control || si_pi->voltage_control_svi2)
6405 0 : si_enable_voltage_control(rdev, true);
6406 0 : if (pi->mvdd_control)
6407 0 : si_get_mvdd_configuration(rdev);
6408 0 : if (pi->voltage_control || si_pi->voltage_control_svi2) {
6409 0 : ret = si_construct_voltage_tables(rdev);
6410 0 : if (ret) {
6411 0 : DRM_ERROR("si_construct_voltage_tables failed\n");
6412 0 : return ret;
6413 : }
6414 : }
6415 0 : if (eg_pi->dynamic_ac_timing) {
6416 0 : ret = si_initialize_mc_reg_table(rdev);
6417 0 : if (ret)
6418 0 : eg_pi->dynamic_ac_timing = false;
6419 : }
6420 0 : if (pi->dynamic_ss)
6421 0 : si_enable_spread_spectrum(rdev, true);
6422 0 : if (pi->thermal_protection)
6423 0 : si_enable_thermal_protection(rdev, true);
6424 0 : si_setup_bsp(rdev);
6425 0 : si_program_git(rdev);
6426 0 : si_program_tp(rdev);
6427 0 : si_program_tpp(rdev);
6428 0 : si_program_sstp(rdev);
6429 0 : si_enable_display_gap(rdev);
6430 0 : si_program_vc(rdev);
6431 0 : ret = si_upload_firmware(rdev);
6432 0 : if (ret) {
6433 0 : DRM_ERROR("si_upload_firmware failed\n");
6434 0 : return ret;
6435 : }
6436 0 : ret = si_process_firmware_header(rdev);
6437 0 : if (ret) {
6438 0 : DRM_ERROR("si_process_firmware_header failed\n");
6439 0 : return ret;
6440 : }
6441 0 : ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6442 0 : if (ret) {
6443 0 : DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6444 0 : return ret;
6445 : }
6446 0 : ret = si_init_smc_table(rdev);
6447 0 : if (ret) {
6448 0 : DRM_ERROR("si_init_smc_table failed\n");
6449 0 : return ret;
6450 : }
6451 0 : ret = si_init_smc_spll_table(rdev);
6452 0 : if (ret) {
6453 0 : DRM_ERROR("si_init_smc_spll_table failed\n");
6454 0 : return ret;
6455 : }
6456 0 : ret = si_init_arb_table_index(rdev);
6457 0 : if (ret) {
6458 0 : DRM_ERROR("si_init_arb_table_index failed\n");
6459 0 : return ret;
6460 : }
6461 0 : if (eg_pi->dynamic_ac_timing) {
6462 0 : ret = si_populate_mc_reg_table(rdev, boot_ps);
6463 0 : if (ret) {
6464 0 : DRM_ERROR("si_populate_mc_reg_table failed\n");
6465 0 : return ret;
6466 : }
6467 : }
6468 0 : ret = si_initialize_smc_cac_tables(rdev);
6469 0 : if (ret) {
6470 0 : DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6471 0 : return ret;
6472 : }
6473 0 : ret = si_initialize_hardware_cac_manager(rdev);
6474 0 : if (ret) {
6475 0 : DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6476 0 : return ret;
6477 : }
6478 0 : ret = si_initialize_smc_dte_tables(rdev);
6479 0 : if (ret) {
6480 0 : DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6481 0 : return ret;
6482 : }
6483 0 : ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6484 0 : if (ret) {
6485 0 : DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6486 0 : return ret;
6487 : }
6488 0 : ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6489 0 : if (ret) {
6490 0 : DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6491 0 : return ret;
6492 : }
6493 0 : si_program_response_times(rdev);
6494 0 : si_program_ds_registers(rdev);
6495 0 : si_dpm_start_smc(rdev);
6496 0 : ret = si_notify_smc_display_change(rdev, false);
6497 0 : if (ret) {
6498 0 : DRM_ERROR("si_notify_smc_display_change failed\n");
6499 0 : return ret;
6500 : }
6501 0 : si_enable_sclk_control(rdev, true);
6502 0 : si_start_dpm(rdev);
6503 :
6504 0 : si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6505 :
6506 0 : si_thermal_start_thermal_controller(rdev);
6507 :
6508 0 : ni_update_current_ps(rdev, boot_ps);
6509 :
6510 0 : return 0;
6511 0 : }
6512 :
6513 0 : static int si_set_temperature_range(struct radeon_device *rdev)
6514 : {
6515 : int ret;
6516 :
6517 0 : ret = si_thermal_enable_alert(rdev, false);
6518 0 : if (ret)
6519 0 : return ret;
6520 0 : ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6521 0 : if (ret)
6522 0 : return ret;
6523 0 : ret = si_thermal_enable_alert(rdev, true);
6524 : if (ret)
6525 0 : return ret;
6526 :
6527 : return ret;
6528 0 : }
6529 :
6530 0 : int si_dpm_late_enable(struct radeon_device *rdev)
6531 : {
6532 : int ret;
6533 :
6534 0 : ret = si_set_temperature_range(rdev);
6535 : if (ret)
6536 : return ret;
6537 :
6538 : return ret;
6539 0 : }
6540 :
6541 0 : void si_dpm_disable(struct radeon_device *rdev)
6542 : {
6543 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6544 0 : struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6545 :
6546 0 : if (!si_is_smc_running(rdev))
6547 0 : return;
6548 0 : si_thermal_stop_thermal_controller(rdev);
6549 0 : si_disable_ulv(rdev);
6550 0 : si_clear_vc(rdev);
6551 0 : if (pi->thermal_protection)
6552 0 : si_enable_thermal_protection(rdev, false);
6553 0 : si_enable_power_containment(rdev, boot_ps, false);
6554 0 : si_enable_smc_cac(rdev, boot_ps, false);
6555 0 : si_enable_spread_spectrum(rdev, false);
6556 0 : si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6557 0 : si_stop_dpm(rdev);
6558 0 : si_reset_to_default(rdev);
6559 0 : si_dpm_stop_smc(rdev);
6560 0 : si_force_switch_to_arb_f0(rdev);
6561 :
6562 0 : ni_update_current_ps(rdev, boot_ps);
6563 0 : }
6564 :
6565 0 : int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6566 : {
6567 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6568 0 : struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6569 : struct radeon_ps *new_ps = &requested_ps;
6570 :
6571 0 : ni_update_requested_ps(rdev, new_ps);
6572 :
6573 0 : si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6574 :
6575 0 : return 0;
6576 0 : }
6577 :
6578 0 : static int si_power_control_set_level(struct radeon_device *rdev)
6579 : {
6580 0 : struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6581 : int ret;
6582 :
6583 0 : ret = si_restrict_performance_levels_before_switch(rdev);
6584 0 : if (ret)
6585 0 : return ret;
6586 0 : ret = si_halt_smc(rdev);
6587 0 : if (ret)
6588 0 : return ret;
6589 0 : ret = si_populate_smc_tdp_limits(rdev, new_ps);
6590 0 : if (ret)
6591 0 : return ret;
6592 0 : ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6593 0 : if (ret)
6594 0 : return ret;
6595 0 : ret = si_resume_smc(rdev);
6596 0 : if (ret)
6597 0 : return ret;
6598 0 : ret = si_set_sw_state(rdev);
6599 0 : if (ret)
6600 0 : return ret;
6601 0 : return 0;
6602 0 : }
6603 :
6604 0 : int si_dpm_set_power_state(struct radeon_device *rdev)
6605 : {
6606 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6607 0 : struct radeon_ps *new_ps = &eg_pi->requested_rps;
6608 0 : struct radeon_ps *old_ps = &eg_pi->current_rps;
6609 : int ret;
6610 :
6611 0 : ret = si_disable_ulv(rdev);
6612 0 : if (ret) {
6613 0 : DRM_ERROR("si_disable_ulv failed\n");
6614 0 : return ret;
6615 : }
6616 0 : ret = si_restrict_performance_levels_before_switch(rdev);
6617 0 : if (ret) {
6618 0 : DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6619 0 : return ret;
6620 : }
6621 0 : if (eg_pi->pcie_performance_request)
6622 0 : si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6623 0 : ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6624 0 : ret = si_enable_power_containment(rdev, new_ps, false);
6625 0 : if (ret) {
6626 0 : DRM_ERROR("si_enable_power_containment failed\n");
6627 0 : return ret;
6628 : }
6629 0 : ret = si_enable_smc_cac(rdev, new_ps, false);
6630 0 : if (ret) {
6631 0 : DRM_ERROR("si_enable_smc_cac failed\n");
6632 0 : return ret;
6633 : }
6634 0 : ret = si_halt_smc(rdev);
6635 0 : if (ret) {
6636 0 : DRM_ERROR("si_halt_smc failed\n");
6637 0 : return ret;
6638 : }
6639 0 : ret = si_upload_sw_state(rdev, new_ps);
6640 0 : if (ret) {
6641 0 : DRM_ERROR("si_upload_sw_state failed\n");
6642 0 : return ret;
6643 : }
6644 0 : ret = si_upload_smc_data(rdev);
6645 0 : if (ret) {
6646 0 : DRM_ERROR("si_upload_smc_data failed\n");
6647 0 : return ret;
6648 : }
6649 0 : ret = si_upload_ulv_state(rdev);
6650 0 : if (ret) {
6651 0 : DRM_ERROR("si_upload_ulv_state failed\n");
6652 0 : return ret;
6653 : }
6654 0 : if (eg_pi->dynamic_ac_timing) {
6655 0 : ret = si_upload_mc_reg_table(rdev, new_ps);
6656 0 : if (ret) {
6657 0 : DRM_ERROR("si_upload_mc_reg_table failed\n");
6658 0 : return ret;
6659 : }
6660 : }
6661 0 : ret = si_program_memory_timing_parameters(rdev, new_ps);
6662 0 : if (ret) {
6663 0 : DRM_ERROR("si_program_memory_timing_parameters failed\n");
6664 0 : return ret;
6665 : }
6666 0 : si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6667 :
6668 0 : ret = si_resume_smc(rdev);
6669 0 : if (ret) {
6670 0 : DRM_ERROR("si_resume_smc failed\n");
6671 0 : return ret;
6672 : }
6673 0 : ret = si_set_sw_state(rdev);
6674 0 : if (ret) {
6675 0 : DRM_ERROR("si_set_sw_state failed\n");
6676 0 : return ret;
6677 : }
6678 0 : ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6679 0 : si_set_vce_clock(rdev, new_ps, old_ps);
6680 0 : if (eg_pi->pcie_performance_request)
6681 0 : si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6682 0 : ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6683 0 : if (ret) {
6684 0 : DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6685 0 : return ret;
6686 : }
6687 0 : ret = si_enable_smc_cac(rdev, new_ps, true);
6688 0 : if (ret) {
6689 0 : DRM_ERROR("si_enable_smc_cac failed\n");
6690 0 : return ret;
6691 : }
6692 0 : ret = si_enable_power_containment(rdev, new_ps, true);
6693 0 : if (ret) {
6694 0 : DRM_ERROR("si_enable_power_containment failed\n");
6695 0 : return ret;
6696 : }
6697 :
6698 0 : ret = si_power_control_set_level(rdev);
6699 0 : if (ret) {
6700 0 : DRM_ERROR("si_power_control_set_level failed\n");
6701 0 : return ret;
6702 : }
6703 :
6704 0 : return 0;
6705 0 : }
6706 :
6707 0 : void si_dpm_post_set_power_state(struct radeon_device *rdev)
6708 : {
6709 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6710 0 : struct radeon_ps *new_ps = &eg_pi->requested_rps;
6711 :
6712 0 : ni_update_current_ps(rdev, new_ps);
6713 0 : }
6714 :
6715 : #if 0
6716 : void si_dpm_reset_asic(struct radeon_device *rdev)
6717 : {
6718 : si_restrict_performance_levels_before_switch(rdev);
6719 : si_disable_ulv(rdev);
6720 : si_set_boot_state(rdev);
6721 : }
6722 : #endif
6723 :
6724 0 : void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6725 : {
6726 0 : si_program_display_gap(rdev);
6727 0 : }
6728 :
6729 : union power_info {
6730 : struct _ATOM_POWERPLAY_INFO info;
6731 : struct _ATOM_POWERPLAY_INFO_V2 info_2;
6732 : struct _ATOM_POWERPLAY_INFO_V3 info_3;
6733 : struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6734 : struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6735 : struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6736 : };
6737 :
6738 : union pplib_clock_info {
6739 : struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6740 : struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6741 : struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6742 : struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6743 : struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6744 : };
6745 :
6746 : union pplib_power_state {
6747 : struct _ATOM_PPLIB_STATE v1;
6748 : struct _ATOM_PPLIB_STATE_V2 v2;
6749 : };
6750 :
6751 0 : static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6752 : struct radeon_ps *rps,
6753 : struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6754 : u8 table_rev)
6755 : {
6756 0 : rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6757 0 : rps->class = le16_to_cpu(non_clock_info->usClassification);
6758 0 : rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6759 :
6760 0 : if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6761 0 : rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6762 0 : rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6763 0 : } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6764 0 : rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6765 0 : rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6766 0 : } else {
6767 0 : rps->vclk = 0;
6768 0 : rps->dclk = 0;
6769 : }
6770 :
6771 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6772 0 : rdev->pm.dpm.boot_ps = rps;
6773 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6774 0 : rdev->pm.dpm.uvd_ps = rps;
6775 0 : }
6776 :
6777 0 : static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6778 : struct radeon_ps *rps, int index,
6779 : union pplib_clock_info *clock_info)
6780 : {
6781 0 : struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6782 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6783 0 : struct si_power_info *si_pi = si_get_pi(rdev);
6784 0 : struct ni_ps *ps = ni_get_ps(rps);
6785 0 : u16 leakage_voltage;
6786 0 : struct rv7xx_pl *pl = &ps->performance_levels[index];
6787 : int ret;
6788 :
6789 0 : ps->performance_level_count = index + 1;
6790 :
6791 0 : pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6792 0 : pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6793 0 : pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6794 0 : pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6795 :
6796 0 : pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6797 0 : pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6798 0 : pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6799 0 : pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6800 0 : si_pi->sys_pcie_mask,
6801 0 : si_pi->boot_pcie_gen,
6802 0 : clock_info->si.ucPCIEGen);
6803 :
6804 : /* patch up vddc if necessary */
6805 0 : ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6806 : &leakage_voltage);
6807 0 : if (ret == 0)
6808 0 : pl->vddc = leakage_voltage;
6809 :
6810 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6811 0 : pi->acpi_vddc = pl->vddc;
6812 0 : eg_pi->acpi_vddci = pl->vddci;
6813 0 : si_pi->acpi_pcie_gen = pl->pcie_gen;
6814 0 : }
6815 :
6816 0 : if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6817 0 : index == 0) {
6818 : /* XXX disable for A0 tahiti */
6819 0 : si_pi->ulv.supported = false;
6820 0 : si_pi->ulv.pl = *pl;
6821 0 : si_pi->ulv.one_pcie_lane_in_ulv = false;
6822 0 : si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6823 0 : si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6824 0 : si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6825 0 : }
6826 :
6827 0 : if (pi->min_vddc_in_table > pl->vddc)
6828 0 : pi->min_vddc_in_table = pl->vddc;
6829 :
6830 0 : if (pi->max_vddc_in_table < pl->vddc)
6831 0 : pi->max_vddc_in_table = pl->vddc;
6832 :
6833 : /* patch up boot state */
6834 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6835 0 : u16 vddc, vddci, mvdd;
6836 0 : radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6837 0 : pl->mclk = rdev->clock.default_mclk;
6838 0 : pl->sclk = rdev->clock.default_sclk;
6839 0 : pl->vddc = vddc;
6840 0 : pl->vddci = vddci;
6841 0 : si_pi->mvdd_bootup_value = mvdd;
6842 0 : }
6843 :
6844 0 : if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6845 : ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6846 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6847 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6848 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6849 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6850 0 : }
6851 0 : }
6852 :
6853 0 : static int si_parse_power_table(struct radeon_device *rdev)
6854 : {
6855 0 : struct radeon_mode_info *mode_info = &rdev->mode_info;
6856 : struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6857 : union pplib_power_state *power_state;
6858 : int i, j, k, non_clock_array_index, clock_array_index;
6859 : union pplib_clock_info *clock_info;
6860 : struct _StateArray *state_array;
6861 : struct _ClockInfoArray *clock_info_array;
6862 : struct _NonClockInfoArray *non_clock_info_array;
6863 : union power_info *power_info;
6864 : int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6865 0 : u16 data_offset;
6866 0 : u8 frev, crev;
6867 : u8 *power_state_offset;
6868 : struct ni_ps *ps;
6869 :
6870 0 : if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6871 : &frev, &crev, &data_offset))
6872 0 : return -EINVAL;
6873 0 : power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6874 :
6875 0 : state_array = (struct _StateArray *)
6876 0 : (mode_info->atom_context->bios + data_offset +
6877 0 : le16_to_cpu(power_info->pplib.usStateArrayOffset));
6878 0 : clock_info_array = (struct _ClockInfoArray *)
6879 0 : (mode_info->atom_context->bios + data_offset +
6880 0 : le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6881 0 : non_clock_info_array = (struct _NonClockInfoArray *)
6882 0 : (mode_info->atom_context->bios + data_offset +
6883 0 : le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6884 :
6885 0 : rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6886 0 : state_array->ucNumEntries, GFP_KERNEL);
6887 0 : if (!rdev->pm.dpm.ps)
6888 0 : return -ENOMEM;
6889 0 : power_state_offset = (u8 *)state_array->states;
6890 0 : for (i = 0; i < state_array->ucNumEntries; i++) {
6891 : u8 *idx;
6892 0 : power_state = (union pplib_power_state *)power_state_offset;
6893 0 : non_clock_array_index = power_state->v2.nonClockInfoIndex;
6894 : non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6895 0 : &non_clock_info_array->nonClockInfo[non_clock_array_index];
6896 0 : if (!rdev->pm.power_state[i].clock_info)
6897 0 : return -EINVAL;
6898 0 : ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6899 0 : if (ps == NULL) {
6900 0 : kfree(rdev->pm.dpm.ps);
6901 0 : return -ENOMEM;
6902 : }
6903 0 : rdev->pm.dpm.ps[i].ps_priv = ps;
6904 0 : si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6905 : non_clock_info,
6906 0 : non_clock_info_array->ucEntrySize);
6907 : k = 0;
6908 0 : idx = (u8 *)&power_state->v2.clockInfoIndex[0];
6909 0 : for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6910 0 : clock_array_index = idx[j];
6911 0 : if (clock_array_index >= clock_info_array->ucNumEntries)
6912 : continue;
6913 0 : if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6914 : break;
6915 0 : clock_info = (union pplib_clock_info *)
6916 0 : ((u8 *)&clock_info_array->clockInfo[0] +
6917 0 : (clock_array_index * clock_info_array->ucEntrySize));
6918 0 : si_parse_pplib_clock_info(rdev,
6919 0 : &rdev->pm.dpm.ps[i], k,
6920 : clock_info);
6921 0 : k++;
6922 0 : }
6923 0 : power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6924 0 : }
6925 0 : rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6926 :
6927 : /* fill in the vce power states */
6928 0 : for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
6929 : u32 sclk, mclk;
6930 0 : clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6931 0 : clock_info = (union pplib_clock_info *)
6932 0 : &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6933 0 : sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6934 0 : sclk |= clock_info->si.ucEngineClockHigh << 16;
6935 0 : mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6936 0 : mclk |= clock_info->si.ucMemoryClockHigh << 16;
6937 0 : rdev->pm.dpm.vce_states[i].sclk = sclk;
6938 0 : rdev->pm.dpm.vce_states[i].mclk = mclk;
6939 : }
6940 :
6941 0 : return 0;
6942 0 : }
6943 :
6944 0 : int si_dpm_init(struct radeon_device *rdev)
6945 : {
6946 : struct rv7xx_power_info *pi;
6947 : struct evergreen_power_info *eg_pi;
6948 : struct ni_power_info *ni_pi;
6949 : struct si_power_info *si_pi;
6950 0 : struct atom_clock_dividers dividers;
6951 : int ret;
6952 0 : u32 mask;
6953 :
6954 0 : si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6955 0 : if (si_pi == NULL)
6956 0 : return -ENOMEM;
6957 0 : rdev->pm.dpm.priv = si_pi;
6958 0 : ni_pi = &si_pi->ni;
6959 0 : eg_pi = &ni_pi->eg;
6960 0 : pi = &eg_pi->rv7xx;
6961 :
6962 0 : ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6963 0 : if (ret)
6964 0 : si_pi->sys_pcie_mask = 0;
6965 : else
6966 0 : si_pi->sys_pcie_mask = mask;
6967 0 : si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6968 0 : si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6969 :
6970 0 : si_set_max_cu_value(rdev);
6971 :
6972 0 : rv770_get_max_vddc(rdev);
6973 0 : si_get_leakage_vddc(rdev);
6974 0 : si_patch_dependency_tables_based_on_leakage(rdev);
6975 :
6976 0 : pi->acpi_vddc = 0;
6977 0 : eg_pi->acpi_vddci = 0;
6978 0 : pi->min_vddc_in_table = 0;
6979 0 : pi->max_vddc_in_table = 0;
6980 :
6981 0 : ret = r600_get_platform_caps(rdev);
6982 0 : if (ret)
6983 0 : return ret;
6984 :
6985 0 : ret = r600_parse_extended_power_table(rdev);
6986 0 : if (ret)
6987 0 : return ret;
6988 :
6989 0 : ret = si_parse_power_table(rdev);
6990 0 : if (ret)
6991 0 : return ret;
6992 :
6993 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6994 0 : kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6995 0 : if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6996 0 : r600_free_extended_power_table(rdev);
6997 0 : return -ENOMEM;
6998 : }
6999 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7000 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7001 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7002 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7003 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7004 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7005 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7006 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7007 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7008 :
7009 0 : if (rdev->pm.dpm.voltage_response_time == 0)
7010 0 : rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7011 0 : if (rdev->pm.dpm.backbias_response_time == 0)
7012 0 : rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7013 :
7014 0 : ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
7015 : 0, false, ÷rs);
7016 0 : if (ret)
7017 0 : pi->ref_div = dividers.ref_div + 1;
7018 : else
7019 0 : pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7020 :
7021 0 : eg_pi->smu_uvd_hs = false;
7022 :
7023 0 : pi->mclk_strobe_mode_threshold = 40000;
7024 0 : if (si_is_special_1gb_platform(rdev))
7025 0 : pi->mclk_stutter_mode_threshold = 0;
7026 : else
7027 0 : pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7028 0 : pi->mclk_edc_enable_threshold = 40000;
7029 0 : eg_pi->mclk_edc_wr_enable_threshold = 40000;
7030 :
7031 0 : ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7032 :
7033 0 : pi->voltage_control =
7034 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7035 : VOLTAGE_OBJ_GPIO_LUT);
7036 0 : if (!pi->voltage_control) {
7037 0 : si_pi->voltage_control_svi2 =
7038 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7039 : VOLTAGE_OBJ_SVID2);
7040 0 : if (si_pi->voltage_control_svi2)
7041 0 : radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7042 0 : &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7043 : }
7044 :
7045 0 : pi->mvdd_control =
7046 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7047 : VOLTAGE_OBJ_GPIO_LUT);
7048 :
7049 0 : eg_pi->vddci_control =
7050 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7051 : VOLTAGE_OBJ_GPIO_LUT);
7052 0 : if (!eg_pi->vddci_control)
7053 0 : si_pi->vddci_control_svi2 =
7054 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7055 : VOLTAGE_OBJ_SVID2);
7056 :
7057 0 : si_pi->vddc_phase_shed_control =
7058 0 : radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7059 : VOLTAGE_OBJ_PHASE_LUT);
7060 :
7061 0 : rv770_get_engine_memory_ss(rdev);
7062 :
7063 0 : pi->asi = RV770_ASI_DFLT;
7064 0 : pi->pasi = CYPRESS_HASI_DFLT;
7065 0 : pi->vrc = SISLANDS_VRC_DFLT;
7066 :
7067 0 : pi->gfx_clock_gating = true;
7068 :
7069 0 : eg_pi->sclk_deep_sleep = true;
7070 0 : si_pi->sclk_deep_sleep_above_low = false;
7071 :
7072 0 : if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7073 0 : pi->thermal_protection = true;
7074 : else
7075 0 : pi->thermal_protection = false;
7076 :
7077 0 : eg_pi->dynamic_ac_timing = true;
7078 :
7079 0 : eg_pi->light_sleep = true;
7080 : #if defined(CONFIG_ACPI)
7081 : eg_pi->pcie_performance_request =
7082 : radeon_acpi_is_pcie_performance_request_supported(rdev);
7083 : #else
7084 0 : eg_pi->pcie_performance_request = false;
7085 : #endif
7086 :
7087 0 : si_pi->sram_end = SMC_RAM_END;
7088 :
7089 0 : rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7090 0 : rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7091 0 : rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7092 0 : rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7093 0 : rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7094 0 : rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7095 0 : rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7096 :
7097 0 : si_initialize_powertune_defaults(rdev);
7098 :
7099 : /* make sure dc limits are valid */
7100 0 : if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7101 0 : (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7102 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7103 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7104 :
7105 0 : si_pi->fan_ctrl_is_in_default_mode = true;
7106 :
7107 0 : return 0;
7108 0 : }
7109 :
7110 0 : void si_dpm_fini(struct radeon_device *rdev)
7111 : {
7112 : int i;
7113 :
7114 0 : for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7115 0 : kfree(rdev->pm.dpm.ps[i].ps_priv);
7116 : }
7117 0 : kfree(rdev->pm.dpm.ps);
7118 0 : kfree(rdev->pm.dpm.priv);
7119 0 : kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7120 0 : r600_free_extended_power_table(rdev);
7121 0 : }
7122 :
7123 0 : void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7124 : struct seq_file *m)
7125 : {
7126 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7127 0 : struct radeon_ps *rps = &eg_pi->current_rps;
7128 0 : struct ni_ps *ps = ni_get_ps(rps);
7129 : struct rv7xx_pl *pl;
7130 : u32 current_index =
7131 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7132 : CURRENT_STATE_INDEX_SHIFT;
7133 :
7134 0 : if (current_index >= ps->performance_level_count) {
7135 0 : seq_printf(m, "invalid dpm profile %d\n", current_index);
7136 0 : } else {
7137 0 : pl = &ps->performance_levels[current_index];
7138 0 : seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7139 0 : seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7140 0 : current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7141 : }
7142 0 : }
7143 :
7144 0 : u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7145 : {
7146 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7147 0 : struct radeon_ps *rps = &eg_pi->current_rps;
7148 0 : struct ni_ps *ps = ni_get_ps(rps);
7149 : struct rv7xx_pl *pl;
7150 : u32 current_index =
7151 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7152 : CURRENT_STATE_INDEX_SHIFT;
7153 :
7154 0 : if (current_index >= ps->performance_level_count) {
7155 0 : return 0;
7156 : } else {
7157 0 : pl = &ps->performance_levels[current_index];
7158 0 : return pl->sclk;
7159 : }
7160 0 : }
7161 :
7162 0 : u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7163 : {
7164 0 : struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7165 0 : struct radeon_ps *rps = &eg_pi->current_rps;
7166 0 : struct ni_ps *ps = ni_get_ps(rps);
7167 : struct rv7xx_pl *pl;
7168 : u32 current_index =
7169 0 : (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7170 : CURRENT_STATE_INDEX_SHIFT;
7171 :
7172 0 : if (current_index >= ps->performance_level_count) {
7173 0 : return 0;
7174 : } else {
7175 0 : pl = &ps->performance_levels[current_index];
7176 0 : return pl->mclk;
7177 : }
7178 0 : }
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