Line data Source code
1 : /*
2 : * Copyright 2013 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : * Authors: Christian König <christian.koenig@amd.com>
23 : */
24 :
25 : #include <dev/pci/drm/drmP.h>
26 : #include "radeon.h"
27 : #include "radeon_asic.h"
28 : #include "rv770d.h"
29 :
30 : /**
31 : * uvd_v2_2_fence_emit - emit an fence & trap command
32 : *
33 : * @rdev: radeon_device pointer
34 : * @fence: fence to emit
35 : *
36 : * Write a fence and a trap command to the ring.
37 : */
38 0 : void uvd_v2_2_fence_emit(struct radeon_device *rdev,
39 : struct radeon_fence *fence)
40 : {
41 0 : struct radeon_ring *ring = &rdev->ring[fence->ring];
42 0 : uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
43 :
44 0 : radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
45 0 : radeon_ring_write(ring, fence->seq);
46 0 : radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
47 0 : radeon_ring_write(ring, lower_32_bits(addr));
48 0 : radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
49 0 : radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
50 0 : radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
51 0 : radeon_ring_write(ring, 0);
52 :
53 0 : radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
54 0 : radeon_ring_write(ring, 0);
55 0 : radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
56 0 : radeon_ring_write(ring, 0);
57 0 : radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
58 0 : radeon_ring_write(ring, 2);
59 0 : }
60 :
61 : /**
62 : * uvd_v2_2_semaphore_emit - emit semaphore command
63 : *
64 : * @rdev: radeon_device pointer
65 : * @ring: radeon_ring pointer
66 : * @semaphore: semaphore to emit commands for
67 : * @emit_wait: true if we should emit a wait command
68 : *
69 : * Emit a semaphore command (either wait or signal) to the UVD ring.
70 : */
71 0 : bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
72 : struct radeon_ring *ring,
73 : struct radeon_semaphore *semaphore,
74 : bool emit_wait)
75 : {
76 0 : uint64_t addr = semaphore->gpu_addr;
77 :
78 0 : radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
79 0 : radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
80 :
81 0 : radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
82 0 : radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
83 :
84 0 : radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
85 0 : radeon_ring_write(ring, emit_wait ? 1 : 0);
86 :
87 0 : return true;
88 : }
89 :
90 : /**
91 : * uvd_v2_2_resume - memory controller programming
92 : *
93 : * @rdev: radeon_device pointer
94 : *
95 : * Let the UVD memory controller know it's offsets
96 : */
97 0 : int uvd_v2_2_resume(struct radeon_device *rdev)
98 : {
99 : uint64_t addr;
100 : uint32_t chip_id, size;
101 : int r;
102 :
103 : /* RV770 uses V1.0 MC */
104 0 : if (rdev->family == CHIP_RV770)
105 0 : return uvd_v1_0_resume(rdev);
106 :
107 0 : r = radeon_uvd_resume(rdev);
108 0 : if (r)
109 0 : return r;
110 :
111 : /* programm the VCPU memory controller bits 0-27 */
112 0 : addr = rdev->uvd.gpu_addr >> 3;
113 0 : size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
114 0 : WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
115 0 : WREG32(UVD_VCPU_CACHE_SIZE0, size);
116 :
117 0 : addr += size;
118 : size = RADEON_UVD_STACK_SIZE >> 3;
119 0 : WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
120 0 : WREG32(UVD_VCPU_CACHE_SIZE1, size);
121 :
122 0 : addr += size;
123 : size = RADEON_UVD_HEAP_SIZE >> 3;
124 0 : WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
125 0 : WREG32(UVD_VCPU_CACHE_SIZE2, size);
126 :
127 : /* bits 28-31 */
128 0 : addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
129 0 : WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
130 :
131 : /* bits 32-39 */
132 0 : addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
133 0 : WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
134 :
135 : /* tell firmware which hardware it is running on */
136 0 : switch (rdev->family) {
137 : default:
138 0 : return -EINVAL;
139 : case CHIP_RV710:
140 : chip_id = 0x01000005;
141 0 : break;
142 : case CHIP_RV730:
143 : chip_id = 0x01000006;
144 0 : break;
145 : case CHIP_RV740:
146 : chip_id = 0x01000007;
147 0 : break;
148 : case CHIP_CYPRESS:
149 : case CHIP_HEMLOCK:
150 : chip_id = 0x01000008;
151 0 : break;
152 : case CHIP_JUNIPER:
153 : chip_id = 0x01000009;
154 0 : break;
155 : case CHIP_REDWOOD:
156 : chip_id = 0x0100000a;
157 0 : break;
158 : case CHIP_CEDAR:
159 : chip_id = 0x0100000b;
160 0 : break;
161 : case CHIP_SUMO:
162 : case CHIP_SUMO2:
163 : chip_id = 0x0100000c;
164 0 : break;
165 : case CHIP_PALM:
166 : chip_id = 0x0100000e;
167 0 : break;
168 : case CHIP_CAYMAN:
169 : chip_id = 0x0100000f;
170 0 : break;
171 : case CHIP_BARTS:
172 : chip_id = 0x01000010;
173 0 : break;
174 : case CHIP_TURKS:
175 : chip_id = 0x01000011;
176 0 : break;
177 : case CHIP_CAICOS:
178 : chip_id = 0x01000012;
179 0 : break;
180 : case CHIP_TAHITI:
181 : chip_id = 0x01000014;
182 0 : break;
183 : case CHIP_VERDE:
184 : chip_id = 0x01000015;
185 0 : break;
186 : case CHIP_PITCAIRN:
187 : case CHIP_OLAND:
188 : chip_id = 0x01000016;
189 0 : break;
190 : case CHIP_ARUBA:
191 : chip_id = 0x01000017;
192 0 : break;
193 : }
194 0 : WREG32(UVD_VCPU_CHIP_ID, chip_id);
195 :
196 0 : return 0;
197 0 : }
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