Line data Source code
1 : /*******************************************************************************
2 :
3 : Copyright (c) 2001-2005, Intel Corporation
4 : All rights reserved.
5 :
6 : Redistribution and use in source and binary forms, with or without
7 : modification, are permitted provided that the following conditions are met:
8 :
9 : 1. Redistributions of source code must retain the above copyright notice,
10 : this list of conditions and the following disclaimer.
11 :
12 : 2. Redistributions in binary form must reproduce the above copyright
13 : notice, this list of conditions and the following disclaimer in the
14 : documentation and/or other materials provided with the distribution.
15 :
16 : 3. Neither the name of the Intel Corporation nor the names of its
17 : contributors may be used to endorse or promote products derived from
18 : this software without specific prior written permission.
19 :
20 : THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 : AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 : IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 : ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 : LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 : CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 : SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 : INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 : CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 : ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 : POSSIBILITY OF SUCH DAMAGE.
31 :
32 : *******************************************************************************/
33 :
34 : /* $OpenBSD: if_em_hw.c,v 1.102 2018/04/29 08:47:10 sf Exp $ */
35 : /*
36 : * if_em_hw.c Shared functions for accessing and configuring the MAC
37 : */
38 :
39 : #include <sys/param.h>
40 : #include <sys/systm.h>
41 : #include <sys/sockio.h>
42 : #include <sys/mbuf.h>
43 : #include <sys/malloc.h>
44 : #include <sys/kernel.h>
45 : #include <sys/device.h>
46 : #include <sys/socket.h>
47 :
48 : #include <net/if.h>
49 : #include <net/if_media.h>
50 :
51 : #include <netinet/in.h>
52 : #include <netinet/if_ether.h>
53 :
54 : #include <uvm/uvm_extern.h>
55 :
56 : #include <dev/pci/pcireg.h>
57 : #include <dev/pci/pcivar.h>
58 :
59 : #include <dev/pci/if_em_hw.h>
60 : #include <dev/pci/if_em_soc.h>
61 :
62 : #include <dev/mii/rgephyreg.h>
63 :
64 : #define STATIC
65 :
66 : static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t);
67 : static void em_swfw_sync_release(struct em_hw *, uint16_t);
68 : static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *);
69 : static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t);
70 : static int32_t em_get_software_semaphore(struct em_hw *);
71 : static void em_release_software_semaphore(struct em_hw *);
72 :
73 : static int32_t em_check_downshift(struct em_hw *);
74 : static void em_clear_vfta(struct em_hw *);
75 : void em_clear_vfta_i350(struct em_hw *);
76 : static int32_t em_commit_shadow_ram(struct em_hw *);
77 : static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t);
78 : static int32_t em_config_fc_after_link_up(struct em_hw *);
79 : static int32_t em_match_gig_phy(struct em_hw *);
80 : static int32_t em_detect_gig_phy(struct em_hw *);
81 : static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t);
82 : static int32_t em_get_auto_rd_done(struct em_hw *);
83 : static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *);
84 : static int32_t em_get_hw_eeprom_semaphore(struct em_hw *);
85 : static int32_t em_get_phy_cfg_done(struct em_hw *);
86 : static int32_t em_get_software_flag(struct em_hw *);
87 : static int32_t em_ich8_cycle_init(struct em_hw *);
88 : static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t);
89 : static int32_t em_id_led_init(struct em_hw *);
90 : static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t,
91 : uint32_t);
92 : static int32_t em_init_lcd_from_nvm(struct em_hw *);
93 : static int32_t em_phy_no_cable_workaround(struct em_hw *);
94 : static void em_init_rx_addrs(struct em_hw *);
95 : static void em_initialize_hardware_bits(struct em_hw *);
96 : static void em_toggle_lanphypc_pch_lpt(struct em_hw *);
97 : static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force);
98 : static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *);
99 : static int32_t em_kumeran_lock_loss_workaround(struct em_hw *);
100 : static int32_t em_mng_enable_host_if(struct em_hw *);
101 : static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t,
102 : uint16_t *);
103 : static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t,
104 : uint16_t *data);
105 : static int32_t em_poll_eerd_eewr_done(struct em_hw *, int);
106 : static void em_put_hw_eeprom_semaphore(struct em_hw *);
107 : static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *);
108 : static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
109 : static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
110 : static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *);
111 : static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *);
112 : static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t,
113 : uint16_t *);
114 : static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t,
115 : uint16_t);
116 : static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
117 : uint16_t *);
118 : static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
119 : uint16_t *);
120 : static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t,
121 : uint16_t *);
122 : static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *);
123 : static void em_release_software_flag(struct em_hw *);
124 : static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t);
125 : static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t);
126 : static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t);
127 : static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t);
128 : static void em_set_pci_express_master_disable(struct em_hw *);
129 : static int32_t em_wait_autoneg(struct em_hw *);
130 : static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t);
131 : static int32_t em_set_phy_type(struct em_hw *);
132 : static void em_phy_init_script(struct em_hw *);
133 : static int32_t em_setup_copper_link(struct em_hw *);
134 : static int32_t em_setup_fiber_serdes_link(struct em_hw *);
135 : static int32_t em_adjust_serdes_amplitude(struct em_hw *);
136 : static int32_t em_phy_force_speed_duplex(struct em_hw *);
137 : static int32_t em_config_mac_to_phy(struct em_hw *);
138 : static void em_raise_mdi_clk(struct em_hw *, uint32_t *);
139 : static void em_lower_mdi_clk(struct em_hw *, uint32_t *);
140 : static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t);
141 : static uint16_t em_shift_in_mdi_bits(struct em_hw *);
142 : static int32_t em_phy_reset_dsp(struct em_hw *);
143 : static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t,
144 : uint16_t *);
145 : static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t,
146 : uint16_t *);
147 : static int32_t em_spi_eeprom_ready(struct em_hw *);
148 : static void em_raise_ee_clk(struct em_hw *, uint32_t *);
149 : static void em_lower_ee_clk(struct em_hw *, uint32_t *);
150 : static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t);
151 : static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t);
152 : static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *);
153 : static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t);
154 : static int32_t em_acquire_eeprom(struct em_hw *);
155 : static void em_release_eeprom(struct em_hw *);
156 : static void em_standby_eeprom(struct em_hw *);
157 : static int32_t em_set_vco_speed(struct em_hw *);
158 : static int32_t em_polarity_reversal_workaround(struct em_hw *);
159 : static int32_t em_set_phy_mode(struct em_hw *);
160 : static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *);
161 : static uint8_t em_calculate_mng_checksum(char *, uint32_t);
162 : static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t);
163 : static int32_t em_configure_kmrn_for_1000(struct em_hw *);
164 : static int32_t em_set_pciex_completion_timeout(struct em_hw *hw);
165 : static int32_t em_set_mdio_slow_mode_hv(struct em_hw *);
166 : int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *);
167 : int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *);
168 : int32_t em_link_stall_workaround_hv(struct em_hw *);
169 : int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t);
170 : int32_t em_k1_workaround_lv(struct em_hw *);
171 : int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t);
172 : int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t);
173 : void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t);
174 : int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t,
175 : uint16_t *, boolean_t);
176 : int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t,
177 : uint16_t *, boolean_t);
178 : int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *,
179 : boolean_t);
180 : int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t);
181 : void em_power_up_serdes_link_82575(struct em_hw *);
182 : int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *,
183 : uint16_t *);
184 : int32_t em_set_eee_i350(struct em_hw *);
185 : int32_t em_set_eee_pchlan(struct em_hw *);
186 : int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *);
187 : int32_t em_initialize_M88E1512_phy(struct em_hw *);
188 :
189 : /* IGP cable length table */
190 : static const uint16_t
191 : em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
192 : {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
193 : 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
194 : 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
195 : 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
196 : 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
197 : 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
198 : 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
199 : 110,
200 : 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120,
201 : 120};
202 :
203 : static const uint16_t
204 : em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
205 : {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
206 : 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
207 : 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
208 : 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
209 : 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
210 : 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
211 : 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118,
212 : 121, 124};
213 :
214 : /******************************************************************************
215 : * Set the phy type member in the hw struct.
216 : *
217 : * hw - Struct containing variables accessed by shared code
218 : *****************************************************************************/
219 : STATIC int32_t
220 0 : em_set_phy_type(struct em_hw *hw)
221 : {
222 : DEBUGFUNC("em_set_phy_type");
223 :
224 0 : if (hw->mac_type == em_undefined)
225 0 : return -E1000_ERR_PHY_TYPE;
226 :
227 0 : switch (hw->phy_id) {
228 : case M88E1000_E_PHY_ID:
229 : case M88E1000_I_PHY_ID:
230 : case M88E1011_I_PHY_ID:
231 : case M88E1111_I_PHY_ID:
232 : case M88E1112_E_PHY_ID:
233 : case M88E1543_E_PHY_ID:
234 : case M88E1512_E_PHY_ID:
235 : case I210_I_PHY_ID:
236 : case I347AT4_E_PHY_ID:
237 0 : hw->phy_type = em_phy_m88;
238 0 : break;
239 : case IGP01E1000_I_PHY_ID:
240 0 : if (hw->mac_type == em_82541 ||
241 0 : hw->mac_type == em_82541_rev_2 ||
242 0 : hw->mac_type == em_82547 ||
243 0 : hw->mac_type == em_82547_rev_2) {
244 0 : hw->phy_type = em_phy_igp;
245 0 : break;
246 : }
247 : case IGP03E1000_E_PHY_ID:
248 : case IGP04E1000_E_PHY_ID:
249 0 : hw->phy_type = em_phy_igp_3;
250 0 : break;
251 : case IFE_E_PHY_ID:
252 : case IFE_PLUS_E_PHY_ID:
253 : case IFE_C_E_PHY_ID:
254 0 : hw->phy_type = em_phy_ife;
255 0 : break;
256 : case M88E1141_E_PHY_ID:
257 0 : hw->phy_type = em_phy_oem;
258 0 : break;
259 : case I82577_E_PHY_ID:
260 0 : hw->phy_type = em_phy_82577;
261 0 : break;
262 : case I82578_E_PHY_ID:
263 0 : hw->phy_type = em_phy_82578;
264 0 : break;
265 : case I82579_E_PHY_ID:
266 0 : hw->phy_type = em_phy_82579;
267 0 : break;
268 : case I217_E_PHY_ID:
269 0 : hw->phy_type = em_phy_i217;
270 0 : break;
271 : case I82580_I_PHY_ID:
272 : case I350_I_PHY_ID:
273 0 : hw->phy_type = em_phy_82580;
274 0 : break;
275 : case RTL8211_E_PHY_ID:
276 0 : hw->phy_type = em_phy_rtl8211;
277 0 : break;
278 : case BME1000_E_PHY_ID:
279 0 : if (hw->phy_revision == 1) {
280 0 : hw->phy_type = em_phy_bm;
281 0 : break;
282 : }
283 : /* FALLTHROUGH */
284 : case GG82563_E_PHY_ID:
285 0 : if (hw->mac_type == em_80003es2lan) {
286 0 : hw->phy_type = em_phy_gg82563;
287 0 : break;
288 : }
289 : /* FALLTHROUGH */
290 : default:
291 : /* Should never have loaded on this device */
292 0 : hw->phy_type = em_phy_undefined;
293 0 : return -E1000_ERR_PHY_TYPE;
294 : }
295 :
296 0 : return E1000_SUCCESS;
297 0 : }
298 :
299 : /******************************************************************************
300 : * IGP phy init script - initializes the GbE PHY
301 : *
302 : * hw - Struct containing variables accessed by shared code
303 : *****************************************************************************/
304 : static void
305 0 : em_phy_init_script(struct em_hw *hw)
306 : {
307 0 : uint16_t phy_saved_data;
308 : DEBUGFUNC("em_phy_init_script");
309 :
310 0 : if (hw->phy_init_script) {
311 0 : msec_delay(20);
312 : /*
313 : * Save off the current value of register 0x2F5B to be
314 : * restored at the end of this routine.
315 : */
316 0 : em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
317 :
318 : /* Disabled the PHY transmitter */
319 0 : em_write_phy_reg(hw, 0x2F5B, 0x0003);
320 0 : msec_delay(20);
321 0 : em_write_phy_reg(hw, 0x0000, 0x0140);
322 0 : msec_delay(5);
323 :
324 0 : switch (hw->mac_type) {
325 : case em_82541:
326 : case em_82547:
327 0 : em_write_phy_reg(hw, 0x1F95, 0x0001);
328 0 : em_write_phy_reg(hw, 0x1F71, 0xBD21);
329 0 : em_write_phy_reg(hw, 0x1F79, 0x0018);
330 0 : em_write_phy_reg(hw, 0x1F30, 0x1600);
331 0 : em_write_phy_reg(hw, 0x1F31, 0x0014);
332 0 : em_write_phy_reg(hw, 0x1F32, 0x161C);
333 0 : em_write_phy_reg(hw, 0x1F94, 0x0003);
334 0 : em_write_phy_reg(hw, 0x1F96, 0x003F);
335 0 : em_write_phy_reg(hw, 0x2010, 0x0008);
336 0 : break;
337 : case em_82541_rev_2:
338 : case em_82547_rev_2:
339 0 : em_write_phy_reg(hw, 0x1F73, 0x0099);
340 0 : break;
341 : default:
342 : break;
343 : }
344 :
345 0 : em_write_phy_reg(hw, 0x0000, 0x3300);
346 0 : msec_delay(20);
347 :
348 : /* Now enable the transmitter */
349 0 : em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
350 :
351 0 : if (hw->mac_type == em_82547) {
352 0 : uint16_t fused, fine, coarse;
353 : /* Move to analog registers page */
354 0 : em_read_phy_reg(hw,
355 : IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
356 :
357 0 : if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
358 0 : em_read_phy_reg(hw,
359 : IGP01E1000_ANALOG_FUSE_STATUS, &fused);
360 :
361 0 : fine = fused &
362 : IGP01E1000_ANALOG_FUSE_FINE_MASK;
363 0 : coarse = fused &
364 : IGP01E1000_ANALOG_FUSE_COARSE_MASK;
365 :
366 0 : if (coarse >
367 : IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
368 0 : coarse -=
369 : IGP01E1000_ANALOG_FUSE_COARSE_10;
370 0 : fine -=
371 : IGP01E1000_ANALOG_FUSE_FINE_1;
372 0 : } else if (coarse ==
373 : IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
374 0 : fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
375 :
376 0 : fused = (fused &
377 0 : IGP01E1000_ANALOG_FUSE_POLY_MASK) |
378 0 : (fine &
379 0 : IGP01E1000_ANALOG_FUSE_FINE_MASK) |
380 0 : (coarse &
381 : IGP01E1000_ANALOG_FUSE_COARSE_MASK);
382 :
383 0 : em_write_phy_reg(hw,
384 : IGP01E1000_ANALOG_FUSE_CONTROL,
385 : fused);
386 :
387 0 : em_write_phy_reg(hw,
388 : IGP01E1000_ANALOG_FUSE_BYPASS,
389 : IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
390 0 : }
391 0 : }
392 : }
393 0 : }
394 :
395 : /******************************************************************************
396 : * Set the mac type member in the hw struct.
397 : *
398 : * hw - Struct containing variables accessed by shared code
399 : *****************************************************************************/
400 : int32_t
401 0 : em_set_mac_type(struct em_hw *hw)
402 : {
403 : DEBUGFUNC("em_set_mac_type");
404 :
405 0 : switch (hw->device_id) {
406 : case E1000_DEV_ID_82542:
407 0 : switch (hw->revision_id) {
408 : case E1000_82542_2_0_REV_ID:
409 0 : hw->mac_type = em_82542_rev2_0;
410 0 : break;
411 : case E1000_82542_2_1_REV_ID:
412 0 : hw->mac_type = em_82542_rev2_1;
413 0 : break;
414 : default:
415 : /* Invalid 82542 revision ID */
416 0 : return -E1000_ERR_MAC_TYPE;
417 : }
418 : break;
419 : case E1000_DEV_ID_82543GC_FIBER:
420 : case E1000_DEV_ID_82543GC_COPPER:
421 0 : hw->mac_type = em_82543;
422 0 : break;
423 : case E1000_DEV_ID_82544EI_COPPER:
424 : case E1000_DEV_ID_82544EI_FIBER:
425 : case E1000_DEV_ID_82544GC_COPPER:
426 : case E1000_DEV_ID_82544GC_LOM:
427 0 : hw->mac_type = em_82544;
428 0 : break;
429 : case E1000_DEV_ID_82540EM:
430 : case E1000_DEV_ID_82540EM_LOM:
431 : case E1000_DEV_ID_82540EP:
432 : case E1000_DEV_ID_82540EP_LOM:
433 : case E1000_DEV_ID_82540EP_LP:
434 0 : hw->mac_type = em_82540;
435 0 : break;
436 : case E1000_DEV_ID_82545EM_COPPER:
437 : case E1000_DEV_ID_82545EM_FIBER:
438 0 : hw->mac_type = em_82545;
439 0 : break;
440 : case E1000_DEV_ID_82545GM_COPPER:
441 : case E1000_DEV_ID_82545GM_FIBER:
442 : case E1000_DEV_ID_82545GM_SERDES:
443 0 : hw->mac_type = em_82545_rev_3;
444 0 : break;
445 : case E1000_DEV_ID_82546EB_COPPER:
446 : case E1000_DEV_ID_82546EB_FIBER:
447 : case E1000_DEV_ID_82546EB_QUAD_COPPER:
448 0 : hw->mac_type = em_82546;
449 0 : break;
450 : case E1000_DEV_ID_82546GB_COPPER:
451 : case E1000_DEV_ID_82546GB_FIBER:
452 : case E1000_DEV_ID_82546GB_SERDES:
453 : case E1000_DEV_ID_82546GB_PCIE:
454 : case E1000_DEV_ID_82546GB_QUAD_COPPER:
455 : case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
456 : case E1000_DEV_ID_82546GB_2:
457 0 : hw->mac_type = em_82546_rev_3;
458 0 : break;
459 : case E1000_DEV_ID_82541EI:
460 : case E1000_DEV_ID_82541EI_MOBILE:
461 : case E1000_DEV_ID_82541ER_LOM:
462 0 : hw->mac_type = em_82541;
463 0 : break;
464 : case E1000_DEV_ID_82541ER:
465 : case E1000_DEV_ID_82541GI:
466 : case E1000_DEV_ID_82541GI_LF:
467 : case E1000_DEV_ID_82541GI_MOBILE:
468 0 : hw->mac_type = em_82541_rev_2;
469 0 : break;
470 : case E1000_DEV_ID_82547EI:
471 : case E1000_DEV_ID_82547EI_MOBILE:
472 0 : hw->mac_type = em_82547;
473 0 : break;
474 : case E1000_DEV_ID_82547GI:
475 0 : hw->mac_type = em_82547_rev_2;
476 0 : break;
477 : case E1000_DEV_ID_82571EB_AF:
478 : case E1000_DEV_ID_82571EB_AT:
479 : case E1000_DEV_ID_82571EB_COPPER:
480 : case E1000_DEV_ID_82571EB_FIBER:
481 : case E1000_DEV_ID_82571EB_SERDES:
482 : case E1000_DEV_ID_82571EB_QUAD_COPPER:
483 : case E1000_DEV_ID_82571EB_QUAD_FIBER:
484 : case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
485 : case E1000_DEV_ID_82571EB_SERDES_DUAL:
486 : case E1000_DEV_ID_82571EB_SERDES_QUAD:
487 : case E1000_DEV_ID_82571PT_QUAD_COPPER:
488 0 : hw->mac_type = em_82571;
489 0 : break;
490 : case E1000_DEV_ID_82572EI_COPPER:
491 : case E1000_DEV_ID_82572EI_FIBER:
492 : case E1000_DEV_ID_82572EI_SERDES:
493 : case E1000_DEV_ID_82572EI:
494 0 : hw->mac_type = em_82572;
495 0 : break;
496 : case E1000_DEV_ID_82573E:
497 : case E1000_DEV_ID_82573E_IAMT:
498 : case E1000_DEV_ID_82573E_PM:
499 : case E1000_DEV_ID_82573L:
500 : case E1000_DEV_ID_82573L_PL_1:
501 : case E1000_DEV_ID_82573L_PL_2:
502 : case E1000_DEV_ID_82573V_PM:
503 0 : hw->mac_type = em_82573;
504 0 : break;
505 : case E1000_DEV_ID_82574L:
506 : case E1000_DEV_ID_82574LA:
507 : case E1000_DEV_ID_82583V:
508 0 : hw->mac_type = em_82574;
509 0 : break;
510 : case E1000_DEV_ID_82575EB_PT:
511 : case E1000_DEV_ID_82575EB_PF:
512 : case E1000_DEV_ID_82575GB_QP:
513 : case E1000_DEV_ID_82575GB_QP_PM:
514 : case E1000_DEV_ID_82576:
515 : case E1000_DEV_ID_82576_FIBER:
516 : case E1000_DEV_ID_82576_SERDES:
517 : case E1000_DEV_ID_82576_QUAD_COPPER:
518 : case E1000_DEV_ID_82576_QUAD_CU_ET2:
519 : case E1000_DEV_ID_82576_NS:
520 : case E1000_DEV_ID_82576_NS_SERDES:
521 : case E1000_DEV_ID_82576_SERDES_QUAD:
522 0 : hw->mac_type = em_82575;
523 0 : hw->initialize_hw_bits_disable = 1;
524 0 : break;
525 : case E1000_DEV_ID_82580_COPPER:
526 : case E1000_DEV_ID_82580_FIBER:
527 : case E1000_DEV_ID_82580_QUAD_FIBER:
528 : case E1000_DEV_ID_82580_SERDES:
529 : case E1000_DEV_ID_82580_SGMII:
530 : case E1000_DEV_ID_82580_COPPER_DUAL:
531 : case E1000_DEV_ID_DH89XXCC_SGMII:
532 : case E1000_DEV_ID_DH89XXCC_SERDES:
533 : case E1000_DEV_ID_DH89XXCC_BACKPLANE:
534 : case E1000_DEV_ID_DH89XXCC_SFP:
535 0 : hw->mac_type = em_82580;
536 0 : hw->initialize_hw_bits_disable = 1;
537 0 : break;
538 : case E1000_DEV_ID_I210_COPPER:
539 : case E1000_DEV_ID_I210_COPPER_OEM1:
540 : case E1000_DEV_ID_I210_COPPER_IT:
541 : case E1000_DEV_ID_I210_FIBER:
542 : case E1000_DEV_ID_I210_SERDES:
543 : case E1000_DEV_ID_I210_SGMII:
544 : case E1000_DEV_ID_I210_COPPER_FLASHLESS:
545 : case E1000_DEV_ID_I210_SERDES_FLASHLESS:
546 : case E1000_DEV_ID_I211_COPPER:
547 0 : hw->mac_type = em_i210;
548 0 : hw->initialize_hw_bits_disable = 1;
549 0 : hw->eee_enable = 1;
550 0 : break;
551 : case E1000_DEV_ID_I350_COPPER:
552 : case E1000_DEV_ID_I350_FIBER:
553 : case E1000_DEV_ID_I350_SERDES:
554 : case E1000_DEV_ID_I350_SGMII:
555 : case E1000_DEV_ID_I350_DA4:
556 : case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
557 : case E1000_DEV_ID_I354_SGMII:
558 : case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
559 0 : hw->mac_type = em_i350;
560 0 : hw->initialize_hw_bits_disable = 1;
561 0 : hw->eee_enable = 1;
562 0 : break;
563 : case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
564 : case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
565 : case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
566 : case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
567 0 : hw->mac_type = em_80003es2lan;
568 0 : break;
569 : case E1000_DEV_ID_ICH8_IFE:
570 : case E1000_DEV_ID_ICH8_IFE_G:
571 : case E1000_DEV_ID_ICH8_IFE_GT:
572 : case E1000_DEV_ID_ICH8_IGP_AMT:
573 : case E1000_DEV_ID_ICH8_IGP_C:
574 : case E1000_DEV_ID_ICH8_IGP_M:
575 : case E1000_DEV_ID_ICH8_IGP_M_AMT:
576 : case E1000_DEV_ID_ICH8_82567V_3:
577 0 : hw->mac_type = em_ich8lan;
578 0 : break;
579 : case E1000_DEV_ID_ICH9_BM:
580 : case E1000_DEV_ID_ICH9_IFE:
581 : case E1000_DEV_ID_ICH9_IFE_G:
582 : case E1000_DEV_ID_ICH9_IFE_GT:
583 : case E1000_DEV_ID_ICH9_IGP_AMT:
584 : case E1000_DEV_ID_ICH9_IGP_C:
585 : case E1000_DEV_ID_ICH9_IGP_M:
586 : case E1000_DEV_ID_ICH9_IGP_M_AMT:
587 : case E1000_DEV_ID_ICH9_IGP_M_V:
588 : case E1000_DEV_ID_ICH10_R_BM_LF:
589 : case E1000_DEV_ID_ICH10_R_BM_LM:
590 : case E1000_DEV_ID_ICH10_R_BM_V:
591 0 : hw->mac_type = em_ich9lan;
592 0 : break;
593 : case E1000_DEV_ID_ICH10_D_BM_LF:
594 : case E1000_DEV_ID_ICH10_D_BM_LM:
595 : case E1000_DEV_ID_ICH10_D_BM_V:
596 0 : hw->mac_type = em_ich10lan;
597 0 : break;
598 : case E1000_DEV_ID_PCH_M_HV_LC:
599 : case E1000_DEV_ID_PCH_M_HV_LM:
600 : case E1000_DEV_ID_PCH_D_HV_DC:
601 : case E1000_DEV_ID_PCH_D_HV_DM:
602 0 : hw->mac_type = em_pchlan;
603 0 : hw->eee_enable = 1;
604 0 : break;
605 : case E1000_DEV_ID_PCH2_LV_LM:
606 : case E1000_DEV_ID_PCH2_LV_V:
607 0 : hw->mac_type = em_pch2lan;
608 0 : break;
609 : case E1000_DEV_ID_PCH_LPT_I217_LM:
610 : case E1000_DEV_ID_PCH_LPT_I217_V:
611 : case E1000_DEV_ID_PCH_LPTLP_I218_LM:
612 : case E1000_DEV_ID_PCH_LPTLP_I218_V:
613 : case E1000_DEV_ID_PCH_I218_LM2:
614 : case E1000_DEV_ID_PCH_I218_V2:
615 : case E1000_DEV_ID_PCH_I218_LM3:
616 : case E1000_DEV_ID_PCH_I218_V3:
617 0 : hw->mac_type = em_pch_lpt;
618 0 : break;
619 : case E1000_DEV_ID_PCH_SPT_I219_LM:
620 : case E1000_DEV_ID_PCH_SPT_I219_V:
621 : case E1000_DEV_ID_PCH_SPT_I219_LM2:
622 : case E1000_DEV_ID_PCH_SPT_I219_V2:
623 : case E1000_DEV_ID_PCH_LBG_I219_LM3:
624 : case E1000_DEV_ID_PCH_SPT_I219_LM4:
625 : case E1000_DEV_ID_PCH_SPT_I219_V4:
626 : case E1000_DEV_ID_PCH_SPT_I219_LM5:
627 : case E1000_DEV_ID_PCH_SPT_I219_V5:
628 0 : hw->mac_type = em_pch_spt;
629 0 : break;
630 : case E1000_DEV_ID_PCH_CNP_I219_LM6:
631 : case E1000_DEV_ID_PCH_CNP_I219_V6:
632 : case E1000_DEV_ID_PCH_CNP_I219_LM7:
633 : case E1000_DEV_ID_PCH_CNP_I219_V7:
634 : case E1000_DEV_ID_PCH_ICP_I219_LM8:
635 : case E1000_DEV_ID_PCH_ICP_I219_V8:
636 : case E1000_DEV_ID_PCH_ICP_I219_LM9:
637 : case E1000_DEV_ID_PCH_ICP_I219_V9:
638 0 : hw->mac_type = em_pch_cnp;
639 0 : break;
640 : case E1000_DEV_ID_EP80579_LAN_1:
641 0 : hw->mac_type = em_icp_xxxx;
642 0 : hw->icp_xxxx_port_num = 0;
643 0 : break;
644 : case E1000_DEV_ID_EP80579_LAN_2:
645 : case E1000_DEV_ID_EP80579_LAN_4:
646 0 : hw->mac_type = em_icp_xxxx;
647 0 : hw->icp_xxxx_port_num = 1;
648 0 : break;
649 : case E1000_DEV_ID_EP80579_LAN_3:
650 : case E1000_DEV_ID_EP80579_LAN_5:
651 0 : hw->mac_type = em_icp_xxxx;
652 0 : hw->icp_xxxx_port_num = 2;
653 0 : break;
654 : case E1000_DEV_ID_EP80579_LAN_6:
655 0 : hw->mac_type = em_icp_xxxx;
656 0 : hw->icp_xxxx_port_num = 3;
657 0 : break;
658 : default:
659 : /* Should never have loaded on this device */
660 0 : return -E1000_ERR_MAC_TYPE;
661 : }
662 :
663 0 : switch (hw->mac_type) {
664 : case em_ich8lan:
665 : case em_ich9lan:
666 : case em_ich10lan:
667 : case em_pchlan:
668 : case em_pch2lan:
669 : case em_pch_lpt:
670 : case em_pch_spt:
671 : case em_pch_cnp:
672 0 : hw->swfwhw_semaphore_present = TRUE;
673 0 : hw->asf_firmware_present = TRUE;
674 0 : break;
675 : case em_80003es2lan:
676 : case em_82575:
677 : case em_82580:
678 : case em_i210:
679 : case em_i350:
680 0 : hw->swfw_sync_present = TRUE;
681 : /* FALLTHROUGH */
682 : case em_82571:
683 : case em_82572:
684 : case em_82573:
685 : case em_82574:
686 0 : hw->eeprom_semaphore_present = TRUE;
687 : /* FALLTHROUGH */
688 : case em_82541:
689 : case em_82547:
690 : case em_82541_rev_2:
691 : case em_82547_rev_2:
692 0 : hw->asf_firmware_present = TRUE;
693 0 : break;
694 : default:
695 : break;
696 : }
697 :
698 0 : return E1000_SUCCESS;
699 0 : }
700 : /*****************************************************************************
701 : * Set media type and TBI compatibility.
702 : *
703 : * hw - Struct containing variables accessed by shared code
704 : * **************************************************************************/
705 : void
706 0 : em_set_media_type(struct em_hw *hw)
707 : {
708 : uint32_t status, ctrl_ext;
709 : DEBUGFUNC("em_set_media_type");
710 :
711 0 : if (hw->mac_type != em_82543) {
712 : /* tbi_compatibility is only valid on 82543 */
713 0 : hw->tbi_compatibility_en = FALSE;
714 0 : }
715 :
716 0 : if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
717 0 : hw->mac_type == em_i210 || hw->mac_type == em_i350) {
718 0 : hw->media_type = em_media_type_copper;
719 :
720 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
721 0 : switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
722 : case E1000_CTRL_EXT_LINK_MODE_SGMII:
723 0 : ctrl_ext |= E1000_CTRL_I2C_ENA;
724 0 : break;
725 : case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
726 : case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
727 0 : hw->media_type = em_media_type_internal_serdes;
728 0 : ctrl_ext |= E1000_CTRL_I2C_ENA;
729 0 : break;
730 : default:
731 0 : ctrl_ext &= ~E1000_CTRL_I2C_ENA;
732 0 : break;
733 : }
734 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
735 0 : return;
736 : }
737 :
738 0 : switch (hw->device_id) {
739 : case E1000_DEV_ID_82545GM_SERDES:
740 : case E1000_DEV_ID_82546GB_SERDES:
741 : case E1000_DEV_ID_82571EB_SERDES:
742 : case E1000_DEV_ID_82571EB_SERDES_DUAL:
743 : case E1000_DEV_ID_82571EB_SERDES_QUAD:
744 : case E1000_DEV_ID_82572EI_SERDES:
745 : case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
746 0 : hw->media_type = em_media_type_internal_serdes;
747 0 : break;
748 : case E1000_DEV_ID_EP80579_LAN_1:
749 : case E1000_DEV_ID_EP80579_LAN_2:
750 : case E1000_DEV_ID_EP80579_LAN_3:
751 : case E1000_DEV_ID_EP80579_LAN_4:
752 : case E1000_DEV_ID_EP80579_LAN_5:
753 : case E1000_DEV_ID_EP80579_LAN_6:
754 0 : hw->media_type = em_media_type_copper;
755 0 : break;
756 : default:
757 0 : switch (hw->mac_type) {
758 : case em_82542_rev2_0:
759 : case em_82542_rev2_1:
760 0 : hw->media_type = em_media_type_fiber;
761 0 : break;
762 : case em_ich8lan:
763 : case em_ich9lan:
764 : case em_ich10lan:
765 : case em_pchlan:
766 : case em_pch2lan:
767 : case em_pch_lpt:
768 : case em_pch_spt:
769 : case em_pch_cnp:
770 : case em_82573:
771 : case em_82574:
772 : /*
773 : * The STATUS_TBIMODE bit is reserved or reused for
774 : * the this device.
775 : */
776 0 : hw->media_type = em_media_type_copper;
777 0 : break;
778 : default:
779 0 : status = E1000_READ_REG(hw, STATUS);
780 0 : if (status & E1000_STATUS_TBIMODE) {
781 0 : hw->media_type = em_media_type_fiber;
782 : /* tbi_compatibility not valid on fiber */
783 0 : hw->tbi_compatibility_en = FALSE;
784 0 : } else {
785 0 : hw->media_type = em_media_type_copper;
786 : }
787 : break;
788 : }
789 : }
790 0 : }
791 : /******************************************************************************
792 : * Reset the transmit and receive units; mask and clear all interrupts.
793 : *
794 : * hw - Struct containing variables accessed by shared code
795 : *****************************************************************************/
796 : int32_t
797 0 : em_reset_hw(struct em_hw *hw)
798 : {
799 : uint32_t ctrl;
800 : uint32_t ctrl_ext;
801 : uint32_t icr;
802 : uint32_t manc;
803 : uint32_t led_ctrl;
804 : uint32_t timeout;
805 : uint32_t extcnf_ctrl;
806 : int32_t ret_val;
807 : DEBUGFUNC("em_reset_hw");
808 :
809 : /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
810 0 : if (hw->mac_type == em_82542_rev2_0) {
811 : DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
812 0 : em_pci_clear_mwi(hw);
813 0 : }
814 0 : if (hw->bus_type == em_bus_type_pci_express) {
815 : /*
816 : * Prevent the PCI-E bus from sticking if there is no TLP
817 : * connection on the last TLP read/write transaction when MAC
818 : * is reset.
819 : */
820 0 : if (em_disable_pciex_master(hw) != E1000_SUCCESS) {
821 : DEBUGOUT("PCI-E Master disable polling has failed.\n");
822 : }
823 0 : }
824 :
825 : /* Set the completion timeout for 82575 chips */
826 0 : if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
827 0 : hw->mac_type == em_i210 || hw->mac_type == em_i350) {
828 0 : ret_val = em_set_pciex_completion_timeout(hw);
829 : if (ret_val) {
830 : DEBUGOUT("PCI-E Set completion timeout has failed.\n");
831 : }
832 0 : }
833 :
834 : /* Clear interrupt mask to stop board from generating interrupts */
835 : DEBUGOUT("Masking off all interrupts\n");
836 0 : E1000_WRITE_REG(hw, IMC, 0xffffffff);
837 : /*
838 : * Disable the Transmit and Receive units. Then delay to allow any
839 : * pending transactions to complete before we hit the MAC with the
840 : * global reset.
841 : */
842 0 : E1000_WRITE_REG(hw, RCTL, 0);
843 0 : E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
844 0 : E1000_WRITE_FLUSH(hw);
845 : /*
846 : * The tbi_compatibility_on Flag must be cleared when Rctl is
847 : * cleared.
848 : */
849 0 : hw->tbi_compatibility_on = FALSE;
850 : /*
851 : * Delay to allow any outstanding PCI transactions to complete before
852 : * resetting the device
853 : */
854 0 : msec_delay(10);
855 :
856 0 : ctrl = E1000_READ_REG(hw, CTRL);
857 :
858 : /* Must reset the PHY before resetting the MAC */
859 0 : if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
860 0 : E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
861 0 : msec_delay(5);
862 0 : }
863 : /*
864 : * Must acquire the MDIO ownership before MAC reset. Ownership
865 : * defaults to firmware after a reset.
866 : */
867 0 : if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
868 : timeout = 10;
869 :
870 0 : extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
871 0 : extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
872 :
873 0 : do {
874 0 : E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
875 0 : extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
876 :
877 0 : if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
878 : break;
879 : else
880 0 : extcnf_ctrl |=
881 : E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
882 :
883 0 : msec_delay(2);
884 0 : timeout--;
885 0 : } while (timeout);
886 : }
887 : /* Workaround for ICH8 bit corruption issue in FIFO memory */
888 0 : if (hw->mac_type == em_ich8lan) {
889 : /* Set Tx and Rx buffer allocation to 8k apiece. */
890 0 : E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
891 : /* Set Packet Buffer Size to 16k. */
892 0 : E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
893 0 : }
894 : /*
895 : * Issue a global reset to the MAC. This will reset the chip's
896 : * transmit, receive, DMA, and link units. It will not effect the
897 : * current PCI configuration. The global reset bit is self-
898 : * clearing, and should clear within a microsecond.
899 : */
900 : DEBUGOUT("Issuing a global reset to MAC\n");
901 :
902 0 : switch (hw->mac_type) {
903 : case em_82544:
904 : case em_82540:
905 : case em_82545:
906 : case em_82546:
907 : case em_82541:
908 : case em_82541_rev_2:
909 : /*
910 : * These controllers can't ack the 64-bit write when issuing
911 : * the reset, so use IO-mapping as a workaround to issue the
912 : * reset
913 : */
914 0 : E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
915 0 : break;
916 : case em_82545_rev_3:
917 : case em_82546_rev_3:
918 : /* Reset is performed on a shadow of the control register */
919 0 : E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
920 0 : break;
921 : case em_ich8lan:
922 : case em_ich9lan:
923 : case em_ich10lan:
924 : case em_pchlan:
925 : case em_pch2lan:
926 : case em_pch_lpt:
927 : case em_pch_spt:
928 : case em_pch_cnp:
929 0 : if (!hw->phy_reset_disable &&
930 0 : em_check_phy_reset_block(hw) == E1000_SUCCESS) {
931 : /*
932 : * PHY HW reset requires MAC CORE reset at the same
933 : * time to make sure the interface between MAC and
934 : * the external PHY is reset.
935 : */
936 0 : ctrl |= E1000_CTRL_PHY_RST;
937 : /*
938 : * Gate automatic PHY configuration by hardware on
939 : * non-managed 82579
940 : */
941 0 : if ((hw->mac_type == em_pch2lan) &&
942 0 : !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
943 0 : em_gate_hw_phy_config_ich8lan(hw, TRUE);
944 0 : }
945 : }
946 0 : em_get_software_flag(hw);
947 0 : E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
948 : /* HW reset releases software_flag */
949 0 : hw->sw_flag = 0;
950 0 : msec_delay(20);
951 :
952 : /* Ungate automatic PHY configuration on non-managed 82579 */
953 0 : if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable &&
954 0 : !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
955 0 : msec_delay(10);
956 0 : em_gate_hw_phy_config_ich8lan(hw, FALSE);
957 0 : }
958 : break;
959 : default:
960 0 : E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
961 0 : break;
962 : }
963 :
964 0 : if (em_check_phy_reset_block(hw) == E1000_SUCCESS) {
965 0 : if (hw->mac_type == em_pchlan) {
966 0 : ret_val = em_hv_phy_workarounds_ich8lan(hw);
967 0 : if (ret_val)
968 0 : return ret_val;
969 : }
970 0 : else if (hw->mac_type == em_pch2lan) {
971 0 : ret_val = em_lv_phy_workarounds_ich8lan(hw);
972 0 : if (ret_val)
973 0 : return ret_val;
974 : }
975 : }
976 :
977 : /*
978 : * After MAC reset, force reload of EEPROM to restore power-on
979 : * settings to device. Later controllers reload the EEPROM
980 : * automatically, so just wait for reload to complete.
981 : */
982 0 : switch (hw->mac_type) {
983 : case em_82542_rev2_0:
984 : case em_82542_rev2_1:
985 : case em_82543:
986 : case em_82544:
987 : /* Wait for reset to complete */
988 0 : usec_delay(10);
989 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
990 0 : ctrl_ext |= E1000_CTRL_EXT_EE_RST;
991 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
992 0 : E1000_WRITE_FLUSH(hw);
993 : /* Wait for EEPROM reload */
994 0 : msec_delay(2);
995 0 : break;
996 : case em_82541:
997 : case em_82541_rev_2:
998 : case em_82547:
999 : case em_82547_rev_2:
1000 : /* Wait for EEPROM reload */
1001 0 : msec_delay(20);
1002 0 : break;
1003 : case em_82573:
1004 : case em_82574:
1005 0 : if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
1006 0 : usec_delay(10);
1007 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1008 0 : ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1009 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1010 0 : E1000_WRITE_FLUSH(hw);
1011 0 : }
1012 : /* FALLTHROUGH */
1013 :
1014 : /* Auto read done will delay 5ms or poll based on mac type */
1015 0 : ret_val = em_get_auto_rd_done(hw);
1016 0 : if (ret_val)
1017 0 : return ret_val;
1018 : break;
1019 : default:
1020 : /* Wait for EEPROM reload (it happens automatically) */
1021 0 : msec_delay(5);
1022 0 : break;
1023 : }
1024 :
1025 : /* Disable HW ARPs on ASF enabled adapters */
1026 0 : if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 &&
1027 0 : hw->mac_type != em_icp_xxxx) {
1028 0 : manc = E1000_READ_REG(hw, MANC);
1029 0 : manc &= ~(E1000_MANC_ARP_EN);
1030 0 : E1000_WRITE_REG(hw, MANC, manc);
1031 0 : }
1032 0 : if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
1033 0 : em_phy_init_script(hw);
1034 :
1035 : /* Configure activity LED after PHY reset */
1036 0 : led_ctrl = E1000_READ_REG(hw, LEDCTL);
1037 0 : led_ctrl &= IGP_ACTIVITY_LED_MASK;
1038 0 : led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1039 0 : E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1040 0 : }
1041 :
1042 : /*
1043 : * For PCH, this write will make sure that any noise
1044 : * will be detected as a CRC error and be dropped rather than show up
1045 : * as a bad packet to the DMA engine.
1046 : */
1047 0 : if (hw->mac_type == em_pchlan)
1048 0 : E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565);
1049 :
1050 : /* Clear interrupt mask to stop board from generating interrupts */
1051 : DEBUGOUT("Masking off all interrupts\n");
1052 0 : E1000_WRITE_REG(hw, IMC, 0xffffffff);
1053 :
1054 : /* Clear any pending interrupt events. */
1055 0 : icr = E1000_READ_REG(hw, ICR);
1056 :
1057 : /* If MWI was previously enabled, reenable it. */
1058 0 : if (hw->mac_type == em_82542_rev2_0) {
1059 0 : if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1060 0 : em_pci_set_mwi(hw);
1061 : }
1062 0 : if (IS_ICH8(hw->mac_type)) {
1063 0 : uint32_t kab = E1000_READ_REG(hw, KABGTXD);
1064 0 : kab |= E1000_KABGTXD_BGSQLBIAS;
1065 0 : E1000_WRITE_REG(hw, KABGTXD, kab);
1066 0 : }
1067 :
1068 0 : if (hw->mac_type == em_82580 || hw->mac_type == em_i350) {
1069 : uint32_t mdicnfg;
1070 0 : uint16_t nvm_data;
1071 :
1072 : /* clear global device reset status bit */
1073 0 : EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET);
1074 :
1075 0 : em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A +
1076 0 : NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1,
1077 : &nvm_data);
1078 :
1079 0 : mdicnfg = EM_READ_REG(hw, E1000_MDICNFG);
1080 0 : if (nvm_data & NVM_WORD24_EXT_MDIO)
1081 0 : mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1082 0 : if (nvm_data & NVM_WORD24_COM_MDIO)
1083 0 : mdicnfg |= E1000_MDICNFG_COM_MDIO;
1084 0 : EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
1085 0 : }
1086 :
1087 0 : if (hw->mac_type == em_i210 || hw->mac_type == em_i350)
1088 0 : em_set_eee_i350(hw);
1089 :
1090 0 : return E1000_SUCCESS;
1091 0 : }
1092 :
1093 : /******************************************************************************
1094 : *
1095 : * Initialize a number of hardware-dependent bits
1096 : *
1097 : * hw: Struct containing variables accessed by shared code
1098 : *
1099 : *****************************************************************************/
1100 : STATIC void
1101 0 : em_initialize_hardware_bits(struct em_hw *hw)
1102 : {
1103 : DEBUGFUNC("em_initialize_hardware_bits");
1104 :
1105 0 : if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) {
1106 : /* Settings common to all silicon */
1107 : uint32_t reg_ctrl, reg_ctrl_ext;
1108 : uint32_t reg_tarc0, reg_tarc1;
1109 : uint32_t reg_tctl;
1110 : uint32_t reg_txdctl, reg_txdctl1;
1111 0 : reg_tarc0 = E1000_READ_REG(hw, TARC0);
1112 0 : reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and
1113 : * 27 */
1114 :
1115 0 : reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1116 0 : reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */
1117 0 : E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1118 :
1119 0 : reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1120 0 : reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */
1121 0 : E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1122 :
1123 0 : switch (hw->mac_type) {
1124 : case em_82571:
1125 : case em_82572:
1126 0 : reg_tarc1 = E1000_READ_REG(hw, TARC1);
1127 0 : reg_tctl = E1000_READ_REG(hw, TCTL);
1128 :
1129 : /* Set the phy Tx compatible mode bits */
1130 0 : reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */
1131 :
1132 0 : reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */
1133 0 : reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */
1134 :
1135 0 : if (reg_tctl & E1000_TCTL_MULR)
1136 : /* Clear bit 28 if MULR is 1b */
1137 0 : reg_tarc1 &= ~0x10000000;
1138 : else
1139 : /* Set bit 28 if MULR is 0b */
1140 0 : reg_tarc1 |= 0x10000000;
1141 :
1142 0 : E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1143 0 : break;
1144 : case em_82573:
1145 : case em_82574:
1146 0 : reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1147 0 : reg_ctrl = E1000_READ_REG(hw, CTRL);
1148 :
1149 0 : reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */
1150 0 : reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
1151 0 : reg_ctrl &= ~0x20000000; /* Clear bit 29 */
1152 :
1153 0 : E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1154 0 : E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1155 0 : break;
1156 : case em_80003es2lan:
1157 0 : if ((hw->media_type == em_media_type_fiber) ||
1158 0 : (hw->media_type == em_media_type_internal_serdes)) {
1159 : /* Clear bit 20 */
1160 0 : reg_tarc0 &= ~0x00100000;
1161 0 : }
1162 0 : reg_tctl = E1000_READ_REG(hw, TCTL);
1163 0 : reg_tarc1 = E1000_READ_REG(hw, TARC1);
1164 0 : if (reg_tctl & E1000_TCTL_MULR)
1165 : /* Clear bit 28 if MULR is 1b */
1166 0 : reg_tarc1 &= ~0x10000000;
1167 : else
1168 : /* Set bit 28 if MULR is 0b */
1169 0 : reg_tarc1 |= 0x10000000;
1170 :
1171 0 : E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1172 0 : break;
1173 : case em_ich8lan:
1174 : case em_ich9lan:
1175 : case em_ich10lan:
1176 : case em_pchlan:
1177 : case em_pch2lan:
1178 : case em_pch_lpt:
1179 : case em_pch_spt:
1180 : case em_pch_cnp:
1181 0 : if (hw->mac_type == em_ich8lan)
1182 : /* Set TARC0 bits 29 and 28 */
1183 0 : reg_tarc0 |= 0x30000000;
1184 :
1185 0 : reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1186 0 : reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
1187 : /* Enable PHY low-power state when MAC is at D3 w/o WoL */
1188 0 : if (hw->mac_type >= em_pchlan)
1189 0 : reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN;
1190 0 : E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1191 :
1192 0 : reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23,
1193 : * 24, 26, 27 */
1194 :
1195 0 : reg_tarc1 = E1000_READ_REG(hw, TARC1);
1196 0 : reg_tctl = E1000_READ_REG(hw, TCTL);
1197 :
1198 0 : if (reg_tctl & E1000_TCTL_MULR)
1199 : /* Clear bit 28 if MULR is 1b */
1200 0 : reg_tarc1 &= ~0x10000000;
1201 : else
1202 : /* Set bit 28 if MULR is 0b */
1203 0 : reg_tarc1 |= 0x10000000;
1204 :
1205 0 : reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and
1206 : * 30 */
1207 :
1208 0 : E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1209 0 : break;
1210 : default:
1211 : break;
1212 : }
1213 :
1214 0 : E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1215 0 : }
1216 0 : }
1217 :
1218 : /**
1219 : * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
1220 : * @hw: pointer to the HW structure
1221 : *
1222 : * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
1223 : * used to reset the PHY to a quiescent state when necessary.
1224 : **/
1225 : static void
1226 0 : em_toggle_lanphypc_pch_lpt(struct em_hw *hw)
1227 : {
1228 : uint32_t mac_reg;
1229 :
1230 : DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
1231 :
1232 : /* Set Phy Config Counter to 50msec */
1233 0 : mac_reg = E1000_READ_REG(hw, FEXTNVM3);
1234 0 : mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
1235 0 : mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
1236 0 : E1000_WRITE_REG(hw, FEXTNVM3, mac_reg);
1237 :
1238 : /* Toggle LANPHYPC Value bit */
1239 0 : mac_reg = E1000_READ_REG(hw, CTRL);
1240 0 : mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
1241 0 : mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
1242 0 : E1000_WRITE_REG(hw, CTRL, mac_reg);
1243 0 : E1000_WRITE_FLUSH(hw);
1244 0 : msec_delay(1);
1245 0 : mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
1246 0 : E1000_WRITE_REG(hw, CTRL, mac_reg);
1247 0 : E1000_WRITE_FLUSH(hw);
1248 :
1249 0 : if (hw->mac_type < em_pch_lpt) {
1250 0 : msec_delay(50);
1251 0 : } else {
1252 : uint16_t count = 20;
1253 :
1254 0 : do {
1255 0 : msec_delay(5);
1256 0 : } while (!(E1000_READ_REG(hw, CTRL_EXT) &
1257 0 : E1000_CTRL_EXT_LPCD) && count--);
1258 :
1259 0 : msec_delay(30);
1260 : }
1261 0 : }
1262 :
1263 : /**
1264 : * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1265 : * @hw: pointer to the HW structure
1266 : * @force: boolean indicating whether or not to force disabling ULP
1267 : *
1268 : * Un-configure ULP mode when link is up, the system is transitioned from
1269 : * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1270 : * system, poll for an indication from ME that ULP has been un-configured.
1271 : * If not on an ME enabled system, un-configure the ULP mode by software.
1272 : *
1273 : * During nominal operation, this function is called when link is acquired
1274 : * to disable ULP mode (force=FALSE); otherwise, for example when unloading
1275 : * the driver or during Sx->S0 transitions, this is called with force=TRUE
1276 : * to forcibly disable ULP.
1277 : */
1278 : static int
1279 0 : em_disable_ulp_lpt_lp(struct em_hw *hw, bool force)
1280 : {
1281 : int ret_val = E1000_SUCCESS;
1282 : uint32_t mac_reg;
1283 0 : uint16_t phy_reg;
1284 : int i = 0;
1285 :
1286 0 : if ((hw->mac_type < em_pch_lpt) ||
1287 0 : (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1288 0 : (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1289 0 : (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1290 0 : (hw->device_id == E1000_DEV_ID_PCH_I218_V2))
1291 0 : return 0;
1292 :
1293 0 : if (E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID) {
1294 0 : if (force) {
1295 : /* Request ME un-configure ULP mode in the PHY */
1296 0 : mac_reg = E1000_READ_REG(hw, H2ME);
1297 0 : mac_reg &= ~E1000_H2ME_ULP;
1298 0 : mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1299 0 : E1000_WRITE_REG(hw, H2ME, mac_reg);
1300 0 : }
1301 :
1302 : /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1303 0 : while (E1000_READ_REG(hw, FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1304 0 : if (i++ == 30) {
1305 : ret_val = -E1000_ERR_PHY;
1306 0 : goto out;
1307 : }
1308 :
1309 0 : msec_delay(10);
1310 : }
1311 : DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1312 :
1313 0 : if (force) {
1314 : mac_reg = E1000_READ_REG(hw, H2ME);
1315 0 : mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1316 0 : E1000_WRITE_REG(hw, H2ME, mac_reg);
1317 0 : } else {
1318 : /* Clear H2ME.ULP after ME ULP configuration */
1319 : mac_reg = E1000_READ_REG(hw, H2ME);
1320 0 : mac_reg &= ~E1000_H2ME_ULP;
1321 0 : E1000_WRITE_REG(hw, H2ME, mac_reg);
1322 : }
1323 :
1324 : goto out;
1325 : }
1326 :
1327 0 : ret_val = em_get_software_flag(hw);
1328 0 : if (ret_val)
1329 : goto out;
1330 :
1331 0 : if (force)
1332 : /* Toggle LANPHYPC Value bit */
1333 0 : em_toggle_lanphypc_pch_lpt(hw);
1334 :
1335 : /* Unforce SMBus mode in PHY */
1336 0 : ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg);
1337 0 : if (ret_val) {
1338 : /* The MAC might be in PCIe mode, so temporarily force to
1339 : * SMBus mode in order to access the PHY.
1340 : */
1341 0 : mac_reg = E1000_READ_REG(hw, CTRL_EXT);
1342 0 : mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1343 0 : E1000_WRITE_REG(hw, CTRL_EXT, mac_reg);
1344 :
1345 0 : msec_delay(50);
1346 :
1347 0 : ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg);
1348 0 : if (ret_val)
1349 : goto release;
1350 : }
1351 0 : phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1352 0 : em_write_phy_reg(hw, CV_SMB_CTRL, phy_reg);
1353 :
1354 : /* Unforce SMBus mode in MAC */
1355 0 : mac_reg = E1000_READ_REG(hw, CTRL_EXT);
1356 0 : mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1357 0 : E1000_WRITE_REG(hw, CTRL_EXT, mac_reg);
1358 :
1359 : /* When ULP mode was previously entered, K1 was disabled by the
1360 : * hardware. Re-Enable K1 in the PHY when exiting ULP.
1361 : */
1362 0 : ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg);
1363 0 : if (ret_val)
1364 : goto release;
1365 0 : phy_reg |= HV_PM_CTRL_K1_ENABLE;
1366 0 : em_write_phy_reg(hw, HV_PM_CTRL, phy_reg);
1367 :
1368 : /* Clear ULP enabled configuration */
1369 0 : ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg);
1370 0 : if (ret_val)
1371 : goto release;
1372 0 : phy_reg &= ~(I218_ULP_CONFIG1_IND |
1373 : I218_ULP_CONFIG1_STICKY_ULP |
1374 : I218_ULP_CONFIG1_RESET_TO_SMBUS |
1375 : I218_ULP_CONFIG1_WOL_HOST |
1376 : I218_ULP_CONFIG1_INBAND_EXIT |
1377 : I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1378 : I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1379 : I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1380 0 : em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg);
1381 :
1382 : /* Commit ULP changes by starting auto ULP configuration */
1383 0 : phy_reg |= I218_ULP_CONFIG1_START;
1384 0 : em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg);
1385 :
1386 : /* Clear Disable SMBus Release on PERST# in MAC */
1387 0 : mac_reg = E1000_READ_REG(hw, FEXTNVM7);
1388 0 : mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1389 0 : E1000_WRITE_REG(hw, FEXTNVM7, mac_reg);
1390 :
1391 : release:
1392 0 : em_release_software_flag(hw);
1393 0 : if (force) {
1394 0 : em_phy_reset(hw);
1395 0 : msec_delay(50);
1396 0 : }
1397 : out:
1398 : if (ret_val)
1399 : DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1400 :
1401 0 : return ret_val;
1402 0 : }
1403 :
1404 : /******************************************************************************
1405 : * Performs basic configuration of the adapter.
1406 : *
1407 : * hw - Struct containing variables accessed by shared code
1408 : *
1409 : * Assumes that the controller has previously been reset and is in a
1410 : * post-reset uninitialized state. Initializes the receive address registers,
1411 : * multicast table, and VLAN filter table. Calls routines to setup link
1412 : * configuration and flow control settings. Clears all on-chip counters. Leaves
1413 : * the transmit and receive units disabled and uninitialized.
1414 : *****************************************************************************/
1415 : int32_t
1416 0 : em_init_hw(struct em_hw *hw)
1417 : {
1418 : uint32_t ctrl;
1419 : uint32_t i;
1420 : int32_t ret_val;
1421 0 : uint16_t pcix_cmd_word;
1422 0 : uint16_t pcix_stat_hi_word;
1423 : uint16_t cmd_mmrbc;
1424 : uint16_t stat_mmrbc;
1425 : uint32_t mta_size;
1426 0 : uint32_t reg_data;
1427 : uint32_t ctrl_ext;
1428 : uint32_t snoop;
1429 : uint32_t fwsm;
1430 : DEBUGFUNC("em_init_hw");
1431 :
1432 : /* force full DMA clock frequency for ICH8 */
1433 0 : if (hw->mac_type == em_ich8lan) {
1434 0 : reg_data = E1000_READ_REG(hw, STATUS);
1435 0 : reg_data &= ~0x80000000;
1436 0 : E1000_WRITE_REG(hw, STATUS, reg_data);
1437 0 : }
1438 :
1439 0 : if (hw->mac_type == em_pchlan ||
1440 0 : hw->mac_type == em_pch2lan ||
1441 0 : hw->mac_type == em_pch_lpt ||
1442 0 : hw->mac_type == em_pch_spt ||
1443 0 : hw->mac_type == em_pch_cnp) {
1444 : /*
1445 : * The MAC-PHY interconnect may still be in SMBus mode
1446 : * after Sx->S0. Toggle the LANPHYPC Value bit to force
1447 : * the interconnect to PCIe mode, but only if there is no
1448 : * firmware present otherwise firmware will have done it.
1449 : */
1450 0 : fwsm = E1000_READ_REG(hw, FWSM);
1451 0 : if ((fwsm & E1000_FWSM_FW_VALID) == 0) {
1452 0 : ctrl = E1000_READ_REG(hw, CTRL);
1453 0 : ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
1454 0 : ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
1455 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
1456 0 : usec_delay(10);
1457 0 : ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
1458 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
1459 0 : msec_delay(50);
1460 0 : }
1461 :
1462 : /* Gate automatic PHY configuration on non-managed 82579 */
1463 0 : if (hw->mac_type == em_pch2lan)
1464 0 : em_gate_hw_phy_config_ich8lan(hw, TRUE);
1465 :
1466 0 : em_disable_ulp_lpt_lp(hw, TRUE);
1467 : /*
1468 : * Reset the PHY before any acccess to it. Doing so,
1469 : * ensures that the PHY is in a known good state before
1470 : * we read/write PHY registers. The generic reset is
1471 : * sufficient here, because we haven't determined
1472 : * the PHY type yet.
1473 : */
1474 0 : em_phy_reset(hw);
1475 :
1476 : /* Ungate automatic PHY configuration on non-managed 82579 */
1477 0 : if (hw->mac_type == em_pch2lan &&
1478 : (fwsm & E1000_FWSM_FW_VALID) == 0)
1479 0 : em_gate_hw_phy_config_ich8lan(hw, FALSE);
1480 :
1481 : /* Set MDIO slow mode before any other MDIO access */
1482 0 : ret_val = em_set_mdio_slow_mode_hv(hw);
1483 0 : if (ret_val)
1484 0 : return ret_val;
1485 : }
1486 :
1487 : /* Initialize Identification LED */
1488 0 : ret_val = em_id_led_init(hw);
1489 0 : if (ret_val) {
1490 : DEBUGOUT("Error Initializing Identification LED\n");
1491 0 : return ret_val;
1492 : }
1493 : /* Set the media type and TBI compatibility */
1494 0 : em_set_media_type(hw);
1495 :
1496 : /* Magic delay that improves problems with i219LM on HP Elitebook */
1497 0 : msec_delay(1);
1498 : /* Must be called after em_set_media_type because media_type is used */
1499 0 : em_initialize_hardware_bits(hw);
1500 :
1501 : /* Disabling VLAN filtering. */
1502 : DEBUGOUT("Initializing the IEEE VLAN\n");
1503 : /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */
1504 0 : if (!IS_ICH8(hw->mac_type)) {
1505 0 : if (hw->mac_type < em_82545_rev_3)
1506 0 : E1000_WRITE_REG(hw, VET, 0);
1507 0 : if (hw->mac_type == em_i350)
1508 0 : em_clear_vfta_i350(hw);
1509 : else
1510 0 : em_clear_vfta(hw);
1511 : }
1512 : /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1513 0 : if (hw->mac_type == em_82542_rev2_0) {
1514 : DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1515 0 : em_pci_clear_mwi(hw);
1516 0 : E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1517 0 : E1000_WRITE_FLUSH(hw);
1518 0 : msec_delay(5);
1519 0 : }
1520 : /*
1521 : * Setup the receive address. This involves initializing all of the
1522 : * Receive Address Registers (RARs 0 - 15).
1523 : */
1524 0 : em_init_rx_addrs(hw);
1525 :
1526 : /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/
1527 0 : if (hw->mac_type == em_82542_rev2_0) {
1528 0 : E1000_WRITE_REG(hw, RCTL, 0);
1529 0 : E1000_WRITE_FLUSH(hw);
1530 0 : msec_delay(1);
1531 0 : if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1532 0 : em_pci_set_mwi(hw);
1533 : }
1534 : /* Zero out the Multicast HASH table */
1535 : DEBUGOUT("Zeroing the MTA\n");
1536 : mta_size = E1000_MC_TBL_SIZE;
1537 0 : if (IS_ICH8(hw->mac_type))
1538 0 : mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1539 0 : for (i = 0; i < mta_size; i++) {
1540 0 : E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1541 : /*
1542 : * use write flush to prevent Memory Write Block (MWB) from
1543 : * occuring when accessing our register space
1544 : */
1545 0 : E1000_WRITE_FLUSH(hw);
1546 : }
1547 : /*
1548 : * Set the PCI priority bit correctly in the CTRL register. This
1549 : * determines if the adapter gives priority to receives, or if it
1550 : * gives equal priority to transmits and receives. Valid only on
1551 : * 82542 and 82543 silicon.
1552 : */
1553 0 : if (hw->dma_fairness && hw->mac_type <= em_82543) {
1554 0 : ctrl = E1000_READ_REG(hw, CTRL);
1555 0 : E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1556 0 : }
1557 0 : switch (hw->mac_type) {
1558 : case em_82545_rev_3:
1559 : case em_82546_rev_3:
1560 : break;
1561 : default:
1562 : /*
1563 : * Workaround for PCI-X problem when BIOS sets MMRBC
1564 : * incorrectly.
1565 : */
1566 0 : if (hw->bus_type == em_bus_type_pcix) {
1567 0 : em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER,
1568 : &pcix_cmd_word);
1569 0 : em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
1570 : &pcix_stat_hi_word);
1571 0 : cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK)
1572 0 : >> PCIX_COMMAND_MMRBC_SHIFT;
1573 0 : stat_mmrbc = (pcix_stat_hi_word &
1574 0 : PCIX_STATUS_HI_MMRBC_MASK) >>
1575 : PCIX_STATUS_HI_MMRBC_SHIFT;
1576 :
1577 0 : if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1578 : stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1579 0 : if (cmd_mmrbc > stat_mmrbc) {
1580 0 : pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1581 0 : pcix_cmd_word |= stat_mmrbc <<
1582 : PCIX_COMMAND_MMRBC_SHIFT;
1583 0 : em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
1584 : &pcix_cmd_word);
1585 0 : }
1586 : }
1587 : break;
1588 : }
1589 :
1590 : /* More time needed for PHY to initialize */
1591 0 : if (IS_ICH8(hw->mac_type))
1592 0 : msec_delay(15);
1593 :
1594 : /*
1595 : * The 82578 Rx buffer will stall if wakeup is enabled in host and
1596 : * the ME. Reading the BM_WUC register will clear the host wakeup bit.
1597 : * Reset the phy after disabling host wakeup to reset the Rx buffer.
1598 : */
1599 0 : if (hw->phy_type == em_phy_82578) {
1600 0 : em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1),
1601 0 : (uint16_t *)®_data);
1602 0 : ret_val = em_phy_reset(hw);
1603 0 : if (ret_val)
1604 0 : return ret_val;
1605 : }
1606 :
1607 : /* Call a subroutine to configure the link and setup flow control. */
1608 0 : ret_val = em_setup_link(hw);
1609 :
1610 : /* Set the transmit descriptor write-back policy */
1611 0 : if (hw->mac_type > em_82544) {
1612 0 : ctrl = E1000_READ_REG(hw, TXDCTL);
1613 0 : ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) |
1614 : E1000_TXDCTL_FULL_TX_DESC_WB;
1615 0 : E1000_WRITE_REG(hw, TXDCTL, ctrl);
1616 0 : }
1617 0 : if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1618 0 : em_enable_tx_pkt_filtering(hw);
1619 0 : }
1620 0 : switch (hw->mac_type) {
1621 : default:
1622 : break;
1623 : case em_80003es2lan:
1624 : /* Enable retransmit on late collisions */
1625 0 : reg_data = E1000_READ_REG(hw, TCTL);
1626 0 : reg_data |= E1000_TCTL_RTLC;
1627 0 : E1000_WRITE_REG(hw, TCTL, reg_data);
1628 :
1629 : /* Configure Gigabit Carry Extend Padding */
1630 0 : reg_data = E1000_READ_REG(hw, TCTL_EXT);
1631 0 : reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1632 0 : reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1633 0 : E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1634 :
1635 : /* Configure Transmit Inter-Packet Gap */
1636 0 : reg_data = E1000_READ_REG(hw, TIPG);
1637 0 : reg_data &= ~E1000_TIPG_IPGT_MASK;
1638 0 : reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1639 0 : E1000_WRITE_REG(hw, TIPG, reg_data);
1640 :
1641 0 : reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1642 0 : reg_data &= ~0x00100000;
1643 0 : E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1644 : /* FALLTHROUGH */
1645 : case em_82571:
1646 : case em_82572:
1647 : case em_82575:
1648 : case em_82580:
1649 : case em_i210:
1650 : case em_i350:
1651 : case em_ich8lan:
1652 : case em_ich9lan:
1653 : case em_ich10lan:
1654 : case em_pchlan:
1655 : case em_pch2lan:
1656 : case em_pch_lpt:
1657 : case em_pch_spt:
1658 : case em_pch_cnp:
1659 0 : ctrl = E1000_READ_REG(hw, TXDCTL1);
1660 0 : ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) |
1661 : E1000_TXDCTL_FULL_TX_DESC_WB;
1662 0 : E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1663 0 : break;
1664 : }
1665 :
1666 0 : if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1667 0 : uint32_t gcr = E1000_READ_REG(hw, GCR);
1668 0 : gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1669 0 : E1000_WRITE_REG(hw, GCR, gcr);
1670 0 : }
1671 : /*
1672 : * Clear all of the statistics registers (clear on read). It is
1673 : * important that we do this after we have tried to establish link
1674 : * because the symbol error count will increment wildly if there is
1675 : * no link.
1676 : */
1677 0 : em_clear_hw_cntrs(hw);
1678 : /*
1679 : * ICH8 No-snoop bits are opposite polarity. Set to snoop by default
1680 : * after reset.
1681 : */
1682 0 : if (IS_ICH8(hw->mac_type)) {
1683 0 : if (hw->mac_type == em_ich8lan)
1684 0 : snoop = PCI_EX_82566_SNOOP_ALL;
1685 : else
1686 : snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL);
1687 :
1688 0 : em_set_pci_ex_no_snoop(hw, snoop);
1689 0 : }
1690 :
1691 0 : if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1692 0 : hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1693 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1694 : /*
1695 : * Relaxed ordering must be disabled to avoid a parity error
1696 : * crash in a PCI slot.
1697 : */
1698 0 : ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1699 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1700 0 : }
1701 0 : return ret_val;
1702 0 : }
1703 :
1704 : /******************************************************************************
1705 : * Adjust SERDES output amplitude based on EEPROM setting.
1706 : *
1707 : * hw - Struct containing variables accessed by shared code.
1708 : *****************************************************************************/
1709 : static int32_t
1710 0 : em_adjust_serdes_amplitude(struct em_hw *hw)
1711 : {
1712 0 : uint16_t eeprom_data;
1713 : int32_t ret_val;
1714 : DEBUGFUNC("em_adjust_serdes_amplitude");
1715 :
1716 0 : if (hw->media_type != em_media_type_internal_serdes ||
1717 0 : hw->mac_type >= em_82575)
1718 0 : return E1000_SUCCESS;
1719 :
1720 0 : switch (hw->mac_type) {
1721 : case em_82545_rev_3:
1722 : case em_82546_rev_3:
1723 : break;
1724 : default:
1725 0 : return E1000_SUCCESS;
1726 : }
1727 :
1728 0 : ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1729 0 : if (ret_val) {
1730 0 : return ret_val;
1731 : }
1732 0 : if (eeprom_data != EEPROM_RESERVED_WORD) {
1733 : /* Adjust SERDES output amplitude only. */
1734 0 : eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1735 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
1736 : eeprom_data);
1737 0 : if (ret_val)
1738 0 : return ret_val;
1739 : }
1740 0 : return E1000_SUCCESS;
1741 0 : }
1742 :
1743 : /******************************************************************************
1744 : * Configures flow control and link settings.
1745 : *
1746 : * hw - Struct containing variables accessed by shared code
1747 : *
1748 : * Determines which flow control settings to use. Calls the appropriate media-
1749 : * specific link configuration function. Configures the flow control settings.
1750 : * Assuming the adapter has a valid link partner, a valid link should be
1751 : * established. Assumes the hardware has previously been reset and the
1752 : * transmitter and receiver are not enabled.
1753 : *****************************************************************************/
1754 : int32_t
1755 0 : em_setup_link(struct em_hw *hw)
1756 : {
1757 : uint32_t ctrl_ext;
1758 : int32_t ret_val;
1759 0 : uint16_t eeprom_data;
1760 : uint16_t eeprom_control2_reg_offset;
1761 : DEBUGFUNC("em_setup_link");
1762 :
1763 : eeprom_control2_reg_offset =
1764 0 : (hw->mac_type != em_icp_xxxx)
1765 : ? EEPROM_INIT_CONTROL2_REG
1766 0 : : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num);
1767 : /*
1768 : * In the case of the phy reset being blocked, we already have a
1769 : * link. We do not have to set it up again.
1770 : */
1771 0 : if (em_check_phy_reset_block(hw))
1772 0 : return E1000_SUCCESS;
1773 : /*
1774 : * Read and store word 0x0F of the EEPROM. This word contains bits
1775 : * that determine the hardware's default PAUSE (flow control) mode, a
1776 : * bit that determines whether the HW defaults to enabling or
1777 : * disabling auto-negotiation, and the direction of the SW defined
1778 : * pins. If there is no SW over-ride of the flow control setting,
1779 : * then the variable hw->fc will be initialized based on a value in
1780 : * the EEPROM.
1781 : */
1782 0 : if (hw->fc == E1000_FC_DEFAULT) {
1783 0 : switch (hw->mac_type) {
1784 : case em_ich8lan:
1785 : case em_ich9lan:
1786 : case em_ich10lan:
1787 : case em_pchlan:
1788 : case em_pch2lan:
1789 : case em_pch_lpt:
1790 : case em_pch_spt:
1791 : case em_pch_cnp:
1792 : case em_82573:
1793 : case em_82574:
1794 0 : hw->fc = E1000_FC_FULL;
1795 0 : break;
1796 : default:
1797 0 : ret_val = em_read_eeprom(hw,
1798 : eeprom_control2_reg_offset, 1, &eeprom_data);
1799 0 : if (ret_val) {
1800 : DEBUGOUT("EEPROM Read Error\n");
1801 0 : return -E1000_ERR_EEPROM;
1802 : }
1803 0 : if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1804 0 : hw->fc = E1000_FC_NONE;
1805 0 : else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1806 : EEPROM_WORD0F_ASM_DIR)
1807 0 : hw->fc = E1000_FC_TX_PAUSE;
1808 : else
1809 0 : hw->fc = E1000_FC_FULL;
1810 : break;
1811 : }
1812 : }
1813 : /*
1814 : * We want to save off the original Flow Control configuration just
1815 : * in case we get disconnected and then reconnected into a different
1816 : * hub or switch with different Flow Control capabilities.
1817 : */
1818 0 : if (hw->mac_type == em_82542_rev2_0)
1819 0 : hw->fc &= (~E1000_FC_TX_PAUSE);
1820 :
1821 0 : if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
1822 0 : hw->fc &= (~E1000_FC_RX_PAUSE);
1823 :
1824 0 : hw->original_fc = hw->fc;
1825 :
1826 : DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1827 : /*
1828 : * Take the 4 bits from EEPROM word 0x0F that determine the initial
1829 : * polarity value for the SW controlled pins, and setup the Extended
1830 : * Device Control reg with that info. This is needed because one of
1831 : * the SW controlled pins is used for signal detection. So this
1832 : * should be done before em_setup_pcs_link() or em_phy_setup() is
1833 : * called.
1834 : */
1835 0 : if (hw->mac_type == em_82543) {
1836 0 : ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1837 : 1, &eeprom_data);
1838 0 : if (ret_val) {
1839 : DEBUGOUT("EEPROM Read Error\n");
1840 0 : return -E1000_ERR_EEPROM;
1841 : }
1842 0 : ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1843 : SWDPIO__EXT_SHIFT);
1844 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1845 0 : }
1846 : /* Make sure we have a valid PHY */
1847 0 : ret_val = em_detect_gig_phy(hw);
1848 0 : if (ret_val) {
1849 : DEBUGOUT("Error, did not detect valid phy.\n");
1850 0 : if (hw->mac_type == em_icp_xxxx)
1851 0 : return E1000_DEFER_INIT;
1852 : else
1853 0 : return ret_val;
1854 : }
1855 : DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1856 :
1857 : /* Call the necessary subroutine to configure the link. */
1858 0 : switch (hw->media_type) {
1859 : case em_media_type_copper:
1860 : case em_media_type_oem:
1861 0 : ret_val = em_setup_copper_link(hw);
1862 0 : break;
1863 : default:
1864 0 : ret_val = em_setup_fiber_serdes_link(hw);
1865 0 : break;
1866 : }
1867 : /*
1868 : * Initialize the flow control address, type, and PAUSE timer
1869 : * registers to their default values. This is done even if flow
1870 : * control is disabled, because it does not hurt anything to
1871 : * initialize these registers.
1872 : */
1873 : DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"
1874 : );
1875 :
1876 : /*
1877 : * FCAL/H and FCT are hardcoded to standard values in
1878 : * em_ich8lan / em_ich9lan / em_ich10lan.
1879 : */
1880 0 : if (!IS_ICH8(hw->mac_type)) {
1881 0 : E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1882 0 : E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1883 0 : E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1884 0 : }
1885 0 : E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1886 :
1887 0 : if (hw->phy_type == em_phy_82577 ||
1888 0 : hw->phy_type == em_phy_82578 ||
1889 0 : hw->phy_type == em_phy_82579 ||
1890 0 : hw->phy_type == em_phy_i217) {
1891 0 : E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000);
1892 0 : em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
1893 0 : hw->fc_pause_time);
1894 0 : }
1895 :
1896 : /*
1897 : * Set the flow control receive threshold registers. Normally, these
1898 : * registers will be set to a default threshold that may be adjusted
1899 : * later by the driver's runtime code. However, if the ability to
1900 : * transmit pause frames in not enabled, then these registers will be
1901 : * set to 0.
1902 : */
1903 0 : if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1904 0 : E1000_WRITE_REG(hw, FCRTL, 0);
1905 0 : E1000_WRITE_REG(hw, FCRTH, 0);
1906 0 : } else {
1907 : /*
1908 : * We need to set up the Receive Threshold high and low water
1909 : * marks as well as (optionally) enabling the transmission of
1910 : * XON frames.
1911 : */
1912 0 : if (hw->fc_send_xon) {
1913 0 : E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water
1914 : | E1000_FCRTL_XONE));
1915 0 : E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1916 0 : } else {
1917 0 : E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1918 0 : E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1919 : }
1920 : }
1921 0 : return ret_val;
1922 0 : }
1923 :
1924 : void
1925 0 : em_power_up_serdes_link_82575(struct em_hw *hw)
1926 : {
1927 : uint32_t reg;
1928 :
1929 : /* Enable PCS to turn on link */
1930 0 : reg = E1000_READ_REG(hw, PCS_CFG0);
1931 0 : reg |= E1000_PCS_CFG_PCS_EN;
1932 0 : E1000_WRITE_REG(hw, PCS_CFG0, reg);
1933 :
1934 : /* Power up the laser */
1935 0 : reg = E1000_READ_REG(hw, CTRL_EXT);
1936 0 : reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1937 0 : E1000_WRITE_REG(hw, CTRL_EXT, reg);
1938 :
1939 : /* flush the write to verify completion */
1940 0 : E1000_WRITE_FLUSH(hw);
1941 0 : delay(5);
1942 0 : }
1943 :
1944 : /******************************************************************************
1945 : * Sets up link for a fiber based or serdes based adapter
1946 : *
1947 : * hw - Struct containing variables accessed by shared code
1948 : *
1949 : * Manipulates Physical Coding Sublayer functions in order to configure
1950 : * link. Assumes the hardware has been previously reset and the transmitter
1951 : * and receiver are not enabled.
1952 : *****************************************************************************/
1953 : static int32_t
1954 0 : em_setup_fiber_serdes_link(struct em_hw *hw)
1955 : {
1956 : uint32_t ctrl, ctrl_ext, reg;
1957 : uint32_t status;
1958 : uint32_t txcw = 0;
1959 : uint32_t i;
1960 : uint32_t signal = 0;
1961 : int32_t ret_val;
1962 : DEBUGFUNC("em_setup_fiber_serdes_link");
1963 : /*
1964 : * On 82571 and 82572 Fiber connections, SerDes loopback mode
1965 : * persists until explicitly turned off or a power cycle is
1966 : * performed. A read to the register does not indicate its status.
1967 : * Therefore, we ensure loopback mode is disabled during
1968 : * initialization.
1969 : */
1970 0 : if (hw->mac_type == em_82571 || hw->mac_type == em_82572 ||
1971 0 : hw->mac_type >= em_82575)
1972 0 : E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1973 :
1974 0 : if (hw->mac_type >= em_82575)
1975 0 : em_power_up_serdes_link_82575(hw);
1976 :
1977 : /*
1978 : * On adapters with a MAC newer than 82544, SWDP 1 will be set when
1979 : * the optics detect a signal. On older adapters, it will be cleared
1980 : * when there is a signal. This applies to fiber media only. If
1981 : * we're on serdes media, adjust the output amplitude to value set in
1982 : * the EEPROM.
1983 : */
1984 0 : ctrl = E1000_READ_REG(hw, CTRL);
1985 0 : if (hw->media_type == em_media_type_fiber)
1986 0 : signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0;
1987 :
1988 0 : ret_val = em_adjust_serdes_amplitude(hw);
1989 0 : if (ret_val)
1990 0 : return ret_val;
1991 :
1992 : /* Take the link out of reset */
1993 0 : ctrl &= ~(E1000_CTRL_LRST);
1994 :
1995 0 : if (hw->mac_type >= em_82575) {
1996 : /* set both sw defined pins on 82575/82576*/
1997 0 : ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1998 :
1999 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2000 0 : switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
2001 : case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2002 : case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
2003 : /* the backplane is always connected */
2004 0 : reg = E1000_READ_REG(hw, PCS_LCTL);
2005 0 : reg |= E1000_PCS_LCTL_FORCE_FCTRL;
2006 0 : reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
2007 0 : reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
2008 : DEBUGOUT("Configuring Forced Link\n");
2009 0 : E1000_WRITE_REG(hw, PCS_LCTL, reg);
2010 0 : em_force_mac_fc(hw);
2011 0 : hw->autoneg_failed = 0;
2012 0 : return E1000_SUCCESS;
2013 : break;
2014 : default:
2015 : /* Set switch control to serdes energy detect */
2016 0 : reg = E1000_READ_REG(hw, CONNSW);
2017 0 : reg |= E1000_CONNSW_ENRGSRC;
2018 0 : E1000_WRITE_REG(hw, CONNSW, reg);
2019 : break;
2020 : }
2021 0 : }
2022 :
2023 : /* Adjust VCO speed to improve BER performance */
2024 0 : ret_val = em_set_vco_speed(hw);
2025 0 : if (ret_val)
2026 0 : return ret_val;
2027 :
2028 0 : em_config_collision_dist(hw);
2029 : /*
2030 : * Check for a software override of the flow control settings, and
2031 : * setup the device accordingly. If auto-negotiation is enabled,
2032 : * then software will have to set the "PAUSE" bits to the correct
2033 : * value in the Tranmsit Config Word Register (TXCW) and re-start
2034 : * auto-negotiation. However, if auto-negotiation is disabled, then
2035 : * software will have to manually configure the two flow control
2036 : * enable bits in the CTRL register.
2037 : *
2038 : * The possible values of the "fc" parameter are: 0: Flow control is
2039 : * completely disabled 1: Rx flow control is enabled (we can receive
2040 : * pause frames, but not send pause frames). 2: Tx flow control is
2041 : * enabled (we can send pause frames but we do not support receiving
2042 : * pause frames). 3: Both Rx and TX flow control (symmetric) are
2043 : * enabled.
2044 : */
2045 0 : switch (hw->fc) {
2046 : case E1000_FC_NONE:
2047 : /*
2048 : * Flow control is completely disabled by a software
2049 : * over-ride.
2050 : */
2051 : txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
2052 0 : break;
2053 : case E1000_FC_RX_PAUSE:
2054 : /*
2055 : * RX Flow control is enabled and TX Flow control is disabled
2056 : * by a software over-ride. Since there really isn't a way to
2057 : * advertise that we are capable of RX Pause ONLY, we will
2058 : * advertise that we support both symmetric and asymmetric RX
2059 : * PAUSE. Later, we will disable the adapter's ability to
2060 : * send PAUSE frames.
2061 : */
2062 : txcw = (E1000_TXCW_ANE | E1000_TXCW_FD |
2063 : E1000_TXCW_PAUSE_MASK);
2064 0 : break;
2065 : case E1000_FC_TX_PAUSE:
2066 : /*
2067 : * TX Flow control is enabled, and RX Flow control is
2068 : * disabled, by a software over-ride.
2069 : */
2070 : txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2071 0 : break;
2072 : case E1000_FC_FULL:
2073 : /*
2074 : * Flow control (both RX and TX) is enabled by a software
2075 : * over-ride.
2076 : */
2077 : txcw = (E1000_TXCW_ANE | E1000_TXCW_FD |
2078 : E1000_TXCW_PAUSE_MASK);
2079 0 : break;
2080 : default:
2081 : DEBUGOUT("Flow control param set incorrectly\n");
2082 0 : return -E1000_ERR_CONFIG;
2083 : break;
2084 : }
2085 : /*
2086 : * Since auto-negotiation is enabled, take the link out of reset (the
2087 : * link will be in reset, because we previously reset the chip). This
2088 : * will restart auto-negotiation. If auto-neogtiation is successful
2089 : * then the link-up status bit will be set and the flow control
2090 : * enable bits (RFCE and TFCE) will be set according to their
2091 : * negotiated value.
2092 : */
2093 : DEBUGOUT("Auto-negotiation enabled\n");
2094 :
2095 0 : E1000_WRITE_REG(hw, TXCW, txcw);
2096 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
2097 0 : E1000_WRITE_FLUSH(hw);
2098 :
2099 0 : hw->txcw = txcw;
2100 0 : msec_delay(1);
2101 : /*
2102 : * If we have a signal (the cable is plugged in) then poll for a
2103 : * "Link-Up" indication in the Device Status Register. Time-out if a
2104 : * link isn't seen in 500 milliseconds seconds (Auto-negotiation
2105 : * should complete in less than 500 milliseconds even if the other
2106 : * end is doing it in SW). For internal serdes, we just assume a
2107 : * signal is present, then poll.
2108 : */
2109 0 : if (hw->media_type == em_media_type_internal_serdes ||
2110 0 : (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2111 : DEBUGOUT("Looking for Link\n");
2112 0 : for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2113 0 : msec_delay(10);
2114 0 : status = E1000_READ_REG(hw, STATUS);
2115 0 : if (status & E1000_STATUS_LU)
2116 : break;
2117 : }
2118 0 : if (i == (LINK_UP_TIMEOUT / 10)) {
2119 : DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2120 0 : hw->autoneg_failed = 1;
2121 : /*
2122 : * AutoNeg failed to achieve a link, so we'll call
2123 : * em_check_for_link. This routine will force the
2124 : * link up if we detect a signal. This will allow us
2125 : * to communicate with non-autonegotiating link
2126 : * partners.
2127 : */
2128 0 : ret_val = em_check_for_link(hw);
2129 0 : if (ret_val) {
2130 : DEBUGOUT("Error while checking for link\n");
2131 0 : return ret_val;
2132 : }
2133 0 : hw->autoneg_failed = 0;
2134 0 : } else {
2135 0 : hw->autoneg_failed = 0;
2136 : DEBUGOUT("Valid Link Found\n");
2137 : }
2138 : } else {
2139 : DEBUGOUT("No Signal Detected\n");
2140 : }
2141 0 : return E1000_SUCCESS;
2142 0 : }
2143 :
2144 : /******************************************************************************
2145 : * Make sure we have a valid PHY and change PHY mode before link setup.
2146 : *
2147 : * hw - Struct containing variables accessed by shared code
2148 : *****************************************************************************/
2149 : static int32_t
2150 0 : em_copper_link_preconfig(struct em_hw *hw)
2151 : {
2152 : uint32_t ctrl;
2153 : int32_t ret_val;
2154 0 : uint16_t phy_data;
2155 : DEBUGFUNC("em_copper_link_preconfig");
2156 :
2157 0 : ctrl = E1000_READ_REG(hw, CTRL);
2158 : /*
2159 : * With 82543, we need to force speed and duplex on the MAC equal to
2160 : * what the PHY speed and duplex configuration is. In addition, we
2161 : * need to perform a hardware reset on the PHY to take it out of
2162 : * reset.
2163 : */
2164 0 : if (hw->mac_type > em_82543) {
2165 0 : ctrl |= E1000_CTRL_SLU;
2166 0 : ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2167 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
2168 0 : } else {
2169 0 : ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX |
2170 : E1000_CTRL_SLU);
2171 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
2172 0 : ret_val = em_phy_hw_reset(hw);
2173 0 : if (ret_val)
2174 0 : return ret_val;
2175 : }
2176 :
2177 : /* Set PHY to class A mode (if necessary) */
2178 0 : ret_val = em_set_phy_mode(hw);
2179 0 : if (ret_val)
2180 0 : return ret_val;
2181 :
2182 0 : if ((hw->mac_type == em_82545_rev_3) ||
2183 0 : (hw->mac_type == em_82546_rev_3)) {
2184 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2185 : &phy_data);
2186 0 : phy_data |= 0x00000008;
2187 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2188 : phy_data);
2189 0 : }
2190 0 : if (hw->mac_type <= em_82543 ||
2191 0 : hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
2192 0 : hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
2193 0 : hw->phy_reset_disable = FALSE;
2194 :
2195 0 : return E1000_SUCCESS;
2196 0 : }
2197 :
2198 : /******************************************************************************
2199 : * Copper link setup for em_phy_igp series.
2200 : *
2201 : * hw - Struct containing variables accessed by shared code
2202 : *****************************************************************************/
2203 : static int32_t
2204 0 : em_copper_link_igp_setup(struct em_hw *hw)
2205 : {
2206 : uint32_t led_ctrl;
2207 : int32_t ret_val;
2208 0 : uint16_t phy_data;
2209 : DEBUGFUNC("em_copper_link_igp_setup");
2210 :
2211 0 : if (hw->phy_reset_disable)
2212 0 : return E1000_SUCCESS;
2213 :
2214 0 : ret_val = em_phy_reset(hw);
2215 0 : if (ret_val) {
2216 : DEBUGOUT("Error Resetting the PHY\n");
2217 0 : return ret_val;
2218 : }
2219 : /* Wait 15ms for MAC to configure PHY from eeprom settings */
2220 0 : msec_delay(15);
2221 0 : if (hw->mac_type != em_ich8lan &&
2222 0 : hw->mac_type != em_ich9lan &&
2223 0 : hw->mac_type != em_ich10lan) {
2224 : /* Configure activity LED after PHY reset */
2225 0 : led_ctrl = E1000_READ_REG(hw, LEDCTL);
2226 0 : led_ctrl &= IGP_ACTIVITY_LED_MASK;
2227 0 : led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2228 0 : E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2229 0 : }
2230 : /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2231 0 : if (hw->phy_type == em_phy_igp) {
2232 : /* disable lplu d3 during driver init */
2233 0 : ret_val = em_set_d3_lplu_state(hw, FALSE);
2234 0 : if (ret_val) {
2235 : DEBUGOUT("Error Disabling LPLU D3\n");
2236 0 : return ret_val;
2237 : }
2238 : }
2239 : /* disable lplu d0 during driver init */
2240 0 : if (hw->mac_type == em_pchlan ||
2241 0 : hw->mac_type == em_pch2lan ||
2242 0 : hw->mac_type == em_pch_lpt ||
2243 0 : hw->mac_type == em_pch_spt ||
2244 0 : hw->mac_type == em_pch_cnp)
2245 0 : ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2246 : else
2247 0 : ret_val = em_set_d0_lplu_state(hw, FALSE);
2248 0 : if (ret_val) {
2249 : DEBUGOUT("Error Disabling LPLU D0\n");
2250 0 : return ret_val;
2251 : }
2252 : /* Configure mdi-mdix settings */
2253 0 : ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2254 0 : if (ret_val)
2255 0 : return ret_val;
2256 :
2257 0 : if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2258 0 : hw->dsp_config_state = em_dsp_config_disabled;
2259 : /* Force MDI for earlier revs of the IGP PHY */
2260 0 : phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
2261 : IGP01E1000_PSCR_FORCE_MDI_MDIX);
2262 0 : hw->mdix = 1;
2263 :
2264 0 : } else {
2265 0 : hw->dsp_config_state = em_dsp_config_enabled;
2266 0 : phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2267 :
2268 0 : switch (hw->mdix) {
2269 : case 1:
2270 0 : phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2271 0 : break;
2272 : case 2:
2273 0 : phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2274 0 : break;
2275 : case 0:
2276 : default:
2277 0 : phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2278 0 : break;
2279 : }
2280 : }
2281 0 : ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2282 0 : if (ret_val)
2283 0 : return ret_val;
2284 :
2285 : /* set auto-master slave resolution settings */
2286 0 : if (hw->autoneg) {
2287 0 : em_ms_type phy_ms_setting = hw->master_slave;
2288 0 : if (hw->ffe_config_state == em_ffe_config_active)
2289 0 : hw->ffe_config_state = em_ffe_config_enabled;
2290 :
2291 0 : if (hw->dsp_config_state == em_dsp_config_activated)
2292 0 : hw->dsp_config_state = em_dsp_config_enabled;
2293 : /*
2294 : * when autonegotiation advertisement is only 1000Mbps then
2295 : * we should disable SmartSpeed and enable Auto MasterSlave
2296 : * resolution as hardware default.
2297 : */
2298 0 : if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2299 : /* Disable SmartSpeed */
2300 0 : ret_val = em_read_phy_reg(hw,
2301 : IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2302 0 : if (ret_val)
2303 0 : return ret_val;
2304 :
2305 0 : phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2306 0 : ret_val = em_write_phy_reg(hw,
2307 : IGP01E1000_PHY_PORT_CONFIG, phy_data);
2308 0 : if (ret_val)
2309 0 : return ret_val;
2310 : /* Set auto Master/Slave resolution process */
2311 0 : ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
2312 : &phy_data);
2313 0 : if (ret_val)
2314 0 : return ret_val;
2315 :
2316 0 : phy_data &= ~CR_1000T_MS_ENABLE;
2317 0 : ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
2318 : phy_data);
2319 0 : if (ret_val)
2320 0 : return ret_val;
2321 : }
2322 0 : ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2323 0 : if (ret_val)
2324 0 : return ret_val;
2325 :
2326 : /* load defaults for future use */
2327 0 : hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2328 0 : ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master :
2329 : em_ms_force_slave) : em_ms_auto;
2330 :
2331 0 : switch (phy_ms_setting) {
2332 : case em_ms_force_master:
2333 0 : phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2334 0 : break;
2335 : case em_ms_force_slave:
2336 0 : phy_data |= CR_1000T_MS_ENABLE;
2337 0 : phy_data &= ~(CR_1000T_MS_VALUE);
2338 0 : break;
2339 : case em_ms_auto:
2340 0 : phy_data &= ~CR_1000T_MS_ENABLE;
2341 0 : break;
2342 : default:
2343 : break;
2344 : }
2345 0 : ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2346 0 : if (ret_val)
2347 0 : return ret_val;
2348 0 : }
2349 0 : return E1000_SUCCESS;
2350 0 : }
2351 :
2352 : /******************************************************************************
2353 : * Copper link setup for em_phy_gg82563 series.
2354 : *
2355 : * hw - Struct containing variables accessed by shared code
2356 : *****************************************************************************/
2357 : static int32_t
2358 0 : em_copper_link_ggp_setup(struct em_hw *hw)
2359 : {
2360 : int32_t ret_val;
2361 0 : uint16_t phy_data;
2362 : uint32_t reg_data;
2363 : DEBUGFUNC("em_copper_link_ggp_setup");
2364 :
2365 0 : if (!hw->phy_reset_disable) {
2366 :
2367 : /* Enable CRS on TX for half-duplex operation. */
2368 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
2369 : &phy_data);
2370 0 : if (ret_val)
2371 0 : return ret_val;
2372 :
2373 0 : phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2374 : /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2375 0 : phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2376 :
2377 0 : ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
2378 : phy_data);
2379 0 : if (ret_val)
2380 0 : return ret_val;
2381 : /*
2382 : * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1
2383 : * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only
2384 : * (MDI-X for 10/100Base-T modes)
2385 : */
2386 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL,
2387 : &phy_data);
2388 :
2389 0 : if (ret_val)
2390 0 : return ret_val;
2391 :
2392 0 : phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2393 :
2394 0 : switch (hw->mdix) {
2395 : case 1:
2396 0 : phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2397 0 : break;
2398 : case 2:
2399 0 : phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2400 0 : break;
2401 : case 0:
2402 : default:
2403 0 : phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2404 0 : break;
2405 : }
2406 : /*
2407 : * Options: disable_polarity_correction = 0 (default)
2408 : * Automatic Correction for Reversed Cable Polarity 0 -
2409 : * Disabled 1 - Enabled
2410 : */
2411 0 : phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2412 0 : if (hw->disable_polarity_correction == 1)
2413 0 : phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2414 0 : ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL,
2415 0 : phy_data);
2416 :
2417 0 : if (ret_val)
2418 0 : return ret_val;
2419 :
2420 : /* SW Reset the PHY so all changes take effect */
2421 0 : ret_val = em_phy_reset(hw);
2422 0 : if (ret_val) {
2423 : DEBUGOUT("Error Resetting the PHY\n");
2424 0 : return ret_val;
2425 : }
2426 : } /* phy_reset_disable */
2427 0 : if (hw->mac_type == em_80003es2lan) {
2428 : /* Bypass RX and TX FIFO's */
2429 0 : ret_val = em_write_kmrn_reg(hw,
2430 : E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2431 : E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
2432 : E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2433 0 : if (ret_val)
2434 0 : return ret_val;
2435 :
2436 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2,
2437 : &phy_data);
2438 0 : if (ret_val)
2439 0 : return ret_val;
2440 :
2441 0 : phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2442 0 : ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2,
2443 : phy_data);
2444 :
2445 0 : if (ret_val)
2446 0 : return ret_val;
2447 :
2448 0 : reg_data = E1000_READ_REG(hw, CTRL_EXT);
2449 0 : reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2450 0 : E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2451 :
2452 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
2453 : &phy_data);
2454 0 : if (ret_val)
2455 0 : return ret_val;
2456 : /*
2457 : * Do not init these registers when the HW is in IAMT mode,
2458 : * since the firmware will have already initialized them. We
2459 : * only initialize them if the HW is not in IAMT mode.
2460 : */
2461 0 : if (em_check_mng_mode(hw) == FALSE) {
2462 : /* Enable Electrical Idle on the PHY */
2463 0 : phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2464 0 : ret_val = em_write_phy_reg(hw,
2465 : GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2466 0 : if (ret_val)
2467 0 : return ret_val;
2468 :
2469 0 : ret_val = em_read_phy_reg(hw,
2470 : GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2471 0 : if (ret_val)
2472 0 : return ret_val;
2473 :
2474 0 : phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2475 0 : ret_val = em_write_phy_reg(hw,
2476 : GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2477 :
2478 0 : if (ret_val)
2479 0 : return ret_val;
2480 : }
2481 : /*
2482 : * Workaround: Disable padding in Kumeran interface in the
2483 : * MAC and in the PHY to avoid CRC errors.
2484 : */
2485 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
2486 : &phy_data);
2487 0 : if (ret_val)
2488 0 : return ret_val;
2489 0 : phy_data |= GG82563_ICR_DIS_PADDING;
2490 0 : ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
2491 : phy_data);
2492 0 : if (ret_val)
2493 0 : return ret_val;
2494 : }
2495 0 : return E1000_SUCCESS;
2496 0 : }
2497 :
2498 : /******************************************************************************
2499 : * Copper link setup for em_phy_m88 series.
2500 : *
2501 : * hw - Struct containing variables accessed by shared code
2502 : *****************************************************************************/
2503 : static int32_t
2504 0 : em_copper_link_mgp_setup(struct em_hw *hw)
2505 : {
2506 : int32_t ret_val;
2507 0 : uint16_t phy_data;
2508 : DEBUGFUNC("em_copper_link_mgp_setup");
2509 :
2510 0 : if (hw->phy_reset_disable)
2511 0 : return E1000_SUCCESS;
2512 :
2513 : /* disable lplu d0 during driver init */
2514 0 : if (hw->mac_type == em_pchlan ||
2515 0 : hw->mac_type == em_pch2lan ||
2516 0 : hw->mac_type == em_pch_lpt ||
2517 0 : hw->mac_type == em_pch_spt ||
2518 0 : hw->mac_type == em_pch_cnp)
2519 0 : ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2520 :
2521 : /* Enable CRS on TX. This must be set for half-duplex operation. */
2522 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2523 0 : if (ret_val)
2524 0 : return ret_val;
2525 :
2526 0 : if (hw->phy_id == M88E1141_E_PHY_ID) {
2527 0 : phy_data |= 0x00000008;
2528 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2529 : phy_data);
2530 0 : if (ret_val)
2531 0 : return ret_val;
2532 :
2533 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2534 : &phy_data);
2535 0 : if (ret_val)
2536 0 : return ret_val;
2537 :
2538 0 : phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX;
2539 :
2540 0 : }
2541 : /* For BM PHY this bit is downshift enable */
2542 0 : else if (hw->phy_type != em_phy_bm)
2543 0 : phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2544 : /*
2545 : * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI
2546 : * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for
2547 : * 10/100Base-T modes)
2548 : */
2549 0 : phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2550 :
2551 0 : switch (hw->mdix) {
2552 : case 1:
2553 0 : phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2554 0 : break;
2555 : case 2:
2556 0 : phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2557 0 : break;
2558 : case 3:
2559 0 : phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2560 0 : break;
2561 : case 0:
2562 : default:
2563 0 : phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2564 0 : break;
2565 : }
2566 : /*
2567 : * Options: disable_polarity_correction = 0 (default) Automatic
2568 : * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled
2569 : */
2570 0 : phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2571 0 : if (hw->disable_polarity_correction == 1)
2572 0 : phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
2573 :
2574 : /* Enable downshift on BM (disabled by default) */
2575 0 : if (hw->phy_type == em_phy_bm)
2576 0 : phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
2577 :
2578 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2579 0 : if (ret_val)
2580 0 : return ret_val;
2581 :
2582 0 : if (((hw->phy_type == em_phy_m88) &&
2583 0 : (hw->phy_revision < M88E1011_I_REV_4) &&
2584 0 : (hw->phy_id != BME1000_E_PHY_ID)) ||
2585 0 : (hw->phy_type == em_phy_oem)) {
2586 : /*
2587 : * Force TX_CLK in the Extended PHY Specific Control Register
2588 : * to 25MHz clock.
2589 : */
2590 0 : ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2591 : &phy_data);
2592 0 : if (ret_val)
2593 0 : return ret_val;
2594 :
2595 0 : if (hw->phy_type == em_phy_oem) {
2596 0 : phy_data |= M88E1000_EPSCR_TX_TIME_CTRL;
2597 0 : phy_data |= M88E1000_EPSCR_RX_TIME_CTRL;
2598 0 : }
2599 0 : phy_data |= M88E1000_EPSCR_TX_CLK_25;
2600 :
2601 0 : if ((hw->phy_revision == E1000_REVISION_2) &&
2602 0 : (hw->phy_id == M88E1111_I_PHY_ID)) {
2603 : /* Vidalia Phy, set the downshift counter to 5x */
2604 0 : phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2605 0 : phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2606 0 : ret_val = em_write_phy_reg(hw,
2607 : M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2608 0 : if (ret_val)
2609 0 : return ret_val;
2610 : } else {
2611 : /* Configure Master and Slave downshift values */
2612 0 : phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
2613 : M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2614 0 : phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
2615 : M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2616 0 : ret_val = em_write_phy_reg(hw,
2617 : M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2618 0 : if (ret_val)
2619 0 : return ret_val;
2620 : }
2621 : }
2622 0 : if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
2623 : /*
2624 : * Set PHY page 0, register 29 to 0x0003
2625 : * The next two writes are supposed to lower BER for gig
2626 : * conection
2627 : */
2628 0 : ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003);
2629 0 : if (ret_val)
2630 0 : return ret_val;
2631 :
2632 : /* Set PHY page 0, register 30 to 0x0000 */
2633 0 : ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000);
2634 0 : if (ret_val)
2635 0 : return ret_val;
2636 : }
2637 0 : if (hw->phy_type == em_phy_82578) {
2638 0 : ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2639 : &phy_data);
2640 0 : if (ret_val)
2641 0 : return ret_val;
2642 :
2643 : /* 82578 PHY - set the downshift count to 1x. */
2644 0 : phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
2645 0 : phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
2646 0 : ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2647 : phy_data);
2648 0 : if (ret_val)
2649 0 : return ret_val;
2650 : }
2651 : /* SW Reset the PHY so all changes take effect */
2652 0 : ret_val = em_phy_reset(hw);
2653 0 : if (ret_val) {
2654 : DEBUGOUT("Error Resetting the PHY\n");
2655 0 : return ret_val;
2656 : }
2657 0 : return E1000_SUCCESS;
2658 0 : }
2659 :
2660 : /******************************************************************************
2661 : * Copper link setup for em_phy_82577 series.
2662 : *
2663 : * hw - Struct containing variables accessed by shared code
2664 : *****************************************************************************/
2665 : static int32_t
2666 0 : em_copper_link_82577_setup(struct em_hw *hw)
2667 : {
2668 : int32_t ret_val;
2669 0 : uint16_t phy_data;
2670 : uint32_t led_ctl;
2671 : DEBUGFUNC("em_copper_link_82577_setup");
2672 :
2673 0 : if (hw->phy_reset_disable)
2674 0 : return E1000_SUCCESS;
2675 :
2676 : /* Enable CRS on TX for half-duplex operation. */
2677 0 : ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data);
2678 0 : if (ret_val)
2679 0 : return ret_val;
2680 :
2681 0 : phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX |
2682 : I82577_PHY_CFG_ENABLE_DOWNSHIFT;
2683 :
2684 0 : ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data);
2685 0 : if (ret_val)
2686 0 : return ret_val;
2687 :
2688 : /* Wait 15ms for MAC to configure PHY from eeprom settings */
2689 0 : msec_delay(15);
2690 0 : led_ctl = hw->ledctl_mode1;
2691 :
2692 : /* disable lplu d0 during driver init */
2693 0 : ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2694 0 : if (ret_val) {
2695 : DEBUGOUT("Error Disabling LPLU D0\n");
2696 0 : return ret_val;
2697 : }
2698 :
2699 0 : E1000_WRITE_REG(hw, LEDCTL, led_ctl);
2700 :
2701 0 : return E1000_SUCCESS;
2702 0 : }
2703 :
2704 : static int32_t
2705 0 : em_copper_link_82580_setup(struct em_hw *hw)
2706 : {
2707 : int32_t ret_val;
2708 0 : uint16_t phy_data;
2709 :
2710 0 : if (hw->phy_reset_disable)
2711 0 : return E1000_SUCCESS;
2712 :
2713 0 : ret_val = em_phy_reset(hw);
2714 0 : if (ret_val)
2715 : goto out;
2716 :
2717 : /* Enable CRS on TX. This must be set for half-duplex operation. */
2718 0 : ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data);
2719 0 : if (ret_val)
2720 : goto out;
2721 :
2722 0 : phy_data |= I82580_CFG_ASSERT_CRS_ON_TX |
2723 : I82580_CFG_ENABLE_DOWNSHIFT;
2724 :
2725 0 : ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data);
2726 :
2727 : out:
2728 0 : return ret_val;
2729 0 : }
2730 :
2731 : static int32_t
2732 0 : em_copper_link_rtl8211_setup(struct em_hw *hw)
2733 : {
2734 : int32_t ret_val;
2735 0 : uint16_t phy_data;
2736 :
2737 : DEBUGFUNC("em_copper_link_rtl8211_setup: begin");
2738 :
2739 0 : if (!hw) {
2740 0 : return -1;
2741 : }
2742 : /* SW Reset the PHY so all changes take effect */
2743 0 : em_phy_hw_reset(hw);
2744 :
2745 : /* Enable CRS on TX. This must be set for half-duplex operation. */
2746 0 : phy_data = 0;
2747 :
2748 0 : ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
2749 0 : if (ret_val) {
2750 0 : printf("Unable to read RGEPHY_CR register\n");
2751 0 : return ret_val;
2752 : }
2753 : DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id,
2754 : hw->phy_addr, phy_data);
2755 0 : phy_data |= RGEPHY_CR_ASSERT_CRS;
2756 :
2757 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
2758 0 : if (ret_val) {
2759 0 : printf("Unable to write RGEPHY_CR register\n");
2760 0 : return ret_val;
2761 : }
2762 :
2763 0 : phy_data = 0; /* LED Control Register 0x18 */
2764 0 : ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data);
2765 0 : if (ret_val) {
2766 0 : printf("Unable to read RGEPHY_LC register\n");
2767 0 : return ret_val;
2768 : }
2769 :
2770 0 : phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */
2771 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data);
2772 0 : if (ret_val) {
2773 0 : printf("Unable to write RGEPHY_LC register\n");
2774 0 : return ret_val;
2775 : }
2776 : /* LED Control and Definition Register 0x11, PHY spec status reg */
2777 0 : phy_data = 0;
2778 0 : ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data);
2779 0 : if (ret_val) {
2780 0 : printf("Unable to read RGEPHY_SR register\n");
2781 0 : return ret_val;
2782 : }
2783 :
2784 0 : phy_data |= 0x0010; /* LED active Low */
2785 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data);
2786 0 : if (ret_val) {
2787 0 : printf("Unable to write RGEPHY_SR register\n");
2788 0 : return ret_val;
2789 : }
2790 :
2791 0 : phy_data = 0;
2792 0 : ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data);
2793 0 : if (ret_val) {
2794 0 : printf("Unable to read RGEPHY_SR register\n");
2795 0 : return ret_val;
2796 : }
2797 :
2798 : /* Switch to Page2 */
2799 0 : phy_data = RGEPHY_PS_PAGE_2;
2800 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data);
2801 0 : if (ret_val) {
2802 0 : printf("Unable to write PHY RGEPHY_PS register\n");
2803 0 : return ret_val;
2804 : }
2805 :
2806 0 : phy_data = 0x0000;
2807 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data);
2808 0 : if (ret_val) {
2809 0 : printf("Unable to write RGEPHY_LC_P2 register\n");
2810 0 : return ret_val;
2811 : }
2812 0 : usec_delay(5);
2813 :
2814 :
2815 : /* LED Configuration Control Reg for setting for 0x1A Register */
2816 0 : phy_data = 0;
2817 0 : ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data);
2818 0 : if (ret_val) {
2819 0 : printf("Unable to read RGEPHY_LC_P2 register\n");
2820 0 : return ret_val;
2821 : }
2822 :
2823 0 : phy_data &= 0xF000;
2824 0 : phy_data |= 0x0F24;
2825 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data);
2826 0 : if (ret_val) {
2827 0 : printf("Unable to write RGEPHY_LC_P2 register\n");
2828 0 : return ret_val;
2829 : }
2830 0 : phy_data = 0;
2831 0 : ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data);
2832 0 : if (ret_val) {
2833 0 : printf("Unable to read RGEPHY_LC_P2 register\n");
2834 0 : return ret_val;
2835 : }
2836 : DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data);
2837 :
2838 :
2839 : /* After setting Page2, go back to Page 0 */
2840 0 : phy_data = 0;
2841 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data);
2842 0 : if (ret_val) {
2843 0 : printf("Unable to write PHY RGEPHY_PS register\n");
2844 0 : return ret_val;
2845 : }
2846 :
2847 : /* pulse streching= 42-84ms, blink rate=84mm */
2848 0 : phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK |
2849 : RGEPHY_LC_DUPLEX | RGEPHY_LC_RX;
2850 :
2851 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data);
2852 0 : if (ret_val) {
2853 0 : printf("Unable to write RGEPHY_LC register\n");
2854 0 : return ret_val;
2855 : }
2856 0 : return E1000_SUCCESS;
2857 0 : }
2858 :
2859 : /******************************************************************************
2860 : * Setup auto-negotiation and flow control advertisements,
2861 : * and then perform auto-negotiation.
2862 : *
2863 : * hw - Struct containing variables accessed by shared code
2864 : *****************************************************************************/
2865 : int32_t
2866 0 : em_copper_link_autoneg(struct em_hw *hw)
2867 : {
2868 : int32_t ret_val;
2869 0 : uint16_t phy_data;
2870 : DEBUGFUNC("em_copper_link_autoneg");
2871 : /*
2872 : * Perform some bounds checking on the hw->autoneg_advertised
2873 : * parameter. If this variable is zero, then set it to the default.
2874 : */
2875 0 : hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2876 : /*
2877 : * If autoneg_advertised is zero, we assume it was not defaulted by
2878 : * the calling code so we set to advertise full capability.
2879 : */
2880 0 : if (hw->autoneg_advertised == 0)
2881 0 : hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2882 :
2883 : /* IFE phy only supports 10/100 */
2884 0 : if (hw->phy_type == em_phy_ife)
2885 0 : hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2886 :
2887 : DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2888 0 : ret_val = em_phy_setup_autoneg(hw);
2889 0 : if (ret_val) {
2890 : DEBUGOUT("Error Setting up Auto-Negotiation\n");
2891 0 : return ret_val;
2892 : }
2893 : DEBUGOUT("Restarting Auto-Neg\n");
2894 : /*
2895 : * Restart auto-negotiation by setting the Auto Neg Enable bit and
2896 : * the Auto Neg Restart bit in the PHY control register.
2897 : */
2898 0 : ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
2899 0 : if (ret_val)
2900 0 : return ret_val;
2901 :
2902 0 : phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
2903 0 : ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
2904 0 : if (ret_val)
2905 0 : return ret_val;
2906 : /*
2907 : * Does the user want to wait for Auto-Neg to complete here, or check
2908 : * at a later time (for example, callback routine).
2909 : */
2910 0 : if (hw->wait_autoneg_complete) {
2911 0 : ret_val = em_wait_autoneg(hw);
2912 0 : if (ret_val) {
2913 : DEBUGOUT("Error while waiting for autoneg to complete\n"
2914 : );
2915 0 : return ret_val;
2916 : }
2917 : }
2918 0 : hw->get_link_status = TRUE;
2919 :
2920 0 : return E1000_SUCCESS;
2921 0 : }
2922 :
2923 : /******************************************************************************
2924 : * Config the MAC and the PHY after link is up.
2925 : * 1) Set up the MAC to the current PHY speed/duplex
2926 : * if we are on 82543. If we
2927 : * are on newer silicon, we only need to configure
2928 : * collision distance in the Transmit Control Register.
2929 : * 2) Set up flow control on the MAC to that established with
2930 : * the link partner.
2931 : * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2932 : *
2933 : * hw - Struct containing variables accessed by shared code
2934 : *****************************************************************************/
2935 : int32_t
2936 0 : em_copper_link_postconfig(struct em_hw *hw)
2937 : {
2938 : int32_t ret_val;
2939 : DEBUGFUNC("em_copper_link_postconfig");
2940 :
2941 0 : if (hw->mac_type >= em_82544 &&
2942 0 : hw->mac_type != em_icp_xxxx) {
2943 0 : em_config_collision_dist(hw);
2944 0 : } else {
2945 0 : ret_val = em_config_mac_to_phy(hw);
2946 0 : if (ret_val) {
2947 : DEBUGOUT("Error configuring MAC to PHY settings\n");
2948 0 : return ret_val;
2949 : }
2950 : }
2951 0 : ret_val = em_config_fc_after_link_up(hw);
2952 0 : if (ret_val) {
2953 : DEBUGOUT("Error Configuring Flow Control\n");
2954 0 : return ret_val;
2955 : }
2956 : /* Config DSP to improve Giga link quality */
2957 0 : if (hw->phy_type == em_phy_igp) {
2958 0 : ret_val = em_config_dsp_after_link_change(hw, TRUE);
2959 0 : if (ret_val) {
2960 : DEBUGOUT("Error Configuring DSP after link up\n");
2961 0 : return ret_val;
2962 : }
2963 : }
2964 0 : return E1000_SUCCESS;
2965 0 : }
2966 :
2967 : /******************************************************************************
2968 : * Detects which PHY is present and setup the speed and duplex
2969 : *
2970 : * hw - Struct containing variables accessed by shared code
2971 : *****************************************************************************/
2972 : static int32_t
2973 0 : em_setup_copper_link(struct em_hw *hw)
2974 : {
2975 : int32_t ret_val;
2976 : uint16_t i;
2977 0 : uint16_t phy_data;
2978 0 : uint16_t reg_data;
2979 : DEBUGFUNC("em_setup_copper_link");
2980 :
2981 0 : switch (hw->mac_type) {
2982 : case em_80003es2lan:
2983 : case em_ich8lan:
2984 : case em_ich9lan:
2985 : case em_ich10lan:
2986 : case em_pchlan:
2987 : case em_pch2lan:
2988 : case em_pch_lpt:
2989 : case em_pch_spt:
2990 : case em_pch_cnp:
2991 : /*
2992 : * Set the mac to wait the maximum time between each
2993 : * iteration and increase the max iterations when polling the
2994 : * phy; this fixes erroneous timeouts at 10Mbps.
2995 : */
2996 0 : ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2997 0 : if (ret_val)
2998 0 : return ret_val;
2999 0 : ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9),
3000 : ®_data);
3001 0 : if (ret_val)
3002 0 : return ret_val;
3003 0 : reg_data |= 0x3F;
3004 0 : ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9),
3005 : reg_data);
3006 0 : if (ret_val)
3007 0 : return ret_val;
3008 : default:
3009 : break;
3010 : }
3011 :
3012 : /* Check if it is a valid PHY and set PHY mode if necessary. */
3013 0 : ret_val = em_copper_link_preconfig(hw);
3014 0 : if (ret_val)
3015 0 : return ret_val;
3016 :
3017 0 : switch (hw->mac_type) {
3018 : case em_80003es2lan:
3019 : /* Kumeran registers are written-only */
3020 : reg_data =
3021 : E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3022 0 : reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3023 0 : ret_val = em_write_kmrn_reg(hw,
3024 : E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3025 0 : if (ret_val)
3026 0 : return ret_val;
3027 : break;
3028 : default:
3029 : break;
3030 : }
3031 :
3032 0 : if (hw->phy_type == em_phy_igp ||
3033 0 : hw->phy_type == em_phy_igp_3 ||
3034 0 : hw->phy_type == em_phy_igp_2) {
3035 0 : ret_val = em_copper_link_igp_setup(hw);
3036 0 : if (ret_val)
3037 0 : return ret_val;
3038 0 : } else if (hw->phy_type == em_phy_m88 ||
3039 0 : hw->phy_type == em_phy_bm ||
3040 0 : hw->phy_type == em_phy_oem ||
3041 0 : hw->phy_type == em_phy_82578) {
3042 0 : ret_val = em_copper_link_mgp_setup(hw);
3043 0 : if (ret_val)
3044 0 : return ret_val;
3045 0 : } else if (hw->phy_type == em_phy_gg82563) {
3046 0 : ret_val = em_copper_link_ggp_setup(hw);
3047 0 : if (ret_val)
3048 0 : return ret_val;
3049 0 : } else if (hw->phy_type == em_phy_82577 ||
3050 0 : hw->phy_type == em_phy_82579 ||
3051 0 : hw->phy_type == em_phy_i217) {
3052 0 : ret_val = em_copper_link_82577_setup(hw);
3053 0 : if (ret_val)
3054 0 : return ret_val;
3055 0 : } else if (hw->phy_type == em_phy_82580) {
3056 0 : ret_val = em_copper_link_82580_setup(hw);
3057 0 : if (ret_val)
3058 0 : return ret_val;
3059 0 : } else if (hw->phy_type == em_phy_rtl8211) {
3060 0 : ret_val = em_copper_link_rtl8211_setup(hw);
3061 0 : if (ret_val)
3062 0 : return ret_val;
3063 : }
3064 0 : if (hw->autoneg) {
3065 : /*
3066 : * Setup autoneg and flow control advertisement and perform
3067 : * autonegotiation
3068 : */
3069 0 : ret_val = em_copper_link_autoneg(hw);
3070 0 : if (ret_val)
3071 0 : return ret_val;
3072 : } else {
3073 : /*
3074 : * PHY will be set to 10H, 10F, 100H,or 100F depending on
3075 : * value from forced_speed_duplex.
3076 : */
3077 : DEBUGOUT("Forcing speed and duplex\n");
3078 0 : ret_val = em_phy_force_speed_duplex(hw);
3079 0 : if (ret_val) {
3080 : DEBUGOUT("Error Forcing Speed and Duplex\n");
3081 0 : return ret_val;
3082 : }
3083 : }
3084 : /*
3085 : * Check link status. Wait up to 100 microseconds for link to become
3086 : * valid.
3087 : */
3088 0 : for (i = 0; i < 10; i++) {
3089 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3090 0 : if (ret_val)
3091 0 : return ret_val;
3092 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3093 0 : if (ret_val)
3094 0 : return ret_val;
3095 :
3096 0 : hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0;
3097 :
3098 0 : if (phy_data & MII_SR_LINK_STATUS) {
3099 : /* Config the MAC and PHY after link is up */
3100 0 : ret_val = em_copper_link_postconfig(hw);
3101 0 : if (ret_val)
3102 0 : return ret_val;
3103 :
3104 : DEBUGOUT("Valid link established!!!\n");
3105 0 : return E1000_SUCCESS;
3106 : }
3107 0 : usec_delay(10);
3108 : }
3109 :
3110 : DEBUGOUT("Unable to establish link!!!\n");
3111 0 : return E1000_SUCCESS;
3112 0 : }
3113 :
3114 : /******************************************************************************
3115 : * Configure the MAC-to-PHY interface for 10/100Mbps
3116 : *
3117 : * hw - Struct containing variables accessed by shared code
3118 : *****************************************************************************/
3119 : static int32_t
3120 0 : em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex)
3121 : {
3122 : int32_t ret_val = E1000_SUCCESS;
3123 : uint32_t tipg;
3124 0 : uint16_t reg_data;
3125 : DEBUGFUNC("em_configure_kmrn_for_10_100");
3126 :
3127 0 : reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3128 0 : ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
3129 : reg_data);
3130 0 : if (ret_val)
3131 0 : return ret_val;
3132 :
3133 : /* Configure Transmit Inter-Packet Gap */
3134 0 : tipg = E1000_READ_REG(hw, TIPG);
3135 0 : tipg &= ~E1000_TIPG_IPGT_MASK;
3136 0 : tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3137 0 : E1000_WRITE_REG(hw, TIPG, tipg);
3138 :
3139 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3140 :
3141 0 : if (ret_val)
3142 0 : return ret_val;
3143 :
3144 0 : if (duplex == HALF_DUPLEX)
3145 0 : reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3146 : else
3147 0 : reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3148 :
3149 0 : ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3150 :
3151 0 : return ret_val;
3152 0 : }
3153 :
3154 : static int32_t
3155 0 : em_configure_kmrn_for_1000(struct em_hw *hw)
3156 : {
3157 : int32_t ret_val = E1000_SUCCESS;
3158 0 : uint16_t reg_data;
3159 : uint32_t tipg;
3160 : DEBUGFUNC("em_configure_kmrn_for_1000");
3161 :
3162 0 : reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3163 0 : ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
3164 : reg_data);
3165 0 : if (ret_val)
3166 0 : return ret_val;
3167 :
3168 : /* Configure Transmit Inter-Packet Gap */
3169 0 : tipg = E1000_READ_REG(hw, TIPG);
3170 0 : tipg &= ~E1000_TIPG_IPGT_MASK;
3171 0 : tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3172 0 : E1000_WRITE_REG(hw, TIPG, tipg);
3173 :
3174 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3175 :
3176 0 : if (ret_val)
3177 0 : return ret_val;
3178 :
3179 0 : reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3180 0 : ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3181 :
3182 0 : return ret_val;
3183 0 : }
3184 :
3185 : /******************************************************************************
3186 : * Configures PHY autoneg and flow control advertisement settings
3187 : *
3188 : * hw - Struct containing variables accessed by shared code
3189 : *****************************************************************************/
3190 : int32_t
3191 0 : em_phy_setup_autoneg(struct em_hw *hw)
3192 : {
3193 : int32_t ret_val;
3194 0 : uint16_t mii_autoneg_adv_reg;
3195 0 : uint16_t mii_1000t_ctrl_reg;
3196 : DEBUGFUNC("em_phy_setup_autoneg");
3197 :
3198 : /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3199 0 : ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3200 0 : if (ret_val)
3201 0 : return ret_val;
3202 :
3203 0 : if (hw->phy_type != em_phy_ife) {
3204 : /* Read the MII 1000Base-T Control Register (Address 9). */
3205 0 : ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
3206 : &mii_1000t_ctrl_reg);
3207 0 : if (ret_val)
3208 0 : return ret_val;
3209 : } else
3210 0 : mii_1000t_ctrl_reg = 0;
3211 : /*
3212 : * Need to parse both autoneg_advertised and fc and set up the
3213 : * appropriate PHY registers. First we will parse for
3214 : * autoneg_advertised software override. Since we can advertise a
3215 : * plethora of combinations, we need to check each bit individually.
3216 : */
3217 : /*
3218 : * First we clear all the 10/100 mb speed bits in the Auto-Neg
3219 : * Advertisement Register (Address 4) and the 1000 mb speed bits in
3220 : * the 1000Base-T Control Register (Address 9).
3221 : */
3222 0 : mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3223 0 : mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3224 :
3225 : DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
3226 :
3227 : /* Do we want to advertise 10 Mb Half Duplex? */
3228 0 : if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3229 : DEBUGOUT("Advertise 10mb Half duplex\n");
3230 0 : mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3231 0 : }
3232 : /* Do we want to advertise 10 Mb Full Duplex? */
3233 0 : if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3234 : DEBUGOUT("Advertise 10mb Full duplex\n");
3235 0 : mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3236 0 : }
3237 : /* Do we want to advertise 100 Mb Half Duplex? */
3238 0 : if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3239 : DEBUGOUT("Advertise 100mb Half duplex\n");
3240 0 : mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3241 0 : }
3242 : /* Do we want to advertise 100 Mb Full Duplex? */
3243 0 : if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3244 : DEBUGOUT("Advertise 100mb Full duplex\n");
3245 0 : mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3246 0 : }
3247 : /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3248 0 : if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3249 : DEBUGOUT("Advertise 1000mb Half duplex requested, request"
3250 : " denied!\n");
3251 : }
3252 : /* Do we want to advertise 1000 Mb Full Duplex? */
3253 0 : if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3254 : DEBUGOUT("Advertise 1000mb Full duplex\n");
3255 0 : mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3256 0 : if (hw->phy_type == em_phy_ife) {
3257 : DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is"
3258 : " not supported.\n");
3259 : }
3260 0 : }
3261 : /*
3262 : * Check for a software override of the flow control settings, and
3263 : * setup the PHY advertisement registers accordingly. If
3264 : * auto-negotiation is enabled, then software will have to set the
3265 : * "PAUSE" bits to the correct value in the Auto-Negotiation
3266 : * Advertisement Register (PHY_AUTONEG_ADV) and re-start
3267 : * auto-negotiation.
3268 : *
3269 : * The possible values of the "fc" parameter are: 0: Flow control is
3270 : * completely disabled 1: Rx flow control is enabled (we can receive
3271 : * pause frames but not send pause frames). 2: Tx flow control is
3272 : * enabled (we can send pause frames but we do not support receiving
3273 : * pause frames). 3: Both Rx and TX flow control (symmetric) are
3274 : * enabled. other: No software override. The flow control
3275 : * configuration in the EEPROM is used.
3276 : */
3277 0 : switch (hw->fc) {
3278 : case E1000_FC_NONE: /* 0 */
3279 : /*
3280 : * Flow control (RX & TX) is completely disabled by a
3281 : * software over-ride.
3282 : */
3283 0 : mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3284 0 : break;
3285 : case E1000_FC_RX_PAUSE:/* 1 */
3286 : /*
3287 : * RX Flow control is enabled, and TX Flow control is
3288 : * disabled, by a software over-ride.
3289 : */
3290 : /*
3291 : * Since there really isn't a way to advertise that we are
3292 : * capable of RX Pause ONLY, we will advertise that we
3293 : * support both symmetric and asymmetric RX PAUSE. Later (in
3294 : * em_config_fc_after_link_up) we will disable the hw's
3295 : * ability to send PAUSE frames.
3296 : */
3297 0 : mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3298 0 : break;
3299 : case E1000_FC_TX_PAUSE:/* 2 */
3300 : /*
3301 : * TX Flow control is enabled, and RX Flow control is
3302 : * disabled, by a software over-ride.
3303 : */
3304 0 : mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3305 0 : mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3306 0 : break;
3307 : case E1000_FC_FULL: /* 3 */
3308 : /*
3309 : * Flow control (both RX and TX) is enabled by a software
3310 : * over-ride.
3311 : */
3312 0 : mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3313 0 : break;
3314 : default:
3315 : DEBUGOUT("Flow control param set incorrectly\n");
3316 0 : return -E1000_ERR_CONFIG;
3317 : }
3318 :
3319 0 : ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3320 0 : if (ret_val)
3321 0 : return ret_val;
3322 :
3323 : DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3324 :
3325 0 : if (hw->phy_type != em_phy_ife) {
3326 0 : ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
3327 0 : mii_1000t_ctrl_reg);
3328 0 : if (ret_val)
3329 0 : return ret_val;
3330 : }
3331 0 : return E1000_SUCCESS;
3332 0 : }
3333 : /******************************************************************************
3334 : * Force PHY speed and duplex settings to hw->forced_speed_duplex
3335 : *
3336 : * hw - Struct containing variables accessed by shared code
3337 : *****************************************************************************/
3338 : static int32_t
3339 0 : em_phy_force_speed_duplex(struct em_hw *hw)
3340 : {
3341 : uint32_t ctrl;
3342 : int32_t ret_val;
3343 0 : uint16_t mii_ctrl_reg;
3344 0 : uint16_t mii_status_reg;
3345 0 : uint16_t phy_data;
3346 : uint16_t i;
3347 : DEBUGFUNC("em_phy_force_speed_duplex");
3348 :
3349 : /* Turn off Flow control if we are forcing speed and duplex. */
3350 0 : hw->fc = E1000_FC_NONE;
3351 :
3352 : DEBUGOUT1("hw->fc = %d\n", hw->fc);
3353 :
3354 : /* Read the Device Control Register. */
3355 0 : ctrl = E1000_READ_REG(hw, CTRL);
3356 :
3357 : /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
3358 0 : ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3359 0 : ctrl &= ~(DEVICE_SPEED_MASK);
3360 :
3361 : /* Clear the Auto Speed Detect Enable bit. */
3362 0 : ctrl &= ~E1000_CTRL_ASDE;
3363 :
3364 : /* Read the MII Control Register. */
3365 0 : ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
3366 0 : if (ret_val)
3367 0 : return ret_val;
3368 :
3369 : /* We need to disable autoneg in order to force link and duplex. */
3370 :
3371 0 : mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
3372 :
3373 : /* Are we forcing Full or Half Duplex? */
3374 0 : if (hw->forced_speed_duplex == em_100_full ||
3375 0 : hw->forced_speed_duplex == em_10_full) {
3376 : /*
3377 : * We want to force full duplex so we SET the full duplex
3378 : * bits in the Device and MII Control Registers.
3379 : */
3380 0 : ctrl |= E1000_CTRL_FD;
3381 0 : mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
3382 : DEBUGOUT("Full Duplex\n");
3383 0 : } else {
3384 : /*
3385 : * We want to force half duplex so we CLEAR the full duplex
3386 : * bits in the Device and MII Control Registers.
3387 : */
3388 0 : ctrl &= ~E1000_CTRL_FD;
3389 0 : mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
3390 : DEBUGOUT("Half Duplex\n");
3391 : }
3392 :
3393 : /* Are we forcing 100Mbps??? */
3394 0 : if (hw->forced_speed_duplex == em_100_full ||
3395 0 : hw->forced_speed_duplex == em_100_half) {
3396 : /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
3397 0 : ctrl |= E1000_CTRL_SPD_100;
3398 0 : mii_ctrl_reg |= MII_CR_SPEED_100;
3399 0 : mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
3400 : DEBUGOUT("Forcing 100mb ");
3401 0 : } else {
3402 : /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
3403 0 : ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
3404 0 : mii_ctrl_reg |= MII_CR_SPEED_10;
3405 0 : mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
3406 : DEBUGOUT("Forcing 10mb ");
3407 : }
3408 :
3409 0 : em_config_collision_dist(hw);
3410 :
3411 : /* Write the configured values back to the Device Control Reg. */
3412 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
3413 :
3414 0 : if ((hw->phy_type == em_phy_m88) ||
3415 0 : (hw->phy_type == em_phy_gg82563) ||
3416 0 : (hw->phy_type == em_phy_bm) ||
3417 0 : (hw->phy_type == em_phy_oem ||
3418 0 : (hw->phy_type == em_phy_82578))) {
3419 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3420 : &phy_data);
3421 0 : if (ret_val)
3422 0 : return ret_val;
3423 : /*
3424 : * Clear Auto-Crossover to force MDI manually. M88E1000
3425 : * requires MDI forced whenever speed are duplex are forced.
3426 : */
3427 0 : phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3428 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3429 : phy_data);
3430 0 : if (ret_val)
3431 0 : return ret_val;
3432 :
3433 : DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
3434 :
3435 : /* Need to reset the PHY or these changes will be ignored */
3436 0 : mii_ctrl_reg |= MII_CR_RESET;
3437 :
3438 0 : }
3439 0 : else if (hw->phy_type == em_phy_rtl8211) {
3440 0 : ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
3441 0 : if(ret_val) {
3442 0 : printf("Unable to read RGEPHY_CR register\n"
3443 : );
3444 0 : return ret_val;
3445 : }
3446 :
3447 : /*
3448 : * Clear Auto-Crossover to force MDI manually. RTL8211 requires
3449 : * MDI forced whenever speed are duplex are forced.
3450 : */
3451 :
3452 0 : phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX
3453 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
3454 0 : if(ret_val) {
3455 0 : printf("Unable to write RGEPHY_CR register\n");
3456 0 : return ret_val;
3457 : }
3458 0 : mii_ctrl_reg |= MII_CR_RESET;
3459 :
3460 0 : }
3461 : /* Disable MDI-X support for 10/100 */
3462 0 : else if (hw->phy_type == em_phy_ife) {
3463 0 : ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
3464 0 : if (ret_val)
3465 0 : return ret_val;
3466 :
3467 0 : phy_data &= ~IFE_PMC_AUTO_MDIX;
3468 0 : phy_data &= ~IFE_PMC_FORCE_MDIX;
3469 :
3470 0 : ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
3471 0 : if (ret_val)
3472 0 : return ret_val;
3473 : } else {
3474 : /*
3475 : * Clear Auto-Crossover to force MDI manually. IGP requires
3476 : * MDI forced whenever speed or duplex are forced.
3477 : */
3478 0 : ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
3479 : &phy_data);
3480 0 : if (ret_val)
3481 0 : return ret_val;
3482 :
3483 0 : phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
3484 0 : phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
3485 :
3486 0 : ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
3487 : phy_data);
3488 0 : if (ret_val)
3489 0 : return ret_val;
3490 : }
3491 :
3492 : /* Write back the modified PHY MII control register. */
3493 0 : ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
3494 0 : if (ret_val)
3495 0 : return ret_val;
3496 :
3497 0 : usec_delay(1);
3498 : /*
3499 : * The wait_autoneg_complete flag may be a little misleading here.
3500 : * Since we are forcing speed and duplex, Auto-Neg is not enabled.
3501 : * But we do want to delay for a period while forcing only so we
3502 : * don't generate false No Link messages. So we will wait here only
3503 : * if the user has set wait_autoneg_complete to 1, which is the
3504 : * default.
3505 : */
3506 0 : if (hw->wait_autoneg_complete) {
3507 : /* We will wait for autoneg to complete. */
3508 : DEBUGOUT("Waiting for forced speed/duplex link.\n");
3509 0 : mii_status_reg = 0;
3510 : /*
3511 : * We will wait for autoneg to complete or 4.5 seconds to
3512 : * expire.
3513 : */
3514 0 : for (i = PHY_FORCE_TIME; i > 0; i--) {
3515 : /*
3516 : * Read the MII Status Register and wait for Auto-Neg
3517 : * Complete bit to be set.
3518 : */
3519 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS,
3520 : &mii_status_reg);
3521 0 : if (ret_val)
3522 0 : return ret_val;
3523 :
3524 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS,
3525 : &mii_status_reg);
3526 0 : if (ret_val)
3527 0 : return ret_val;
3528 :
3529 0 : if (mii_status_reg & MII_SR_LINK_STATUS)
3530 : break;
3531 0 : msec_delay(100);
3532 : }
3533 0 : if ((i == 0) &&
3534 0 : ((hw->phy_type == em_phy_m88) ||
3535 0 : (hw->phy_type == em_phy_gg82563) ||
3536 0 : (hw->phy_type == em_phy_bm))) {
3537 : /*
3538 : * We didn't get link. Reset the DSP and wait again
3539 : * for link.
3540 : */
3541 0 : ret_val = em_phy_reset_dsp(hw);
3542 0 : if (ret_val) {
3543 : DEBUGOUT("Error Resetting PHY DSP\n");
3544 0 : return ret_val;
3545 : }
3546 : }
3547 : /*
3548 : * This loop will early-out if the link condition has been
3549 : * met.
3550 : */
3551 0 : for (i = PHY_FORCE_TIME; i > 0; i--) {
3552 0 : if (mii_status_reg & MII_SR_LINK_STATUS)
3553 : break;
3554 0 : msec_delay(100);
3555 : /*
3556 : * Read the MII Status Register and wait for Auto-Neg
3557 : * Complete bit to be set.
3558 : */
3559 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS,
3560 : &mii_status_reg);
3561 0 : if (ret_val)
3562 0 : return ret_val;
3563 :
3564 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS,
3565 : &mii_status_reg);
3566 0 : if (ret_val)
3567 0 : return ret_val;
3568 : }
3569 : }
3570 0 : if (hw->phy_type == em_phy_m88 ||
3571 0 : hw->phy_type == em_phy_bm ||
3572 0 : hw->phy_type == em_phy_oem) {
3573 : /*
3574 : * Because we reset the PHY above, we need to re-force TX_CLK
3575 : * in the Extended PHY Specific Control Register to 25MHz
3576 : * clock. This value defaults back to a 2.5MHz clock when
3577 : * the PHY is reset.
3578 : */
3579 0 : ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
3580 : &phy_data);
3581 0 : if (ret_val)
3582 0 : return ret_val;
3583 :
3584 0 : phy_data |= M88E1000_EPSCR_TX_CLK_25;
3585 0 : ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
3586 : phy_data);
3587 0 : if (ret_val)
3588 0 : return ret_val;
3589 : /*
3590 : * In addition, because of the s/w reset above, we need to
3591 : * enable CRS on TX. This must be set for both full and half
3592 : * duplex operation.
3593 : */
3594 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3595 : &phy_data);
3596 0 : if (ret_val)
3597 0 : return ret_val;
3598 :
3599 0 : if (hw->phy_id == M88E1141_E_PHY_ID)
3600 0 : phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX;
3601 : else
3602 0 : phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3603 :
3604 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3605 0 : phy_data);
3606 0 : if (ret_val)
3607 0 : return ret_val;
3608 :
3609 0 : if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
3610 0 : (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full ||
3611 0 : hw->forced_speed_duplex == em_10_half)) {
3612 0 : ret_val = em_polarity_reversal_workaround(hw);
3613 0 : if (ret_val)
3614 0 : return ret_val;
3615 : }
3616 0 : } else if (hw->phy_type == em_phy_rtl8211) {
3617 : /*
3618 : * In addition, because of the s/w reset above, we need to enable
3619 : * CRX on TX. This must be set for both full and half duplex
3620 : * operation.
3621 : */
3622 :
3623 0 : ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
3624 0 : if(ret_val) {
3625 0 : printf("Unable to read RGEPHY_CR register\n");
3626 0 : return ret_val;
3627 : }
3628 :
3629 0 : phy_data &= ~RGEPHY_CR_ASSERT_CRS;
3630 0 : ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
3631 0 : if(ret_val) {
3632 0 : printf("Unable to write RGEPHY_CR register\n");
3633 0 : return ret_val;
3634 : }
3635 0 : } else if (hw->phy_type == em_phy_gg82563) {
3636 : /*
3637 : * The TX_CLK of the Extended PHY Specific Control Register
3638 : * defaults to 2.5MHz on a reset. We need to re-force it
3639 : * back to 25MHz, if we're not in a forced 10/duplex
3640 : * configuration.
3641 : */
3642 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
3643 : &phy_data);
3644 0 : if (ret_val)
3645 0 : return ret_val;
3646 :
3647 0 : phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
3648 0 : if ((hw->forced_speed_duplex == em_10_full) ||
3649 0 : (hw->forced_speed_duplex == em_10_half))
3650 0 : phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
3651 : else
3652 0 : phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
3653 :
3654 : /* Also due to the reset, we need to enable CRS on Tx. */
3655 0 : phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
3656 :
3657 0 : ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
3658 : phy_data);
3659 0 : if (ret_val)
3660 0 : return ret_val;
3661 : }
3662 0 : return E1000_SUCCESS;
3663 0 : }
3664 :
3665 : /******************************************************************************
3666 : * Sets the collision distance in the Transmit Control register
3667 : *
3668 : * hw - Struct containing variables accessed by shared code
3669 : *
3670 : * Link should have been established previously. Reads the speed and duplex
3671 : * information from the Device Status register.
3672 : *****************************************************************************/
3673 : void
3674 0 : em_config_collision_dist(struct em_hw *hw)
3675 : {
3676 : uint32_t tctl, coll_dist;
3677 : DEBUGFUNC("em_config_collision_dist");
3678 :
3679 0 : if (hw->mac_type < em_82543)
3680 0 : coll_dist = E1000_COLLISION_DISTANCE_82542;
3681 : else
3682 : coll_dist = E1000_COLLISION_DISTANCE;
3683 :
3684 0 : tctl = E1000_READ_REG(hw, TCTL);
3685 :
3686 0 : tctl &= ~E1000_TCTL_COLD;
3687 0 : tctl |= coll_dist << E1000_COLD_SHIFT;
3688 :
3689 0 : E1000_WRITE_REG(hw, TCTL, tctl);
3690 0 : E1000_WRITE_FLUSH(hw);
3691 0 : }
3692 :
3693 : /******************************************************************************
3694 : * Sets MAC speed and duplex settings to reflect the those in the PHY
3695 : *
3696 : * hw - Struct containing variables accessed by shared code
3697 : * mii_reg - data to write to the MII control register
3698 : *
3699 : * The contents of the PHY register containing the needed information need to
3700 : * be passed in.
3701 : *****************************************************************************/
3702 : static int32_t
3703 0 : em_config_mac_to_phy(struct em_hw *hw)
3704 : {
3705 : uint32_t ctrl;
3706 : int32_t ret_val;
3707 0 : uint16_t phy_data;
3708 : DEBUGFUNC("em_config_mac_to_phy");
3709 : /*
3710 : * 82544 or newer MAC, Auto Speed Detection takes care of MAC
3711 : * speed/duplex configuration.
3712 : */
3713 0 : if (hw->mac_type >= em_82544
3714 0 : && hw->mac_type != em_icp_xxxx)
3715 0 : return E1000_SUCCESS;
3716 : /*
3717 : * Read the Device Control Register and set the bits to Force Speed
3718 : * and Duplex.
3719 : */
3720 0 : ctrl = E1000_READ_REG(hw, CTRL);
3721 0 : ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3722 0 : ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3723 : /*
3724 : * Set up duplex in the Device Control and Transmit Control registers
3725 : * depending on negotiated values.
3726 : */
3727 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3728 0 : if (ret_val)
3729 0 : return ret_val;
3730 :
3731 0 : if (phy_data & M88E1000_PSSR_DPLX)
3732 0 : ctrl |= E1000_CTRL_FD;
3733 : else
3734 0 : ctrl &= ~E1000_CTRL_FD;
3735 :
3736 0 : em_config_collision_dist(hw);
3737 : /*
3738 : * Set up speed in the Device Control register depending on
3739 : * negotiated values.
3740 : */
3741 0 : if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3742 0 : ctrl |= E1000_CTRL_SPD_1000;
3743 0 : else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3744 0 : ctrl |= E1000_CTRL_SPD_100;
3745 :
3746 : /* Write the configured values back to the Device Control Reg. */
3747 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
3748 0 : return E1000_SUCCESS;
3749 0 : }
3750 :
3751 : /******************************************************************************
3752 : * Forces the MAC's flow control settings.
3753 : *
3754 : * hw - Struct containing variables accessed by shared code
3755 : *
3756 : * Sets the TFCE and RFCE bits in the device control register to reflect
3757 : * the adapter settings. TFCE and RFCE need to be explicitly set by
3758 : * software when a Copper PHY is used because autonegotiation is managed
3759 : * by the PHY rather than the MAC. Software must also configure these
3760 : * bits when link is forced on a fiber connection.
3761 : *****************************************************************************/
3762 : int32_t
3763 0 : em_force_mac_fc(struct em_hw *hw)
3764 : {
3765 : uint32_t ctrl;
3766 : DEBUGFUNC("em_force_mac_fc");
3767 :
3768 : /* Get the current configuration of the Device Control Register */
3769 0 : ctrl = E1000_READ_REG(hw, CTRL);
3770 : /*
3771 : * Because we didn't get link via the internal auto-negotiation
3772 : * mechanism (we either forced link or we got link via PHY auto-neg),
3773 : * we have to manually enable/disable transmit an receive flow
3774 : * control.
3775 : *
3776 : * The "Case" statement below enables/disable flow control according to
3777 : * the "hw->fc" parameter.
3778 : *
3779 : * The possible values of the "fc" parameter are: 0: Flow control is
3780 : * completely disabled 1: Rx flow control is enabled (we can receive
3781 : * pause frames but not send pause frames). 2: Tx flow control is
3782 : * enabled (we can send pause frames frames but we do not receive
3783 : * pause frames). 3: Both Rx and TX flow control (symmetric) is
3784 : * enabled. other: No other values should be possible at this point.
3785 : */
3786 :
3787 0 : switch (hw->fc) {
3788 : case E1000_FC_NONE:
3789 0 : ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3790 0 : break;
3791 : case E1000_FC_RX_PAUSE:
3792 0 : ctrl &= (~E1000_CTRL_TFCE);
3793 0 : ctrl |= E1000_CTRL_RFCE;
3794 0 : break;
3795 : case E1000_FC_TX_PAUSE:
3796 0 : ctrl &= (~E1000_CTRL_RFCE);
3797 0 : ctrl |= E1000_CTRL_TFCE;
3798 0 : break;
3799 : case E1000_FC_FULL:
3800 0 : ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3801 0 : break;
3802 : default:
3803 : DEBUGOUT("Flow control param set incorrectly\n");
3804 0 : return -E1000_ERR_CONFIG;
3805 : }
3806 :
3807 : /* Disable TX Flow Control for 82542 (rev 2.0) */
3808 0 : if (hw->mac_type == em_82542_rev2_0)
3809 0 : ctrl &= (~E1000_CTRL_TFCE);
3810 :
3811 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
3812 0 : return E1000_SUCCESS;
3813 0 : }
3814 : /******************************************************************************
3815 : * Configures flow control settings after link is established
3816 : *
3817 : * hw - Struct containing variables accessed by shared code
3818 : *
3819 : * Should be called immediately after a valid link has been established.
3820 : * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3821 : * and autonegotiation is enabled, the MAC flow control settings will be set
3822 : * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3823 : * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3824 : *****************************************************************************/
3825 : STATIC int32_t
3826 0 : em_config_fc_after_link_up(struct em_hw *hw)
3827 : {
3828 : int32_t ret_val;
3829 0 : uint16_t mii_status_reg;
3830 0 : uint16_t mii_nway_adv_reg;
3831 0 : uint16_t mii_nway_lp_ability_reg;
3832 0 : uint16_t speed;
3833 0 : uint16_t duplex;
3834 : DEBUGFUNC("em_config_fc_after_link_up");
3835 : /*
3836 : * Check for the case where we have fiber media and auto-neg failed
3837 : * so we had to force link. In this case, we need to force the
3838 : * configuration of the MAC to match the "fc" parameter.
3839 : */
3840 0 : if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed))
3841 0 : || ((hw->media_type == em_media_type_internal_serdes) &&
3842 0 : (hw->autoneg_failed)) ||
3843 0 : ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) ||
3844 0 : ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) {
3845 0 : ret_val = em_force_mac_fc(hw);
3846 0 : if (ret_val) {
3847 : DEBUGOUT("Error forcing flow control settings\n");
3848 0 : return ret_val;
3849 : }
3850 : }
3851 : /*
3852 : * Check for the case where we have copper media and auto-neg is
3853 : * enabled. In this case, we need to check and see if Auto-Neg has
3854 : * completed, and if so, how the PHY and link partner has flow
3855 : * control configured.
3856 : */
3857 0 : if ((hw->media_type == em_media_type_copper ||
3858 0 : (hw->media_type == em_media_type_oem)) &&
3859 0 : hw->autoneg) {
3860 : /*
3861 : * Read the MII Status Register and check to see if AutoNeg
3862 : * has completed. We read this twice because this reg has
3863 : * some "sticky" (latched) bits.
3864 : */
3865 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
3866 0 : if (ret_val)
3867 0 : return ret_val;
3868 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
3869 0 : if (ret_val)
3870 0 : return ret_val;
3871 :
3872 0 : if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3873 : /*
3874 : * The AutoNeg process has completed, so we now need
3875 : * to read both the Auto Negotiation Advertisement
3876 : * Register (Address 4) and the Auto_Negotiation Base
3877 : * Page Ability Register (Address 5) to determine how
3878 : * flow control was negotiated.
3879 : */
3880 0 : ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
3881 : &mii_nway_adv_reg);
3882 0 : if (ret_val)
3883 0 : return ret_val;
3884 0 : ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
3885 : &mii_nway_lp_ability_reg);
3886 0 : if (ret_val)
3887 0 : return ret_val;
3888 : /*
3889 : * Two bits in the Auto Negotiation Advertisement
3890 : * Register (Address 4) and two bits in the Auto
3891 : * Negotiation Base Page Ability Register (Address 5)
3892 : * determine flow control for both the PHY and the
3893 : * link partner. The following table, taken out of
3894 : * the IEEE 802.3ab/D6.0 dated March 25, 1999,
3895 : * describes these PAUSE resolution bits and how flow
3896 : * control is determined based upon these settings.
3897 : * NOTE: DC = Don't Care
3898 : *
3899 : * LOCAL DEVICE | LINK PARTNER |
3900 : * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3901 : * -------|---------|-------|---------|---------------
3902 : * 0 | 0 | DC | DC | em_fc_none
3903 : * 0 | 1 | 0 | DC | em_fc_none
3904 : * 0 | 1 | 1 | 0 | em_fc_none
3905 : * 0 | 1 | 1 | 1 | em_fc_tx_pause
3906 : * 1 | 0 | 0 | DC | em_fc_none
3907 : * 1 | DC | 1 | DC | em_fc_full
3908 : * 1 | 1 | 0 | 0 | em_fc_none
3909 : * 1 | 1 | 0 | 1 | em_fc_rx_pause
3910 : *
3911 : */
3912 : /*
3913 : * Are both PAUSE bits set to 1? If so, this implies
3914 : * Symmetric Flow Control is enabled at both ends.
3915 : * The ASM_DIR bits are irrelevant per the spec.
3916 : *
3917 : * For Symmetric Flow Control:
3918 : *
3919 : * LOCAL DEVICE | LINK PARTNER
3920 : * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3921 : * -------|---------|-------|---------|---------------
3922 : * 1 | DC | 1 | DC | em_fc_full
3923 : *
3924 : */
3925 0 : if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3926 0 : (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3927 : /*
3928 : * Now we need to check if the user selected
3929 : * RX ONLY of pause frames. In this case, we
3930 : * had to advertise FULL flow control because
3931 : * we could not advertise RX ONLY. Hence, we
3932 : * must now check to see if we need to turn
3933 : * OFF the TRANSMISSION of PAUSE frames.
3934 : */
3935 0 : if (hw->original_fc == E1000_FC_FULL) {
3936 0 : hw->fc = E1000_FC_FULL;
3937 : DEBUGOUT("Flow Control = FULL.\n");
3938 0 : } else {
3939 0 : hw->fc = E1000_FC_RX_PAUSE;
3940 : DEBUGOUT("Flow Control = RX PAUSE"
3941 : " frames only.\n");
3942 : }
3943 : }
3944 : /*
3945 : * For receiving PAUSE frames ONLY.
3946 : *
3947 : * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR |
3948 : * PAUSE | ASM_DIR | Result
3949 : * -------|---------|-------|---------|---------------
3950 : * ----- 0 | 1 | 1 | 1 |
3951 : * em_fc_tx_pause
3952 : *
3953 : */
3954 0 : else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3955 0 : (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3956 0 : (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3957 0 : (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
3958 0 : hw->fc = E1000_FC_TX_PAUSE;
3959 : DEBUGOUT("Flow Control = TX PAUSE frames only."
3960 : "\n");
3961 0 : }
3962 : /*
3963 : * For transmitting PAUSE frames ONLY.
3964 : *
3965 : * LOCAL DEVICE | LINK PARTNER
3966 : * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3967 : * -------|---------|-------|---------|---------------
3968 : * 1 | 1 | 0 | 1 | em_fc_rx_pause
3969 : *
3970 : */
3971 0 : else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3972 0 : (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3973 0 : !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3974 0 : (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
3975 0 : hw->fc = E1000_FC_RX_PAUSE;
3976 : DEBUGOUT("Flow Control = RX PAUSE frames only."
3977 : "\n");
3978 0 : }
3979 : /*
3980 : * Per the IEEE spec, at this point flow control
3981 : * should be disabled. However, we want to consider
3982 : * that we could be connected to a legacy switch that
3983 : * doesn't advertise desired flow control, but can be
3984 : * forced on the link partner. So if we advertised
3985 : * no flow control, that is what we will resolve to.
3986 : * If we advertised some kind of receive capability
3987 : * (Rx Pause Only or Full Flow Control) and the link
3988 : * partner advertised none, we will configure
3989 : * ourselves to enable Rx Flow Control only. We can
3990 : * do this safely for two reasons: If the link
3991 : * partner really didn't want flow control enabled,
3992 : * and we enable Rx, no harm done since we won't be
3993 : * receiving any PAUSE frames anyway. If the intent
3994 : * on the link partner was to have flow control
3995 : * enabled, then by us enabling RX only, we can at
3996 : * least receive pause frames and process them. This
3997 : * is a good idea because in most cases, since we are
3998 : * predominantly a server NIC, more times than not we
3999 : * will be asked to delay transmission of packets
4000 : * than asking our link partner to pause transmission
4001 : * of frames.
4002 : */
4003 0 : else if ((hw->original_fc == E1000_FC_NONE ||
4004 0 : hw->original_fc == E1000_FC_TX_PAUSE) ||
4005 0 : hw->fc_strict_ieee) {
4006 0 : hw->fc = E1000_FC_NONE;
4007 : DEBUGOUT("Flow Control = NONE.\n");
4008 0 : } else {
4009 0 : hw->fc = E1000_FC_RX_PAUSE;
4010 : DEBUGOUT("Flow Control = RX PAUSE frames only."
4011 : "\n");
4012 : }
4013 : /*
4014 : * Now we need to do one last check... If we auto-
4015 : * negotiated to HALF DUPLEX, flow control should not
4016 : * be enabled per IEEE 802.3 spec.
4017 : */
4018 0 : ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4019 0 : if (ret_val) {
4020 : DEBUGOUT("Error getting link speed and duplex"
4021 : "\n");
4022 0 : return ret_val;
4023 : }
4024 0 : if (duplex == HALF_DUPLEX)
4025 0 : hw->fc = E1000_FC_NONE;
4026 : /*
4027 : * Now we call a subroutine to actually force the MAC
4028 : * controller to use the correct flow control
4029 : * settings.
4030 : */
4031 0 : ret_val = em_force_mac_fc(hw);
4032 0 : if (ret_val) {
4033 : DEBUGOUT("Error forcing flow control settings"
4034 : "\n");
4035 0 : return ret_val;
4036 : }
4037 : } else {
4038 : DEBUGOUT("Copper PHY and Auto Neg has not completed."
4039 : "\n");
4040 : }
4041 : }
4042 0 : return E1000_SUCCESS;
4043 0 : }
4044 : /******************************************************************************
4045 : * Checks to see if the link status of the hardware has changed.
4046 : *
4047 : * hw - Struct containing variables accessed by shared code
4048 : *
4049 : * Called by any function that needs to check the link status of the adapter.
4050 : *****************************************************************************/
4051 : int32_t
4052 0 : em_check_for_link(struct em_hw *hw)
4053 : {
4054 : uint32_t rxcw = 0;
4055 : uint32_t ctrl;
4056 : uint32_t status;
4057 : uint32_t rctl;
4058 : uint32_t icr;
4059 : uint32_t signal = 0;
4060 : int32_t ret_val;
4061 0 : uint16_t phy_data;
4062 : DEBUGFUNC("em_check_for_link");
4063 0 : uint16_t speed, duplex;
4064 :
4065 0 : if (hw->mac_type >= em_82575 &&
4066 0 : hw->media_type != em_media_type_copper) {
4067 0 : ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed,
4068 : &duplex);
4069 0 : hw->get_link_status = hw->serdes_link_down;
4070 :
4071 0 : return (ret_val);
4072 : }
4073 :
4074 0 : ctrl = E1000_READ_REG(hw, CTRL);
4075 0 : status = E1000_READ_REG(hw, STATUS);
4076 : /*
4077 : * On adapters with a MAC newer than 82544, SW Defineable pin 1 will
4078 : * be set when the optics detect a signal. On older adapters, it will
4079 : * be cleared when there is a signal. This applies to fiber media
4080 : * only.
4081 : */
4082 0 : if ((hw->media_type == em_media_type_fiber) ||
4083 0 : (hw->media_type == em_media_type_internal_serdes)) {
4084 0 : rxcw = E1000_READ_REG(hw, RXCW);
4085 :
4086 0 : if (hw->media_type == em_media_type_fiber) {
4087 0 : signal = (hw->mac_type > em_82544) ?
4088 : E1000_CTRL_SWDPIN1 : 0;
4089 0 : if (status & E1000_STATUS_LU)
4090 0 : hw->get_link_status = FALSE;
4091 : }
4092 : }
4093 : /*
4094 : * If we have a copper PHY then we only want to go out to the PHY
4095 : * registers to see if Auto-Neg has completed and/or if our link
4096 : * status has changed. The get_link_status flag will be set if we
4097 : * receive a Link Status Change interrupt or we have Rx Sequence
4098 : * Errors.
4099 : */
4100 0 : if ((hw->media_type == em_media_type_copper ||
4101 0 : (hw->media_type == em_media_type_oem)) &&
4102 0 : hw->get_link_status) {
4103 : /*
4104 : * First we want to see if the MII Status Register reports
4105 : * link. If so, then we want to get the current speed/duplex
4106 : * of the PHY. Read the register twice since the link bit is
4107 : * sticky.
4108 : */
4109 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4110 0 : if (ret_val)
4111 0 : return ret_val;
4112 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4113 0 : if (ret_val)
4114 0 : return ret_val;
4115 :
4116 0 : hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0;
4117 :
4118 0 : if (hw->mac_type == em_pchlan) {
4119 0 : ret_val = em_k1_gig_workaround_hv(hw,
4120 : hw->icp_xxxx_is_link_up);
4121 0 : if (ret_val)
4122 0 : return ret_val;
4123 : }
4124 :
4125 0 : if (phy_data & MII_SR_LINK_STATUS) {
4126 0 : hw->get_link_status = FALSE;
4127 :
4128 0 : if (hw->phy_type == em_phy_82578) {
4129 0 : ret_val = em_link_stall_workaround_hv(hw);
4130 0 : if (ret_val)
4131 0 : return ret_val;
4132 : }
4133 :
4134 0 : if (hw->mac_type == em_pch2lan) {
4135 0 : ret_val = em_k1_workaround_lv(hw);
4136 0 : if (ret_val)
4137 0 : return ret_val;
4138 : }
4139 : /* Work-around I218 hang issue */
4140 0 : if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4141 0 : (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4142 0 : (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4143 0 : (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
4144 0 : ret_val = em_k1_workaround_lpt_lp(hw,
4145 0 : hw->icp_xxxx_is_link_up);
4146 0 : if (ret_val)
4147 0 : return ret_val;
4148 : }
4149 :
4150 : /*
4151 : * Check if there was DownShift, must be checked
4152 : * immediately after link-up
4153 : */
4154 0 : em_check_downshift(hw);
4155 :
4156 : /* Enable/Disable EEE after link up */
4157 0 : if (hw->mac_type == em_pch2lan ||
4158 0 : hw->mac_type == em_pch_lpt ||
4159 0 : hw->mac_type == em_pch_spt ||
4160 0 : hw->mac_type == em_pch_cnp) {
4161 0 : ret_val = em_set_eee_pchlan(hw);
4162 0 : if (ret_val)
4163 0 : return ret_val;
4164 : }
4165 :
4166 : /*
4167 : * If we are on 82544 or 82543 silicon and
4168 : * speed/duplex are forced to 10H or 10F, then we
4169 : * will implement the polarity reversal workaround.
4170 : * We disable interrupts first, and upon returning,
4171 : * place the devices interrupt state to its previous
4172 : * value except for the link status change interrupt
4173 : * which will happen due to the execution of this
4174 : * workaround.
4175 : */
4176 0 : if ((hw->mac_type == em_82544 ||
4177 0 : hw->mac_type == em_82543) && (!hw->autoneg) &&
4178 0 : (hw->forced_speed_duplex == em_10_full ||
4179 0 : hw->forced_speed_duplex == em_10_half)) {
4180 0 : E1000_WRITE_REG(hw, IMC, 0xffffffff);
4181 0 : ret_val = em_polarity_reversal_workaround(hw);
4182 0 : icr = E1000_READ_REG(hw, ICR);
4183 0 : E1000_WRITE_REG(hw, ICS,
4184 : (icr & ~E1000_ICS_LSC));
4185 0 : E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
4186 0 : }
4187 : } else {
4188 : /* No link detected */
4189 0 : em_config_dsp_after_link_change(hw, FALSE);
4190 0 : return 0;
4191 : }
4192 : /*
4193 : * If we are forcing speed/duplex, then we simply return
4194 : * since we have already determined whether we have link or
4195 : * not.
4196 : */
4197 0 : if (!hw->autoneg)
4198 0 : return -E1000_ERR_CONFIG;
4199 :
4200 : /* optimize the dsp settings for the igp phy */
4201 0 : em_config_dsp_after_link_change(hw, TRUE);
4202 : /*
4203 : * We have a M88E1000 PHY and Auto-Neg is enabled. If we
4204 : * have Si on board that is 82544 or newer, Auto Speed
4205 : * Detection takes care of MAC speed/duplex configuration.
4206 : * So we only need to configure Collision Distance in the
4207 : * MAC. Otherwise, we need to force speed/duplex on the MAC
4208 : * to the current PHY speed/duplex settings.
4209 : */
4210 0 : if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) {
4211 0 : em_config_collision_dist(hw);
4212 0 : } else {
4213 0 : ret_val = em_config_mac_to_phy(hw);
4214 0 : if (ret_val) {
4215 : DEBUGOUT("Error configuring MAC to PHY"
4216 : " settings\n");
4217 0 : return ret_val;
4218 : }
4219 : }
4220 : /*
4221 : * Configure Flow Control now that Auto-Neg has completed.
4222 : * First, we need to restore the desired flow control
4223 : * settings because we may have had to re-autoneg with a
4224 : * different link partner.
4225 : */
4226 0 : ret_val = em_config_fc_after_link_up(hw);
4227 0 : if (ret_val) {
4228 : DEBUGOUT("Error configuring flow control\n");
4229 0 : return ret_val;
4230 : }
4231 : /*
4232 : * At this point we know that we are on copper and we have
4233 : * auto-negotiated link. These are conditions for checking
4234 : * the link partner capability register. We use the link
4235 : * speed to determine if TBI compatibility needs to be turned
4236 : * on or off. If the link is not at gigabit speed, then TBI
4237 : * compatibility is not needed. If we are at gigabit speed,
4238 : * we turn on TBI compatibility.
4239 : */
4240 0 : if (hw->tbi_compatibility_en) {
4241 0 : uint16_t speed, duplex;
4242 0 : ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4243 0 : if (ret_val) {
4244 : DEBUGOUT("Error getting link speed and duplex"
4245 : "\n");
4246 0 : return ret_val;
4247 : }
4248 0 : if (speed != SPEED_1000) {
4249 : /*
4250 : * If link speed is not set to gigabit speed,
4251 : * we do not need to enable TBI
4252 : * compatibility.
4253 : */
4254 0 : if (hw->tbi_compatibility_on) {
4255 : /*
4256 : * If we previously were in the mode,
4257 : * turn it off.
4258 : */
4259 0 : rctl = E1000_READ_REG(hw, RCTL);
4260 0 : rctl &= ~E1000_RCTL_SBP;
4261 0 : E1000_WRITE_REG(hw, RCTL, rctl);
4262 0 : hw->tbi_compatibility_on = FALSE;
4263 0 : }
4264 : } else {
4265 : /*
4266 : * If TBI compatibility is was previously
4267 : * off, turn it on. For compatibility with a
4268 : * TBI link partner, we will store bad
4269 : * packets. Some frames have an additional
4270 : * byte on the end and will look like CRC
4271 : * errors to to the hardware.
4272 : */
4273 0 : if (!hw->tbi_compatibility_on) {
4274 0 : hw->tbi_compatibility_on = TRUE;
4275 0 : rctl = E1000_READ_REG(hw, RCTL);
4276 0 : rctl |= E1000_RCTL_SBP;
4277 0 : E1000_WRITE_REG(hw, RCTL, rctl);
4278 0 : }
4279 : }
4280 0 : }
4281 : }
4282 : /*
4283 : * If we don't have link (auto-negotiation failed or link partner
4284 : * cannot auto-negotiate), the cable is plugged in (we have signal),
4285 : * and our link partner is not trying to auto-negotiate with us (we
4286 : * are receiving idles or data), we need to force link up. We also
4287 : * need to give auto-negotiation time to complete, in case the cable
4288 : * was just plugged in. The autoneg_failed flag does this.
4289 : */
4290 0 : else if ((((hw->media_type == em_media_type_fiber) &&
4291 0 : ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
4292 0 : (hw->media_type == em_media_type_internal_serdes)) &&
4293 0 : (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
4294 0 : if (hw->autoneg_failed == 0) {
4295 0 : hw->autoneg_failed = 1;
4296 0 : return 0;
4297 : }
4298 : DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
4299 :
4300 : /* Disable auto-negotiation in the TXCW register */
4301 0 : E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
4302 :
4303 : /* Force link-up and also force full-duplex. */
4304 0 : ctrl = E1000_READ_REG(hw, CTRL);
4305 0 : ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
4306 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
4307 :
4308 : /* Configure Flow Control after forcing link up. */
4309 0 : ret_val = em_config_fc_after_link_up(hw);
4310 0 : if (ret_val) {
4311 : DEBUGOUT("Error configuring flow control\n");
4312 0 : return ret_val;
4313 : }
4314 : }
4315 : /*
4316 : * If we are forcing link and we are receiving /C/ ordered sets,
4317 : * re-enable auto-negotiation in the TXCW register and disable forced
4318 : * link in the Device Control register in an attempt to
4319 : * auto-negotiate with our link partner.
4320 : */
4321 0 : else if (((hw->media_type == em_media_type_fiber) ||
4322 0 : (hw->media_type == em_media_type_internal_serdes)) &&
4323 0 : (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4324 : DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
4325 0 : E1000_WRITE_REG(hw, TXCW, hw->txcw);
4326 0 : E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4327 :
4328 0 : hw->serdes_link_down = FALSE;
4329 0 : }
4330 : /*
4331 : * If we force link for non-auto-negotiation switch, check link
4332 : * status based on MAC synchronization for internal serdes media
4333 : * type.
4334 : */
4335 0 : else if ((hw->media_type == em_media_type_internal_serdes) &&
4336 0 : !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
4337 : /* SYNCH bit and IV bit are sticky. */
4338 0 : usec_delay(10);
4339 0 : if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
4340 0 : if (!(rxcw & E1000_RXCW_IV)) {
4341 0 : hw->serdes_link_down = FALSE;
4342 : DEBUGOUT("SERDES: Link is up.\n");
4343 0 : }
4344 : } else {
4345 0 : hw->serdes_link_down = TRUE;
4346 : DEBUGOUT("SERDES: Link is down.\n");
4347 : }
4348 : }
4349 0 : if ((hw->media_type == em_media_type_internal_serdes) &&
4350 0 : (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
4351 0 : hw->serdes_link_down = !(E1000_STATUS_LU &
4352 0 : E1000_READ_REG(hw, STATUS));
4353 0 : }
4354 0 : return E1000_SUCCESS;
4355 0 : }
4356 :
4357 : int32_t
4358 0 : em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed,
4359 : uint16_t *duplex)
4360 : {
4361 : uint32_t pcs;
4362 :
4363 0 : hw->serdes_link_down = TRUE;
4364 0 : *speed = 0;
4365 0 : *duplex = 0;
4366 :
4367 : /*
4368 : * Read the PCS Status register for link state. For non-copper mode,
4369 : * the status register is not accurate. The PCS status register is
4370 : * used instead.
4371 : */
4372 0 : pcs = E1000_READ_REG(hw, PCS_LSTAT);
4373 :
4374 : /*
4375 : * The link up bit determines when link is up on autoneg. The sync ok
4376 : * gets set once both sides sync up and agree upon link. Stable link
4377 : * can be determined by checking for both link up and link sync ok
4378 : */
4379 0 : if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
4380 0 : hw->serdes_link_down = FALSE;
4381 :
4382 : /* Detect and store PCS speed */
4383 0 : if (pcs & E1000_PCS_LSTS_SPEED_1000) {
4384 0 : *speed = SPEED_1000;
4385 0 : } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
4386 0 : *speed = SPEED_100;
4387 0 : } else {
4388 0 : *speed = SPEED_10;
4389 : }
4390 :
4391 : /* Detect and store PCS duplex */
4392 0 : if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
4393 0 : *duplex = FULL_DUPLEX;
4394 0 : } else {
4395 0 : *duplex = HALF_DUPLEX;
4396 : }
4397 : }
4398 :
4399 0 : return (0);
4400 : }
4401 :
4402 :
4403 : /******************************************************************************
4404 : * Detects the current speed and duplex settings of the hardware.
4405 : *
4406 : * hw - Struct containing variables accessed by shared code
4407 : * speed - Speed of the connection
4408 : * duplex - Duplex setting of the connection
4409 : *****************************************************************************/
4410 : int32_t
4411 0 : em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex)
4412 : {
4413 : uint32_t status;
4414 : int32_t ret_val;
4415 0 : uint16_t phy_data;
4416 : DEBUGFUNC("em_get_speed_and_duplex");
4417 :
4418 0 : if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper)
4419 0 : return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex);
4420 :
4421 0 : if (hw->mac_type >= em_82543) {
4422 0 : status = E1000_READ_REG(hw, STATUS);
4423 0 : if (status & E1000_STATUS_SPEED_1000) {
4424 0 : *speed = SPEED_1000;
4425 : DEBUGOUT("1000 Mbs, ");
4426 0 : } else if (status & E1000_STATUS_SPEED_100) {
4427 0 : *speed = SPEED_100;
4428 : DEBUGOUT("100 Mbs, ");
4429 0 : } else {
4430 0 : *speed = SPEED_10;
4431 : DEBUGOUT("10 Mbs, ");
4432 : }
4433 :
4434 0 : if (status & E1000_STATUS_FD) {
4435 0 : *duplex = FULL_DUPLEX;
4436 : DEBUGOUT("Full Duplex\n");
4437 0 : } else {
4438 0 : *duplex = HALF_DUPLEX;
4439 : DEBUGOUT(" Half Duplex\n");
4440 : }
4441 : } else {
4442 : DEBUGOUT("1000 Mbs, Full Duplex\n");
4443 0 : *speed = SPEED_1000;
4444 0 : *duplex = FULL_DUPLEX;
4445 : }
4446 : /*
4447 : * IGP01 PHY may advertise full duplex operation after speed
4448 : * downgrade even if it is operating at half duplex. Here we set the
4449 : * duplex settings to match the duplex in the link partner's
4450 : * capabilities.
4451 : */
4452 0 : if (hw->phy_type == em_phy_igp && hw->speed_downgraded) {
4453 0 : ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4454 0 : if (ret_val)
4455 0 : return ret_val;
4456 :
4457 0 : if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4458 0 : *duplex = HALF_DUPLEX;
4459 : else {
4460 0 : ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
4461 : &phy_data);
4462 0 : if (ret_val)
4463 0 : return ret_val;
4464 0 : if ((*speed == SPEED_100 &&
4465 0 : !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
4466 0 : (*speed == SPEED_10 &&
4467 0 : !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4468 0 : *duplex = HALF_DUPLEX;
4469 : }
4470 : }
4471 0 : if ((hw->mac_type == em_80003es2lan) &&
4472 0 : (hw->media_type == em_media_type_copper)) {
4473 0 : if (*speed == SPEED_1000)
4474 0 : ret_val = em_configure_kmrn_for_1000(hw);
4475 : else
4476 0 : ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
4477 0 : if (ret_val)
4478 0 : return ret_val;
4479 : }
4480 0 : if ((hw->mac_type == em_ich8lan) &&
4481 0 : (hw->phy_type == em_phy_igp_3) &&
4482 0 : (*speed == SPEED_1000)) {
4483 0 : ret_val = em_kumeran_lock_loss_workaround(hw);
4484 0 : if (ret_val)
4485 0 : return ret_val;
4486 : }
4487 0 : return E1000_SUCCESS;
4488 0 : }
4489 :
4490 : /******************************************************************************
4491 : * Blocks until autoneg completes or times out (~4.5 seconds)
4492 : *
4493 : * hw - Struct containing variables accessed by shared code
4494 : *****************************************************************************/
4495 : STATIC int32_t
4496 0 : em_wait_autoneg(struct em_hw *hw)
4497 : {
4498 : int32_t ret_val;
4499 : uint16_t i;
4500 0 : uint16_t phy_data;
4501 : DEBUGFUNC("em_wait_autoneg");
4502 : DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4503 :
4504 : /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4505 0 : for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
4506 : /*
4507 : * Read the MII Status Register and wait for Auto-Neg
4508 : * Complete bit to be set.
4509 : */
4510 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4511 0 : if (ret_val)
4512 0 : return ret_val;
4513 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4514 0 : if (ret_val)
4515 0 : return ret_val;
4516 0 : if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4517 0 : return E1000_SUCCESS;
4518 : }
4519 0 : msec_delay(100);
4520 : }
4521 0 : return E1000_SUCCESS;
4522 0 : }
4523 :
4524 : /******************************************************************************
4525 : * Raises the Management Data Clock
4526 : *
4527 : * hw - Struct containing variables accessed by shared code
4528 : * ctrl - Device control register's current value
4529 : *****************************************************************************/
4530 : static void
4531 0 : em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4532 : {
4533 : /*
4534 : * Raise the clock input to the Management Data Clock (by setting the
4535 : * MDC bit), and then delay 10 microseconds.
4536 : */
4537 0 : E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4538 0 : E1000_WRITE_FLUSH(hw);
4539 0 : usec_delay(10);
4540 0 : }
4541 :
4542 : /******************************************************************************
4543 : * Lowers the Management Data Clock
4544 : *
4545 : * hw - Struct containing variables accessed by shared code
4546 : * ctrl - Device control register's current value
4547 : *****************************************************************************/
4548 : static void
4549 0 : em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4550 : {
4551 : /*
4552 : * Lower the clock input to the Management Data Clock (by clearing
4553 : * the MDC bit), and then delay 10 microseconds.
4554 : */
4555 0 : E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4556 0 : E1000_WRITE_FLUSH(hw);
4557 0 : usec_delay(10);
4558 0 : }
4559 :
4560 : /******************************************************************************
4561 : * Shifts data bits out to the PHY
4562 : *
4563 : * hw - Struct containing variables accessed by shared code
4564 : * data - Data to send out to the PHY
4565 : * count - Number of bits to shift out
4566 : *
4567 : * Bits are shifted out in MSB to LSB order.
4568 : *****************************************************************************/
4569 : static void
4570 0 : em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count)
4571 : {
4572 0 : uint32_t ctrl;
4573 : uint32_t mask;
4574 : /*
4575 : * We need to shift "count" number of bits out to the PHY. So, the
4576 : * value in the "data" parameter will be shifted out to the PHY one
4577 : * bit at a time. In order to do this, "data" must be broken down
4578 : * into bits.
4579 : */
4580 : mask = 0x01;
4581 0 : mask <<= (count - 1);
4582 :
4583 0 : ctrl = E1000_READ_REG(hw, CTRL);
4584 :
4585 : /* Set MDIO_DIR and MDC_DIR direction bits to be used as output
4586 : * pins.
4587 : */
4588 0 : ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4589 :
4590 0 : while (mask) {
4591 : /*
4592 : * A "1" is shifted out to the PHY by setting the MDIO bit to
4593 : * "1" and then raising and lowering the Management Data
4594 : * Clock. A "0" is shifted out to the PHY by setting the MDIO
4595 : * bit to "0" and then raising and lowering the clock.
4596 : */
4597 0 : if (data & mask)
4598 0 : ctrl |= E1000_CTRL_MDIO;
4599 : else
4600 0 : ctrl &= ~E1000_CTRL_MDIO;
4601 :
4602 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
4603 0 : E1000_WRITE_FLUSH(hw);
4604 :
4605 0 : usec_delay(10);
4606 :
4607 0 : em_raise_mdi_clk(hw, &ctrl);
4608 0 : em_lower_mdi_clk(hw, &ctrl);
4609 :
4610 0 : mask = mask >> 1;
4611 : }
4612 0 : }
4613 :
4614 : /******************************************************************************
4615 : * Shifts data bits in from the PHY
4616 : *
4617 : * hw - Struct containing variables accessed by shared code
4618 : *
4619 : * Bits are shifted in in MSB to LSB order.
4620 : *****************************************************************************/
4621 : static uint16_t
4622 0 : em_shift_in_mdi_bits(struct em_hw *hw)
4623 : {
4624 0 : uint32_t ctrl;
4625 : uint16_t data = 0;
4626 : uint8_t i;
4627 : /*
4628 : * In order to read a register from the PHY, we need to shift in a
4629 : * total of 18 bits from the PHY. The first two bit (turnaround)
4630 : * times are used to avoid contention on the MDIO pin when a read
4631 : * operation is performed. These two bits are ignored by us and
4632 : * thrown away. Bits are "shifted in" by raising the input to the
4633 : * Management Data Clock (setting the MDC bit), and then reading the
4634 : * value of the MDIO bit.
4635 : */
4636 0 : ctrl = E1000_READ_REG(hw, CTRL);
4637 : /*
4638 : * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
4639 : * input.
4640 : */
4641 0 : ctrl &= ~E1000_CTRL_MDIO_DIR;
4642 0 : ctrl &= ~E1000_CTRL_MDIO;
4643 :
4644 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
4645 0 : E1000_WRITE_FLUSH(hw);
4646 : /*
4647 : * Raise and Lower the clock before reading in the data. This
4648 : * accounts for the turnaround bits. The first clock occurred when we
4649 : * clocked out the last bit of the Register Address.
4650 : */
4651 0 : em_raise_mdi_clk(hw, &ctrl);
4652 0 : em_lower_mdi_clk(hw, &ctrl);
4653 :
4654 0 : for (data = 0, i = 0; i < 16; i++) {
4655 0 : data = data << 1;
4656 0 : em_raise_mdi_clk(hw, &ctrl);
4657 0 : ctrl = E1000_READ_REG(hw, CTRL);
4658 : /* Check to see if we shifted in a "1". */
4659 0 : if (ctrl & E1000_CTRL_MDIO)
4660 0 : data |= 1;
4661 0 : em_lower_mdi_clk(hw, &ctrl);
4662 : }
4663 :
4664 0 : em_raise_mdi_clk(hw, &ctrl);
4665 0 : em_lower_mdi_clk(hw, &ctrl);
4666 :
4667 0 : return data;
4668 0 : }
4669 :
4670 : STATIC int32_t
4671 0 : em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)
4672 : {
4673 : uint32_t swfw_sync = 0;
4674 0 : uint32_t swmask = mask;
4675 0 : uint32_t fwmask = mask << 16;
4676 : int32_t timeout = 200;
4677 : DEBUGFUNC("em_swfw_sync_acquire");
4678 :
4679 0 : if (hw->swfwhw_semaphore_present)
4680 0 : return em_get_software_flag(hw);
4681 :
4682 0 : if (!hw->swfw_sync_present)
4683 0 : return em_get_hw_eeprom_semaphore(hw);
4684 :
4685 0 : while (timeout) {
4686 0 : if (em_get_hw_eeprom_semaphore(hw))
4687 0 : return -E1000_ERR_SWFW_SYNC;
4688 :
4689 0 : swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
4690 0 : if (!(swfw_sync & (fwmask | swmask))) {
4691 : break;
4692 : }
4693 : /*
4694 : * firmware currently using resource (fwmask)
4695 : * or other software thread currently using resource (swmask)
4696 : */
4697 0 : em_put_hw_eeprom_semaphore(hw);
4698 0 : msec_delay_irq(5);
4699 0 : timeout--;
4700 : }
4701 :
4702 0 : if (!timeout) {
4703 : DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout."
4704 : "\n");
4705 0 : return -E1000_ERR_SWFW_SYNC;
4706 : }
4707 0 : swfw_sync |= swmask;
4708 0 : E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
4709 :
4710 0 : em_put_hw_eeprom_semaphore(hw);
4711 0 : return E1000_SUCCESS;
4712 0 : }
4713 :
4714 : STATIC void
4715 0 : em_swfw_sync_release(struct em_hw *hw, uint16_t mask)
4716 : {
4717 : uint32_t swfw_sync;
4718 0 : uint32_t swmask = mask;
4719 : DEBUGFUNC("em_swfw_sync_release");
4720 :
4721 0 : if (hw->swfwhw_semaphore_present) {
4722 0 : em_release_software_flag(hw);
4723 0 : return;
4724 : }
4725 0 : if (!hw->swfw_sync_present) {
4726 0 : em_put_hw_eeprom_semaphore(hw);
4727 0 : return;
4728 : }
4729 : /*
4730 : * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC;
4731 : */
4732 0 : while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
4733 : /* empty */
4734 :
4735 0 : swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
4736 0 : swfw_sync &= ~swmask;
4737 0 : E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
4738 :
4739 0 : em_put_hw_eeprom_semaphore(hw);
4740 0 : }
4741 :
4742 : /****************************************************************************
4743 : * Read BM PHY wakeup register. It works as such:
4744 : * 1) Set page 769, register 17, bit 2 = 1
4745 : * 2) Set page to 800 for host (801 if we were manageability)
4746 : * 3) Write the address using the address opcode (0x11)
4747 : * 4) Read or write the data using the data opcode (0x12)
4748 : * 5) Restore 769_17.2 to its original value
4749 : ****************************************************************************/
4750 : int32_t
4751 0 : em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr,
4752 : uint16_t *phy_data, boolean_t read)
4753 : {
4754 : int32_t ret_val;
4755 0 : uint16_t reg = BM_PHY_REG_NUM(reg_addr);
4756 0 : uint16_t phy_reg = 0;
4757 :
4758 : /* All operations in this function are phy address 1 */
4759 0 : hw->phy_addr = 1;
4760 :
4761 : /* Set page 769 */
4762 0 : em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
4763 : (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT));
4764 :
4765 0 : ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg);
4766 0 : if (ret_val)
4767 : goto out;
4768 :
4769 : /* First clear bit 4 to avoid a power state change */
4770 0 : phy_reg &= ~(BM_WUC_HOST_WU_BIT);
4771 0 : ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg);
4772 0 : if (ret_val)
4773 : goto out;
4774 :
4775 : /* Write bit 2 = 1, and clear bit 4 to 769_17 */
4776 0 : ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG,
4777 0 : phy_reg | BM_WUC_ENABLE_BIT);
4778 0 : if (ret_val)
4779 : goto out;
4780 :
4781 : /* Select page 800 */
4782 0 : ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
4783 : (BM_WUC_PAGE << PHY_PAGE_SHIFT));
4784 :
4785 : /* Write the page 800 offset value using opcode 0x11 */
4786 0 : ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg);
4787 0 : if (ret_val)
4788 : goto out;
4789 :
4790 0 : if (read)
4791 : /* Read the page 800 value using opcode 0x12 */
4792 0 : ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE,
4793 : phy_data);
4794 : else
4795 : /* Write the page 800 value using opcode 0x12 */
4796 0 : ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE,
4797 0 : *phy_data);
4798 :
4799 0 : if (ret_val)
4800 : goto out;
4801 :
4802 : /*
4803 : * Restore 769_17.2 to its original value
4804 : * Set page 769
4805 : */
4806 0 : em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
4807 : (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT));
4808 :
4809 : /* Clear 769_17.2 */
4810 0 : ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg);
4811 : if (ret_val)
4812 0 : goto out;
4813 :
4814 : out:
4815 0 : return ret_val;
4816 0 : }
4817 :
4818 : /***************************************************************************
4819 : * Read HV PHY vendor specific high registers
4820 : ***************************************************************************/
4821 : int32_t
4822 0 : em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr,
4823 : uint16_t *phy_data, boolean_t read)
4824 : {
4825 : int32_t ret_val;
4826 : uint32_t addr_reg = 0;
4827 : uint32_t data_reg = 0;
4828 :
4829 : /* This takes care of the difference with desktop vs mobile phy */
4830 0 : addr_reg = (hw->phy_type == em_phy_82578) ?
4831 : I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG;
4832 0 : data_reg = addr_reg + 1;
4833 :
4834 : /* All operations in this function are phy address 2 */
4835 0 : hw->phy_addr = 2;
4836 :
4837 : /* masking with 0x3F to remove the page from offset */
4838 0 : ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F);
4839 0 : if (ret_val) {
4840 0 : printf("Could not write PHY the HV address register\n");
4841 0 : goto out;
4842 : }
4843 :
4844 : /* Read or write the data value next */
4845 0 : if (read)
4846 0 : ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data);
4847 : else
4848 0 : ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data);
4849 :
4850 0 : if (ret_val) {
4851 0 : printf("Could not read data value from HV data register\n");
4852 0 : goto out;
4853 : }
4854 :
4855 : out:
4856 0 : return ret_val;
4857 : }
4858 :
4859 : /******************************************************************************
4860 : * Reads or writes the value from a PHY register, if the value is on a specific
4861 : * non zero page, sets the page first.
4862 : * hw - Struct containing variables accessed by shared code
4863 : * reg_addr - address of the PHY register to read
4864 : *****************************************************************************/
4865 : int32_t
4866 0 : em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data,
4867 : boolean_t read)
4868 : {
4869 : uint32_t ret_val;
4870 : uint16_t swfw;
4871 0 : uint16_t page = BM_PHY_REG_PAGE(reg_addr);
4872 0 : uint16_t reg = BM_PHY_REG_NUM(reg_addr);
4873 :
4874 : DEBUGFUNC("em_access_phy_reg_hv");
4875 :
4876 : swfw = E1000_SWFW_PHY0_SM;
4877 :
4878 0 : if (em_swfw_sync_acquire(hw, swfw))
4879 0 : return -E1000_ERR_SWFW_SYNC;
4880 :
4881 0 : if (page == BM_WUC_PAGE) {
4882 0 : ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr,
4883 : phy_data, read);
4884 0 : goto release;
4885 : }
4886 :
4887 0 : if (page >= HV_INTC_FC_PAGE_START)
4888 0 : hw->phy_addr = 1;
4889 : else
4890 0 : hw->phy_addr = 2;
4891 :
4892 0 : if (page == HV_INTC_FC_PAGE_START)
4893 0 : page = 0;
4894 :
4895 : /*
4896 : * Workaround MDIO accesses being disabled after entering IEEE Power
4897 : * Down (whenever bit 11 of the PHY Control register is set)
4898 : */
4899 0 : if (!read &&
4900 0 : (hw->phy_type == em_phy_82578) &&
4901 0 : (hw->phy_revision >= 1) &&
4902 0 : (hw->phy_addr == 2) &&
4903 0 : ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
4904 0 : (*phy_data & (1 << 11))) {
4905 0 : uint16_t data2 = 0x7EFF;
4906 :
4907 0 : ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
4908 : &data2, FALSE);
4909 0 : if (ret_val)
4910 0 : return ret_val;
4911 0 : }
4912 :
4913 0 : if (reg_addr > MAX_PHY_MULTI_PAGE_REG) {
4914 0 : ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
4915 0 : (page << PHY_PAGE_SHIFT));
4916 0 : if (ret_val)
4917 0 : return ret_val;
4918 : }
4919 0 : if (read)
4920 0 : ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg,
4921 : phy_data);
4922 : else
4923 0 : ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg,
4924 0 : *phy_data);
4925 : release:
4926 0 : em_swfw_sync_release(hw, swfw);
4927 0 : return ret_val;
4928 0 : }
4929 :
4930 : /******************************************************************************
4931 : * Reads the value from a PHY register, if the value is on a specific non zero
4932 : * page, sets the page first.
4933 : * hw - Struct containing variables accessed by shared code
4934 : * reg_addr - address of the PHY register to read
4935 : *****************************************************************************/
4936 : int32_t
4937 0 : em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
4938 : {
4939 : uint32_t ret_val;
4940 : uint16_t swfw;
4941 : DEBUGFUNC("em_read_phy_reg");
4942 :
4943 0 : if (hw->mac_type == em_pchlan ||
4944 0 : hw->mac_type == em_pch2lan ||
4945 0 : hw->mac_type == em_pch_lpt ||
4946 0 : hw->mac_type == em_pch_spt ||
4947 0 : hw->mac_type == em_pch_cnp)
4948 0 : return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE));
4949 :
4950 0 : if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) &&
4951 0 : (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
4952 : swfw = E1000_SWFW_PHY1_SM;
4953 0 : } else {
4954 : swfw = E1000_SWFW_PHY0_SM;
4955 : }
4956 0 : if (em_swfw_sync_acquire(hw, swfw))
4957 0 : return -E1000_ERR_SWFW_SYNC;
4958 :
4959 0 : if ((hw->phy_type == em_phy_igp ||
4960 0 : hw->phy_type == em_phy_igp_3 ||
4961 0 : hw->phy_type == em_phy_igp_2) &&
4962 0 : (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
4963 0 : ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
4964 0 : (uint16_t) reg_addr);
4965 0 : if (ret_val) {
4966 0 : em_swfw_sync_release(hw, swfw);
4967 0 : return ret_val;
4968 : }
4969 0 : } else if (hw->phy_type == em_phy_gg82563) {
4970 0 : if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
4971 0 : (hw->mac_type == em_80003es2lan)) {
4972 : /* Select Configuration Page */
4973 0 : if ((reg_addr & MAX_PHY_REG_ADDRESS) <
4974 : GG82563_MIN_ALT_REG) {
4975 0 : ret_val = em_write_phy_reg_ex(hw,
4976 : GG82563_PHY_PAGE_SELECT,
4977 : (uint16_t) ((uint16_t) reg_addr >>
4978 : GG82563_PAGE_SHIFT));
4979 0 : } else {
4980 : /*
4981 : * Use Alternative Page Select register to
4982 : * access registers 30 and 31
4983 : */
4984 0 : ret_val = em_write_phy_reg_ex(hw,
4985 : GG82563_PHY_PAGE_SELECT_ALT,
4986 : (uint16_t) ((uint16_t) reg_addr >>
4987 : GG82563_PAGE_SHIFT));
4988 : }
4989 :
4990 0 : if (ret_val) {
4991 0 : em_swfw_sync_release(hw, swfw);
4992 0 : return ret_val;
4993 : }
4994 : }
4995 0 : } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
4996 0 : if (reg_addr > MAX_PHY_MULTI_PAGE_REG) {
4997 0 : ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT,
4998 0 : (uint16_t) ((uint16_t) reg_addr >>
4999 : PHY_PAGE_SHIFT));
5000 0 : if (ret_val)
5001 0 : return ret_val;
5002 : }
5003 : }
5004 0 : ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
5005 : phy_data);
5006 :
5007 0 : em_swfw_sync_release(hw, swfw);
5008 0 : return ret_val;
5009 0 : }
5010 :
5011 : STATIC int32_t
5012 0 : em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5013 : {
5014 : uint32_t i;
5015 : uint32_t mdic = 0;
5016 : DEBUGFUNC("em_read_phy_reg_ex");
5017 :
5018 0 : if (reg_addr > MAX_PHY_REG_ADDRESS) {
5019 : DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5020 0 : return -E1000_ERR_PARAM;
5021 : }
5022 0 : if (hw->mac_type == em_icp_xxxx) {
5023 0 : *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num,
5024 : reg_addr);
5025 0 : return E1000_SUCCESS;
5026 : }
5027 0 : if (hw->mac_type > em_82543) {
5028 : /*
5029 : * Set up Op-code, Phy Address, and register address in the
5030 : * MDI Control register. The MAC will take care of
5031 : * interfacing with the PHY to retrieve the desired data.
5032 : */
5033 0 : mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
5034 0 : (hw->phy_addr << E1000_MDIC_PHY_SHIFT) |
5035 : (E1000_MDIC_OP_READ));
5036 :
5037 0 : E1000_WRITE_REG(hw, MDIC, mdic);
5038 :
5039 : /*
5040 : * Poll the ready bit to see if the MDI read completed
5041 : * Increasing the time out as testing showed failures with
5042 : * the lower time out (from FreeBSD driver)
5043 : */
5044 0 : for (i = 0; i < 1960; i++) {
5045 0 : usec_delay(50);
5046 0 : mdic = E1000_READ_REG(hw, MDIC);
5047 0 : if (mdic & E1000_MDIC_READY)
5048 : break;
5049 : }
5050 0 : if (!(mdic & E1000_MDIC_READY)) {
5051 : DEBUGOUT("MDI Read did not complete\n");
5052 0 : return -E1000_ERR_PHY;
5053 : }
5054 0 : if (mdic & E1000_MDIC_ERROR) {
5055 : DEBUGOUT("MDI Error\n");
5056 0 : return -E1000_ERR_PHY;
5057 : }
5058 0 : *phy_data = (uint16_t) mdic;
5059 :
5060 0 : if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
5061 0 : hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp)
5062 0 : usec_delay(100);
5063 : } else {
5064 : /*
5065 : * We must first send a preamble through the MDIO pin to
5066 : * signal the beginning of an MII instruction. This is done
5067 : * by sending 32 consecutive "1" bits.
5068 : */
5069 0 : em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
5070 : /*
5071 : * Now combine the next few fields that are required for a
5072 : * read operation. We use this method instead of calling the
5073 : * em_shift_out_mdi_bits routine five different times. The
5074 : * format of a MII read instruction consists of a shift out
5075 : * of 14 bits and is defined as follows: <Preamble><SOF><Op
5076 : * Code><Phy Addr><Reg Addr> followed by a shift in of 18
5077 : * bits. This first two bits shifted in are TurnAround bits
5078 : * used to avoid contention on the MDIO pin when a READ
5079 : * operation is performed. These two bits are thrown away
5080 : * followed by a shift in of 16 bits which contains the
5081 : * desired data.
5082 : */
5083 0 : mdic = ((reg_addr) | (hw->phy_addr << 5) |
5084 0 : (PHY_OP_READ << 10) | (PHY_SOF << 12));
5085 :
5086 0 : em_shift_out_mdi_bits(hw, mdic, 14);
5087 : /*
5088 : * Now that we've shifted out the read command to the MII, we
5089 : * need to "shift in" the 16-bit value (18 total bits) of the
5090 : * requested PHY register address.
5091 : */
5092 0 : *phy_data = em_shift_in_mdi_bits(hw);
5093 : }
5094 0 : return E1000_SUCCESS;
5095 0 : }
5096 :
5097 : /******************************************************************************
5098 : * Writes a value to a PHY register
5099 : *
5100 : * hw - Struct containing variables accessed by shared code
5101 : * reg_addr - address of the PHY register to write
5102 : * data - data to write to the PHY
5103 : *****************************************************************************/
5104 : int32_t
5105 0 : em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5106 : {
5107 : uint32_t ret_val;
5108 : DEBUGFUNC("em_write_phy_reg");
5109 :
5110 0 : if (hw->mac_type == em_pchlan ||
5111 0 : hw->mac_type == em_pch2lan ||
5112 0 : hw->mac_type == em_pch_lpt ||
5113 0 : hw->mac_type == em_pch_spt ||
5114 0 : hw->mac_type == em_pch_cnp)
5115 0 : return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE));
5116 :
5117 0 : if (em_swfw_sync_acquire(hw, hw->swfw))
5118 0 : return -E1000_ERR_SWFW_SYNC;
5119 :
5120 0 : if ((hw->phy_type == em_phy_igp ||
5121 0 : hw->phy_type == em_phy_igp_3 ||
5122 0 : hw->phy_type == em_phy_igp_2) &&
5123 0 : (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
5124 0 : ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
5125 0 : (uint16_t) reg_addr);
5126 0 : if (ret_val) {
5127 0 : em_swfw_sync_release(hw, hw->swfw);
5128 0 : return ret_val;
5129 : }
5130 0 : } else if (hw->phy_type == em_phy_gg82563) {
5131 0 : if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
5132 0 : (hw->mac_type == em_80003es2lan)) {
5133 : /* Select Configuration Page */
5134 0 : if ((reg_addr & MAX_PHY_REG_ADDRESS) <
5135 : GG82563_MIN_ALT_REG) {
5136 0 : ret_val = em_write_phy_reg_ex(hw,
5137 : GG82563_PHY_PAGE_SELECT,
5138 : (uint16_t) ((uint16_t) reg_addr >>
5139 : GG82563_PAGE_SHIFT));
5140 0 : } else {
5141 : /*
5142 : * Use Alternative Page Select register to
5143 : * access registers 30 and 31
5144 : */
5145 0 : ret_val = em_write_phy_reg_ex(hw,
5146 : GG82563_PHY_PAGE_SELECT_ALT,
5147 : (uint16_t) ((uint16_t) reg_addr >>
5148 : GG82563_PAGE_SHIFT));
5149 : }
5150 :
5151 0 : if (ret_val) {
5152 0 : em_swfw_sync_release(hw, hw->swfw);
5153 0 : return ret_val;
5154 : }
5155 : }
5156 0 : } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
5157 0 : if (reg_addr > MAX_PHY_MULTI_PAGE_REG) {
5158 0 : ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT,
5159 0 : (uint16_t) ((uint16_t) reg_addr >>
5160 : PHY_PAGE_SHIFT));
5161 0 : if (ret_val)
5162 0 : return ret_val;
5163 : }
5164 : }
5165 0 : ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
5166 0 : phy_data);
5167 :
5168 0 : em_swfw_sync_release(hw, hw->swfw);
5169 0 : return ret_val;
5170 0 : }
5171 :
5172 : STATIC int32_t
5173 0 : em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5174 : {
5175 : uint32_t i;
5176 : uint32_t mdic = 0;
5177 : DEBUGFUNC("em_write_phy_reg_ex");
5178 :
5179 0 : if (reg_addr > MAX_PHY_REG_ADDRESS) {
5180 : DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5181 0 : return -E1000_ERR_PARAM;
5182 : }
5183 0 : if (hw->mac_type == em_icp_xxxx) {
5184 0 : gcu_miibus_writereg(hw, hw->icp_xxxx_port_num,
5185 0 : reg_addr, phy_data);
5186 0 : return E1000_SUCCESS;
5187 : }
5188 0 : if (hw->mac_type > em_82543) {
5189 : /*
5190 : * Set up Op-code, Phy Address, register address, and data
5191 : * intended for the PHY register in the MDI Control register.
5192 : * The MAC will take care of interfacing with the PHY to send
5193 : * the desired data.
5194 : */
5195 0 : mdic = (((uint32_t) phy_data) |
5196 0 : (reg_addr << E1000_MDIC_REG_SHIFT) |
5197 0 : (hw->phy_addr << E1000_MDIC_PHY_SHIFT) |
5198 : (E1000_MDIC_OP_WRITE));
5199 :
5200 0 : E1000_WRITE_REG(hw, MDIC, mdic);
5201 :
5202 : /* Poll the ready bit to see if the MDI read completed */
5203 0 : for (i = 0; i < 641; i++) {
5204 0 : usec_delay(5);
5205 0 : mdic = E1000_READ_REG(hw, MDIC);
5206 0 : if (mdic & E1000_MDIC_READY)
5207 : break;
5208 : }
5209 0 : if (!(mdic & E1000_MDIC_READY)) {
5210 : DEBUGOUT("MDI Write did not complete\n");
5211 0 : return -E1000_ERR_PHY;
5212 : }
5213 :
5214 0 : if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
5215 0 : hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp)
5216 0 : usec_delay(100);
5217 : } else {
5218 : /*
5219 : * We'll need to use the SW defined pins to shift the write
5220 : * command out to the PHY. We first send a preamble to the
5221 : * PHY to signal the beginning of the MII instruction. This
5222 : * is done by sending 32 consecutive "1" bits.
5223 : */
5224 0 : em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
5225 : /*
5226 : * Now combine the remaining required fields that will
5227 : * indicate a write operation. We use this method instead of
5228 : * calling the em_shift_out_mdi_bits routine for each field
5229 : * in the command. The format of a MII write instruction is
5230 : * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg
5231 : * Addr><Turnaround><Data>.
5232 : */
5233 0 : mdic = ((PHY_TURNAROUND) | (reg_addr << 2) |
5234 0 : (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) |
5235 : (PHY_SOF << 14));
5236 0 : mdic <<= 16;
5237 0 : mdic |= (uint32_t) phy_data;
5238 :
5239 0 : em_shift_out_mdi_bits(hw, mdic, 32);
5240 : }
5241 :
5242 0 : return E1000_SUCCESS;
5243 0 : }
5244 :
5245 : STATIC int32_t
5246 0 : em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data)
5247 : {
5248 : uint32_t reg_val;
5249 : DEBUGFUNC("em_read_kmrn_reg");
5250 :
5251 0 : if (em_swfw_sync_acquire(hw, hw->swfw))
5252 0 : return -E1000_ERR_SWFW_SYNC;
5253 :
5254 : /* Write register address */
5255 0 : reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
5256 0 : E1000_KUMCTRLSTA_OFFSET) |
5257 : E1000_KUMCTRLSTA_REN;
5258 :
5259 0 : E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
5260 0 : usec_delay(2);
5261 :
5262 : /* Read the data returned */
5263 0 : reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
5264 0 : *data = (uint16_t) reg_val;
5265 :
5266 0 : em_swfw_sync_release(hw, hw->swfw);
5267 0 : return E1000_SUCCESS;
5268 0 : }
5269 :
5270 : STATIC int32_t
5271 0 : em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data)
5272 : {
5273 : uint32_t reg_val;
5274 : DEBUGFUNC("em_write_kmrn_reg");
5275 :
5276 0 : if (em_swfw_sync_acquire(hw, hw->swfw))
5277 0 : return -E1000_ERR_SWFW_SYNC;
5278 :
5279 0 : reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
5280 0 : E1000_KUMCTRLSTA_OFFSET) | data;
5281 :
5282 0 : E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
5283 0 : usec_delay(2);
5284 :
5285 0 : em_swfw_sync_release(hw, hw->swfw);
5286 0 : return E1000_SUCCESS;
5287 0 : }
5288 :
5289 : /******************************************************************************
5290 : * Returns the PHY to the power-on reset state
5291 : *
5292 : * hw - Struct containing variables accessed by shared code
5293 : *****************************************************************************/
5294 : int32_t
5295 0 : em_phy_hw_reset(struct em_hw *hw)
5296 : {
5297 : uint32_t ctrl, ctrl_ext;
5298 : uint32_t led_ctrl;
5299 : int32_t ret_val;
5300 : DEBUGFUNC("em_phy_hw_reset");
5301 : /*
5302 : * In the case of the phy reset being blocked, it's not an error, we
5303 : * simply return success without performing the reset.
5304 : */
5305 0 : ret_val = em_check_phy_reset_block(hw);
5306 0 : if (ret_val)
5307 0 : return E1000_SUCCESS;
5308 :
5309 : DEBUGOUT("Resetting Phy...\n");
5310 :
5311 0 : if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) {
5312 0 : if (em_swfw_sync_acquire(hw, hw->swfw)) {
5313 : DEBUGOUT("Unable to acquire swfw sync\n");
5314 0 : return -E1000_ERR_SWFW_SYNC;
5315 : }
5316 : /*
5317 : * Read the device control register and assert the
5318 : * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For
5319 : * pre-em_82571 hardware, we delay for 10ms between the
5320 : * assert and deassert. For em_82571 hardware and later, we
5321 : * instead delay for 50us between and 10ms after the
5322 : * deassertion.
5323 : */
5324 0 : ctrl = E1000_READ_REG(hw, CTRL);
5325 0 : E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
5326 0 : E1000_WRITE_FLUSH(hw);
5327 :
5328 0 : if (hw->mac_type < em_82571)
5329 0 : msec_delay(10);
5330 : else
5331 0 : usec_delay(100);
5332 :
5333 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
5334 0 : E1000_WRITE_FLUSH(hw);
5335 :
5336 0 : if (hw->mac_type >= em_82571)
5337 0 : msec_delay_irq(10);
5338 0 : em_swfw_sync_release(hw, hw->swfw);
5339 : /*
5340 : * the M88E1141_E_PHY_ID might need reset here, but nothing
5341 : * proves it
5342 : */
5343 0 : } else {
5344 : /*
5345 : * Read the Extended Device Control Register, assert the
5346 : * PHY_RESET_DIR bit to put the PHY into reset. Then, take it
5347 : * out of reset.
5348 : */
5349 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5350 0 : ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
5351 0 : ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
5352 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5353 0 : E1000_WRITE_FLUSH(hw);
5354 0 : msec_delay(10);
5355 0 : ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
5356 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5357 0 : E1000_WRITE_FLUSH(hw);
5358 : }
5359 0 : usec_delay(150);
5360 :
5361 0 : if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
5362 : /* Configure activity LED after PHY reset */
5363 0 : led_ctrl = E1000_READ_REG(hw, LEDCTL);
5364 0 : led_ctrl &= IGP_ACTIVITY_LED_MASK;
5365 0 : led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
5366 0 : E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
5367 0 : }
5368 : /* Wait for FW to finish PHY configuration. */
5369 0 : ret_val = em_get_phy_cfg_done(hw);
5370 0 : if (ret_val != E1000_SUCCESS)
5371 0 : return ret_val;
5372 0 : em_release_software_semaphore(hw);
5373 :
5374 0 : if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3))
5375 0 : ret_val = em_init_lcd_from_nvm(hw);
5376 :
5377 0 : return ret_val;
5378 0 : }
5379 :
5380 : /*****************************************************************************
5381 : * SW-based LCD Configuration.
5382 : * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
5383 : * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
5384 : * in NVM determines whether HW should configure LPLU and Gbe Disable.
5385 : *****************************************************************************/
5386 : int32_t
5387 0 : em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state)
5388 : {
5389 : int32_t ret_val = E1000_SUCCESS;
5390 : uint32_t mac_reg;
5391 0 : uint16_t oem_reg;
5392 : uint16_t swfw = E1000_SWFW_PHY0_SM;
5393 :
5394 0 : if (hw->mac_type < em_pchlan)
5395 0 : return ret_val;
5396 :
5397 0 : ret_val = em_swfw_sync_acquire(hw, swfw);
5398 0 : if (ret_val)
5399 0 : return ret_val;
5400 :
5401 0 : if (hw->mac_type == em_pchlan) {
5402 0 : mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL);
5403 0 : if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
5404 : goto out;
5405 : }
5406 :
5407 0 : mac_reg = E1000_READ_REG(hw, FEXTNVM);
5408 0 : if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M))
5409 : goto out;
5410 :
5411 0 : mac_reg = E1000_READ_REG(hw, PHY_CTRL);
5412 :
5413 0 : ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg);
5414 0 : if (ret_val)
5415 : goto out;
5416 :
5417 0 : oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
5418 :
5419 0 : if (d0_state) {
5420 0 : if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
5421 0 : oem_reg |= HV_OEM_BITS_GBE_DIS;
5422 :
5423 0 : if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
5424 0 : oem_reg |= HV_OEM_BITS_LPLU;
5425 : /* Restart auto-neg to activate the bits */
5426 0 : if (!em_check_phy_reset_block(hw))
5427 0 : oem_reg |= HV_OEM_BITS_RESTART_AN;
5428 :
5429 : } else {
5430 0 : if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
5431 : E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
5432 0 : oem_reg |= HV_OEM_BITS_GBE_DIS;
5433 :
5434 0 : if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
5435 : E1000_PHY_CTRL_NOND0A_LPLU))
5436 0 : oem_reg |= HV_OEM_BITS_LPLU;
5437 : }
5438 :
5439 0 : ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg);
5440 :
5441 : out:
5442 0 : em_swfw_sync_release(hw, swfw);
5443 :
5444 0 : return ret_val;
5445 0 : }
5446 :
5447 :
5448 : /******************************************************************************
5449 : * Resets the PHY
5450 : *
5451 : * hw - Struct containing variables accessed by shared code
5452 : *
5453 : * Sets bit 15 of the MII Control regiser
5454 : *****************************************************************************/
5455 : int32_t
5456 0 : em_phy_reset(struct em_hw *hw)
5457 : {
5458 : int32_t ret_val;
5459 0 : uint16_t phy_data;
5460 : DEBUGFUNC("em_phy_reset");
5461 : /*
5462 : * In the case of the phy reset being blocked, it's not an error, we
5463 : * simply return success without performing the reset.
5464 : */
5465 0 : ret_val = em_check_phy_reset_block(hw);
5466 0 : if (ret_val)
5467 0 : return E1000_SUCCESS;
5468 :
5469 0 : switch (hw->phy_type) {
5470 : case em_phy_igp:
5471 : case em_phy_igp_2:
5472 : case em_phy_igp_3:
5473 : case em_phy_ife:
5474 0 : ret_val = em_phy_hw_reset(hw);
5475 0 : if (ret_val)
5476 0 : return ret_val;
5477 : break;
5478 : default:
5479 0 : ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
5480 0 : if (ret_val)
5481 0 : return ret_val;
5482 :
5483 0 : phy_data |= MII_CR_RESET;
5484 0 : ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
5485 0 : if (ret_val)
5486 0 : return ret_val;
5487 :
5488 0 : usec_delay(1);
5489 0 : break;
5490 : }
5491 :
5492 : /* Allow time for h/w to get to a quiescent state after reset */
5493 0 : msec_delay(10);
5494 :
5495 0 : if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2)
5496 0 : em_phy_init_script(hw);
5497 :
5498 0 : if (hw->mac_type == em_pchlan) {
5499 0 : ret_val = em_hv_phy_workarounds_ich8lan(hw);
5500 0 : if (ret_val)
5501 0 : return ret_val;
5502 0 : } else if (hw->mac_type == em_pch2lan) {
5503 0 : ret_val = em_lv_phy_workarounds_ich8lan(hw);
5504 0 : if (ret_val)
5505 0 : return ret_val;
5506 : }
5507 :
5508 0 : if (hw->mac_type >= em_pchlan) {
5509 0 : ret_val = em_oem_bits_config_pchlan(hw, TRUE);
5510 0 : if (ret_val)
5511 0 : return ret_val;
5512 : }
5513 :
5514 : /* Ungate automatic PHY configuration on non-managed 82579 */
5515 0 : if ((hw->mac_type == em_pch2lan) &&
5516 0 : !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
5517 0 : msec_delay(10);
5518 0 : em_gate_hw_phy_config_ich8lan(hw, FALSE);
5519 0 : }
5520 :
5521 0 : if (hw->phy_id == M88E1512_E_PHY_ID) {
5522 0 : ret_val = em_initialize_M88E1512_phy(hw);
5523 0 : if (ret_val)
5524 0 : return ret_val;
5525 : }
5526 :
5527 0 : return E1000_SUCCESS;
5528 0 : }
5529 :
5530 : /******************************************************************************
5531 : * Work-around for 82566 Kumeran PCS lock loss:
5532 : * On link status change (i.e. PCI reset, speed change) and link is up and
5533 : * speed is gigabit-
5534 : * 0) if workaround is optionally disabled do nothing
5535 : * 1) wait 1ms for Kumeran link to come up
5536 : * 2) check Kumeran Diagnostic register PCS lock loss bit
5537 : * 3) if not set the link is locked (all is good), otherwise...
5538 : * 4) reset the PHY
5539 : * 5) repeat up to 10 times
5540 : * Note: this is only called for IGP3 copper when speed is 1gb.
5541 : *
5542 : * hw - struct containing variables accessed by shared code
5543 : *****************************************************************************/
5544 : STATIC int32_t
5545 0 : em_kumeran_lock_loss_workaround(struct em_hw *hw)
5546 : {
5547 : int32_t ret_val;
5548 : int32_t reg;
5549 : int32_t cnt;
5550 0 : uint16_t phy_data;
5551 0 : if (hw->kmrn_lock_loss_workaround_disabled)
5552 0 : return E1000_SUCCESS;
5553 : /*
5554 : * Make sure link is up before proceeding. If not just return.
5555 : * Attempting this while link is negotiating fouled up link stability
5556 : */
5557 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
5558 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
5559 :
5560 0 : if (phy_data & MII_SR_LINK_STATUS) {
5561 0 : for (cnt = 0; cnt < 10; cnt++) {
5562 : /* read once to clear */
5563 0 : ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG,
5564 : &phy_data);
5565 0 : if (ret_val)
5566 0 : return ret_val;
5567 : /* and again to get new status */
5568 0 : ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
5569 0 : if (ret_val)
5570 0 : return ret_val;
5571 :
5572 : /* check for PCS lock */
5573 0 : if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5574 0 : return E1000_SUCCESS;
5575 :
5576 : /* Issue PHY reset */
5577 0 : em_phy_hw_reset(hw);
5578 0 : msec_delay_irq(5);
5579 : }
5580 : /* Disable GigE link negotiation */
5581 0 : reg = E1000_READ_REG(hw, PHY_CTRL);
5582 0 : E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE
5583 : | E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5584 :
5585 : /* unable to acquire PCS lock */
5586 0 : return E1000_ERR_PHY;
5587 : }
5588 0 : return E1000_SUCCESS;
5589 0 : }
5590 :
5591 : /******************************************************************************
5592 : * Reads and matches the expected PHY address for known PHY IDs
5593 : *
5594 : * hw - Struct containing variables accessed by shared code
5595 : *****************************************************************************/
5596 : STATIC int32_t
5597 0 : em_match_gig_phy(struct em_hw *hw)
5598 : {
5599 : int32_t phy_init_status, ret_val;
5600 0 : uint16_t phy_id_high, phy_id_low;
5601 : boolean_t match = FALSE;
5602 : DEBUGFUNC("em_match_gig_phy");
5603 :
5604 0 : ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
5605 0 : if (ret_val)
5606 0 : return ret_val;
5607 :
5608 0 : hw->phy_id = (uint32_t) (phy_id_high << 16);
5609 0 : usec_delay(20);
5610 0 : ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
5611 0 : if (ret_val)
5612 0 : return ret_val;
5613 :
5614 0 : hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
5615 0 : hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
5616 :
5617 0 : switch (hw->mac_type) {
5618 : case em_82543:
5619 0 : if (hw->phy_id == M88E1000_E_PHY_ID)
5620 0 : match = TRUE;
5621 : break;
5622 : case em_82544:
5623 0 : if (hw->phy_id == M88E1000_I_PHY_ID)
5624 0 : match = TRUE;
5625 : break;
5626 : case em_82540:
5627 : case em_82545:
5628 : case em_82545_rev_3:
5629 : case em_82546:
5630 : case em_82546_rev_3:
5631 0 : if (hw->phy_id == M88E1011_I_PHY_ID)
5632 0 : match = TRUE;
5633 : break;
5634 : case em_82541:
5635 : case em_82541_rev_2:
5636 : case em_82547:
5637 : case em_82547_rev_2:
5638 0 : if (hw->phy_id == IGP01E1000_I_PHY_ID)
5639 0 : match = TRUE;
5640 : break;
5641 : case em_82573:
5642 0 : if (hw->phy_id == M88E1111_I_PHY_ID)
5643 0 : match = TRUE;
5644 : break;
5645 : case em_82574:
5646 0 : if (hw->phy_id == BME1000_E_PHY_ID)
5647 0 : match = TRUE;
5648 : break;
5649 : case em_82575:
5650 0 : if (hw->phy_id == M88E1000_E_PHY_ID)
5651 0 : match = TRUE;
5652 0 : if (hw->phy_id == IGP01E1000_I_PHY_ID)
5653 0 : match = TRUE;
5654 0 : if (hw->phy_id == IGP03E1000_E_PHY_ID)
5655 0 : match = TRUE;
5656 : break;
5657 : case em_82580:
5658 : case em_i210:
5659 : case em_i350:
5660 0 : if (hw->phy_id == I82580_I_PHY_ID ||
5661 0 : hw->phy_id == I210_I_PHY_ID ||
5662 0 : hw->phy_id == I347AT4_E_PHY_ID ||
5663 0 : hw->phy_id == I350_I_PHY_ID ||
5664 0 : hw->phy_id == M88E1112_E_PHY_ID ||
5665 0 : hw->phy_id == M88E1543_E_PHY_ID ||
5666 0 : hw->phy_id == M88E1512_E_PHY_ID) {
5667 : uint32_t mdic;
5668 :
5669 0 : mdic = EM_READ_REG(hw, E1000_MDICNFG);
5670 0 : mdic &= E1000_MDICNFG_PHY_MASK;
5671 0 : hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
5672 : DEBUGOUT1("MDICNFG PHY ADDR %d",
5673 : mdic >> E1000_MDICNFG_PHY_SHIFT);
5674 : match = TRUE;
5675 0 : }
5676 : break;
5677 : case em_80003es2lan:
5678 0 : if (hw->phy_id == GG82563_E_PHY_ID)
5679 0 : match = TRUE;
5680 : break;
5681 : case em_ich8lan:
5682 : case em_ich9lan:
5683 : case em_ich10lan:
5684 : case em_pchlan:
5685 : case em_pch2lan:
5686 0 : if (hw->phy_id == IGP03E1000_E_PHY_ID)
5687 0 : match = TRUE;
5688 0 : if (hw->phy_id == IFE_E_PHY_ID)
5689 0 : match = TRUE;
5690 0 : if (hw->phy_id == IFE_PLUS_E_PHY_ID)
5691 0 : match = TRUE;
5692 0 : if (hw->phy_id == IFE_C_E_PHY_ID)
5693 0 : match = TRUE;
5694 0 : if (hw->phy_id == BME1000_E_PHY_ID)
5695 0 : match = TRUE;
5696 0 : if (hw->phy_id == I82577_E_PHY_ID)
5697 0 : match = TRUE;
5698 0 : if (hw->phy_id == I82578_E_PHY_ID)
5699 0 : match = TRUE;
5700 0 : if (hw->phy_id == I82579_E_PHY_ID)
5701 0 : match = TRUE;
5702 : break;
5703 : case em_pch_lpt:
5704 : case em_pch_spt:
5705 : case em_pch_cnp:
5706 0 : if (hw->phy_id == I217_E_PHY_ID)
5707 0 : match = TRUE;
5708 : break;
5709 : case em_icp_xxxx:
5710 0 : if (hw->phy_id == M88E1141_E_PHY_ID)
5711 0 : match = TRUE;
5712 0 : if (hw->phy_id == RTL8211_E_PHY_ID)
5713 0 : match = TRUE;
5714 : break;
5715 : default:
5716 : DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
5717 0 : return -E1000_ERR_CONFIG;
5718 : }
5719 0 : phy_init_status = em_set_phy_type(hw);
5720 :
5721 0 : if ((match) && (phy_init_status == E1000_SUCCESS)) {
5722 : DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
5723 0 : return E1000_SUCCESS;
5724 : }
5725 : DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
5726 0 : return -E1000_ERR_PHY;
5727 0 : }
5728 :
5729 : /******************************************************************************
5730 : * Probes the expected PHY address for known PHY IDs
5731 : *
5732 : * hw - Struct containing variables accessed by shared code
5733 : *****************************************************************************/
5734 : STATIC int32_t
5735 0 : em_detect_gig_phy(struct em_hw *hw)
5736 : {
5737 : int32_t ret_val;
5738 : DEBUGFUNC("em_detect_gig_phy");
5739 :
5740 0 : if (hw->phy_id != 0)
5741 0 : return E1000_SUCCESS;
5742 :
5743 : /* default phy address, most phys reside here, but not all (ICH10) */
5744 0 : if (hw->mac_type != em_icp_xxxx)
5745 0 : hw->phy_addr = 1;
5746 : else
5747 0 : hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */
5748 :
5749 : /*
5750 : * The 82571 firmware may still be configuring the PHY. In this
5751 : * case, we cannot access the PHY until the configuration is done.
5752 : * So we explicitly set the PHY values.
5753 : */
5754 0 : if (hw->mac_type == em_82571 ||
5755 0 : hw->mac_type == em_82572) {
5756 0 : hw->phy_id = IGP01E1000_I_PHY_ID;
5757 0 : hw->phy_type = em_phy_igp_2;
5758 0 : return E1000_SUCCESS;
5759 : }
5760 :
5761 : /*
5762 : * Some of the fiber cards dont have a phy, so we must exit cleanly
5763 : * here
5764 : */
5765 0 : if ((hw->media_type == em_media_type_fiber) &&
5766 0 : (hw->mac_type == em_82542_rev2_0 ||
5767 0 : hw->mac_type == em_82542_rev2_1 ||
5768 0 : hw->mac_type == em_82543 ||
5769 0 : hw->mac_type == em_82573 ||
5770 0 : hw->mac_type == em_82574 ||
5771 0 : hw->mac_type == em_80003es2lan)) {
5772 0 : hw->phy_type = em_phy_undefined;
5773 0 : return E1000_SUCCESS;
5774 : }
5775 :
5776 0 : if ((hw->media_type == em_media_type_internal_serdes ||
5777 0 : hw->media_type == em_media_type_fiber) &&
5778 0 : hw->mac_type >= em_82575) {
5779 0 : hw->phy_type = em_phy_undefined;
5780 0 : return E1000_SUCCESS;
5781 : }
5782 :
5783 : /*
5784 : * Up to 82543 (incl), we need reset the phy, or it might not get
5785 : * detected
5786 : */
5787 0 : if (hw->mac_type <= em_82543) {
5788 0 : ret_val = em_phy_hw_reset(hw);
5789 0 : if (ret_val)
5790 0 : return ret_val;
5791 : }
5792 : /*
5793 : * ESB-2 PHY reads require em_phy_gg82563 to be set because of a
5794 : * work- around that forces PHY page 0 to be set or the reads fail.
5795 : * The rest of the code in this routine uses em_read_phy_reg to read
5796 : * the PHY ID. So for ESB-2 we need to have this set so our reads
5797 : * won't fail. If the attached PHY is not a em_phy_gg82563, the
5798 : * routines below will figure this out as well.
5799 : */
5800 0 : if (hw->mac_type == em_80003es2lan)
5801 0 : hw->phy_type = em_phy_gg82563;
5802 :
5803 : /* Power on SGMII phy if it is disabled */
5804 0 : if (hw->mac_type == em_82580 || hw->mac_type == em_i210 ||
5805 0 : hw->mac_type == em_i350) {
5806 0 : uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT);
5807 0 : EM_WRITE_REG(hw, E1000_CTRL_EXT,
5808 : ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
5809 0 : delay(300);
5810 0 : }
5811 :
5812 : /* Read the PHY ID Registers to identify which PHY is onboard. */
5813 0 : for (hw->phy_addr = 1; (hw->phy_addr < 4); hw->phy_addr++) {
5814 0 : ret_val = em_match_gig_phy(hw);
5815 0 : if (ret_val == E1000_SUCCESS)
5816 0 : return E1000_SUCCESS;
5817 : }
5818 0 : return -E1000_ERR_PHY;
5819 0 : }
5820 :
5821 : /******************************************************************************
5822 : * Resets the PHY's DSP
5823 : *
5824 : * hw - Struct containing variables accessed by shared code
5825 : *****************************************************************************/
5826 : static int32_t
5827 0 : em_phy_reset_dsp(struct em_hw *hw)
5828 : {
5829 : int32_t ret_val;
5830 : DEBUGFUNC("em_phy_reset_dsp");
5831 :
5832 : do {
5833 0 : if (hw->phy_type != em_phy_gg82563) {
5834 0 : ret_val = em_write_phy_reg(hw, 29, 0x001d);
5835 0 : if (ret_val)
5836 : break;
5837 : }
5838 0 : ret_val = em_write_phy_reg(hw, 30, 0x00c1);
5839 0 : if (ret_val)
5840 : break;
5841 0 : ret_val = em_write_phy_reg(hw, 30, 0x0000);
5842 0 : if (ret_val)
5843 : break;
5844 : ret_val = E1000_SUCCESS;
5845 : } while (0);
5846 :
5847 0 : return ret_val;
5848 : }
5849 :
5850 : /******************************************************************************
5851 : * Sets up eeprom variables in the hw struct. Must be called after mac_type
5852 : * is configured. Additionally, if this is ICH8, the flash controller GbE
5853 : * registers must be mapped, or this will crash.
5854 : *
5855 : * hw - Struct containing variables accessed by shared code
5856 : *****************************************************************************/
5857 : int32_t
5858 0 : em_init_eeprom_params(struct em_hw *hw)
5859 : {
5860 0 : struct em_eeprom_info *eeprom = &hw->eeprom;
5861 0 : uint32_t eecd = E1000_READ_REG(hw, EECD);
5862 : int32_t ret_val = E1000_SUCCESS;
5863 0 : uint16_t eeprom_size;
5864 : DEBUGFUNC("em_init_eeprom_params");
5865 :
5866 0 : switch (hw->mac_type) {
5867 : case em_82542_rev2_0:
5868 : case em_82542_rev2_1:
5869 : case em_82543:
5870 : case em_82544:
5871 0 : eeprom->type = em_eeprom_microwire;
5872 0 : eeprom->word_size = 64;
5873 0 : eeprom->opcode_bits = 3;
5874 0 : eeprom->address_bits = 6;
5875 0 : eeprom->delay_usec = 50;
5876 0 : eeprom->use_eerd = FALSE;
5877 0 : eeprom->use_eewr = FALSE;
5878 0 : break;
5879 : case em_82540:
5880 : case em_82545:
5881 : case em_82545_rev_3:
5882 : case em_icp_xxxx:
5883 : case em_82546:
5884 : case em_82546_rev_3:
5885 0 : eeprom->type = em_eeprom_microwire;
5886 0 : eeprom->opcode_bits = 3;
5887 0 : eeprom->delay_usec = 50;
5888 0 : if (eecd & E1000_EECD_SIZE) {
5889 0 : eeprom->word_size = 256;
5890 0 : eeprom->address_bits = 8;
5891 0 : } else {
5892 0 : eeprom->word_size = 64;
5893 0 : eeprom->address_bits = 6;
5894 : }
5895 0 : eeprom->use_eerd = FALSE;
5896 0 : eeprom->use_eewr = FALSE;
5897 0 : break;
5898 : case em_82541:
5899 : case em_82541_rev_2:
5900 : case em_82547:
5901 : case em_82547_rev_2:
5902 0 : if (eecd & E1000_EECD_TYPE) {
5903 0 : eeprom->type = em_eeprom_spi;
5904 0 : eeprom->opcode_bits = 8;
5905 0 : eeprom->delay_usec = 1;
5906 0 : if (eecd & E1000_EECD_ADDR_BITS) {
5907 0 : eeprom->page_size = 32;
5908 0 : eeprom->address_bits = 16;
5909 0 : } else {
5910 0 : eeprom->page_size = 8;
5911 0 : eeprom->address_bits = 8;
5912 : }
5913 : } else {
5914 0 : eeprom->type = em_eeprom_microwire;
5915 0 : eeprom->opcode_bits = 3;
5916 0 : eeprom->delay_usec = 50;
5917 0 : if (eecd & E1000_EECD_ADDR_BITS) {
5918 0 : eeprom->word_size = 256;
5919 0 : eeprom->address_bits = 8;
5920 0 : } else {
5921 0 : eeprom->word_size = 64;
5922 0 : eeprom->address_bits = 6;
5923 : }
5924 : }
5925 0 : eeprom->use_eerd = FALSE;
5926 0 : eeprom->use_eewr = FALSE;
5927 0 : break;
5928 : case em_82571:
5929 : case em_82572:
5930 0 : eeprom->type = em_eeprom_spi;
5931 0 : eeprom->opcode_bits = 8;
5932 0 : eeprom->delay_usec = 1;
5933 0 : if (eecd & E1000_EECD_ADDR_BITS) {
5934 0 : eeprom->page_size = 32;
5935 0 : eeprom->address_bits = 16;
5936 0 : } else {
5937 0 : eeprom->page_size = 8;
5938 0 : eeprom->address_bits = 8;
5939 : }
5940 0 : eeprom->use_eerd = FALSE;
5941 0 : eeprom->use_eewr = FALSE;
5942 0 : break;
5943 : case em_82573:
5944 : case em_82574:
5945 : case em_82575:
5946 : case em_82580:
5947 : case em_i210:
5948 : case em_i350:
5949 0 : eeprom->type = em_eeprom_spi;
5950 0 : eeprom->opcode_bits = 8;
5951 0 : eeprom->delay_usec = 1;
5952 0 : if (eecd & E1000_EECD_ADDR_BITS) {
5953 0 : eeprom->page_size = 32;
5954 0 : eeprom->address_bits = 16;
5955 0 : } else {
5956 0 : eeprom->page_size = 8;
5957 0 : eeprom->address_bits = 8;
5958 : }
5959 0 : eeprom->use_eerd = TRUE;
5960 0 : eeprom->use_eewr = TRUE;
5961 0 : if (em_is_onboard_nvm_eeprom(hw) == FALSE) {
5962 0 : eeprom->type = em_eeprom_flash;
5963 0 : eeprom->word_size = 2048;
5964 : /*
5965 : * Ensure that the Autonomous FLASH update bit is
5966 : * cleared due to Flash update issue on parts which
5967 : * use a FLASH for NVM.
5968 : */
5969 0 : eecd &= ~E1000_EECD_AUPDEN;
5970 0 : E1000_WRITE_REG(hw, EECD, eecd);
5971 0 : }
5972 0 : if (em_get_flash_presence_i210(hw) == FALSE) {
5973 0 : eeprom->type = em_eeprom_invm;
5974 0 : eeprom->word_size = INVM_SIZE;
5975 0 : eeprom->use_eerd = FALSE;
5976 0 : eeprom->use_eewr = FALSE;
5977 0 : }
5978 : break;
5979 : case em_80003es2lan:
5980 0 : eeprom->type = em_eeprom_spi;
5981 0 : eeprom->opcode_bits = 8;
5982 0 : eeprom->delay_usec = 1;
5983 0 : if (eecd & E1000_EECD_ADDR_BITS) {
5984 0 : eeprom->page_size = 32;
5985 0 : eeprom->address_bits = 16;
5986 0 : } else {
5987 0 : eeprom->page_size = 8;
5988 0 : eeprom->address_bits = 8;
5989 : }
5990 0 : eeprom->use_eerd = TRUE;
5991 0 : eeprom->use_eewr = FALSE;
5992 0 : break;
5993 : case em_ich8lan:
5994 : case em_ich9lan:
5995 : case em_ich10lan:
5996 : case em_pchlan:
5997 : case em_pch2lan:
5998 : case em_pch_lpt:
5999 : {
6000 : int32_t i = 0;
6001 : uint32_t flash_size =
6002 0 : E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
6003 0 : eeprom->type = em_eeprom_ich8;
6004 0 : eeprom->use_eerd = FALSE;
6005 0 : eeprom->use_eewr = FALSE;
6006 0 : eeprom->word_size = E1000_SHADOW_RAM_WORDS;
6007 : /*
6008 : * Zero the shadow RAM structure. But don't load it
6009 : * from NVM so as to save time for driver init
6010 : */
6011 0 : if (hw->eeprom_shadow_ram != NULL) {
6012 0 : for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
6013 0 : hw->eeprom_shadow_ram[i].modified =
6014 : FALSE;
6015 0 : hw->eeprom_shadow_ram[i].eeprom_word =
6016 : 0xFFFF;
6017 : }
6018 : }
6019 0 : hw->flash_base_addr = (flash_size &
6020 0 : ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE;
6021 :
6022 0 : hw->flash_bank_size = ((flash_size >> 16) &
6023 0 : ICH_GFPREG_BASE_MASK) + 1;
6024 0 : hw->flash_bank_size -= (flash_size &
6025 : ICH_GFPREG_BASE_MASK);
6026 :
6027 0 : hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
6028 :
6029 0 : hw->flash_bank_size /= 2 * sizeof(uint16_t);
6030 :
6031 : break;
6032 : }
6033 : case em_pch_spt:
6034 : case em_pch_cnp:
6035 : {
6036 : int32_t i = 0;
6037 0 : uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */);
6038 :
6039 0 : eeprom->type = em_eeprom_ich8;
6040 0 : eeprom->use_eerd = FALSE;
6041 0 : eeprom->use_eewr = FALSE;
6042 0 : eeprom->word_size = E1000_SHADOW_RAM_WORDS;
6043 : /*
6044 : * Zero the shadow RAM structure. But don't load it
6045 : * from NVM so as to save time for driver init
6046 : */
6047 0 : if (hw->eeprom_shadow_ram != NULL) {
6048 0 : for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
6049 0 : hw->eeprom_shadow_ram[i].modified =
6050 : FALSE;
6051 0 : hw->eeprom_shadow_ram[i].eeprom_word =
6052 : 0xFFFF;
6053 : }
6054 : }
6055 0 : hw->flash_base_addr = 0;
6056 0 : flash_size = ((flash_size >> 1) & 0x1f) + 1;
6057 0 : flash_size *= 4096;
6058 0 : hw->flash_bank_size = flash_size / 4;
6059 : }
6060 0 : break;
6061 : default:
6062 : break;
6063 : }
6064 :
6065 0 : if (eeprom->type == em_eeprom_spi) {
6066 : /*
6067 : * eeprom_size will be an enum [0..8] that maps to eeprom
6068 : * sizes 128B to 32KB (incremented by powers of 2).
6069 : */
6070 0 : if (hw->mac_type <= em_82547_rev_2) {
6071 : /* Set to default value for initial eeprom read. */
6072 0 : eeprom->word_size = 64;
6073 0 : ret_val = em_read_eeprom(hw, EEPROM_CFG, 1,
6074 : &eeprom_size);
6075 0 : if (ret_val)
6076 0 : return ret_val;
6077 0 : eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >>
6078 : EEPROM_SIZE_SHIFT;
6079 : /*
6080 : * 256B eeprom size was not supported in earlier
6081 : * hardware, so we bump eeprom_size up one to ensure
6082 : * that "1" (which maps to 256B) is never the result
6083 : * used in the shifting logic below.
6084 : */
6085 0 : if (eeprom_size)
6086 0 : eeprom_size++;
6087 : } else {
6088 0 : eeprom_size = (uint16_t) (
6089 0 : (eecd & E1000_EECD_SIZE_EX_MASK) >>
6090 : E1000_EECD_SIZE_EX_SHIFT);
6091 : }
6092 :
6093 : /* EEPROM access above 16k is unsupported */
6094 0 : if (eeprom_size + EEPROM_WORD_SIZE_SHIFT >
6095 : EEPROM_WORD_SIZE_SHIFT_MAX) {
6096 0 : eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX;
6097 0 : } else {
6098 0 : eeprom->word_size = 1 <<
6099 : (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
6100 : }
6101 : }
6102 0 : return ret_val;
6103 0 : }
6104 :
6105 : /******************************************************************************
6106 : * Raises the EEPROM's clock input.
6107 : *
6108 : * hw - Struct containing variables accessed by shared code
6109 : * eecd - EECD's current value
6110 : *****************************************************************************/
6111 : static void
6112 0 : em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd)
6113 : {
6114 : /*
6115 : * Raise the clock input to the EEPROM (by setting the SK bit), and
6116 : * then wait <delay> microseconds.
6117 : */
6118 0 : *eecd = *eecd | E1000_EECD_SK;
6119 0 : E1000_WRITE_REG(hw, EECD, *eecd);
6120 0 : E1000_WRITE_FLUSH(hw);
6121 0 : usec_delay(hw->eeprom.delay_usec);
6122 0 : }
6123 :
6124 : /******************************************************************************
6125 : * Lowers the EEPROM's clock input.
6126 : *
6127 : * hw - Struct containing variables accessed by shared code
6128 : * eecd - EECD's current value
6129 : *****************************************************************************/
6130 : static void
6131 0 : em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd)
6132 : {
6133 : /*
6134 : * Lower the clock input to the EEPROM (by clearing the SK bit), and
6135 : * then wait 50 microseconds.
6136 : */
6137 0 : *eecd = *eecd & ~E1000_EECD_SK;
6138 0 : E1000_WRITE_REG(hw, EECD, *eecd);
6139 0 : E1000_WRITE_FLUSH(hw);
6140 0 : usec_delay(hw->eeprom.delay_usec);
6141 0 : }
6142 :
6143 : /******************************************************************************
6144 : * Shift data bits out to the EEPROM.
6145 : *
6146 : * hw - Struct containing variables accessed by shared code
6147 : * data - data to send to the EEPROM
6148 : * count - number of bits to shift out
6149 : *****************************************************************************/
6150 : static void
6151 0 : em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count)
6152 : {
6153 0 : struct em_eeprom_info *eeprom = &hw->eeprom;
6154 0 : uint32_t eecd;
6155 : uint32_t mask;
6156 : /*
6157 : * We need to shift "count" bits out to the EEPROM. So, value in the
6158 : * "data" parameter will be shifted out to the EEPROM one bit at a
6159 : * time. In order to do this, "data" must be broken down into bits.
6160 : */
6161 0 : mask = 0x01 << (count - 1);
6162 0 : eecd = E1000_READ_REG(hw, EECD);
6163 0 : if (eeprom->type == em_eeprom_microwire) {
6164 0 : eecd &= ~E1000_EECD_DO;
6165 0 : } else if (eeprom->type == em_eeprom_spi) {
6166 0 : eecd |= E1000_EECD_DO;
6167 0 : }
6168 0 : do {
6169 : /*
6170 : * A "1" is shifted out to the EEPROM by setting bit "DI" to
6171 : * a "1", and then raising and then lowering the clock (the
6172 : * SK bit controls the clock input to the EEPROM). A "0" is
6173 : * shifted out to the EEPROM by setting "DI" to "0" and then
6174 : * raising and then lowering the clock.
6175 : */
6176 0 : eecd &= ~E1000_EECD_DI;
6177 :
6178 0 : if (data & mask)
6179 0 : eecd |= E1000_EECD_DI;
6180 :
6181 0 : E1000_WRITE_REG(hw, EECD, eecd);
6182 0 : E1000_WRITE_FLUSH(hw);
6183 :
6184 0 : usec_delay(eeprom->delay_usec);
6185 :
6186 0 : em_raise_ee_clk(hw, &eecd);
6187 0 : em_lower_ee_clk(hw, &eecd);
6188 :
6189 0 : mask = mask >> 1;
6190 :
6191 0 : } while (mask);
6192 :
6193 : /* We leave the "DI" bit set to "0" when we leave this routine. */
6194 0 : eecd &= ~E1000_EECD_DI;
6195 0 : E1000_WRITE_REG(hw, EECD, eecd);
6196 0 : }
6197 :
6198 : /******************************************************************************
6199 : * Shift data bits in from the EEPROM
6200 : *
6201 : * hw - Struct containing variables accessed by shared code
6202 : *****************************************************************************/
6203 : static uint16_t
6204 0 : em_shift_in_ee_bits(struct em_hw *hw, uint16_t count)
6205 : {
6206 0 : uint32_t eecd;
6207 : uint32_t i;
6208 : uint16_t data;
6209 : /*
6210 : * In order to read a register from the EEPROM, we need to shift
6211 : * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
6212 : * the clock input to the EEPROM (setting the SK bit), and then
6213 : * reading the value of the "DO" bit. During this "shifting in"
6214 : * process the "DI" bit should always be clear.
6215 : */
6216 :
6217 0 : eecd = E1000_READ_REG(hw, EECD);
6218 :
6219 0 : eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
6220 : data = 0;
6221 :
6222 0 : for (i = 0; i < count; i++) {
6223 0 : data = data << 1;
6224 0 : em_raise_ee_clk(hw, &eecd);
6225 :
6226 0 : eecd = E1000_READ_REG(hw, EECD);
6227 :
6228 0 : eecd &= ~(E1000_EECD_DI);
6229 0 : if (eecd & E1000_EECD_DO)
6230 0 : data |= 1;
6231 :
6232 0 : em_lower_ee_clk(hw, &eecd);
6233 : }
6234 :
6235 0 : return data;
6236 0 : }
6237 : /******************************************************************************
6238 : * Prepares EEPROM for access
6239 : *
6240 : * hw - Struct containing variables accessed by shared code
6241 : *
6242 : * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
6243 : * function should be called before issuing a command to the EEPROM.
6244 : *****************************************************************************/
6245 : static int32_t
6246 0 : em_acquire_eeprom(struct em_hw *hw)
6247 : {
6248 0 : struct em_eeprom_info *eeprom = &hw->eeprom;
6249 : uint32_t eecd, i = 0;
6250 : DEBUGFUNC("em_acquire_eeprom");
6251 :
6252 0 : if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
6253 0 : return -E1000_ERR_SWFW_SYNC;
6254 0 : eecd = E1000_READ_REG(hw, EECD);
6255 :
6256 0 : if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) {
6257 : /* Request EEPROM Access */
6258 0 : if (hw->mac_type > em_82544) {
6259 0 : eecd |= E1000_EECD_REQ;
6260 0 : E1000_WRITE_REG(hw, EECD, eecd);
6261 0 : eecd = E1000_READ_REG(hw, EECD);
6262 0 : while ((!(eecd & E1000_EECD_GNT)) &&
6263 0 : (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
6264 0 : i++;
6265 0 : usec_delay(5);
6266 0 : eecd = E1000_READ_REG(hw, EECD);
6267 : }
6268 0 : if (!(eecd & E1000_EECD_GNT)) {
6269 0 : eecd &= ~E1000_EECD_REQ;
6270 0 : E1000_WRITE_REG(hw, EECD, eecd);
6271 : DEBUGOUT("Could not acquire EEPROM grant\n");
6272 0 : em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
6273 0 : return -E1000_ERR_EEPROM;
6274 : }
6275 : }
6276 : }
6277 :
6278 : /* Setup EEPROM for Read/Write */
6279 0 : if (eeprom->type == em_eeprom_microwire) {
6280 : /* Clear SK and DI */
6281 0 : eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
6282 0 : E1000_WRITE_REG(hw, EECD, eecd);
6283 :
6284 : /* Set CS */
6285 0 : eecd |= E1000_EECD_CS;
6286 0 : E1000_WRITE_REG(hw, EECD, eecd);
6287 0 : } else if (eeprom->type == em_eeprom_spi) {
6288 : /* Clear SK and CS */
6289 0 : eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
6290 0 : E1000_WRITE_REG(hw, EECD, eecd);
6291 0 : usec_delay(1);
6292 0 : }
6293 0 : return E1000_SUCCESS;
6294 0 : }
6295 :
6296 : /******************************************************************************
6297 : * Returns EEPROM to a "standby" state
6298 : *
6299 : * hw - Struct containing variables accessed by shared code
6300 : *****************************************************************************/
6301 : static void
6302 0 : em_standby_eeprom(struct em_hw *hw)
6303 : {
6304 0 : struct em_eeprom_info *eeprom = &hw->eeprom;
6305 : uint32_t eecd;
6306 0 : eecd = E1000_READ_REG(hw, EECD);
6307 :
6308 0 : if (eeprom->type == em_eeprom_microwire) {
6309 0 : eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
6310 0 : E1000_WRITE_REG(hw, EECD, eecd);
6311 0 : E1000_WRITE_FLUSH(hw);
6312 0 : usec_delay(eeprom->delay_usec);
6313 :
6314 : /* Clock high */
6315 0 : eecd |= E1000_EECD_SK;
6316 0 : E1000_WRITE_REG(hw, EECD, eecd);
6317 0 : E1000_WRITE_FLUSH(hw);
6318 0 : usec_delay(eeprom->delay_usec);
6319 :
6320 : /* Select EEPROM */
6321 0 : eecd |= E1000_EECD_CS;
6322 0 : E1000_WRITE_REG(hw, EECD, eecd);
6323 0 : E1000_WRITE_FLUSH(hw);
6324 0 : usec_delay(eeprom->delay_usec);
6325 :
6326 : /* Clock low */
6327 0 : eecd &= ~E1000_EECD_SK;
6328 0 : E1000_WRITE_REG(hw, EECD, eecd);
6329 0 : E1000_WRITE_FLUSH(hw);
6330 0 : usec_delay(eeprom->delay_usec);
6331 0 : } else if (eeprom->type == em_eeprom_spi) {
6332 : /* Toggle CS to flush commands */
6333 0 : eecd |= E1000_EECD_CS;
6334 0 : E1000_WRITE_REG(hw, EECD, eecd);
6335 0 : E1000_WRITE_FLUSH(hw);
6336 0 : usec_delay(eeprom->delay_usec);
6337 0 : eecd &= ~E1000_EECD_CS;
6338 0 : E1000_WRITE_REG(hw, EECD, eecd);
6339 0 : E1000_WRITE_FLUSH(hw);
6340 0 : usec_delay(eeprom->delay_usec);
6341 0 : }
6342 0 : }
6343 :
6344 : /******************************************************************************
6345 : * Terminates a command by inverting the EEPROM's chip select pin
6346 : *
6347 : * hw - Struct containing variables accessed by shared code
6348 : *****************************************************************************/
6349 : static void
6350 0 : em_release_eeprom(struct em_hw *hw)
6351 : {
6352 : uint32_t eecd;
6353 : DEBUGFUNC("em_release_eeprom");
6354 :
6355 0 : eecd = E1000_READ_REG(hw, EECD);
6356 :
6357 0 : if (hw->eeprom.type == em_eeprom_spi) {
6358 0 : eecd |= E1000_EECD_CS; /* Pull CS high */
6359 0 : eecd &= ~E1000_EECD_SK; /* Lower SCK */
6360 :
6361 0 : E1000_WRITE_REG(hw, EECD, eecd);
6362 :
6363 0 : usec_delay(hw->eeprom.delay_usec);
6364 0 : } else if (hw->eeprom.type == em_eeprom_microwire) {
6365 : /* cleanup eeprom */
6366 :
6367 : /* CS on Microwire is active-high */
6368 0 : eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
6369 :
6370 0 : E1000_WRITE_REG(hw, EECD, eecd);
6371 :
6372 : /* Rising edge of clock */
6373 0 : eecd |= E1000_EECD_SK;
6374 0 : E1000_WRITE_REG(hw, EECD, eecd);
6375 0 : E1000_WRITE_FLUSH(hw);
6376 0 : usec_delay(hw->eeprom.delay_usec);
6377 :
6378 : /* Falling edge of clock */
6379 0 : eecd &= ~E1000_EECD_SK;
6380 0 : E1000_WRITE_REG(hw, EECD, eecd);
6381 0 : E1000_WRITE_FLUSH(hw);
6382 0 : usec_delay(hw->eeprom.delay_usec);
6383 0 : }
6384 : /* Stop requesting EEPROM access */
6385 0 : if (hw->mac_type > em_82544) {
6386 0 : eecd &= ~E1000_EECD_REQ;
6387 0 : E1000_WRITE_REG(hw, EECD, eecd);
6388 0 : }
6389 0 : em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
6390 0 : }
6391 :
6392 : /******************************************************************************
6393 : * Reads a 16 bit word from the EEPROM.
6394 : *
6395 : * hw - Struct containing variables accessed by shared code
6396 : *****************************************************************************/
6397 : STATIC int32_t
6398 0 : em_spi_eeprom_ready(struct em_hw *hw)
6399 : {
6400 : uint16_t retry_count = 0;
6401 : uint8_t spi_stat_reg;
6402 : DEBUGFUNC("em_spi_eeprom_ready");
6403 : /*
6404 : * Read "Status Register" repeatedly until the LSB is cleared. The
6405 : * EEPROM will signal that the command has been completed by clearing
6406 : * bit 0 of the internal status register. If it's not cleared within
6407 : * 5 milliseconds, then error out.
6408 : */
6409 : retry_count = 0;
6410 0 : do {
6411 0 : em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
6412 0 : hw->eeprom.opcode_bits);
6413 0 : spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8);
6414 0 : if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
6415 : break;
6416 :
6417 0 : usec_delay(5);
6418 0 : retry_count += 5;
6419 :
6420 0 : em_standby_eeprom(hw);
6421 0 : } while (retry_count < EEPROM_MAX_RETRY_SPI);
6422 : /*
6423 : * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
6424 : * only 0-5mSec on 5V devices)
6425 : */
6426 0 : if (retry_count >= EEPROM_MAX_RETRY_SPI) {
6427 : DEBUGOUT("SPI EEPROM Status error\n");
6428 0 : return -E1000_ERR_EEPROM;
6429 : }
6430 0 : return E1000_SUCCESS;
6431 0 : }
6432 :
6433 : /******************************************************************************
6434 : * Reads a 16 bit word from the EEPROM.
6435 : *
6436 : * hw - Struct containing variables accessed by shared code
6437 : * offset - offset of word in the EEPROM to read
6438 : * data - word read from the EEPROM
6439 : * words - number of words to read
6440 : *****************************************************************************/
6441 : int32_t
6442 0 : em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words,
6443 : uint16_t *data)
6444 : {
6445 0 : struct em_eeprom_info *eeprom = &hw->eeprom;
6446 : uint32_t i = 0;
6447 : DEBUGFUNC("em_read_eeprom");
6448 :
6449 : /* If eeprom is not yet detected, do so now */
6450 0 : if (eeprom->word_size == 0)
6451 0 : em_init_eeprom_params(hw);
6452 : /*
6453 : * A check for invalid values: offset too large, too many words, and
6454 : * not enough words.
6455 : */
6456 0 : if ((offset >= eeprom->word_size) ||
6457 0 : (words > eeprom->word_size - offset) ||
6458 0 : (words == 0)) {
6459 : DEBUGOUT2("\"words\" parameter out of bounds. Words = %d,"
6460 : " size = %d\n", offset, eeprom->word_size);
6461 0 : return -E1000_ERR_EEPROM;
6462 : }
6463 : /*
6464 : * EEPROM's that don't use EERD to read require us to bit-bang the
6465 : * SPI directly. In this case, we need to acquire the EEPROM so that
6466 : * FW or other port software does not interrupt.
6467 : */
6468 0 : if (em_is_onboard_nvm_eeprom(hw) == TRUE &&
6469 0 : em_get_flash_presence_i210(hw) == TRUE &&
6470 0 : hw->eeprom.use_eerd == FALSE) {
6471 : /* Prepare the EEPROM for bit-bang reading */
6472 0 : if (em_acquire_eeprom(hw) != E1000_SUCCESS)
6473 0 : return -E1000_ERR_EEPROM;
6474 : }
6475 : /* Eerd register EEPROM access requires no eeprom aquire/release */
6476 0 : if (eeprom->use_eerd == TRUE)
6477 0 : return em_read_eeprom_eerd(hw, offset, words, data);
6478 :
6479 : /* ICH EEPROM access is done via the ICH flash controller */
6480 0 : if (eeprom->type == em_eeprom_ich8)
6481 0 : return em_read_eeprom_ich8(hw, offset, words, data);
6482 :
6483 : /* Some i210/i211 have a special OTP chip */
6484 0 : if (eeprom->type == em_eeprom_invm)
6485 0 : return em_read_invm_i210(hw, offset, words, data);
6486 :
6487 : /*
6488 : * Set up the SPI or Microwire EEPROM for bit-bang reading. We have
6489 : * acquired the EEPROM at this point, so any returns should relase it
6490 : */
6491 0 : if (eeprom->type == em_eeprom_spi) {
6492 : uint16_t word_in;
6493 : uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
6494 0 : if (em_spi_eeprom_ready(hw)) {
6495 0 : em_release_eeprom(hw);
6496 0 : return -E1000_ERR_EEPROM;
6497 : }
6498 0 : em_standby_eeprom(hw);
6499 : /*
6500 : * Some SPI eeproms use the 8th address bit embedded in the
6501 : * opcode
6502 : */
6503 0 : if ((eeprom->address_bits == 8) && (offset >= 128))
6504 0 : read_opcode |= EEPROM_A8_OPCODE_SPI;
6505 :
6506 : /* Send the READ command (opcode + addr) */
6507 0 : em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
6508 0 : em_shift_out_ee_bits(hw, (uint16_t) (offset * 2),
6509 0 : eeprom->address_bits);
6510 : /*
6511 : * Read the data. The address of the eeprom internally
6512 : * increments with each byte (spi) being read, saving on the
6513 : * overhead of eeprom setup and tear-down. The address
6514 : * counter will roll over if reading beyond the size of the
6515 : * eeprom, thus allowing the entire memory to be read
6516 : * starting from any offset.
6517 : */
6518 0 : for (i = 0; i < words; i++) {
6519 0 : word_in = em_shift_in_ee_bits(hw, 16);
6520 0 : data[i] = (word_in >> 8) | (word_in << 8);
6521 : }
6522 0 : } else if (eeprom->type == em_eeprom_microwire) {
6523 0 : for (i = 0; i < words; i++) {
6524 : /* Send the READ command (opcode + addr) */
6525 0 : em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
6526 0 : eeprom->opcode_bits);
6527 0 : em_shift_out_ee_bits(hw, (uint16_t) (offset + i),
6528 0 : eeprom->address_bits);
6529 : /*
6530 : * Read the data. For microwire, each word requires
6531 : * the overhead of eeprom setup and tear-down.
6532 : */
6533 0 : data[i] = em_shift_in_ee_bits(hw, 16);
6534 0 : em_standby_eeprom(hw);
6535 : }
6536 : }
6537 : /* End this read operation */
6538 0 : em_release_eeprom(hw);
6539 :
6540 0 : return E1000_SUCCESS;
6541 0 : }
6542 :
6543 : /******************************************************************************
6544 : * Reads a 16 bit word from the EEPROM using the EERD register.
6545 : *
6546 : * hw - Struct containing variables accessed by shared code
6547 : * offset - offset of word in the EEPROM to read
6548 : * data - word read from the EEPROM
6549 : * words - number of words to read
6550 : *****************************************************************************/
6551 : STATIC int32_t
6552 0 : em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words,
6553 : uint16_t *data)
6554 : {
6555 : uint32_t i, eerd = 0;
6556 : int32_t error = 0;
6557 0 : for (i = 0; i < words; i++) {
6558 0 : eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) +
6559 : E1000_EEPROM_RW_REG_START;
6560 :
6561 0 : E1000_WRITE_REG(hw, EERD, eerd);
6562 0 : error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
6563 :
6564 0 : if (error) {
6565 : break;
6566 : }
6567 0 : data[i] = (E1000_READ_REG(hw, EERD) >>
6568 : E1000_EEPROM_RW_REG_DATA);
6569 :
6570 : }
6571 :
6572 0 : return error;
6573 : }
6574 :
6575 : /******************************************************************************
6576 : * Writes a 16 bit word from the EEPROM using the EEWR register.
6577 : *
6578 : * hw - Struct containing variables accessed by shared code
6579 : * offset - offset of word in the EEPROM to read
6580 : * data - word read from the EEPROM
6581 : * words - number of words to read
6582 : *****************************************************************************/
6583 : STATIC int32_t
6584 0 : em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words,
6585 : uint16_t *data)
6586 : {
6587 : uint32_t register_value = 0;
6588 : uint32_t i = 0;
6589 : int32_t error = 0;
6590 0 : if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
6591 0 : return -E1000_ERR_SWFW_SYNC;
6592 :
6593 0 : for (i = 0; i < words; i++) {
6594 0 : register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
6595 0 : ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) |
6596 : E1000_EEPROM_RW_REG_START;
6597 :
6598 0 : error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
6599 0 : if (error) {
6600 : break;
6601 : }
6602 0 : E1000_WRITE_REG(hw, EEWR, register_value);
6603 :
6604 0 : error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
6605 :
6606 0 : if (error) {
6607 : break;
6608 : }
6609 : }
6610 :
6611 0 : em_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
6612 0 : return error;
6613 0 : }
6614 :
6615 : /******************************************************************************
6616 : * Polls the status bit (bit 1) of the EERD to determine when the read is done.
6617 : *
6618 : * hw - Struct containing variables accessed by shared code
6619 : *****************************************************************************/
6620 : STATIC int32_t
6621 0 : em_poll_eerd_eewr_done(struct em_hw *hw, int eerd)
6622 : {
6623 : uint32_t attempts = 100000;
6624 : uint32_t i, reg = 0;
6625 : int32_t done = E1000_ERR_EEPROM;
6626 0 : for (i = 0; i < attempts; i++) {
6627 0 : if (eerd == E1000_EEPROM_POLL_READ)
6628 0 : reg = E1000_READ_REG(hw, EERD);
6629 : else
6630 0 : reg = E1000_READ_REG(hw, EEWR);
6631 :
6632 0 : if (reg & E1000_EEPROM_RW_REG_DONE) {
6633 : done = E1000_SUCCESS;
6634 0 : break;
6635 : }
6636 0 : usec_delay(5);
6637 : }
6638 :
6639 0 : return done;
6640 : }
6641 :
6642 : /******************************************************************************
6643 : * Description: Determines if the onboard NVM is FLASH or EEPROM.
6644 : *
6645 : * hw - Struct containing variables accessed by shared code
6646 : *****************************************************************************/
6647 : STATIC boolean_t
6648 0 : em_is_onboard_nvm_eeprom(struct em_hw *hw)
6649 : {
6650 : uint32_t eecd = 0;
6651 : DEBUGFUNC("em_is_onboard_nvm_eeprom");
6652 :
6653 0 : if (IS_ICH8(hw->mac_type))
6654 0 : return FALSE;
6655 :
6656 0 : if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
6657 0 : eecd = E1000_READ_REG(hw, EECD);
6658 :
6659 : /* Isolate bits 15 & 16 */
6660 0 : eecd = ((eecd >> 15) & 0x03);
6661 :
6662 : /* If both bits are set, device is Flash type */
6663 0 : if (eecd == 0x03) {
6664 0 : return FALSE;
6665 : }
6666 : }
6667 0 : return TRUE;
6668 0 : }
6669 :
6670 : /******************************************************************************
6671 : * Check if flash device is detected.
6672 : *
6673 : * hw - Struct containing variables accessed by shared code
6674 : *****************************************************************************/
6675 : boolean_t
6676 0 : em_get_flash_presence_i210(struct em_hw *hw)
6677 : {
6678 : uint32_t eecd;
6679 : DEBUGFUNC("em_get_flash_presence_i210");
6680 :
6681 0 : if (hw->mac_type != em_i210)
6682 0 : return TRUE;
6683 :
6684 0 : eecd = E1000_READ_REG(hw, EECD);
6685 :
6686 0 : if (eecd & E1000_EECD_FLUPD)
6687 0 : return TRUE;
6688 :
6689 0 : return FALSE;
6690 0 : }
6691 :
6692 : /******************************************************************************
6693 : * Verifies that the EEPROM has a valid checksum
6694 : *
6695 : * hw - Struct containing variables accessed by shared code
6696 : *
6697 : * Reads the first 64 16 bit words of the EEPROM and sums the values read.
6698 : * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
6699 : * valid.
6700 : *****************************************************************************/
6701 : int32_t
6702 0 : em_validate_eeprom_checksum(struct em_hw *hw)
6703 : {
6704 : uint16_t checksum = 0;
6705 0 : uint16_t i, eeprom_data;
6706 : uint16_t checksum_reg;
6707 : DEBUGFUNC("em_validate_eeprom_checksum");
6708 :
6709 0 : checksum_reg = hw->mac_type != em_icp_xxxx ?
6710 : EEPROM_CHECKSUM_REG :
6711 : EEPROM_CHECKSUM_REG_ICP_xxxx;
6712 :
6713 0 : if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) &&
6714 0 : (em_is_onboard_nvm_eeprom(hw) == FALSE)) {
6715 : /*
6716 : * Check bit 4 of word 10h. If it is 0, firmware is done
6717 : * updating 10h-12h. Checksum may need to be fixed.
6718 : */
6719 0 : em_read_eeprom(hw, 0x10, 1, &eeprom_data);
6720 0 : if ((eeprom_data & 0x10) == 0) {
6721 : /*
6722 : * Read 0x23 and check bit 15. This bit is a 1 when
6723 : * the checksum has already been fixed. If the
6724 : * checksum is still wrong and this bit is a 1, we
6725 : * need to return bad checksum. Otherwise, we need
6726 : * to set this bit to a 1 and update the checksum.
6727 : */
6728 0 : em_read_eeprom(hw, 0x23, 1, &eeprom_data);
6729 0 : if ((eeprom_data & 0x8000) == 0) {
6730 0 : eeprom_data |= 0x8000;
6731 0 : em_write_eeprom(hw, 0x23, 1, &eeprom_data);
6732 0 : em_update_eeprom_checksum(hw);
6733 0 : }
6734 : }
6735 : }
6736 0 : if (IS_ICH8(hw->mac_type)) {
6737 : uint16_t word;
6738 : uint16_t valid_csum_mask;
6739 :
6740 : /*
6741 : * Drivers must allocate the shadow ram structure for the
6742 : * EEPROM checksum to be updated. Otherwise, this bit as
6743 : * well as the checksum must both be set correctly for this
6744 : * validation to pass.
6745 : */
6746 0 : switch (hw->mac_type) {
6747 : case em_pch_lpt:
6748 : case em_pch_spt:
6749 : case em_pch_cnp:
6750 : word = EEPROM_COMPAT;
6751 : valid_csum_mask = EEPROM_COMPAT_VALID_CSUM;
6752 0 : break;
6753 : default:
6754 : word = EEPROM_FUTURE_INIT_WORD1;
6755 : valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM;
6756 0 : break;
6757 : }
6758 0 : em_read_eeprom(hw, word, 1, &eeprom_data);
6759 0 : if ((eeprom_data & valid_csum_mask) == 0) {
6760 0 : eeprom_data |= valid_csum_mask;
6761 0 : em_write_eeprom(hw, word, 1, &eeprom_data);
6762 0 : em_update_eeprom_checksum(hw);
6763 0 : }
6764 0 : }
6765 0 : for (i = 0; i < (checksum_reg + 1); i++) {
6766 0 : if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
6767 : DEBUGOUT("EEPROM Read Error\n");
6768 0 : return -E1000_ERR_EEPROM;
6769 : }
6770 0 : checksum += eeprom_data;
6771 : }
6772 :
6773 0 : if (checksum == (uint16_t) EEPROM_SUM)
6774 0 : return E1000_SUCCESS;
6775 : else {
6776 : DEBUGOUT("EEPROM Checksum Invalid\n");
6777 0 : return -E1000_ERR_EEPROM;
6778 : }
6779 0 : }
6780 :
6781 : /******************************************************************************
6782 : * Calculates the EEPROM checksum and writes it to the EEPROM
6783 : *
6784 : * hw - Struct containing variables accessed by shared code
6785 : *
6786 : * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
6787 : * Writes the difference to word offset 63 of the EEPROM.
6788 : *****************************************************************************/
6789 : int32_t
6790 0 : em_update_eeprom_checksum(struct em_hw *hw)
6791 : {
6792 : uint32_t ctrl_ext;
6793 0 : uint16_t checksum = 0;
6794 0 : uint16_t i, eeprom_data;
6795 : DEBUGFUNC("em_update_eeprom_checksum");
6796 :
6797 0 : for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
6798 0 : if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
6799 : DEBUGOUT("EEPROM Read Error\n");
6800 0 : return -E1000_ERR_EEPROM;
6801 : }
6802 0 : checksum += eeprom_data;
6803 : }
6804 0 : checksum = (uint16_t) EEPROM_SUM - checksum;
6805 0 : if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
6806 : DEBUGOUT("EEPROM Write Error\n");
6807 0 : return -E1000_ERR_EEPROM;
6808 0 : } else if (hw->eeprom.type == em_eeprom_flash) {
6809 0 : em_commit_shadow_ram(hw);
6810 0 : } else if (hw->eeprom.type == em_eeprom_ich8) {
6811 0 : em_commit_shadow_ram(hw);
6812 : /*
6813 : * Reload the EEPROM, or else modifications will not appear
6814 : * until after next adapter reset.
6815 : */
6816 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
6817 0 : ctrl_ext |= E1000_CTRL_EXT_EE_RST;
6818 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
6819 0 : msec_delay(10);
6820 0 : }
6821 0 : return E1000_SUCCESS;
6822 0 : }
6823 :
6824 : /******************************************************************************
6825 : * Parent function for writing words to the different EEPROM types.
6826 : *
6827 : * hw - Struct containing variables accessed by shared code
6828 : * offset - offset within the EEPROM to be written to
6829 : * words - number of words to write
6830 : * data - 16 bit word to be written to the EEPROM
6831 : *
6832 : * If em_update_eeprom_checksum is not called after this function, the
6833 : * EEPROM will most likely contain an invalid checksum.
6834 : *****************************************************************************/
6835 : int32_t
6836 0 : em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words,
6837 : uint16_t *data)
6838 : {
6839 0 : struct em_eeprom_info *eeprom = &hw->eeprom;
6840 : int32_t status = 0;
6841 : DEBUGFUNC("em_write_eeprom");
6842 :
6843 : /* If eeprom is not yet detected, do so now */
6844 0 : if (eeprom->word_size == 0)
6845 0 : em_init_eeprom_params(hw);
6846 : /*
6847 : * A check for invalid values: offset too large, too many words, and
6848 : * not enough words.
6849 : */
6850 0 : if ((offset >= eeprom->word_size) ||
6851 0 : (words > eeprom->word_size - offset) ||
6852 0 : (words == 0)) {
6853 : DEBUGOUT("\"words\" parameter out of bounds\n");
6854 0 : return -E1000_ERR_EEPROM;
6855 : }
6856 : /* 82573/4 writes only through eewr */
6857 0 : if (eeprom->use_eewr == TRUE)
6858 0 : return em_write_eeprom_eewr(hw, offset, words, data);
6859 :
6860 0 : if (eeprom->type == em_eeprom_ich8)
6861 0 : return em_write_eeprom_ich8(hw, offset, words, data);
6862 :
6863 : /* Prepare the EEPROM for writing */
6864 0 : if (em_acquire_eeprom(hw) != E1000_SUCCESS)
6865 0 : return -E1000_ERR_EEPROM;
6866 :
6867 0 : if (eeprom->type == em_eeprom_microwire) {
6868 0 : status = em_write_eeprom_microwire(hw, offset, words, data);
6869 0 : } else {
6870 0 : status = em_write_eeprom_spi(hw, offset, words, data);
6871 0 : msec_delay(10);
6872 : }
6873 :
6874 : /* Done with writing */
6875 0 : em_release_eeprom(hw);
6876 :
6877 0 : return status;
6878 0 : }
6879 :
6880 : /******************************************************************************
6881 : * Writes a 16 bit word to a given offset in an SPI EEPROM.
6882 : *
6883 : * hw - Struct containing variables accessed by shared code
6884 : * offset - offset within the EEPROM to be written to
6885 : * words - number of words to write
6886 : * data - pointer to array of 8 bit words to be written to the EEPROM
6887 : *
6888 : *****************************************************************************/
6889 : STATIC int32_t
6890 0 : em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words,
6891 : uint16_t *data)
6892 : {
6893 0 : struct em_eeprom_info *eeprom = &hw->eeprom;
6894 : uint16_t widx = 0;
6895 : DEBUGFUNC("em_write_eeprom_spi");
6896 :
6897 0 : while (widx < words) {
6898 : uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
6899 0 : if (em_spi_eeprom_ready(hw))
6900 0 : return -E1000_ERR_EEPROM;
6901 :
6902 0 : em_standby_eeprom(hw);
6903 :
6904 : /* Send the WRITE ENABLE command (8 bit opcode ) */
6905 0 : em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
6906 0 : eeprom->opcode_bits);
6907 :
6908 0 : em_standby_eeprom(hw);
6909 : /*
6910 : * Some SPI eeproms use the 8th address bit embedded in the
6911 : * opcode
6912 : */
6913 0 : if ((eeprom->address_bits == 8) && (offset >= 128))
6914 0 : write_opcode |= EEPROM_A8_OPCODE_SPI;
6915 :
6916 : /* Send the Write command (8-bit opcode + addr) */
6917 0 : em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
6918 :
6919 0 : em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2),
6920 0 : eeprom->address_bits);
6921 :
6922 : /* Send the data */
6923 : /*
6924 : * Loop to allow for up to whole page write (32 bytes) of
6925 : * eeprom
6926 : */
6927 0 : while (widx < words) {
6928 0 : uint16_t word_out = data[widx];
6929 0 : word_out = (word_out >> 8) | (word_out << 8);
6930 0 : em_shift_out_ee_bits(hw, word_out, 16);
6931 0 : widx++;
6932 : /*
6933 : * Some larger eeprom sizes are capable of a 32-byte
6934 : * PAGE WRITE operation, while the smaller eeproms
6935 : * are capable of an 8-byte PAGE WRITE operation.
6936 : * Break the inner loop to pass new address
6937 : */
6938 0 : if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
6939 0 : em_standby_eeprom(hw);
6940 0 : break;
6941 : }
6942 0 : }
6943 0 : }
6944 :
6945 0 : return E1000_SUCCESS;
6946 0 : }
6947 :
6948 : /******************************************************************************
6949 : * Writes a 16 bit word to a given offset in a Microwire EEPROM.
6950 : *
6951 : * hw - Struct containing variables accessed by shared code
6952 : * offset - offset within the EEPROM to be written to
6953 : * words - number of words to write
6954 : * data - pointer to array of 16 bit words to be written to the EEPROM
6955 : *
6956 : *****************************************************************************/
6957 : STATIC int32_t
6958 0 : em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words,
6959 : uint16_t *data)
6960 : {
6961 0 : struct em_eeprom_info *eeprom = &hw->eeprom;
6962 : uint32_t eecd;
6963 : uint16_t words_written = 0;
6964 : uint16_t i = 0;
6965 : DEBUGFUNC("em_write_eeprom_microwire");
6966 : /*
6967 : * Send the write enable command to the EEPROM (3-bit opcode plus
6968 : * 6/8-bit dummy address beginning with 11). It's less work to
6969 : * include the 11 of the dummy address as part of the opcode than it
6970 : * is to shift it over the correct number of bits for the address.
6971 : * This puts the EEPROM into write/erase mode.
6972 : */
6973 0 : em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
6974 0 : (uint16_t) (eeprom->opcode_bits + 2));
6975 :
6976 0 : em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2));
6977 :
6978 : /* Prepare the EEPROM */
6979 0 : em_standby_eeprom(hw);
6980 :
6981 0 : while (words_written < words) {
6982 : /* Send the Write command (3-bit opcode + addr) */
6983 0 : em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
6984 : eeprom->opcode_bits);
6985 :
6986 0 : em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written),
6987 0 : eeprom->address_bits);
6988 :
6989 : /* Send the data */
6990 0 : em_shift_out_ee_bits(hw, data[words_written], 16);
6991 : /*
6992 : * Toggle the CS line. This in effect tells the EEPROM to
6993 : * execute the previous command.
6994 : */
6995 0 : em_standby_eeprom(hw);
6996 : /*
6997 : * Read DO repeatedly until it is high (equal to '1'). The
6998 : * EEPROM will signal that the command has been completed by
6999 : * raising the DO signal. If DO does not go high in 10
7000 : * milliseconds, then error out.
7001 : */
7002 0 : for (i = 0; i < 200; i++) {
7003 0 : eecd = E1000_READ_REG(hw, EECD);
7004 0 : if (eecd & E1000_EECD_DO)
7005 : break;
7006 0 : usec_delay(50);
7007 : }
7008 0 : if (i == 200) {
7009 : DEBUGOUT("EEPROM Write did not complete\n");
7010 0 : return -E1000_ERR_EEPROM;
7011 : }
7012 : /* Recover from write */
7013 0 : em_standby_eeprom(hw);
7014 :
7015 0 : words_written++;
7016 : }
7017 : /*
7018 : * Send the write disable command to the EEPROM (3-bit opcode plus
7019 : * 6/8-bit dummy address beginning with 10). It's less work to
7020 : * include the 10 of the dummy address as part of the opcode than it
7021 : * is to shift it over the correct number of bits for the address.
7022 : * This takes the EEPROM out of write/erase mode.
7023 : */
7024 0 : em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
7025 0 : (uint16_t) (eeprom->opcode_bits + 2));
7026 :
7027 0 : em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2));
7028 :
7029 0 : return E1000_SUCCESS;
7030 0 : }
7031 :
7032 : /******************************************************************************
7033 : * Flushes the cached eeprom to NVM. This is done by saving the modified values
7034 : * in the eeprom cache and the non modified values in the currently active bank
7035 : * to the new bank.
7036 : *
7037 : * hw - Struct containing variables accessed by shared code
7038 : * offset - offset of word in the EEPROM to read
7039 : * data - word read from the EEPROM
7040 : * words - number of words to read
7041 : *****************************************************************************/
7042 : STATIC int32_t
7043 0 : em_commit_shadow_ram(struct em_hw *hw)
7044 : {
7045 : uint32_t attempts = 100000;
7046 : uint32_t eecd = 0;
7047 : uint32_t flop = 0;
7048 : uint32_t i = 0;
7049 : int32_t error = E1000_SUCCESS;
7050 : uint32_t old_bank_offset = 0;
7051 : uint32_t new_bank_offset = 0;
7052 0 : uint8_t low_byte = 0;
7053 0 : uint8_t high_byte = 0;
7054 : boolean_t sector_write_failed = FALSE;
7055 0 : if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
7056 : /*
7057 : * The flop register will be used to determine if flash type
7058 : * is STM
7059 : */
7060 0 : flop = E1000_READ_REG(hw, FLOP);
7061 0 : for (i = 0; i < attempts; i++) {
7062 0 : eecd = E1000_READ_REG(hw, EECD);
7063 0 : if ((eecd & E1000_EECD_FLUPD) == 0) {
7064 : break;
7065 : }
7066 0 : usec_delay(5);
7067 : }
7068 :
7069 0 : if (i == attempts) {
7070 0 : return -E1000_ERR_EEPROM;
7071 : }
7072 : /*
7073 : * If STM opcode located in bits 15:8 of flop, reset firmware
7074 : */
7075 0 : if ((flop & 0xFF00) == E1000_STM_OPCODE) {
7076 0 : E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
7077 0 : }
7078 : /* Perform the flash update */
7079 0 : E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
7080 :
7081 0 : for (i = 0; i < attempts; i++) {
7082 0 : eecd = E1000_READ_REG(hw, EECD);
7083 0 : if ((eecd & E1000_EECD_FLUPD) == 0) {
7084 : break;
7085 : }
7086 0 : usec_delay(5);
7087 : }
7088 :
7089 0 : if (i == attempts) {
7090 0 : return -E1000_ERR_EEPROM;
7091 : }
7092 : }
7093 0 : if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) &&
7094 0 : hw->eeprom_shadow_ram != NULL) {
7095 : /*
7096 : * We're writing to the opposite bank so if we're on bank 1,
7097 : * write to bank 0 etc. We also need to erase the segment
7098 : * that is going to be written
7099 : */
7100 0 : if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
7101 : new_bank_offset = hw->flash_bank_size * 2;
7102 : old_bank_offset = 0;
7103 0 : em_erase_ich8_4k_segment(hw, 1);
7104 0 : } else {
7105 : old_bank_offset = hw->flash_bank_size * 2;
7106 : new_bank_offset = 0;
7107 0 : em_erase_ich8_4k_segment(hw, 0);
7108 : }
7109 :
7110 : sector_write_failed = FALSE;
7111 : /*
7112 : * Loop for every byte in the shadow RAM, which is in units
7113 : * of words.
7114 : */
7115 0 : for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7116 : /*
7117 : * Determine whether to write the value stored in the
7118 : * other NVM bank or a modified value stored in the
7119 : * shadow RAM
7120 : */
7121 0 : if (hw->eeprom_shadow_ram[i].modified == TRUE) {
7122 0 : low_byte = (uint8_t)
7123 0 : hw->eeprom_shadow_ram[i].eeprom_word;
7124 0 : usec_delay(100);
7125 0 : error = em_verify_write_ich8_byte(hw,
7126 0 : (i << 1) + new_bank_offset, low_byte);
7127 :
7128 0 : if (error != E1000_SUCCESS)
7129 0 : sector_write_failed = TRUE;
7130 : else {
7131 0 : high_byte = (uint8_t)
7132 0 : (hw->eeprom_shadow_ram
7133 0 : [i].eeprom_word >> 8);
7134 0 : usec_delay(100);
7135 : }
7136 : } else {
7137 0 : em_read_ich8_byte(hw, (i << 1) +
7138 : old_bank_offset, &low_byte);
7139 0 : usec_delay(100);
7140 0 : error = em_verify_write_ich8_byte(hw,
7141 0 : (i << 1) + new_bank_offset, low_byte);
7142 :
7143 0 : if (error != E1000_SUCCESS)
7144 0 : sector_write_failed = TRUE;
7145 : else {
7146 0 : em_read_ich8_byte(hw, (i << 1) +
7147 0 : old_bank_offset + 1, &high_byte);
7148 0 : usec_delay(100);
7149 : }
7150 : }
7151 : /*
7152 : * If the write of the low byte was successful, go
7153 : * ahread and write the high byte while checking to
7154 : * make sure that if it is the signature byte, then
7155 : * it is handled properly
7156 : */
7157 0 : if (sector_write_failed == FALSE) {
7158 : /*
7159 : * If the word is 0x13, then make sure the
7160 : * signature bits (15:14) are 11b until the
7161 : * commit has completed. This will allow us
7162 : * to write 10b which indicates the signature
7163 : * is valid. We want to do this after the
7164 : * write has completed so that we don't mark
7165 : * the segment valid while the write is still
7166 : * in progress
7167 : */
7168 0 : if (i == E1000_ICH_NVM_SIG_WORD)
7169 0 : high_byte = E1000_ICH_NVM_VALID_SIG_MASK |
7170 0 : high_byte;
7171 :
7172 0 : error = em_verify_write_ich8_byte(hw, (i << 1)
7173 0 : + new_bank_offset + 1, high_byte);
7174 0 : if (error != E1000_SUCCESS)
7175 0 : sector_write_failed = TRUE;
7176 :
7177 : } else {
7178 : /*
7179 : * If the write failed then break from the
7180 : * loop and return an error
7181 : */
7182 : break;
7183 : }
7184 : }
7185 : /*
7186 : * Don't bother writing the segment valid bits if sector
7187 : * programming failed.
7188 : */
7189 0 : if (sector_write_failed == FALSE) {
7190 : /*
7191 : * Finally validate the new segment by setting bit
7192 : * 15:14 to 10b in word 0x13 , this can be done
7193 : * without an erase as well since these bits are 11
7194 : * to start with and we need to change bit 14 to 0b
7195 : */
7196 0 : em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 +
7197 : new_bank_offset, &high_byte);
7198 0 : high_byte &= 0xBF;
7199 0 : error = em_verify_write_ich8_byte(hw,
7200 : E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
7201 : high_byte);
7202 : /*
7203 : * And invalidate the previously valid segment by
7204 : * setting its signature word (0x13) high_byte to 0b.
7205 : * This can be done without an erase because flash
7206 : * erase sets all bits to 1's. We can write 1's to
7207 : * 0's without an erase
7208 : */
7209 0 : if (error == E1000_SUCCESS) {
7210 0 : error = em_verify_write_ich8_byte(hw,
7211 0 : E1000_ICH_NVM_SIG_WORD * 2 + 1 +
7212 : old_bank_offset, 0);
7213 0 : }
7214 : /* Clear the now not used entry in the cache */
7215 0 : for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
7216 0 : hw->eeprom_shadow_ram[i].modified = FALSE;
7217 0 : hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
7218 : }
7219 : }
7220 : }
7221 0 : return error;
7222 0 : }
7223 :
7224 : /******************************************************************************
7225 : * Reads the adapter's part number from the EEPROM
7226 : *
7227 : * hw - Struct containing variables accessed by shared code
7228 : * part_num - Adapter's part number
7229 : *****************************************************************************/
7230 : int32_t
7231 0 : em_read_part_num(struct em_hw *hw, uint32_t *part_num)
7232 : {
7233 : uint16_t offset = EEPROM_PBA_BYTE_1;
7234 0 : uint16_t eeprom_data;
7235 : DEBUGFUNC("em_read_part_num");
7236 :
7237 : /* Get word 0 from EEPROM */
7238 0 : if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
7239 : DEBUGOUT("EEPROM Read Error\n");
7240 0 : return -E1000_ERR_EEPROM;
7241 : }
7242 : /* Save word 0 in upper half of part_num */
7243 0 : *part_num = (uint32_t) (eeprom_data << 16);
7244 :
7245 : /* Get word 1 from EEPROM */
7246 0 : if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
7247 : DEBUGOUT("EEPROM Read Error\n");
7248 0 : return -E1000_ERR_EEPROM;
7249 : }
7250 : /* Save word 1 in lower half of part_num */
7251 0 : *part_num |= eeprom_data;
7252 :
7253 0 : return E1000_SUCCESS;
7254 0 : }
7255 :
7256 : /******************************************************************************
7257 : * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
7258 : * second function of dual function devices
7259 : *
7260 : * hw - Struct containing variables accessed by shared code
7261 : *****************************************************************************/
7262 : int32_t
7263 0 : em_read_mac_addr(struct em_hw *hw)
7264 : {
7265 : uint16_t offset;
7266 0 : uint16_t eeprom_data, i;
7267 : uint16_t ia_base_addr = 0;
7268 : DEBUGFUNC("em_read_mac_addr");
7269 :
7270 0 : if (hw->mac_type == em_icp_xxxx) {
7271 0 : ia_base_addr = (uint16_t)
7272 0 : EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num);
7273 0 : } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) {
7274 0 : ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func);
7275 0 : }
7276 0 : for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
7277 0 : offset = i >> 1;
7278 0 : if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data)
7279 0 : < 0) {
7280 : DEBUGOUT("EEPROM Read Error\n");
7281 0 : return -E1000_ERR_EEPROM;
7282 : }
7283 0 : hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
7284 0 : hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8);
7285 : }
7286 :
7287 0 : switch (hw->mac_type) {
7288 : default:
7289 : break;
7290 : case em_82546:
7291 : case em_82546_rev_3:
7292 : case em_82571:
7293 : case em_82575:
7294 : case em_80003es2lan:
7295 0 : if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
7296 0 : hw->perm_mac_addr[5] ^= 0x01;
7297 : break;
7298 : }
7299 :
7300 0 : for (i = 0; i < NODE_ADDRESS_SIZE; i++)
7301 0 : hw->mac_addr[i] = hw->perm_mac_addr[i];
7302 0 : return E1000_SUCCESS;
7303 0 : }
7304 :
7305 : /******************************************************************************
7306 : * Explicitly disables jumbo frames and resets some PHY registers back to hw-
7307 : * defaults. This is necessary in case the ethernet cable was inserted AFTER
7308 : * the firmware initialized the PHY. Otherwise it is left in a state where
7309 : * it is possible to transmit but not receive packets. Observed on I217-LM and
7310 : * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c.
7311 : *
7312 : * hw - Struct containing variables accessed by shared code
7313 : *****************************************************************************/
7314 : STATIC int32_t
7315 0 : em_phy_no_cable_workaround(struct em_hw *hw) {
7316 : int32_t ret_val, dft_ret_val;
7317 : uint32_t mac_reg;
7318 0 : uint16_t data, phy_reg;
7319 :
7320 : /* disable Rx path while enabling workaround */
7321 0 : em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg);
7322 0 : ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14));
7323 0 : if (ret_val)
7324 0 : return ret_val;
7325 :
7326 : /* Write MAC register values back to h/w defaults */
7327 0 : mac_reg = E1000_READ_REG(hw, FFLT_DBG);
7328 0 : mac_reg &= ~(0xF << 14);
7329 0 : E1000_WRITE_REG(hw, FFLT_DBG, mac_reg);
7330 :
7331 0 : mac_reg = E1000_READ_REG(hw, RCTL);
7332 0 : mac_reg &= ~E1000_RCTL_SECRC;
7333 0 : E1000_WRITE_REG(hw, RCTL, mac_reg);
7334 :
7335 0 : ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data);
7336 0 : if (ret_val)
7337 : goto out;
7338 0 : ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL,
7339 0 : data & ~(1 << 0));
7340 0 : if (ret_val)
7341 : goto out;
7342 :
7343 0 : ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data);
7344 0 : if (ret_val)
7345 : goto out;
7346 :
7347 0 : data &= ~(0xF << 8);
7348 0 : data |= (0xB << 8);
7349 0 : ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data);
7350 0 : if (ret_val)
7351 : goto out;
7352 :
7353 : /* Write PHY register values back to h/w defaults */
7354 0 : em_read_phy_reg(hw, I2_SMBUS_CTRL, &data);
7355 0 : data &= ~(0x7F << 5);
7356 0 : ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data);
7357 0 : if (ret_val)
7358 : goto out;
7359 :
7360 0 : em_read_phy_reg(hw, I2_MODE_CTRL, &data);
7361 0 : data |= (1 << 13);
7362 0 : ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data);
7363 0 : if (ret_val)
7364 : goto out;
7365 :
7366 : /*
7367 : * 776.20 and 776.23 are not documented in
7368 : * i217-ethernet-controller-datasheet.pdf...
7369 : */
7370 0 : em_read_phy_reg(hw, PHY_REG(776, 20), &data);
7371 0 : data &= ~(0x3FF << 2);
7372 0 : data |= (0x8 << 2);
7373 0 : ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data);
7374 0 : if (ret_val)
7375 : goto out;
7376 :
7377 0 : ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00);
7378 0 : if (ret_val)
7379 : goto out;
7380 :
7381 0 : em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data);
7382 0 : ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10));
7383 : if (ret_val)
7384 0 : goto out;
7385 :
7386 : out:
7387 : /* re-enable Rx path after enabling workaround */
7388 0 : dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14));
7389 0 : if (ret_val)
7390 0 : return ret_val;
7391 : else
7392 0 : return dft_ret_val;
7393 0 : }
7394 :
7395 : /******************************************************************************
7396 : * Initializes receive address filters.
7397 : *
7398 : * hw - Struct containing variables accessed by shared code
7399 : *
7400 : * Places the MAC address in receive address register 0 and clears the rest
7401 : * of the receive addresss registers. Clears the multicast table. Assumes
7402 : * the receiver is in reset when the routine is called.
7403 : *****************************************************************************/
7404 : STATIC void
7405 0 : em_init_rx_addrs(struct em_hw *hw)
7406 : {
7407 : uint32_t i;
7408 : uint32_t rar_num;
7409 : DEBUGFUNC("em_init_rx_addrs");
7410 :
7411 0 : if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt ||
7412 0 : hw->mac_type == em_pch_cnp || hw->mac_type == em_pch2lan)
7413 0 : if (em_phy_no_cable_workaround(hw))
7414 0 : printf(" ...failed to apply em_phy_no_cable_"
7415 : "workaround.\n");
7416 :
7417 : /* Setup the receive address. */
7418 : DEBUGOUT("Programming MAC Address into RAR[0]\n");
7419 :
7420 0 : em_rar_set(hw, hw->mac_addr, 0);
7421 :
7422 : rar_num = E1000_RAR_ENTRIES;
7423 : /*
7424 : * Reserve a spot for the Locally Administered Address to work around
7425 : * an 82571 issue in which a reset on one port will reload the MAC on
7426 : * the other port.
7427 : */
7428 0 : if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
7429 0 : rar_num -= 1;
7430 0 : if (IS_ICH8(hw->mac_type))
7431 0 : rar_num = E1000_RAR_ENTRIES_ICH8LAN;
7432 0 : if (hw->mac_type == em_ich8lan)
7433 0 : rar_num -= 1;
7434 0 : if (hw->mac_type == em_82580)
7435 0 : rar_num = E1000_RAR_ENTRIES_82580;
7436 0 : if (hw->mac_type == em_i210)
7437 0 : rar_num = E1000_RAR_ENTRIES_82575;
7438 0 : if (hw->mac_type == em_i350)
7439 0 : rar_num = E1000_RAR_ENTRIES_I350;
7440 :
7441 : /* Zero out the other 15 receive addresses. */
7442 : DEBUGOUT("Clearing RAR[1-15]\n");
7443 0 : for (i = 1; i < rar_num; i++) {
7444 0 : E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
7445 0 : E1000_WRITE_FLUSH(hw);
7446 0 : E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
7447 0 : E1000_WRITE_FLUSH(hw);
7448 : }
7449 0 : }
7450 :
7451 : /******************************************************************************
7452 : * Updates the MAC's list of multicast addresses.
7453 : *
7454 : * hw - Struct containing variables accessed by shared code
7455 : * mc_addr_list - the list of new multicast addresses
7456 : * mc_addr_count - number of addresses
7457 : * pad - number of bytes between addresses in the list
7458 : * rar_used_count - offset where to start adding mc addresses into the RAR's
7459 : *
7460 : * The given list replaces any existing list. Clears the last 15 receive
7461 : * address registers and the multicast table. Uses receive address registers
7462 : * for the first 15 multicast addresses, and hashes the rest into the
7463 : * multicast table.
7464 : *****************************************************************************/
7465 : void
7466 0 : em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list,
7467 : uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count)
7468 : {
7469 : uint32_t hash_value;
7470 : uint32_t i;
7471 : uint32_t num_rar_entry;
7472 : uint32_t num_mta_entry;
7473 : DEBUGFUNC("em_mc_addr_list_update");
7474 : /*
7475 : * Set the new number of MC addresses that we are being requested to
7476 : * use.
7477 : */
7478 0 : hw->num_mc_addrs = mc_addr_count;
7479 :
7480 : /* Clear RAR[1-15] */
7481 : DEBUGOUT(" Clearing RAR[1-15]\n");
7482 : num_rar_entry = E1000_RAR_ENTRIES;
7483 0 : if (IS_ICH8(hw->mac_type))
7484 0 : num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
7485 0 : if (hw->mac_type == em_ich8lan)
7486 0 : num_rar_entry -= 1;
7487 : /*
7488 : * Reserve a spot for the Locally Administered Address to work around
7489 : * an 82571 issue in which a reset on one port will reload the MAC on
7490 : * the other port.
7491 : */
7492 0 : if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE))
7493 0 : num_rar_entry -= 1;
7494 :
7495 0 : for (i = rar_used_count; i < num_rar_entry; i++) {
7496 0 : E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
7497 0 : E1000_WRITE_FLUSH(hw);
7498 0 : E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
7499 0 : E1000_WRITE_FLUSH(hw);
7500 : }
7501 :
7502 : /* Clear the MTA */
7503 : DEBUGOUT(" Clearing MTA\n");
7504 : num_mta_entry = E1000_NUM_MTA_REGISTERS;
7505 0 : if (IS_ICH8(hw->mac_type))
7506 0 : num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
7507 :
7508 0 : for (i = 0; i < num_mta_entry; i++) {
7509 0 : E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
7510 0 : E1000_WRITE_FLUSH(hw);
7511 : }
7512 :
7513 : /* Add the new addresses */
7514 0 : for (i = 0; i < mc_addr_count; i++) {
7515 : DEBUGOUT(" Adding the multicast addresses:\n");
7516 : DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
7517 : mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
7518 : mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
7519 : mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
7520 : mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
7521 : mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
7522 : mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
7523 :
7524 0 : hash_value = em_hash_mc_addr(hw, mc_addr_list +
7525 0 : (i * (ETH_LENGTH_OF_ADDRESS + pad)));
7526 :
7527 : DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
7528 : /*
7529 : * Place this multicast address in the RAR if there is room, *
7530 : * else put it in the MTA
7531 : */
7532 0 : if (rar_used_count < num_rar_entry) {
7533 0 : em_rar_set(hw, mc_addr_list +
7534 : (i * (ETH_LENGTH_OF_ADDRESS + pad)),
7535 : rar_used_count);
7536 0 : rar_used_count++;
7537 0 : } else {
7538 0 : em_mta_set(hw, hash_value);
7539 : }
7540 : }
7541 : DEBUGOUT("MC Update Complete\n");
7542 0 : }
7543 :
7544 : /******************************************************************************
7545 : * Hashes an address to determine its location in the multicast table
7546 : *
7547 : * hw - Struct containing variables accessed by shared code
7548 : * mc_addr - the multicast address to hash
7549 : *****************************************************************************/
7550 : uint32_t
7551 0 : em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr)
7552 : {
7553 : uint32_t hash_value = 0;
7554 : /*
7555 : * The portion of the address that is used for the hash table is
7556 : * determined by the mc_filter_type setting.
7557 : */
7558 0 : switch (hw->mc_filter_type) {
7559 : /*
7560 : * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB
7561 : * MSB
7562 : */
7563 : case 0:
7564 0 : if (IS_ICH8(hw->mac_type)) {
7565 : /* [47:38] i.e. 0x158 for above example address */
7566 0 : hash_value = ((mc_addr[4] >> 6) |
7567 0 : (((uint16_t) mc_addr[5]) << 2));
7568 0 : } else {
7569 : /* [47:36] i.e. 0x563 for above example address */
7570 0 : hash_value = ((mc_addr[4] >> 4) |
7571 0 : (((uint16_t) mc_addr[5]) << 4));
7572 : }
7573 : break;
7574 : case 1:
7575 0 : if (IS_ICH8(hw->mac_type)) {
7576 : /* [46:37] i.e. 0x2B1 for above example address */
7577 0 : hash_value = ((mc_addr[4] >> 5) |
7578 0 : (((uint16_t) mc_addr[5]) << 3));
7579 0 : } else {
7580 : /* [46:35] i.e. 0xAC6 for above example address */
7581 0 : hash_value = ((mc_addr[4] >> 3) |
7582 0 : (((uint16_t) mc_addr[5]) << 5));
7583 : }
7584 : break;
7585 : case 2:
7586 0 : if (IS_ICH8(hw->mac_type)) {
7587 : /* [45:36] i.e. 0x163 for above example address */
7588 0 : hash_value = ((mc_addr[4] >> 4) |
7589 0 : (((uint16_t) mc_addr[5]) << 4));
7590 0 : } else {
7591 : /* [45:34] i.e. 0x5D8 for above example address */
7592 0 : hash_value = ((mc_addr[4] >> 2) |
7593 0 : (((uint16_t) mc_addr[5]) << 6));
7594 : }
7595 : break;
7596 : case 3:
7597 0 : if (IS_ICH8(hw->mac_type)) {
7598 : /* [43:34] i.e. 0x18D for above example address */
7599 0 : hash_value = ((mc_addr[4] >> 2) |
7600 0 : (((uint16_t) mc_addr[5]) << 6));
7601 0 : } else {
7602 : /* [43:32] i.e. 0x634 for above example address */
7603 0 : hash_value = ((mc_addr[4]) |
7604 0 : (((uint16_t) mc_addr[5]) << 8));
7605 : }
7606 : break;
7607 : }
7608 :
7609 0 : hash_value &= 0xFFF;
7610 0 : if (IS_ICH8(hw->mac_type))
7611 0 : hash_value &= 0x3FF;
7612 :
7613 0 : return hash_value;
7614 : }
7615 :
7616 : /******************************************************************************
7617 : * Sets the bit in the multicast table corresponding to the hash value.
7618 : *
7619 : * hw - Struct containing variables accessed by shared code
7620 : * hash_value - Multicast address hash value
7621 : *****************************************************************************/
7622 : void
7623 0 : em_mta_set(struct em_hw *hw, uint32_t hash_value)
7624 : {
7625 : uint32_t hash_bit, hash_reg;
7626 : uint32_t mta;
7627 : uint32_t temp;
7628 : /*
7629 : * The MTA is a register array of 128 32-bit registers. It is treated
7630 : * like an array of 4096 bits. We want to set bit
7631 : * BitArray[hash_value]. So we figure out what register the bit is
7632 : * in, read it, OR in the new bit, then write back the new value.
7633 : * The register is determined by the upper 7 bits of the hash value
7634 : * and the bit within that register are determined by the lower 5
7635 : * bits of the value.
7636 : */
7637 0 : hash_reg = (hash_value >> 5) & 0x7F;
7638 0 : if (IS_ICH8(hw->mac_type))
7639 0 : hash_reg &= 0x1F;
7640 :
7641 0 : hash_bit = hash_value & 0x1F;
7642 :
7643 0 : mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
7644 :
7645 0 : mta |= (1 << hash_bit);
7646 : /*
7647 : * If we are on an 82544 and we are trying to write an odd offset in
7648 : * the MTA, save off the previous entry before writing and restore
7649 : * the old value after writing.
7650 : */
7651 0 : if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
7652 0 : temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
7653 0 : E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
7654 0 : E1000_WRITE_FLUSH(hw);
7655 0 : E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
7656 0 : E1000_WRITE_FLUSH(hw);
7657 0 : } else {
7658 0 : E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
7659 0 : E1000_WRITE_FLUSH(hw);
7660 : }
7661 0 : }
7662 :
7663 : /******************************************************************************
7664 : * Puts an ethernet address into a receive address register.
7665 : *
7666 : * hw - Struct containing variables accessed by shared code
7667 : * addr - Address to put into receive address register
7668 : * index - Receive address register to write
7669 : *****************************************************************************/
7670 : void
7671 0 : em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index)
7672 : {
7673 : uint32_t rar_low, rar_high;
7674 : /*
7675 : * HW expects these in little endian so we reverse the byte order
7676 : * from network order (big endian) to little endian
7677 : */
7678 0 : rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) |
7679 0 : ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
7680 0 : rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
7681 : /*
7682 : * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
7683 : * unit hang.
7684 : *
7685 : * Description: If there are any Rx frames queued up or otherwise
7686 : * present in the HW before RSS is enabled, and then we enable RSS,
7687 : * the HW Rx unit will hang. To work around this issue, we have to
7688 : * disable receives and flush out all Rx frames before we enable RSS.
7689 : * To do so, we modify we redirect all Rx traffic to manageability
7690 : * and then reset the HW. This flushes away Rx frames, and (since the
7691 : * redirections to manageability persists across resets) keeps new
7692 : * ones from coming in while we work. Then, we clear the Address
7693 : * Valid AV bit for all MAC addresses and undo the re-direction to
7694 : * manageability. Now, frames are coming in again, but the MAC won't
7695 : * accept them, so far so good. We now proceed to initialize RSS (if
7696 : * necessary) and configure the Rx unit. Last, we re-enable the AV
7697 : * bits and continue on our merry way.
7698 : */
7699 0 : switch (hw->mac_type) {
7700 : case em_82571:
7701 : case em_82572:
7702 : case em_80003es2lan:
7703 0 : if (hw->leave_av_bit_off == TRUE)
7704 : break;
7705 : default:
7706 : /* Indicate to hardware the Address is Valid. */
7707 0 : rar_high |= E1000_RAH_AV;
7708 0 : break;
7709 : }
7710 :
7711 0 : E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
7712 0 : E1000_WRITE_FLUSH(hw);
7713 0 : E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
7714 0 : E1000_WRITE_FLUSH(hw);
7715 0 : }
7716 :
7717 : /******************************************************************************
7718 : * Clears the VLAN filer table
7719 : *
7720 : * hw - Struct containing variables accessed by shared code
7721 : *****************************************************************************/
7722 : STATIC void
7723 0 : em_clear_vfta(struct em_hw *hw)
7724 : {
7725 : uint32_t offset;
7726 : uint32_t vfta_value = 0;
7727 : uint32_t vfta_offset = 0;
7728 : uint32_t vfta_bit_in_reg = 0;
7729 0 : if (IS_ICH8(hw->mac_type))
7730 0 : return;
7731 :
7732 0 : if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
7733 0 : if (hw->mng_cookie.vlan_id != 0) {
7734 : /*
7735 : * The VFTA is a 4096b bit-field, each identifying a
7736 : * single VLAN ID. The following operations
7737 : * determine which 32b entry (i.e. offset) into the
7738 : * array we want to set the VLAN ID (i.e. bit) of the
7739 : * manageability unit.
7740 : */
7741 0 : vfta_offset = (hw->mng_cookie.vlan_id >>
7742 0 : E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
7743 :
7744 0 : vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
7745 : E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
7746 0 : }
7747 : }
7748 0 : for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
7749 : /*
7750 : * If the offset we want to clear is the same offset of the
7751 : * manageability VLAN ID, then clear all bits except that of
7752 : * the manageability unit
7753 : */
7754 0 : vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
7755 0 : E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
7756 0 : E1000_WRITE_FLUSH(hw);
7757 : }
7758 0 : }
7759 :
7760 : /*
7761 : * Due to hw errata, if the host tries to configure the VFTA register
7762 : * while performing queries from the BMC or DMA, then the VFTA in some
7763 : * cases won't be written.
7764 : */
7765 : void
7766 0 : em_clear_vfta_i350(struct em_hw *hw)
7767 : {
7768 : uint32_t offset;
7769 : int i;
7770 :
7771 0 : for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
7772 0 : for (i = 0; i < 10; i++)
7773 0 : E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
7774 0 : E1000_WRITE_FLUSH(hw);
7775 : }
7776 0 : }
7777 :
7778 : STATIC int32_t
7779 0 : em_id_led_init(struct em_hw *hw)
7780 : {
7781 : uint32_t ledctl;
7782 : const uint32_t ledctl_mask = 0x000000FF;
7783 : const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
7784 : const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
7785 0 : uint16_t eeprom_data, i, temp;
7786 : const uint16_t led_mask = 0x0F;
7787 : DEBUGFUNC("em_id_led_init");
7788 :
7789 0 : if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) {
7790 : /* Nothing to do */
7791 0 : return E1000_SUCCESS;
7792 : }
7793 0 : ledctl = E1000_READ_REG(hw, LEDCTL);
7794 0 : hw->ledctl_default = ledctl;
7795 0 : hw->ledctl_mode1 = hw->ledctl_default;
7796 0 : hw->ledctl_mode2 = hw->ledctl_default;
7797 :
7798 0 : if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
7799 : DEBUGOUT("EEPROM Read Error\n");
7800 0 : return -E1000_ERR_EEPROM;
7801 : }
7802 0 : if ((hw->mac_type == em_82573) &&
7803 0 : (eeprom_data == ID_LED_RESERVED_82573))
7804 0 : eeprom_data = ID_LED_DEFAULT_82573;
7805 0 : else if ((eeprom_data == ID_LED_RESERVED_0000) ||
7806 0 : (eeprom_data == ID_LED_RESERVED_FFFF)) {
7807 0 : if (hw->mac_type == em_ich8lan ||
7808 0 : hw->mac_type == em_ich9lan ||
7809 0 : hw->mac_type == em_ich10lan) // XXX
7810 0 : eeprom_data = ID_LED_DEFAULT_ICH8LAN;
7811 : else
7812 0 : eeprom_data = ID_LED_DEFAULT;
7813 : }
7814 0 : for (i = 0; i < 4; i++) {
7815 0 : temp = (eeprom_data >> (i << 2)) & led_mask;
7816 0 : switch (temp) {
7817 : case ID_LED_ON1_DEF2:
7818 : case ID_LED_ON1_ON2:
7819 : case ID_LED_ON1_OFF2:
7820 0 : hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
7821 0 : hw->ledctl_mode1 |= ledctl_on << (i << 3);
7822 0 : break;
7823 : case ID_LED_OFF1_DEF2:
7824 : case ID_LED_OFF1_ON2:
7825 : case ID_LED_OFF1_OFF2:
7826 0 : hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
7827 0 : hw->ledctl_mode1 |= ledctl_off << (i << 3);
7828 0 : break;
7829 : default:
7830 : /* Do nothing */
7831 : break;
7832 : }
7833 0 : switch (temp) {
7834 : case ID_LED_DEF1_ON2:
7835 : case ID_LED_ON1_ON2:
7836 : case ID_LED_OFF1_ON2:
7837 0 : hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
7838 0 : hw->ledctl_mode2 |= ledctl_on << (i << 3);
7839 0 : break;
7840 : case ID_LED_DEF1_OFF2:
7841 : case ID_LED_ON1_OFF2:
7842 : case ID_LED_OFF1_OFF2:
7843 0 : hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
7844 0 : hw->ledctl_mode2 |= ledctl_off << (i << 3);
7845 0 : break;
7846 : default:
7847 : /* Do nothing */
7848 : break;
7849 : }
7850 : }
7851 0 : return E1000_SUCCESS;
7852 0 : }
7853 :
7854 : /******************************************************************************
7855 : * Clears all hardware statistics counters.
7856 : *
7857 : * hw - Struct containing variables accessed by shared code
7858 : *****************************************************************************/
7859 : void
7860 0 : em_clear_hw_cntrs(struct em_hw *hw)
7861 : {
7862 0 : volatile uint32_t temp;
7863 0 : temp = E1000_READ_REG(hw, CRCERRS);
7864 0 : temp = E1000_READ_REG(hw, SYMERRS);
7865 0 : temp = E1000_READ_REG(hw, MPC);
7866 0 : temp = E1000_READ_REG(hw, SCC);
7867 0 : temp = E1000_READ_REG(hw, ECOL);
7868 0 : temp = E1000_READ_REG(hw, MCC);
7869 0 : temp = E1000_READ_REG(hw, LATECOL);
7870 0 : temp = E1000_READ_REG(hw, COLC);
7871 0 : temp = E1000_READ_REG(hw, DC);
7872 0 : temp = E1000_READ_REG(hw, SEC);
7873 0 : temp = E1000_READ_REG(hw, RLEC);
7874 0 : temp = E1000_READ_REG(hw, XONRXC);
7875 0 : temp = E1000_READ_REG(hw, XONTXC);
7876 0 : temp = E1000_READ_REG(hw, XOFFRXC);
7877 0 : temp = E1000_READ_REG(hw, XOFFTXC);
7878 0 : temp = E1000_READ_REG(hw, FCRUC);
7879 :
7880 0 : if (!IS_ICH8(hw->mac_type)) {
7881 0 : temp = E1000_READ_REG(hw, PRC64);
7882 0 : temp = E1000_READ_REG(hw, PRC127);
7883 0 : temp = E1000_READ_REG(hw, PRC255);
7884 0 : temp = E1000_READ_REG(hw, PRC511);
7885 0 : temp = E1000_READ_REG(hw, PRC1023);
7886 0 : temp = E1000_READ_REG(hw, PRC1522);
7887 0 : }
7888 0 : temp = E1000_READ_REG(hw, GPRC);
7889 0 : temp = E1000_READ_REG(hw, BPRC);
7890 0 : temp = E1000_READ_REG(hw, MPRC);
7891 0 : temp = E1000_READ_REG(hw, GPTC);
7892 0 : temp = E1000_READ_REG(hw, GORCL);
7893 0 : temp = E1000_READ_REG(hw, GORCH);
7894 0 : temp = E1000_READ_REG(hw, GOTCL);
7895 0 : temp = E1000_READ_REG(hw, GOTCH);
7896 0 : temp = E1000_READ_REG(hw, RNBC);
7897 0 : temp = E1000_READ_REG(hw, RUC);
7898 0 : temp = E1000_READ_REG(hw, RFC);
7899 0 : temp = E1000_READ_REG(hw, ROC);
7900 0 : temp = E1000_READ_REG(hw, RJC);
7901 0 : temp = E1000_READ_REG(hw, TORL);
7902 0 : temp = E1000_READ_REG(hw, TORH);
7903 0 : temp = E1000_READ_REG(hw, TOTL);
7904 0 : temp = E1000_READ_REG(hw, TOTH);
7905 0 : temp = E1000_READ_REG(hw, TPR);
7906 0 : temp = E1000_READ_REG(hw, TPT);
7907 :
7908 0 : if (!IS_ICH8(hw->mac_type)) {
7909 0 : temp = E1000_READ_REG(hw, PTC64);
7910 0 : temp = E1000_READ_REG(hw, PTC127);
7911 0 : temp = E1000_READ_REG(hw, PTC255);
7912 0 : temp = E1000_READ_REG(hw, PTC511);
7913 0 : temp = E1000_READ_REG(hw, PTC1023);
7914 0 : temp = E1000_READ_REG(hw, PTC1522);
7915 0 : }
7916 0 : temp = E1000_READ_REG(hw, MPTC);
7917 0 : temp = E1000_READ_REG(hw, BPTC);
7918 :
7919 0 : if (hw->mac_type < em_82543)
7920 0 : return;
7921 :
7922 0 : temp = E1000_READ_REG(hw, ALGNERRC);
7923 0 : temp = E1000_READ_REG(hw, RXERRC);
7924 0 : temp = E1000_READ_REG(hw, TNCRS);
7925 0 : temp = E1000_READ_REG(hw, CEXTERR);
7926 0 : temp = E1000_READ_REG(hw, TSCTC);
7927 0 : temp = E1000_READ_REG(hw, TSCTFC);
7928 :
7929 0 : if (hw->mac_type <= em_82544
7930 0 : || hw->mac_type == em_icp_xxxx)
7931 0 : return;
7932 :
7933 0 : temp = E1000_READ_REG(hw, MGTPRC);
7934 0 : temp = E1000_READ_REG(hw, MGTPDC);
7935 0 : temp = E1000_READ_REG(hw, MGTPTC);
7936 :
7937 0 : if (hw->mac_type <= em_82547_rev_2)
7938 0 : return;
7939 :
7940 0 : temp = E1000_READ_REG(hw, IAC);
7941 0 : temp = E1000_READ_REG(hw, ICRXOC);
7942 :
7943 0 : if (hw->phy_type == em_phy_82577 ||
7944 0 : hw->phy_type == em_phy_82578 ||
7945 0 : hw->phy_type == em_phy_82579 ||
7946 0 : hw->phy_type == em_phy_i217) {
7947 0 : uint16_t phy_data;
7948 :
7949 0 : em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
7950 0 : em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
7951 0 : em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
7952 0 : em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
7953 0 : em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
7954 0 : em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
7955 0 : em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
7956 0 : em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
7957 0 : em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
7958 0 : em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
7959 0 : em_read_phy_reg(hw, HV_DC_UPPER, &phy_data);
7960 0 : em_read_phy_reg(hw, HV_DC_LOWER, &phy_data);
7961 0 : em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
7962 0 : em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
7963 0 : }
7964 :
7965 0 : if (hw->mac_type == em_ich8lan ||
7966 0 : hw->mac_type == em_ich9lan ||
7967 0 : hw->mac_type == em_ich10lan ||
7968 0 : hw->mac_type == em_pchlan ||
7969 0 : (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt &&
7970 0 : hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp))
7971 0 : return;
7972 :
7973 0 : temp = E1000_READ_REG(hw, ICRXPTC);
7974 0 : temp = E1000_READ_REG(hw, ICRXATC);
7975 0 : temp = E1000_READ_REG(hw, ICTXPTC);
7976 0 : temp = E1000_READ_REG(hw, ICTXATC);
7977 0 : temp = E1000_READ_REG(hw, ICTXQEC);
7978 0 : temp = E1000_READ_REG(hw, ICTXQMTC);
7979 0 : temp = E1000_READ_REG(hw, ICRXDMTC);
7980 0 : }
7981 :
7982 : #ifndef SMALL_KERNEL
7983 : /******************************************************************************
7984 : * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
7985 : *
7986 : * hw - Struct containing variables accessed by shared code
7987 : * frame_len - The length of the frame in question
7988 : * mac_addr - The Ethernet destination address of the frame in question
7989 : *****************************************************************************/
7990 : void
7991 0 : em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats,
7992 : uint32_t frame_len, uint8_t *mac_addr)
7993 : {
7994 : uint64_t carry_bit;
7995 : /* First adjust the frame length. */
7996 0 : frame_len--;
7997 : /*
7998 : * We need to adjust the statistics counters, since the hardware
7999 : * counters overcount this packet as a CRC error and undercount the
8000 : * packet as a good packet
8001 : */
8002 : /* This packet should not be counted as a CRC error. */
8003 0 : stats->crcerrs--;
8004 : /* This packet does count as a Good Packet Received. */
8005 0 : stats->gprc++;
8006 :
8007 : /* Adjust the Good Octets received counters */
8008 0 : carry_bit = 0x80000000 & stats->gorcl;
8009 0 : stats->gorcl += frame_len;
8010 : /*
8011 : * If the high bit of Gorcl (the low 32 bits of the Good Octets
8012 : * Received Count) was one before the addition, AND it is zero after,
8013 : * then we lost the carry out, need to add one to Gorch (Good Octets
8014 : * Received Count High). This could be simplified if all environments
8015 : * supported 64-bit integers.
8016 : */
8017 0 : if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
8018 0 : stats->gorch++;
8019 : /*
8020 : * Is this a broadcast or multicast? Check broadcast first, since
8021 : * the test for a multicast frame will test positive on a broadcast
8022 : * frame.
8023 : */
8024 0 : if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
8025 : /* Broadcast packet */
8026 0 : stats->bprc++;
8027 0 : else if (*mac_addr & 0x01)
8028 : /* Multicast packet */
8029 0 : stats->mprc++;
8030 :
8031 0 : if (frame_len == hw->max_frame_size) {
8032 : /*
8033 : * In this case, the hardware has overcounted the number of
8034 : * oversize frames.
8035 : */
8036 0 : if (stats->roc > 0)
8037 0 : stats->roc--;
8038 : }
8039 : /*
8040 : * Adjust the bin counters when the extra byte put the frame in the
8041 : * wrong bin. Remember that the frame_len was adjusted above.
8042 : */
8043 0 : if (frame_len == 64) {
8044 0 : stats->prc64++;
8045 0 : stats->prc127--;
8046 0 : } else if (frame_len == 127) {
8047 0 : stats->prc127++;
8048 0 : stats->prc255--;
8049 0 : } else if (frame_len == 255) {
8050 0 : stats->prc255++;
8051 0 : stats->prc511--;
8052 0 : } else if (frame_len == 511) {
8053 0 : stats->prc511++;
8054 0 : stats->prc1023--;
8055 0 : } else if (frame_len == 1023) {
8056 0 : stats->prc1023++;
8057 0 : stats->prc1522--;
8058 0 : } else if (frame_len == 1522) {
8059 0 : stats->prc1522++;
8060 0 : }
8061 0 : }
8062 : #endif /* !SMALL_KERNEL */
8063 :
8064 : /******************************************************************************
8065 : * Gets the current PCI bus type, speed, and width of the hardware
8066 : *
8067 : * hw - Struct containing variables accessed by shared code
8068 : *****************************************************************************/
8069 : void
8070 0 : em_get_bus_info(struct em_hw *hw)
8071 : {
8072 : int32_t ret_val;
8073 0 : uint16_t pci_ex_link_status;
8074 : uint32_t status;
8075 0 : switch (hw->mac_type) {
8076 : case em_82542_rev2_0:
8077 : case em_82542_rev2_1:
8078 0 : hw->bus_type = em_bus_type_unknown;
8079 0 : hw->bus_speed = em_bus_speed_unknown;
8080 0 : hw->bus_width = em_bus_width_unknown;
8081 0 : break;
8082 : case em_icp_xxxx:
8083 0 : hw->bus_type = em_bus_type_cpp;
8084 0 : hw->bus_speed = em_bus_speed_unknown;
8085 0 : hw->bus_width = em_bus_width_unknown;
8086 0 : break;
8087 : case em_82571:
8088 : case em_82572:
8089 : case em_82573:
8090 : case em_82574:
8091 : case em_82575:
8092 : case em_82580:
8093 : case em_80003es2lan:
8094 : case em_i210:
8095 : case em_i350:
8096 0 : hw->bus_type = em_bus_type_pci_express;
8097 0 : hw->bus_speed = em_bus_speed_2500;
8098 0 : ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS,
8099 : &pci_ex_link_status);
8100 0 : if (ret_val)
8101 0 : hw->bus_width = em_bus_width_unknown;
8102 : else
8103 0 : hw->bus_width = (pci_ex_link_status &
8104 0 : PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT;
8105 : break;
8106 : case em_ich8lan:
8107 : case em_ich9lan:
8108 : case em_ich10lan:
8109 : case em_pchlan:
8110 : case em_pch2lan:
8111 : case em_pch_lpt:
8112 : case em_pch_spt:
8113 : case em_pch_cnp:
8114 0 : hw->bus_type = em_bus_type_pci_express;
8115 0 : hw->bus_speed = em_bus_speed_2500;
8116 0 : hw->bus_width = em_bus_width_pciex_1;
8117 0 : break;
8118 : default:
8119 0 : status = E1000_READ_REG(hw, STATUS);
8120 0 : hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
8121 : em_bus_type_pcix : em_bus_type_pci;
8122 :
8123 0 : if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
8124 0 : hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
8125 : em_bus_speed_66 : em_bus_speed_120;
8126 0 : } else if (hw->bus_type == em_bus_type_pci) {
8127 0 : hw->bus_speed = (status & E1000_STATUS_PCI66) ?
8128 : em_bus_speed_66 : em_bus_speed_33;
8129 0 : } else {
8130 0 : switch (status & E1000_STATUS_PCIX_SPEED) {
8131 : case E1000_STATUS_PCIX_SPEED_66:
8132 0 : hw->bus_speed = em_bus_speed_66;
8133 0 : break;
8134 : case E1000_STATUS_PCIX_SPEED_100:
8135 0 : hw->bus_speed = em_bus_speed_100;
8136 0 : break;
8137 : case E1000_STATUS_PCIX_SPEED_133:
8138 0 : hw->bus_speed = em_bus_speed_133;
8139 0 : break;
8140 : default:
8141 0 : hw->bus_speed = em_bus_speed_reserved;
8142 0 : break;
8143 : }
8144 : }
8145 0 : hw->bus_width = (status & E1000_STATUS_BUS64) ?
8146 : em_bus_width_64 : em_bus_width_32;
8147 0 : break;
8148 : }
8149 0 : }
8150 :
8151 : /******************************************************************************
8152 : * Writes a value to one of the devices registers using port I/O (as opposed to
8153 : * memory mapped I/O). Only 82544 and newer devices support port I/O.
8154 : *
8155 : * hw - Struct containing variables accessed by shared code
8156 : * offset - offset to write to
8157 : * value - value to write
8158 : *****************************************************************************/
8159 : STATIC void
8160 0 : em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value)
8161 : {
8162 0 : unsigned long io_addr = hw->io_base;
8163 0 : unsigned long io_data = hw->io_base + 4;
8164 0 : em_io_write(hw, io_addr, offset);
8165 0 : em_io_write(hw, io_data, value);
8166 0 : }
8167 :
8168 : /******************************************************************************
8169 : * Estimates the cable length.
8170 : *
8171 : * hw - Struct containing variables accessed by shared code
8172 : * min_length - The estimated minimum length
8173 : * max_length - The estimated maximum length
8174 : *
8175 : * returns: - E1000_ERR_XXX
8176 : * E1000_SUCCESS
8177 : *
8178 : * This function always returns a ranged length (minimum & maximum).
8179 : * So for M88 phy's, this function interprets the one value returned from the
8180 : * register to the minimum and maximum range.
8181 : * For IGP phy's, the function calculates the range by the AGC registers.
8182 : *****************************************************************************/
8183 : STATIC int32_t
8184 0 : em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
8185 : uint16_t *max_length)
8186 : {
8187 : int32_t ret_val;
8188 : uint16_t agc_value = 0;
8189 0 : uint16_t i, phy_data;
8190 : uint16_t cable_length;
8191 : DEBUGFUNC("em_get_cable_length");
8192 :
8193 0 : *min_length = *max_length = 0;
8194 :
8195 : /* Use old method for Phy older than IGP */
8196 0 : if (hw->phy_type == em_phy_m88 ||
8197 0 : hw->phy_type == em_phy_oem ||
8198 0 : hw->phy_type == em_phy_82578) {
8199 :
8200 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
8201 : &phy_data);
8202 0 : if (ret_val)
8203 0 : return ret_val;
8204 0 : cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
8205 : M88E1000_PSSR_CABLE_LENGTH_SHIFT;
8206 :
8207 : /* Convert the enum value to ranged values */
8208 0 : switch (cable_length) {
8209 : case em_cable_length_50:
8210 0 : *min_length = 0;
8211 0 : *max_length = em_igp_cable_length_50;
8212 0 : break;
8213 : case em_cable_length_50_80:
8214 0 : *min_length = em_igp_cable_length_50;
8215 0 : *max_length = em_igp_cable_length_80;
8216 0 : break;
8217 : case em_cable_length_80_110:
8218 0 : *min_length = em_igp_cable_length_80;
8219 0 : *max_length = em_igp_cable_length_110;
8220 0 : break;
8221 : case em_cable_length_110_140:
8222 0 : *min_length = em_igp_cable_length_110;
8223 0 : *max_length = em_igp_cable_length_140;
8224 0 : break;
8225 : case em_cable_length_140:
8226 0 : *min_length = em_igp_cable_length_140;
8227 0 : *max_length = em_igp_cable_length_170;
8228 0 : break;
8229 : default:
8230 0 : return -E1000_ERR_PHY;
8231 : break;
8232 : }
8233 0 : } else if (hw->phy_type == em_phy_rtl8211) {
8234 : /* no cable length info on RTL8211, fake */
8235 0 : *min_length = 0;
8236 0 : *max_length = em_igp_cable_length_50;
8237 0 : } else if (hw->phy_type == em_phy_gg82563) {
8238 0 : ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
8239 : &phy_data);
8240 0 : if (ret_val)
8241 0 : return ret_val;
8242 0 : cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
8243 :
8244 0 : switch (cable_length) {
8245 : case em_gg_cable_length_60:
8246 0 : *min_length = 0;
8247 0 : *max_length = em_igp_cable_length_60;
8248 0 : break;
8249 : case em_gg_cable_length_60_115:
8250 0 : *min_length = em_igp_cable_length_60;
8251 0 : *max_length = em_igp_cable_length_115;
8252 0 : break;
8253 : case em_gg_cable_length_115_150:
8254 0 : *min_length = em_igp_cable_length_115;
8255 0 : *max_length = em_igp_cable_length_150;
8256 0 : break;
8257 : case em_gg_cable_length_150:
8258 0 : *min_length = em_igp_cable_length_150;
8259 0 : *max_length = em_igp_cable_length_180;
8260 0 : break;
8261 : default:
8262 0 : return -E1000_ERR_PHY;
8263 : break;
8264 : }
8265 0 : } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */
8266 : uint16_t cur_agc_value;
8267 : uint16_t min_agc_value =
8268 : IGP01E1000_AGC_LENGTH_TABLE_SIZE;
8269 0 : uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
8270 : {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B,
8271 : IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D};
8272 :
8273 : /* Read the AGC registers for all channels */
8274 0 : for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
8275 0 : ret_val = em_read_phy_reg(hw, agc_reg_array[i],
8276 : &phy_data);
8277 0 : if (ret_val)
8278 0 : return ret_val;
8279 :
8280 0 : cur_agc_value = phy_data >>
8281 : IGP01E1000_AGC_LENGTH_SHIFT;
8282 :
8283 : /* Value bound check. */
8284 0 : if ((cur_agc_value >=
8285 0 : IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
8286 0 : (cur_agc_value == 0))
8287 0 : return -E1000_ERR_PHY;
8288 :
8289 0 : agc_value += cur_agc_value;
8290 :
8291 : /* Update minimal AGC value. */
8292 0 : if (min_agc_value > cur_agc_value)
8293 0 : min_agc_value = cur_agc_value;
8294 : }
8295 :
8296 : /* Remove the minimal AGC result for length < 50m */
8297 0 : if (agc_value < IGP01E1000_PHY_CHANNEL_NUM *
8298 : em_igp_cable_length_50) {
8299 0 : agc_value -= min_agc_value;
8300 :
8301 : /*
8302 : * Get the average length of the remaining 3 channels
8303 : */
8304 0 : agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
8305 0 : } else {
8306 : /* Get the average length of all the 4 channels. */
8307 0 : agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
8308 : }
8309 :
8310 : /* Set the range of the calculated length. */
8311 0 : *min_length = ((em_igp_cable_length_table[agc_value] -
8312 0 : IGP01E1000_AGC_RANGE) > 0) ?
8313 : (em_igp_cable_length_table[agc_value] -
8314 : IGP01E1000_AGC_RANGE) : 0;
8315 0 : *max_length = em_igp_cable_length_table[agc_value] +
8316 : IGP01E1000_AGC_RANGE;
8317 0 : } else if (hw->phy_type == em_phy_igp_2 ||
8318 0 : hw->phy_type == em_phy_igp_3) {
8319 : uint16_t cur_agc_index, max_agc_index = 0;
8320 : uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
8321 0 : uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
8322 : {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B,
8323 : IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D};
8324 : /* Read the AGC registers for all channels */
8325 0 : for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
8326 0 : ret_val = em_read_phy_reg(hw, agc_reg_array[i],
8327 : &phy_data);
8328 0 : if (ret_val)
8329 0 : return ret_val;
8330 : /*
8331 : * Getting bits 15:9, which represent the combination
8332 : * of course and fine gain values. The result is a
8333 : * number that can be put into the lookup table to
8334 : * obtain the approximate cable length.
8335 : */
8336 0 : cur_agc_index = (phy_data >>
8337 0 : IGP02E1000_AGC_LENGTH_SHIFT) &
8338 : IGP02E1000_AGC_LENGTH_MASK;
8339 :
8340 : /* Array index bound check. */
8341 0 : if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE)
8342 0 : || (cur_agc_index == 0))
8343 0 : return -E1000_ERR_PHY;
8344 :
8345 : /* Remove min & max AGC values from calculation. */
8346 0 : if (em_igp_2_cable_length_table[min_agc_index] >
8347 0 : em_igp_2_cable_length_table[cur_agc_index])
8348 0 : min_agc_index = cur_agc_index;
8349 0 : if (em_igp_2_cable_length_table[max_agc_index] <
8350 0 : em_igp_2_cable_length_table[cur_agc_index])
8351 0 : max_agc_index = cur_agc_index;
8352 :
8353 0 : agc_value += em_igp_2_cable_length_table
8354 : [cur_agc_index];
8355 : }
8356 :
8357 0 : agc_value -= (em_igp_2_cable_length_table[min_agc_index] +
8358 0 : em_igp_2_cable_length_table[max_agc_index]);
8359 0 : agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
8360 : /*
8361 : * Calculate cable length with the error range of +/- 10
8362 : * meters.
8363 : */
8364 0 : *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
8365 : (agc_value - IGP02E1000_AGC_RANGE) : 0;
8366 0 : *max_length = agc_value + IGP02E1000_AGC_RANGE;
8367 0 : }
8368 0 : return E1000_SUCCESS;
8369 0 : }
8370 :
8371 : /******************************************************************************
8372 : * Check if Downshift occured
8373 : *
8374 : * hw - Struct containing variables accessed by shared code
8375 : * downshift - output parameter : 0 - No Downshift ocured.
8376 : * 1 - Downshift ocured.
8377 : *
8378 : * returns: - E1000_ERR_XXX
8379 : * E1000_SUCCESS
8380 : *
8381 : * For phy's older then IGP, this function reads the Downshift bit in the Phy
8382 : * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
8383 : * Link Health register. In IGP this bit is latched high, so the driver must
8384 : * read it immediately after link is established.
8385 : *****************************************************************************/
8386 : STATIC int32_t
8387 0 : em_check_downshift(struct em_hw *hw)
8388 : {
8389 : int32_t ret_val;
8390 0 : uint16_t phy_data;
8391 : DEBUGFUNC("em_check_downshift");
8392 :
8393 0 : if (hw->phy_type == em_phy_igp ||
8394 0 : hw->phy_type == em_phy_igp_3 ||
8395 0 : hw->phy_type == em_phy_igp_2) {
8396 0 : ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
8397 : &phy_data);
8398 0 : if (ret_val)
8399 0 : return ret_val;
8400 :
8401 0 : hw->speed_downgraded = (phy_data &
8402 : IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
8403 0 : } else if ((hw->phy_type == em_phy_m88) ||
8404 0 : (hw->phy_type == em_phy_gg82563) ||
8405 0 : (hw->phy_type == em_phy_oem) ||
8406 0 : (hw->phy_type == em_phy_82578)) {
8407 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
8408 : &phy_data);
8409 0 : if (ret_val)
8410 0 : return ret_val;
8411 :
8412 0 : hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
8413 : M88E1000_PSSR_DOWNSHIFT_SHIFT;
8414 0 : } else if (hw->phy_type == em_phy_ife) {
8415 : /* em_phy_ife supports 10/100 speed only */
8416 0 : hw->speed_downgraded = FALSE;
8417 0 : }
8418 0 : return E1000_SUCCESS;
8419 0 : }
8420 :
8421 : /*****************************************************************************
8422 : *
8423 : * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
8424 : * gigabit link is achieved to improve link quality.
8425 : *
8426 : * hw: Struct containing variables accessed by shared code
8427 : *
8428 : * returns: - E1000_ERR_PHY if fail to read/write the PHY
8429 : * E1000_SUCCESS at any other case.
8430 : *
8431 : ****************************************************************************/
8432 : STATIC int32_t
8433 0 : em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up)
8434 : {
8435 : int32_t ret_val;
8436 0 : uint16_t phy_data, phy_saved_data, speed, duplex, i;
8437 0 : uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
8438 : {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B,
8439 : IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D};
8440 0 : uint16_t min_length, max_length;
8441 : DEBUGFUNC("em_config_dsp_after_link_change");
8442 :
8443 0 : if (hw->phy_type != em_phy_igp)
8444 0 : return E1000_SUCCESS;
8445 :
8446 0 : if (link_up) {
8447 0 : ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
8448 0 : if (ret_val) {
8449 : DEBUGOUT("Error getting link speed and duplex\n");
8450 0 : return ret_val;
8451 : }
8452 0 : if (speed == SPEED_1000) {
8453 :
8454 0 : ret_val = em_get_cable_length(hw, &min_length, &max_length);
8455 0 : if (ret_val)
8456 0 : return ret_val;
8457 :
8458 0 : if ((hw->dsp_config_state == em_dsp_config_enabled) &&
8459 0 : min_length >= em_igp_cable_length_50) {
8460 :
8461 0 : for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM;
8462 0 : i++) {
8463 0 : ret_val = em_read_phy_reg(hw,
8464 0 : dsp_reg_array[i], &phy_data);
8465 0 : if (ret_val)
8466 0 : return ret_val;
8467 :
8468 0 : phy_data &=
8469 : ~IGP01E1000_PHY_EDAC_MU_INDEX;
8470 :
8471 0 : ret_val = em_write_phy_reg(hw,
8472 0 : dsp_reg_array[i], phy_data);
8473 0 : if (ret_val)
8474 0 : return ret_val;
8475 : }
8476 0 : hw->dsp_config_state = em_dsp_config_activated;
8477 0 : }
8478 0 : if ((hw->ffe_config_state == em_ffe_config_enabled) &&
8479 0 : (min_length < em_igp_cable_length_50)) {
8480 :
8481 : uint16_t ffe_idle_err_timeout =
8482 : FFE_IDLE_ERR_COUNT_TIMEOUT_20;
8483 : uint32_t idle_errs = 0;
8484 : /* clear previous idle error counts */
8485 0 : ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
8486 : &phy_data);
8487 0 : if (ret_val)
8488 0 : return ret_val;
8489 :
8490 0 : for (i = 0; i < ffe_idle_err_timeout; i++) {
8491 0 : usec_delay(1000);
8492 0 : ret_val = em_read_phy_reg(hw,
8493 : PHY_1000T_STATUS, &phy_data);
8494 0 : if (ret_val)
8495 0 : return ret_val;
8496 :
8497 0 : idle_errs += (phy_data &
8498 : SR_1000T_IDLE_ERROR_CNT);
8499 0 : if (idle_errs >
8500 : SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
8501 0 : hw->ffe_config_state =
8502 : em_ffe_config_active;
8503 :
8504 0 : ret_val = em_write_phy_reg(hw,
8505 : IGP01E1000_PHY_DSP_FFE,
8506 : IGP01E1000_PHY_DSP_FFE_CM_CP);
8507 0 : if (ret_val)
8508 0 : return ret_val;
8509 : break;
8510 : }
8511 0 : if (idle_errs)
8512 0 : ffe_idle_err_timeout =
8513 : FFE_IDLE_ERR_COUNT_TIMEOUT_100;
8514 : }
8515 0 : }
8516 : }
8517 : } else {
8518 0 : if (hw->dsp_config_state == em_dsp_config_activated) {
8519 : /*
8520 : * Save off the current value of register 0x2F5B to
8521 : * be restored at the end of the routines.
8522 : */
8523 0 : ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
8524 :
8525 0 : if (ret_val)
8526 0 : return ret_val;
8527 :
8528 : /* Disable the PHY transmitter */
8529 0 : ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
8530 :
8531 0 : if (ret_val)
8532 0 : return ret_val;
8533 :
8534 0 : msec_delay_irq(20);
8535 :
8536 0 : ret_val = em_write_phy_reg(hw, 0x0000,
8537 : IGP01E1000_IEEE_FORCE_GIGA);
8538 0 : if (ret_val)
8539 0 : return ret_val;
8540 0 : for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
8541 0 : ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
8542 : &phy_data);
8543 0 : if (ret_val)
8544 0 : return ret_val;
8545 :
8546 0 : phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
8547 0 : phy_data |=
8548 : IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
8549 :
8550 0 : ret_val = em_write_phy_reg(hw,
8551 0 : dsp_reg_array[i], phy_data);
8552 0 : if (ret_val)
8553 0 : return ret_val;
8554 : }
8555 :
8556 0 : ret_val = em_write_phy_reg(hw, 0x0000,
8557 : IGP01E1000_IEEE_RESTART_AUTONEG);
8558 0 : if (ret_val)
8559 0 : return ret_val;
8560 :
8561 0 : msec_delay_irq(20);
8562 :
8563 : /* Now enable the transmitter */
8564 0 : ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
8565 :
8566 0 : if (ret_val)
8567 0 : return ret_val;
8568 :
8569 0 : hw->dsp_config_state = em_dsp_config_enabled;
8570 0 : }
8571 0 : if (hw->ffe_config_state == em_ffe_config_active) {
8572 : /*
8573 : * Save off the current value of register 0x2F5B to
8574 : * be restored at the end of the routines.
8575 : */
8576 0 : ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
8577 :
8578 0 : if (ret_val)
8579 0 : return ret_val;
8580 :
8581 : /* Disable the PHY transmitter */
8582 0 : ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
8583 :
8584 0 : if (ret_val)
8585 0 : return ret_val;
8586 :
8587 0 : msec_delay_irq(20);
8588 :
8589 0 : ret_val = em_write_phy_reg(hw, 0x0000,
8590 : IGP01E1000_IEEE_FORCE_GIGA);
8591 0 : if (ret_val)
8592 0 : return ret_val;
8593 0 : ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
8594 : IGP01E1000_PHY_DSP_FFE_DEFAULT);
8595 0 : if (ret_val)
8596 0 : return ret_val;
8597 :
8598 0 : ret_val = em_write_phy_reg(hw, 0x0000,
8599 : IGP01E1000_IEEE_RESTART_AUTONEG);
8600 0 : if (ret_val)
8601 0 : return ret_val;
8602 :
8603 0 : msec_delay_irq(20);
8604 :
8605 : /* Now enable the transmitter */
8606 0 : ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
8607 :
8608 0 : if (ret_val)
8609 0 : return ret_val;
8610 :
8611 0 : hw->ffe_config_state = em_ffe_config_enabled;
8612 0 : }
8613 : }
8614 0 : return E1000_SUCCESS;
8615 0 : }
8616 :
8617 : /*****************************************************************************
8618 : * Set PHY to class A mode
8619 : * Assumes the following operations will follow to enable the new class mode.
8620 : * 1. Do a PHY soft reset
8621 : * 2. Restart auto-negotiation or force link.
8622 : *
8623 : * hw - Struct containing variables accessed by shared code
8624 : ****************************************************************************/
8625 : static int32_t
8626 0 : em_set_phy_mode(struct em_hw *hw)
8627 : {
8628 : int32_t ret_val;
8629 0 : uint16_t eeprom_data;
8630 : DEBUGFUNC("em_set_phy_mode");
8631 :
8632 0 : if ((hw->mac_type == em_82545_rev_3) &&
8633 0 : (hw->media_type == em_media_type_copper)) {
8634 0 : ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
8635 : &eeprom_data);
8636 0 : if (ret_val) {
8637 0 : return ret_val;
8638 : }
8639 0 : if ((eeprom_data != EEPROM_RESERVED_WORD) &&
8640 0 : (eeprom_data & EEPROM_PHY_CLASS_A)) {
8641 0 : ret_val = em_write_phy_reg(hw,
8642 : M88E1000_PHY_PAGE_SELECT, 0x000B);
8643 0 : if (ret_val)
8644 0 : return ret_val;
8645 0 : ret_val = em_write_phy_reg(hw,
8646 : M88E1000_PHY_GEN_CONTROL, 0x8104);
8647 0 : if (ret_val)
8648 0 : return ret_val;
8649 :
8650 0 : hw->phy_reset_disable = FALSE;
8651 0 : }
8652 : }
8653 0 : return E1000_SUCCESS;
8654 0 : }
8655 :
8656 : /*****************************************************************************
8657 : *
8658 : * This function sets the lplu state according to the active flag. When
8659 : * activating lplu this function also disables smart speed and vise versa.
8660 : * lplu will not be activated unless the device autonegotiation advertisement
8661 : * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
8662 : * hw: Struct containing variables accessed by shared code
8663 : * active - true to enable lplu false to disable lplu.
8664 : *
8665 : * returns: - E1000_ERR_PHY if fail to read/write the PHY
8666 : * E1000_SUCCESS at any other case.
8667 : *
8668 : ****************************************************************************/
8669 : STATIC int32_t
8670 0 : em_set_d3_lplu_state(struct em_hw *hw, boolean_t active)
8671 : {
8672 : uint32_t phy_ctrl = 0;
8673 : int32_t ret_val;
8674 0 : uint16_t phy_data;
8675 : DEBUGFUNC("em_set_d3_lplu_state");
8676 :
8677 0 : if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2
8678 0 : && hw->phy_type != em_phy_igp_3)
8679 0 : return E1000_SUCCESS;
8680 : /*
8681 : * During driver activity LPLU should not be used or it will attain
8682 : * link from the lowest speeds starting from 10Mbps. The capability
8683 : * is used for Dx transitions and states
8684 : */
8685 0 : if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) {
8686 0 : ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
8687 0 : if (ret_val)
8688 0 : return ret_val;
8689 0 : } else if (IS_ICH8(hw->mac_type)) {
8690 : /*
8691 : * MAC writes into PHY register based on the state transition
8692 : * and start auto-negotiation. SW driver can overwrite the
8693 : * settings in CSR PHY power control E1000_PHY_CTRL register.
8694 : */
8695 0 : phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
8696 0 : } else {
8697 0 : ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
8698 : &phy_data);
8699 0 : if (ret_val)
8700 0 : return ret_val;
8701 : }
8702 :
8703 0 : if (!active) {
8704 0 : if (hw->mac_type == em_82541_rev_2 ||
8705 0 : hw->mac_type == em_82547_rev_2) {
8706 0 : phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
8707 0 : ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
8708 : phy_data);
8709 0 : if (ret_val)
8710 0 : return ret_val;
8711 : } else {
8712 0 : if (IS_ICH8(hw->mac_type)) {
8713 0 : phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
8714 0 : E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
8715 0 : } else {
8716 0 : phy_data &= ~IGP02E1000_PM_D3_LPLU;
8717 0 : ret_val = em_write_phy_reg(hw,
8718 : IGP02E1000_PHY_POWER_MGMT, phy_data);
8719 0 : if (ret_val)
8720 0 : return ret_val;
8721 : }
8722 : }
8723 : /*
8724 : * LPLU and SmartSpeed are mutually exclusive. LPLU is used
8725 : * during Dx states where the power conservation is most
8726 : * important. During driver activity we should enable
8727 : * SmartSpeed, so performance is maintained.
8728 : */
8729 0 : if (hw->smart_speed == em_smart_speed_on) {
8730 0 : ret_val = em_read_phy_reg(hw,
8731 : IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8732 0 : if (ret_val)
8733 0 : return ret_val;
8734 :
8735 0 : phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
8736 0 : ret_val = em_write_phy_reg(hw,
8737 : IGP01E1000_PHY_PORT_CONFIG, phy_data);
8738 0 : if (ret_val)
8739 0 : return ret_val;
8740 0 : } else if (hw->smart_speed == em_smart_speed_off) {
8741 0 : ret_val = em_read_phy_reg(hw,
8742 : IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8743 0 : if (ret_val)
8744 0 : return ret_val;
8745 :
8746 0 : phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8747 0 : ret_val = em_write_phy_reg(hw,
8748 : IGP01E1000_PHY_PORT_CONFIG, phy_data);
8749 0 : if (ret_val)
8750 0 : return ret_val;
8751 : }
8752 0 : } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
8753 0 : || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
8754 0 : (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
8755 :
8756 0 : if (hw->mac_type == em_82541_rev_2 ||
8757 0 : hw->mac_type == em_82547_rev_2) {
8758 0 : phy_data |= IGP01E1000_GMII_FLEX_SPD;
8759 0 : ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
8760 : phy_data);
8761 0 : if (ret_val)
8762 0 : return ret_val;
8763 : } else {
8764 0 : if (IS_ICH8(hw->mac_type)) {
8765 0 : phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
8766 0 : E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
8767 0 : } else {
8768 0 : phy_data |= IGP02E1000_PM_D3_LPLU;
8769 0 : ret_val = em_write_phy_reg(hw,
8770 : IGP02E1000_PHY_POWER_MGMT, phy_data);
8771 0 : if (ret_val)
8772 0 : return ret_val;
8773 : }
8774 : }
8775 :
8776 : /* When LPLU is enabled we should disable SmartSpeed */
8777 0 : ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
8778 : &phy_data);
8779 0 : if (ret_val)
8780 0 : return ret_val;
8781 :
8782 0 : phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8783 0 : ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
8784 : phy_data);
8785 0 : if (ret_val)
8786 0 : return ret_val;
8787 :
8788 : }
8789 0 : return E1000_SUCCESS;
8790 0 : }
8791 :
8792 : /*****************************************************************************
8793 : *
8794 : * This function sets the lplu d0 state according to the active flag. When
8795 : * activating lplu this function also disables smart speed and vise versa.
8796 : * lplu will not be activated unless the device autonegotiation advertisement
8797 : * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
8798 : * hw: Struct containing variables accessed by shared code
8799 : * active - true to enable lplu false to disable lplu.
8800 : *
8801 : * returns: - E1000_ERR_PHY if fail to read/write the PHY
8802 : * E1000_SUCCESS at any other case.
8803 : *
8804 : ****************************************************************************/
8805 : STATIC int32_t
8806 0 : em_set_d0_lplu_state(struct em_hw *hw, boolean_t active)
8807 : {
8808 : uint32_t phy_ctrl = 0;
8809 : int32_t ret_val;
8810 0 : uint16_t phy_data;
8811 : DEBUGFUNC("em_set_d0_lplu_state");
8812 :
8813 0 : if (hw->mac_type <= em_82547_rev_2)
8814 0 : return E1000_SUCCESS;
8815 :
8816 0 : if (IS_ICH8(hw->mac_type)) {
8817 0 : phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
8818 0 : } else {
8819 0 : ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
8820 : &phy_data);
8821 0 : if (ret_val)
8822 0 : return ret_val;
8823 : }
8824 :
8825 0 : if (!active) {
8826 0 : if (IS_ICH8(hw->mac_type)) {
8827 0 : phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
8828 0 : E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
8829 0 : } else {
8830 0 : phy_data &= ~IGP02E1000_PM_D0_LPLU;
8831 0 : ret_val = em_write_phy_reg(hw,
8832 : IGP02E1000_PHY_POWER_MGMT, phy_data);
8833 0 : if (ret_val)
8834 0 : return ret_val;
8835 : }
8836 : /*
8837 : * LPLU and SmartSpeed are mutually exclusive. LPLU is used
8838 : * during Dx states where the power conservation is most
8839 : * important. During driver activity we should enable
8840 : * SmartSpeed, so performance is maintained.
8841 : */
8842 0 : if (hw->smart_speed == em_smart_speed_on) {
8843 0 : ret_val = em_read_phy_reg(hw,
8844 : IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8845 0 : if (ret_val)
8846 0 : return ret_val;
8847 :
8848 0 : phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
8849 0 : ret_val = em_write_phy_reg(hw,
8850 : IGP01E1000_PHY_PORT_CONFIG, phy_data);
8851 0 : if (ret_val)
8852 0 : return ret_val;
8853 0 : } else if (hw->smart_speed == em_smart_speed_off) {
8854 0 : ret_val = em_read_phy_reg(hw,
8855 : IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8856 0 : if (ret_val)
8857 0 : return ret_val;
8858 :
8859 0 : phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8860 0 : ret_val = em_write_phy_reg(hw,
8861 : IGP01E1000_PHY_PORT_CONFIG, phy_data);
8862 0 : if (ret_val)
8863 0 : return ret_val;
8864 : }
8865 : } else {
8866 0 : if (IS_ICH8(hw->mac_type)) {
8867 0 : phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
8868 0 : E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
8869 0 : } else {
8870 0 : phy_data |= IGP02E1000_PM_D0_LPLU;
8871 0 : ret_val = em_write_phy_reg(hw,
8872 : IGP02E1000_PHY_POWER_MGMT, phy_data);
8873 0 : if (ret_val)
8874 0 : return ret_val;
8875 : }
8876 :
8877 : /* When LPLU is enabled we should disable SmartSpeed */
8878 0 : ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
8879 : &phy_data);
8880 0 : if (ret_val)
8881 0 : return ret_val;
8882 :
8883 0 : phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8884 0 : ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
8885 : phy_data);
8886 0 : if (ret_val)
8887 0 : return ret_val;
8888 :
8889 : }
8890 0 : return E1000_SUCCESS;
8891 0 : }
8892 :
8893 : /***************************************************************************
8894 : * Set Low Power Link Up state
8895 : *
8896 : * Sets the LPLU state according to the active flag. For PCH, if OEM write
8897 : * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
8898 : * the phy speed. This function will manually set the LPLU bit and restart
8899 : * auto-neg as hw would do. D3 and D0 LPLU will call the same function
8900 : * since it configures the same bit.
8901 : ***************************************************************************/
8902 : int32_t
8903 0 : em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active)
8904 : {
8905 : int32_t ret_val = E1000_SUCCESS;
8906 0 : uint16_t oem_reg;
8907 :
8908 : DEBUGFUNC("e1000_set_lplu_state_pchlan");
8909 :
8910 0 : ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg);
8911 0 : if (ret_val)
8912 : goto out;
8913 :
8914 0 : if (active)
8915 0 : oem_reg |= HV_OEM_BITS_LPLU;
8916 : else
8917 0 : oem_reg &= ~HV_OEM_BITS_LPLU;
8918 :
8919 0 : oem_reg |= HV_OEM_BITS_RESTART_AN;
8920 0 : ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg);
8921 :
8922 : out:
8923 0 : return ret_val;
8924 0 : }
8925 :
8926 : /******************************************************************************
8927 : * Change VCO speed register to improve Bit Error Rate performance of SERDES.
8928 : *
8929 : * hw - Struct containing variables accessed by shared code
8930 : *****************************************************************************/
8931 : static int32_t
8932 0 : em_set_vco_speed(struct em_hw *hw)
8933 : {
8934 : int32_t ret_val;
8935 0 : uint16_t default_page = 0;
8936 0 : uint16_t phy_data;
8937 : DEBUGFUNC("em_set_vco_speed");
8938 :
8939 0 : switch (hw->mac_type) {
8940 : case em_82545_rev_3:
8941 : case em_82546_rev_3:
8942 : break;
8943 : default:
8944 0 : return E1000_SUCCESS;
8945 : }
8946 :
8947 : /* Set PHY register 30, page 5, bit 8 to 0 */
8948 :
8949 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
8950 0 : if (ret_val)
8951 0 : return ret_val;
8952 :
8953 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
8954 0 : if (ret_val)
8955 0 : return ret_val;
8956 :
8957 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8958 0 : if (ret_val)
8959 0 : return ret_val;
8960 :
8961 0 : phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
8962 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8963 0 : if (ret_val)
8964 0 : return ret_val;
8965 :
8966 : /* Set PHY register 30, page 4, bit 11 to 1 */
8967 :
8968 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
8969 0 : if (ret_val)
8970 0 : return ret_val;
8971 :
8972 0 : ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8973 0 : if (ret_val)
8974 0 : return ret_val;
8975 :
8976 0 : phy_data |= M88E1000_PHY_VCO_REG_BIT11;
8977 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8978 0 : if (ret_val)
8979 0 : return ret_val;
8980 :
8981 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
8982 0 : if (ret_val)
8983 0 : return ret_val;
8984 :
8985 0 : return E1000_SUCCESS;
8986 0 : }
8987 :
8988 : /*****************************************************************************
8989 : * This function reads the cookie from ARC ram.
8990 : *
8991 : * returns: - E1000_SUCCESS .
8992 : ****************************************************************************/
8993 : STATIC int32_t
8994 0 : em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer)
8995 : {
8996 : uint8_t i;
8997 : uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
8998 : uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
8999 : length = (length >> 2);
9000 : offset = (offset >> 2);
9001 :
9002 0 : for (i = 0; i < length; i++) {
9003 0 : *((uint32_t *) buffer + i) =
9004 0 : E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
9005 : }
9006 0 : return E1000_SUCCESS;
9007 : }
9008 :
9009 : /*****************************************************************************
9010 : * This function checks whether the HOST IF is enabled for command operaton
9011 : * and also checks whether the previous command is completed.
9012 : * It busy waits in case of previous command is not completed.
9013 : *
9014 : * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
9015 : * timeout
9016 : * - E1000_SUCCESS for success.
9017 : ****************************************************************************/
9018 : STATIC int32_t
9019 0 : em_mng_enable_host_if(struct em_hw *hw)
9020 : {
9021 : uint32_t hicr;
9022 : uint8_t i;
9023 : /* Check that the host interface is enabled. */
9024 0 : hicr = E1000_READ_REG(hw, HICR);
9025 0 : if ((hicr & E1000_HICR_EN) == 0) {
9026 : DEBUGOUT("E1000_HOST_EN bit disabled.\n");
9027 0 : return -E1000_ERR_HOST_INTERFACE_COMMAND;
9028 : }
9029 : /* check the previous command is completed */
9030 0 : for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
9031 0 : hicr = E1000_READ_REG(hw, HICR);
9032 0 : if (!(hicr & E1000_HICR_C))
9033 : break;
9034 0 : msec_delay_irq(1);
9035 : }
9036 :
9037 0 : if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
9038 : DEBUGOUT("Previous command timeout failed .\n");
9039 0 : return -E1000_ERR_HOST_INTERFACE_COMMAND;
9040 : }
9041 0 : return E1000_SUCCESS;
9042 0 : }
9043 :
9044 : /*****************************************************************************
9045 : * This function checks the mode of the firmware.
9046 : *
9047 : * returns - TRUE when the mode is IAMT or FALSE.
9048 : ****************************************************************************/
9049 : boolean_t
9050 0 : em_check_mng_mode(struct em_hw *hw)
9051 : {
9052 : uint32_t fwsm;
9053 0 : fwsm = E1000_READ_REG(hw, FWSM);
9054 :
9055 0 : if (IS_ICH8(hw->mac_type)) {
9056 0 : if ((fwsm & E1000_FWSM_MODE_MASK) ==
9057 : (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
9058 0 : return TRUE;
9059 0 : } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
9060 : (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
9061 0 : return TRUE;
9062 :
9063 0 : return FALSE;
9064 0 : }
9065 :
9066 : /*****************************************************************************
9067 : * This function calculates the checksum.
9068 : *
9069 : * returns - checksum of buffer contents.
9070 : ****************************************************************************/
9071 : STATIC uint8_t
9072 0 : em_calculate_mng_checksum(char *buffer, uint32_t length)
9073 : {
9074 : uint8_t sum = 0;
9075 : uint32_t i;
9076 0 : if (!buffer)
9077 0 : return 0;
9078 :
9079 0 : for (i = 0; i < length; i++)
9080 0 : sum += buffer[i];
9081 :
9082 0 : return (uint8_t) (0 - sum);
9083 0 : }
9084 :
9085 : /*****************************************************************************
9086 : * This function checks whether tx pkt filtering needs to be enabled or not.
9087 : *
9088 : * returns - TRUE for packet filtering or FALSE.
9089 : ****************************************************************************/
9090 : boolean_t
9091 0 : em_enable_tx_pkt_filtering(struct em_hw *hw)
9092 : {
9093 : /* called in init as well as watchdog timer functions */
9094 : int32_t ret_val, checksum;
9095 : boolean_t tx_filter = FALSE;
9096 0 : struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
9097 0 : uint8_t *buffer = (uint8_t *) & (hw->mng_cookie);
9098 0 : if (em_check_mng_mode(hw)) {
9099 0 : ret_val = em_mng_enable_host_if(hw);
9100 0 : if (ret_val == E1000_SUCCESS) {
9101 0 : ret_val = em_host_if_read_cookie(hw, buffer);
9102 0 : if (ret_val == E1000_SUCCESS) {
9103 0 : checksum = hdr->checksum;
9104 0 : hdr->checksum = 0;
9105 0 : if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
9106 0 : checksum == em_calculate_mng_checksum(
9107 : (char *) buffer,
9108 : E1000_MNG_DHCP_COOKIE_LENGTH)) {
9109 0 : if (hdr->status &
9110 : E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
9111 0 : tx_filter = TRUE;
9112 : } else
9113 : tx_filter = TRUE;
9114 : } else
9115 : tx_filter = TRUE;
9116 : }
9117 : }
9118 0 : hw->tx_pkt_filtering = tx_filter;
9119 0 : return tx_filter;
9120 : }
9121 :
9122 : static int32_t
9123 0 : em_polarity_reversal_workaround(struct em_hw *hw)
9124 : {
9125 : int32_t ret_val;
9126 0 : uint16_t mii_status_reg;
9127 : uint16_t i;
9128 : /* Polarity reversal workaround for forced 10F/10H links. */
9129 :
9130 : /* Disable the transmitter on the PHY */
9131 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
9132 0 : if (ret_val)
9133 0 : return ret_val;
9134 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
9135 0 : if (ret_val)
9136 0 : return ret_val;
9137 :
9138 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
9139 0 : if (ret_val)
9140 0 : return ret_val;
9141 :
9142 : /* This loop will early-out if the NO link condition has been met. */
9143 0 : for (i = PHY_FORCE_TIME; i > 0; i--) {
9144 : /*
9145 : * Read the MII Status Register and wait for Link Status bit
9146 : * to be clear.
9147 : */
9148 :
9149 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9150 0 : if (ret_val)
9151 0 : return ret_val;
9152 :
9153 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9154 0 : if (ret_val)
9155 0 : return ret_val;
9156 :
9157 0 : if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
9158 : break;
9159 0 : msec_delay_irq(100);
9160 : }
9161 :
9162 : /* Recommended delay time after link has been lost */
9163 0 : msec_delay_irq(1000);
9164 :
9165 : /* Now we will re-enable the transmitter on the PHY */
9166 :
9167 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
9168 0 : if (ret_val)
9169 0 : return ret_val;
9170 0 : msec_delay_irq(50);
9171 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
9172 0 : if (ret_val)
9173 0 : return ret_val;
9174 0 : msec_delay_irq(50);
9175 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
9176 0 : if (ret_val)
9177 0 : return ret_val;
9178 0 : msec_delay_irq(50);
9179 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
9180 0 : if (ret_val)
9181 0 : return ret_val;
9182 :
9183 0 : ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
9184 0 : if (ret_val)
9185 0 : return ret_val;
9186 :
9187 : /* This loop will early-out if the link condition has been met. */
9188 0 : for (i = PHY_FORCE_TIME; i > 0; i--) {
9189 : /*
9190 : * Read the MII Status Register and wait for Link Status bit
9191 : * to be set.
9192 : */
9193 :
9194 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9195 0 : if (ret_val)
9196 0 : return ret_val;
9197 :
9198 0 : ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9199 0 : if (ret_val)
9200 0 : return ret_val;
9201 :
9202 0 : if (mii_status_reg & MII_SR_LINK_STATUS)
9203 : break;
9204 0 : msec_delay_irq(100);
9205 : }
9206 0 : return E1000_SUCCESS;
9207 0 : }
9208 :
9209 : /******************************************************************************
9210 : *
9211 : * Disables PCI-Express master access.
9212 : *
9213 : * hw: Struct containing variables accessed by shared code
9214 : *
9215 : * returns: - none.
9216 : *
9217 : *****************************************************************************/
9218 : STATIC void
9219 0 : em_set_pci_express_master_disable(struct em_hw *hw)
9220 : {
9221 : uint32_t ctrl;
9222 : DEBUGFUNC("em_set_pci_express_master_disable");
9223 :
9224 0 : if (hw->bus_type != em_bus_type_pci_express)
9225 0 : return;
9226 :
9227 0 : ctrl = E1000_READ_REG(hw, CTRL);
9228 0 : ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
9229 0 : E1000_WRITE_REG(hw, CTRL, ctrl);
9230 0 : }
9231 :
9232 : /******************************************************************************
9233 : *
9234 : * Disables PCI-Express master access and verifies there are no pending
9235 : * requests
9236 : *
9237 : * hw: Struct containing variables accessed by shared code
9238 : *
9239 : * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
9240 : * caused the master requests to be disabled.
9241 : * E1000_SUCCESS master requests disabled.
9242 : *
9243 : ******************************************************************************/
9244 : int32_t
9245 0 : em_disable_pciex_master(struct em_hw *hw)
9246 : {
9247 : int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
9248 : DEBUGFUNC("em_disable_pciex_master");
9249 :
9250 0 : if (hw->bus_type != em_bus_type_pci_express)
9251 0 : return E1000_SUCCESS;
9252 :
9253 0 : em_set_pci_express_master_disable(hw);
9254 :
9255 0 : while (timeout) {
9256 0 : if (!(E1000_READ_REG(hw, STATUS) &
9257 : E1000_STATUS_GIO_MASTER_ENABLE))
9258 : break;
9259 : else
9260 0 : usec_delay(100);
9261 0 : timeout--;
9262 : }
9263 :
9264 0 : if (!timeout) {
9265 : DEBUGOUT("Master requests are pending.\n");
9266 0 : return -E1000_ERR_MASTER_REQUESTS_PENDING;
9267 : }
9268 0 : return E1000_SUCCESS;
9269 0 : }
9270 :
9271 : /******************************************************************************
9272 : *
9273 : * Check for EEPROM Auto Read bit done.
9274 : *
9275 : * hw: Struct containing variables accessed by shared code
9276 : *
9277 : * returns: - E1000_ERR_RESET if fail to reset MAC
9278 : * E1000_SUCCESS at any other case.
9279 : *
9280 : ******************************************************************************/
9281 : STATIC int32_t
9282 0 : em_get_auto_rd_done(struct em_hw *hw)
9283 : {
9284 : int32_t timeout = AUTO_READ_DONE_TIMEOUT;
9285 : DEBUGFUNC("em_get_auto_rd_done");
9286 :
9287 0 : switch (hw->mac_type) {
9288 : default:
9289 0 : msec_delay(5);
9290 0 : break;
9291 : case em_82571:
9292 : case em_82572:
9293 : case em_82573:
9294 : case em_82574:
9295 : case em_82575:
9296 : case em_82580:
9297 : case em_80003es2lan:
9298 : case em_i210:
9299 : case em_i350:
9300 : case em_ich8lan:
9301 : case em_ich9lan:
9302 : case em_ich10lan:
9303 : case em_pchlan:
9304 : case em_pch2lan:
9305 : case em_pch_lpt:
9306 : case em_pch_spt:
9307 : case em_pch_cnp:
9308 0 : while (timeout) {
9309 0 : if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
9310 : break;
9311 : else
9312 0 : msec_delay(1);
9313 0 : timeout--;
9314 : }
9315 :
9316 0 : if (!timeout) {
9317 : DEBUGOUT("Auto read by HW from EEPROM has not"
9318 : " completed.\n");
9319 0 : return -E1000_ERR_RESET;
9320 : }
9321 : break;
9322 : }
9323 : /*
9324 : * PHY configuration from NVM just starts after EECD_AUTO_RD sets to
9325 : * high. Need to wait for PHY configuration completion before
9326 : * accessing NVM and PHY.
9327 : */
9328 0 : if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574))
9329 0 : msec_delay(25);
9330 :
9331 0 : return E1000_SUCCESS;
9332 0 : }
9333 :
9334 : /***************************************************************************
9335 : * Checks if the PHY configuration is done
9336 : *
9337 : * hw: Struct containing variables accessed by shared code
9338 : *
9339 : * returns: - E1000_ERR_RESET if fail to reset MAC
9340 : * E1000_SUCCESS at any other case.
9341 : *
9342 : ***************************************************************************/
9343 : STATIC int32_t
9344 0 : em_get_phy_cfg_done(struct em_hw *hw)
9345 : {
9346 : int32_t timeout = PHY_CFG_TIMEOUT;
9347 : uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0;
9348 : DEBUGFUNC("em_get_phy_cfg_done");
9349 :
9350 0 : switch (hw->mac_type) {
9351 : default:
9352 0 : msec_delay_irq(10);
9353 0 : break;
9354 : case em_80003es2lan:
9355 : case em_82575:
9356 : case em_82580:
9357 : case em_i350:
9358 0 : switch (hw->bus_func) {
9359 : case 1:
9360 : cfg_mask = E1000_NVM_CFG_DONE_PORT_1;
9361 0 : break;
9362 : case 2:
9363 : cfg_mask = E1000_NVM_CFG_DONE_PORT_2;
9364 0 : break;
9365 : case 3:
9366 : cfg_mask = E1000_NVM_CFG_DONE_PORT_3;
9367 0 : break;
9368 : }
9369 : /* FALLTHROUGH */
9370 : case em_82571:
9371 : case em_82572:
9372 0 : while (timeout) {
9373 0 : if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
9374 : break;
9375 : else
9376 0 : msec_delay(1);
9377 0 : timeout--;
9378 : }
9379 : if (!timeout) {
9380 : DEBUGOUT("MNG configuration cycle has not completed."
9381 : "\n");
9382 : }
9383 0 : break;
9384 : }
9385 :
9386 0 : return E1000_SUCCESS;
9387 : }
9388 :
9389 : /***************************************************************************
9390 : *
9391 : * Using the combination of SMBI and SWESMBI semaphore bits when resetting
9392 : * adapter or Eeprom access.
9393 : *
9394 : * hw: Struct containing variables accessed by shared code
9395 : *
9396 : * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
9397 : * E1000_SUCCESS at any other case.
9398 : *
9399 : ***************************************************************************/
9400 : STATIC int32_t
9401 0 : em_get_hw_eeprom_semaphore(struct em_hw *hw)
9402 : {
9403 : int32_t timeout;
9404 : uint32_t swsm;
9405 : DEBUGFUNC("em_get_hw_eeprom_semaphore");
9406 :
9407 0 : if (!hw->eeprom_semaphore_present)
9408 0 : return E1000_SUCCESS;
9409 :
9410 0 : if (hw->mac_type == em_80003es2lan) {
9411 : /* Get the SW semaphore. */
9412 0 : if (em_get_software_semaphore(hw) != E1000_SUCCESS)
9413 0 : return -E1000_ERR_EEPROM;
9414 : }
9415 : /* Get the FW semaphore. */
9416 0 : timeout = hw->eeprom.word_size + 1;
9417 0 : while (timeout) {
9418 0 : swsm = E1000_READ_REG(hw, SWSM);
9419 0 : swsm |= E1000_SWSM_SWESMBI;
9420 0 : E1000_WRITE_REG(hw, SWSM, swsm);
9421 : /* if we managed to set the bit we got the semaphore. */
9422 0 : swsm = E1000_READ_REG(hw, SWSM);
9423 0 : if (swsm & E1000_SWSM_SWESMBI)
9424 : break;
9425 :
9426 0 : usec_delay(50);
9427 0 : timeout--;
9428 : }
9429 :
9430 0 : if (!timeout) {
9431 : /* Release semaphores */
9432 0 : em_put_hw_eeprom_semaphore(hw);
9433 : DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set."
9434 : "\n");
9435 0 : return -E1000_ERR_EEPROM;
9436 : }
9437 0 : return E1000_SUCCESS;
9438 0 : }
9439 :
9440 : /***************************************************************************
9441 : * This function clears HW semaphore bits.
9442 : *
9443 : * hw: Struct containing variables accessed by shared code
9444 : *
9445 : * returns: - None.
9446 : *
9447 : ***************************************************************************/
9448 : STATIC void
9449 0 : em_put_hw_eeprom_semaphore(struct em_hw *hw)
9450 : {
9451 : uint32_t swsm;
9452 : DEBUGFUNC("em_put_hw_eeprom_semaphore");
9453 :
9454 0 : if (!hw->eeprom_semaphore_present)
9455 0 : return;
9456 :
9457 0 : swsm = E1000_READ_REG(hw, SWSM);
9458 0 : if (hw->mac_type == em_80003es2lan) {
9459 : /* Release both semaphores. */
9460 0 : swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
9461 0 : } else
9462 0 : swsm &= ~(E1000_SWSM_SWESMBI);
9463 0 : E1000_WRITE_REG(hw, SWSM, swsm);
9464 0 : }
9465 :
9466 : /***************************************************************************
9467 : *
9468 : * Obtaining software semaphore bit (SMBI) before resetting PHY.
9469 : *
9470 : * hw: Struct containing variables accessed by shared code
9471 : *
9472 : * returns: - E1000_ERR_RESET if fail to obtain semaphore.
9473 : * E1000_SUCCESS at any other case.
9474 : *
9475 : ***************************************************************************/
9476 : STATIC int32_t
9477 0 : em_get_software_semaphore(struct em_hw *hw)
9478 : {
9479 0 : int32_t timeout = hw->eeprom.word_size + 1;
9480 : uint32_t swsm;
9481 : DEBUGFUNC("em_get_software_semaphore");
9482 :
9483 0 : if (hw->mac_type != em_80003es2lan)
9484 0 : return E1000_SUCCESS;
9485 :
9486 0 : while (timeout) {
9487 0 : swsm = E1000_READ_REG(hw, SWSM);
9488 : /*
9489 : * If SMBI bit cleared, it is now set and we hold the
9490 : * semaphore
9491 : */
9492 0 : if (!(swsm & E1000_SWSM_SMBI))
9493 : break;
9494 0 : msec_delay_irq(1);
9495 0 : timeout--;
9496 : }
9497 :
9498 0 : if (!timeout) {
9499 : DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
9500 0 : return -E1000_ERR_RESET;
9501 : }
9502 0 : return E1000_SUCCESS;
9503 0 : }
9504 :
9505 : /***************************************************************************
9506 : *
9507 : * Release semaphore bit (SMBI).
9508 : *
9509 : * hw: Struct containing variables accessed by shared code
9510 : *
9511 : ***************************************************************************/
9512 : STATIC void
9513 0 : em_release_software_semaphore(struct em_hw *hw)
9514 : {
9515 : uint32_t swsm;
9516 : DEBUGFUNC("em_release_software_semaphore");
9517 :
9518 0 : if (hw->mac_type != em_80003es2lan)
9519 0 : return;
9520 :
9521 0 : swsm = E1000_READ_REG(hw, SWSM);
9522 : /* Release the SW semaphores. */
9523 0 : swsm &= ~E1000_SWSM_SMBI;
9524 0 : E1000_WRITE_REG(hw, SWSM, swsm);
9525 0 : }
9526 :
9527 : /******************************************************************************
9528 : * Checks if PHY reset is blocked due to SOL/IDER session, for example.
9529 : * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
9530 : * the caller to figure out how to deal with it.
9531 : *
9532 : * hw - Struct containing variables accessed by shared code
9533 : *
9534 : * returns: - E1000_BLK_PHY_RESET
9535 : * E1000_SUCCESS
9536 : *
9537 : *****************************************************************************/
9538 : int32_t
9539 0 : em_check_phy_reset_block(struct em_hw *hw)
9540 : {
9541 : uint32_t manc = 0;
9542 : uint32_t fwsm = 0;
9543 : DEBUGFUNC("em_check_phy_reset_block\n");
9544 :
9545 0 : if (IS_ICH8(hw->mac_type)) {
9546 : int i = 0;
9547 : int blocked = 0;
9548 0 : do {
9549 0 : fwsm = E1000_READ_REG(hw, FWSM);
9550 0 : if (!(fwsm & E1000_FWSM_RSPCIPHY)) {
9551 : blocked = 1;
9552 0 : msec_delay(10);
9553 0 : continue;
9554 : }
9555 : blocked = 0;
9556 0 : } while (blocked && (i++ < 30));
9557 0 : return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
9558 : }
9559 0 : if (hw->mac_type > em_82547_rev_2)
9560 0 : manc = E1000_READ_REG(hw, MANC);
9561 0 : return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
9562 : E1000_BLK_PHY_RESET : E1000_SUCCESS;
9563 0 : }
9564 :
9565 : /******************************************************************************
9566 : * Configure PCI-Ex no-snoop
9567 : *
9568 : * hw - Struct containing variables accessed by shared code.
9569 : * no_snoop - Bitmap of no-snoop events.
9570 : *
9571 : * returns: E1000_SUCCESS
9572 : *
9573 : *****************************************************************************/
9574 : STATIC int32_t
9575 0 : em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop)
9576 : {
9577 : uint32_t gcr_reg = 0;
9578 : DEBUGFUNC("em_set_pci_ex_no_snoop");
9579 :
9580 0 : if (hw->bus_type == em_bus_type_unknown)
9581 0 : em_get_bus_info(hw);
9582 :
9583 0 : if (hw->bus_type != em_bus_type_pci_express)
9584 0 : return E1000_SUCCESS;
9585 :
9586 0 : if (no_snoop) {
9587 0 : gcr_reg = E1000_READ_REG(hw, GCR);
9588 0 : gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
9589 0 : gcr_reg |= no_snoop;
9590 0 : E1000_WRITE_REG(hw, GCR, gcr_reg);
9591 0 : }
9592 0 : if (IS_ICH8(hw->mac_type)) {
9593 : uint32_t ctrl_ext;
9594 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
9595 0 : ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
9596 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
9597 0 : }
9598 0 : return E1000_SUCCESS;
9599 0 : }
9600 :
9601 : /***************************************************************************
9602 : *
9603 : * Get software semaphore FLAG bit (SWFLAG).
9604 : * SWFLAG is used to synchronize the access to all shared resource between
9605 : * SW, FW and HW.
9606 : *
9607 : * hw: Struct containing variables accessed by shared code
9608 : *
9609 : ***************************************************************************/
9610 : STATIC int32_t
9611 0 : em_get_software_flag(struct em_hw *hw)
9612 : {
9613 : int32_t timeout = PHY_CFG_TIMEOUT;
9614 : uint32_t extcnf_ctrl;
9615 : DEBUGFUNC("em_get_software_flag");
9616 :
9617 0 : if (IS_ICH8(hw->mac_type)) {
9618 0 : if (hw->sw_flag) {
9619 0 : hw->sw_flag++;
9620 0 : return E1000_SUCCESS;
9621 : }
9622 0 : while (timeout) {
9623 0 : extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
9624 0 : if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
9625 : break;
9626 0 : msec_delay_irq(1);
9627 0 : timeout--;
9628 : }
9629 0 : if (!timeout) {
9630 0 : printf("%s: SW has already locked the resource?\n",
9631 : __func__);
9632 0 : return -E1000_ERR_CONFIG;
9633 : }
9634 : timeout = SW_FLAG_TIMEOUT;
9635 0 : extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
9636 0 : E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
9637 :
9638 0 : while (timeout) {
9639 0 : extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
9640 0 : if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
9641 : break;
9642 0 : msec_delay_irq(1);
9643 0 : timeout--;
9644 : }
9645 :
9646 0 : if (!timeout) {
9647 0 : printf("Failed to acquire the semaphore, FW or HW "
9648 : "has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
9649 0 : E1000_READ_REG(hw, FWSM), extcnf_ctrl);
9650 0 : extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
9651 0 : E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
9652 0 : return -E1000_ERR_CONFIG;
9653 : }
9654 : }
9655 0 : hw->sw_flag++;
9656 0 : return E1000_SUCCESS;
9657 0 : }
9658 :
9659 : /***************************************************************************
9660 : *
9661 : * Release software semaphore FLAG bit (SWFLAG).
9662 : * SWFLAG is used to synchronize the access to all shared resource between
9663 : * SW, FW and HW.
9664 : *
9665 : * hw: Struct containing variables accessed by shared code
9666 : *
9667 : ***************************************************************************/
9668 : STATIC void
9669 0 : em_release_software_flag(struct em_hw *hw)
9670 : {
9671 : uint32_t extcnf_ctrl;
9672 : DEBUGFUNC("em_release_software_flag");
9673 :
9674 0 : if (IS_ICH8(hw->mac_type)) {
9675 0 : KASSERT(hw->sw_flag > 0);
9676 0 : if (--hw->sw_flag > 0)
9677 0 : return;
9678 0 : extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
9679 0 : extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
9680 0 : E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
9681 0 : }
9682 0 : return;
9683 0 : }
9684 :
9685 : /**
9686 : * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
9687 : * @hw: pointer to the HW structure
9688 : * @bank: pointer to the variable that returns the active bank
9689 : *
9690 : * Reads signature byte from the NVM using the flash access registers.
9691 : * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
9692 : **/
9693 : int32_t
9694 0 : em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank)
9695 : {
9696 : uint32_t eecd;
9697 0 : uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t);
9698 : uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
9699 0 : uint32_t nvm_dword = 0;
9700 0 : uint8_t sig_byte = 0;
9701 : int32_t ret_val;
9702 :
9703 : DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan");
9704 :
9705 0 : switch (hw->mac_type) {
9706 : case em_pch_spt:
9707 : case em_pch_cnp:
9708 0 : bank1_offset = hw->flash_bank_size * 2;
9709 : act_offset = E1000_ICH_NVM_SIG_WORD * 2;
9710 :
9711 : /* set bank to 0 in case flash read fails. */
9712 0 : *bank = 0;
9713 :
9714 : /* Check bank 0 */
9715 0 : ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword);
9716 0 : if (ret_val)
9717 0 : return ret_val;
9718 0 : sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
9719 0 : if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
9720 : E1000_ICH_NVM_SIG_VALUE) {
9721 0 : *bank = 0;
9722 0 : return 0;
9723 : }
9724 :
9725 : /* Check bank 1 */
9726 0 : ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset,
9727 : &nvm_dword);
9728 0 : if (ret_val)
9729 0 : return ret_val;
9730 0 : sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
9731 0 : if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
9732 : E1000_ICH_NVM_SIG_VALUE) {
9733 0 : *bank = 1;
9734 0 : return 0;
9735 : }
9736 :
9737 : DEBUGOUT("ERROR: No valid NVM bank present\n");
9738 0 : return -1;
9739 : case em_ich8lan:
9740 : case em_ich9lan:
9741 0 : eecd = E1000_READ_REG(hw, EECD);
9742 0 : if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
9743 : E1000_EECD_SEC1VAL_VALID_MASK) {
9744 0 : if (eecd & E1000_EECD_SEC1VAL)
9745 0 : *bank = 1;
9746 : else
9747 0 : *bank = 0;
9748 :
9749 0 : return E1000_SUCCESS;
9750 : }
9751 : DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
9752 : /* fall-thru */
9753 : default:
9754 : /* set bank to 0 in case flash read fails */
9755 0 : *bank = 0;
9756 :
9757 : /* Check bank 0 */
9758 0 : ret_val = em_read_ich8_byte(hw, act_offset,
9759 : &sig_byte);
9760 0 : if (ret_val)
9761 0 : return ret_val;
9762 0 : if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
9763 : E1000_ICH_NVM_SIG_VALUE) {
9764 0 : *bank = 0;
9765 0 : return E1000_SUCCESS;
9766 : }
9767 :
9768 : /* Check bank 1 */
9769 0 : ret_val = em_read_ich8_byte(hw, act_offset +
9770 : bank1_offset,
9771 : &sig_byte);
9772 0 : if (ret_val)
9773 0 : return ret_val;
9774 0 : if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
9775 : E1000_ICH_NVM_SIG_VALUE) {
9776 0 : *bank = 1;
9777 0 : return E1000_SUCCESS;
9778 : }
9779 :
9780 : DEBUGOUT("ERROR: No valid NVM bank present\n");
9781 0 : return -1;
9782 : }
9783 0 : }
9784 :
9785 : STATIC int32_t
9786 0 : em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words,
9787 : uint16_t *data)
9788 : {
9789 : int32_t error = E1000_SUCCESS;
9790 0 : uint32_t flash_bank = 0;
9791 : uint32_t act_offset = 0;
9792 : uint32_t bank_offset = 0;
9793 0 : uint32_t dword = 0;
9794 : uint16_t i = 0, add;
9795 :
9796 : /*
9797 : * We need to know which is the valid flash bank. In the event that
9798 : * we didn't allocate eeprom_shadow_ram, we may not be managing
9799 : * flash_bank. So it cannot be trusted and needs to be updated with
9800 : * each read.
9801 : */
9802 :
9803 0 : if (hw->mac_type < em_pch_spt)
9804 0 : return -E1000_ERR_EEPROM;
9805 :
9806 0 : error = em_get_software_flag(hw);
9807 0 : if (error != E1000_SUCCESS)
9808 0 : return error;
9809 :
9810 0 : error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank);
9811 0 : if (error != E1000_SUCCESS) {
9812 : DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
9813 0 : flash_bank = 0;
9814 0 : }
9815 :
9816 : /*
9817 : * Adjust offset appropriately if we're on bank 1 - adjust for word
9818 : * size
9819 : */
9820 0 : bank_offset = flash_bank * (hw->flash_bank_size * 2);
9821 :
9822 0 : for (i = add = 0; i < words; i += add) {
9823 0 : if ((offset + i) % 2) {
9824 : add = 1;
9825 0 : if (hw->eeprom_shadow_ram != NULL
9826 0 : && hw->eeprom_shadow_ram[offset + i].modified) {
9827 0 : data[i] =
9828 0 : hw->eeprom_shadow_ram[offset+i].eeprom_word;
9829 0 : continue;
9830 : }
9831 0 : act_offset = bank_offset + (offset + i - 1) * 2;
9832 0 : } else {
9833 : add = 2;
9834 0 : if (hw->eeprom_shadow_ram != NULL
9835 0 : && hw->eeprom_shadow_ram[offset+i].modified
9836 0 : && hw->eeprom_shadow_ram[offset+i+1].modified) {
9837 0 : data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
9838 0 : data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word;
9839 0 : continue;
9840 : }
9841 0 : act_offset = bank_offset + (offset + i) * 2;
9842 : }
9843 0 : error = em_read_ich8_dword(hw, act_offset, &dword);
9844 0 : if (error != E1000_SUCCESS)
9845 : break;
9846 0 : if (hw->eeprom_shadow_ram != NULL
9847 0 : && hw->eeprom_shadow_ram[offset+i].modified) {
9848 0 : data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
9849 0 : } else {
9850 0 : if (add == 1)
9851 0 : data[i] = dword >> 16;
9852 : else
9853 0 : data[i] = dword & 0xFFFFUL;
9854 : }
9855 0 : if (add == 1 || words-i == 1)
9856 : continue;
9857 0 : if (hw->eeprom_shadow_ram != NULL
9858 0 : && hw->eeprom_shadow_ram[offset+i+1].modified) {
9859 0 : data[i+1] =
9860 0 : hw->eeprom_shadow_ram[offset+i+1].eeprom_word;
9861 0 : } else {
9862 0 : data[i+1] = dword >> 16;
9863 : }
9864 : }
9865 :
9866 0 : em_release_software_flag(hw);
9867 :
9868 0 : return error;
9869 0 : }
9870 :
9871 : /******************************************************************************
9872 : * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
9873 : * register.
9874 : *
9875 : * hw - Struct containing variables accessed by shared code
9876 : * offset - offset of word in the EEPROM to read
9877 : * data - word read from the EEPROM
9878 : * words - number of words to read
9879 : *****************************************************************************/
9880 : STATIC int32_t
9881 0 : em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
9882 : uint16_t *data)
9883 : {
9884 : int32_t error = E1000_SUCCESS;
9885 0 : uint32_t flash_bank = 0;
9886 : uint32_t act_offset = 0;
9887 : uint32_t bank_offset = 0;
9888 0 : uint16_t word = 0;
9889 : uint16_t i = 0;
9890 : /*
9891 : * We need to know which is the valid flash bank. In the event that
9892 : * we didn't allocate eeprom_shadow_ram, we may not be managing
9893 : * flash_bank. So it cannot be trusted and needs to be updated with
9894 : * each read.
9895 : */
9896 :
9897 0 : if (hw->mac_type >= em_pch_spt)
9898 0 : return em_read_eeprom_spt(hw, offset, words, data);
9899 :
9900 0 : error = em_get_software_flag(hw);
9901 0 : if (error != E1000_SUCCESS)
9902 0 : return error;
9903 :
9904 0 : error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank);
9905 0 : if (error != E1000_SUCCESS) {
9906 : DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
9907 0 : flash_bank = 0;
9908 0 : }
9909 :
9910 : /*
9911 : * Adjust offset appropriately if we're on bank 1 - adjust for word
9912 : * size
9913 : */
9914 0 : bank_offset = flash_bank * (hw->flash_bank_size * 2);
9915 :
9916 0 : for (i = 0; i < words; i++) {
9917 0 : if (hw->eeprom_shadow_ram != NULL &&
9918 0 : hw->eeprom_shadow_ram[offset + i].modified == TRUE) {
9919 0 : data[i] =
9920 0 : hw->eeprom_shadow_ram[offset + i].eeprom_word;
9921 0 : } else {
9922 : /* The NVM part needs a byte offset, hence * 2 */
9923 0 : act_offset = bank_offset + ((offset + i) * 2);
9924 0 : error = em_read_ich8_word(hw, act_offset, &word);
9925 0 : if (error != E1000_SUCCESS)
9926 : break;
9927 0 : data[i] = word;
9928 : }
9929 : }
9930 :
9931 0 : em_release_software_flag(hw);
9932 :
9933 0 : return error;
9934 0 : }
9935 :
9936 : /******************************************************************************
9937 : * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
9938 : * register. Actually, writes are written to the shadow ram cache in the hw
9939 : * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to
9940 : * the NVM, which occurs when the NVM checksum is updated.
9941 : *
9942 : * hw - Struct containing variables accessed by shared code
9943 : * offset - offset of word in the EEPROM to write
9944 : * words - number of words to write
9945 : * data - words to write to the EEPROM
9946 : *****************************************************************************/
9947 : STATIC int32_t
9948 0 : em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
9949 : uint16_t *data)
9950 : {
9951 : uint32_t i = 0;
9952 : int32_t error = E1000_SUCCESS;
9953 0 : error = em_get_software_flag(hw);
9954 0 : if (error != E1000_SUCCESS)
9955 0 : return error;
9956 : /*
9957 : * A driver can write to the NVM only if it has eeprom_shadow_ram
9958 : * allocated. Subsequent reads to the modified words are read from
9959 : * this cached structure as well. Writes will only go into this
9960 : * cached structure unless it's followed by a call to
9961 : * em_update_eeprom_checksum() where it will commit the changes and
9962 : * clear the "modified" field.
9963 : */
9964 0 : if (hw->eeprom_shadow_ram != NULL) {
9965 0 : for (i = 0; i < words; i++) {
9966 0 : if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
9967 0 : hw->eeprom_shadow_ram[offset + i].modified =
9968 : TRUE;
9969 0 : hw->eeprom_shadow_ram[offset + i].eeprom_word =
9970 0 : data[i];
9971 : } else {
9972 : error = -E1000_ERR_EEPROM;
9973 0 : break;
9974 : }
9975 : }
9976 : } else {
9977 : /*
9978 : * Drivers have the option to not allocate eeprom_shadow_ram
9979 : * as long as they don't perform any NVM writes. An attempt
9980 : * in doing so will result in this error.
9981 : */
9982 : error = -E1000_ERR_EEPROM;
9983 : }
9984 :
9985 0 : em_release_software_flag(hw);
9986 :
9987 0 : return error;
9988 0 : }
9989 :
9990 : /******************************************************************************
9991 : * This function does initial flash setup so that a new read/write/erase cycle
9992 : * can be started.
9993 : *
9994 : * hw - The pointer to the hw structure
9995 : ****************************************************************************/
9996 : STATIC int32_t
9997 0 : em_ich8_cycle_init(struct em_hw *hw)
9998 : {
9999 : union ich8_hws_flash_status hsfsts;
10000 : int32_t error = E1000_ERR_EEPROM;
10001 : int32_t i = 0;
10002 : DEBUGFUNC("em_ich8_cycle_init");
10003 :
10004 0 : if (hw->mac_type >= em_pch_spt)
10005 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw,
10006 0 : ICH_FLASH_HSFSTS) & 0xFFFFUL;
10007 : else
10008 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10009 : ICH_FLASH_HSFSTS);
10010 :
10011 : /* May be check the Flash Des Valid bit in Hw status */
10012 0 : if (hsfsts.hsf_status.fldesvalid == 0) {
10013 : DEBUGOUT("Flash descriptor invalid. SW Sequencing must be"
10014 : " used.");
10015 0 : return error;
10016 : }
10017 : /* Clear FCERR in Hw status by writing 1 */
10018 : /* Clear DAEL in Hw status by writing a 1 */
10019 0 : hsfsts.hsf_status.flcerr = 1;
10020 0 : hsfsts.hsf_status.dael = 1;
10021 0 : if (hw->mac_type >= em_pch_spt)
10022 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,
10023 : hsfsts.regval & 0xFFFFUL);
10024 : else
10025 0 : E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
10026 : hsfsts.regval);
10027 : /*
10028 : * Either we should have a hardware SPI cycle in progress bit to
10029 : * check against, in order to start a new cycle or FDONE bit should
10030 : * be changed in the hardware so that it is 1 after hardware reset,
10031 : * which can then be used as an indication whether a cycle is in
10032 : * progress or has been completed .. we should also have some
10033 : * software semaphore mechanism to guard FDONE or the cycle in
10034 : * progress bit so that two threads access to those bits can be
10035 : * sequentiallized or a way so that 2 threads dont start the cycle at
10036 : * the same time
10037 : */
10038 :
10039 0 : if (hsfsts.hsf_status.flcinprog == 0) {
10040 : /*
10041 : * There is no cycle running at present, so we can start a
10042 : * cycle
10043 : */
10044 : /* Begin by setting Flash Cycle Done. */
10045 0 : hsfsts.hsf_status.flcdone = 1;
10046 0 : if (hw->mac_type >= em_pch_spt)
10047 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,
10048 : hsfsts.regval & 0xFFFFUL);
10049 : else
10050 0 : E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
10051 : hsfsts.regval);
10052 : error = E1000_SUCCESS;
10053 0 : } else {
10054 : /*
10055 : * otherwise poll for sometime so the current cycle has a
10056 : * chance to end before giving up.
10057 : */
10058 0 : for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
10059 0 : if (hw->mac_type >= em_pch_spt)
10060 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG32(
10061 0 : hw, ICH_FLASH_HSFSTS) & 0xFFFFUL;
10062 : else
10063 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG16(
10064 : hw, ICH_FLASH_HSFSTS);
10065 0 : if (hsfsts.hsf_status.flcinprog == 0) {
10066 : error = E1000_SUCCESS;
10067 0 : break;
10068 : }
10069 0 : usec_delay(1);
10070 : }
10071 0 : if (error == E1000_SUCCESS) {
10072 : /*
10073 : * Successful in waiting for previous cycle to
10074 : * timeout, now set the Flash Cycle Done.
10075 : */
10076 0 : hsfsts.hsf_status.flcdone = 1;
10077 0 : if (hw->mac_type >= em_pch_spt)
10078 0 : E1000_WRITE_ICH_FLASH_REG32(hw,
10079 : ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL);
10080 : else
10081 0 : E1000_WRITE_ICH_FLASH_REG16(hw,
10082 : ICH_FLASH_HSFSTS, hsfsts.regval);
10083 : } else {
10084 : DEBUGOUT("Flash controller busy, cannot get access");
10085 : }
10086 : }
10087 0 : return error;
10088 0 : }
10089 :
10090 : /******************************************************************************
10091 : * This function starts a flash cycle and waits for its completion
10092 : *
10093 : * hw - The pointer to the hw structure
10094 : *****************************************************************************/
10095 : STATIC int32_t
10096 0 : em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout)
10097 : {
10098 : union ich8_hws_flash_ctrl hsflctl;
10099 : union ich8_hws_flash_status hsfsts;
10100 : int32_t error = E1000_ERR_EEPROM;
10101 : uint32_t i = 0;
10102 :
10103 : /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
10104 0 : if (hw->mac_type >= em_pch_spt)
10105 0 : hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw,
10106 0 : ICH_FLASH_HSFSTS) >> 16;
10107 : else
10108 0 : hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,
10109 : ICH_FLASH_HSFCTL);
10110 0 : hsflctl.hsf_ctrl.flcgo = 1;
10111 :
10112 0 : if (hw->mac_type >= em_pch_spt)
10113 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,
10114 : (uint32_t)hsflctl.regval << 16);
10115 : else
10116 0 : E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
10117 : hsflctl.regval);
10118 :
10119 : /* wait till FDONE bit is set to 1 */
10120 0 : do {
10121 0 : if (hw->mac_type >= em_pch_spt)
10122 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw,
10123 0 : ICH_FLASH_HSFSTS) & 0xFFFFUL;
10124 : else
10125 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10126 : ICH_FLASH_HSFSTS);
10127 0 : if (hsfsts.hsf_status.flcdone == 1)
10128 : break;
10129 0 : usec_delay(1);
10130 0 : i++;
10131 0 : } while (i < timeout);
10132 0 : if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
10133 : error = E1000_SUCCESS;
10134 0 : }
10135 0 : return error;
10136 : }
10137 :
10138 : /******************************************************************************
10139 : * Reads a byte or word from the NVM using the ICH8 flash access registers.
10140 : *
10141 : * hw - The pointer to the hw structure
10142 : * index - The index of the byte or word to read.
10143 : * size - Size of data to read, 1=byte 2=word
10144 : * data - Pointer to the word to store the value read.
10145 : *****************************************************************************/
10146 : STATIC int32_t
10147 0 : em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
10148 : uint16_t *data)
10149 : {
10150 : union ich8_hws_flash_status hsfsts;
10151 : union ich8_hws_flash_ctrl hsflctl;
10152 : uint32_t flash_linear_address;
10153 : uint32_t flash_data = 0;
10154 : int32_t error = -E1000_ERR_EEPROM;
10155 : int32_t count = 0;
10156 : DEBUGFUNC("em_read_ich8_data");
10157 :
10158 0 : if (size < 1 || size > 2 || data == 0x0 ||
10159 0 : index > ICH_FLASH_LINEAR_ADDR_MASK)
10160 0 : return error;
10161 :
10162 0 : flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
10163 0 : hw->flash_base_addr;
10164 :
10165 0 : do {
10166 0 : usec_delay(1);
10167 : /* Steps */
10168 0 : error = em_ich8_cycle_init(hw);
10169 0 : if (error != E1000_SUCCESS)
10170 : break;
10171 :
10172 0 : hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,
10173 : ICH_FLASH_HSFCTL);
10174 : /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
10175 0 : hsflctl.hsf_ctrl.fldbcount = size - 1;
10176 0 : hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
10177 0 : E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
10178 : hsflctl.regval);
10179 : /*
10180 : * Write the last 24 bits of index into Flash Linear address
10181 : * field in Flash Address
10182 : */
10183 : /* TODO: TBD maybe check the index against the size of flash */
10184 :
10185 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,
10186 : flash_linear_address);
10187 :
10188 0 : error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
10189 : /*
10190 : * Check if FCERR is set to 1, if set to 1, clear it and try
10191 : * the whole sequence a few more times, else read in (shift
10192 : * in) the Flash Data0, the order is least significant byte
10193 : * first msb to lsb
10194 : */
10195 0 : if (error == E1000_SUCCESS) {
10196 0 : flash_data = E1000_READ_ICH_FLASH_REG(hw,
10197 : ICH_FLASH_FDATA0);
10198 0 : if (size == 1) {
10199 0 : *data = (uint8_t) (flash_data & 0x000000FF);
10200 0 : } else if (size == 2) {
10201 0 : *data = (uint16_t) (flash_data & 0x0000FFFF);
10202 0 : }
10203 : break;
10204 : } else {
10205 : /*
10206 : * If we've gotten here, then things are probably
10207 : * completely hosed, but if the error condition is
10208 : * detected, it won't hurt to give it another
10209 : * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10210 : */
10211 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10212 : ICH_FLASH_HSFSTS);
10213 0 : if (hsfsts.hsf_status.flcerr == 1) {
10214 : /* Repeat for some time before giving up. */
10215 : continue;
10216 0 : } else if (hsfsts.hsf_status.flcdone == 0) {
10217 : DEBUGOUT("Timeout error - flash cycle did not"
10218 : " complete.");
10219 : break;
10220 : }
10221 : }
10222 0 : } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
10223 :
10224 0 : return error;
10225 0 : }
10226 :
10227 : STATIC int32_t
10228 0 : em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data)
10229 : {
10230 : union ich8_hws_flash_status hsfsts;
10231 : union ich8_hws_flash_ctrl hsflctl;
10232 : uint32_t flash_linear_address;
10233 : int32_t error = -E1000_ERR_EEPROM;
10234 : uint32_t count = 0;
10235 : DEBUGFUNC("em_read_ich8_data32");
10236 :
10237 0 : if (hw->mac_type < em_pch_spt)
10238 0 : return error;
10239 0 : if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
10240 0 : return error;
10241 0 : flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
10242 0 : hw->flash_base_addr;
10243 :
10244 0 : do {
10245 0 : usec_delay(1);
10246 : /* Steps */
10247 0 : error = em_ich8_cycle_init(hw);
10248 0 : if (error != E1000_SUCCESS)
10249 : break;
10250 :
10251 : /* 32 bit accesses in SPT. */
10252 0 : hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw,
10253 0 : ICH_FLASH_HSFSTS) >> 16;
10254 :
10255 0 : hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1;
10256 0 : hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
10257 :
10258 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,
10259 : (uint32_t)hsflctl.regval << 16);
10260 : /*
10261 : * Write the last 24 bits of offset into Flash Linear address
10262 : * field in Flash Address
10263 : */
10264 : /* TODO: TBD maybe check the offset against the size of flash */
10265 :
10266 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,
10267 : flash_linear_address);
10268 :
10269 0 : error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
10270 : /*
10271 : * Check if FCERR is set to 1, if set to 1, clear it and try
10272 : * the whole sequence a few more times, else read in (shift
10273 : * in) the Flash Data0, the order is least significant byte
10274 : * first msb to lsb
10275 : */
10276 0 : if (error == E1000_SUCCESS) {
10277 0 : (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw,
10278 : ICH_FLASH_FDATA0);
10279 0 : break;
10280 : } else {
10281 : /*
10282 : * If we've gotten here, then things are probably
10283 : * completely hosed, but if the error condition is
10284 : * detected, it won't hurt to give it another
10285 : * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10286 : */
10287 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10288 : ICH_FLASH_HSFSTS);
10289 0 : if (hsfsts.hsf_status.flcerr == 1) {
10290 : /* Repeat for some time before giving up. */
10291 : continue;
10292 0 : } else if (hsfsts.hsf_status.flcdone == 0) {
10293 : DEBUGOUT("Timeout error - flash cycle did not"
10294 : " complete.");
10295 : break;
10296 : }
10297 : }
10298 0 : } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
10299 :
10300 0 : return error;
10301 0 : }
10302 :
10303 :
10304 : /******************************************************************************
10305 : * Writes One /two bytes to the NVM using the ICH8 flash access registers.
10306 : *
10307 : * hw - The pointer to the hw structure
10308 : * index - The index of the byte/word to write.
10309 : * size - Size of data to read, 1=byte 2=word
10310 : * data - The byte(s) to write to the NVM.
10311 : *****************************************************************************/
10312 : STATIC int32_t
10313 0 : em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
10314 : uint16_t data)
10315 : {
10316 : union ich8_hws_flash_status hsfsts;
10317 : union ich8_hws_flash_ctrl hsflctl;
10318 : uint32_t flash_linear_address;
10319 : uint32_t flash_data = 0;
10320 : int32_t error = -E1000_ERR_EEPROM;
10321 : int32_t count = 0;
10322 : DEBUGFUNC("em_write_ich8_data");
10323 :
10324 0 : if (hw->mac_type >= em_pch_spt)
10325 0 : return -E1000_ERR_EEPROM;
10326 0 : if (size < 1 || size > 2 || data > size * 0xff ||
10327 0 : index > ICH_FLASH_LINEAR_ADDR_MASK)
10328 0 : return error;
10329 :
10330 0 : flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
10331 0 : hw->flash_base_addr;
10332 :
10333 0 : do {
10334 0 : usec_delay(1);
10335 : /* Steps */
10336 0 : error = em_ich8_cycle_init(hw);
10337 0 : if (error != E1000_SUCCESS)
10338 : break;
10339 :
10340 0 : hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,
10341 : ICH_FLASH_HSFCTL);
10342 : /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
10343 0 : hsflctl.hsf_ctrl.fldbcount = size - 1;
10344 0 : hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
10345 0 : E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
10346 : hsflctl.regval);
10347 : /*
10348 : * Write the last 24 bits of index into Flash Linear address
10349 : * field in Flash Address
10350 : */
10351 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,
10352 : flash_linear_address);
10353 :
10354 0 : if (size == 1)
10355 0 : flash_data = (uint32_t) data & 0x00FF;
10356 : else
10357 : flash_data = (uint32_t) data;
10358 :
10359 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data);
10360 : /*
10361 : * check if FCERR is set to 1 , if set to 1, clear it and try
10362 : * the whole sequence a few more times else done
10363 : */
10364 0 : error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
10365 0 : if (error == E1000_SUCCESS) {
10366 : break;
10367 : } else {
10368 : /*
10369 : * If we're here, then things are most likely
10370 : * completely hosed, but if the error condition is
10371 : * detected, it won't hurt to give it another
10372 : * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10373 : */
10374 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10375 : ICH_FLASH_HSFSTS);
10376 0 : if (hsfsts.hsf_status.flcerr == 1) {
10377 : /* Repeat for some time before giving up. */
10378 : continue;
10379 0 : } else if (hsfsts.hsf_status.flcdone == 0) {
10380 : DEBUGOUT("Timeout error - flash cycle did not"
10381 : " complete.");
10382 : break;
10383 : }
10384 : }
10385 0 : } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
10386 :
10387 0 : return error;
10388 0 : }
10389 :
10390 : /******************************************************************************
10391 : * Reads a single byte from the NVM using the ICH8 flash access registers.
10392 : *
10393 : * hw - pointer to em_hw structure
10394 : * index - The index of the byte to read.
10395 : * data - Pointer to a byte to store the value read.
10396 : *****************************************************************************/
10397 : STATIC int32_t
10398 0 : em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data)
10399 : {
10400 : int32_t status = E1000_SUCCESS;
10401 0 : uint16_t word = 0;
10402 :
10403 0 : if (hw->mac_type >= em_pch_spt)
10404 0 : return -E1000_ERR_EEPROM;
10405 : else
10406 0 : status = em_read_ich8_data(hw, index, 1, &word);
10407 0 : if (status == E1000_SUCCESS) {
10408 0 : *data = (uint8_t) word;
10409 0 : }
10410 0 : return status;
10411 0 : }
10412 :
10413 : /******************************************************************************
10414 : * Writes a single byte to the NVM using the ICH8 flash access registers.
10415 : * Performs verification by reading back the value and then going through
10416 : * a retry algorithm before giving up.
10417 : *
10418 : * hw - pointer to em_hw structure
10419 : * index - The index of the byte to write.
10420 : * byte - The byte to write to the NVM.
10421 : *****************************************************************************/
10422 : STATIC int32_t
10423 0 : em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte)
10424 : {
10425 : int32_t error = E1000_SUCCESS;
10426 : int32_t program_retries = 0;
10427 : DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
10428 :
10429 0 : error = em_write_ich8_byte(hw, index, byte);
10430 :
10431 0 : if (error != E1000_SUCCESS) {
10432 0 : for (program_retries = 0; program_retries < 100;
10433 0 : program_retries++) {
10434 : DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n",
10435 : byte, index);
10436 0 : error = em_write_ich8_byte(hw, index, byte);
10437 0 : usec_delay(100);
10438 0 : if (error == E1000_SUCCESS)
10439 : break;
10440 : }
10441 : }
10442 0 : if (program_retries == 100)
10443 0 : error = E1000_ERR_EEPROM;
10444 :
10445 0 : return error;
10446 : }
10447 :
10448 : /******************************************************************************
10449 : * Writes a single byte to the NVM using the ICH8 flash access registers.
10450 : *
10451 : * hw - pointer to em_hw structure
10452 : * index - The index of the byte to read.
10453 : * data - The byte to write to the NVM.
10454 : *****************************************************************************/
10455 : STATIC int32_t
10456 0 : em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data)
10457 : {
10458 : int32_t status = E1000_SUCCESS;
10459 0 : uint16_t word = (uint16_t) data;
10460 0 : status = em_write_ich8_data(hw, index, 1, word);
10461 :
10462 0 : return status;
10463 : }
10464 :
10465 : /******************************************************************************
10466 : * Reads a dword from the NVM using the ICH8 flash access registers.
10467 : *
10468 : * hw - pointer to em_hw structure
10469 : * index - The starting BYTE index of the word to read.
10470 : * data - Pointer to a word to store the value read.
10471 : *****************************************************************************/
10472 : STATIC int32_t
10473 0 : em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data)
10474 : {
10475 : int32_t status = E1000_SUCCESS;
10476 0 : status = em_read_ich8_data32(hw, index, data);
10477 0 : return status;
10478 : }
10479 :
10480 : /******************************************************************************
10481 : * Reads a word from the NVM using the ICH8 flash access registers.
10482 : *
10483 : * hw - pointer to em_hw structure
10484 : * index - The starting byte index of the word to read.
10485 : * data - Pointer to a word to store the value read.
10486 : *****************************************************************************/
10487 : STATIC int32_t
10488 0 : em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data)
10489 : {
10490 : int32_t status = E1000_SUCCESS;
10491 0 : status = em_read_ich8_data(hw, index, 2, data);
10492 0 : return status;
10493 : }
10494 :
10495 : /******************************************************************************
10496 : * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
10497 : * based.
10498 : *
10499 : * hw - pointer to em_hw structure
10500 : * bank - 0 for first bank, 1 for second bank
10501 : *
10502 : * Note that this function may actually erase as much as 8 or 64 KBytes. The
10503 : * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
10504 : * bank size may be 4, 8 or 64 KBytes
10505 : *****************************************************************************/
10506 : int32_t
10507 0 : em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank)
10508 : {
10509 : union ich8_hws_flash_status hsfsts;
10510 : union ich8_hws_flash_ctrl hsflctl;
10511 : uint32_t flash_linear_address;
10512 : int32_t count = 0;
10513 : int32_t error = E1000_ERR_EEPROM;
10514 : int32_t iteration;
10515 : int32_t sub_sector_size = 0;
10516 : int32_t bank_size;
10517 : int32_t j = 0;
10518 : int32_t error_flag = 0;
10519 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
10520 : /*
10521 : * Determine HW Sector size: Read BERASE bits of Hw flash Status
10522 : * register
10523 : */
10524 : /*
10525 : * 00: The Hw sector is 256 bytes, hence we need to erase 16
10526 : * consecutive sectors. The start index for the nth Hw sector can be
10527 : * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes,
10528 : * hence we need to erase 1 sector. The start index for the nth Hw
10529 : * sector can be calculated as bank * 4096 10: The HW sector is 8K
10530 : * bytes 11: The Hw sector size is 64K bytes
10531 : */
10532 0 : if (hsfsts.hsf_status.berasesz == 0x0) {
10533 : /* Hw sector size 256 */
10534 : sub_sector_size = ICH_FLASH_SEG_SIZE_256;
10535 : bank_size = ICH_FLASH_SECTOR_SIZE;
10536 : iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
10537 0 : } else if (hsfsts.hsf_status.berasesz == 0x1) {
10538 : bank_size = ICH_FLASH_SEG_SIZE_4K;
10539 : iteration = 1;
10540 0 : } else if (hsfsts.hsf_status.berasesz == 0x2) {
10541 0 : if (hw->mac_type == em_ich9lan) {
10542 : uint32_t gfpreg, sector_base_addr, sector_end_addr;
10543 0 : gfpreg = E1000_READ_ICH_FLASH_REG(hw,
10544 : ICH_FLASH_GFPREG);
10545 : /*
10546 : * sector_X_addr is a "sector"-aligned address (4096 bytes)
10547 : * Add 1 to sector_end_addr since this sector is included in
10548 : * the overall size.
10549 : */
10550 0 : sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK;
10551 : sector_end_addr =
10552 0 : ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1;
10553 :
10554 : /*
10555 : * find total size of the NVM, then cut in half since the total
10556 : * size represents two separate NVM banks.
10557 : */
10558 0 : bank_size = (sector_end_addr - sector_base_addr)
10559 0 : << ICH_FLASH_SECT_ADDR_SHIFT;
10560 0 : bank_size /= 2;
10561 : /* Word align */
10562 : bank_size =
10563 0 : (bank_size / sizeof(uint16_t)) * sizeof(uint16_t);
10564 :
10565 : sub_sector_size = ICH_FLASH_SEG_SIZE_8K;
10566 0 : iteration = bank_size / ICH_FLASH_SEG_SIZE_8K;
10567 : } else {
10568 0 : return error;
10569 : }
10570 0 : } else if (hsfsts.hsf_status.berasesz == 0x3) {
10571 : bank_size = ICH_FLASH_SEG_SIZE_64K;
10572 : iteration = 1;
10573 : } else {
10574 0 : return error;
10575 : }
10576 :
10577 0 : for (j = 0; j < iteration; j++) {
10578 0 : do {
10579 0 : count++;
10580 : /* Steps */
10581 0 : error = em_ich8_cycle_init(hw);
10582 0 : if (error != E1000_SUCCESS) {
10583 : error_flag = 1;
10584 0 : break;
10585 : }
10586 : /*
10587 : * Write a value 11 (block Erase) in Flash Cycle
10588 : * field in Hw flash Control
10589 : */
10590 0 : hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,
10591 : ICH_FLASH_HSFCTL);
10592 0 : hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
10593 0 : E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
10594 : hsflctl.regval);
10595 : /*
10596 : * Write the last 24 bits of an index within the
10597 : * block into Flash Linear address field in Flash
10598 : * Address. This probably needs to be calculated
10599 : * here based off the on-chip erase sector size and
10600 : * the software bank size (4, 8 or 64 KBytes)
10601 : */
10602 : flash_linear_address =
10603 0 : bank * bank_size + j * sub_sector_size;
10604 0 : flash_linear_address += hw->flash_base_addr;
10605 0 : flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
10606 :
10607 0 : E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,
10608 : flash_linear_address);
10609 :
10610 : error =
10611 0 : em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
10612 : /*
10613 : * Check if FCERR is set to 1. If 1, clear it and
10614 : * try the whole sequence a few more times else Done
10615 : */
10616 0 : if (error == E1000_SUCCESS) {
10617 : break;
10618 : } else {
10619 0 : hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,
10620 : ICH_FLASH_HSFSTS);
10621 0 : if (hsfsts.hsf_status.flcerr == 1) {
10622 : /*
10623 : * repeat for some time before giving
10624 : * up
10625 : */
10626 : continue;
10627 0 : } else if (hsfsts.hsf_status.flcdone == 0) {
10628 : error_flag = 1;
10629 0 : break;
10630 : }
10631 : }
10632 0 : } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
10633 0 : if (error_flag == 1)
10634 : break;
10635 : }
10636 0 : if (error_flag != 1)
10637 0 : error = E1000_SUCCESS;
10638 0 : return error;
10639 0 : }
10640 :
10641 : /******************************************************************************
10642 : * Reads 16-bit words from the OTP. Return error when the word is not
10643 : * stored in OTP.
10644 : *
10645 : * hw - Struct containing variables accessed by shared code
10646 : * offset - offset of word in the OTP to read
10647 : * data - word read from the OTP
10648 : * words - number of words to read
10649 : *****************************************************************************/
10650 : STATIC int32_t
10651 0 : em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words,
10652 : uint16_t *data)
10653 : {
10654 : int32_t ret_val = E1000_SUCCESS;
10655 :
10656 0 : switch (offset)
10657 : {
10658 : case EEPROM_MAC_ADDR_WORD0:
10659 : case EEPROM_MAC_ADDR_WORD1:
10660 : case EEPROM_MAC_ADDR_WORD2:
10661 : /* Generate random MAC address if there's none. */
10662 0 : ret_val = em_read_invm_word_i210(hw, offset, data);
10663 0 : if (ret_val != E1000_SUCCESS) {
10664 : DEBUGOUT("MAC Addr not found in iNVM\n");
10665 0 : *data = 0xFFFF;
10666 : ret_val = E1000_SUCCESS;
10667 0 : }
10668 : break;
10669 : case EEPROM_INIT_CONTROL2_REG:
10670 0 : ret_val = em_read_invm_word_i210(hw, offset, data);
10671 0 : if (ret_val != E1000_SUCCESS) {
10672 0 : *data = NVM_INIT_CTRL_2_DEFAULT_I211;
10673 : ret_val = E1000_SUCCESS;
10674 0 : }
10675 : break;
10676 : case EEPROM_INIT_CONTROL4_REG:
10677 0 : ret_val = em_read_invm_word_i210(hw, offset, data);
10678 0 : if (ret_val != E1000_SUCCESS) {
10679 0 : *data = NVM_INIT_CTRL_4_DEFAULT_I211;
10680 : ret_val = E1000_SUCCESS;
10681 0 : }
10682 : break;
10683 : case EEPROM_LED_1_CFG:
10684 0 : ret_val = em_read_invm_word_i210(hw, offset, data);
10685 0 : if (ret_val != E1000_SUCCESS) {
10686 0 : *data = NVM_LED_1_CFG_DEFAULT_I211;
10687 : ret_val = E1000_SUCCESS;
10688 0 : }
10689 : break;
10690 : case EEPROM_LED_0_2_CFG:
10691 0 : ret_val = em_read_invm_word_i210(hw, offset, data);
10692 0 : if (ret_val != E1000_SUCCESS) {
10693 0 : *data = NVM_LED_0_2_CFG_DEFAULT_I211;
10694 : ret_val = E1000_SUCCESS;
10695 0 : }
10696 : break;
10697 : case EEPROM_ID_LED_SETTINGS:
10698 0 : ret_val = em_read_invm_word_i210(hw, offset, data);
10699 0 : if (ret_val != E1000_SUCCESS) {
10700 0 : *data = ID_LED_RESERVED_FFFF;
10701 : ret_val = E1000_SUCCESS;
10702 0 : }
10703 : break;
10704 : default:
10705 : DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset);
10706 0 : *data = NVM_RESERVED_WORD;
10707 0 : break;
10708 : }
10709 :
10710 0 : return ret_val;
10711 : }
10712 :
10713 : /******************************************************************************
10714 : * Reads 16-bit words from the OTP. Return error when the word is not
10715 : * stored in OTP.
10716 : *
10717 : * hw - Struct containing variables accessed by shared code
10718 : * offset - offset of word in the OTP to read
10719 : * data - word read from the OTP
10720 : *****************************************************************************/
10721 : STATIC int32_t
10722 0 : em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data)
10723 : {
10724 : int32_t error = -E1000_NOT_IMPLEMENTED;
10725 : uint32_t invm_dword;
10726 : uint16_t i;
10727 : uint8_t record_type, word_address;
10728 :
10729 0 : for (i = 0; i < INVM_SIZE; i++) {
10730 0 : invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i));
10731 : /* Get record type */
10732 0 : record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);
10733 0 : if (record_type == INVM_UNINITIALIZED_STRUCTURE)
10734 : break;
10735 0 : if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE)
10736 0 : i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;
10737 0 : if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE)
10738 0 : i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;
10739 0 : if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) {
10740 0 : word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);
10741 0 : if (word_address == address) {
10742 0 : *data = INVM_DWORD_TO_WORD_DATA(invm_dword);
10743 : error = E1000_SUCCESS;
10744 0 : break;
10745 : }
10746 : }
10747 : }
10748 :
10749 0 : return error;
10750 : }
10751 :
10752 : STATIC int32_t
10753 0 : em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr,
10754 : uint32_t cnf_size)
10755 : {
10756 : uint32_t ret_val = E1000_SUCCESS;
10757 0 : uint16_t word_addr, reg_data, reg_addr;
10758 : uint16_t i;
10759 : /* cnf_base_addr is in DWORD */
10760 0 : word_addr = (uint16_t) (cnf_base_addr << 1);
10761 :
10762 : /* cnf_size is returned in size of dwords */
10763 0 : for (i = 0; i < cnf_size; i++) {
10764 : ret_val =
10765 0 : em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data);
10766 0 : if (ret_val)
10767 0 : return ret_val;
10768 :
10769 : ret_val =
10770 0 : em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr);
10771 0 : if (ret_val)
10772 0 : return ret_val;
10773 :
10774 0 : ret_val = em_get_software_flag(hw);
10775 0 : if (ret_val != E1000_SUCCESS)
10776 0 : return ret_val;
10777 :
10778 : ret_val =
10779 0 : em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data);
10780 :
10781 0 : em_release_software_flag(hw);
10782 : }
10783 :
10784 0 : return ret_val;
10785 0 : }
10786 :
10787 : /******************************************************************************
10788 : * This function initializes the PHY from the NVM on ICH8 platforms. This
10789 : * is needed due to an issue where the NVM configuration is not properly
10790 : * autoloaded after power transitions. Therefore, after each PHY reset, we
10791 : * will load the configuration data out of the NVM manually.
10792 : *
10793 : * hw: Struct containing variables accessed by shared code
10794 : *****************************************************************************/
10795 : STATIC int32_t
10796 0 : em_init_lcd_from_nvm(struct em_hw *hw)
10797 : {
10798 : uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask;
10799 0 : if (hw->phy_type != em_phy_igp_3)
10800 0 : return E1000_SUCCESS;
10801 :
10802 : /* Check if SW needs configure the PHY */
10803 0 : if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT ||
10804 0 : hw->device_id == E1000_DEV_ID_ICH8_IGP_M ||
10805 0 : hw->mac_type == em_pchlan ||
10806 0 : hw->mac_type == em_pch2lan ||
10807 0 : hw->mac_type == em_pch_lpt ||
10808 0 : hw->mac_type == em_pch_spt ||
10809 0 : hw->mac_type == em_pch_cnp)
10810 0 : sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M;
10811 : else
10812 : sw_cfg_mask = FEXTNVM_SW_CONFIG;
10813 :
10814 0 : reg_data = E1000_READ_REG(hw, FEXTNVM);
10815 0 : if (!(reg_data & sw_cfg_mask))
10816 0 : return E1000_SUCCESS;
10817 :
10818 : /* Wait for basic configuration completes before proceeding */
10819 : loop = 0;
10820 0 : do {
10821 : reg_data =
10822 0 : E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
10823 0 : usec_delay(100);
10824 0 : loop++;
10825 0 : } while ((!reg_data) && (loop < 50));
10826 :
10827 : /* Clear the Init Done bit for the next init event */
10828 0 : reg_data = E1000_READ_REG(hw, STATUS);
10829 0 : reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
10830 0 : E1000_WRITE_REG(hw, STATUS, reg_data);
10831 : /*
10832 : * Make sure HW does not configure LCD from PHY extended
10833 : * configuration before SW configuration
10834 : */
10835 0 : reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
10836 0 : if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
10837 0 : reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
10838 0 : cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
10839 0 : cnf_size >>= 16;
10840 0 : if (cnf_size) {
10841 0 : reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
10842 0 : cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
10843 : /* cnf_base_addr is in DWORD */
10844 0 : cnf_base_addr >>= 16;
10845 :
10846 : /* Configure LCD from extended configuration region. */
10847 0 : ret_val = em_init_lcd_from_nvm_config_region(hw,
10848 : cnf_base_addr, cnf_size);
10849 0 : if (ret_val)
10850 0 : return ret_val;
10851 : }
10852 : }
10853 0 : return E1000_SUCCESS;
10854 0 : }
10855 :
10856 : /******************************************************************************
10857 : * em_set_pciex_completion_timeout - set pci-e completion timeout
10858 : *
10859 : * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
10860 : * however the hardware default for these parts is 500us to 1ms which is less
10861 : * than the 10ms recommended by the pci-e spec. To address this we need to
10862 : * increase the value to either 10ms to 200ms for capability version 1 config,
10863 : * or 16ms to 55ms for version 2.
10864 : *
10865 : * * hw - pointer to em_hw structure
10866 : *****************************************************************************/
10867 : int32_t
10868 0 : em_set_pciex_completion_timeout(struct em_hw *hw)
10869 : {
10870 0 : uint32_t gcr = E1000_READ_REG(hw, GCR);
10871 : int32_t ret_val = E1000_SUCCESS;
10872 :
10873 : /* Only take action if timeout value is not set by system BIOS */
10874 0 : if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
10875 : goto out;
10876 :
10877 : DEBUGOUT("PCIe completion timeout not set by system BIOS.");
10878 :
10879 : /*
10880 : * If capababilities version is type 1 we can write the
10881 : * timeout of 10ms to 200ms through the GCR register
10882 : */
10883 :
10884 0 : if (!(gcr & E1000_GCR_CAP_VER2)) {
10885 0 : gcr |= E1000_GCR_CMPL_TMOUT_10ms;
10886 : DEBUGOUT("PCIe capability version 1 detected, setting \
10887 : completion timeout to 10ms.");
10888 0 : goto out;
10889 : }
10890 :
10891 : /*
10892 : * For version 2 capabilities we need to write the config space
10893 : * directly in order to set the completion timeout value for
10894 : * 16ms to 55ms
10895 : *
10896 : * XXX: Implement em_*_pcie_cap_reg() first.
10897 : */
10898 : #if 0
10899 : ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
10900 : &pciex_devctl2);
10901 :
10902 : if (ret_val)
10903 : goto out;
10904 :
10905 : pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
10906 :
10907 : ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
10908 : &pciex_devctl2);
10909 : #endif
10910 :
10911 : out:
10912 :
10913 : /* Disable completion timeout resend */
10914 0 : gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
10915 :
10916 : DEBUGOUT("PCIe completion timeout resend disabled.");
10917 :
10918 0 : E1000_WRITE_REG(hw, GCR, gcr);
10919 0 : return ret_val;
10920 : }
10921 :
10922 : /***************************************************************************
10923 : * Set slow MDIO access mode
10924 : ***************************************************************************/
10925 : static int32_t
10926 0 : em_set_mdio_slow_mode_hv(struct em_hw *hw)
10927 : {
10928 : int32_t ret_val;
10929 0 : uint16_t data;
10930 : DEBUGFUNC("em_set_mdio_slow_mode_hv");
10931 :
10932 0 : ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data);
10933 0 : if (ret_val)
10934 0 : return ret_val;
10935 :
10936 0 : data |= HV_KMRN_MDIO_SLOW;
10937 :
10938 0 : ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data);
10939 :
10940 0 : return ret_val;
10941 0 : }
10942 :
10943 : /***************************************************************************
10944 : * A series of Phy workarounds to be done after every PHY reset.
10945 : ***************************************************************************/
10946 : int32_t
10947 0 : em_hv_phy_workarounds_ich8lan(struct em_hw *hw)
10948 : {
10949 : int32_t ret_val = E1000_SUCCESS;
10950 0 : uint16_t phy_data;
10951 : uint16_t swfw;
10952 : DEBUGFUNC("em_hv_phy_workarounds_ich8lan");
10953 :
10954 0 : if (hw->mac_type != em_pchlan)
10955 : goto out;
10956 :
10957 : swfw = E1000_SWFW_PHY0_SM;
10958 :
10959 : /* Set MDIO slow mode before any other MDIO access */
10960 0 : if (hw->phy_type == em_phy_82577 ||
10961 0 : hw->phy_type == em_phy_82578) {
10962 0 : ret_val = em_set_mdio_slow_mode_hv(hw);
10963 0 : if (ret_val)
10964 : goto out;
10965 : }
10966 :
10967 : /* Hanksville M Phy init for IEEE. */
10968 0 : if ((hw->revision_id == 2) &&
10969 0 : (hw->phy_type == em_phy_82577) &&
10970 0 : ((hw->phy_revision == 2) || (hw->phy_revision == 3))) {
10971 0 : em_write_phy_reg(hw, 0x10, 0x8823);
10972 0 : em_write_phy_reg(hw, 0x11, 0x0018);
10973 0 : em_write_phy_reg(hw, 0x10, 0x8824);
10974 0 : em_write_phy_reg(hw, 0x11, 0x0016);
10975 0 : em_write_phy_reg(hw, 0x10, 0x8825);
10976 0 : em_write_phy_reg(hw, 0x11, 0x001A);
10977 0 : em_write_phy_reg(hw, 0x10, 0x888C);
10978 0 : em_write_phy_reg(hw, 0x11, 0x0007);
10979 0 : em_write_phy_reg(hw, 0x10, 0x888D);
10980 0 : em_write_phy_reg(hw, 0x11, 0x0007);
10981 0 : em_write_phy_reg(hw, 0x10, 0x888E);
10982 0 : em_write_phy_reg(hw, 0x11, 0x0007);
10983 0 : em_write_phy_reg(hw, 0x10, 0x8827);
10984 0 : em_write_phy_reg(hw, 0x11, 0x0001);
10985 0 : em_write_phy_reg(hw, 0x10, 0x8835);
10986 0 : em_write_phy_reg(hw, 0x11, 0x0001);
10987 0 : em_write_phy_reg(hw, 0x10, 0x8834);
10988 0 : em_write_phy_reg(hw, 0x11, 0x0001);
10989 0 : em_write_phy_reg(hw, 0x10, 0x8833);
10990 0 : em_write_phy_reg(hw, 0x11, 0x0002);
10991 0 : }
10992 :
10993 0 : if (((hw->phy_type == em_phy_82577) &&
10994 0 : ((hw->phy_revision == 1) || (hw->phy_revision == 2))) ||
10995 0 : ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) {
10996 : /* Disable generation of early preamble */
10997 0 : ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431);
10998 0 : if (ret_val)
10999 : goto out;
11000 :
11001 : /* Preamble tuning for SSC */
11002 0 : ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204);
11003 0 : if (ret_val)
11004 : goto out;
11005 : }
11006 :
11007 0 : if (hw->phy_type == em_phy_82578) {
11008 : /*
11009 : * Return registers to default by doing a soft reset then
11010 : * writing 0x3140 to the control register.
11011 : */
11012 0 : if (hw->phy_revision < 2) {
11013 0 : em_phy_reset(hw);
11014 0 : ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140);
11015 0 : }
11016 : }
11017 :
11018 0 : if ((hw->revision_id == 2) &&
11019 0 : (hw->phy_type == em_phy_82577) &&
11020 0 : ((hw->phy_revision == 2) || (hw->phy_revision == 3))) {
11021 : /*
11022 : * Workaround for OEM (GbE) not operating after reset -
11023 : * restart AN (twice)
11024 : */
11025 0 : ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400);
11026 0 : if (ret_val)
11027 : goto out;
11028 0 : ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400);
11029 0 : if (ret_val)
11030 : goto out;
11031 : }
11032 :
11033 : /* Select page 0 */
11034 0 : ret_val = em_swfw_sync_acquire(hw, swfw);
11035 0 : if (ret_val)
11036 : goto out;
11037 :
11038 0 : hw->phy_addr = 1;
11039 0 : ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
11040 0 : em_swfw_sync_release(hw, swfw);
11041 0 : if (ret_val)
11042 : goto out;
11043 :
11044 : /* Workaround for link disconnects on a busy hub in half duplex */
11045 0 : ret_val = em_read_phy_reg(hw,
11046 : PHY_REG(BM_PORT_CTRL_PAGE, 17),
11047 : &phy_data);
11048 0 : if (ret_val)
11049 : goto release;
11050 0 : ret_val = em_write_phy_reg(hw,
11051 : PHY_REG(BM_PORT_CTRL_PAGE, 17),
11052 0 : phy_data & 0x00FF);
11053 : release:
11054 : out:
11055 0 : return ret_val;
11056 0 : }
11057 :
11058 :
11059 : /***************************************************************************
11060 : * Si workaround
11061 : *
11062 : * This function works around a Si bug where the link partner can get
11063 : * a link up indication before the PHY does. If small packets are sent
11064 : * by the link partner they can be placed in the packet buffer without
11065 : * being properly accounted for by the PHY and will stall preventing
11066 : * further packets from being received. The workaround is to clear the
11067 : * packet buffer after the PHY detects link up.
11068 : ***************************************************************************/
11069 : int32_t
11070 0 : em_link_stall_workaround_hv(struct em_hw *hw)
11071 : {
11072 : int32_t ret_val = E1000_SUCCESS;
11073 0 : uint16_t phy_data;
11074 :
11075 0 : if (hw->phy_type != em_phy_82578)
11076 : goto out;
11077 :
11078 : /* Do not apply workaround if in PHY loopback bit 14 set */
11079 0 : em_read_phy_reg(hw, PHY_CTRL, &phy_data);
11080 0 : if (phy_data & E1000_PHY_CTRL_LOOPBACK)
11081 : goto out;
11082 :
11083 : /* check if link is up and at 1Gbps */
11084 0 : ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data);
11085 0 : if (ret_val)
11086 : goto out;
11087 :
11088 0 : phy_data &= BM_CS_STATUS_LINK_UP |
11089 : BM_CS_STATUS_RESOLVED |
11090 : BM_CS_STATUS_SPEED_MASK;
11091 :
11092 0 : if (phy_data != (BM_CS_STATUS_LINK_UP |
11093 : BM_CS_STATUS_RESOLVED |
11094 : BM_CS_STATUS_SPEED_1000))
11095 : goto out;
11096 :
11097 0 : msec_delay(200);
11098 :
11099 : /* flush the packets in the fifo buffer */
11100 0 : ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL,
11101 : HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED);
11102 0 : if (ret_val)
11103 : goto out;
11104 :
11105 0 : ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL,
11106 : HV_MUX_DATA_CTRL_GEN_TO_MAC);
11107 :
11108 : out:
11109 0 : return ret_val;
11110 0 : }
11111 :
11112 : /****************************************************************************
11113 : * K1 Si workaround
11114 : *
11115 : * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
11116 : * from a lower speed. This workaround disables K1 whenever link is at 1Gig.
11117 : * If link is down, the function will restore the default K1 setting located
11118 : * in the NVM.
11119 : ****************************************************************************/
11120 : int32_t
11121 0 : em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link)
11122 : {
11123 : int32_t ret_val;
11124 0 : uint16_t phy_data;
11125 : boolean_t k1_enable;
11126 :
11127 : DEBUGFUNC("em_k1_gig_workaround_hv");
11128 :
11129 0 : if (hw->mac_type != em_pchlan)
11130 0 : return E1000_SUCCESS;
11131 :
11132 0 : ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data);
11133 0 : if (ret_val)
11134 0 : return ret_val;
11135 :
11136 0 : k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE;
11137 :
11138 : /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
11139 0 : if (link) {
11140 0 : if (hw->phy_type == em_phy_82578) {
11141 0 : ret_val = em_read_phy_reg(hw, BM_CS_STATUS,
11142 : &phy_data);
11143 0 : if (ret_val)
11144 0 : return ret_val;
11145 :
11146 0 : phy_data &= BM_CS_STATUS_LINK_UP |
11147 : BM_CS_STATUS_RESOLVED |
11148 : BM_CS_STATUS_SPEED_MASK;
11149 :
11150 0 : if (phy_data == (BM_CS_STATUS_LINK_UP |
11151 : BM_CS_STATUS_RESOLVED |
11152 : BM_CS_STATUS_SPEED_1000))
11153 0 : k1_enable = FALSE;
11154 : }
11155 :
11156 0 : if (hw->phy_type == em_phy_82577) {
11157 0 : ret_val = em_read_phy_reg(hw, HV_M_STATUS,
11158 : &phy_data);
11159 0 : if (ret_val)
11160 0 : return ret_val;
11161 :
11162 0 : phy_data &= HV_M_STATUS_LINK_UP |
11163 : HV_M_STATUS_AUTONEG_COMPLETE |
11164 : HV_M_STATUS_SPEED_MASK;
11165 :
11166 0 : if (phy_data == (HV_M_STATUS_LINK_UP |
11167 : HV_M_STATUS_AUTONEG_COMPLETE |
11168 : HV_M_STATUS_SPEED_1000))
11169 0 : k1_enable = FALSE;
11170 : }
11171 :
11172 : /* Link stall fix for link up */
11173 0 : ret_val = em_write_phy_reg(hw, PHY_REG(770, 19),
11174 : 0x0100);
11175 0 : if (ret_val)
11176 0 : return ret_val;
11177 :
11178 : } else {
11179 : /* Link stall fix for link down */
11180 0 : ret_val = em_write_phy_reg(hw, PHY_REG(770, 19),
11181 : 0x4100);
11182 0 : if (ret_val)
11183 0 : return ret_val;
11184 : }
11185 :
11186 0 : ret_val = em_configure_k1_ich8lan(hw, k1_enable);
11187 :
11188 0 : return ret_val;
11189 0 : }
11190 :
11191 : /* Workaround to set the K1 beacon duration for 82579 parts */
11192 : int32_t
11193 0 : em_k1_workaround_lv(struct em_hw *hw)
11194 : {
11195 : int32_t ret_val;
11196 0 : uint16_t phy_data;
11197 : uint32_t mac_reg;
11198 :
11199 0 : ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data);
11200 0 : if (ret_val)
11201 0 : return ret_val;
11202 :
11203 0 : if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
11204 0 : == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
11205 0 : mac_reg = E1000_READ_REG(hw, FEXTNVM4);
11206 0 : mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
11207 :
11208 0 : if (phy_data & HV_M_STATUS_SPEED_1000)
11209 0 : mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
11210 : else
11211 0 : mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
11212 :
11213 0 : E1000_WRITE_REG(hw, FEXTNVM4, mac_reg);
11214 0 : }
11215 :
11216 0 : return E1000_SUCCESS;
11217 0 : }
11218 :
11219 : /**
11220 : * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
11221 : *
11222 : * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
11223 : * preventing further DMA write requests. Workaround the issue by disabling
11224 : * the de-assertion of the clock request when in 1Gbps mode.
11225 : * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
11226 : * speeds in order to avoid Tx hangs.
11227 : **/
11228 : int32_t
11229 0 : em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link)
11230 : {
11231 0 : uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6);
11232 0 : uint32_t status = E1000_READ_REG(hw, STATUS);
11233 : int32_t ret_val = E1000_SUCCESS;
11234 0 : uint16_t reg;
11235 :
11236 0 : if (link && (status & E1000_STATUS_SPEED_1000)) {
11237 0 : ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11238 : ®);
11239 0 : if (ret_val)
11240 0 : return ret_val;
11241 :
11242 0 : ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11243 0 : reg & ~E1000_KMRNCTRLSTA_K1_ENABLE);
11244 0 : if (ret_val)
11245 0 : return ret_val;
11246 :
11247 0 : usec_delay(10);
11248 :
11249 0 : E1000_WRITE_REG(hw, FEXTNVM6,
11250 : fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
11251 :
11252 0 : ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11253 0 : reg);
11254 0 : } else {
11255 : /* clear FEXTNVM6 bit 8 on link down or 10/100 */
11256 0 : fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
11257 :
11258 0 : if (!link || ((status & E1000_STATUS_SPEED_100) &&
11259 0 : (status & E1000_STATUS_FD)))
11260 : goto update_fextnvm6;
11261 :
11262 0 : ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®);
11263 0 : if (ret_val)
11264 0 : return ret_val;
11265 :
11266 : /* Clear link status transmit timeout */
11267 0 : reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
11268 :
11269 0 : if (status & E1000_STATUS_SPEED_100) {
11270 : /* Set inband Tx timeout to 5x10us for 100Half */
11271 0 : reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
11272 :
11273 : /* Do not extend the K1 entry latency for 100Half */
11274 0 : fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
11275 0 : } else {
11276 : /* Set inband Tx timeout to 50x10us for 10Full/Half */
11277 0 : reg |= 50 <<
11278 : I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
11279 :
11280 : /* Extend the K1 entry latency for 10 Mbps */
11281 0 : fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
11282 : }
11283 :
11284 0 : ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg);
11285 0 : if (ret_val)
11286 0 : return ret_val;
11287 :
11288 : update_fextnvm6:
11289 0 : E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6);
11290 : }
11291 :
11292 0 : return ret_val;
11293 :
11294 0 : }
11295 :
11296 :
11297 : /***************************************************************************
11298 : * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
11299 : * @hw: pointer to the HW structure
11300 : * @gate: boolean set to TRUE to gate, FALSE to ungate
11301 : *
11302 : * Gate/ungate the automatic PHY configuration via hardware; perform
11303 : * the configuration via software instead.
11304 : ***************************************************************************/
11305 : void
11306 0 : em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate)
11307 : {
11308 : uint32_t extcnf_ctrl;
11309 :
11310 : DEBUGFUNC("em_gate_hw_phy_config_ich8lan");
11311 :
11312 0 : if (hw->mac_type != em_pch2lan)
11313 0 : return;
11314 :
11315 0 : extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
11316 :
11317 0 : if (gate)
11318 0 : extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
11319 : else
11320 0 : extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
11321 :
11322 0 : E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
11323 0 : }
11324 :
11325 : /***************************************************************************
11326 : * Configure K1 power state
11327 : *
11328 : * Configure the K1 power state based on the provided parameter.
11329 : * Assumes semaphore already acquired.
11330 : *
11331 : * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
11332 : ***************************************************************************/
11333 : int32_t
11334 0 : em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable)
11335 : {
11336 : int32_t ret_val = E1000_SUCCESS;
11337 : uint32_t ctrl_reg = 0;
11338 : uint32_t ctrl_ext = 0;
11339 : uint32_t reg = 0;
11340 0 : uint16_t kmrn_reg = 0;
11341 :
11342 0 : ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11343 : &kmrn_reg);
11344 0 : if (ret_val)
11345 : goto out;
11346 :
11347 0 : if (k1_enable)
11348 0 : kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
11349 : else
11350 0 : kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
11351 :
11352 0 : ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11353 0 : kmrn_reg);
11354 0 : if (ret_val)
11355 : goto out;
11356 :
11357 0 : usec_delay(20);
11358 0 : ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
11359 0 : ctrl_reg = E1000_READ_REG(hw, CTRL);
11360 :
11361 0 : reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
11362 0 : reg |= E1000_CTRL_FRCSPD;
11363 0 : E1000_WRITE_REG(hw, CTRL, reg);
11364 :
11365 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
11366 0 : usec_delay(20);
11367 0 : E1000_WRITE_REG(hw, CTRL, ctrl_reg);
11368 0 : E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
11369 0 : usec_delay(20);
11370 :
11371 : out:
11372 0 : return ret_val;
11373 0 : }
11374 :
11375 : /***************************************************************************
11376 : * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
11377 : * done after every PHY reset.
11378 : ***************************************************************************/
11379 : int32_t
11380 0 : em_lv_phy_workarounds_ich8lan(struct em_hw *hw)
11381 : {
11382 : int32_t ret_val = E1000_SUCCESS;
11383 : uint16_t swfw;
11384 :
11385 : DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
11386 :
11387 0 : if (hw->mac_type != em_pch2lan)
11388 : goto out;
11389 :
11390 : /* Set MDIO slow mode before any other MDIO access */
11391 0 : ret_val = em_set_mdio_slow_mode_hv(hw);
11392 :
11393 : swfw = E1000_SWFW_PHY0_SM;
11394 0 : ret_val = em_swfw_sync_acquire(hw, swfw);
11395 0 : if (ret_val)
11396 : goto out;
11397 0 : ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR,
11398 : I82579_MSE_THRESHOLD);
11399 0 : if (ret_val)
11400 : goto release;
11401 : /* set MSE higher to enable link to stay up when noise is high */
11402 0 : ret_val = em_write_phy_reg(hw, I82579_EMI_DATA,
11403 : 0x0034);
11404 0 : if (ret_val)
11405 : goto release;
11406 0 : ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR,
11407 : I82579_MSE_LINK_DOWN);
11408 0 : if (ret_val)
11409 : goto release;
11410 : /* drop link after 5 times MSE threshold was reached */
11411 0 : ret_val = em_write_phy_reg(hw, I82579_EMI_DATA,
11412 : 0x0005);
11413 : release:
11414 0 : em_swfw_sync_release(hw, swfw);
11415 :
11416 : out:
11417 0 : return ret_val;
11418 : }
11419 :
11420 : int32_t
11421 0 : em_set_eee_i350(struct em_hw *hw)
11422 : {
11423 : int32_t ret_val = E1000_SUCCESS;
11424 : uint32_t ipcnfg, eeer;
11425 :
11426 0 : if ((hw->mac_type < em_i350) ||
11427 0 : (hw->media_type != em_media_type_copper))
11428 : goto out;
11429 0 : ipcnfg = EM_READ_REG(hw, E1000_IPCNFG);
11430 0 : eeer = EM_READ_REG(hw, E1000_EEER);
11431 :
11432 0 : if (hw->eee_enable) {
11433 0 : ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
11434 0 : eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
11435 : E1000_EEER_LPI_FC);
11436 0 : } else {
11437 0 : ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
11438 0 : eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
11439 : E1000_EEER_LPI_FC);
11440 : }
11441 0 : EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
11442 0 : EM_WRITE_REG(hw, E1000_EEER, eeer);
11443 0 : EM_READ_REG(hw, E1000_IPCNFG);
11444 0 : EM_READ_REG(hw, E1000_EEER);
11445 : out:
11446 0 : return ret_val;
11447 : }
11448 :
11449 : /***************************************************************************
11450 : * em_set_eee_pchlan - Enable/disable EEE support
11451 : * @hw: pointer to the HW structure
11452 : *
11453 : * Enable/disable EEE based on setting in dev_spec structure. The bits in
11454 : * the LPI Control register will remain set only if/when link is up.
11455 : ***************************************************************************/
11456 : int32_t
11457 0 : em_set_eee_pchlan(struct em_hw *hw)
11458 : {
11459 : int32_t ret_val = E1000_SUCCESS;
11460 0 : uint16_t phy_reg;
11461 :
11462 : DEBUGFUNC("em_set_eee_pchlan");
11463 :
11464 0 : if (hw->phy_type != em_phy_82579 &&
11465 0 : hw->phy_type != em_phy_i217)
11466 : goto out;
11467 :
11468 0 : ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg);
11469 0 : if (ret_val)
11470 : goto out;
11471 :
11472 0 : if (hw->eee_enable)
11473 0 : phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
11474 : else
11475 0 : phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
11476 :
11477 0 : ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg);
11478 : out:
11479 0 : return ret_val;
11480 0 : }
11481 :
11482 : /**
11483 : * em_initialize_M88E1512_phy - Initialize M88E1512 PHY
11484 : * @hw: pointer to the HW structure
11485 : *
11486 : * Initialize Marvell 1512 to work correctly with Avoton.
11487 : **/
11488 : int32_t
11489 0 : em_initialize_M88E1512_phy(struct em_hw *hw)
11490 : {
11491 : int32_t ret_val = E1000_SUCCESS;
11492 :
11493 : DEBUGFUNC("e1000_initialize_M88E1512_phy");
11494 :
11495 : /* Check if this is correct PHY. */
11496 0 : if (hw->phy_id != M88E1512_E_PHY_ID)
11497 : goto out;
11498 :
11499 : /* Switch to PHY page 0xFF. */
11500 0 : ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF);
11501 0 : if (ret_val)
11502 : goto out;
11503 :
11504 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B);
11505 0 : if (ret_val)
11506 : goto out;
11507 :
11508 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144);
11509 0 : if (ret_val)
11510 : goto out;
11511 :
11512 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28);
11513 0 : if (ret_val)
11514 : goto out;
11515 :
11516 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146);
11517 0 : if (ret_val)
11518 : goto out;
11519 :
11520 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233);
11521 0 : if (ret_val)
11522 : goto out;
11523 :
11524 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D);
11525 0 : if (ret_val)
11526 : goto out;
11527 :
11528 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C);
11529 0 : if (ret_val)
11530 : goto out;
11531 :
11532 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159);
11533 0 : if (ret_val)
11534 : goto out;
11535 :
11536 : /* Switch to PHY page 0xFB. */
11537 0 : ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB);
11538 0 : if (ret_val)
11539 : goto out;
11540 :
11541 0 : ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D);
11542 0 : if (ret_val)
11543 : goto out;
11544 :
11545 : /* Switch to PHY page 0x12. */
11546 0 : ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12);
11547 0 : if (ret_val)
11548 : goto out;
11549 :
11550 : /* Change mode to SGMII-to-Copper */
11551 0 : ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001);
11552 0 : if (ret_val)
11553 : goto out;
11554 :
11555 : /* Return the PHY to page 0. */
11556 0 : ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0);
11557 0 : if (ret_val)
11558 : goto out;
11559 :
11560 0 : ret_val = em_phy_hw_reset(hw);
11561 0 : if (ret_val) {
11562 : DEBUGOUT("Error committing the PHY changes\n");
11563 0 : return ret_val;
11564 : }
11565 :
11566 0 : msec_delay(1000);
11567 : out:
11568 0 : return ret_val;
11569 0 : }
11570 :
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