Line data Source code
1 : /*******************************************************************************
2 :
3 : Copyright (c) 2001-2005, Intel Corporation
4 : All rights reserved.
5 :
6 : Redistribution and use in source and binary forms, with or without
7 : modification, are permitted provided that the following conditions are met:
8 :
9 : 1. Redistributions of source code must retain the above copyright notice,
10 : this list of conditions and the following disclaimer.
11 :
12 : 2. Redistributions in binary form must reproduce the above copyright
13 : notice, this list of conditions and the following disclaimer in the
14 : documentation and/or other materials provided with the distribution.
15 :
16 : 3. Neither the name of the Intel Corporation nor the names of its
17 : contributors may be used to endorse or promote products derived from
18 : this software without specific prior written permission.
19 :
20 : THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 : AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 : IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 : ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 : LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 : CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 : SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 : INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 : CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 : ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 : POSSIBILITY OF SUCH DAMAGE.
31 :
32 : *******************************************************************************/
33 :
34 : /* $OpenBSD: ixgb_hw.c,v 1.8 2015/11/24 17:11:40 mpi Exp $ */
35 :
36 : /* ixgb_hw.c
37 : * Shared functions for accessing and configuring the adapter
38 : */
39 :
40 : #include <sys/param.h>
41 : #include <sys/systm.h>
42 : #include <sys/sockio.h>
43 : #include <sys/mbuf.h>
44 : #include <sys/malloc.h>
45 : #include <sys/kernel.h>
46 : #include <sys/device.h>
47 : #include <sys/socket.h>
48 :
49 : #include <net/if.h>
50 : #include <net/if_media.h>
51 :
52 : #include <netinet/in.h>
53 : #include <netinet/if_ether.h>
54 :
55 : #include <uvm/uvm_extern.h>
56 :
57 : #include <dev/pci/pcireg.h>
58 : #include <dev/pci/pcivar.h>
59 :
60 : #include <dev/pci/ixgb_hw.h>
61 : #include <dev/pci/ixgb_ids.h>
62 :
63 : /* Local function prototypes */
64 :
65 : static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr);
66 :
67 : static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
68 :
69 : static void ixgb_get_bus_info(struct ixgb_hw *hw);
70 :
71 : static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
72 :
73 : static void ixgb_optics_reset(struct ixgb_hw *hw);
74 :
75 : static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
76 :
77 : static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
78 :
79 : uint32_t ixgb_mac_reset(struct ixgb_hw *hw);
80 :
81 : uint32_t
82 0 : ixgb_mac_reset(struct ixgb_hw *hw)
83 : {
84 : uint32_t ctrl_reg;
85 :
86 : ctrl_reg = IXGB_CTRL0_RST |
87 : IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
88 : IXGB_CTRL0_SDP2_DIR |
89 : IXGB_CTRL0_SDP1_DIR |
90 : IXGB_CTRL0_SDP0_DIR |
91 : IXGB_CTRL0_SDP3 | /* Initial value 1101 */
92 : IXGB_CTRL0_SDP2 |
93 : IXGB_CTRL0_SDP0;
94 :
95 : #ifdef HP_ZX1
96 : /* Workaround for 82597EX reset errata */
97 : IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
98 : #else
99 0 : IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
100 : #endif
101 :
102 : /* Delay a few ms just to allow the reset to complete */
103 0 : msec_delay(IXGB_DELAY_AFTER_RESET);
104 0 : ctrl_reg = IXGB_READ_REG(hw, CTRL0);
105 : #ifdef DBG
106 : /* Make sure the self-clearing global reset bit did self clear */
107 0 : ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
108 : #endif
109 :
110 0 : if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) {
111 : ctrl_reg = /* Enable interrupt from XFP and SerDes */
112 : IXGB_CTRL1_GPI0_EN |
113 : IXGB_CTRL1_SDP6_DIR |
114 : IXGB_CTRL1_SDP7_DIR |
115 : IXGB_CTRL1_SDP6 |
116 : IXGB_CTRL1_SDP7;
117 0 : IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
118 0 : ixgb_optics_reset_bcm(hw);
119 0 : }
120 :
121 0 : if (hw->phy_type == ixgb_phy_type_txn17401)
122 0 : ixgb_optics_reset(hw);
123 :
124 0 : return ctrl_reg;
125 : }
126 :
127 : /******************************************************************************
128 : * Reset the transmit and receive units; mask and clear all interrupts.
129 : *
130 : * hw - Struct containing variables accessed by shared code
131 : *****************************************************************************/
132 : boolean_t
133 0 : ixgb_adapter_stop(struct ixgb_hw *hw)
134 : {
135 : uint32_t ctrl_reg;
136 : uint32_t icr_reg;
137 :
138 : DEBUGFUNC("ixgb_adapter_stop");
139 :
140 : /* If we are stopped or resetting exit gracefully and wait to be
141 : * started again before accessing the hardware. */
142 0 : if(hw->adapter_stopped) {
143 : DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
144 0 : return FALSE;
145 : }
146 :
147 : /* Set the Adapter Stopped flag so other driver functions stop touching
148 : * the Hardware. */
149 0 : hw->adapter_stopped = TRUE;
150 :
151 : /* Clear interrupt mask to stop board from generating interrupts */
152 : DEBUGOUT("Masking off all interrupts\n");
153 0 : IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
154 :
155 : /* Disable the Transmit and Receive units. Then delay to allow any
156 : * pending transactions to complete before we hit the MAC with the
157 : * global reset. */
158 0 : IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
159 0 : IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
160 0 : msec_delay(IXGB_DELAY_BEFORE_RESET);
161 :
162 : /* Issue a global reset to the MAC. This will reset the chip's
163 : * transmit, receive, DMA, and link units. It will not effect the
164 : * current PCI configuration. The global reset bit is self- clearing,
165 : * and should clear within a microsecond. */
166 : DEBUGOUT("Issuing a global reset to MAC\n");
167 :
168 0 : ctrl_reg = ixgb_mac_reset(hw);
169 :
170 : /* Clear interrupt mask to stop board from generating interrupts */
171 : DEBUGOUT("Masking off all interrupts\n");
172 0 : IXGB_WRITE_REG(hw, IMC, 0xffffffff);
173 :
174 : /* Clear any pending interrupt events. */
175 0 : icr_reg = IXGB_READ_REG(hw, ICR);
176 :
177 0 : return (ctrl_reg & IXGB_CTRL0_RST);
178 0 : }
179 :
180 : /******************************************************************************
181 : * Identifies the vendor of the optics module on the adapter. The SR adapters
182 : * support two different types of XPAK optics, so it is necessary to determine
183 : * which optics are present before applying any optics-specific workarounds.
184 : *
185 : * hw - Struct containing variables accessed by shared code.
186 : *
187 : * Returns: the vendor of the XPAK optics module.
188 : *****************************************************************************/
189 : static ixgb_xpak_vendor
190 0 : ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
191 : {
192 : uint32_t i;
193 0 : uint16_t vendor_name[5];
194 : ixgb_xpak_vendor xpak_vendor;
195 :
196 : DEBUGFUNC("ixgb_identify_xpak_vendor");
197 :
198 : /* Read the first few bytes of the vendor string from the XPAK NVR
199 : * registers. These are standard XENPAK/XPAK registers, so all XPAK
200 : * devices should implement them. */
201 0 : for(i = 0; i < 5; i++) {
202 0 : vendor_name[i] =
203 0 : ixgb_read_phy_reg(hw, MDIO_PMA_PMD_XPAK_VENDOR_NAME + i,
204 : IXGB_PHY_ADDRESS, MDIO_PMA_PMD_DID);
205 : }
206 :
207 : /* Determine the actual vendor */
208 0 : if (vendor_name[0] == 'I' &&
209 0 : vendor_name[1] == 'N' &&
210 0 : vendor_name[2] == 'T' &&
211 0 : vendor_name[3] == 'E' &&
212 0 : vendor_name[4] == 'L') {
213 : xpak_vendor = ixgb_xpak_vendor_intel;
214 0 : }
215 : else {
216 : xpak_vendor = ixgb_xpak_vendor_infineon;
217 : }
218 0 : return (xpak_vendor);
219 0 : }
220 :
221 : /******************************************************************************
222 : * Determine the physical layer module on the adapter.
223 : *
224 : * hw - Struct containing variables accessed by shared code. The device_id
225 : * field must be (correctly) populated before calling this routine.
226 : *
227 : * Returns: the phy type of the adapter.
228 : *****************************************************************************/
229 : static ixgb_phy_type
230 0 : ixgb_identify_phy(struct ixgb_hw *hw)
231 : {
232 : ixgb_phy_type phy_type;
233 : ixgb_xpak_vendor xpak_vendor;
234 :
235 : DEBUGFUNC("ixgb_identify_phy");
236 :
237 : /* Infer the transceiver/phy type from the device id */
238 0 : switch(hw->device_id) {
239 : case IXGB_DEVICE_ID_82597EX:
240 : DEBUGOUT("Identified TXN17401 optics\n");
241 : phy_type = ixgb_phy_type_txn17401;
242 0 : break;
243 :
244 : case IXGB_DEVICE_ID_82597EX_SR:
245 : /* The SR adapters carry two different types of XPAK optics
246 : * modules; read the vendor identifier to determine the exact
247 : * type of optics. */
248 0 : xpak_vendor = ixgb_identify_xpak_vendor(hw);
249 0 : if(xpak_vendor == ixgb_xpak_vendor_intel) {
250 : DEBUGOUT("Identified TXN17201 optics\n");
251 : phy_type = ixgb_phy_type_txn17201;
252 0 : } else {
253 : DEBUGOUT("Identified G6005 optics\n");
254 : phy_type = ixgb_phy_type_g6005;
255 : }
256 : break;
257 :
258 : case IXGB_DEVICE_ID_82597EX_LR:
259 : DEBUGOUT("Identified G6104 optics\n");
260 : phy_type = ixgb_phy_type_g6104;
261 0 : break;
262 :
263 : case IXGB_DEVICE_ID_82597EX_CX4:
264 : DEBUGOUT("Identified CX4\n");
265 0 : xpak_vendor = ixgb_identify_xpak_vendor(hw);
266 0 : if(xpak_vendor == ixgb_xpak_vendor_intel) {
267 : DEBUGOUT("Identified TXN17201 optics\n");
268 : phy_type = ixgb_phy_type_txn17201;
269 0 : } else {
270 : DEBUGOUT("Identified G6005 optics\n");
271 : phy_type = ixgb_phy_type_g6005;
272 : }
273 : break;
274 :
275 : default:
276 : DEBUGOUT("Unknown physical layer module\n");
277 : phy_type = ixgb_phy_type_unknown;
278 0 : break;
279 : }
280 :
281 : /* update phy type for sun specific board */
282 0 : if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID)
283 0 : phy_type = ixgb_phy_type_bcm;
284 :
285 0 : return (phy_type);
286 : }
287 :
288 : /******************************************************************************
289 : * Performs basic configuration of the adapter.
290 : *
291 : * hw - Struct containing variables accessed by shared code
292 : *
293 : * Resets the controller.
294 : * Reads and validates the EEPROM.
295 : * Initializes the receive address registers.
296 : * Initializes the multicast table.
297 : * Clears all on-chip counters.
298 : * Calls routine to setup flow control settings.
299 : * Leaves the transmit and receive units disabled and uninitialized.
300 : *
301 : * Returns:
302 : * TRUE if successful,
303 : * FALSE if unrecoverable problems were encountered.
304 : *****************************************************************************/
305 : boolean_t
306 0 : ixgb_init_hw(struct ixgb_hw *hw)
307 : {
308 : uint32_t i;
309 : uint32_t ctrl_reg;
310 : boolean_t status;
311 :
312 : DEBUGFUNC("ixgb_init_hw");
313 :
314 : /* Issue a global reset to the MAC. This will reset the chip's
315 : * transmit, receive, DMA, and link units. It will not effect the
316 : * current PCI configuration. The global reset bit is self- clearing,
317 : * and should clear within a microsecond. */
318 : DEBUGOUT("Issuing a global reset to MAC\n");
319 :
320 0 : ctrl_reg = ixgb_mac_reset(hw);
321 :
322 : DEBUGOUT("Issuing an EE reset to MAC\n");
323 : #ifdef HP_ZX1
324 : /* Workaround for 82597EX reset errata */
325 : IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
326 : #else
327 0 : IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
328 : #endif
329 :
330 : /* Delay a few ms just to allow the reset to complete */
331 0 : msec_delay(IXGB_DELAY_AFTER_EE_RESET);
332 :
333 0 : if(ixgb_get_eeprom_data(hw) == FALSE) {
334 0 : return (FALSE);
335 : }
336 :
337 : /* Use the device id to determine the type of phy/transceiver. */
338 0 : hw->device_id = ixgb_get_ee_device_id(hw);
339 0 : hw->phy_type = ixgb_identify_phy(hw);
340 :
341 : /* Setup the receive addresses. Receive Address Registers (RARs 0 -
342 : * 15). */
343 0 : ixgb_init_rx_addrs(hw);
344 :
345 : /*
346 : * Check that a valid MAC address has been set.
347 : * If it is not valid, we fail hardware init.
348 : */
349 0 : if(!mac_addr_valid(hw->curr_mac_addr)) {
350 : DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
351 0 : return (FALSE);
352 : }
353 :
354 : /* tell the routines in this file they can access hardware again */
355 0 : hw->adapter_stopped = FALSE;
356 :
357 : /* Fill in the bus_info structure */
358 0 : ixgb_get_bus_info(hw);
359 :
360 : /* Zero out the Multicast HASH table */
361 : DEBUGOUT("Zeroing the MTA\n");
362 0 : for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
363 0 : IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
364 :
365 : /* Zero out the VLAN Filter Table Array */
366 0 : ixgb_clear_vfta(hw);
367 :
368 : /* Zero all of the hardware counters */
369 0 : ixgb_clear_hw_cntrs(hw);
370 :
371 : /* Call a subroutine to setup flow control. */
372 0 : status = ixgb_setup_fc(hw);
373 :
374 : /* 82597EX errata: Call check-for-link in case lane deskew is locked */
375 0 : ixgb_check_for_link(hw);
376 :
377 0 : return (status);
378 0 : }
379 :
380 : /******************************************************************************
381 : * Initializes receive address filters.
382 : *
383 : * hw - Struct containing variables accessed by shared code
384 : *
385 : * Places the MAC address in receive address register 0 and clears the rest
386 : * of the receive addresss registers. Clears the multicast table. Assumes
387 : * the receiver is in reset when the routine is called.
388 : *****************************************************************************/
389 : void
390 0 : ixgb_init_rx_addrs(struct ixgb_hw *hw)
391 : {
392 : uint32_t i;
393 :
394 : DEBUGFUNC("ixgb_init_rx_addrs");
395 :
396 : /*
397 : * If the current mac address is valid, assume it is a software override
398 : * to the permanent address.
399 : * Otherwise, use the permanent address from the eeprom.
400 : */
401 0 : if(!mac_addr_valid(hw->curr_mac_addr)) {
402 :
403 : /* Get the MAC address from the eeprom for later reference */
404 0 : ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
405 :
406 : DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
407 : hw->curr_mac_addr[0], hw->curr_mac_addr[1],
408 : hw->curr_mac_addr[2]);
409 : DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
410 : hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
411 0 : } else {
412 :
413 : /* Setup the receive address. */
414 : DEBUGOUT("Overriding MAC Address in RAR[0]\n");
415 : DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
416 : hw->curr_mac_addr[0], hw->curr_mac_addr[1],
417 : hw->curr_mac_addr[2]);
418 : DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3],
419 : hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
420 :
421 0 : ixgb_rar_set(hw, hw->curr_mac_addr, 0);
422 : }
423 :
424 : /* Zero out the other 15 receive addresses. */
425 : DEBUGOUT("Clearing RAR[1-15]\n");
426 0 : for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
427 0 : IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
428 0 : IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
429 : }
430 :
431 : return;
432 0 : }
433 :
434 : /******************************************************************************
435 : * Updates the MAC's list of multicast addresses.
436 : *
437 : * hw - Struct containing variables accessed by shared code
438 : * mc_addr_list - the list of new multicast addresses
439 : * mc_addr_count - number of addresses
440 : * pad - number of bytes between addresses in the list
441 : *
442 : * The given list replaces any existing list. Clears the last 15 receive
443 : * address registers and the multicast table. Uses receive address registers
444 : * for the first 15 multicast addresses, and hashes the rest into the
445 : * multicast table.
446 : *****************************************************************************/
447 : void
448 0 : ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list,
449 : uint32_t mc_addr_count, uint32_t pad)
450 : {
451 : uint32_t hash_value;
452 : uint32_t i;
453 : uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
454 :
455 : DEBUGFUNC("ixgb_mc_addr_list_update");
456 :
457 : /* Set the new number of MC addresses that we are being requested to
458 : * use. */
459 0 : hw->num_mc_addrs = mc_addr_count;
460 :
461 : /* Clear RAR[1-15] */
462 : DEBUGOUT(" Clearing RAR[1-15]\n");
463 0 : for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
464 0 : IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
465 0 : IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
466 : }
467 :
468 : /* Clear the MTA */
469 : DEBUGOUT(" Clearing MTA\n");
470 0 : for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
471 0 : IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
472 : }
473 :
474 : /* Add the new addresses */
475 0 : for(i = 0; i < mc_addr_count; i++) {
476 : DEBUGOUT(" Adding the multicast addresses:\n");
477 : DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
478 : mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
479 : mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1],
480 : mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2],
481 : mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3],
482 : mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4],
483 : mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]);
484 :
485 : /* Place this multicast address in the RAR if there is room, *
486 : * else put it in the MTA */
487 0 : if(rar_used_count < IXGB_RAR_ENTRIES) {
488 0 : ixgb_rar_set(hw,
489 : mc_addr_list +
490 : (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
491 : rar_used_count);
492 : DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
493 0 : rar_used_count++;
494 0 : } else {
495 : hash_value =
496 0 : ixgb_hash_mc_addr(hw,
497 : mc_addr_list +
498 : (i *
499 : (IXGB_ETH_LENGTH_OF_ADDRESS +
500 : pad)));
501 :
502 : DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
503 :
504 0 : ixgb_mta_set(hw, hash_value);
505 : }
506 : }
507 :
508 : DEBUGOUT("MC Update Complete\n");
509 : return;
510 0 : }
511 :
512 : /******************************************************************************
513 : * Hashes an address to determine its location in the multicast table
514 : *
515 : * hw - Struct containing variables accessed by shared code
516 : * mc_addr - the multicast address to hash
517 : *
518 : * Returns:
519 : * The hash value
520 : *****************************************************************************/
521 : static uint32_t
522 0 : ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr)
523 : {
524 : uint32_t hash_value = 0;
525 :
526 : DEBUGFUNC("ixgb_hash_mc_addr");
527 :
528 : /* The portion of the address that is used for the hash table is
529 : * determined by the mc_filter_type setting. */
530 0 : switch(hw->mc_filter_type) {
531 : /* [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB MSB -
532 : * According to H/W docs */
533 : case 0:
534 : /* [47:36] i.e. 0x563 for above example address */
535 : hash_value =
536 0 : ((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4));
537 0 : break;
538 : case 1: /* [46:35] i.e. 0xAC6 for above
539 : * example address */
540 : hash_value =
541 0 : ((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5));
542 0 : break;
543 : case 2: /* [45:34] i.e. 0x5D8 for above
544 : * example address */
545 : hash_value =
546 0 : ((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6));
547 0 : break;
548 : case 3: /* [43:32] i.e. 0x634 for above
549 : * example address */
550 0 : hash_value = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8));
551 0 : break;
552 : default:
553 : /* Invalid mc_filter_type, what should we do? */
554 : DEBUGOUT("MC filter type param set incorrectly\n");
555 0 : ASSERT(0);
556 : break;
557 : }
558 :
559 0 : hash_value &= 0xFFF;
560 0 : return (hash_value);
561 : }
562 :
563 : /******************************************************************************
564 : * Sets the bit in the multicast table corresponding to the hash value.
565 : *
566 : * hw - Struct containing variables accessed by shared code
567 : * hash_value - Multicast address hash value
568 : *****************************************************************************/
569 : static void
570 0 : ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value)
571 : {
572 : uint32_t hash_bit, hash_reg;
573 : uint32_t mta_reg;
574 :
575 : /* The MTA is a register array of 128 32-bit registers. It is treated
576 : * like an array of 4096 bits. We want to set bit
577 : * BitArray[hash_value]. So we figure out what register the bit is in,
578 : * read it, OR in the new bit, then write back the new value. The
579 : * register is determined by the upper 7 bits of the hash value and the
580 : * bit within that register are determined by the lower 5 bits of the
581 : * value. */
582 0 : hash_reg = (hash_value >> 5) & 0x7F;
583 0 : hash_bit = hash_value & 0x1F;
584 0 : mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
585 0 : mta_reg |= (1 << hash_bit);
586 0 : IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
587 : return;
588 0 : }
589 :
590 : /******************************************************************************
591 : * Puts an ethernet address into a receive address register.
592 : *
593 : * hw - Struct containing variables accessed by shared code
594 : * addr - Address to put into receive address register
595 : * index - Receive address register to write
596 : *****************************************************************************/
597 : void
598 0 : ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index)
599 : {
600 : uint32_t rar_low, rar_high;
601 :
602 : DEBUGFUNC("ixgb_rar_set");
603 :
604 : /* HW expects these in little endian so we reverse the byte order from
605 : * network order (big endian) to little endian */
606 0 : rar_low = ((uint32_t)addr[0] |
607 0 : ((uint32_t)addr[1] << 8) |
608 0 : ((uint32_t)addr[2] << 16) |
609 0 : ((uint32_t)addr[3] << 24));
610 :
611 0 : rar_high = ((uint32_t)addr[4] |
612 0 : ((uint32_t)addr[5] << 8) |
613 : IXGB_RAH_AV);
614 :
615 0 : IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
616 0 : IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
617 : return;
618 0 : }
619 :
620 : /******************************************************************************
621 : * Writes a value to the specified offset in the VLAN filter table.
622 : *
623 : * hw - Struct containing variables accessed by shared code
624 : * offset - Offset in VLAN filer table to write
625 : * value - Value to write into VLAN filter table
626 : *****************************************************************************/
627 : void
628 0 : ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value)
629 : {
630 0 : IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
631 0 : return;
632 : }
633 :
634 : /******************************************************************************
635 : * Clears the VLAN filer table
636 : *
637 : * hw - Struct containing variables accessed by shared code
638 : *****************************************************************************/
639 : void
640 0 : ixgb_clear_vfta(struct ixgb_hw *hw)
641 : {
642 : uint32_t offset;
643 :
644 0 : for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
645 0 : IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
646 : return;
647 0 : }
648 :
649 : /******************************************************************************
650 : * Configures the flow control settings based on SW configuration.
651 : *
652 : * hw - Struct containing variables accessed by shared code
653 : *****************************************************************************/
654 :
655 : boolean_t
656 0 : ixgb_setup_fc(struct ixgb_hw *hw)
657 : {
658 : uint32_t ctrl_reg;
659 : uint32_t pap_reg = 0; /* by default, assume no pause time */
660 : boolean_t status = TRUE;
661 :
662 : DEBUGFUNC("ixgb_setup_fc");
663 :
664 : /* Get the current control reg 0 settings */
665 0 : ctrl_reg = IXGB_READ_REG(hw, CTRL0);
666 :
667 : /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
668 0 : ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
669 :
670 : /* The possible values of the "flow_control" parameter are:
671 : * 0: Flow control is completely disabled
672 : * 1: Rx flow control is enabled (we can receive pause frames but not send
673 : * pause frames).
674 : * 2: Tx flow control is enabled (we can send pause frames but we do not
675 : * support receiving pause frames)
676 : * 3: Both Rx and TX flow control (symmetric) are enabled.
677 : * other: Invalid. */
678 0 : switch(hw->fc.type) {
679 : case ixgb_fc_none: /* 0 */
680 : /* Set CMDC bit to disable Rx Flow control */
681 0 : ctrl_reg |= (IXGB_CTRL0_CMDC);
682 0 : break;
683 : case ixgb_fc_rx_pause: /* 1 */
684 : /* RX Flow control is enabled, and TX Flow control is disabled. */
685 0 : ctrl_reg |= (IXGB_CTRL0_RPE);
686 0 : break;
687 : case ixgb_fc_tx_pause: /* 2 */
688 : /* TX Flow control is enabled, and RX Flow control is disabled,
689 : * by a software over-ride. */
690 0 : ctrl_reg |= (IXGB_CTRL0_TPE);
691 0 : pap_reg = hw->fc.pause_time;
692 0 : break;
693 : case ixgb_fc_full: /* 3 */
694 : /* Flow control (both RX and TX) is enabled by a software
695 : * over-ride. */
696 0 : ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
697 0 : pap_reg = hw->fc.pause_time;
698 0 : break;
699 : default:
700 : /* We should never get here. The value should be 0-3. */
701 : DEBUGOUT("Flow control param set incorrectly\n");
702 0 : ASSERT(0);
703 : break;
704 : }
705 :
706 : /* Write the new settings */
707 0 : IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
708 :
709 0 : if(pap_reg != 0) {
710 0 : IXGB_WRITE_REG(hw, PAP, pap_reg);
711 0 : }
712 :
713 : /* Set the flow control receive threshold registers. Normally, these
714 : * registers will be set to a default threshold that may be adjusted
715 : * later by the driver's runtime code. However, if the ability to
716 : * transmit pause frames in not enabled, then these registers will be
717 : * set to 0. */
718 0 : if(!(hw->fc.type & ixgb_fc_tx_pause)) {
719 0 : IXGB_WRITE_REG(hw, FCRTL, 0);
720 0 : IXGB_WRITE_REG(hw, FCRTH, 0);
721 0 : } else {
722 : /* We need to set up the Receive Threshold high and low water
723 : * marks as well as (optionally) enabling the transmission of
724 : * XON frames. */
725 0 : if(hw->fc.send_xon) {
726 0 : IXGB_WRITE_REG(hw, FCRTL,
727 : (hw->fc.low_water | IXGB_FCRTL_XONE));
728 0 : } else {
729 0 : IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
730 : }
731 0 : IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
732 : }
733 0 : return (status);
734 : }
735 :
736 : /******************************************************************************
737 : * Reads a word from a device over the Management Data Interface (MDI) bus.
738 : * This interface is used to manage Physical layer devices.
739 : *
740 : * hw - Struct containing variables accessed by hw code
741 : * reg_address - Offset of device register being read.
742 : * phy_address - Address of device on MDI.
743 : *
744 : * Returns: Data word (16 bits) from MDI device.
745 : *
746 : * The 82597EX has support for several MDI access methods. This routine
747 : * uses the new protocol MDI Single Command and Address Operation.
748 : * This requires that first an address cycle command is sent, followed by a
749 : * read command.
750 : *****************************************************************************/
751 : uint16_t
752 0 : ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
753 : uint32_t phy_address, uint32_t device_type)
754 : {
755 : uint32_t i;
756 : uint32_t data;
757 : uint32_t command = 0;
758 :
759 0 : ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
760 0 : ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
761 0 : ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
762 :
763 : /* Setup and write the address cycle command */
764 0 : command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
765 0 : (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
766 0 : (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
767 : (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
768 :
769 0 : IXGB_WRITE_REG(hw, MSCA, command);
770 :
771 : /**************************************************************
772 : ** Check every 10 usec to see if the address cycle completed
773 : ** The COMMAND bit will clear when the operation is complete.
774 : ** This may take as long as 64 usecs (we'll wait 100 usecs max)
775 : ** from the CPU Write to the Ready bit assertion.
776 : **************************************************************/
777 :
778 0 : for(i = 0; i < 10; i++) {
779 0 : usec_delay(10);
780 :
781 0 : command = IXGB_READ_REG(hw, MSCA);
782 :
783 0 : if((command & IXGB_MSCA_MDI_COMMAND) == 0)
784 : break;
785 : }
786 :
787 0 : ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
788 :
789 : /* Address cycle complete, setup and write the read command */
790 : command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
791 : (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
792 0 : (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
793 : (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
794 :
795 0 : IXGB_WRITE_REG(hw, MSCA, command);
796 :
797 : /**************************************************************
798 : ** Check every 10 usec to see if the read command completed
799 : ** The COMMAND bit will clear when the operation is complete.
800 : ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
801 : ** from the CPU Write to the Ready bit assertion.
802 : **************************************************************/
803 :
804 0 : for(i = 0; i < 10; i++) {
805 0 : usec_delay(10);
806 :
807 0 : command = IXGB_READ_REG(hw, MSCA);
808 :
809 0 : if((command & IXGB_MSCA_MDI_COMMAND) == 0)
810 : break;
811 : }
812 :
813 0 : ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
814 :
815 : /* Operation is complete, get the data from the MDIO Read/Write Data
816 : * register and return. */
817 0 : data = IXGB_READ_REG(hw, MSRWD);
818 0 : data >>= IXGB_MSRWD_READ_DATA_SHIFT;
819 0 : return ((uint16_t)data);
820 : }
821 :
822 : /******************************************************************************
823 : * Writes a word to a device over the Management Data Interface (MDI) bus.
824 : * This interface is used to manage Physical layer devices.
825 : *
826 : * hw - Struct containing variables accessed by hw code
827 : * reg_address - Offset of device register being read.
828 : * phy_address - Address of device on MDI.
829 : * device_type - Also known as the Device ID or DID.
830 : * data - 16-bit value to be written
831 : *
832 : * Returns: void.
833 : *
834 : * The 82597EX has support for several MDI access methods. This routine
835 : * uses the new protocol MDI Single Command and Address Operation.
836 : * This requires that first an address cycle command is sent, followed by a
837 : * write command.
838 : *****************************************************************************/
839 : void
840 0 : ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address,
841 : uint32_t phy_address, uint32_t device_type, uint16_t data)
842 : {
843 : uint32_t i;
844 : uint32_t command = 0;
845 :
846 0 : ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
847 0 : ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
848 0 : ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
849 :
850 : /* Put the data in the MDIO Read/Write Data register */
851 0 : IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
852 :
853 : /* Setup and write the address cycle command */
854 0 : command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
855 0 : (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
856 0 : (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
857 : (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
858 :
859 0 : IXGB_WRITE_REG(hw, MSCA, command);
860 :
861 : /**************************************************************
862 : ** Check every 10 usec to see if the address cycle completed
863 : ** The COMMAND bit will clear when the operation is complete.
864 : ** This may take as long as 64 usecs (we'll wait 100 usecs max)
865 : ** from the CPU Write to the Ready bit assertion.
866 : **************************************************************/
867 :
868 0 : for(i = 0; i < 10; i++) {
869 0 : usec_delay(10);
870 :
871 0 : command = IXGB_READ_REG(hw, MSCA);
872 :
873 0 : if((command & IXGB_MSCA_MDI_COMMAND) == 0)
874 : break;
875 : }
876 :
877 0 : ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
878 :
879 : /* Address cycle complete, setup and write the write command */
880 : command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
881 : (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
882 0 : (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
883 : (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
884 :
885 0 : IXGB_WRITE_REG(hw, MSCA, command);
886 :
887 : /**************************************************************
888 : ** Check every 10 usec to see if the read command completed
889 : ** The COMMAND bit will clear when the operation is complete.
890 : ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
891 : ** from the CPU Write to the Ready bit assertion.
892 : **************************************************************/
893 :
894 0 : for(i = 0; i < 10; i++) {
895 0 : usec_delay(10);
896 :
897 0 : command = IXGB_READ_REG(hw, MSCA);
898 :
899 0 : if((command & IXGB_MSCA_MDI_COMMAND) == 0)
900 : break;
901 : }
902 :
903 0 : ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
904 :
905 : /* Operation is complete, return. */
906 0 : }
907 :
908 : /******************************************************************************
909 : * Checks to see if the link status of the hardware has changed.
910 : *
911 : * hw - Struct containing variables accessed by hw code
912 : *
913 : * Called by any function that needs to check the link status of the adapter.
914 : *****************************************************************************/
915 : void
916 0 : ixgb_check_for_link(struct ixgb_hw *hw)
917 : {
918 : uint32_t status_reg;
919 : uint32_t xpcss_reg;
920 :
921 : DEBUGFUNC("ixgb_check_for_link");
922 :
923 0 : xpcss_reg = IXGB_READ_REG(hw, XPCSS);
924 0 : status_reg = IXGB_READ_REG(hw, STATUS);
925 :
926 0 : if((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
927 0 : (status_reg & IXGB_STATUS_LU)) {
928 0 : hw->link_up = TRUE;
929 0 : } else if(!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
930 0 : (status_reg & IXGB_STATUS_LU)) {
931 : DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
932 0 : hw->link_up = ixgb_link_reset(hw);
933 0 : } else {
934 : /*
935 : * 82597EX errata. Since the lane deskew problem may prevent
936 : * link, reset the link before reporting link down.
937 : */
938 0 : hw->link_up = ixgb_link_reset(hw);
939 : }
940 : /* Anything else for 10 Gig?? */
941 0 : }
942 :
943 : /******************************************************************************
944 : * Check for a bad link condition that may have occured.
945 : * The indication is that the RFC / LFC registers may be incrementing
946 : * continually. A full adapter reset is required to recover.
947 : *
948 : * hw - Struct containing variables accessed by hw code
949 : *
950 : * Called by any function that needs to check the link status of the adapter.
951 : *****************************************************************************/
952 : boolean_t
953 0 : ixgb_check_for_bad_link(struct ixgb_hw *hw)
954 : {
955 : uint32_t newLFC, newRFC;
956 : boolean_t bad_link_returncode = FALSE;
957 :
958 0 : if(hw->phy_type == ixgb_phy_type_txn17401) {
959 0 : newLFC = IXGB_READ_REG(hw, LFC);
960 0 : newRFC = IXGB_READ_REG(hw, RFC);
961 0 : if((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) {
962 : DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n");
963 : bad_link_returncode = TRUE;
964 0 : }
965 0 : hw->lastLFC = newLFC;
966 0 : hw->lastRFC = newRFC;
967 0 : }
968 :
969 0 : return bad_link_returncode;
970 : }
971 :
972 : /******************************************************************************
973 : * Clears all hardware statistics counters.
974 : *
975 : * hw - Struct containing variables accessed by shared code
976 : *****************************************************************************/
977 : void
978 0 : ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
979 : {
980 0 : volatile uint32_t temp_reg;
981 :
982 : DEBUGFUNC("ixgb_clear_hw_cntrs");
983 :
984 : /* if we are stopped or resetting exit gracefully */
985 0 : if(hw->adapter_stopped) {
986 : DEBUGOUT("Exiting because the adapter is stopped!!!\n");
987 0 : return;
988 : }
989 :
990 0 : temp_reg = IXGB_READ_REG(hw, TPRL);
991 0 : temp_reg = IXGB_READ_REG(hw, TPRH);
992 0 : temp_reg = IXGB_READ_REG(hw, GPRCL);
993 0 : temp_reg = IXGB_READ_REG(hw, GPRCH);
994 0 : temp_reg = IXGB_READ_REG(hw, BPRCL);
995 0 : temp_reg = IXGB_READ_REG(hw, BPRCH);
996 0 : temp_reg = IXGB_READ_REG(hw, MPRCL);
997 0 : temp_reg = IXGB_READ_REG(hw, MPRCH);
998 0 : temp_reg = IXGB_READ_REG(hw, UPRCL);
999 0 : temp_reg = IXGB_READ_REG(hw, UPRCH);
1000 0 : temp_reg = IXGB_READ_REG(hw, VPRCL);
1001 0 : temp_reg = IXGB_READ_REG(hw, VPRCH);
1002 0 : temp_reg = IXGB_READ_REG(hw, JPRCL);
1003 0 : temp_reg = IXGB_READ_REG(hw, JPRCH);
1004 0 : temp_reg = IXGB_READ_REG(hw, GORCL);
1005 0 : temp_reg = IXGB_READ_REG(hw, GORCH);
1006 0 : temp_reg = IXGB_READ_REG(hw, TORL);
1007 0 : temp_reg = IXGB_READ_REG(hw, TORH);
1008 0 : temp_reg = IXGB_READ_REG(hw, RNBC);
1009 0 : temp_reg = IXGB_READ_REG(hw, RUC);
1010 0 : temp_reg = IXGB_READ_REG(hw, ROC);
1011 0 : temp_reg = IXGB_READ_REG(hw, RLEC);
1012 0 : temp_reg = IXGB_READ_REG(hw, CRCERRS);
1013 0 : temp_reg = IXGB_READ_REG(hw, ICBC);
1014 0 : temp_reg = IXGB_READ_REG(hw, ECBC);
1015 0 : temp_reg = IXGB_READ_REG(hw, MPC);
1016 0 : temp_reg = IXGB_READ_REG(hw, TPTL);
1017 0 : temp_reg = IXGB_READ_REG(hw, TPTH);
1018 0 : temp_reg = IXGB_READ_REG(hw, GPTCL);
1019 0 : temp_reg = IXGB_READ_REG(hw, GPTCH);
1020 0 : temp_reg = IXGB_READ_REG(hw, BPTCL);
1021 0 : temp_reg = IXGB_READ_REG(hw, BPTCH);
1022 0 : temp_reg = IXGB_READ_REG(hw, MPTCL);
1023 0 : temp_reg = IXGB_READ_REG(hw, MPTCH);
1024 0 : temp_reg = IXGB_READ_REG(hw, UPTCL);
1025 0 : temp_reg = IXGB_READ_REG(hw, UPTCH);
1026 0 : temp_reg = IXGB_READ_REG(hw, VPTCL);
1027 0 : temp_reg = IXGB_READ_REG(hw, VPTCH);
1028 0 : temp_reg = IXGB_READ_REG(hw, JPTCL);
1029 0 : temp_reg = IXGB_READ_REG(hw, JPTCH);
1030 0 : temp_reg = IXGB_READ_REG(hw, GOTCL);
1031 0 : temp_reg = IXGB_READ_REG(hw, GOTCH);
1032 0 : temp_reg = IXGB_READ_REG(hw, TOTL);
1033 0 : temp_reg = IXGB_READ_REG(hw, TOTH);
1034 0 : temp_reg = IXGB_READ_REG(hw, DC);
1035 0 : temp_reg = IXGB_READ_REG(hw, PLT64C);
1036 0 : temp_reg = IXGB_READ_REG(hw, TSCTC);
1037 0 : temp_reg = IXGB_READ_REG(hw, TSCTFC);
1038 0 : temp_reg = IXGB_READ_REG(hw, IBIC);
1039 0 : temp_reg = IXGB_READ_REG(hw, RFC);
1040 0 : temp_reg = IXGB_READ_REG(hw, LFC);
1041 0 : temp_reg = IXGB_READ_REG(hw, PFRC);
1042 0 : temp_reg = IXGB_READ_REG(hw, PFTC);
1043 0 : temp_reg = IXGB_READ_REG(hw, MCFRC);
1044 0 : temp_reg = IXGB_READ_REG(hw, MCFTC);
1045 0 : temp_reg = IXGB_READ_REG(hw, XONRXC);
1046 0 : temp_reg = IXGB_READ_REG(hw, XONTXC);
1047 0 : temp_reg = IXGB_READ_REG(hw, XOFFRXC);
1048 0 : temp_reg = IXGB_READ_REG(hw, XOFFTXC);
1049 0 : temp_reg = IXGB_READ_REG(hw, RJC);
1050 0 : return;
1051 0 : }
1052 :
1053 : /******************************************************************************
1054 : * Turns on the software controllable LED
1055 : *
1056 : * hw - Struct containing variables accessed by shared code
1057 : *****************************************************************************/
1058 : void
1059 0 : ixgb_led_on(struct ixgb_hw *hw)
1060 : {
1061 0 : uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1062 :
1063 : /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1064 0 : ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1065 0 : IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1066 : return;
1067 0 : }
1068 :
1069 : /******************************************************************************
1070 : * Turns off the software controllable LED
1071 : *
1072 : * hw - Struct containing variables accessed by shared code
1073 : *****************************************************************************/
1074 : void
1075 0 : ixgb_led_off(struct ixgb_hw *hw)
1076 : {
1077 0 : uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1078 :
1079 : /* To turn off the LED, set software-definable pin 0 (SDP0). */
1080 0 : ctrl0_reg |= IXGB_CTRL0_SDP0;
1081 0 : IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1082 : return;
1083 0 : }
1084 :
1085 : /******************************************************************************
1086 : * Gets the current PCI bus type, speed, and width of the hardware
1087 : *
1088 : * hw - Struct containing variables accessed by shared code
1089 : *****************************************************************************/
1090 : static void
1091 0 : ixgb_get_bus_info(struct ixgb_hw *hw)
1092 : {
1093 : uint32_t status_reg;
1094 :
1095 0 : status_reg = IXGB_READ_REG(hw, STATUS);
1096 :
1097 0 : hw->bus.type =
1098 0 : (status_reg & IXGB_STATUS_PCIX_MODE) ? ixgb_bus_type_pcix :
1099 : ixgb_bus_type_pci;
1100 :
1101 0 : if(hw->bus.type == ixgb_bus_type_pci) {
1102 0 : hw->bus.speed =
1103 0 : (status_reg & IXGB_STATUS_PCI_SPD) ? ixgb_bus_speed_66 :
1104 : ixgb_bus_speed_33;
1105 0 : } else {
1106 0 : switch(status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1107 : case IXGB_STATUS_PCIX_SPD_66:
1108 0 : hw->bus.speed = ixgb_bus_speed_66;
1109 0 : break;
1110 : case IXGB_STATUS_PCIX_SPD_100:
1111 0 : hw->bus.speed = ixgb_bus_speed_100;
1112 0 : break;
1113 : case IXGB_STATUS_PCIX_SPD_133:
1114 0 : hw->bus.speed = ixgb_bus_speed_133;
1115 0 : break;
1116 : default:
1117 0 : hw->bus.speed = ixgb_bus_speed_reserved;
1118 0 : break;
1119 : }
1120 : }
1121 :
1122 0 : hw->bus.width =
1123 0 : (status_reg & IXGB_STATUS_BUS64) ? ixgb_bus_width_64 :
1124 : ixgb_bus_width_32;
1125 :
1126 : return;
1127 0 : }
1128 :
1129 : /******************************************************************************
1130 : * Tests a MAC address to ensure it is a valid Individual Address
1131 : *
1132 : * mac_addr - pointer to MAC address.
1133 : *
1134 : *****************************************************************************/
1135 : boolean_t
1136 0 : mac_addr_valid(uint8_t *mac_addr)
1137 : {
1138 : boolean_t is_valid = TRUE;
1139 :
1140 : DEBUGFUNC("mac_addr_valid");
1141 :
1142 : /* Make sure it is not a multicast address */
1143 0 : if(IS_MULTICAST(mac_addr)) {
1144 : DEBUGOUT("MAC address is multicast\n");
1145 : is_valid = FALSE;
1146 0 : }
1147 : /* Not a broadcast address */
1148 0 : else if(IS_BROADCAST(mac_addr)) {
1149 : DEBUGOUT("MAC address is broadcast\n");
1150 : is_valid = FALSE;
1151 0 : }
1152 : /* Reject the zero address */
1153 0 : else if (mac_addr[0] == 0 &&
1154 0 : mac_addr[1] == 0 &&
1155 0 : mac_addr[2] == 0 &&
1156 0 : mac_addr[3] == 0 &&
1157 0 : mac_addr[4] == 0 &&
1158 0 : mac_addr[5] == 0) {
1159 : DEBUGOUT("MAC address is all zeros\n");
1160 : is_valid = FALSE;
1161 0 : }
1162 0 : return (is_valid);
1163 : }
1164 :
1165 : /******************************************************************************
1166 : * Resets the 10GbE link. Waits the settle time and returns the state of
1167 : * the link.
1168 : *
1169 : * hw - Struct containing variables accessed by shared code
1170 : *****************************************************************************/
1171 : boolean_t
1172 0 : ixgb_link_reset(struct ixgb_hw *hw)
1173 : {
1174 : boolean_t link_status = FALSE;
1175 : uint8_t wait_retries = MAX_RESET_ITERATIONS;
1176 : uint8_t lrst_retries = MAX_RESET_ITERATIONS;
1177 :
1178 0 : do {
1179 : /* Reset the link */
1180 0 : IXGB_WRITE_REG(hw, CTRL0,
1181 : IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1182 :
1183 : /* Wait for link-up and lane re-alignment */
1184 0 : do {
1185 0 : usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1186 : link_status =
1187 0 : ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) &&
1188 0 : (IXGB_READ_REG(hw, XPCSS) &
1189 : IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
1190 0 : } while(!link_status && --wait_retries);
1191 :
1192 0 : } while(!link_status && --lrst_retries);
1193 :
1194 0 : return link_status;
1195 : }
1196 :
1197 : /******************************************************************************
1198 : * Resets the 10GbE optics module.
1199 : *
1200 : * hw - Struct containing variables accessed by shared code
1201 : *****************************************************************************/
1202 : void
1203 0 : ixgb_optics_reset(struct ixgb_hw *hw)
1204 : {
1205 0 : if(hw->phy_type == ixgb_phy_type_txn17401) {
1206 : uint16_t mdio_reg;
1207 :
1208 0 : ixgb_write_phy_reg(hw,
1209 : MDIO_PMA_PMD_CR1,
1210 : IXGB_PHY_ADDRESS,
1211 : MDIO_PMA_PMD_DID,
1212 : MDIO_PMA_PMD_CR1_RESET);
1213 :
1214 0 : mdio_reg = ixgb_read_phy_reg(hw,
1215 : MDIO_PMA_PMD_CR1,
1216 : IXGB_PHY_ADDRESS,
1217 : MDIO_PMA_PMD_DID);
1218 0 : }
1219 :
1220 0 : return;
1221 : }
1222 :
1223 : /******************************************************************************
1224 : * Resets the 10GbE optics module for Sun variant NIC.
1225 : *
1226 : * hw - Struct containing variables accessed by shared code
1227 : *****************************************************************************/
1228 :
1229 : #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
1230 : #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
1231 : #define IXGB_BCM8704_USER_CTRL_REG 0xC800
1232 : #define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
1233 : #define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
1234 : #define IXGB_SUN_PHY_ADDRESS 0x0000
1235 : #define IXGB_SUN_PHY_RESET_DELAY 305
1236 :
1237 : static void
1238 0 : ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1239 : {
1240 0 : uint32_t ctrl = IXGB_READ_REG(hw, CTRL0);
1241 0 : ctrl &= ~IXGB_CTRL0_SDP2;
1242 0 : ctrl |= IXGB_CTRL0_SDP3;
1243 0 : IXGB_WRITE_REG(hw, CTRL0, ctrl);
1244 :
1245 : /* SerDes needs extra delay */
1246 0 : msec_delay(IXGB_SUN_PHY_RESET_DELAY);
1247 :
1248 : /* Broadcom 7408L configuration */
1249 : /* Reference clock config */
1250 0 : ixgb_write_phy_reg(hw,
1251 : IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1252 : IXGB_SUN_PHY_ADDRESS,
1253 : IXGB_BCM8704_USER_DEV3_ADDR,
1254 : IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1255 : /* we must read the registers twice */
1256 0 : ixgb_read_phy_reg(hw,
1257 : IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1258 : IXGB_SUN_PHY_ADDRESS,
1259 : IXGB_BCM8704_USER_DEV3_ADDR);
1260 0 : ixgb_read_phy_reg(hw,
1261 : IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1262 : IXGB_SUN_PHY_ADDRESS,
1263 : IXGB_BCM8704_USER_DEV3_ADDR);
1264 :
1265 0 : ixgb_write_phy_reg(hw,
1266 : IXGB_BCM8704_USER_CTRL_REG,
1267 : IXGB_SUN_PHY_ADDRESS,
1268 : IXGB_BCM8704_USER_DEV3_ADDR,
1269 : IXGB_BCM8704_USER_CTRL_REG_VAL);
1270 0 : ixgb_read_phy_reg(hw,
1271 : IXGB_BCM8704_USER_CTRL_REG,
1272 : IXGB_SUN_PHY_ADDRESS,
1273 : IXGB_BCM8704_USER_DEV3_ADDR);
1274 0 : ixgb_read_phy_reg(hw,
1275 : IXGB_BCM8704_USER_CTRL_REG,
1276 : IXGB_SUN_PHY_ADDRESS,
1277 : IXGB_BCM8704_USER_DEV3_ADDR);
1278 :
1279 : /* SerDes needs extra delay */
1280 0 : msec_delay(IXGB_SUN_PHY_RESET_DELAY);
1281 :
1282 : return;
1283 0 : }
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