Line data Source code
1 : /* $OpenBSD: ixgbe_82599.c,v 1.16 2016/11/17 21:08:27 mikeb Exp $ */
2 :
3 : /******************************************************************************
4 :
5 : Copyright (c) 2001-2015, Intel Corporation
6 : All rights reserved.
7 :
8 : Redistribution and use in source and binary forms, with or without
9 : modification, are permitted provided that the following conditions are met:
10 :
11 : 1. Redistributions of source code must retain the above copyright notice,
12 : this list of conditions and the following disclaimer.
13 :
14 : 2. Redistributions in binary form must reproduce the above copyright
15 : notice, this list of conditions and the following disclaimer in the
16 : documentation and/or other materials provided with the distribution.
17 :
18 : 3. Neither the name of the Intel Corporation nor the names of its
19 : contributors may be used to endorse or promote products derived from
20 : this software without specific prior written permission.
21 :
22 : THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 : AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 : IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 : ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 : LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 : CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 : SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 : INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 : CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 : ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 : POSSIBILITY OF SUCH DAMAGE.
33 :
34 : ******************************************************************************/
35 : /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82599.c 292674 2015-12-23 22:45:17Z sbruno $*/
36 :
37 : #include <dev/pci/ixgbe.h>
38 : #include <dev/pci/ixgbe_type.h>
39 :
40 : #define IXGBE_82599_MAX_TX_QUEUES 128
41 : #define IXGBE_82599_MAX_RX_QUEUES 128
42 : #define IXGBE_82599_RAR_ENTRIES 128
43 : #define IXGBE_82599_MC_TBL_SIZE 128
44 : #define IXGBE_82599_VFT_TBL_SIZE 128
45 : #define IXGBE_82599_RX_PB_SIZE 512
46 :
47 : int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
48 : ixgbe_link_speed *speed,
49 : bool *autoneg);
50 : enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
51 : void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
52 : void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
53 : void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
54 : void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
55 : ixgbe_link_speed speed);
56 : int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
57 : ixgbe_link_speed speed,
58 : bool autoneg_wait_to_complete);
59 : int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
60 : bool autoneg_wait_to_complete);
61 : int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
62 : ixgbe_link_speed speed,
63 : bool autoneg_wait_to_complete);
64 : int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
65 : void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
66 : int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
67 : int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,
68 : uint8_t *val);
69 : int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,
70 : uint8_t val);
71 : int32_t ixgbe_start_hw_82599(struct ixgbe_hw *hw);
72 : int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
73 : int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
74 : uint32_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
75 : int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval);
76 : int32_t prot_autoc_read_82599(struct ixgbe_hw *, bool *locked, uint32_t *reg_val);
77 : int32_t prot_autoc_write_82599(struct ixgbe_hw *, uint32_t reg_val, bool locked);
78 :
79 : void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
80 :
81 : int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
82 : ixgbe_link_speed speed,
83 : bool autoneg_wait_to_complete);
84 :
85 : int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
86 : bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
87 : int32_t ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
88 : int32_t ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
89 : uint16_t offset, uint16_t *data);
90 : int32_t ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, uint8_t byte_offset,
91 : uint8_t dev_addr, uint8_t *data);
92 : int32_t ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, uint8_t byte_offset,
93 : uint8_t dev_addr, uint8_t data);
94 :
95 0 : void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
96 : {
97 0 : struct ixgbe_mac_info *mac = &hw->mac;
98 :
99 : DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
100 :
101 : /*
102 : * enable the laser control functions for SFP+ fiber
103 : * and MNG not enabled
104 : */
105 0 : if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
106 0 : !ixgbe_mng_enabled(hw)) {
107 0 : mac->ops.disable_tx_laser =
108 : ixgbe_disable_tx_laser_multispeed_fiber;
109 0 : mac->ops.enable_tx_laser =
110 : ixgbe_enable_tx_laser_multispeed_fiber;
111 0 : mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;
112 :
113 0 : } else {
114 0 : mac->ops.disable_tx_laser = NULL;
115 0 : mac->ops.enable_tx_laser = NULL;
116 0 : mac->ops.flap_tx_laser = NULL;
117 : }
118 :
119 0 : if (hw->phy.multispeed_fiber) {
120 : /* Set up dual speed SFP+ support */
121 0 : mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
122 0 : mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;
123 0 : mac->ops.set_rate_select_speed =
124 : ixgbe_set_hard_rate_select_speed;
125 0 : if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed)
126 0 : mac->ops.set_rate_select_speed =
127 : ixgbe_set_soft_rate_select_speed;
128 : } else {
129 0 : if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
130 0 : (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
131 0 : hw->phy.smart_speed == ixgbe_smart_speed_on) &&
132 0 : !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
133 0 : mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;
134 0 : } else {
135 0 : mac->ops.setup_link = ixgbe_setup_mac_link_82599;
136 : }
137 : }
138 0 : }
139 :
140 : /**
141 : * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
142 : * @hw: pointer to hardware structure
143 : *
144 : * Initialize any function pointers that were not able to be
145 : * set during init_shared_code because the PHY/SFP type was
146 : * not known. Perform the SFP init if necessary.
147 : *
148 : **/
149 0 : int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
150 : {
151 0 : struct ixgbe_mac_info *mac = &hw->mac;
152 0 : struct ixgbe_phy_info *phy = &hw->phy;
153 : int32_t ret_val = IXGBE_SUCCESS;
154 : uint32_t esdp;
155 :
156 : DEBUGFUNC("ixgbe_init_phy_ops_82599");
157 :
158 0 : if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
159 : /* Store flag indicating I2C bus access control unit. */
160 0 : hw->phy.qsfp_shared_i2c_bus = TRUE;
161 :
162 : /* Initialize access to QSFP+ I2C bus */
163 0 : esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
164 0 : esdp |= IXGBE_ESDP_SDP0_DIR;
165 0 : esdp &= ~IXGBE_ESDP_SDP1_DIR;
166 0 : esdp &= ~IXGBE_ESDP_SDP0;
167 0 : esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
168 0 : esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
169 0 : IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
170 0 : IXGBE_WRITE_FLUSH(hw);
171 :
172 0 : phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;
173 0 : phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;
174 0 : }
175 : /* Identify the PHY or SFP module */
176 0 : ret_val = phy->ops.identify(hw);
177 0 : if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
178 : goto init_phy_ops_out;
179 :
180 : /* Setup function pointers based on detected SFP module and speeds */
181 0 : ixgbe_init_mac_link_ops_82599(hw);
182 0 : if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
183 0 : hw->phy.ops.reset = NULL;
184 :
185 : /* If copper media, overwrite with copper function pointers */
186 0 : if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
187 0 : mac->ops.setup_link = ixgbe_setup_copper_link_82599;
188 0 : mac->ops.get_link_capabilities =
189 : ixgbe_get_copper_link_capabilities_generic;
190 0 : }
191 :
192 : /* Set necessary function pointers based on PHY type */
193 0 : switch (hw->phy.type) {
194 : case ixgbe_phy_tn:
195 0 : phy->ops.setup_link = ixgbe_setup_phy_link_tnx;
196 0 : phy->ops.check_link = ixgbe_check_phy_link_tnx;
197 0 : phy->ops.get_firmware_version =
198 : ixgbe_get_phy_firmware_version_tnx;
199 0 : break;
200 : default:
201 : break;
202 : }
203 : init_phy_ops_out:
204 0 : return ret_val;
205 : }
206 :
207 0 : int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
208 : {
209 : int32_t ret_val = IXGBE_SUCCESS;
210 0 : uint16_t list_offset, data_offset, data_value;
211 :
212 : DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
213 :
214 0 : if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
215 0 : ixgbe_init_mac_link_ops_82599(hw);
216 :
217 0 : hw->phy.ops.reset = NULL;
218 :
219 0 : ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
220 : &data_offset);
221 0 : if (ret_val != IXGBE_SUCCESS)
222 : goto setup_sfp_out;
223 :
224 : /* PHY config will finish before releasing the semaphore */
225 0 : ret_val = hw->mac.ops.acquire_swfw_sync(hw,
226 : IXGBE_GSSR_MAC_CSR_SM);
227 0 : if (ret_val != IXGBE_SUCCESS) {
228 : ret_val = IXGBE_ERR_SWFW_SYNC;
229 0 : goto setup_sfp_out;
230 : }
231 :
232 0 : if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
233 : goto setup_sfp_err;
234 0 : while (data_value != 0xffff) {
235 0 : IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
236 0 : IXGBE_WRITE_FLUSH(hw);
237 0 : if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
238 : goto setup_sfp_err;
239 : }
240 :
241 : /* Release the semaphore */
242 0 : hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
243 : /* Delay obtaining semaphore again to allow FW access
244 : * prot_autoc_write uses the semaphore too.
245 : */
246 0 : msec_delay(hw->eeprom.semaphore_delay);
247 :
248 : /* Restart DSP and set SFI mode */
249 0 : ret_val = hw->mac.ops.prot_autoc_write(hw,
250 0 : hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
251 : FALSE);
252 :
253 0 : if (ret_val) {
254 : DEBUGOUT("sfp module setup not complete\n");
255 : ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
256 : goto setup_sfp_out;
257 : }
258 :
259 : }
260 :
261 : setup_sfp_out:
262 0 : return ret_val;
263 :
264 : setup_sfp_err:
265 : /* Release the semaphore */
266 0 : hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
267 : /* Delay obtaining semaphore again to allow FW access */
268 0 : msec_delay(hw->eeprom.semaphore_delay);
269 : ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
270 : "eeprom read at offset %d failed", data_offset);
271 0 : return IXGBE_ERR_PHY;
272 0 : }
273 :
274 : /**
275 : * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
276 : * @hw: pointer to hardware structure
277 : * @locked: Return the if we locked for this read.
278 : * @reg_val: Value we read from AUTOC
279 : *
280 : * For this part (82599) we need to wrap read-modify-writes with a possible
281 : * FW/SW lock. It is assumed this lock will be freed with the next
282 : * prot_autoc_write_82599().
283 : */
284 0 : int32_t prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked,
285 : uint32_t *reg_val)
286 : {
287 : int32_t ret_val;
288 :
289 0 : *locked = FALSE;
290 : /* If LESM is on then we need to hold the SW/FW semaphore. */
291 0 : if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
292 0 : ret_val = hw->mac.ops.acquire_swfw_sync(hw,
293 : IXGBE_GSSR_MAC_CSR_SM);
294 0 : if (ret_val != IXGBE_SUCCESS)
295 0 : return IXGBE_ERR_SWFW_SYNC;
296 :
297 0 : *locked = TRUE;
298 0 : }
299 :
300 0 : *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
301 0 : return IXGBE_SUCCESS;
302 0 : }
303 :
304 : /**
305 : * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
306 : * @hw: pointer to hardware structure
307 : * @reg_val: value to write to AUTOC
308 : * @locked: bool to indicate whether the SW/FW lock was already taken by
309 : * previous proc_autoc_read_82599.
310 : *
311 : * This part (82599) may need to hold the SW/FW lock around all writes to
312 : * AUTOC. Likewise after a write we need to do a pipeline reset.
313 : */
314 0 : int32_t prot_autoc_write_82599(struct ixgbe_hw *hw, uint32_t autoc, bool locked)
315 : {
316 : int32_t ret_val = IXGBE_SUCCESS;
317 :
318 : /* Blocked by MNG FW so bail */
319 0 : if (ixgbe_check_reset_blocked(hw))
320 : goto out;
321 :
322 : /* We only need to get the lock if:
323 : * - We didn't do it already (in the read part of a read-modify-write)
324 : * - LESM is enabled.
325 : */
326 0 : if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
327 0 : ret_val = hw->mac.ops.acquire_swfw_sync(hw,
328 : IXGBE_GSSR_MAC_CSR_SM);
329 0 : if (ret_val != IXGBE_SUCCESS)
330 0 : return IXGBE_ERR_SWFW_SYNC;
331 :
332 : locked = TRUE;
333 0 : }
334 :
335 0 : IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
336 0 : ret_val = ixgbe_reset_pipeline_82599(hw);
337 :
338 : out:
339 : /* Free the SW/FW semaphore as we either grabbed it here or
340 : * already had it when this function was called.
341 : */
342 0 : if (locked)
343 0 : hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
344 :
345 0 : return ret_val;
346 0 : }
347 :
348 : /**
349 : * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
350 : * @hw: pointer to hardware structure
351 : *
352 : * Initialize the function pointers and assign the MAC type for 82599.
353 : * Does not touch the hardware.
354 : **/
355 :
356 0 : int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw)
357 : {
358 0 : struct ixgbe_mac_info *mac = &hw->mac;
359 0 : struct ixgbe_phy_info *phy = &hw->phy;
360 0 : struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
361 : int32_t ret_val;
362 :
363 : DEBUGFUNC("ixgbe_init_ops_82599");
364 :
365 0 : ret_val = ixgbe_init_phy_ops_generic(hw);
366 0 : ret_val = ixgbe_init_ops_generic(hw);
367 :
368 : /* PHY */
369 0 : phy->ops.identify = ixgbe_identify_phy_82599;
370 0 : phy->ops.init = ixgbe_init_phy_ops_82599;
371 :
372 : /* MAC */
373 0 : mac->ops.reset_hw = ixgbe_reset_hw_82599;
374 0 : mac->ops.get_media_type = ixgbe_get_media_type_82599;
375 0 : mac->ops.get_supported_physical_layer =
376 : ixgbe_get_supported_physical_layer_82599;
377 0 : mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;
378 0 : mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;
379 0 : mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;
380 0 : mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;
381 0 : mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;
382 0 : mac->ops.start_hw = ixgbe_start_hw_82599;
383 :
384 0 : mac->ops.prot_autoc_read = prot_autoc_read_82599;
385 0 : mac->ops.prot_autoc_write = prot_autoc_write_82599;
386 :
387 : /* RAR, Multicast, VLAN */
388 0 : mac->ops.set_vmdq = ixgbe_set_vmdq_generic;
389 0 : mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;
390 0 : mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;
391 0 : mac->rar_highwater = 1;
392 0 : mac->ops.set_vfta = ixgbe_set_vfta_generic;
393 0 : mac->ops.set_vlvf = ixgbe_set_vlvf_generic;
394 0 : mac->ops.clear_vfta = ixgbe_clear_vfta_generic;
395 0 : mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;
396 0 : mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;
397 :
398 : /* Link */
399 0 : mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;
400 0 : mac->ops.check_link = ixgbe_check_mac_link_generic;
401 0 : mac->ops.stop_mac_link_on_d3 = ixgbe_stop_mac_link_on_d3_82599;
402 0 : ixgbe_init_mac_link_ops_82599(hw);
403 :
404 0 : mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
405 0 : mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
406 0 : mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
407 0 : mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
408 0 : mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
409 0 : mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
410 0 : mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/;
411 :
412 0 : hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
413 :
414 : /* EEPROM */
415 0 : eeprom->ops.read = ixgbe_read_eeprom_82599;
416 :
417 0 : return ret_val;
418 : }
419 :
420 : /**
421 : * ixgbe_get_link_capabilities_82599 - Determines link capabilities
422 : * @hw: pointer to hardware structure
423 : * @speed: pointer to link speed
424 : * @autoneg: TRUE when autoneg or autotry is enabled
425 : *
426 : * Determines the link capabilities by reading the AUTOC register.
427 : **/
428 0 : int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
429 : ixgbe_link_speed *speed,
430 : bool *autoneg)
431 : {
432 : int32_t status = IXGBE_SUCCESS;
433 : uint32_t autoc = 0;
434 :
435 : DEBUGFUNC("ixgbe_get_link_capabilities_82599");
436 :
437 : /* Check if 1G SFP module. */
438 0 : if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
439 0 : hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
440 0 : hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
441 0 : hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
442 0 : hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
443 0 : hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
444 0 : *speed = IXGBE_LINK_SPEED_1GB_FULL;
445 0 : *autoneg = TRUE;
446 0 : goto out;
447 : }
448 :
449 : /*
450 : * Determine link capabilities based on the stored value of AUTOC,
451 : * which represents EEPROM defaults. If AUTOC value has not
452 : * been stored, use the current register values.
453 : */
454 0 : if (hw->mac.orig_link_settings_stored)
455 0 : autoc = hw->mac.orig_autoc;
456 : else
457 0 : autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
458 :
459 0 : switch (autoc & IXGBE_AUTOC_LMS_MASK) {
460 : case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
461 0 : *speed = IXGBE_LINK_SPEED_1GB_FULL;
462 0 : *autoneg = FALSE;
463 0 : break;
464 :
465 : case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
466 0 : *speed = IXGBE_LINK_SPEED_10GB_FULL;
467 0 : *autoneg = FALSE;
468 0 : break;
469 :
470 : case IXGBE_AUTOC_LMS_1G_AN:
471 0 : *speed = IXGBE_LINK_SPEED_1GB_FULL;
472 0 : *autoneg = TRUE;
473 0 : break;
474 :
475 : case IXGBE_AUTOC_LMS_10G_SERIAL:
476 0 : *speed = IXGBE_LINK_SPEED_10GB_FULL;
477 0 : *autoneg = FALSE;
478 0 : break;
479 :
480 : case IXGBE_AUTOC_LMS_KX4_KX_KR:
481 : case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
482 0 : *speed = IXGBE_LINK_SPEED_UNKNOWN;
483 0 : if (autoc & IXGBE_AUTOC_KR_SUPP)
484 0 : *speed |= IXGBE_LINK_SPEED_10GB_FULL;
485 0 : if (autoc & IXGBE_AUTOC_KX4_SUPP)
486 0 : *speed |= IXGBE_LINK_SPEED_10GB_FULL;
487 0 : if (autoc & IXGBE_AUTOC_KX_SUPP)
488 0 : *speed |= IXGBE_LINK_SPEED_1GB_FULL;
489 0 : *autoneg = TRUE;
490 0 : break;
491 :
492 : case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
493 0 : *speed = IXGBE_LINK_SPEED_100_FULL;
494 0 : if (autoc & IXGBE_AUTOC_KR_SUPP)
495 0 : *speed |= IXGBE_LINK_SPEED_10GB_FULL;
496 0 : if (autoc & IXGBE_AUTOC_KX4_SUPP)
497 0 : *speed |= IXGBE_LINK_SPEED_10GB_FULL;
498 0 : if (autoc & IXGBE_AUTOC_KX_SUPP)
499 0 : *speed |= IXGBE_LINK_SPEED_1GB_FULL;
500 0 : *autoneg = TRUE;
501 0 : break;
502 :
503 : case IXGBE_AUTOC_LMS_SGMII_1G_100M:
504 0 : *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
505 0 : *autoneg = FALSE;
506 0 : break;
507 :
508 : default:
509 : status = IXGBE_ERR_LINK_SETUP;
510 : goto out;
511 : break;
512 : }
513 :
514 0 : if (hw->phy.multispeed_fiber) {
515 0 : *speed |= IXGBE_LINK_SPEED_10GB_FULL |
516 : IXGBE_LINK_SPEED_1GB_FULL;
517 :
518 : /* QSFP must not enable full auto-negotiation
519 : * Limited autoneg is enabled at 1G
520 : */
521 0 : if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
522 0 : *autoneg = FALSE;
523 : else
524 0 : *autoneg = TRUE;
525 : }
526 :
527 : out:
528 0 : return status;
529 : }
530 :
531 : /**
532 : * ixgbe_get_media_type_82599 - Get media type
533 : * @hw: pointer to hardware structure
534 : *
535 : * Returns the media type (fiber, copper, backplane)
536 : **/
537 0 : enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
538 : {
539 : enum ixgbe_media_type media_type;
540 :
541 : DEBUGFUNC("ixgbe_get_media_type_82599");
542 :
543 : /* Detect if there is a copper PHY attached. */
544 0 : switch (hw->phy.type) {
545 : case ixgbe_phy_cu_unknown:
546 : case ixgbe_phy_tn:
547 : media_type = ixgbe_media_type_copper;
548 0 : goto out;
549 : default:
550 : break;
551 : }
552 :
553 0 : switch (hw->device_id) {
554 : case IXGBE_DEV_ID_82599_KX4:
555 : case IXGBE_DEV_ID_82599_KX4_MEZZ:
556 : case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
557 : case IXGBE_DEV_ID_82599_KR:
558 : case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
559 : case IXGBE_DEV_ID_82599_XAUI_LOM:
560 : /* Default device ID is mezzanine card KX/KX4 */
561 : media_type = ixgbe_media_type_backplane;
562 0 : break;
563 : case IXGBE_DEV_ID_82599_SFP:
564 : case IXGBE_DEV_ID_82599_SFP_FCOE:
565 : case IXGBE_DEV_ID_82599_SFP_EM:
566 : case IXGBE_DEV_ID_82599_SFP_SF2:
567 : case IXGBE_DEV_ID_82599_SFP_SF_QP:
568 : case IXGBE_DEV_ID_82599EN_SFP:
569 : media_type = ixgbe_media_type_fiber;
570 0 : break;
571 : case IXGBE_DEV_ID_82599_CX4:
572 : media_type = ixgbe_media_type_cx4;
573 0 : break;
574 : case IXGBE_DEV_ID_82599_T3_LOM:
575 : media_type = ixgbe_media_type_copper;
576 0 : break;
577 : case IXGBE_DEV_ID_82599_QSFP_SF_QP:
578 : media_type = ixgbe_media_type_fiber_qsfp;
579 0 : break;
580 : case IXGBE_DEV_ID_82599_BYPASS:
581 : media_type = ixgbe_media_type_fiber_fixed;
582 0 : hw->phy.multispeed_fiber = TRUE;
583 0 : break;
584 : default:
585 : media_type = ixgbe_media_type_unknown;
586 0 : break;
587 : }
588 : out:
589 0 : return media_type;
590 : }
591 :
592 : /**
593 : * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
594 : * @hw: pointer to hardware structure
595 : *
596 : * Disables link during D3 power down sequence.
597 : *
598 : **/
599 0 : void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
600 : {
601 : uint32_t autoc2_reg;
602 0 : uint16_t ee_ctrl_2 = 0;
603 :
604 : DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
605 0 : ixgbe_read_eeprom_82599(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
606 :
607 0 : if (!ixgbe_mng_present(hw) &&
608 0 : (ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT)) {
609 0 : autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
610 0 : autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
611 0 : IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
612 0 : }
613 0 : }
614 :
615 : /**
616 : * ixgbe_start_mac_link_82599 - Setup MAC link settings
617 : * @hw: pointer to hardware structure
618 : * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
619 : *
620 : * Configures link settings based on values in the ixgbe_hw struct.
621 : * Restarts the link. Performs autonegotiation if needed.
622 : **/
623 0 : int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
624 : bool autoneg_wait_to_complete)
625 : {
626 : uint32_t autoc_reg;
627 : uint32_t links_reg;
628 : uint32_t i;
629 : int32_t status = IXGBE_SUCCESS;
630 : bool got_lock = FALSE;
631 :
632 : DEBUGFUNC("ixgbe_start_mac_link_82599");
633 :
634 :
635 : /* reset_pipeline requires us to hold this lock as it writes to
636 : * AUTOC.
637 : */
638 0 : if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
639 0 : status = hw->mac.ops.acquire_swfw_sync(hw,
640 : IXGBE_GSSR_MAC_CSR_SM);
641 0 : if (status != IXGBE_SUCCESS)
642 : goto out;
643 :
644 : got_lock = TRUE;
645 0 : }
646 :
647 : /* Restart link */
648 0 : ixgbe_reset_pipeline_82599(hw);
649 :
650 0 : if (got_lock)
651 0 : hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
652 :
653 : /* Only poll for autoneg to complete if specified to do so */
654 0 : if (autoneg_wait_to_complete) {
655 0 : autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
656 0 : if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
657 0 : IXGBE_AUTOC_LMS_KX4_KX_KR ||
658 0 : (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
659 0 : IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
660 0 : (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
661 : IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
662 : links_reg = 0; /* Just in case Autoneg time = 0 */
663 0 : for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
664 0 : links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
665 0 : if (links_reg & IXGBE_LINKS_KX_AN_COMP)
666 : break;
667 0 : msec_delay(100);
668 : }
669 0 : if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
670 : status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
671 : DEBUGOUT("Autoneg did not complete.\n");
672 0 : }
673 : }
674 : }
675 :
676 : /* Add delay to filter out noises during initial link setup */
677 0 : msec_delay(50);
678 :
679 : out:
680 0 : return status;
681 : }
682 :
683 : /**
684 : * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
685 : * @hw: pointer to hardware structure
686 : *
687 : * The base drivers may require better control over SFP+ module
688 : * PHY states. This includes selectively shutting down the Tx
689 : * laser on the PHY, effectively halting physical link.
690 : **/
691 0 : void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
692 : {
693 0 : uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
694 :
695 : /* Blocked by MNG FW so bail */
696 0 : if (ixgbe_check_reset_blocked(hw))
697 0 : return;
698 :
699 : /* Disable Tx laser; allow 100us to go dark per spec */
700 0 : esdp_reg |= IXGBE_ESDP_SDP3;
701 0 : IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
702 0 : IXGBE_WRITE_FLUSH(hw);
703 0 : usec_delay(100);
704 0 : }
705 :
706 : /**
707 : * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
708 : * @hw: pointer to hardware structure
709 : *
710 : * The base drivers may require better control over SFP+ module
711 : * PHY states. This includes selectively turning on the Tx
712 : * laser on the PHY, effectively starting physical link.
713 : **/
714 0 : void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
715 : {
716 0 : uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
717 :
718 : /* Enable Tx laser; allow 100ms to light up */
719 0 : esdp_reg &= ~IXGBE_ESDP_SDP3;
720 0 : IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
721 0 : IXGBE_WRITE_FLUSH(hw);
722 0 : msec_delay(100);
723 0 : }
724 :
725 : /**
726 : * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
727 : * @hw: pointer to hardware structure
728 : *
729 : * When the driver changes the link speeds that it can support,
730 : * it sets autotry_restart to TRUE to indicate that we need to
731 : * initiate a new autotry session with the link partner. To do
732 : * so, we set the speed then disable and re-enable the Tx laser, to
733 : * alert the link partner that it also needs to restart autotry on its
734 : * end. This is consistent with TRUE clause 37 autoneg, which also
735 : * involves a loss of signal.
736 : **/
737 0 : void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
738 : {
739 : DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
740 :
741 : /* Blocked by MNG FW so bail */
742 0 : if (ixgbe_check_reset_blocked(hw))
743 : return;
744 :
745 0 : if (hw->mac.autotry_restart) {
746 0 : ixgbe_disable_tx_laser_multispeed_fiber(hw);
747 0 : ixgbe_enable_tx_laser_multispeed_fiber(hw);
748 0 : hw->mac.autotry_restart = FALSE;
749 0 : }
750 0 : }
751 :
752 : /**
753 : * ixgbe_set_hard_rate_select_speed - Set module link speed
754 : * @hw: pointer to hardware structure
755 : * @speed: link speed to set
756 : *
757 : * Set module link speed via RS0/RS1 rate select pins.
758 : */
759 0 : void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,
760 : ixgbe_link_speed speed)
761 : {
762 0 : uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
763 :
764 0 : switch (speed) {
765 : case IXGBE_LINK_SPEED_10GB_FULL:
766 0 : esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
767 0 : break;
768 : case IXGBE_LINK_SPEED_1GB_FULL:
769 0 : esdp_reg &= ~IXGBE_ESDP_SDP5;
770 0 : esdp_reg |= IXGBE_ESDP_SDP5_DIR;
771 0 : break;
772 : default:
773 : DEBUGOUT("Invalid fixed module speed\n");
774 0 : return;
775 : }
776 :
777 0 : IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
778 0 : IXGBE_WRITE_FLUSH(hw);
779 0 : }
780 :
781 : /**
782 : * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
783 : * @hw: pointer to hardware structure
784 : * @speed: new link speed
785 : * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
786 : *
787 : * Implements the Intel SmartSpeed algorithm.
788 : **/
789 0 : int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
790 : ixgbe_link_speed speed,
791 : bool autoneg_wait_to_complete)
792 : {
793 : int32_t status = IXGBE_SUCCESS;
794 0 : ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
795 : int32_t i, j;
796 0 : bool link_up = FALSE;
797 0 : uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
798 :
799 : DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
800 :
801 : /* Set autoneg_advertised value based on input link speed */
802 0 : hw->phy.autoneg_advertised = 0;
803 :
804 0 : if (speed & IXGBE_LINK_SPEED_10GB_FULL)
805 0 : hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
806 :
807 0 : if (speed & IXGBE_LINK_SPEED_1GB_FULL)
808 0 : hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
809 :
810 0 : if (speed & IXGBE_LINK_SPEED_100_FULL)
811 0 : hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
812 :
813 : /*
814 : * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
815 : * autoneg advertisement if link is unable to be established at the
816 : * highest negotiated rate. This can sometimes happen due to integrity
817 : * issues with the physical media connection.
818 : */
819 :
820 : /* First, try to get link with full advertisement */
821 0 : hw->phy.smart_speed_active = FALSE;
822 0 : for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
823 0 : status = ixgbe_setup_mac_link_82599(hw, speed,
824 : autoneg_wait_to_complete);
825 0 : if (status != IXGBE_SUCCESS)
826 : goto out;
827 :
828 : /*
829 : * Wait for the controller to acquire link. Per IEEE 802.3ap,
830 : * Section 73.10.2, we may have to wait up to 500ms if KR is
831 : * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
832 : * Table 9 in the AN MAS.
833 : */
834 0 : for (i = 0; i < 5; i++) {
835 0 : msec_delay(100);
836 :
837 : /* If we have link, just jump out */
838 0 : status = ixgbe_check_link(hw, &link_speed, &link_up,
839 : FALSE);
840 0 : if (status != IXGBE_SUCCESS)
841 : goto out;
842 :
843 0 : if (link_up)
844 : goto out;
845 : }
846 : }
847 :
848 : /*
849 : * We didn't get link. If we advertised KR plus one of KX4/KX
850 : * (or BX4/BX), then disable KR and try again.
851 : */
852 0 : if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
853 0 : ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
854 : goto out;
855 :
856 : /* Turn SmartSpeed on to disable KR support */
857 0 : hw->phy.smart_speed_active = TRUE;
858 0 : status = ixgbe_setup_mac_link_82599(hw, speed,
859 : autoneg_wait_to_complete);
860 0 : if (status != IXGBE_SUCCESS)
861 : goto out;
862 :
863 : /*
864 : * Wait for the controller to acquire link. 600ms will allow for
865 : * the AN link_fail_inhibit_timer as well for multiple cycles of
866 : * parallel detect, both 10g and 1g. This allows for the maximum
867 : * connect attempts as defined in the AN MAS table 73-7.
868 : */
869 0 : for (i = 0; i < 6; i++) {
870 0 : msec_delay(100);
871 :
872 : /* If we have link, just jump out */
873 0 : status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
874 0 : if (status != IXGBE_SUCCESS)
875 : goto out;
876 :
877 0 : if (link_up)
878 : goto out;
879 : }
880 :
881 : /* We didn't get link. Turn SmartSpeed back off. */
882 0 : hw->phy.smart_speed_active = FALSE;
883 0 : status = ixgbe_setup_mac_link_82599(hw, speed,
884 : autoneg_wait_to_complete);
885 :
886 : out:
887 0 : if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
888 : DEBUGOUT("Smartspeed has downgraded the link speed "
889 : "from the maximum advertised\n");
890 0 : return status;
891 0 : }
892 :
893 : /**
894 : * ixgbe_setup_mac_link_82599 - Set MAC link speed
895 : * @hw: pointer to hardware structure
896 : * @speed: new link speed
897 : * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
898 : *
899 : * Set the link speed in the AUTOC register and restarts link.
900 : **/
901 0 : int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
902 : ixgbe_link_speed speed,
903 : bool autoneg_wait_to_complete)
904 : {
905 0 : bool autoneg = FALSE;
906 : int32_t status = IXGBE_SUCCESS;
907 : uint32_t pma_pmd_1g, link_mode;
908 : /* holds the value of AUTOC register at this current point in time */
909 0 : uint32_t current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
910 : /* holds the cached value of AUTOC register */
911 : uint32_t orig_autoc = 0;
912 : /* Temporary variable used for comparison purposes */
913 : uint32_t autoc = current_autoc;
914 0 : uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
915 0 : uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
916 : uint32_t links_reg;
917 : uint32_t i;
918 0 : ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
919 :
920 : DEBUGFUNC("ixgbe_setup_mac_link_82599");
921 :
922 : /* Check to see if speed passed in is supported. */
923 0 : status = ixgbe_get_link_capabilities_82599(hw, &link_capabilities,
924 : &autoneg);
925 0 : if (status)
926 : goto out;
927 :
928 0 : speed &= link_capabilities;
929 :
930 0 : if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
931 : status = IXGBE_ERR_LINK_SETUP;
932 0 : goto out;
933 : }
934 :
935 : /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
936 0 : if (hw->mac.orig_link_settings_stored)
937 0 : orig_autoc = hw->mac.orig_autoc;
938 : else
939 : orig_autoc = autoc;
940 :
941 0 : link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
942 0 : pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
943 :
944 0 : if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
945 0 : link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
946 0 : link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
947 : /* Set KX4/KX/KR support according to speed requested */
948 0 : autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
949 0 : if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
950 0 : if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
951 0 : autoc |= IXGBE_AUTOC_KX4_SUPP;
952 0 : if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
953 0 : (hw->phy.smart_speed_active == FALSE))
954 0 : autoc |= IXGBE_AUTOC_KR_SUPP;
955 : }
956 0 : if (speed & IXGBE_LINK_SPEED_1GB_FULL)
957 0 : autoc |= IXGBE_AUTOC_KX_SUPP;
958 0 : } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
959 0 : (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
960 0 : link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
961 : /* Switch from 1G SFI to 10G SFI if requested */
962 0 : if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
963 0 : (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
964 0 : autoc &= ~IXGBE_AUTOC_LMS_MASK;
965 0 : autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
966 0 : }
967 0 : } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
968 0 : (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
969 : /* Switch from 10G SFI to 1G SFI if requested */
970 0 : if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
971 : (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
972 0 : autoc &= ~IXGBE_AUTOC_LMS_MASK;
973 0 : if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
974 0 : autoc |= IXGBE_AUTOC_LMS_1G_AN;
975 : else
976 : autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
977 : }
978 : }
979 :
980 0 : if (autoc != current_autoc) {
981 : /* Restart link */
982 0 : status = hw->mac.ops.prot_autoc_write(hw, autoc, FALSE);
983 0 : if (status != IXGBE_SUCCESS)
984 : goto out;
985 :
986 : /* Only poll for autoneg to complete if specified to do so */
987 0 : if (autoneg_wait_to_complete) {
988 0 : if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
989 : link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
990 : link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
991 : links_reg = 0; /*Just in case Autoneg time=0*/
992 0 : for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
993 : links_reg =
994 0 : IXGBE_READ_REG(hw, IXGBE_LINKS);
995 0 : if (links_reg & IXGBE_LINKS_KX_AN_COMP)
996 : break;
997 0 : msec_delay(100);
998 : }
999 0 : if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1000 : status =
1001 : IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1002 : DEBUGOUT("Autoneg did not complete.\n");
1003 0 : }
1004 : }
1005 : }
1006 :
1007 : /* Add delay to filter out noises during initial link setup */
1008 0 : msec_delay(50);
1009 0 : }
1010 :
1011 : out:
1012 0 : return status;
1013 0 : }
1014 :
1015 : /**
1016 : * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1017 : * @hw: pointer to hardware structure
1018 : * @speed: new link speed
1019 : * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
1020 : *
1021 : * Restarts link on PHY and MAC based on settings passed in.
1022 : **/
1023 0 : int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1024 : ixgbe_link_speed speed,
1025 : bool autoneg_wait_to_complete)
1026 : {
1027 : int32_t status;
1028 :
1029 : DEBUGFUNC("ixgbe_setup_copper_link_82599");
1030 :
1031 : /* Setup the PHY according to input speed */
1032 0 : status = hw->phy.ops.setup_link_speed(hw, speed,
1033 : autoneg_wait_to_complete);
1034 : /* Set up MAC */
1035 0 : ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1036 :
1037 0 : return status;
1038 : }
1039 :
1040 : /**
1041 : * ixgbe_reset_hw_82599 - Perform hardware reset
1042 : * @hw: pointer to hardware structure
1043 : *
1044 : * Resets the hardware by resetting the transmit and receive units, masks
1045 : * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1046 : * reset.
1047 : **/
1048 0 : int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1049 : {
1050 0 : ixgbe_link_speed link_speed;
1051 : int32_t status;
1052 : uint32_t ctrl = 0;
1053 : uint32_t i, autoc, autoc2;
1054 : uint32_t curr_lms;
1055 0 : bool link_up = FALSE;
1056 :
1057 : DEBUGFUNC("ixgbe_reset_hw_82599");
1058 :
1059 : /* Call adapter stop to disable tx/rx and clear interrupts */
1060 0 : status = hw->mac.ops.stop_adapter(hw);
1061 0 : if (status != IXGBE_SUCCESS)
1062 : goto reset_hw_out;
1063 :
1064 : /* flush pending Tx transactions */
1065 0 : ixgbe_clear_tx_pending(hw);
1066 :
1067 : /* PHY ops must be identified and initialized prior to reset */
1068 :
1069 : /* Identify PHY and related function pointers */
1070 0 : status = hw->phy.ops.init(hw);
1071 :
1072 0 : if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1073 : goto reset_hw_out;
1074 :
1075 : /* Setup SFP module if there is one present. */
1076 0 : if (hw->phy.sfp_setup_needed) {
1077 0 : status = hw->mac.ops.setup_sfp(hw);
1078 0 : hw->phy.sfp_setup_needed = FALSE;
1079 0 : }
1080 :
1081 0 : if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1082 : goto reset_hw_out;
1083 :
1084 : /* Reset PHY */
1085 0 : if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1086 0 : hw->phy.ops.reset(hw);
1087 :
1088 : /* remember AUTOC from before we reset */
1089 0 : curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1090 :
1091 : mac_reset_top:
1092 : /*
1093 : * Issue global reset to the MAC. Needs to be SW reset if link is up.
1094 : * If link reset is used when link is up, it might reset the PHY when
1095 : * mng is using it. If link is down or the flag to force full link
1096 : * reset is set, then perform link reset.
1097 : */
1098 : ctrl = IXGBE_CTRL_LNK_RST;
1099 0 : if (!hw->force_full_reset) {
1100 0 : hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1101 0 : if (link_up)
1102 0 : ctrl = IXGBE_CTRL_RST;
1103 : }
1104 :
1105 0 : ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1106 0 : IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1107 0 : IXGBE_WRITE_FLUSH(hw);
1108 :
1109 : /* Poll for reset bit to self-clear meaning reset is complete */
1110 0 : for (i = 0; i < 10; i++) {
1111 0 : usec_delay(1);
1112 0 : ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1113 0 : if (!(ctrl & IXGBE_CTRL_RST_MASK))
1114 : break;
1115 : }
1116 :
1117 0 : if (ctrl & IXGBE_CTRL_RST_MASK) {
1118 : status = IXGBE_ERR_RESET_FAILED;
1119 : DEBUGOUT("Reset polling failed to complete.\n");
1120 0 : }
1121 :
1122 0 : msec_delay(50);
1123 :
1124 : /*
1125 : * Double resets are required for recovery from certain error
1126 : * conditions. Between resets, it is necessary to stall to
1127 : * allow time for any pending HW events to complete.
1128 : */
1129 0 : if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1130 0 : hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1131 0 : goto mac_reset_top;
1132 : }
1133 :
1134 : /*
1135 : * Store the original AUTOC/AUTOC2 values if they have not been
1136 : * stored off yet. Otherwise restore the stored original
1137 : * values since the reset operation sets back to defaults.
1138 : */
1139 0 : autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1140 0 : autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1141 :
1142 : /* Enable link if disabled in NVM */
1143 0 : if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1144 0 : autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1145 0 : IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1146 0 : IXGBE_WRITE_FLUSH(hw);
1147 0 : }
1148 :
1149 0 : if (hw->mac.orig_link_settings_stored == FALSE) {
1150 0 : hw->mac.orig_autoc = autoc;
1151 0 : hw->mac.orig_autoc2 = autoc2;
1152 0 : hw->mac.orig_link_settings_stored = TRUE;
1153 0 : } else {
1154 :
1155 : /* If MNG FW is running on a multi-speed device that
1156 : * doesn't autoneg with out driver support we need to
1157 : * leave LMS in the state it was before we MAC reset.
1158 : * Likewise if we support WoL we don't want change the
1159 : * LMS state.
1160 : */
1161 0 : if (hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw))
1162 0 : hw->mac.orig_autoc =
1163 0 : (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1164 : curr_lms;
1165 :
1166 0 : if (autoc != hw->mac.orig_autoc) {
1167 0 : status = hw->mac.ops.prot_autoc_write(hw,
1168 : hw->mac.orig_autoc,
1169 : FALSE);
1170 0 : if (status != IXGBE_SUCCESS)
1171 : goto reset_hw_out;
1172 : }
1173 :
1174 0 : if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1175 0 : (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1176 0 : autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1177 0 : autoc2 |= (hw->mac.orig_autoc2 &
1178 : IXGBE_AUTOC2_UPPER_MASK);
1179 0 : IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1180 0 : }
1181 : }
1182 :
1183 : /* Store the permanent mac address */
1184 0 : hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1185 :
1186 : /*
1187 : * Store MAC address from RAR0, clear receive address registers, and
1188 : * clear the multicast table. Also reset num_rar_entries to 128,
1189 : * since we modify this value when programming the SAN MAC address.
1190 : */
1191 0 : hw->mac.num_rar_entries = 128;
1192 0 : hw->mac.ops.init_rx_addrs(hw);
1193 :
1194 : reset_hw_out:
1195 0 : return status;
1196 0 : }
1197 :
1198 : /**
1199 : * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1200 : * @hw: pointer to hardware structure
1201 : * @reg: analog register to read
1202 : * @val: read value
1203 : *
1204 : * Performs read operation to Omer analog register specified.
1205 : **/
1206 0 : int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,
1207 : uint8_t *val)
1208 : {
1209 : uint32_t core_ctl;
1210 :
1211 : DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1212 :
1213 0 : IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1214 : (reg << 8));
1215 0 : IXGBE_WRITE_FLUSH(hw);
1216 0 : usec_delay(10);
1217 0 : core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1218 0 : *val = (uint8_t)core_ctl;
1219 :
1220 0 : return IXGBE_SUCCESS;
1221 : }
1222 :
1223 : /**
1224 : * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1225 : * @hw: pointer to hardware structure
1226 : * @reg: atlas register to write
1227 : * @val: value to write
1228 : *
1229 : * Performs write operation to Omer analog register specified.
1230 : **/
1231 0 : int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg,
1232 : uint8_t val)
1233 : {
1234 : uint32_t core_ctl;
1235 :
1236 : DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1237 :
1238 0 : core_ctl = (reg << 8) | val;
1239 0 : IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1240 0 : IXGBE_WRITE_FLUSH(hw);
1241 0 : usec_delay(10);
1242 :
1243 0 : return IXGBE_SUCCESS;
1244 : }
1245 :
1246 : /**
1247 : * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1248 : * @hw: pointer to hardware structure
1249 : *
1250 : * Starts the hardware using the generic start_hw function
1251 : * and the generation start_hw function.
1252 : * Then performs revision-specific operations, if any.
1253 : **/
1254 0 : int32_t ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1255 : {
1256 : int32_t ret_val = IXGBE_SUCCESS;
1257 :
1258 : DEBUGFUNC("ixgbe_start_hw_82599");
1259 :
1260 0 : ret_val = ixgbe_start_hw_generic(hw);
1261 0 : if (ret_val != IXGBE_SUCCESS)
1262 : goto out;
1263 :
1264 0 : ret_val = ixgbe_start_hw_gen2(hw);
1265 0 : if (ret_val != IXGBE_SUCCESS)
1266 : goto out;
1267 :
1268 : /* We need to run link autotry after the driver loads */
1269 0 : hw->mac.autotry_restart = TRUE;
1270 :
1271 0 : if (ret_val == IXGBE_SUCCESS)
1272 0 : ret_val = ixgbe_verify_fw_version_82599(hw);
1273 : out:
1274 0 : return ret_val;
1275 : }
1276 :
1277 : /**
1278 : * ixgbe_identify_phy_82599 - Get physical layer module
1279 : * @hw: pointer to hardware structure
1280 : *
1281 : * Determines the physical layer module found on the current adapter.
1282 : * If PHY already detected, maintains current PHY type in hw struct,
1283 : * otherwise executes the PHY detection routine.
1284 : **/
1285 0 : int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1286 : {
1287 : int32_t status;
1288 :
1289 : DEBUGFUNC("ixgbe_identify_phy_82599");
1290 :
1291 : /* Detect PHY if not unknown - returns success if already detected. */
1292 0 : status = ixgbe_identify_phy_generic(hw);
1293 0 : if (status != IXGBE_SUCCESS) {
1294 : /* 82599 10GBASE-T requires an external PHY */
1295 0 : if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1296 0 : return status;
1297 : else
1298 0 : status = ixgbe_identify_module_generic(hw);
1299 0 : }
1300 :
1301 : /* Set PHY type none if no PHY detected */
1302 0 : if (hw->phy.type == ixgbe_phy_unknown) {
1303 0 : hw->phy.type = ixgbe_phy_none;
1304 0 : return IXGBE_SUCCESS;
1305 : }
1306 :
1307 : /* Return error if SFP module has been detected but is not supported */
1308 0 : if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1309 0 : return IXGBE_ERR_SFP_NOT_SUPPORTED;
1310 :
1311 0 : return status;
1312 0 : }
1313 :
1314 : /**
1315 : * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1316 : * @hw: pointer to hardware structure
1317 : *
1318 : * Determines physical layer capabilities of the current configuration.
1319 : **/
1320 0 : uint32_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1321 : {
1322 : uint32_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1323 0 : uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1324 0 : uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1325 0 : uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1326 0 : uint32_t pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1327 0 : uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1328 0 : uint16_t ext_ability = 0;
1329 :
1330 : DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
1331 :
1332 0 : hw->phy.ops.identify(hw);
1333 :
1334 0 : switch (hw->phy.type) {
1335 : case ixgbe_phy_tn:
1336 : case ixgbe_phy_cu_unknown:
1337 0 : hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1338 : IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1339 0 : if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1340 0 : physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1341 0 : if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1342 0 : physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1343 0 : if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1344 0 : physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1345 : goto out;
1346 : default:
1347 : break;
1348 : }
1349 :
1350 0 : switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1351 : case IXGBE_AUTOC_LMS_1G_AN:
1352 : case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1353 0 : if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1354 : physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1355 : IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1356 0 : goto out;
1357 : } else
1358 : /* SFI mode so read SFP module */
1359 : goto sfp_check;
1360 : break;
1361 : case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1362 0 : if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1363 0 : physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1364 0 : else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1365 0 : physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1366 0 : else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1367 0 : physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1368 : goto out;
1369 : break;
1370 : case IXGBE_AUTOC_LMS_10G_SERIAL:
1371 0 : if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1372 : physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1373 0 : goto out;
1374 : } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1375 : goto sfp_check;
1376 : break;
1377 : case IXGBE_AUTOC_LMS_KX4_KX_KR:
1378 : case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1379 0 : if (autoc & IXGBE_AUTOC_KX_SUPP)
1380 0 : physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1381 0 : if (autoc & IXGBE_AUTOC_KX4_SUPP)
1382 0 : physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1383 0 : if (autoc & IXGBE_AUTOC_KR_SUPP)
1384 0 : physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1385 : goto out;
1386 : break;
1387 : default:
1388 : goto out;
1389 : break;
1390 : }
1391 :
1392 : sfp_check:
1393 : /* SFP check must be done last since DA modules are sometimes used to
1394 : * test KR mode - we need to id KR mode correctly before SFP module.
1395 : * Call identify_sfp because the pluggable module may have changed */
1396 0 : physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
1397 : out:
1398 0 : return physical_layer;
1399 0 : }
1400 :
1401 : /**
1402 : * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1403 : * @hw: pointer to hardware structure
1404 : * @regval: register value to write to RXCTRL
1405 : *
1406 : * Enables the Rx DMA unit for 82599
1407 : **/
1408 0 : int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval)
1409 : {
1410 :
1411 : DEBUGFUNC("ixgbe_enable_rx_dma_82599");
1412 :
1413 : /*
1414 : * Workaround for 82599 silicon errata when enabling the Rx datapath.
1415 : * If traffic is incoming before we enable the Rx unit, it could hang
1416 : * the Rx DMA unit. Therefore, make sure the security engine is
1417 : * completely disabled prior to enabling the Rx unit.
1418 : */
1419 :
1420 0 : hw->mac.ops.disable_sec_rx_path(hw);
1421 :
1422 0 : if (regval & IXGBE_RXCTRL_RXEN)
1423 0 : ixgbe_enable_rx(hw);
1424 : else
1425 0 : ixgbe_disable_rx(hw);
1426 :
1427 0 : hw->mac.ops.enable_sec_rx_path(hw);
1428 :
1429 0 : return IXGBE_SUCCESS;
1430 : }
1431 :
1432 : /**
1433 : * ixgbe_verify_fw_version_82599 - verify FW version for 82599
1434 : * @hw: pointer to hardware structure
1435 : *
1436 : * Verifies that installed the firmware version is 0.6 or higher
1437 : * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1438 : *
1439 : * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1440 : * if the FW version is not supported.
1441 : **/
1442 0 : int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
1443 : {
1444 : int32_t status = IXGBE_ERR_EEPROM_VERSION;
1445 0 : uint16_t fw_offset, fw_ptp_cfg_offset;
1446 0 : uint16_t fw_version;
1447 :
1448 : DEBUGFUNC("ixgbe_verify_fw_version_82599");
1449 :
1450 : /* firmware check is only necessary for SFI devices */
1451 0 : if (hw->phy.media_type != ixgbe_media_type_fiber) {
1452 : status = IXGBE_SUCCESS;
1453 0 : goto fw_version_out;
1454 : }
1455 :
1456 : /* get the offset to the Firmware Module block */
1457 0 : if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
1458 : ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1459 : "eeprom read at offset %d failed", IXGBE_FW_PTR);
1460 0 : return IXGBE_ERR_EEPROM_VERSION;
1461 : }
1462 :
1463 0 : if ((fw_offset == 0) || (fw_offset == 0xFFFF))
1464 : goto fw_version_out;
1465 :
1466 : /* get the offset to the Pass Through Patch Configuration block */
1467 0 : if (hw->eeprom.ops.read(hw, (fw_offset +
1468 : IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
1469 : &fw_ptp_cfg_offset)) {
1470 : ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1471 : "eeprom read at offset %d failed",
1472 : fw_offset +
1473 : IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
1474 0 : return IXGBE_ERR_EEPROM_VERSION;
1475 : }
1476 :
1477 0 : if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
1478 : goto fw_version_out;
1479 :
1480 : /* get the firmware version */
1481 0 : if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
1482 : IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
1483 : ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1484 : "eeprom read at offset %d failed",
1485 : fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
1486 0 : return IXGBE_ERR_EEPROM_VERSION;
1487 : }
1488 :
1489 0 : if (fw_version > 0x5)
1490 0 : status = IXGBE_SUCCESS;
1491 :
1492 : fw_version_out:
1493 0 : return status;
1494 0 : }
1495 :
1496 : /**
1497 : * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
1498 : * @hw: pointer to hardware structure
1499 : *
1500 : * Returns TRUE if the LESM FW module is present and enabled. Otherwise
1501 : * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
1502 : **/
1503 0 : bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
1504 : {
1505 : bool lesm_enabled = FALSE;
1506 0 : uint16_t fw_offset, fw_lesm_param_offset, fw_lesm_state;
1507 : int32_t status;
1508 :
1509 : DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
1510 :
1511 : /* get the offset to the Firmware Module block */
1512 0 : status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
1513 :
1514 0 : if ((status != IXGBE_SUCCESS) ||
1515 0 : (fw_offset == 0) || (fw_offset == 0xFFFF))
1516 : goto out;
1517 :
1518 : /* get the offset to the LESM Parameters block */
1519 0 : status = hw->eeprom.ops.read(hw, (fw_offset +
1520 : IXGBE_FW_LESM_PARAMETERS_PTR),
1521 : &fw_lesm_param_offset);
1522 :
1523 0 : if ((status != IXGBE_SUCCESS) ||
1524 0 : (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
1525 : goto out;
1526 :
1527 : /* get the LESM state word */
1528 0 : status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
1529 : IXGBE_FW_LESM_STATE_1),
1530 : &fw_lesm_state);
1531 :
1532 0 : if ((status == IXGBE_SUCCESS) &&
1533 0 : (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
1534 0 : lesm_enabled = TRUE;
1535 :
1536 : out:
1537 0 : return lesm_enabled;
1538 0 : }
1539 :
1540 : /**
1541 : * ixgbe_read_eeprom_82599 - Read EEPROM word using
1542 : * fastest available method
1543 : *
1544 : * @hw: pointer to hardware structure
1545 : * @offset: offset of word in the EEPROM to read
1546 : * @data: word read from the EEPROM
1547 : *
1548 : * Reads a 16 bit word from the EEPROM
1549 : **/
1550 0 : int32_t ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
1551 : uint16_t offset, uint16_t *data)
1552 : {
1553 0 : struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1554 : int32_t ret_val = IXGBE_ERR_CONFIG;
1555 :
1556 : DEBUGFUNC("ixgbe_read_eeprom_82599");
1557 :
1558 : /*
1559 : * If EEPROM is detected and can be addressed using 14 bits,
1560 : * use EERD otherwise use bit bang
1561 : */
1562 0 : if ((eeprom->type == ixgbe_eeprom_spi) &&
1563 0 : (offset <= IXGBE_EERD_MAX_ADDR))
1564 0 : ret_val = ixgbe_read_eerd_generic(hw, offset, data);
1565 : else
1566 0 : ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
1567 :
1568 0 : return ret_val;
1569 : }
1570 :
1571 : /**
1572 : * ixgbe_reset_pipeline_82599 - perform pipeline reset
1573 : *
1574 : * @hw: pointer to hardware structure
1575 : *
1576 : * Reset pipeline by asserting Restart_AN together with LMS change to ensure
1577 : * full pipeline reset. This function assumes the SW/FW lock is held.
1578 : **/
1579 0 : int32_t ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
1580 : {
1581 : int32_t ret_val;
1582 : uint32_t anlp1_reg = 0;
1583 : uint32_t i, autoc_reg, autoc2_reg;
1584 :
1585 : /* Enable link if disabled in NVM */
1586 0 : autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1587 0 : if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1588 0 : autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1589 0 : IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
1590 0 : IXGBE_WRITE_FLUSH(hw);
1591 0 : }
1592 :
1593 0 : autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1594 0 : autoc_reg |= IXGBE_AUTOC_AN_RESTART;
1595 : /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
1596 0 : IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
1597 : autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
1598 : /* Wait for AN to leave state 0 */
1599 0 : for (i = 0; i < 10; i++) {
1600 0 : msec_delay(4);
1601 0 : anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
1602 0 : if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
1603 : break;
1604 : }
1605 :
1606 0 : if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
1607 : DEBUGOUT("auto negotiation not completed\n");
1608 : ret_val = IXGBE_ERR_RESET_FAILED;
1609 0 : goto reset_pipeline_out;
1610 : }
1611 :
1612 0 : ret_val = IXGBE_SUCCESS;
1613 :
1614 : reset_pipeline_out:
1615 : /* Write AUTOC register with original LMS field and Restart_AN */
1616 0 : IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
1617 0 : IXGBE_WRITE_FLUSH(hw);
1618 :
1619 0 : return ret_val;
1620 : }
1621 :
1622 : /**
1623 : * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
1624 : * @hw: pointer to hardware structure
1625 : * @byte_offset: byte offset to read
1626 : * @data: value read
1627 : *
1628 : * Performs byte read operation to SFP module's EEPROM over I2C interface at
1629 : * a specified device address.
1630 : **/
1631 0 : int32_t ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, uint8_t byte_offset,
1632 : uint8_t dev_addr, uint8_t *data)
1633 : {
1634 : uint32_t esdp;
1635 : int32_t status;
1636 : int32_t timeout = 200;
1637 :
1638 : DEBUGFUNC("ixgbe_read_i2c_byte_82599");
1639 :
1640 0 : if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
1641 : /* Acquire I2C bus ownership. */
1642 0 : esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1643 0 : esdp |= IXGBE_ESDP_SDP0;
1644 0 : IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
1645 0 : IXGBE_WRITE_FLUSH(hw);
1646 :
1647 0 : while (timeout) {
1648 0 : esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1649 0 : if (esdp & IXGBE_ESDP_SDP1)
1650 : break;
1651 :
1652 0 : msec_delay(5);
1653 0 : timeout--;
1654 : }
1655 :
1656 0 : if (!timeout) {
1657 : DEBUGOUT("Driver can't access resource,"
1658 : " acquiring I2C bus timeout.\n");
1659 : status = IXGBE_ERR_I2C;
1660 0 : goto release_i2c_access;
1661 : }
1662 : }
1663 :
1664 0 : status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
1665 :
1666 : release_i2c_access:
1667 :
1668 0 : if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
1669 : /* Release I2C bus ownership. */
1670 0 : esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1671 0 : esdp &= ~IXGBE_ESDP_SDP0;
1672 0 : IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
1673 0 : IXGBE_WRITE_FLUSH(hw);
1674 0 : }
1675 :
1676 0 : return status;
1677 : }
1678 :
1679 : /**
1680 : * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
1681 : * @hw: pointer to hardware structure
1682 : * @byte_offset: byte offset to write
1683 : * @data: value to write
1684 : *
1685 : * Performs byte write operation to SFP module's EEPROM over I2C interface at
1686 : * a specified device address.
1687 : **/
1688 0 : int32_t ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, uint8_t byte_offset,
1689 : uint8_t dev_addr, uint8_t data)
1690 : {
1691 : uint32_t esdp;
1692 : int32_t status;
1693 : int32_t timeout = 200;
1694 :
1695 : DEBUGFUNC("ixgbe_write_i2c_byte_82599");
1696 :
1697 0 : if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
1698 : /* Acquire I2C bus ownership. */
1699 0 : esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1700 0 : esdp |= IXGBE_ESDP_SDP0;
1701 0 : IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
1702 0 : IXGBE_WRITE_FLUSH(hw);
1703 :
1704 0 : while (timeout) {
1705 0 : esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1706 0 : if (esdp & IXGBE_ESDP_SDP1)
1707 : break;
1708 :
1709 0 : msec_delay(5);
1710 0 : timeout--;
1711 : }
1712 :
1713 0 : if (!timeout) {
1714 : DEBUGOUT("Driver can't access resource,"
1715 : " acquiring I2C bus timeout.\n");
1716 : status = IXGBE_ERR_I2C;
1717 0 : goto release_i2c_access;
1718 : }
1719 : }
1720 :
1721 0 : status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
1722 :
1723 : release_i2c_access:
1724 :
1725 0 : if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
1726 : /* Release I2C bus ownership. */
1727 0 : esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
1728 0 : esdp &= ~IXGBE_ESDP_SDP0;
1729 0 : IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
1730 0 : IXGBE_WRITE_FLUSH(hw);
1731 0 : }
1732 :
1733 0 : return status;
1734 : }
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