Line data Source code
1 : /* $OpenBSD: pci.c,v 1.112 2018/07/28 15:28:51 kettenis Exp $ */
2 : /* $NetBSD: pci.c,v 1.31 1997/06/06 23:48:04 thorpej Exp $ */
3 :
4 : /*
5 : * Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
6 : * Copyright (c) 1994 Charles Hannum. All rights reserved.
7 : *
8 : * Redistribution and use in source and binary forms, with or without
9 : * modification, are permitted provided that the following conditions
10 : * are met:
11 : * 1. Redistributions of source code must retain the above copyright
12 : * notice, this list of conditions and the following disclaimer.
13 : * 2. Redistributions in binary form must reproduce the above copyright
14 : * notice, this list of conditions and the following disclaimer in the
15 : * documentation and/or other materials provided with the distribution.
16 : * 3. All advertising materials mentioning features or use of this software
17 : * must display the following acknowledgement:
18 : * This product includes software developed by Charles Hannum.
19 : * 4. The name of the author may not be used to endorse or promote products
20 : * derived from this software without specific prior written permission.
21 : *
22 : * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 : * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 : * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 : * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 : * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 : * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 : * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 : * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 : * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 : * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 : */
33 :
34 : /*
35 : * PCI bus autoconfiguration.
36 : */
37 :
38 : #include <sys/param.h>
39 : #include <sys/systm.h>
40 : #include <sys/device.h>
41 : #include <sys/malloc.h>
42 :
43 : #include <dev/pci/pcireg.h>
44 : #include <dev/pci/pcivar.h>
45 : #include <dev/pci/pcidevs.h>
46 : #include <dev/pci/ppbreg.h>
47 :
48 : int pcimatch(struct device *, void *, void *);
49 : void pciattach(struct device *, struct device *, void *);
50 : int pcidetach(struct device *, int);
51 : int pciactivate(struct device *, int);
52 : void pci_suspend(struct pci_softc *);
53 : void pci_powerdown(struct pci_softc *);
54 : void pci_resume(struct pci_softc *);
55 :
56 : #define NMAPREG ((PCI_MAPREG_END - PCI_MAPREG_START) / \
57 : sizeof(pcireg_t))
58 : struct pci_dev {
59 : struct device *pd_dev;
60 : LIST_ENTRY(pci_dev) pd_next;
61 : pcitag_t pd_tag; /* pci register tag */
62 : pcireg_t pd_csr;
63 : pcireg_t pd_bhlc;
64 : pcireg_t pd_int;
65 : pcireg_t pd_map[NMAPREG];
66 : pcireg_t pd_mask[NMAPREG];
67 : pcireg_t pd_msi_mc;
68 : pcireg_t pd_msi_ma;
69 : pcireg_t pd_msi_mau32;
70 : pcireg_t pd_msi_md;
71 : int pd_pmcsr_state;
72 : int pd_vga_decode;
73 : };
74 :
75 : #ifdef APERTURE
76 : extern int allowaperture;
77 : #endif
78 :
79 : struct cfattach pci_ca = {
80 : sizeof(struct pci_softc), pcimatch, pciattach, pcidetach, pciactivate
81 : };
82 :
83 : struct cfdriver pci_cd = {
84 : NULL, "pci", DV_DULL
85 : };
86 :
87 : int pci_ndomains;
88 :
89 : struct proc *pci_vga_proc;
90 : struct pci_softc *pci_vga_pci;
91 : pcitag_t pci_vga_tag;
92 :
93 : int pci_dopm;
94 :
95 : int pciprint(void *, const char *);
96 : int pcisubmatch(struct device *, void *, void *);
97 :
98 : #ifdef PCI_MACHDEP_ENUMERATE_BUS
99 : #define pci_enumerate_bus PCI_MACHDEP_ENUMERATE_BUS
100 : #else
101 : int pci_enumerate_bus(struct pci_softc *,
102 : int (*)(struct pci_attach_args *), struct pci_attach_args *);
103 : #endif
104 : int pci_reserve_resources(struct pci_attach_args *);
105 : int pci_primary_vga(struct pci_attach_args *);
106 :
107 : /*
108 : * Important note about PCI-ISA bridges:
109 : *
110 : * Callbacks are used to configure these devices so that ISA/EISA bridges
111 : * can attach their child busses after PCI configuration is done.
112 : *
113 : * This works because:
114 : * (1) there can be at most one ISA/EISA bridge per PCI bus, and
115 : * (2) any ISA/EISA bridges must be attached to primary PCI
116 : * busses (i.e. bus zero).
117 : *
118 : * That boils down to: there can only be one of these outstanding
119 : * at a time, it is cleared when configuring PCI bus 0 before any
120 : * subdevices have been found, and it is run after all subdevices
121 : * of PCI bus 0 have been found.
122 : *
123 : * This is needed because there are some (legacy) PCI devices which
124 : * can show up as ISA/EISA devices as well (the prime example of which
125 : * are VGA controllers). If you attach ISA from a PCI-ISA/EISA bridge,
126 : * and the bridge is seen before the video board is, the board can show
127 : * up as an ISA device, and that can (bogusly) complicate the PCI device's
128 : * attach code, or make the PCI device not be properly attached at all.
129 : *
130 : * We use the generic config_defer() facility to achieve this.
131 : */
132 :
133 : int
134 0 : pcimatch(struct device *parent, void *match, void *aux)
135 : {
136 0 : struct cfdata *cf = match;
137 0 : struct pcibus_attach_args *pba = aux;
138 :
139 0 : if (strcmp(pba->pba_busname, cf->cf_driver->cd_name))
140 0 : return (0);
141 :
142 : /* Check the locators */
143 0 : if (cf->pcibuscf_bus != PCIBUS_UNK_BUS &&
144 0 : cf->pcibuscf_bus != pba->pba_bus)
145 0 : return (0);
146 :
147 : /* sanity */
148 0 : if (pba->pba_bus < 0 || pba->pba_bus > 255)
149 0 : return (0);
150 :
151 : /*
152 : * XXX check other (hardware?) indicators
153 : */
154 :
155 0 : return (1);
156 0 : }
157 :
158 : void
159 0 : pciattach(struct device *parent, struct device *self, void *aux)
160 : {
161 0 : struct pcibus_attach_args *pba = aux;
162 0 : struct pci_softc *sc = (struct pci_softc *)self;
163 :
164 0 : pci_attach_hook(parent, self, pba);
165 :
166 0 : printf("\n");
167 :
168 0 : LIST_INIT(&sc->sc_devs);
169 :
170 0 : sc->sc_iot = pba->pba_iot;
171 0 : sc->sc_memt = pba->pba_memt;
172 0 : sc->sc_dmat = pba->pba_dmat;
173 0 : sc->sc_pc = pba->pba_pc;
174 0 : sc->sc_flags = pba->pba_flags;
175 0 : sc->sc_ioex = pba->pba_ioex;
176 0 : sc->sc_memex = pba->pba_memex;
177 0 : sc->sc_pmemex = pba->pba_pmemex;
178 0 : sc->sc_busex = pba->pba_busex;
179 0 : sc->sc_domain = pba->pba_domain;
180 0 : sc->sc_bus = pba->pba_bus;
181 0 : sc->sc_bridgetag = pba->pba_bridgetag;
182 0 : sc->sc_bridgeih = pba->pba_bridgeih;
183 0 : sc->sc_maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus);
184 0 : sc->sc_intrswiz = pba->pba_intrswiz;
185 0 : sc->sc_intrtag = pba->pba_intrtag;
186 :
187 : /* Reserve our own bus number. */
188 0 : if (sc->sc_busex)
189 0 : extent_alloc_region(sc->sc_busex, sc->sc_bus, 1, EX_NOWAIT);
190 :
191 0 : pci_enumerate_bus(sc, pci_reserve_resources, NULL);
192 :
193 : /* Find the VGA device that's currently active. */
194 0 : if (pci_enumerate_bus(sc, pci_primary_vga, NULL))
195 0 : pci_vga_pci = sc;
196 :
197 0 : pci_enumerate_bus(sc, NULL, NULL);
198 0 : }
199 :
200 : int
201 0 : pcidetach(struct device *self, int flags)
202 : {
203 0 : return pci_detach_devices((struct pci_softc *)self, flags);
204 : }
205 :
206 : int
207 0 : pciactivate(struct device *self, int act)
208 : {
209 : int rv = 0;
210 :
211 0 : switch (act) {
212 : case DVACT_SUSPEND:
213 0 : rv = config_activate_children(self, act);
214 0 : pci_suspend((struct pci_softc *)self);
215 0 : break;
216 : case DVACT_RESUME:
217 0 : pci_resume((struct pci_softc *)self);
218 0 : rv = config_activate_children(self, act);
219 0 : break;
220 : case DVACT_POWERDOWN:
221 0 : rv = config_activate_children(self, act);
222 0 : pci_powerdown((struct pci_softc *)self);
223 0 : break;
224 : default:
225 0 : rv = config_activate_children(self, act);
226 0 : break;
227 : }
228 0 : return (rv);
229 : }
230 :
231 : void
232 0 : pci_suspend(struct pci_softc *sc)
233 : {
234 : struct pci_dev *pd;
235 0 : pcireg_t bhlc, reg;
236 0 : int off, i;
237 :
238 0 : LIST_FOREACH(pd, &sc->sc_devs, pd_next) {
239 : /*
240 : * Only handle header type 0 here; PCI-PCI bridges and
241 : * CardBus bridges need special handling, which will
242 : * be done in their specific drivers.
243 : */
244 0 : bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG);
245 0 : if (PCI_HDRTYPE_TYPE(bhlc) != 0)
246 : continue;
247 :
248 : /* Save registers that may get lost. */
249 0 : for (i = 0; i < NMAPREG; i++)
250 0 : pd->pd_map[i] = pci_conf_read(sc->sc_pc, pd->pd_tag,
251 0 : PCI_MAPREG_START + (i * 4));
252 0 : pd->pd_csr = pci_conf_read(sc->sc_pc, pd->pd_tag,
253 : PCI_COMMAND_STATUS_REG);
254 0 : pd->pd_bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag,
255 : PCI_BHLC_REG);
256 0 : pd->pd_int = pci_conf_read(sc->sc_pc, pd->pd_tag,
257 : PCI_INTERRUPT_REG);
258 :
259 0 : if (pci_get_capability(sc->sc_pc, pd->pd_tag,
260 : PCI_CAP_MSI, &off, ®)) {
261 0 : pd->pd_msi_ma = pci_conf_read(sc->sc_pc, pd->pd_tag,
262 0 : off + PCI_MSI_MA);
263 0 : if (reg & PCI_MSI_MC_C64) {
264 0 : pd->pd_msi_mau32 = pci_conf_read(sc->sc_pc,
265 : pd->pd_tag, off + PCI_MSI_MAU32);
266 0 : pd->pd_msi_md = pci_conf_read(sc->sc_pc,
267 0 : pd->pd_tag, off + PCI_MSI_MD64);
268 0 : } else {
269 0 : pd->pd_msi_md = pci_conf_read(sc->sc_pc,
270 : pd->pd_tag, off + PCI_MSI_MD32);
271 : }
272 0 : pd->pd_msi_mc = reg;
273 0 : }
274 : }
275 0 : }
276 :
277 : void
278 0 : pci_powerdown(struct pci_softc *sc)
279 : {
280 : struct pci_dev *pd;
281 : pcireg_t bhlc;
282 :
283 0 : LIST_FOREACH(pd, &sc->sc_devs, pd_next) {
284 : /*
285 : * Only handle header type 0 here; PCI-PCI bridges and
286 : * CardBus bridges need special handling, which will
287 : * be done in their specific drivers.
288 : */
289 0 : bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG);
290 0 : if (PCI_HDRTYPE_TYPE(bhlc) != 0)
291 : continue;
292 :
293 0 : if (pci_dopm) {
294 : /*
295 : * Place the device into the lowest possible
296 : * power state.
297 : */
298 0 : pd->pd_pmcsr_state = pci_get_powerstate(sc->sc_pc,
299 0 : pd->pd_tag);
300 0 : pci_set_powerstate(sc->sc_pc, pd->pd_tag,
301 0 : pci_min_powerstate(sc->sc_pc, pd->pd_tag));
302 0 : }
303 : }
304 0 : }
305 :
306 : void
307 0 : pci_resume(struct pci_softc *sc)
308 : {
309 : struct pci_dev *pd;
310 0 : pcireg_t bhlc, reg;
311 0 : int off, i;
312 :
313 0 : LIST_FOREACH(pd, &sc->sc_devs, pd_next) {
314 : /*
315 : * Only handle header type 0 here; PCI-PCI bridges and
316 : * CardBus bridges need special handling, which will
317 : * be done in their specific drivers.
318 : */
319 0 : bhlc = pci_conf_read(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG);
320 0 : if (PCI_HDRTYPE_TYPE(bhlc) != 0)
321 : continue;
322 :
323 : /* Restore power. */
324 0 : if (pci_dopm)
325 0 : pci_set_powerstate(sc->sc_pc, pd->pd_tag,
326 0 : pd->pd_pmcsr_state);
327 :
328 : /* Restore the registers saved above. */
329 0 : for (i = 0; i < NMAPREG; i++)
330 0 : pci_conf_write(sc->sc_pc, pd->pd_tag,
331 0 : PCI_MAPREG_START + (i * 4), pd->pd_map[i]);
332 0 : reg = pci_conf_read(sc->sc_pc, pd->pd_tag,
333 : PCI_COMMAND_STATUS_REG);
334 0 : pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_COMMAND_STATUS_REG,
335 0 : (reg & 0xffff0000) | (pd->pd_csr & 0x0000ffff));
336 0 : pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_BHLC_REG,
337 0 : pd->pd_bhlc);
338 0 : pci_conf_write(sc->sc_pc, pd->pd_tag, PCI_INTERRUPT_REG,
339 0 : pd->pd_int);
340 :
341 0 : if (pci_get_capability(sc->sc_pc, pd->pd_tag,
342 : PCI_CAP_MSI, &off, ®)) {
343 0 : pci_conf_write(sc->sc_pc, pd->pd_tag,
344 0 : off + PCI_MSI_MA, pd->pd_msi_ma);
345 0 : if (reg & PCI_MSI_MC_C64) {
346 0 : pci_conf_write(sc->sc_pc, pd->pd_tag,
347 0 : off + PCI_MSI_MAU32, pd->pd_msi_mau32);
348 0 : pci_conf_write(sc->sc_pc, pd->pd_tag,
349 0 : off + PCI_MSI_MD64, pd->pd_msi_md);
350 0 : } else {
351 0 : pci_conf_write(sc->sc_pc, pd->pd_tag,
352 0 : off + PCI_MSI_MD32, pd->pd_msi_md);
353 : }
354 0 : pci_conf_write(sc->sc_pc, pd->pd_tag,
355 0 : off + PCI_MSI_MC, pd->pd_msi_mc);
356 0 : }
357 : }
358 0 : }
359 :
360 : int
361 0 : pciprint(void *aux, const char *pnp)
362 : {
363 0 : struct pci_attach_args *pa = aux;
364 0 : char devinfo[256];
365 :
366 0 : if (pnp) {
367 0 : pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo,
368 : sizeof devinfo);
369 0 : printf("%s at %s", devinfo, pnp);
370 0 : }
371 0 : printf(" dev %d function %d", pa->pa_device, pa->pa_function);
372 0 : if (!pnp) {
373 0 : pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo,
374 : sizeof devinfo);
375 0 : printf(" %s", devinfo);
376 0 : }
377 :
378 0 : return (UNCONF);
379 0 : }
380 :
381 : int
382 0 : pcisubmatch(struct device *parent, void *match, void *aux)
383 : {
384 0 : struct cfdata *cf = match;
385 0 : struct pci_attach_args *pa = aux;
386 :
387 0 : if (cf->pcicf_dev != PCI_UNK_DEV &&
388 0 : cf->pcicf_dev != pa->pa_device)
389 0 : return (0);
390 0 : if (cf->pcicf_function != PCI_UNK_FUNCTION &&
391 0 : cf->pcicf_function != pa->pa_function)
392 0 : return (0);
393 :
394 0 : return ((*cf->cf_attach->ca_match)(parent, match, aux));
395 0 : }
396 :
397 : int
398 0 : pci_probe_device(struct pci_softc *sc, pcitag_t tag,
399 : int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
400 : {
401 0 : pci_chipset_tag_t pc = sc->sc_pc;
402 0 : struct pci_attach_args pa;
403 : struct pci_dev *pd;
404 0 : pcireg_t id, class, intr, bhlcr, cap;
405 0 : int pin, bus, device, function;
406 0 : int off, ret = 0;
407 : uint64_t addr;
408 :
409 0 : pci_decompose_tag(pc, tag, &bus, &device, &function);
410 :
411 0 : bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
412 0 : if (PCI_HDRTYPE_TYPE(bhlcr) > 2)
413 0 : return (0);
414 :
415 0 : id = pci_conf_read(pc, tag, PCI_ID_REG);
416 0 : class = pci_conf_read(pc, tag, PCI_CLASS_REG);
417 :
418 : /* Invalid vendor ID value? */
419 0 : if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
420 0 : return (0);
421 : /* XXX Not invalid, but we've done this ~forever. */
422 0 : if (PCI_VENDOR(id) == 0)
423 0 : return (0);
424 :
425 0 : pa.pa_iot = sc->sc_iot;
426 0 : pa.pa_memt = sc->sc_memt;
427 0 : pa.pa_dmat = sc->sc_dmat;
428 0 : pa.pa_pc = pc;
429 0 : pa.pa_ioex = sc->sc_ioex;
430 0 : pa.pa_memex = sc->sc_memex;
431 0 : pa.pa_pmemex = sc->sc_pmemex;
432 0 : pa.pa_busex = sc->sc_busex;
433 0 : pa.pa_domain = sc->sc_domain;
434 0 : pa.pa_bus = bus;
435 0 : pa.pa_device = device;
436 0 : pa.pa_function = function;
437 0 : pa.pa_tag = tag;
438 0 : pa.pa_id = id;
439 0 : pa.pa_class = class;
440 0 : pa.pa_bridgetag = sc->sc_bridgetag;
441 0 : pa.pa_bridgeih = sc->sc_bridgeih;
442 :
443 : /* This is a simplification of the NetBSD code.
444 : We don't support turning off I/O or memory
445 : on broken hardware. <csapuntz@stanford.edu> */
446 0 : pa.pa_flags = sc->sc_flags;
447 0 : pa.pa_flags |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
448 :
449 0 : if (sc->sc_bridgetag == NULL) {
450 0 : pa.pa_intrswiz = 0;
451 0 : pa.pa_intrtag = tag;
452 0 : } else {
453 0 : pa.pa_intrswiz = sc->sc_intrswiz + device;
454 0 : pa.pa_intrtag = sc->sc_intrtag;
455 : }
456 :
457 0 : intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
458 :
459 0 : pin = PCI_INTERRUPT_PIN(intr);
460 0 : pa.pa_rawintrpin = pin;
461 0 : if (pin == PCI_INTERRUPT_PIN_NONE) {
462 : /* no interrupt */
463 0 : pa.pa_intrpin = 0;
464 0 : } else {
465 : /*
466 : * swizzle it based on the number of busses we're
467 : * behind and our device number.
468 : */
469 0 : pa.pa_intrpin = /* XXX */
470 0 : ((pin + pa.pa_intrswiz - 1) % 4) + 1;
471 : }
472 0 : pa.pa_intrline = PCI_INTERRUPT_LINE(intr);
473 :
474 0 : if (pci_get_ht_capability(pc, tag, PCI_HT_CAP_MSI, &off, &cap)) {
475 : /*
476 : * XXX Should we enable MSI mapping ourselves on
477 : * systems that have it disabled?
478 : */
479 0 : if (cap & PCI_HT_MSI_ENABLED) {
480 0 : if ((cap & PCI_HT_MSI_FIXED) == 0) {
481 0 : addr = pci_conf_read(pc, tag,
482 0 : off + PCI_HT_MSI_ADDR);
483 0 : addr |= (uint64_t)pci_conf_read(pc, tag,
484 0 : off + PCI_HT_MSI_ADDR_HI32) << 32;
485 0 : } else
486 : addr = PCI_HT_MSI_FIXED_ADDR;
487 :
488 : /*
489 : * XXX This will fail to enable MSI on systems
490 : * that don't use the canonical address.
491 : */
492 0 : if (addr == PCI_HT_MSI_FIXED_ADDR)
493 0 : pa.pa_flags |= PCI_FLAGS_MSI_ENABLED;
494 : }
495 : }
496 :
497 : /*
498 : * Give the MD code a chance to alter pci_attach_args and/or
499 : * skip devices.
500 : */
501 : if (pci_probe_device_hook(pc, &pa) != 0)
502 : return (0);
503 :
504 0 : if (match != NULL) {
505 0 : ret = (*match)(&pa);
506 0 : if (ret != 0 && pap != NULL)
507 0 : *pap = pa;
508 : } else {
509 : pcireg_t address, csr;
510 : int i, reg, reg_start, reg_end;
511 : int s;
512 :
513 0 : pd = malloc(sizeof *pd, M_DEVBUF, M_ZERO | M_WAITOK);
514 0 : pd->pd_tag = tag;
515 0 : LIST_INSERT_HEAD(&sc->sc_devs, pd, pd_next);
516 :
517 0 : switch (PCI_HDRTYPE_TYPE(bhlcr)) {
518 : case 0:
519 : reg_start = PCI_MAPREG_START;
520 : reg_end = PCI_MAPREG_END;
521 0 : break;
522 : case 1: /* PCI-PCI bridge */
523 : reg_start = PCI_MAPREG_START;
524 : reg_end = PCI_MAPREG_PPB_END;
525 0 : break;
526 : case 2: /* PCI-CardBus bridge */
527 : reg_start = PCI_MAPREG_START;
528 : reg_end = PCI_MAPREG_PCB_END;
529 0 : break;
530 : default:
531 0 : return (0);
532 : }
533 :
534 0 : s = splhigh();
535 0 : csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
536 0 : if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
537 0 : pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr &
538 : ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE));
539 :
540 0 : for (reg = reg_start, i = 0; reg < reg_end; reg += 4, i++) {
541 0 : address = pci_conf_read(pc, tag, reg);
542 0 : pci_conf_write(pc, tag, reg, 0xffffffff);
543 0 : pd->pd_mask[i] = pci_conf_read(pc, tag, reg);
544 0 : pci_conf_write(pc, tag, reg, address);
545 : }
546 :
547 0 : if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
548 0 : pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
549 0 : splx(s);
550 :
551 0 : if ((PCI_CLASS(class) == PCI_CLASS_DISPLAY &&
552 0 : PCI_SUBCLASS(class) == PCI_SUBCLASS_DISPLAY_VGA) ||
553 0 : (PCI_CLASS(class) == PCI_CLASS_PREHISTORIC &&
554 0 : PCI_SUBCLASS(class) == PCI_SUBCLASS_PREHISTORIC_VGA))
555 0 : pd->pd_vga_decode = 1;
556 :
557 0 : pd->pd_dev = config_found_sm(&sc->sc_dev, &pa, pciprint,
558 : pcisubmatch);
559 0 : if (pd->pd_dev)
560 0 : pci_dev_postattach(pd->pd_dev, &pa);
561 0 : }
562 :
563 0 : return (ret);
564 0 : }
565 :
566 : int
567 0 : pci_detach_devices(struct pci_softc *sc, int flags)
568 : {
569 : struct pci_dev *pd, *next;
570 : int ret;
571 :
572 0 : ret = config_detach_children(&sc->sc_dev, flags);
573 0 : if (ret != 0)
574 0 : return (ret);
575 :
576 0 : for (pd = LIST_FIRST(&sc->sc_devs); pd != NULL; pd = next) {
577 0 : next = LIST_NEXT(pd, pd_next);
578 0 : free(pd, M_DEVBUF, sizeof *pd);
579 : }
580 0 : LIST_INIT(&sc->sc_devs);
581 :
582 0 : return (0);
583 0 : }
584 :
585 : int
586 0 : pci_get_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid,
587 : int *offset, pcireg_t *value)
588 : {
589 : pcireg_t reg;
590 : unsigned int ofs;
591 :
592 0 : reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
593 0 : if (!(reg & PCI_STATUS_CAPLIST_SUPPORT))
594 0 : return (0);
595 :
596 : /* Determine the Capability List Pointer register to start with. */
597 0 : reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
598 0 : switch (PCI_HDRTYPE_TYPE(reg)) {
599 : case 0: /* standard device header */
600 : case 1: /* PCI-PCI bridge header */
601 : ofs = PCI_CAPLISTPTR_REG;
602 0 : break;
603 : case 2: /* PCI-CardBus bridge header */
604 : ofs = PCI_CARDBUS_CAPLISTPTR_REG;
605 0 : break;
606 : default:
607 0 : return (0);
608 : }
609 :
610 0 : ofs = PCI_CAPLIST_PTR(pci_conf_read(pc, tag, ofs));
611 0 : while (ofs != 0) {
612 : /*
613 : * Some devices, like parts of the NVIDIA C51 chipset,
614 : * have a broken Capabilities List. So we need to do
615 : * a sanity check here.
616 : */
617 0 : if ((ofs & 3) || (ofs < 0x40))
618 0 : return (0);
619 0 : reg = pci_conf_read(pc, tag, ofs);
620 0 : if (PCI_CAPLIST_CAP(reg) == capid) {
621 0 : if (offset)
622 0 : *offset = ofs;
623 0 : if (value)
624 0 : *value = reg;
625 0 : return (1);
626 : }
627 0 : ofs = PCI_CAPLIST_NEXT(reg);
628 : }
629 :
630 0 : return (0);
631 0 : }
632 :
633 : int
634 0 : pci_get_ht_capability(pci_chipset_tag_t pc, pcitag_t tag, int capid,
635 : int *offset, pcireg_t *value)
636 : {
637 : pcireg_t reg;
638 0 : unsigned int ofs;
639 :
640 0 : if (pci_get_capability(pc, tag, PCI_CAP_HT, &ofs, NULL) == 0)
641 0 : return (0);
642 :
643 0 : while (ofs != 0) {
644 : #ifdef DIAGNOSTIC
645 0 : if ((ofs & 3) || (ofs < 0x40))
646 0 : panic("pci_get_ht_capability");
647 : #endif
648 0 : reg = pci_conf_read(pc, tag, ofs);
649 0 : if (PCI_HT_CAP(reg) == capid) {
650 0 : if (offset)
651 0 : *offset = ofs;
652 0 : if (value)
653 0 : *value = reg;
654 0 : return (1);
655 : }
656 0 : ofs = PCI_CAPLIST_NEXT(reg);
657 : }
658 :
659 0 : return (0);
660 0 : }
661 :
662 : uint16_t
663 0 : pci_requester_id(pci_chipset_tag_t pc, pcitag_t tag)
664 : {
665 0 : int bus, dev, func;
666 :
667 0 : pci_decompose_tag(pc, tag, &bus, &dev, &func);
668 0 : return ((bus << 8) | (dev << 3) | func);
669 0 : }
670 :
671 : int
672 0 : pci_find_device(struct pci_attach_args *pa,
673 : int (*match)(struct pci_attach_args *))
674 : {
675 : extern struct cfdriver pci_cd;
676 : struct device *pcidev;
677 : int i;
678 :
679 0 : for (i = 0; i < pci_cd.cd_ndevs; i++) {
680 0 : pcidev = pci_cd.cd_devs[i];
681 0 : if (pcidev != NULL &&
682 0 : pci_enumerate_bus((struct pci_softc *)pcidev,
683 0 : match, pa) != 0)
684 0 : return (1);
685 : }
686 0 : return (0);
687 0 : }
688 :
689 : int
690 0 : pci_get_powerstate(pci_chipset_tag_t pc, pcitag_t tag)
691 : {
692 : pcireg_t reg;
693 0 : int offset;
694 :
695 0 : if (pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, 0)) {
696 0 : reg = pci_conf_read(pc, tag, offset + PCI_PMCSR);
697 0 : return (reg & PCI_PMCSR_STATE_MASK);
698 : }
699 0 : return (PCI_PMCSR_STATE_D0);
700 0 : }
701 :
702 : int
703 0 : pci_set_powerstate(pci_chipset_tag_t pc, pcitag_t tag, int state)
704 : {
705 : pcireg_t reg;
706 0 : int offset, ostate = state;
707 :
708 : /*
709 : * Warn the firmware that we are going to put the device
710 : * into the given state.
711 : */
712 0 : pci_set_powerstate_md(pc, tag, state, 1);
713 :
714 0 : if (pci_get_capability(pc, tag, PCI_CAP_PWRMGMT, &offset, 0)) {
715 0 : if (state == PCI_PMCSR_STATE_D3) {
716 : /*
717 : * The PCI Power Management spec says we
718 : * should disable I/O and memory space as well
719 : * as bus mastering before we place the device
720 : * into D3.
721 : */
722 0 : reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
723 0 : reg &= ~PCI_COMMAND_IO_ENABLE;
724 0 : reg &= ~PCI_COMMAND_MEM_ENABLE;
725 0 : reg &= ~PCI_COMMAND_MASTER_ENABLE;
726 0 : pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
727 0 : }
728 0 : reg = pci_conf_read(pc, tag, offset + PCI_PMCSR);
729 0 : if ((reg & PCI_PMCSR_STATE_MASK) != state) {
730 : ostate = reg & PCI_PMCSR_STATE_MASK;
731 :
732 0 : pci_conf_write(pc, tag, offset + PCI_PMCSR,
733 0 : (reg & ~PCI_PMCSR_STATE_MASK) | state);
734 0 : if (state == PCI_PMCSR_STATE_D3 ||
735 0 : ostate == PCI_PMCSR_STATE_D3)
736 0 : delay(10 * 1000);
737 : }
738 : }
739 :
740 : /*
741 : * Warn the firmware that the device is now in the given
742 : * state.
743 : */
744 0 : pci_set_powerstate_md(pc, tag, state, 0);
745 :
746 0 : return (ostate);
747 0 : }
748 :
749 : #ifndef PCI_MACHDEP_ENUMERATE_BUS
750 : /*
751 : * Generic PCI bus enumeration routine. Used unless machine-dependent
752 : * code needs to provide something else.
753 : */
754 : int
755 0 : pci_enumerate_bus(struct pci_softc *sc,
756 : int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
757 : {
758 0 : pci_chipset_tag_t pc = sc->sc_pc;
759 : int device, function, nfunctions, ret;
760 : const struct pci_quirkdata *qd;
761 : pcireg_t id, bhlcr;
762 : pcitag_t tag;
763 :
764 0 : for (device = 0; device < sc->sc_maxndevs; device++) {
765 0 : tag = pci_make_tag(pc, sc->sc_bus, device, 0);
766 :
767 0 : bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
768 0 : if (PCI_HDRTYPE_TYPE(bhlcr) > 2)
769 : continue;
770 :
771 0 : id = pci_conf_read(pc, tag, PCI_ID_REG);
772 :
773 : /* Invalid vendor ID value? */
774 0 : if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
775 : continue;
776 : /* XXX Not invalid, but we've done this ~forever. */
777 0 : if (PCI_VENDOR(id) == 0)
778 : continue;
779 :
780 0 : qd = pci_lookup_quirkdata(PCI_VENDOR(id), PCI_PRODUCT(id));
781 :
782 0 : if (qd != NULL &&
783 0 : (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)
784 0 : nfunctions = 8;
785 0 : else if (qd != NULL &&
786 0 : (qd->quirks & PCI_QUIRK_MONOFUNCTION) != 0)
787 0 : nfunctions = 1;
788 : else
789 0 : nfunctions = PCI_HDRTYPE_MULTIFN(bhlcr) ? 8 : 1;
790 :
791 0 : for (function = 0; function < nfunctions; function++) {
792 0 : tag = pci_make_tag(pc, sc->sc_bus, device, function);
793 0 : ret = pci_probe_device(sc, tag, match, pap);
794 0 : if (match != NULL && ret != 0)
795 0 : return (ret);
796 : }
797 : }
798 :
799 0 : return (0);
800 0 : }
801 : #endif /* PCI_MACHDEP_ENUMERATE_BUS */
802 :
803 : int
804 0 : pci_reserve_resources(struct pci_attach_args *pa)
805 : {
806 0 : pci_chipset_tag_t pc = pa->pa_pc;
807 0 : pcitag_t tag = pa->pa_tag;
808 0 : pcireg_t bhlc, blr, type, bir;
809 : pcireg_t addr, mask;
810 0 : bus_addr_t base, limit;
811 0 : bus_size_t size;
812 : int reg, reg_start, reg_end, reg_rom;
813 0 : int bus, dev, func;
814 : int sec, sub;
815 0 : int flags;
816 : int s;
817 :
818 0 : pci_decompose_tag(pc, tag, &bus, &dev, &func);
819 :
820 0 : bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
821 0 : switch (PCI_HDRTYPE_TYPE(bhlc)) {
822 : case 0:
823 : reg_start = PCI_MAPREG_START;
824 : reg_end = PCI_MAPREG_END;
825 : reg_rom = PCI_ROM_REG;
826 0 : break;
827 : case 1: /* PCI-PCI bridge */
828 : reg_start = PCI_MAPREG_START;
829 : reg_end = PCI_MAPREG_PPB_END;
830 : reg_rom = 0; /* 0x38 */
831 0 : break;
832 : case 2: /* PCI-CardBus bridge */
833 : reg_start = PCI_MAPREG_START;
834 : reg_end = PCI_MAPREG_PCB_END;
835 : reg_rom = 0;
836 0 : break;
837 : default:
838 0 : return (0);
839 : }
840 :
841 0 : for (reg = reg_start; reg < reg_end; reg += 4) {
842 0 : if (!pci_mapreg_probe(pc, tag, reg, &type))
843 : continue;
844 :
845 0 : if (pci_mapreg_info(pc, tag, reg, type, &base, &size, &flags))
846 : continue;
847 :
848 0 : if (base == 0)
849 : continue;
850 :
851 0 : switch (type) {
852 : case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
853 : case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
854 0 : if (ISSET(flags, BUS_SPACE_MAP_PREFETCHABLE) &&
855 0 : pa->pa_pmemex && extent_alloc_region(pa->pa_pmemex,
856 0 : base, size, EX_NOWAIT) == 0) {
857 : break;
858 : }
859 : #ifdef __sparc64__
860 : /*
861 : * Certain SPARC T5 systems assign
862 : * non-prefetchable 64-bit BARs of its onboard
863 : * mpii(4) controllers addresses in the
864 : * prefetchable memory range. This is
865 : * (probably) safe, as reads from the device
866 : * registers mapped by these BARs are
867 : * side-effect free. So assume the firmware
868 : * knows what it is doing.
869 : */
870 : if (base >= 0x100000000 &&
871 : pa->pa_pmemex && extent_alloc_region(pa->pa_pmemex,
872 : base, size, EX_NOWAIT) == 0) {
873 : break;
874 : }
875 : #endif
876 0 : if (pa->pa_memex && extent_alloc_region(pa->pa_memex,
877 0 : base, size, EX_NOWAIT)) {
878 0 : printf("%d:%d:%d: mem address conflict 0x%lx/0x%lx\n",
879 0 : bus, dev, func, base, size);
880 0 : pci_conf_write(pc, tag, reg, 0);
881 0 : if (type & PCI_MAPREG_MEM_TYPE_64BIT)
882 0 : pci_conf_write(pc, tag, reg + 4, 0);
883 : }
884 : break;
885 : case PCI_MAPREG_TYPE_IO:
886 0 : if (pa->pa_ioex && extent_alloc_region(pa->pa_ioex,
887 0 : base, size, EX_NOWAIT)) {
888 0 : printf("%d:%d:%d: io address conflict 0x%lx/0x%lx\n",
889 0 : bus, dev, func, base, size);
890 0 : pci_conf_write(pc, tag, reg, 0);
891 0 : }
892 : break;
893 : }
894 :
895 0 : if (type & PCI_MAPREG_MEM_TYPE_64BIT)
896 0 : reg += 4;
897 : }
898 :
899 0 : if (reg_rom != 0) {
900 0 : s = splhigh();
901 0 : addr = pci_conf_read(pc, tag, PCI_ROM_REG);
902 0 : pci_conf_write(pc, tag, PCI_ROM_REG, ~PCI_ROM_ENABLE);
903 0 : mask = pci_conf_read(pc, tag, PCI_ROM_REG);
904 0 : pci_conf_write(pc, tag, PCI_ROM_REG, addr);
905 0 : splx(s);
906 :
907 0 : base = PCI_ROM_ADDR(addr);
908 0 : size = PCI_ROM_SIZE(mask);
909 0 : if (base != 0 && size != 0) {
910 0 : if (pa->pa_pmemex && extent_alloc_region(pa->pa_pmemex,
911 0 : base, size, EX_NOWAIT) &&
912 0 : pa->pa_memex && extent_alloc_region(pa->pa_memex,
913 0 : base, size, EX_NOWAIT)) {
914 0 : printf("%d:%d:%d: mem address conflict 0x%lx/0x%lx\n",
915 0 : bus, dev, func, base, size);
916 0 : pci_conf_write(pc, tag, PCI_ROM_REG, 0);
917 0 : }
918 : }
919 : }
920 :
921 0 : if (PCI_HDRTYPE_TYPE(bhlc) != 1)
922 0 : return (0);
923 :
924 : /* Figure out the I/O address range of the bridge. */
925 0 : blr = pci_conf_read(pc, tag, PPB_REG_IOSTATUS);
926 0 : base = (blr & 0x000000f0) << 8;
927 0 : limit = (blr & 0x000f000) | 0x00000fff;
928 0 : blr = pci_conf_read(pc, tag, PPB_REG_IO_HI);
929 0 : base |= (blr & 0x0000ffff) << 16;
930 0 : limit |= (blr & 0xffff0000);
931 0 : if (limit > base)
932 0 : size = (limit - base + 1);
933 : else
934 0 : size = 0;
935 0 : if (pa->pa_ioex && base > 0 && size > 0) {
936 0 : if (extent_alloc_region(pa->pa_ioex, base, size, EX_NOWAIT)) {
937 0 : printf("%d:%d:%d: bridge io address conflict 0x%lx/0x%lx\n",
938 0 : bus, dev, func, base, size);
939 : blr &= 0xffff0000;
940 0 : blr |= 0x000000f0;
941 0 : pci_conf_write(pc, tag, PPB_REG_IOSTATUS, blr);
942 0 : }
943 : }
944 :
945 : /* Figure out the memory mapped I/O address range of the bridge. */
946 0 : blr = pci_conf_read(pc, tag, PPB_REG_MEM);
947 0 : base = (blr & 0x0000fff0) << 16;
948 0 : limit = (blr & 0xfff00000) | 0x000fffff;
949 0 : if (limit > base)
950 0 : size = (limit - base + 1);
951 : else
952 0 : size = 0;
953 0 : if (pa->pa_memex && base > 0 && size > 0) {
954 0 : if (extent_alloc_region(pa->pa_memex, base, size, EX_NOWAIT)) {
955 0 : printf("%d:%d:%d: bridge mem address conflict 0x%lx/0x%lx\n",
956 0 : bus, dev, func, base, size);
957 0 : pci_conf_write(pc, tag, PPB_REG_MEM, 0x0000fff0);
958 0 : }
959 : }
960 :
961 : /* Figure out the prefetchable memory address range of the bridge. */
962 0 : blr = pci_conf_read(pc, tag, PPB_REG_PREFMEM);
963 0 : base = (blr & 0x0000fff0) << 16;
964 0 : limit = (blr & 0xfff00000) | 0x000fffff;
965 : #ifdef __LP64__
966 0 : blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFBASE_HI32);
967 0 : base |= ((uint64_t)blr) << 32;
968 0 : blr = pci_conf_read(pc, pa->pa_tag, PPB_REG_PREFLIM_HI32);
969 0 : limit |= ((uint64_t)blr) << 32;
970 : #endif
971 0 : if (limit > base)
972 0 : size = (limit - base + 1);
973 : else
974 0 : size = 0;
975 0 : if (pa->pa_pmemex && base > 0 && size > 0) {
976 0 : if (extent_alloc_region(pa->pa_pmemex, base, size, EX_NOWAIT)) {
977 0 : printf("%d:%d:%d: bridge mem address conflict 0x%lx/0x%lx\n",
978 0 : bus, dev, func, base, size);
979 0 : pci_conf_write(pc, tag, PPB_REG_PREFMEM, 0x0000fff0);
980 0 : }
981 0 : } else if (pa->pa_memex && base > 0 && size > 0) {
982 0 : if (extent_alloc_region(pa->pa_memex, base, size, EX_NOWAIT)) {
983 0 : printf("%d:%d:%d: bridge mem address conflict 0x%lx/0x%lx\n",
984 0 : bus, dev, func, base, size);
985 0 : pci_conf_write(pc, tag, PPB_REG_PREFMEM, 0x0000fff0);
986 0 : }
987 : }
988 :
989 : /* Figure out the bus range handled by the bridge. */
990 0 : bir = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
991 0 : sec = PPB_BUSINFO_SECONDARY(bir);
992 0 : sub = PPB_BUSINFO_SUBORDINATE(bir);
993 0 : if (pa->pa_busex && sub >= sec && sub > 0) {
994 0 : if (extent_alloc_region(pa->pa_busex, sec, sub - sec + 1,
995 : EX_NOWAIT)) {
996 0 : printf("%d:%d:%d: bridge bus conflict %d-%d\n",
997 0 : bus, dev, func, sec, sub);
998 0 : }
999 : }
1000 :
1001 0 : return (0);
1002 0 : }
1003 :
1004 : /*
1005 : * Vital Product Data (PCI 2.2)
1006 : */
1007 :
1008 : int
1009 0 : pci_vpd_read(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count,
1010 : pcireg_t *data)
1011 : {
1012 0 : uint32_t reg;
1013 0 : int ofs, i, j;
1014 :
1015 0 : KASSERT(data != NULL);
1016 0 : KASSERT((offset + count) < 0x7fff);
1017 :
1018 0 : if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0)
1019 0 : return (1);
1020 :
1021 0 : for (i = 0; i < count; offset += sizeof(*data), i++) {
1022 0 : reg &= 0x0000ffff;
1023 : reg &= ~PCI_VPD_OPFLAG;
1024 0 : reg |= PCI_VPD_ADDRESS(offset);
1025 0 : pci_conf_write(pc, tag, ofs, reg);
1026 :
1027 : /*
1028 : * PCI 2.2 does not specify how long we should poll
1029 : * for completion nor whether the operation can fail.
1030 : */
1031 : j = 0;
1032 0 : do {
1033 0 : if (j++ == 20)
1034 0 : return (1);
1035 0 : delay(4);
1036 0 : reg = pci_conf_read(pc, tag, ofs);
1037 0 : } while ((reg & PCI_VPD_OPFLAG) == 0);
1038 0 : data[i] = pci_conf_read(pc, tag, PCI_VPD_DATAREG(ofs));
1039 : }
1040 :
1041 0 : return (0);
1042 0 : }
1043 :
1044 : int
1045 0 : pci_vpd_write(pci_chipset_tag_t pc, pcitag_t tag, int offset, int count,
1046 : pcireg_t *data)
1047 : {
1048 0 : pcireg_t reg;
1049 0 : int ofs, i, j;
1050 :
1051 0 : KASSERT(data != NULL);
1052 0 : KASSERT((offset + count) < 0x7fff);
1053 :
1054 0 : if (pci_get_capability(pc, tag, PCI_CAP_VPD, &ofs, ®) == 0)
1055 0 : return (1);
1056 :
1057 0 : for (i = 0; i < count; offset += sizeof(*data), i++) {
1058 0 : pci_conf_write(pc, tag, PCI_VPD_DATAREG(ofs), data[i]);
1059 :
1060 0 : reg &= 0x0000ffff;
1061 0 : reg |= PCI_VPD_OPFLAG;
1062 0 : reg |= PCI_VPD_ADDRESS(offset);
1063 0 : pci_conf_write(pc, tag, ofs, reg);
1064 :
1065 : /*
1066 : * PCI 2.2 does not specify how long we should poll
1067 : * for completion nor whether the operation can fail.
1068 : */
1069 : j = 0;
1070 0 : do {
1071 0 : if (j++ == 20)
1072 0 : return (1);
1073 0 : delay(1);
1074 0 : reg = pci_conf_read(pc, tag, ofs);
1075 0 : } while (reg & PCI_VPD_OPFLAG);
1076 : }
1077 :
1078 0 : return (0);
1079 0 : }
1080 :
1081 : int
1082 0 : pci_matchbyid(struct pci_attach_args *pa, const struct pci_matchid *ids,
1083 : int nent)
1084 : {
1085 : const struct pci_matchid *pm;
1086 : int i;
1087 :
1088 0 : for (i = 0, pm = ids; i < nent; i++, pm++)
1089 0 : if (PCI_VENDOR(pa->pa_id) == pm->pm_vid &&
1090 0 : PCI_PRODUCT(pa->pa_id) == pm->pm_pid)
1091 0 : return (1);
1092 0 : return (0);
1093 0 : }
1094 :
1095 : void
1096 0 : pci_disable_legacy_vga(struct device *dev)
1097 : {
1098 : struct pci_softc *pci;
1099 : struct pci_dev *pd;
1100 :
1101 : /* XXX Until we attach the drm drivers directly to pci. */
1102 0 : while (dev->dv_parent->dv_cfdata->cf_driver != &pci_cd)
1103 : dev = dev->dv_parent;
1104 :
1105 0 : pci = (struct pci_softc *)dev->dv_parent;
1106 0 : LIST_FOREACH(pd, &pci->sc_devs, pd_next) {
1107 0 : if (pd->pd_dev == dev) {
1108 0 : pd->pd_vga_decode = 0;
1109 0 : break;
1110 : }
1111 : }
1112 0 : }
1113 :
1114 : #ifdef USER_PCICONF
1115 : /*
1116 : * This is the user interface to PCI configuration space.
1117 : */
1118 :
1119 : #include <sys/pciio.h>
1120 : #include <sys/fcntl.h>
1121 :
1122 : #ifdef DEBUG
1123 : #define PCIDEBUG(x) printf x
1124 : #else
1125 : #define PCIDEBUG(x)
1126 : #endif
1127 :
1128 : void pci_disable_vga(pci_chipset_tag_t, pcitag_t);
1129 : void pci_enable_vga(pci_chipset_tag_t, pcitag_t);
1130 : void pci_route_vga(struct pci_softc *);
1131 : void pci_unroute_vga(struct pci_softc *);
1132 :
1133 : int pciopen(dev_t dev, int oflags, int devtype, struct proc *p);
1134 : int pciclose(dev_t dev, int flag, int devtype, struct proc *p);
1135 : int pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p);
1136 :
1137 : int
1138 0 : pciopen(dev_t dev, int oflags, int devtype, struct proc *p)
1139 : {
1140 : PCIDEBUG(("pciopen ndevs: %d\n" , pci_cd.cd_ndevs));
1141 :
1142 0 : if (minor(dev) >= pci_ndomains) {
1143 0 : return ENXIO;
1144 : }
1145 :
1146 : #ifndef APERTURE
1147 : if ((oflags & FWRITE) && securelevel > 0) {
1148 : return EPERM;
1149 : }
1150 : #else
1151 0 : if ((oflags & FWRITE) && securelevel > 0 && allowaperture == 0) {
1152 0 : return EPERM;
1153 : }
1154 : #endif
1155 0 : return (0);
1156 0 : }
1157 :
1158 : int
1159 0 : pciclose(dev_t dev, int flag, int devtype, struct proc *p)
1160 : {
1161 : PCIDEBUG(("pciclose\n"));
1162 :
1163 0 : pci_vga_proc = NULL;
1164 0 : return (0);
1165 : }
1166 :
1167 : int
1168 0 : pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
1169 : {
1170 0 : struct pcisel *sel = (struct pcisel *)data;
1171 : struct pci_io *io;
1172 : struct pci_rom *rom;
1173 : int i, error;
1174 : pcitag_t tag;
1175 : struct pci_softc *pci;
1176 : pci_chipset_tag_t pc;
1177 :
1178 0 : switch (cmd) {
1179 : case PCIOCREAD:
1180 : case PCIOCREADMASK:
1181 : break;
1182 : case PCIOCWRITE:
1183 0 : if (!(flag & FWRITE))
1184 0 : return EPERM;
1185 : break;
1186 : case PCIOCGETROMLEN:
1187 : case PCIOCGETROM:
1188 : break;
1189 : case PCIOCGETVGA:
1190 : case PCIOCSETVGA:
1191 0 : if (pci_vga_pci == NULL)
1192 0 : return EINVAL;
1193 : break;
1194 : default:
1195 0 : return ENOTTY;
1196 : }
1197 :
1198 0 : for (i = 0; i < pci_cd.cd_ndevs; i++) {
1199 0 : pci = pci_cd.cd_devs[i];
1200 0 : if (pci != NULL && pci->sc_domain == minor(dev) &&
1201 0 : pci->sc_bus == sel->pc_bus)
1202 : break;
1203 : }
1204 0 : if (i >= pci_cd.cd_ndevs)
1205 0 : return ENXIO;
1206 :
1207 : /* Check bounds */
1208 0 : if (pci->sc_bus >= 256 ||
1209 0 : sel->pc_dev >= pci_bus_maxdevs(pci->sc_pc, pci->sc_bus) ||
1210 0 : sel->pc_func >= 8)
1211 0 : return EINVAL;
1212 :
1213 0 : pc = pci->sc_pc;
1214 0 : tag = pci_make_tag(pc, sel->pc_bus, sel->pc_dev, sel->pc_func);
1215 :
1216 0 : switch (cmd) {
1217 : case PCIOCREAD:
1218 0 : io = (struct pci_io *)data;
1219 0 : switch (io->pi_width) {
1220 : case 4:
1221 : /* Configuration space bounds check */
1222 0 : if (io->pi_reg < 0 ||
1223 0 : io->pi_reg >= pci_conf_size(pc, tag))
1224 0 : return EINVAL;
1225 : /* Make sure the register is properly aligned */
1226 0 : if (io->pi_reg & 0x3)
1227 0 : return EINVAL;
1228 0 : io->pi_data = pci_conf_read(pc, tag, io->pi_reg);
1229 : error = 0;
1230 0 : break;
1231 : default:
1232 : error = EINVAL;
1233 0 : break;
1234 : }
1235 : break;
1236 :
1237 : case PCIOCWRITE:
1238 0 : io = (struct pci_io *)data;
1239 0 : switch (io->pi_width) {
1240 : case 4:
1241 : /* Configuration space bounds check */
1242 0 : if (io->pi_reg < 0 ||
1243 0 : io->pi_reg >= pci_conf_size(pc, tag))
1244 0 : return EINVAL;
1245 : /* Make sure the register is properly aligned */
1246 0 : if (io->pi_reg & 0x3)
1247 0 : return EINVAL;
1248 0 : pci_conf_write(pc, tag, io->pi_reg, io->pi_data);
1249 : error = 0;
1250 0 : break;
1251 : default:
1252 : error = EINVAL;
1253 0 : break;
1254 : }
1255 : break;
1256 :
1257 : case PCIOCREADMASK:
1258 : {
1259 0 : io = (struct pci_io *)data;
1260 : struct pci_dev *pd;
1261 0 : int dev, func, i;
1262 :
1263 0 : if (io->pi_width != 4 || io->pi_reg & 0x3 ||
1264 0 : io->pi_reg < PCI_MAPREG_START ||
1265 0 : io->pi_reg >= PCI_MAPREG_END)
1266 0 : return (EINVAL);
1267 :
1268 : error = ENODEV;
1269 0 : LIST_FOREACH(pd, &pci->sc_devs, pd_next) {
1270 0 : pci_decompose_tag(pc, pd->pd_tag, NULL, &dev, &func);
1271 0 : if (dev == sel->pc_dev && func == sel->pc_func) {
1272 0 : i = (io->pi_reg - PCI_MAPREG_START) / 4;
1273 0 : io->pi_data = pd->pd_mask[i];
1274 : error = 0;
1275 0 : break;
1276 : }
1277 : }
1278 0 : break;
1279 0 : }
1280 :
1281 : case PCIOCGETROMLEN:
1282 : case PCIOCGETROM:
1283 : {
1284 : pcireg_t addr, mask, bhlc;
1285 0 : bus_space_handle_t h;
1286 : bus_size_t len, off;
1287 0 : char buf[256];
1288 : int s;
1289 :
1290 0 : rom = (struct pci_rom *)data;
1291 :
1292 0 : bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
1293 0 : if (PCI_HDRTYPE_TYPE(bhlc) != 0)
1294 0 : return (ENODEV);
1295 :
1296 0 : s = splhigh();
1297 0 : addr = pci_conf_read(pc, tag, PCI_ROM_REG);
1298 0 : pci_conf_write(pc, tag, PCI_ROM_REG, ~PCI_ROM_ENABLE);
1299 0 : mask = pci_conf_read(pc, tag, PCI_ROM_REG);
1300 0 : pci_conf_write(pc, tag, PCI_ROM_REG, addr);
1301 0 : splx(s);
1302 :
1303 : /*
1304 : * Section 6.2.5.2 `Expansion ROM Base Addres Register',
1305 : *
1306 : * tells us that only the upper 21 bits are writable.
1307 : * This means that the size of a ROM must be a
1308 : * multiple of 2 KB. So reading the ROM in chunks of
1309 : * 256 bytes should work just fine.
1310 : */
1311 0 : if ((PCI_ROM_ADDR(addr) == 0 ||
1312 0 : PCI_ROM_SIZE(mask) % sizeof(buf)) != 0)
1313 0 : return (ENODEV);
1314 :
1315 : /* If we're just after the size, skip reading the ROM. */
1316 0 : if (cmd == PCIOCGETROMLEN) {
1317 : error = 0;
1318 0 : goto fail;
1319 : }
1320 :
1321 0 : if (rom->pr_romlen < PCI_ROM_SIZE(mask)) {
1322 : error = ENOMEM;
1323 0 : goto fail;
1324 : }
1325 :
1326 0 : error = bus_space_map(pci->sc_memt, PCI_ROM_ADDR(addr),
1327 0 : PCI_ROM_SIZE(mask), 0, &h);
1328 0 : if (error)
1329 : goto fail;
1330 :
1331 : off = 0;
1332 : len = PCI_ROM_SIZE(mask);
1333 0 : while (len > 0 && error == 0) {
1334 0 : s = splhigh();
1335 0 : pci_conf_write(pc, tag, PCI_ROM_REG,
1336 0 : addr | PCI_ROM_ENABLE);
1337 0 : bus_space_read_region_1(pci->sc_memt, h, off,
1338 : buf, sizeof(buf));
1339 0 : pci_conf_write(pc, tag, PCI_ROM_REG, addr);
1340 0 : splx(s);
1341 :
1342 0 : error = copyout(buf, rom->pr_rom + off, sizeof(buf));
1343 0 : off += sizeof(buf);
1344 0 : len -= sizeof(buf);
1345 : }
1346 :
1347 0 : bus_space_unmap(pci->sc_memt, h, PCI_ROM_SIZE(mask));
1348 :
1349 : fail:
1350 0 : rom->pr_romlen = PCI_ROM_SIZE(mask);
1351 0 : break;
1352 0 : }
1353 :
1354 : case PCIOCGETVGA:
1355 : {
1356 0 : struct pci_vga *vga = (struct pci_vga *)data;
1357 : struct pci_dev *pd;
1358 0 : int bus, dev, func;
1359 :
1360 0 : vga->pv_decode = 0;
1361 0 : LIST_FOREACH(pd, &pci->sc_devs, pd_next) {
1362 0 : pci_decompose_tag(pc, pd->pd_tag, NULL, &dev, &func);
1363 0 : if (dev == sel->pc_dev && func == sel->pc_func) {
1364 0 : if (pd->pd_vga_decode)
1365 0 : vga->pv_decode = PCI_VGA_IO_ENABLE |
1366 : PCI_VGA_MEM_ENABLE;
1367 : break;
1368 : }
1369 : }
1370 :
1371 0 : pci_decompose_tag(pci_vga_pci->sc_pc,
1372 0 : pci_vga_tag, &bus, &dev, &func);
1373 0 : vga->pv_sel.pc_bus = bus;
1374 0 : vga->pv_sel.pc_dev = dev;
1375 0 : vga->pv_sel.pc_func = func;
1376 : error = 0;
1377 : break;
1378 0 : }
1379 : case PCIOCSETVGA:
1380 : {
1381 0 : struct pci_vga *vga = (struct pci_vga *)data;
1382 0 : int bus, dev, func;
1383 :
1384 0 : switch (vga->pv_lock) {
1385 : case PCI_VGA_UNLOCK:
1386 : case PCI_VGA_LOCK:
1387 : case PCI_VGA_TRYLOCK:
1388 : break;
1389 : default:
1390 0 : return (EINVAL);
1391 : }
1392 :
1393 0 : if (vga->pv_lock == PCI_VGA_UNLOCK) {
1394 0 : if (pci_vga_proc != p)
1395 0 : return (EINVAL);
1396 0 : pci_vga_proc = NULL;
1397 0 : wakeup(&pci_vga_proc);
1398 0 : return (0);
1399 : }
1400 :
1401 0 : while (pci_vga_proc != p && pci_vga_proc != NULL) {
1402 0 : if (vga->pv_lock == PCI_VGA_TRYLOCK)
1403 0 : return (EBUSY);
1404 0 : error = tsleep(&pci_vga_proc, PLOCK | PCATCH,
1405 : "vgalk", 0);
1406 0 : if (error)
1407 0 : return (error);
1408 : }
1409 0 : pci_vga_proc = p;
1410 :
1411 0 : pci_decompose_tag(pci_vga_pci->sc_pc,
1412 0 : pci_vga_tag, &bus, &dev, &func);
1413 0 : if (bus != vga->pv_sel.pc_bus || dev != vga->pv_sel.pc_dev ||
1414 0 : func != vga->pv_sel.pc_func) {
1415 0 : pci_disable_vga(pci_vga_pci->sc_pc, pci_vga_tag);
1416 0 : if (pci != pci_vga_pci) {
1417 0 : pci_unroute_vga(pci_vga_pci);
1418 0 : pci_route_vga(pci);
1419 0 : pci_vga_pci = pci;
1420 0 : }
1421 0 : pci_enable_vga(pc, tag);
1422 0 : pci_vga_tag = tag;
1423 0 : }
1424 :
1425 : error = 0;
1426 0 : break;
1427 0 : }
1428 :
1429 : default:
1430 : error = ENOTTY;
1431 0 : break;
1432 : }
1433 :
1434 0 : return (error);
1435 0 : }
1436 :
1437 : void
1438 0 : pci_disable_vga(pci_chipset_tag_t pc, pcitag_t tag)
1439 : {
1440 : pcireg_t csr;
1441 :
1442 0 : csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
1443 0 : csr &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
1444 0 : pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
1445 0 : }
1446 :
1447 : void
1448 0 : pci_enable_vga(pci_chipset_tag_t pc, pcitag_t tag)
1449 : {
1450 : pcireg_t csr;
1451 :
1452 0 : csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
1453 0 : csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
1454 0 : pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
1455 0 : }
1456 :
1457 : void
1458 0 : pci_route_vga(struct pci_softc *sc)
1459 : {
1460 0 : pci_chipset_tag_t pc = sc->sc_pc;
1461 : pcireg_t bc;
1462 :
1463 0 : if (sc->sc_bridgetag == NULL)
1464 0 : return;
1465 :
1466 0 : bc = pci_conf_read(pc, *sc->sc_bridgetag, PPB_REG_BRIDGECONTROL);
1467 0 : bc |= PPB_BC_VGA_ENABLE;
1468 0 : pci_conf_write(pc, *sc->sc_bridgetag, PPB_REG_BRIDGECONTROL, bc);
1469 :
1470 0 : pci_route_vga((struct pci_softc *)sc->sc_dev.dv_parent->dv_parent);
1471 0 : }
1472 :
1473 : void
1474 0 : pci_unroute_vga(struct pci_softc *sc)
1475 : {
1476 0 : pci_chipset_tag_t pc = sc->sc_pc;
1477 : pcireg_t bc;
1478 :
1479 0 : if (sc->sc_bridgetag == NULL)
1480 0 : return;
1481 :
1482 0 : bc = pci_conf_read(pc, *sc->sc_bridgetag, PPB_REG_BRIDGECONTROL);
1483 0 : bc &= ~PPB_BC_VGA_ENABLE;
1484 0 : pci_conf_write(pc, *sc->sc_bridgetag, PPB_REG_BRIDGECONTROL, bc);
1485 :
1486 0 : pci_unroute_vga((struct pci_softc *)sc->sc_dev.dv_parent->dv_parent);
1487 0 : }
1488 : #endif /* USER_PCICONF */
1489 :
1490 : int
1491 0 : pci_primary_vga(struct pci_attach_args *pa)
1492 : {
1493 : /* XXX For now, only handle the first PCI domain. */
1494 0 : if (pa->pa_domain != 0)
1495 0 : return (0);
1496 :
1497 0 : if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
1498 0 : PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA) &&
1499 0 : (PCI_CLASS(pa->pa_class) != PCI_CLASS_PREHISTORIC ||
1500 0 : PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_PREHISTORIC_VGA))
1501 0 : return (0);
1502 :
1503 0 : if ((pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG)
1504 0 : & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
1505 0 : != (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
1506 0 : return (0);
1507 :
1508 0 : pci_vga_tag = pa->pa_tag;
1509 :
1510 0 : return (1);
1511 0 : }
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