Line data Source code
1 : /* $OpenBSD: qlw_pci.c,v 1.10 2017/08/17 12:21:31 jsg Exp $ */
2 :
3 : /*
4 : * Copyright (c) 2011 David Gwynne <dlg@openbsd.org>
5 : * Copyright (c) 2013, 2014 Jonathan Matthew <jmatthew@openbsd.org>
6 : * Copyright (c) 2014 Mark Kettenis <kettenis@openbsd.org>
7 : *
8 : * Permission to use, copy, modify, and distribute this software for any
9 : * purpose with or without fee is hereby granted, provided that the above
10 : * copyright notice and this permission notice appear in all copies.
11 : *
12 : * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 : * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 : * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 : * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 : * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 : * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 : * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 : */
20 :
21 : #include "bio.h"
22 :
23 : #include <sys/param.h>
24 : #include <sys/systm.h>
25 : #include <sys/kernel.h>
26 : #include <sys/malloc.h>
27 : #include <sys/device.h>
28 : #include <sys/sensors.h>
29 : #include <sys/rwlock.h>
30 :
31 : #include <machine/bus.h>
32 :
33 : #include <dev/pci/pcireg.h>
34 : #include <dev/pci/pcivar.h>
35 : #include <dev/pci/pcidevs.h>
36 :
37 : #ifdef __sparc64__
38 : #include <dev/ofw/openfirm.h>
39 : #endif
40 :
41 : #include <scsi/scsi_all.h>
42 : #include <scsi/scsiconf.h>
43 :
44 : #include <dev/ic/qlwreg.h>
45 : #include <dev/ic/qlwvar.h>
46 :
47 : #ifndef ISP_NOFIRMWARE
48 : #include <dev/microcode/isp/asm_1040.h>
49 : #include <dev/microcode/isp/asm_1080.h>
50 : #include <dev/microcode/isp/asm_12160.h>
51 : #endif
52 :
53 : #define QLW_PCI_MEM_BAR 0x14
54 : #define QLW_PCI_IO_BAR 0x10
55 :
56 : int qlw_pci_match(struct device *, void *, void *);
57 : void qlw_pci_attach(struct device *, struct device *, void *);
58 : int qlw_pci_detach(struct device *, int);
59 :
60 : struct qlw_pci_softc {
61 : struct qlw_softc psc_qlw;
62 :
63 : pci_chipset_tag_t psc_pc;
64 : pcitag_t psc_tag;
65 :
66 : void *psc_ih;
67 : };
68 :
69 : struct cfattach qlw_pci_ca = {
70 : sizeof(struct qlw_pci_softc),
71 : qlw_pci_match,
72 : qlw_pci_attach
73 : };
74 :
75 : static const struct pci_matchid qlw_devices[] = {
76 : { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP1020 },
77 : { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP1240 },
78 : { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP1080 },
79 : { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP1280 },
80 : { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP10160 },
81 : { PCI_VENDOR_QLOGIC, PCI_PRODUCT_QLOGIC_ISP12160 },
82 : };
83 :
84 : int
85 0 : qlw_pci_match(struct device *parent, void *match, void *aux)
86 : {
87 0 : struct pci_attach_args *pa = aux;
88 :
89 : /* Silly AMI MegaRAID exposes its ISP12160 to us. */
90 0 : if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_QLOGIC_ISP12160) {
91 : pcireg_t subid;
92 :
93 0 : subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBVEND_0);
94 0 : if (PCI_VENDOR(subid) == PCI_VENDOR_AMI)
95 0 : return (0);
96 0 : }
97 :
98 0 : return (pci_matchbyid(aux, qlw_devices, nitems(qlw_devices)) * 2);
99 0 : }
100 :
101 : void
102 0 : qlw_pci_attach(struct device *parent, struct device *self, void *aux)
103 : {
104 0 : struct qlw_pci_softc *psc = (void *)self;
105 0 : struct qlw_softc *sc = &psc->psc_qlw;
106 0 : struct pci_attach_args *pa = aux;
107 0 : pci_intr_handle_t ih;
108 : const char *intrstr;
109 : u_int32_t pcictl;
110 : #ifdef __sparc64__
111 : int node, initiator;
112 : #endif
113 :
114 0 : pcireg_t bars[] = { QLW_PCI_MEM_BAR, QLW_PCI_IO_BAR };
115 : pcireg_t memtype;
116 : int r;
117 :
118 0 : psc->psc_pc = pa->pa_pc;
119 0 : psc->psc_tag = pa->pa_tag;
120 0 : psc->psc_ih = NULL;
121 0 : sc->sc_dmat = pa->pa_dmat;
122 0 : sc->sc_ios = 0;
123 :
124 0 : for (r = 0; r < nitems(bars); r++) {
125 0 : memtype = pci_mapreg_type(psc->psc_pc, psc->psc_tag, bars[r]);
126 0 : if (pci_mapreg_map(pa, bars[r], memtype, 0,
127 0 : &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_ios, 0) == 0)
128 : break;
129 :
130 0 : sc->sc_ios = 0;
131 : }
132 0 : if (sc->sc_ios == 0) {
133 0 : printf(": unable to map registers\n");
134 0 : return;
135 : }
136 :
137 0 : if (pci_intr_map(pa, &ih)) {
138 0 : printf(": unable to map interrupt\n");
139 0 : goto unmap;
140 : }
141 0 : intrstr = pci_intr_string(psc->psc_pc, ih);
142 0 : psc->psc_ih = pci_intr_establish(psc->psc_pc, ih, IPL_BIO,
143 0 : qlw_intr, sc, DEVNAME(sc));
144 0 : if (psc->psc_ih == NULL) {
145 0 : printf(": unable to establish interrupt");
146 0 : if (intrstr != NULL)
147 0 : printf(" at %s", intrstr);
148 0 : printf("\n");
149 0 : goto deintr;
150 : }
151 :
152 0 : printf(": %s\n", intrstr);
153 :
154 0 : pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
155 0 : pcictl |= PCI_COMMAND_INVALIDATE_ENABLE |
156 : PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
157 0 : pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, pcictl);
158 :
159 0 : pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
160 0 : pcictl &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
161 0 : pcictl &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
162 0 : pcictl |= (0x80 << PCI_LATTIMER_SHIFT);
163 0 : pcictl |= (0x10 << PCI_CACHELINE_SHIFT);
164 0 : pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, pcictl);
165 :
166 0 : pcictl = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
167 0 : pcictl &= ~1;
168 0 : pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, pcictl);
169 :
170 0 : switch (PCI_PRODUCT(pa->pa_id)) {
171 : case PCI_PRODUCT_QLOGIC_ISP1020:
172 0 : sc->sc_isp_gen = QLW_GEN_ISP1040;
173 0 : switch (PCI_REVISION(pa->pa_class)) {
174 : case 0:
175 0 : sc->sc_isp_type = QLW_ISP1020;
176 0 : break;
177 : case 1:
178 0 : sc->sc_isp_type = QLW_ISP1020A;
179 0 : break;
180 : case 2:
181 0 : sc->sc_isp_type = QLW_ISP1040;
182 0 : break;
183 : case 3:
184 0 : sc->sc_isp_type = QLW_ISP1040A;
185 0 : break;
186 : case 4:
187 0 : sc->sc_isp_type = QLW_ISP1040B;
188 0 : break;
189 : case 5:
190 : default:
191 0 : sc->sc_isp_type = QLW_ISP1040C;
192 0 : break;
193 : }
194 0 : sc->sc_numbusses = 1;
195 0 : if (PCI_REVISION(pa->pa_class) < 2)
196 0 : sc->sc_clock = 40; /* ISP1020/1020A */
197 : else
198 0 : sc->sc_clock = 60; /* ISP1040/1040A/1040B/1040C */
199 : break;
200 :
201 : case PCI_PRODUCT_QLOGIC_ISP1240:
202 0 : sc->sc_isp_gen = QLW_GEN_ISP1080;
203 0 : sc->sc_isp_type = QLW_ISP1240;
204 0 : sc->sc_numbusses = 2;
205 0 : sc->sc_clock = 60;
206 0 : break;
207 :
208 : case PCI_PRODUCT_QLOGIC_ISP1080:
209 0 : sc->sc_isp_gen = QLW_GEN_ISP1080;
210 0 : sc->sc_isp_type = QLW_ISP1080;
211 0 : sc->sc_numbusses = 1;
212 0 : sc->sc_clock = 100;
213 0 : break;
214 :
215 : case PCI_PRODUCT_QLOGIC_ISP1280:
216 0 : sc->sc_isp_gen = QLW_GEN_ISP1080;
217 0 : sc->sc_isp_type = QLW_ISP1280;
218 0 : sc->sc_numbusses = 2;
219 0 : sc->sc_clock = 100;
220 0 : break;
221 :
222 : case PCI_PRODUCT_QLOGIC_ISP10160:
223 0 : sc->sc_isp_gen = QLW_GEN_ISP12160;
224 0 : sc->sc_isp_type = QLW_ISP10160;
225 0 : sc->sc_numbusses = 1;
226 0 : sc->sc_clock = 100;
227 0 : break;
228 :
229 : case PCI_PRODUCT_QLOGIC_ISP12160:
230 0 : sc->sc_isp_gen = QLW_GEN_ISP12160;
231 0 : sc->sc_isp_type = QLW_ISP12160;
232 0 : sc->sc_numbusses = 2;
233 0 : sc->sc_clock = 100;
234 0 : break;
235 :
236 : default:
237 0 : printf("unknown pci id %x", pa->pa_id);
238 0 : return;
239 : }
240 :
241 : #ifndef ISP_NOFIRMWARE
242 0 : switch (sc->sc_isp_gen) {
243 : case QLW_GEN_ISP1040:
244 0 : sc->sc_firmware = isp_1040_risc_code;
245 0 : break;
246 : case QLW_GEN_ISP1080:
247 0 : sc->sc_firmware = isp_1080_risc_code;
248 0 : break;
249 : case QLW_GEN_ISP12160:
250 0 : sc->sc_firmware = isp_12160_risc_code;
251 0 : break;
252 : default:
253 : break;
254 : }
255 : #endif
256 :
257 : /*
258 : * The standard SCSI initiator ID is 7, but various SGI
259 : * machines use 0 as the initiator ID for their onboard SCSI.
260 : * Add-on cards should have a valid nvram, which will override
261 : * these defaults.
262 : */
263 : #ifdef __sgi__
264 : sc->sc_initiator[0] = sc->sc_initiator[1] = 0;
265 : #else
266 0 : sc->sc_initiator[0] = sc->sc_initiator[1] = 7;
267 : #endif
268 :
269 : #ifdef __sparc64__
270 : /*
271 : * Walk up the Open Firmware device tree until we find a
272 : * "scsi-initiator-id" property.
273 : */
274 : node = PCITAG_NODE(pa->pa_tag);
275 : while (node) {
276 : if (OF_getprop(node, "scsi-initiator-id",
277 : &initiator, sizeof(initiator)) == sizeof(initiator)) {
278 : /*
279 : * Override the SCSI initiator ID provided by
280 : * the nvram.
281 : */
282 : sc->sc_flags |= QLW_FLAG_INITIATOR;
283 : sc->sc_initiator[0] = sc->sc_initiator[1] = initiator;
284 : break;
285 : }
286 : node = OF_parent(node);
287 : }
288 : #endif
289 :
290 0 : sc->sc_host_cmd_ctrl = QLW_HOST_CMD_CTRL_PCI;
291 0 : sc->sc_mbox_base = QLW_MBOX_BASE_PCI;
292 :
293 0 : if (qlw_attach(sc) != 0) {
294 : /* error printed by qlw_attach */
295 : goto deintr;
296 : }
297 :
298 0 : return;
299 :
300 : deintr:
301 0 : pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
302 0 : psc->psc_ih = NULL;
303 : unmap:
304 0 : bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
305 0 : sc->sc_ios = 0;
306 0 : }
307 :
308 : int
309 0 : qlw_pci_detach(struct device *self, int flags)
310 : {
311 0 : struct qlw_pci_softc *psc = (struct qlw_pci_softc *)self;
312 0 : struct qlw_softc *sc = &psc->psc_qlw;
313 : int rv;
314 :
315 0 : if (psc->psc_ih == NULL) {
316 : /* we didnt attach properly, so nothing to detach */
317 0 : return (0);
318 : }
319 :
320 0 : rv = qlw_detach(sc, flags);
321 0 : if (rv != 0)
322 0 : return (rv);
323 :
324 0 : pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
325 0 : psc->psc_ih = NULL;
326 :
327 0 : bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
328 0 : sc->sc_ios = 0;
329 :
330 0 : return (0);
331 0 : }
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