Line data Source code
1 : /*
2 : * Copyright 2013 Advanced Micro Devices, Inc.
3 : *
4 : * Permission is hereby granted, free of charge, to any person obtaining a
5 : * copy of this software and associated documentation files (the "Software"),
6 : * to deal in the Software without restriction, including without limitation
7 : * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 : * and/or sell copies of the Software, and to permit persons to whom the
9 : * Software is furnished to do so, subject to the following conditions:
10 : *
11 : * The above copyright notice and this permission notice shall be included in
12 : * all copies or substantial portions of the Software.
13 : *
14 : * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 : * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 : * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 : * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 : * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 : * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 : * OTHER DEALINGS IN THE SOFTWARE.
21 : *
22 : */
23 :
24 : #include <dev/pci/drm/drmP.h>
25 : #include "radeon.h"
26 : #include "radeon_asic.h"
27 : #include "radeon_ucode.h"
28 : #include "cikd.h"
29 : #include "r600_dpm.h"
30 : #include "ci_dpm.h"
31 : #include "atom.h"
32 :
33 : #define MC_CG_ARB_FREQ_F0 0x0a
34 : #define MC_CG_ARB_FREQ_F1 0x0b
35 : #define MC_CG_ARB_FREQ_F2 0x0c
36 : #define MC_CG_ARB_FREQ_F3 0x0d
37 :
38 : #define SMC_RAM_END 0x40000
39 :
40 : #define VOLTAGE_SCALE 4
41 : #define VOLTAGE_VID_OFFSET_SCALE1 625
42 : #define VOLTAGE_VID_OFFSET_SCALE2 100
43 :
44 : static const struct ci_pt_defaults defaults_hawaii_xt =
45 : {
46 : 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
47 : { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
48 : { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
49 : };
50 :
51 : static const struct ci_pt_defaults defaults_hawaii_pro =
52 : {
53 : 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
54 : { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
55 : { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
56 : };
57 :
58 : static const struct ci_pt_defaults defaults_bonaire_xt =
59 : {
60 : 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
61 : { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
62 : { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
63 : };
64 :
65 : static const struct ci_pt_defaults defaults_bonaire_pro =
66 : {
67 : 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
68 : { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
69 : { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
70 : };
71 :
72 : static const struct ci_pt_defaults defaults_saturn_xt =
73 : {
74 : 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
75 : { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
76 : { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
77 : };
78 :
79 : static const struct ci_pt_defaults defaults_saturn_pro =
80 : {
81 : 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
82 : { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
83 : { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
84 : };
85 :
86 : static const struct ci_pt_config_reg didt_config_ci[] =
87 : {
88 : { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
89 : { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
90 : { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 : { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 : { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 : { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 : { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 : { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 : { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 : { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 : { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 : { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 : { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
101 : { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
102 : { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
103 : { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
104 : { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
105 : { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
106 : { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
107 : { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 : { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 : { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 : { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 : { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 : { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 : { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 : { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 : { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 : { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 : { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 : { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
119 : { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
120 : { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
121 : { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
122 : { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
123 : { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
124 : { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
125 : { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 : { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 : { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 : { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 : { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 : { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 : { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 : { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 : { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 : { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 : { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 : { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
137 : { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
138 : { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
139 : { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
140 : { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
141 : { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
142 : { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
143 : { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 : { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 : { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 : { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 : { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 : { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 : { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 : { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 : { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 : { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 : { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 : { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
155 : { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
156 : { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
157 : { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
158 : { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
159 : { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
160 : { 0xFFFFFFFF }
161 : };
162 :
163 : extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
164 : extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
165 : u32 arb_freq_src, u32 arb_freq_dest);
166 : extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
167 : extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
168 : extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
169 : u32 max_voltage_steps,
170 : struct atom_voltage_table *voltage_table);
171 : extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
172 : extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
173 : extern int ci_mc_load_microcode(struct radeon_device *rdev);
174 : extern void cik_update_cg(struct radeon_device *rdev,
175 : u32 block, bool enable);
176 :
177 : static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
178 : struct atom_voltage_table_entry *voltage_table,
179 : u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
180 : static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
181 : static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
182 : u32 target_tdp);
183 : static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
184 :
185 : static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
186 : PPSMC_Msg msg, u32 parameter);
187 :
188 : static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
189 : static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
190 :
191 0 : static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
192 : {
193 0 : struct ci_power_info *pi = rdev->pm.dpm.priv;
194 :
195 0 : return pi;
196 : }
197 :
198 0 : static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
199 : {
200 0 : struct ci_ps *ps = rps->ps_priv;
201 :
202 0 : return ps;
203 : }
204 :
205 0 : static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
206 : {
207 0 : struct ci_power_info *pi = ci_get_pi(rdev);
208 :
209 0 : switch (rdev->pdev->device) {
210 : case 0x6649:
211 : case 0x6650:
212 : case 0x6651:
213 : case 0x6658:
214 : case 0x665C:
215 : case 0x665D:
216 : default:
217 0 : pi->powertune_defaults = &defaults_bonaire_xt;
218 0 : break;
219 : case 0x6640:
220 : case 0x6641:
221 : case 0x6646:
222 : case 0x6647:
223 0 : pi->powertune_defaults = &defaults_saturn_xt;
224 0 : break;
225 : case 0x67B8:
226 : case 0x67B0:
227 0 : pi->powertune_defaults = &defaults_hawaii_xt;
228 0 : break;
229 : case 0x67BA:
230 : case 0x67B1:
231 0 : pi->powertune_defaults = &defaults_hawaii_pro;
232 0 : break;
233 : case 0x67A0:
234 : case 0x67A1:
235 : case 0x67A2:
236 : case 0x67A8:
237 : case 0x67A9:
238 : case 0x67AA:
239 : case 0x67B9:
240 : case 0x67BE:
241 0 : pi->powertune_defaults = &defaults_bonaire_xt;
242 0 : break;
243 : }
244 :
245 0 : pi->dte_tj_offset = 0;
246 :
247 0 : pi->caps_power_containment = true;
248 0 : pi->caps_cac = false;
249 0 : pi->caps_sq_ramping = false;
250 0 : pi->caps_db_ramping = false;
251 0 : pi->caps_td_ramping = false;
252 0 : pi->caps_tcp_ramping = false;
253 :
254 0 : if (pi->caps_power_containment) {
255 0 : pi->caps_cac = true;
256 0 : if (rdev->family == CHIP_HAWAII)
257 0 : pi->enable_bapm_feature = false;
258 : else
259 0 : pi->enable_bapm_feature = true;
260 0 : pi->enable_tdc_limit_feature = true;
261 0 : pi->enable_pkg_pwr_tracking_feature = true;
262 0 : }
263 0 : }
264 :
265 0 : static u8 ci_convert_to_vid(u16 vddc)
266 : {
267 0 : return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
268 : }
269 :
270 0 : static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
271 : {
272 0 : struct ci_power_info *pi = ci_get_pi(rdev);
273 0 : u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
274 0 : u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
275 0 : u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
276 : u32 i;
277 :
278 0 : if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
279 0 : return -EINVAL;
280 0 : if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
281 0 : return -EINVAL;
282 0 : if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
283 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
284 0 : return -EINVAL;
285 :
286 0 : for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
287 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
288 0 : lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
289 0 : hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
290 0 : hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
291 0 : } else {
292 0 : lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
293 0 : hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
294 : }
295 : }
296 0 : return 0;
297 0 : }
298 :
299 0 : static int ci_populate_vddc_vid(struct radeon_device *rdev)
300 : {
301 0 : struct ci_power_info *pi = ci_get_pi(rdev);
302 0 : u8 *vid = pi->smc_powertune_table.VddCVid;
303 : u32 i;
304 :
305 0 : if (pi->vddc_voltage_table.count > 8)
306 0 : return -EINVAL;
307 :
308 0 : for (i = 0; i < pi->vddc_voltage_table.count; i++)
309 0 : vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
310 :
311 0 : return 0;
312 0 : }
313 :
314 0 : static int ci_populate_svi_load_line(struct radeon_device *rdev)
315 : {
316 0 : struct ci_power_info *pi = ci_get_pi(rdev);
317 0 : const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
318 :
319 0 : pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
320 0 : pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
321 0 : pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
322 0 : pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
323 :
324 0 : return 0;
325 : }
326 :
327 0 : static int ci_populate_tdc_limit(struct radeon_device *rdev)
328 : {
329 0 : struct ci_power_info *pi = ci_get_pi(rdev);
330 0 : const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
331 : u16 tdc_limit;
332 :
333 0 : tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
334 0 : pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
335 0 : pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
336 0 : pt_defaults->tdc_vddc_throttle_release_limit_perc;
337 0 : pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
338 :
339 0 : return 0;
340 : }
341 :
342 0 : static int ci_populate_dw8(struct radeon_device *rdev)
343 : {
344 0 : struct ci_power_info *pi = ci_get_pi(rdev);
345 0 : const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
346 : int ret;
347 :
348 0 : ret = ci_read_smc_sram_dword(rdev,
349 : SMU7_FIRMWARE_HEADER_LOCATION +
350 : offsetof(SMU7_Firmware_Header, PmFuseTable) +
351 : offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
352 0 : (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
353 0 : pi->sram_end);
354 0 : if (ret)
355 0 : return -EINVAL;
356 : else
357 0 : pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
358 :
359 0 : return 0;
360 0 : }
361 :
362 0 : static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
363 : {
364 0 : struct ci_power_info *pi = ci_get_pi(rdev);
365 :
366 0 : if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
367 0 : (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
368 0 : rdev->pm.dpm.fan.fan_output_sensitivity =
369 0 : rdev->pm.dpm.fan.default_fan_output_sensitivity;
370 :
371 0 : pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
372 0 : cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
373 :
374 0 : return 0;
375 : }
376 :
377 0 : static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
378 : {
379 0 : struct ci_power_info *pi = ci_get_pi(rdev);
380 0 : u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
381 0 : u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
382 : int i, min, max;
383 :
384 0 : min = max = hi_vid[0];
385 0 : for (i = 0; i < 8; i++) {
386 0 : if (0 != hi_vid[i]) {
387 0 : if (min > hi_vid[i])
388 0 : min = hi_vid[i];
389 0 : if (max < hi_vid[i])
390 0 : max = hi_vid[i];
391 : }
392 :
393 0 : if (0 != lo_vid[i]) {
394 0 : if (min > lo_vid[i])
395 0 : min = lo_vid[i];
396 0 : if (max < lo_vid[i])
397 0 : max = lo_vid[i];
398 : }
399 : }
400 :
401 0 : if ((min == 0) || (max == 0))
402 0 : return -EINVAL;
403 0 : pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
404 0 : pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
405 :
406 0 : return 0;
407 0 : }
408 :
409 0 : static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
410 : {
411 0 : struct ci_power_info *pi = ci_get_pi(rdev);
412 0 : u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
413 0 : u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
414 : struct radeon_cac_tdp_table *cac_tdp_table =
415 0 : rdev->pm.dpm.dyn_state.cac_tdp_table;
416 :
417 0 : hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
418 0 : lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
419 :
420 0 : pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
421 0 : pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
422 :
423 0 : return 0;
424 : }
425 :
426 0 : static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
427 : {
428 0 : struct ci_power_info *pi = ci_get_pi(rdev);
429 0 : const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
430 0 : SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
431 : struct radeon_cac_tdp_table *cac_tdp_table =
432 0 : rdev->pm.dpm.dyn_state.cac_tdp_table;
433 0 : struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
434 : int i, j, k;
435 : const u16 *def1;
436 : const u16 *def2;
437 :
438 0 : dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
439 0 : dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
440 :
441 0 : dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
442 0 : dpm_table->GpuTjMax =
443 0 : (u8)(pi->thermal_temp_setting.temperature_high / 1000);
444 0 : dpm_table->GpuTjHyst = 8;
445 :
446 0 : dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
447 :
448 0 : if (ppm) {
449 0 : dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
450 0 : dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
451 0 : } else {
452 0 : dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
453 0 : dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
454 : }
455 :
456 0 : dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
457 0 : def1 = pt_defaults->bapmti_r;
458 0 : def2 = pt_defaults->bapmti_rc;
459 :
460 0 : for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
461 0 : for (j = 0; j < SMU7_DTE_SOURCES; j++) {
462 0 : for (k = 0; k < SMU7_DTE_SINKS; k++) {
463 0 : dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
464 0 : dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
465 0 : def1++;
466 0 : def2++;
467 : }
468 : }
469 : }
470 :
471 0 : return 0;
472 : }
473 :
474 0 : static int ci_populate_pm_base(struct radeon_device *rdev)
475 : {
476 0 : struct ci_power_info *pi = ci_get_pi(rdev);
477 0 : u32 pm_fuse_table_offset;
478 : int ret;
479 :
480 0 : if (pi->caps_power_containment) {
481 0 : ret = ci_read_smc_sram_dword(rdev,
482 : SMU7_FIRMWARE_HEADER_LOCATION +
483 : offsetof(SMU7_Firmware_Header, PmFuseTable),
484 0 : &pm_fuse_table_offset, pi->sram_end);
485 0 : if (ret)
486 0 : return ret;
487 0 : ret = ci_populate_bapm_vddc_vid_sidd(rdev);
488 0 : if (ret)
489 0 : return ret;
490 0 : ret = ci_populate_vddc_vid(rdev);
491 0 : if (ret)
492 0 : return ret;
493 0 : ret = ci_populate_svi_load_line(rdev);
494 0 : if (ret)
495 0 : return ret;
496 0 : ret = ci_populate_tdc_limit(rdev);
497 0 : if (ret)
498 0 : return ret;
499 0 : ret = ci_populate_dw8(rdev);
500 0 : if (ret)
501 0 : return ret;
502 0 : ret = ci_populate_fuzzy_fan(rdev);
503 0 : if (ret)
504 0 : return ret;
505 0 : ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
506 0 : if (ret)
507 0 : return ret;
508 0 : ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
509 0 : if (ret)
510 0 : return ret;
511 0 : ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
512 0 : (u8 *)&pi->smc_powertune_table,
513 0 : sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
514 0 : if (ret)
515 0 : return ret;
516 : }
517 :
518 0 : return 0;
519 0 : }
520 :
521 0 : static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
522 : {
523 0 : struct ci_power_info *pi = ci_get_pi(rdev);
524 : u32 data;
525 :
526 0 : if (pi->caps_sq_ramping) {
527 0 : data = RREG32_DIDT(DIDT_SQ_CTRL0);
528 0 : if (enable)
529 0 : data |= DIDT_CTRL_EN;
530 : else
531 0 : data &= ~DIDT_CTRL_EN;
532 0 : WREG32_DIDT(DIDT_SQ_CTRL0, data);
533 0 : }
534 :
535 0 : if (pi->caps_db_ramping) {
536 0 : data = RREG32_DIDT(DIDT_DB_CTRL0);
537 0 : if (enable)
538 0 : data |= DIDT_CTRL_EN;
539 : else
540 0 : data &= ~DIDT_CTRL_EN;
541 0 : WREG32_DIDT(DIDT_DB_CTRL0, data);
542 0 : }
543 :
544 0 : if (pi->caps_td_ramping) {
545 0 : data = RREG32_DIDT(DIDT_TD_CTRL0);
546 0 : if (enable)
547 0 : data |= DIDT_CTRL_EN;
548 : else
549 0 : data &= ~DIDT_CTRL_EN;
550 0 : WREG32_DIDT(DIDT_TD_CTRL0, data);
551 0 : }
552 :
553 0 : if (pi->caps_tcp_ramping) {
554 0 : data = RREG32_DIDT(DIDT_TCP_CTRL0);
555 0 : if (enable)
556 0 : data |= DIDT_CTRL_EN;
557 : else
558 0 : data &= ~DIDT_CTRL_EN;
559 0 : WREG32_DIDT(DIDT_TCP_CTRL0, data);
560 0 : }
561 0 : }
562 :
563 0 : static int ci_program_pt_config_registers(struct radeon_device *rdev,
564 : const struct ci_pt_config_reg *cac_config_regs)
565 : {
566 : const struct ci_pt_config_reg *config_regs = cac_config_regs;
567 : u32 data;
568 : u32 cache = 0;
569 :
570 0 : if (config_regs == NULL)
571 0 : return -EINVAL;
572 :
573 0 : while (config_regs->offset != 0xFFFFFFFF) {
574 0 : if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
575 0 : cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
576 0 : } else {
577 0 : switch (config_regs->type) {
578 : case CISLANDS_CONFIGREG_SMC_IND:
579 0 : data = RREG32_SMC(config_regs->offset);
580 0 : break;
581 : case CISLANDS_CONFIGREG_DIDT_IND:
582 0 : data = RREG32_DIDT(config_regs->offset);
583 0 : break;
584 : default:
585 0 : data = RREG32(config_regs->offset << 2);
586 0 : break;
587 : }
588 :
589 0 : data &= ~config_regs->mask;
590 0 : data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
591 0 : data |= cache;
592 :
593 0 : switch (config_regs->type) {
594 : case CISLANDS_CONFIGREG_SMC_IND:
595 0 : WREG32_SMC(config_regs->offset, data);
596 0 : break;
597 : case CISLANDS_CONFIGREG_DIDT_IND:
598 0 : WREG32_DIDT(config_regs->offset, data);
599 0 : break;
600 : default:
601 0 : WREG32(config_regs->offset << 2, data);
602 0 : break;
603 : }
604 : cache = 0;
605 : }
606 0 : config_regs++;
607 : }
608 0 : return 0;
609 0 : }
610 :
611 0 : static int ci_enable_didt(struct radeon_device *rdev, bool enable)
612 : {
613 0 : struct ci_power_info *pi = ci_get_pi(rdev);
614 : int ret;
615 :
616 0 : if (pi->caps_sq_ramping || pi->caps_db_ramping ||
617 0 : pi->caps_td_ramping || pi->caps_tcp_ramping) {
618 0 : cik_enter_rlc_safe_mode(rdev);
619 :
620 0 : if (enable) {
621 0 : ret = ci_program_pt_config_registers(rdev, didt_config_ci);
622 0 : if (ret) {
623 0 : cik_exit_rlc_safe_mode(rdev);
624 0 : return ret;
625 : }
626 : }
627 :
628 0 : ci_do_enable_didt(rdev, enable);
629 :
630 0 : cik_exit_rlc_safe_mode(rdev);
631 0 : }
632 :
633 0 : return 0;
634 0 : }
635 :
636 0 : static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
637 : {
638 0 : struct ci_power_info *pi = ci_get_pi(rdev);
639 : PPSMC_Result smc_result;
640 : int ret = 0;
641 :
642 0 : if (enable) {
643 0 : pi->power_containment_features = 0;
644 0 : if (pi->caps_power_containment) {
645 0 : if (pi->enable_bapm_feature) {
646 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
647 0 : if (smc_result != PPSMC_Result_OK)
648 0 : ret = -EINVAL;
649 : else
650 0 : pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
651 : }
652 :
653 0 : if (pi->enable_tdc_limit_feature) {
654 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
655 0 : if (smc_result != PPSMC_Result_OK)
656 0 : ret = -EINVAL;
657 : else
658 0 : pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
659 : }
660 :
661 0 : if (pi->enable_pkg_pwr_tracking_feature) {
662 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
663 0 : if (smc_result != PPSMC_Result_OK) {
664 : ret = -EINVAL;
665 0 : } else {
666 : struct radeon_cac_tdp_table *cac_tdp_table =
667 0 : rdev->pm.dpm.dyn_state.cac_tdp_table;
668 : u32 default_pwr_limit =
669 0 : (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
670 :
671 0 : pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
672 :
673 0 : ci_set_power_limit(rdev, default_pwr_limit);
674 : }
675 : }
676 : }
677 : } else {
678 0 : if (pi->caps_power_containment && pi->power_containment_features) {
679 0 : if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
680 0 : ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
681 :
682 0 : if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
683 0 : ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
684 :
685 0 : if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
686 0 : ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
687 0 : pi->power_containment_features = 0;
688 0 : }
689 : }
690 :
691 0 : return ret;
692 : }
693 :
694 0 : static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
695 : {
696 0 : struct ci_power_info *pi = ci_get_pi(rdev);
697 : PPSMC_Result smc_result;
698 : int ret = 0;
699 :
700 0 : if (pi->caps_cac) {
701 0 : if (enable) {
702 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
703 0 : if (smc_result != PPSMC_Result_OK) {
704 : ret = -EINVAL;
705 0 : pi->cac_enabled = false;
706 0 : } else {
707 0 : pi->cac_enabled = true;
708 : }
709 0 : } else if (pi->cac_enabled) {
710 0 : ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
711 0 : pi->cac_enabled = false;
712 0 : }
713 : }
714 :
715 0 : return ret;
716 : }
717 :
718 0 : static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
719 : bool enable)
720 : {
721 0 : struct ci_power_info *pi = ci_get_pi(rdev);
722 : PPSMC_Result smc_result = PPSMC_Result_OK;
723 :
724 0 : if (pi->thermal_sclk_dpm_enabled) {
725 0 : if (enable)
726 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
727 : else
728 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
729 : }
730 :
731 0 : if (smc_result == PPSMC_Result_OK)
732 0 : return 0;
733 : else
734 0 : return -EINVAL;
735 0 : }
736 :
737 0 : static int ci_power_control_set_level(struct radeon_device *rdev)
738 : {
739 0 : struct ci_power_info *pi = ci_get_pi(rdev);
740 : struct radeon_cac_tdp_table *cac_tdp_table =
741 0 : rdev->pm.dpm.dyn_state.cac_tdp_table;
742 : s32 adjust_percent;
743 : s32 target_tdp;
744 : int ret = 0;
745 : bool adjust_polarity = false; /* ??? */
746 :
747 0 : if (pi->caps_power_containment) {
748 : adjust_percent = adjust_polarity ?
749 0 : rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
750 0 : target_tdp = ((100 + adjust_percent) *
751 0 : (s32)cac_tdp_table->configurable_tdp) / 100;
752 :
753 0 : ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
754 0 : }
755 :
756 0 : return ret;
757 : }
758 :
759 0 : void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
760 : {
761 0 : struct ci_power_info *pi = ci_get_pi(rdev);
762 :
763 0 : if (pi->uvd_power_gated == gate)
764 0 : return;
765 :
766 0 : pi->uvd_power_gated = gate;
767 :
768 0 : ci_update_uvd_dpm(rdev, gate);
769 0 : }
770 :
771 0 : bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
772 : {
773 0 : struct ci_power_info *pi = ci_get_pi(rdev);
774 0 : u32 vblank_time = r600_dpm_get_vblank_time(rdev);
775 0 : u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
776 :
777 : /* disable mclk switching if the refresh is >120Hz, even if the
778 : * blanking period would allow it
779 : */
780 0 : if (r600_dpm_get_vrefresh(rdev) > 120)
781 0 : return true;
782 :
783 : /* disable mclk switching if the refresh is >120Hz, even if the
784 : * blanking period would allow it
785 : */
786 0 : if (r600_dpm_get_vrefresh(rdev) > 120)
787 0 : return true;
788 :
789 0 : if (vblank_time < switch_limit)
790 0 : return true;
791 : else
792 0 : return false;
793 :
794 0 : }
795 :
796 0 : static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
797 : struct radeon_ps *rps)
798 : {
799 0 : struct ci_ps *ps = ci_get_ps(rps);
800 0 : struct ci_power_info *pi = ci_get_pi(rdev);
801 : struct radeon_clock_and_voltage_limits *max_limits;
802 : bool disable_mclk_switching;
803 : u32 sclk, mclk;
804 : int i;
805 :
806 0 : if (rps->vce_active) {
807 0 : rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
808 0 : rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
809 0 : } else {
810 0 : rps->evclk = 0;
811 0 : rps->ecclk = 0;
812 : }
813 :
814 0 : if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
815 0 : ci_dpm_vblank_too_short(rdev))
816 0 : disable_mclk_switching = true;
817 : else
818 : disable_mclk_switching = false;
819 :
820 0 : if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
821 0 : pi->battery_state = true;
822 : else
823 0 : pi->battery_state = false;
824 :
825 0 : if (rdev->pm.dpm.ac_power)
826 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
827 : else
828 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
829 :
830 0 : if (rdev->pm.dpm.ac_power == false) {
831 0 : for (i = 0; i < ps->performance_level_count; i++) {
832 0 : if (ps->performance_levels[i].mclk > max_limits->mclk)
833 0 : ps->performance_levels[i].mclk = max_limits->mclk;
834 0 : if (ps->performance_levels[i].sclk > max_limits->sclk)
835 0 : ps->performance_levels[i].sclk = max_limits->sclk;
836 : }
837 : }
838 :
839 : /* XXX validate the min clocks required for display */
840 :
841 0 : if (disable_mclk_switching) {
842 0 : mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
843 0 : sclk = ps->performance_levels[0].sclk;
844 0 : } else {
845 0 : mclk = ps->performance_levels[0].mclk;
846 0 : sclk = ps->performance_levels[0].sclk;
847 : }
848 :
849 0 : if (rps->vce_active) {
850 0 : if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
851 0 : sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
852 0 : if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
853 0 : mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
854 : }
855 :
856 0 : ps->performance_levels[0].sclk = sclk;
857 0 : ps->performance_levels[0].mclk = mclk;
858 :
859 0 : if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
860 0 : ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
861 :
862 0 : if (disable_mclk_switching) {
863 0 : if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
864 0 : ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
865 : } else {
866 0 : if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
867 0 : ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
868 : }
869 0 : }
870 :
871 0 : static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
872 : int min_temp, int max_temp)
873 : {
874 : int low_temp = 0 * 1000;
875 : int high_temp = 255 * 1000;
876 : u32 tmp;
877 :
878 0 : if (low_temp < min_temp)
879 0 : low_temp = min_temp;
880 0 : if (high_temp > max_temp)
881 0 : high_temp = max_temp;
882 0 : if (high_temp < low_temp) {
883 0 : DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
884 0 : return -EINVAL;
885 : }
886 :
887 0 : tmp = RREG32_SMC(CG_THERMAL_INT);
888 0 : tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
889 0 : tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
890 0 : CI_DIG_THERM_INTL(low_temp / 1000);
891 0 : WREG32_SMC(CG_THERMAL_INT, tmp);
892 :
893 : #if 0
894 : /* XXX: need to figure out how to handle this properly */
895 : tmp = RREG32_SMC(CG_THERMAL_CTRL);
896 : tmp &= DIG_THERM_DPM_MASK;
897 : tmp |= DIG_THERM_DPM(high_temp / 1000);
898 : WREG32_SMC(CG_THERMAL_CTRL, tmp);
899 : #endif
900 :
901 0 : rdev->pm.dpm.thermal.min_temp = low_temp;
902 0 : rdev->pm.dpm.thermal.max_temp = high_temp;
903 :
904 0 : return 0;
905 0 : }
906 :
907 0 : static int ci_thermal_enable_alert(struct radeon_device *rdev,
908 : bool enable)
909 : {
910 0 : u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
911 : PPSMC_Result result;
912 :
913 0 : if (enable) {
914 0 : thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
915 0 : WREG32_SMC(CG_THERMAL_INT, thermal_int);
916 0 : rdev->irq.dpm_thermal = false;
917 0 : result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
918 0 : if (result != PPSMC_Result_OK) {
919 : DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
920 0 : return -EINVAL;
921 : }
922 : } else {
923 0 : thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
924 0 : WREG32_SMC(CG_THERMAL_INT, thermal_int);
925 0 : rdev->irq.dpm_thermal = true;
926 0 : result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
927 0 : if (result != PPSMC_Result_OK) {
928 : DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
929 0 : return -EINVAL;
930 : }
931 : }
932 :
933 0 : return 0;
934 0 : }
935 :
936 0 : static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
937 : {
938 0 : struct ci_power_info *pi = ci_get_pi(rdev);
939 : u32 tmp;
940 :
941 0 : if (pi->fan_ctrl_is_in_default_mode) {
942 0 : tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
943 0 : pi->fan_ctrl_default_mode = tmp;
944 0 : tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
945 0 : pi->t_min = tmp;
946 0 : pi->fan_ctrl_is_in_default_mode = false;
947 0 : }
948 :
949 0 : tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
950 : tmp |= TMIN(0);
951 0 : WREG32_SMC(CG_FDO_CTRL2, tmp);
952 :
953 0 : tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
954 0 : tmp |= FDO_PWM_MODE(mode);
955 0 : WREG32_SMC(CG_FDO_CTRL2, tmp);
956 0 : }
957 :
958 0 : static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
959 : {
960 0 : struct ci_power_info *pi = ci_get_pi(rdev);
961 0 : SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
962 : u32 duty100;
963 : u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
964 : u16 fdo_min, slope1, slope2;
965 : u32 reference_clock, tmp;
966 : int ret;
967 : u64 tmp64;
968 :
969 0 : if (!pi->fan_table_start) {
970 0 : rdev->pm.dpm.fan.ucode_fan_control = false;
971 0 : return 0;
972 : }
973 :
974 0 : duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
975 :
976 0 : if (duty100 == 0) {
977 0 : rdev->pm.dpm.fan.ucode_fan_control = false;
978 0 : return 0;
979 : }
980 :
981 0 : tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
982 0 : do_div(tmp64, 10000);
983 0 : fdo_min = (u16)tmp64;
984 :
985 0 : t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
986 0 : t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
987 :
988 0 : pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
989 0 : pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
990 :
991 0 : slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
992 0 : slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
993 :
994 0 : fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
995 0 : fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
996 0 : fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
997 :
998 0 : fan_table.Slope1 = cpu_to_be16(slope1);
999 0 : fan_table.Slope2 = cpu_to_be16(slope2);
1000 :
1001 0 : fan_table.FdoMin = cpu_to_be16(fdo_min);
1002 :
1003 0 : fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
1004 :
1005 0 : fan_table.HystUp = cpu_to_be16(1);
1006 :
1007 0 : fan_table.HystSlope = cpu_to_be16(1);
1008 :
1009 0 : fan_table.TempRespLim = cpu_to_be16(5);
1010 :
1011 0 : reference_clock = radeon_get_xclk(rdev);
1012 :
1013 0 : fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1014 : reference_clock) / 1600);
1015 :
1016 0 : fan_table.FdoMax = cpu_to_be16((u16)duty100);
1017 :
1018 0 : tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1019 0 : fan_table.TempSrc = (uint8_t)tmp;
1020 :
1021 0 : ret = ci_copy_bytes_to_smc(rdev,
1022 0 : pi->fan_table_start,
1023 : (u8 *)(&fan_table),
1024 : sizeof(fan_table),
1025 0 : pi->sram_end);
1026 :
1027 0 : if (ret) {
1028 0 : DRM_ERROR("Failed to load fan table to the SMC.");
1029 0 : rdev->pm.dpm.fan.ucode_fan_control = false;
1030 0 : }
1031 :
1032 0 : return 0;
1033 0 : }
1034 :
1035 0 : static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1036 : {
1037 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1038 : PPSMC_Result ret;
1039 :
1040 0 : if (pi->caps_od_fuzzy_fan_control_support) {
1041 0 : ret = ci_send_msg_to_smc_with_parameter(rdev,
1042 : PPSMC_StartFanControl,
1043 : FAN_CONTROL_FUZZY);
1044 0 : if (ret != PPSMC_Result_OK)
1045 0 : return -EINVAL;
1046 0 : ret = ci_send_msg_to_smc_with_parameter(rdev,
1047 : PPSMC_MSG_SetFanPwmMax,
1048 0 : rdev->pm.dpm.fan.default_max_fan_pwm);
1049 0 : if (ret != PPSMC_Result_OK)
1050 0 : return -EINVAL;
1051 : } else {
1052 0 : ret = ci_send_msg_to_smc_with_parameter(rdev,
1053 : PPSMC_StartFanControl,
1054 : FAN_CONTROL_TABLE);
1055 0 : if (ret != PPSMC_Result_OK)
1056 0 : return -EINVAL;
1057 : }
1058 :
1059 0 : pi->fan_is_controlled_by_smc = true;
1060 0 : return 0;
1061 0 : }
1062 :
1063 0 : static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1064 : {
1065 : PPSMC_Result ret;
1066 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1067 :
1068 0 : ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1069 0 : if (ret == PPSMC_Result_OK) {
1070 0 : pi->fan_is_controlled_by_smc = false;
1071 0 : return 0;
1072 : } else
1073 0 : return -EINVAL;
1074 0 : }
1075 :
1076 0 : int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1077 : u32 *speed)
1078 : {
1079 : u32 duty, duty100;
1080 : u64 tmp64;
1081 :
1082 0 : if (rdev->pm.no_fan)
1083 0 : return -ENOENT;
1084 :
1085 0 : duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1086 0 : duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
1087 :
1088 0 : if (duty100 == 0)
1089 0 : return -EINVAL;
1090 :
1091 0 : tmp64 = (u64)duty * 100;
1092 0 : do_div(tmp64, duty100);
1093 0 : *speed = (u32)tmp64;
1094 :
1095 0 : if (*speed > 100)
1096 0 : *speed = 100;
1097 :
1098 0 : return 0;
1099 0 : }
1100 :
1101 0 : int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1102 : u32 speed)
1103 : {
1104 : u32 tmp;
1105 : u32 duty, duty100;
1106 : u64 tmp64;
1107 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1108 :
1109 0 : if (rdev->pm.no_fan)
1110 0 : return -ENOENT;
1111 :
1112 0 : if (pi->fan_is_controlled_by_smc)
1113 0 : return -EINVAL;
1114 :
1115 0 : if (speed > 100)
1116 0 : return -EINVAL;
1117 :
1118 0 : duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1119 :
1120 0 : if (duty100 == 0)
1121 0 : return -EINVAL;
1122 :
1123 0 : tmp64 = (u64)speed * duty100;
1124 0 : do_div(tmp64, 100);
1125 0 : duty = (u32)tmp64;
1126 :
1127 0 : tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1128 0 : tmp |= FDO_STATIC_DUTY(duty);
1129 0 : WREG32_SMC(CG_FDO_CTRL0, tmp);
1130 :
1131 0 : return 0;
1132 0 : }
1133 :
1134 0 : void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
1135 : {
1136 0 : if (mode) {
1137 : /* stop auto-manage */
1138 0 : if (rdev->pm.dpm.fan.ucode_fan_control)
1139 0 : ci_fan_ctrl_stop_smc_fan_control(rdev);
1140 0 : ci_fan_ctrl_set_static_mode(rdev, mode);
1141 0 : } else {
1142 : /* restart auto-manage */
1143 0 : if (rdev->pm.dpm.fan.ucode_fan_control)
1144 0 : ci_thermal_start_smc_fan_control(rdev);
1145 : else
1146 0 : ci_fan_ctrl_set_default_mode(rdev);
1147 : }
1148 0 : }
1149 :
1150 0 : u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev)
1151 : {
1152 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1153 : u32 tmp;
1154 :
1155 0 : if (pi->fan_is_controlled_by_smc)
1156 0 : return 0;
1157 :
1158 0 : tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
1159 0 : return (tmp >> FDO_PWM_MODE_SHIFT);
1160 0 : }
1161 :
1162 : #if 0
1163 : static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1164 : u32 *speed)
1165 : {
1166 : u32 tach_period;
1167 : u32 xclk = radeon_get_xclk(rdev);
1168 :
1169 : if (rdev->pm.no_fan)
1170 : return -ENOENT;
1171 :
1172 : if (rdev->pm.fan_pulses_per_revolution == 0)
1173 : return -ENOENT;
1174 :
1175 : tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1176 : if (tach_period == 0)
1177 : return -ENOENT;
1178 :
1179 : *speed = 60 * xclk * 10000 / tach_period;
1180 :
1181 : return 0;
1182 : }
1183 :
1184 : static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1185 : u32 speed)
1186 : {
1187 : u32 tach_period, tmp;
1188 : u32 xclk = radeon_get_xclk(rdev);
1189 :
1190 : if (rdev->pm.no_fan)
1191 : return -ENOENT;
1192 :
1193 : if (rdev->pm.fan_pulses_per_revolution == 0)
1194 : return -ENOENT;
1195 :
1196 : if ((speed < rdev->pm.fan_min_rpm) ||
1197 : (speed > rdev->pm.fan_max_rpm))
1198 : return -EINVAL;
1199 :
1200 : if (rdev->pm.dpm.fan.ucode_fan_control)
1201 : ci_fan_ctrl_stop_smc_fan_control(rdev);
1202 :
1203 : tach_period = 60 * xclk * 10000 / (8 * speed);
1204 : tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1205 : tmp |= TARGET_PERIOD(tach_period);
1206 : WREG32_SMC(CG_TACH_CTRL, tmp);
1207 :
1208 : ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1209 :
1210 : return 0;
1211 : }
1212 : #endif
1213 :
1214 0 : static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1215 : {
1216 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1217 : u32 tmp;
1218 :
1219 0 : if (!pi->fan_ctrl_is_in_default_mode) {
1220 0 : tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1221 0 : tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1222 0 : WREG32_SMC(CG_FDO_CTRL2, tmp);
1223 :
1224 0 : tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1225 0 : tmp |= TMIN(pi->t_min);
1226 0 : WREG32_SMC(CG_FDO_CTRL2, tmp);
1227 0 : pi->fan_ctrl_is_in_default_mode = true;
1228 0 : }
1229 0 : }
1230 :
1231 0 : static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1232 : {
1233 0 : if (rdev->pm.dpm.fan.ucode_fan_control) {
1234 0 : ci_fan_ctrl_start_smc_fan_control(rdev);
1235 0 : ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1236 0 : }
1237 0 : }
1238 :
1239 0 : static void ci_thermal_initialize(struct radeon_device *rdev)
1240 : {
1241 : u32 tmp;
1242 :
1243 0 : if (rdev->pm.fan_pulses_per_revolution) {
1244 0 : tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1245 0 : tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1246 0 : WREG32_SMC(CG_TACH_CTRL, tmp);
1247 0 : }
1248 :
1249 0 : tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1250 0 : tmp |= TACH_PWM_RESP_RATE(0x28);
1251 0 : WREG32_SMC(CG_FDO_CTRL2, tmp);
1252 0 : }
1253 :
1254 0 : static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1255 : {
1256 : int ret;
1257 :
1258 0 : ci_thermal_initialize(rdev);
1259 0 : ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1260 0 : if (ret)
1261 0 : return ret;
1262 0 : ret = ci_thermal_enable_alert(rdev, true);
1263 0 : if (ret)
1264 0 : return ret;
1265 0 : if (rdev->pm.dpm.fan.ucode_fan_control) {
1266 0 : ret = ci_thermal_setup_fan_table(rdev);
1267 0 : if (ret)
1268 0 : return ret;
1269 0 : ci_thermal_start_smc_fan_control(rdev);
1270 0 : }
1271 :
1272 0 : return 0;
1273 0 : }
1274 :
1275 0 : static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1276 : {
1277 0 : if (!rdev->pm.no_fan)
1278 0 : ci_fan_ctrl_set_default_mode(rdev);
1279 0 : }
1280 :
1281 : #if 0
1282 : static int ci_read_smc_soft_register(struct radeon_device *rdev,
1283 : u16 reg_offset, u32 *value)
1284 : {
1285 : struct ci_power_info *pi = ci_get_pi(rdev);
1286 :
1287 : return ci_read_smc_sram_dword(rdev,
1288 : pi->soft_regs_start + reg_offset,
1289 : value, pi->sram_end);
1290 : }
1291 : #endif
1292 :
1293 0 : static int ci_write_smc_soft_register(struct radeon_device *rdev,
1294 : u16 reg_offset, u32 value)
1295 : {
1296 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1297 :
1298 0 : return ci_write_smc_sram_dword(rdev,
1299 0 : pi->soft_regs_start + reg_offset,
1300 0 : value, pi->sram_end);
1301 : }
1302 :
1303 0 : static void ci_init_fps_limits(struct radeon_device *rdev)
1304 : {
1305 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1306 0 : SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1307 :
1308 0 : if (pi->caps_fps) {
1309 : u16 tmp;
1310 :
1311 : tmp = 45;
1312 0 : table->FpsHighT = cpu_to_be16(tmp);
1313 :
1314 : tmp = 30;
1315 0 : table->FpsLowT = cpu_to_be16(tmp);
1316 0 : }
1317 0 : }
1318 :
1319 0 : static int ci_update_sclk_t(struct radeon_device *rdev)
1320 : {
1321 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1322 : int ret = 0;
1323 0 : u32 low_sclk_interrupt_t = 0;
1324 :
1325 0 : if (pi->caps_sclk_throttle_low_notification) {
1326 0 : low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1327 :
1328 0 : ret = ci_copy_bytes_to_smc(rdev,
1329 0 : pi->dpm_table_start +
1330 : offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1331 : (u8 *)&low_sclk_interrupt_t,
1332 0 : sizeof(u32), pi->sram_end);
1333 :
1334 0 : }
1335 :
1336 0 : return ret;
1337 0 : }
1338 :
1339 0 : static void ci_get_leakage_voltages(struct radeon_device *rdev)
1340 : {
1341 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1342 0 : u16 leakage_id, virtual_voltage_id;
1343 0 : u16 vddc, vddci;
1344 : int i;
1345 :
1346 0 : pi->vddc_leakage.count = 0;
1347 0 : pi->vddci_leakage.count = 0;
1348 :
1349 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1350 0 : for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1351 0 : virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1352 0 : if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1353 : continue;
1354 0 : if (vddc != 0 && vddc != virtual_voltage_id) {
1355 0 : pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1356 0 : pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1357 0 : pi->vddc_leakage.count++;
1358 0 : }
1359 : }
1360 0 : } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1361 0 : for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1362 0 : virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1363 0 : if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1364 : virtual_voltage_id,
1365 0 : leakage_id) == 0) {
1366 0 : if (vddc != 0 && vddc != virtual_voltage_id) {
1367 0 : pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1368 0 : pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1369 0 : pi->vddc_leakage.count++;
1370 0 : }
1371 0 : if (vddci != 0 && vddci != virtual_voltage_id) {
1372 0 : pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1373 0 : pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1374 0 : pi->vddci_leakage.count++;
1375 0 : }
1376 : }
1377 : }
1378 : }
1379 0 : }
1380 :
1381 0 : static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1382 : {
1383 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1384 : bool want_thermal_protection;
1385 : enum radeon_dpm_event_src dpm_event_src;
1386 : u32 tmp;
1387 :
1388 0 : switch (sources) {
1389 : case 0:
1390 : default:
1391 : want_thermal_protection = false;
1392 0 : break;
1393 : case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1394 : want_thermal_protection = true;
1395 : dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1396 0 : break;
1397 : case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1398 : want_thermal_protection = true;
1399 : dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1400 0 : break;
1401 : case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1402 : (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1403 : want_thermal_protection = true;
1404 : dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1405 0 : break;
1406 : }
1407 :
1408 0 : if (want_thermal_protection) {
1409 : #if 0
1410 : /* XXX: need to figure out how to handle this properly */
1411 : tmp = RREG32_SMC(CG_THERMAL_CTRL);
1412 : tmp &= DPM_EVENT_SRC_MASK;
1413 : tmp |= DPM_EVENT_SRC(dpm_event_src);
1414 : WREG32_SMC(CG_THERMAL_CTRL, tmp);
1415 : #endif
1416 :
1417 : tmp = RREG32_SMC(GENERAL_PWRMGT);
1418 0 : if (pi->thermal_protection)
1419 0 : tmp &= ~THERMAL_PROTECTION_DIS;
1420 : else
1421 0 : tmp |= THERMAL_PROTECTION_DIS;
1422 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
1423 0 : } else {
1424 : tmp = RREG32_SMC(GENERAL_PWRMGT);
1425 0 : tmp |= THERMAL_PROTECTION_DIS;
1426 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
1427 : }
1428 0 : }
1429 :
1430 0 : static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1431 : enum radeon_dpm_auto_throttle_src source,
1432 : bool enable)
1433 : {
1434 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1435 :
1436 0 : if (enable) {
1437 0 : if (!(pi->active_auto_throttle_sources & (1 << source))) {
1438 0 : pi->active_auto_throttle_sources |= 1 << source;
1439 0 : ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1440 0 : }
1441 : } else {
1442 0 : if (pi->active_auto_throttle_sources & (1 << source)) {
1443 0 : pi->active_auto_throttle_sources &= ~(1 << source);
1444 0 : ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1445 0 : }
1446 : }
1447 0 : }
1448 :
1449 0 : static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1450 : {
1451 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1452 0 : ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1453 0 : }
1454 :
1455 0 : static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1456 : {
1457 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1458 : PPSMC_Result smc_result;
1459 :
1460 0 : if (!pi->need_update_smu7_dpm_table)
1461 0 : return 0;
1462 :
1463 0 : if ((!pi->sclk_dpm_key_disabled) &&
1464 0 : (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1465 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1466 0 : if (smc_result != PPSMC_Result_OK)
1467 0 : return -EINVAL;
1468 : }
1469 :
1470 0 : if ((!pi->mclk_dpm_key_disabled) &&
1471 0 : (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1472 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1473 0 : if (smc_result != PPSMC_Result_OK)
1474 0 : return -EINVAL;
1475 : }
1476 :
1477 0 : pi->need_update_smu7_dpm_table = 0;
1478 0 : return 0;
1479 0 : }
1480 :
1481 0 : static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1482 : {
1483 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1484 : PPSMC_Result smc_result;
1485 :
1486 0 : if (enable) {
1487 0 : if (!pi->sclk_dpm_key_disabled) {
1488 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1489 0 : if (smc_result != PPSMC_Result_OK)
1490 0 : return -EINVAL;
1491 : }
1492 :
1493 0 : if (!pi->mclk_dpm_key_disabled) {
1494 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1495 0 : if (smc_result != PPSMC_Result_OK)
1496 0 : return -EINVAL;
1497 :
1498 0 : WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1499 :
1500 0 : WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1501 0 : WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1502 0 : WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1503 :
1504 0 : udelay(10);
1505 :
1506 0 : WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1507 0 : WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1508 0 : WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1509 0 : }
1510 : } else {
1511 0 : if (!pi->sclk_dpm_key_disabled) {
1512 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1513 0 : if (smc_result != PPSMC_Result_OK)
1514 0 : return -EINVAL;
1515 : }
1516 :
1517 0 : if (!pi->mclk_dpm_key_disabled) {
1518 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1519 0 : if (smc_result != PPSMC_Result_OK)
1520 0 : return -EINVAL;
1521 : }
1522 : }
1523 :
1524 0 : return 0;
1525 0 : }
1526 :
1527 0 : static int ci_start_dpm(struct radeon_device *rdev)
1528 : {
1529 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1530 : PPSMC_Result smc_result;
1531 : int ret;
1532 : u32 tmp;
1533 :
1534 0 : tmp = RREG32_SMC(GENERAL_PWRMGT);
1535 0 : tmp |= GLOBAL_PWRMGT_EN;
1536 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
1537 :
1538 0 : tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1539 0 : tmp |= DYNAMIC_PM_EN;
1540 0 : WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1541 :
1542 0 : ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1543 :
1544 0 : WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1545 :
1546 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1547 0 : if (smc_result != PPSMC_Result_OK)
1548 0 : return -EINVAL;
1549 :
1550 0 : ret = ci_enable_sclk_mclk_dpm(rdev, true);
1551 0 : if (ret)
1552 0 : return ret;
1553 :
1554 0 : if (!pi->pcie_dpm_key_disabled) {
1555 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1556 0 : if (smc_result != PPSMC_Result_OK)
1557 0 : return -EINVAL;
1558 : }
1559 :
1560 0 : return 0;
1561 0 : }
1562 :
1563 0 : static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1564 : {
1565 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1566 : PPSMC_Result smc_result;
1567 :
1568 0 : if (!pi->need_update_smu7_dpm_table)
1569 0 : return 0;
1570 :
1571 0 : if ((!pi->sclk_dpm_key_disabled) &&
1572 0 : (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1573 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1574 0 : if (smc_result != PPSMC_Result_OK)
1575 0 : return -EINVAL;
1576 : }
1577 :
1578 0 : if ((!pi->mclk_dpm_key_disabled) &&
1579 0 : (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1580 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1581 0 : if (smc_result != PPSMC_Result_OK)
1582 0 : return -EINVAL;
1583 : }
1584 :
1585 0 : return 0;
1586 0 : }
1587 :
1588 0 : static int ci_stop_dpm(struct radeon_device *rdev)
1589 : {
1590 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1591 : PPSMC_Result smc_result;
1592 : int ret;
1593 : u32 tmp;
1594 :
1595 0 : tmp = RREG32_SMC(GENERAL_PWRMGT);
1596 0 : tmp &= ~GLOBAL_PWRMGT_EN;
1597 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
1598 :
1599 0 : tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1600 0 : tmp &= ~DYNAMIC_PM_EN;
1601 0 : WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1602 :
1603 0 : if (!pi->pcie_dpm_key_disabled) {
1604 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1605 0 : if (smc_result != PPSMC_Result_OK)
1606 0 : return -EINVAL;
1607 : }
1608 :
1609 0 : ret = ci_enable_sclk_mclk_dpm(rdev, false);
1610 0 : if (ret)
1611 0 : return ret;
1612 :
1613 0 : smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1614 0 : if (smc_result != PPSMC_Result_OK)
1615 0 : return -EINVAL;
1616 :
1617 0 : return 0;
1618 0 : }
1619 :
1620 0 : static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1621 : {
1622 0 : u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1623 :
1624 0 : if (enable)
1625 0 : tmp &= ~SCLK_PWRMGT_OFF;
1626 : else
1627 0 : tmp |= SCLK_PWRMGT_OFF;
1628 0 : WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1629 0 : }
1630 :
1631 : #if 0
1632 : static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1633 : bool ac_power)
1634 : {
1635 : struct ci_power_info *pi = ci_get_pi(rdev);
1636 : struct radeon_cac_tdp_table *cac_tdp_table =
1637 : rdev->pm.dpm.dyn_state.cac_tdp_table;
1638 : u32 power_limit;
1639 :
1640 : if (ac_power)
1641 : power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1642 : else
1643 : power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1644 :
1645 : ci_set_power_limit(rdev, power_limit);
1646 :
1647 : if (pi->caps_automatic_dc_transition) {
1648 : if (ac_power)
1649 : ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1650 : else
1651 : ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1652 : }
1653 :
1654 : return 0;
1655 : }
1656 : #endif
1657 :
1658 0 : static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1659 : PPSMC_Msg msg, u32 parameter)
1660 : {
1661 0 : WREG32(SMC_MSG_ARG_0, parameter);
1662 0 : return ci_send_msg_to_smc(rdev, msg);
1663 : }
1664 :
1665 0 : static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1666 : PPSMC_Msg msg, u32 *parameter)
1667 : {
1668 : PPSMC_Result smc_result;
1669 :
1670 0 : smc_result = ci_send_msg_to_smc(rdev, msg);
1671 :
1672 0 : if ((smc_result == PPSMC_Result_OK) && parameter)
1673 0 : *parameter = RREG32(SMC_MSG_ARG_0);
1674 :
1675 0 : return smc_result;
1676 : }
1677 :
1678 0 : static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1679 : {
1680 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1681 :
1682 0 : if (!pi->sclk_dpm_key_disabled) {
1683 : PPSMC_Result smc_result =
1684 0 : ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1685 0 : if (smc_result != PPSMC_Result_OK)
1686 0 : return -EINVAL;
1687 0 : }
1688 :
1689 0 : return 0;
1690 0 : }
1691 :
1692 0 : static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1693 : {
1694 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1695 :
1696 0 : if (!pi->mclk_dpm_key_disabled) {
1697 : PPSMC_Result smc_result =
1698 0 : ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1699 0 : if (smc_result != PPSMC_Result_OK)
1700 0 : return -EINVAL;
1701 0 : }
1702 :
1703 0 : return 0;
1704 0 : }
1705 :
1706 0 : static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1707 : {
1708 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1709 :
1710 0 : if (!pi->pcie_dpm_key_disabled) {
1711 : PPSMC_Result smc_result =
1712 0 : ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1713 0 : if (smc_result != PPSMC_Result_OK)
1714 0 : return -EINVAL;
1715 0 : }
1716 :
1717 0 : return 0;
1718 0 : }
1719 :
1720 0 : static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1721 : {
1722 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1723 :
1724 0 : if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1725 : PPSMC_Result smc_result =
1726 0 : ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1727 0 : if (smc_result != PPSMC_Result_OK)
1728 0 : return -EINVAL;
1729 0 : }
1730 :
1731 0 : return 0;
1732 0 : }
1733 :
1734 0 : static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1735 : u32 target_tdp)
1736 : {
1737 : PPSMC_Result smc_result =
1738 0 : ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1739 0 : if (smc_result != PPSMC_Result_OK)
1740 0 : return -EINVAL;
1741 0 : return 0;
1742 0 : }
1743 :
1744 : #if 0
1745 : static int ci_set_boot_state(struct radeon_device *rdev)
1746 : {
1747 : return ci_enable_sclk_mclk_dpm(rdev, false);
1748 : }
1749 : #endif
1750 :
1751 0 : static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1752 : {
1753 0 : u32 sclk_freq;
1754 : PPSMC_Result smc_result =
1755 0 : ci_send_msg_to_smc_return_parameter(rdev,
1756 : PPSMC_MSG_API_GetSclkFrequency,
1757 : &sclk_freq);
1758 0 : if (smc_result != PPSMC_Result_OK)
1759 0 : sclk_freq = 0;
1760 :
1761 0 : return sclk_freq;
1762 0 : }
1763 :
1764 0 : static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1765 : {
1766 0 : u32 mclk_freq;
1767 : PPSMC_Result smc_result =
1768 0 : ci_send_msg_to_smc_return_parameter(rdev,
1769 : PPSMC_MSG_API_GetMclkFrequency,
1770 : &mclk_freq);
1771 0 : if (smc_result != PPSMC_Result_OK)
1772 0 : mclk_freq = 0;
1773 :
1774 0 : return mclk_freq;
1775 0 : }
1776 :
1777 0 : static void ci_dpm_start_smc(struct radeon_device *rdev)
1778 : {
1779 : int i;
1780 :
1781 0 : ci_program_jump_on_start(rdev);
1782 0 : ci_start_smc_clock(rdev);
1783 0 : ci_start_smc(rdev);
1784 0 : for (i = 0; i < rdev->usec_timeout; i++) {
1785 0 : if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1786 : break;
1787 : }
1788 0 : }
1789 :
1790 0 : static void ci_dpm_stop_smc(struct radeon_device *rdev)
1791 : {
1792 0 : ci_reset_smc(rdev);
1793 0 : ci_stop_smc_clock(rdev);
1794 0 : }
1795 :
1796 0 : static int ci_process_firmware_header(struct radeon_device *rdev)
1797 : {
1798 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1799 0 : u32 tmp;
1800 : int ret;
1801 :
1802 0 : ret = ci_read_smc_sram_dword(rdev,
1803 : SMU7_FIRMWARE_HEADER_LOCATION +
1804 : offsetof(SMU7_Firmware_Header, DpmTable),
1805 0 : &tmp, pi->sram_end);
1806 0 : if (ret)
1807 0 : return ret;
1808 :
1809 0 : pi->dpm_table_start = tmp;
1810 :
1811 0 : ret = ci_read_smc_sram_dword(rdev,
1812 : SMU7_FIRMWARE_HEADER_LOCATION +
1813 : offsetof(SMU7_Firmware_Header, SoftRegisters),
1814 0 : &tmp, pi->sram_end);
1815 0 : if (ret)
1816 0 : return ret;
1817 :
1818 0 : pi->soft_regs_start = tmp;
1819 :
1820 0 : ret = ci_read_smc_sram_dword(rdev,
1821 : SMU7_FIRMWARE_HEADER_LOCATION +
1822 : offsetof(SMU7_Firmware_Header, mcRegisterTable),
1823 0 : &tmp, pi->sram_end);
1824 0 : if (ret)
1825 0 : return ret;
1826 :
1827 0 : pi->mc_reg_table_start = tmp;
1828 :
1829 0 : ret = ci_read_smc_sram_dword(rdev,
1830 : SMU7_FIRMWARE_HEADER_LOCATION +
1831 : offsetof(SMU7_Firmware_Header, FanTable),
1832 0 : &tmp, pi->sram_end);
1833 0 : if (ret)
1834 0 : return ret;
1835 :
1836 0 : pi->fan_table_start = tmp;
1837 :
1838 0 : ret = ci_read_smc_sram_dword(rdev,
1839 : SMU7_FIRMWARE_HEADER_LOCATION +
1840 : offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1841 0 : &tmp, pi->sram_end);
1842 0 : if (ret)
1843 0 : return ret;
1844 :
1845 0 : pi->arb_table_start = tmp;
1846 :
1847 0 : return 0;
1848 0 : }
1849 :
1850 0 : static void ci_read_clock_registers(struct radeon_device *rdev)
1851 : {
1852 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1853 :
1854 0 : pi->clock_registers.cg_spll_func_cntl =
1855 0 : RREG32_SMC(CG_SPLL_FUNC_CNTL);
1856 0 : pi->clock_registers.cg_spll_func_cntl_2 =
1857 0 : RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1858 0 : pi->clock_registers.cg_spll_func_cntl_3 =
1859 0 : RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1860 0 : pi->clock_registers.cg_spll_func_cntl_4 =
1861 0 : RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1862 0 : pi->clock_registers.cg_spll_spread_spectrum =
1863 0 : RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1864 0 : pi->clock_registers.cg_spll_spread_spectrum_2 =
1865 0 : RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1866 0 : pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1867 0 : pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1868 0 : pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1869 0 : pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1870 0 : pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1871 0 : pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1872 0 : pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1873 0 : pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1874 0 : pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1875 0 : }
1876 :
1877 0 : static void ci_init_sclk_t(struct radeon_device *rdev)
1878 : {
1879 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1880 :
1881 0 : pi->low_sclk_interrupt_t = 0;
1882 0 : }
1883 :
1884 0 : static void ci_enable_thermal_protection(struct radeon_device *rdev,
1885 : bool enable)
1886 : {
1887 0 : u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1888 :
1889 0 : if (enable)
1890 0 : tmp &= ~THERMAL_PROTECTION_DIS;
1891 : else
1892 0 : tmp |= THERMAL_PROTECTION_DIS;
1893 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
1894 0 : }
1895 :
1896 0 : static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1897 : {
1898 0 : u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1899 :
1900 0 : tmp |= STATIC_PM_EN;
1901 :
1902 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
1903 0 : }
1904 :
1905 : #if 0
1906 : static int ci_enter_ulp_state(struct radeon_device *rdev)
1907 : {
1908 :
1909 : WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1910 :
1911 : udelay(25000);
1912 :
1913 : return 0;
1914 : }
1915 :
1916 : static int ci_exit_ulp_state(struct radeon_device *rdev)
1917 : {
1918 : int i;
1919 :
1920 : WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1921 :
1922 : udelay(7000);
1923 :
1924 : for (i = 0; i < rdev->usec_timeout; i++) {
1925 : if (RREG32(SMC_RESP_0) == 1)
1926 : break;
1927 : udelay(1000);
1928 : }
1929 :
1930 : return 0;
1931 : }
1932 : #endif
1933 :
1934 0 : static int ci_notify_smc_display_change(struct radeon_device *rdev,
1935 : bool has_display)
1936 : {
1937 0 : PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1938 :
1939 0 : return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1940 : }
1941 :
1942 0 : static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1943 : bool enable)
1944 : {
1945 0 : struct ci_power_info *pi = ci_get_pi(rdev);
1946 :
1947 0 : if (enable) {
1948 0 : if (pi->caps_sclk_ds) {
1949 0 : if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1950 0 : return -EINVAL;
1951 : } else {
1952 0 : if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1953 0 : return -EINVAL;
1954 : }
1955 : } else {
1956 0 : if (pi->caps_sclk_ds) {
1957 0 : if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1958 0 : return -EINVAL;
1959 : }
1960 : }
1961 :
1962 0 : return 0;
1963 0 : }
1964 :
1965 0 : static void ci_program_display_gap(struct radeon_device *rdev)
1966 : {
1967 0 : u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1968 : u32 pre_vbi_time_in_us;
1969 : u32 frame_time_in_us;
1970 0 : u32 ref_clock = rdev->clock.spll.reference_freq;
1971 0 : u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1972 0 : u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1973 :
1974 0 : tmp &= ~DISP_GAP_MASK;
1975 0 : if (rdev->pm.dpm.new_active_crtc_count > 0)
1976 0 : tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1977 : else
1978 0 : tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1979 0 : WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1980 :
1981 0 : if (refresh_rate == 0)
1982 0 : refresh_rate = 60;
1983 0 : if (vblank_time == 0xffffffff)
1984 0 : vblank_time = 500;
1985 0 : frame_time_in_us = 1000000 / refresh_rate;
1986 : pre_vbi_time_in_us =
1987 0 : frame_time_in_us - 200 - vblank_time;
1988 0 : tmp = pre_vbi_time_in_us * (ref_clock / 100);
1989 :
1990 0 : WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1991 0 : ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1992 0 : ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1993 :
1994 :
1995 0 : ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1996 :
1997 0 : }
1998 :
1999 0 : static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
2000 : {
2001 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2002 : u32 tmp;
2003 :
2004 0 : if (enable) {
2005 0 : if (pi->caps_sclk_ss_support) {
2006 0 : tmp = RREG32_SMC(GENERAL_PWRMGT);
2007 0 : tmp |= DYN_SPREAD_SPECTRUM_EN;
2008 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
2009 0 : }
2010 : } else {
2011 0 : tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
2012 0 : tmp &= ~SSEN;
2013 0 : WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
2014 :
2015 0 : tmp = RREG32_SMC(GENERAL_PWRMGT);
2016 0 : tmp &= ~DYN_SPREAD_SPECTRUM_EN;
2017 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
2018 : }
2019 0 : }
2020 :
2021 0 : static void ci_program_sstp(struct radeon_device *rdev)
2022 : {
2023 0 : WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
2024 0 : }
2025 :
2026 0 : static void ci_enable_display_gap(struct radeon_device *rdev)
2027 : {
2028 0 : u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
2029 :
2030 0 : tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
2031 0 : tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
2032 : DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
2033 :
2034 0 : WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
2035 0 : }
2036 :
2037 0 : static void ci_program_vc(struct radeon_device *rdev)
2038 : {
2039 : u32 tmp;
2040 :
2041 0 : tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2042 0 : tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
2043 0 : WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2044 :
2045 0 : WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
2046 0 : WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
2047 0 : WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
2048 0 : WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
2049 0 : WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
2050 0 : WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
2051 0 : WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
2052 0 : WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
2053 0 : }
2054 :
2055 0 : static void ci_clear_vc(struct radeon_device *rdev)
2056 : {
2057 : u32 tmp;
2058 :
2059 0 : tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2060 0 : tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2061 0 : WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2062 :
2063 0 : WREG32_SMC(CG_FTV_0, 0);
2064 0 : WREG32_SMC(CG_FTV_1, 0);
2065 0 : WREG32_SMC(CG_FTV_2, 0);
2066 0 : WREG32_SMC(CG_FTV_3, 0);
2067 0 : WREG32_SMC(CG_FTV_4, 0);
2068 0 : WREG32_SMC(CG_FTV_5, 0);
2069 0 : WREG32_SMC(CG_FTV_6, 0);
2070 0 : WREG32_SMC(CG_FTV_7, 0);
2071 0 : }
2072 :
2073 0 : static int ci_upload_firmware(struct radeon_device *rdev)
2074 : {
2075 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2076 : int i, ret;
2077 :
2078 0 : for (i = 0; i < rdev->usec_timeout; i++) {
2079 0 : if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
2080 : break;
2081 : }
2082 0 : WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
2083 :
2084 0 : ci_stop_smc_clock(rdev);
2085 0 : ci_reset_smc(rdev);
2086 :
2087 0 : ret = ci_load_smc_ucode(rdev, pi->sram_end);
2088 :
2089 0 : return ret;
2090 :
2091 : }
2092 :
2093 0 : static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2094 : struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
2095 : struct atom_voltage_table *voltage_table)
2096 : {
2097 : u32 i;
2098 :
2099 0 : if (voltage_dependency_table == NULL)
2100 0 : return -EINVAL;
2101 :
2102 0 : voltage_table->mask_low = 0;
2103 0 : voltage_table->phase_delay = 0;
2104 :
2105 0 : voltage_table->count = voltage_dependency_table->count;
2106 0 : for (i = 0; i < voltage_table->count; i++) {
2107 0 : voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2108 0 : voltage_table->entries[i].smio_low = 0;
2109 : }
2110 :
2111 0 : return 0;
2112 0 : }
2113 :
2114 0 : static int ci_construct_voltage_tables(struct radeon_device *rdev)
2115 : {
2116 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2117 : int ret;
2118 :
2119 0 : if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2120 0 : ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2121 : VOLTAGE_OBJ_GPIO_LUT,
2122 0 : &pi->vddc_voltage_table);
2123 0 : if (ret)
2124 0 : return ret;
2125 0 : } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2126 0 : ret = ci_get_svi2_voltage_table(rdev,
2127 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2128 0 : &pi->vddc_voltage_table);
2129 0 : if (ret)
2130 0 : return ret;
2131 : }
2132 :
2133 0 : if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2134 0 : si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2135 : &pi->vddc_voltage_table);
2136 :
2137 0 : if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2138 0 : ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2139 : VOLTAGE_OBJ_GPIO_LUT,
2140 0 : &pi->vddci_voltage_table);
2141 0 : if (ret)
2142 0 : return ret;
2143 0 : } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2144 0 : ret = ci_get_svi2_voltage_table(rdev,
2145 0 : &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2146 0 : &pi->vddci_voltage_table);
2147 0 : if (ret)
2148 0 : return ret;
2149 : }
2150 :
2151 0 : if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2152 0 : si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2153 : &pi->vddci_voltage_table);
2154 :
2155 0 : if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2156 0 : ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2157 : VOLTAGE_OBJ_GPIO_LUT,
2158 0 : &pi->mvdd_voltage_table);
2159 0 : if (ret)
2160 0 : return ret;
2161 0 : } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2162 0 : ret = ci_get_svi2_voltage_table(rdev,
2163 0 : &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2164 0 : &pi->mvdd_voltage_table);
2165 0 : if (ret)
2166 0 : return ret;
2167 : }
2168 :
2169 0 : if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2170 0 : si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2171 : &pi->mvdd_voltage_table);
2172 :
2173 0 : return 0;
2174 0 : }
2175 :
2176 0 : static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2177 : struct atom_voltage_table_entry *voltage_table,
2178 : SMU7_Discrete_VoltageLevel *smc_voltage_table)
2179 : {
2180 : int ret;
2181 :
2182 0 : ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2183 0 : &smc_voltage_table->StdVoltageHiSidd,
2184 0 : &smc_voltage_table->StdVoltageLoSidd);
2185 :
2186 0 : if (ret) {
2187 0 : smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2188 0 : smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2189 0 : }
2190 :
2191 0 : smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2192 0 : smc_voltage_table->StdVoltageHiSidd =
2193 0 : cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2194 0 : smc_voltage_table->StdVoltageLoSidd =
2195 0 : cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2196 0 : }
2197 :
2198 0 : static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2199 : SMU7_Discrete_DpmTable *table)
2200 : {
2201 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2202 : unsigned int count;
2203 :
2204 0 : table->VddcLevelCount = pi->vddc_voltage_table.count;
2205 0 : for (count = 0; count < table->VddcLevelCount; count++) {
2206 0 : ci_populate_smc_voltage_table(rdev,
2207 0 : &pi->vddc_voltage_table.entries[count],
2208 0 : &table->VddcLevel[count]);
2209 :
2210 0 : if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2211 0 : table->VddcLevel[count].Smio |=
2212 0 : pi->vddc_voltage_table.entries[count].smio_low;
2213 : else
2214 0 : table->VddcLevel[count].Smio = 0;
2215 : }
2216 0 : table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2217 :
2218 0 : return 0;
2219 : }
2220 :
2221 0 : static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2222 : SMU7_Discrete_DpmTable *table)
2223 : {
2224 : unsigned int count;
2225 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2226 :
2227 0 : table->VddciLevelCount = pi->vddci_voltage_table.count;
2228 0 : for (count = 0; count < table->VddciLevelCount; count++) {
2229 0 : ci_populate_smc_voltage_table(rdev,
2230 0 : &pi->vddci_voltage_table.entries[count],
2231 0 : &table->VddciLevel[count]);
2232 :
2233 0 : if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2234 0 : table->VddciLevel[count].Smio |=
2235 0 : pi->vddci_voltage_table.entries[count].smio_low;
2236 : else
2237 0 : table->VddciLevel[count].Smio = 0;
2238 : }
2239 0 : table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2240 :
2241 0 : return 0;
2242 : }
2243 :
2244 0 : static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2245 : SMU7_Discrete_DpmTable *table)
2246 : {
2247 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2248 : unsigned int count;
2249 :
2250 0 : table->MvddLevelCount = pi->mvdd_voltage_table.count;
2251 0 : for (count = 0; count < table->MvddLevelCount; count++) {
2252 0 : ci_populate_smc_voltage_table(rdev,
2253 0 : &pi->mvdd_voltage_table.entries[count],
2254 0 : &table->MvddLevel[count]);
2255 :
2256 0 : if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2257 0 : table->MvddLevel[count].Smio |=
2258 0 : pi->mvdd_voltage_table.entries[count].smio_low;
2259 : else
2260 0 : table->MvddLevel[count].Smio = 0;
2261 : }
2262 0 : table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2263 :
2264 0 : return 0;
2265 : }
2266 :
2267 0 : static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2268 : SMU7_Discrete_DpmTable *table)
2269 : {
2270 : int ret;
2271 :
2272 0 : ret = ci_populate_smc_vddc_table(rdev, table);
2273 0 : if (ret)
2274 0 : return ret;
2275 :
2276 0 : ret = ci_populate_smc_vddci_table(rdev, table);
2277 0 : if (ret)
2278 0 : return ret;
2279 :
2280 0 : ret = ci_populate_smc_mvdd_table(rdev, table);
2281 0 : if (ret)
2282 0 : return ret;
2283 :
2284 0 : return 0;
2285 0 : }
2286 :
2287 0 : static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2288 : SMU7_Discrete_VoltageLevel *voltage)
2289 : {
2290 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2291 : u32 i = 0;
2292 :
2293 0 : if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2294 0 : for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2295 0 : if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2296 0 : voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2297 0 : break;
2298 : }
2299 : }
2300 :
2301 0 : if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2302 0 : return -EINVAL;
2303 : }
2304 :
2305 0 : return -EINVAL;
2306 0 : }
2307 :
2308 0 : static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2309 : struct atom_voltage_table_entry *voltage_table,
2310 : u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2311 : {
2312 : u16 v_index, idx;
2313 : bool voltage_found = false;
2314 0 : *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2315 0 : *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2316 :
2317 0 : if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2318 0 : return -EINVAL;
2319 :
2320 0 : if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2321 0 : for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2322 0 : if (voltage_table->value ==
2323 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2324 : voltage_found = true;
2325 0 : if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2326 0 : idx = v_index;
2327 : else
2328 0 : idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2329 0 : *std_voltage_lo_sidd =
2330 0 : rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2331 0 : *std_voltage_hi_sidd =
2332 0 : rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2333 0 : break;
2334 : }
2335 : }
2336 :
2337 0 : if (!voltage_found) {
2338 0 : for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2339 0 : if (voltage_table->value <=
2340 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2341 : voltage_found = true;
2342 0 : if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2343 0 : idx = v_index;
2344 : else
2345 0 : idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2346 0 : *std_voltage_lo_sidd =
2347 0 : rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2348 0 : *std_voltage_hi_sidd =
2349 0 : rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2350 0 : break;
2351 : }
2352 : }
2353 : }
2354 : }
2355 :
2356 0 : return 0;
2357 0 : }
2358 :
2359 0 : static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2360 : const struct radeon_phase_shedding_limits_table *limits,
2361 : u32 sclk,
2362 : u32 *phase_shedding)
2363 : {
2364 : unsigned int i;
2365 :
2366 0 : *phase_shedding = 1;
2367 :
2368 0 : for (i = 0; i < limits->count; i++) {
2369 0 : if (sclk < limits->entries[i].sclk) {
2370 0 : *phase_shedding = i;
2371 0 : break;
2372 : }
2373 : }
2374 0 : }
2375 :
2376 0 : static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2377 : const struct radeon_phase_shedding_limits_table *limits,
2378 : u32 mclk,
2379 : u32 *phase_shedding)
2380 : {
2381 : unsigned int i;
2382 :
2383 0 : *phase_shedding = 1;
2384 :
2385 0 : for (i = 0; i < limits->count; i++) {
2386 0 : if (mclk < limits->entries[i].mclk) {
2387 0 : *phase_shedding = i;
2388 0 : break;
2389 : }
2390 : }
2391 0 : }
2392 :
2393 0 : static int ci_init_arb_table_index(struct radeon_device *rdev)
2394 : {
2395 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2396 0 : u32 tmp;
2397 : int ret;
2398 :
2399 0 : ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2400 0 : &tmp, pi->sram_end);
2401 0 : if (ret)
2402 0 : return ret;
2403 :
2404 0 : tmp &= 0x00FFFFFF;
2405 0 : tmp |= MC_CG_ARB_FREQ_F1 << 24;
2406 :
2407 0 : return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2408 0 : tmp, pi->sram_end);
2409 0 : }
2410 :
2411 0 : static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2412 : struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2413 : u32 clock, u32 *voltage)
2414 : {
2415 : u32 i = 0;
2416 :
2417 0 : if (allowed_clock_voltage_table->count == 0)
2418 0 : return -EINVAL;
2419 :
2420 0 : for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2421 0 : if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2422 0 : *voltage = allowed_clock_voltage_table->entries[i].v;
2423 0 : return 0;
2424 : }
2425 : }
2426 :
2427 0 : *voltage = allowed_clock_voltage_table->entries[i-1].v;
2428 :
2429 0 : return 0;
2430 0 : }
2431 :
2432 0 : static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2433 : u32 sclk, u32 min_sclk_in_sr)
2434 : {
2435 : u32 i;
2436 : u32 tmp;
2437 0 : u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2438 : min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2439 :
2440 0 : if (sclk < min)
2441 0 : return 0;
2442 :
2443 0 : for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2444 0 : tmp = sclk / (1 << i);
2445 0 : if (tmp >= min || i == 0)
2446 : break;
2447 : }
2448 :
2449 0 : return (u8)i;
2450 0 : }
2451 :
2452 0 : static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2453 : {
2454 0 : return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2455 : }
2456 :
2457 0 : static int ci_reset_to_default(struct radeon_device *rdev)
2458 : {
2459 0 : return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2460 : 0 : -EINVAL;
2461 : }
2462 :
2463 0 : static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2464 : {
2465 : u32 tmp;
2466 :
2467 0 : tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2468 :
2469 0 : if (tmp == MC_CG_ARB_FREQ_F0)
2470 0 : return 0;
2471 :
2472 0 : return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2473 0 : }
2474 :
2475 0 : static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2476 : const u32 engine_clock,
2477 : const u32 memory_clock,
2478 : u32 *dram_timimg2)
2479 : {
2480 : bool patch;
2481 : u32 tmp, tmp2;
2482 :
2483 0 : tmp = RREG32(MC_SEQ_MISC0);
2484 0 : patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2485 :
2486 0 : if (patch &&
2487 0 : ((rdev->pdev->device == 0x67B0) ||
2488 0 : (rdev->pdev->device == 0x67B1))) {
2489 0 : if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2490 0 : tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2491 0 : *dram_timimg2 &= ~0x00ff0000;
2492 0 : *dram_timimg2 |= tmp2 << 16;
2493 0 : } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2494 0 : tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2495 0 : *dram_timimg2 &= ~0x00ff0000;
2496 0 : *dram_timimg2 |= tmp2 << 16;
2497 0 : }
2498 : }
2499 0 : }
2500 :
2501 :
2502 0 : static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2503 : u32 sclk,
2504 : u32 mclk,
2505 : SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2506 : {
2507 : u32 dram_timing;
2508 0 : u32 dram_timing2;
2509 : u32 burst_time;
2510 :
2511 0 : radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2512 :
2513 0 : dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2514 0 : dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2515 0 : burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2516 :
2517 0 : ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2518 :
2519 0 : arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2520 0 : arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2521 0 : arb_regs->McArbBurstTime = (u8)burst_time;
2522 :
2523 0 : return 0;
2524 0 : }
2525 :
2526 0 : static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2527 : {
2528 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2529 0 : SMU7_Discrete_MCArbDramTimingTable arb_regs;
2530 : u32 i, j;
2531 : int ret = 0;
2532 :
2533 0 : memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2534 :
2535 0 : for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2536 0 : for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2537 0 : ret = ci_populate_memory_timing_parameters(rdev,
2538 0 : pi->dpm_table.sclk_table.dpm_levels[i].value,
2539 0 : pi->dpm_table.mclk_table.dpm_levels[j].value,
2540 0 : &arb_regs.entries[i][j]);
2541 0 : if (ret)
2542 : break;
2543 : }
2544 : }
2545 :
2546 0 : if (ret == 0)
2547 0 : ret = ci_copy_bytes_to_smc(rdev,
2548 0 : pi->arb_table_start,
2549 : (u8 *)&arb_regs,
2550 : sizeof(SMU7_Discrete_MCArbDramTimingTable),
2551 0 : pi->sram_end);
2552 :
2553 0 : return ret;
2554 0 : }
2555 :
2556 0 : static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2557 : {
2558 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2559 :
2560 0 : if (pi->need_update_smu7_dpm_table == 0)
2561 0 : return 0;
2562 :
2563 0 : return ci_do_program_memory_timing_parameters(rdev);
2564 0 : }
2565 :
2566 0 : static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2567 : struct radeon_ps *radeon_boot_state)
2568 : {
2569 0 : struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2570 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2571 : u32 level = 0;
2572 :
2573 0 : for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2574 0 : if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2575 0 : boot_state->performance_levels[0].sclk) {
2576 0 : pi->smc_state_table.GraphicsBootLevel = level;
2577 0 : break;
2578 : }
2579 : }
2580 :
2581 0 : for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2582 0 : if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2583 0 : boot_state->performance_levels[0].mclk) {
2584 0 : pi->smc_state_table.MemoryBootLevel = level;
2585 0 : break;
2586 : }
2587 : }
2588 0 : }
2589 :
2590 0 : static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2591 : {
2592 : u32 i;
2593 : u32 mask_value = 0;
2594 :
2595 0 : for (i = dpm_table->count; i > 0; i--) {
2596 0 : mask_value = mask_value << 1;
2597 0 : if (dpm_table->dpm_levels[i-1].enabled)
2598 0 : mask_value |= 0x1;
2599 : else
2600 : mask_value &= 0xFFFFFFFE;
2601 : }
2602 :
2603 0 : return mask_value;
2604 : }
2605 :
2606 0 : static void ci_populate_smc_link_level(struct radeon_device *rdev,
2607 : SMU7_Discrete_DpmTable *table)
2608 : {
2609 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2610 0 : struct ci_dpm_table *dpm_table = &pi->dpm_table;
2611 : u32 i;
2612 :
2613 0 : for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2614 0 : table->LinkLevel[i].PcieGenSpeed =
2615 0 : (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2616 0 : table->LinkLevel[i].PcieLaneCount =
2617 0 : r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2618 0 : table->LinkLevel[i].EnabledForActivity = 1;
2619 0 : table->LinkLevel[i].DownT = cpu_to_be32(5);
2620 0 : table->LinkLevel[i].UpT = cpu_to_be32(30);
2621 : }
2622 :
2623 0 : pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2624 0 : pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2625 0 : ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2626 0 : }
2627 :
2628 0 : static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2629 : SMU7_Discrete_DpmTable *table)
2630 : {
2631 : u32 count;
2632 0 : struct atom_clock_dividers dividers;
2633 : int ret = -EINVAL;
2634 :
2635 0 : table->UvdLevelCount =
2636 0 : rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2637 :
2638 0 : for (count = 0; count < table->UvdLevelCount; count++) {
2639 0 : table->UvdLevel[count].VclkFrequency =
2640 0 : rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2641 0 : table->UvdLevel[count].DclkFrequency =
2642 0 : rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2643 0 : table->UvdLevel[count].MinVddc =
2644 0 : rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2645 0 : table->UvdLevel[count].MinVddcPhases = 1;
2646 :
2647 0 : ret = radeon_atom_get_clock_dividers(rdev,
2648 : COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2649 0 : table->UvdLevel[count].VclkFrequency, false, ÷rs);
2650 0 : if (ret)
2651 0 : return ret;
2652 :
2653 0 : table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2654 :
2655 0 : ret = radeon_atom_get_clock_dividers(rdev,
2656 : COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2657 0 : table->UvdLevel[count].DclkFrequency, false, ÷rs);
2658 0 : if (ret)
2659 0 : return ret;
2660 :
2661 0 : table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2662 :
2663 0 : table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2664 0 : table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2665 0 : table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2666 : }
2667 :
2668 0 : return ret;
2669 0 : }
2670 :
2671 0 : static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2672 : SMU7_Discrete_DpmTable *table)
2673 : {
2674 : u32 count;
2675 0 : struct atom_clock_dividers dividers;
2676 : int ret = -EINVAL;
2677 :
2678 0 : table->VceLevelCount =
2679 0 : rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2680 :
2681 0 : for (count = 0; count < table->VceLevelCount; count++) {
2682 0 : table->VceLevel[count].Frequency =
2683 0 : rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2684 0 : table->VceLevel[count].MinVoltage =
2685 0 : (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2686 0 : table->VceLevel[count].MinPhases = 1;
2687 :
2688 0 : ret = radeon_atom_get_clock_dividers(rdev,
2689 : COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2690 0 : table->VceLevel[count].Frequency, false, ÷rs);
2691 0 : if (ret)
2692 0 : return ret;
2693 :
2694 0 : table->VceLevel[count].Divider = (u8)dividers.post_divider;
2695 :
2696 0 : table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2697 0 : table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2698 : }
2699 :
2700 0 : return ret;
2701 :
2702 0 : }
2703 :
2704 0 : static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2705 : SMU7_Discrete_DpmTable *table)
2706 : {
2707 : u32 count;
2708 0 : struct atom_clock_dividers dividers;
2709 : int ret = -EINVAL;
2710 :
2711 0 : table->AcpLevelCount = (u8)
2712 0 : (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2713 :
2714 0 : for (count = 0; count < table->AcpLevelCount; count++) {
2715 0 : table->AcpLevel[count].Frequency =
2716 0 : rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2717 0 : table->AcpLevel[count].MinVoltage =
2718 0 : rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2719 0 : table->AcpLevel[count].MinPhases = 1;
2720 :
2721 0 : ret = radeon_atom_get_clock_dividers(rdev,
2722 : COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2723 0 : table->AcpLevel[count].Frequency, false, ÷rs);
2724 0 : if (ret)
2725 0 : return ret;
2726 :
2727 0 : table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2728 :
2729 0 : table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2730 0 : table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2731 : }
2732 :
2733 0 : return ret;
2734 0 : }
2735 :
2736 0 : static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2737 : SMU7_Discrete_DpmTable *table)
2738 : {
2739 : u32 count;
2740 0 : struct atom_clock_dividers dividers;
2741 : int ret = -EINVAL;
2742 :
2743 0 : table->SamuLevelCount =
2744 0 : rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2745 :
2746 0 : for (count = 0; count < table->SamuLevelCount; count++) {
2747 0 : table->SamuLevel[count].Frequency =
2748 0 : rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2749 0 : table->SamuLevel[count].MinVoltage =
2750 0 : rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2751 0 : table->SamuLevel[count].MinPhases = 1;
2752 :
2753 0 : ret = radeon_atom_get_clock_dividers(rdev,
2754 : COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2755 0 : table->SamuLevel[count].Frequency, false, ÷rs);
2756 0 : if (ret)
2757 0 : return ret;
2758 :
2759 0 : table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2760 :
2761 0 : table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2762 0 : table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2763 : }
2764 :
2765 0 : return ret;
2766 0 : }
2767 :
2768 0 : static int ci_calculate_mclk_params(struct radeon_device *rdev,
2769 : u32 memory_clock,
2770 : SMU7_Discrete_MemoryLevel *mclk,
2771 : bool strobe_mode,
2772 : bool dll_state_on)
2773 : {
2774 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2775 0 : u32 dll_cntl = pi->clock_registers.dll_cntl;
2776 0 : u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2777 0 : u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2778 0 : u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2779 0 : u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2780 0 : u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2781 0 : u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2782 0 : u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2783 0 : u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2784 0 : struct atom_mpll_param mpll_param;
2785 : int ret;
2786 :
2787 0 : ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2788 0 : if (ret)
2789 0 : return ret;
2790 :
2791 0 : mpll_func_cntl &= ~BWCTRL_MASK;
2792 0 : mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2793 :
2794 0 : mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2795 0 : mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2796 0 : CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2797 :
2798 0 : mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2799 0 : mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2800 :
2801 0 : if (pi->mem_gddr5) {
2802 0 : mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2803 0 : mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2804 : YCLK_POST_DIV(mpll_param.post_div);
2805 0 : }
2806 :
2807 0 : if (pi->caps_mclk_ss_support) {
2808 0 : struct radeon_atom_ss ss;
2809 : u32 freq_nom;
2810 : u32 tmp;
2811 0 : u32 reference_clock = rdev->clock.mpll.reference_freq;
2812 :
2813 0 : if (mpll_param.qdr == 1)
2814 0 : freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2815 : else
2816 0 : freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2817 :
2818 0 : tmp = (freq_nom / reference_clock);
2819 0 : tmp = tmp * tmp;
2820 0 : if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2821 : ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2822 0 : u32 clks = reference_clock * 5 / ss.rate;
2823 0 : u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2824 :
2825 0 : mpll_ss1 &= ~CLKV_MASK;
2826 0 : mpll_ss1 |= CLKV(clkv);
2827 :
2828 0 : mpll_ss2 &= ~CLKS_MASK;
2829 0 : mpll_ss2 |= CLKS(clks);
2830 0 : }
2831 0 : }
2832 :
2833 0 : mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2834 0 : mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2835 :
2836 0 : if (dll_state_on)
2837 0 : mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2838 : else
2839 0 : mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2840 :
2841 0 : mclk->MclkFrequency = memory_clock;
2842 0 : mclk->MpllFuncCntl = mpll_func_cntl;
2843 0 : mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2844 0 : mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2845 0 : mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2846 0 : mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2847 0 : mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2848 0 : mclk->DllCntl = dll_cntl;
2849 0 : mclk->MpllSs1 = mpll_ss1;
2850 0 : mclk->MpllSs2 = mpll_ss2;
2851 :
2852 0 : return 0;
2853 0 : }
2854 :
2855 0 : static int ci_populate_single_memory_level(struct radeon_device *rdev,
2856 : u32 memory_clock,
2857 : SMU7_Discrete_MemoryLevel *memory_level)
2858 : {
2859 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2860 : int ret;
2861 : bool dll_state_on;
2862 :
2863 0 : if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2864 0 : ret = ci_get_dependency_volt_by_clk(rdev,
2865 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2866 0 : memory_clock, &memory_level->MinVddc);
2867 0 : if (ret)
2868 0 : return ret;
2869 : }
2870 :
2871 0 : if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2872 0 : ret = ci_get_dependency_volt_by_clk(rdev,
2873 : &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2874 0 : memory_clock, &memory_level->MinVddci);
2875 0 : if (ret)
2876 0 : return ret;
2877 : }
2878 :
2879 0 : if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2880 0 : ret = ci_get_dependency_volt_by_clk(rdev,
2881 : &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2882 0 : memory_clock, &memory_level->MinMvdd);
2883 0 : if (ret)
2884 0 : return ret;
2885 : }
2886 :
2887 0 : memory_level->MinVddcPhases = 1;
2888 :
2889 0 : if (pi->vddc_phase_shed_control)
2890 0 : ci_populate_phase_value_based_on_mclk(rdev,
2891 0 : &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2892 : memory_clock,
2893 : &memory_level->MinVddcPhases);
2894 :
2895 0 : memory_level->EnabledForThrottle = 1;
2896 0 : memory_level->UpH = 0;
2897 0 : memory_level->DownH = 100;
2898 0 : memory_level->VoltageDownH = 0;
2899 0 : memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2900 :
2901 0 : memory_level->StutterEnable = false;
2902 0 : memory_level->StrobeEnable = false;
2903 0 : memory_level->EdcReadEnable = false;
2904 0 : memory_level->EdcWriteEnable = false;
2905 0 : memory_level->RttEnable = false;
2906 :
2907 0 : memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2908 :
2909 0 : if (pi->mclk_stutter_mode_threshold &&
2910 0 : (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2911 0 : (pi->uvd_enabled == false) &&
2912 0 : (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2913 0 : (rdev->pm.dpm.new_active_crtc_count <= 2))
2914 0 : memory_level->StutterEnable = true;
2915 :
2916 0 : if (pi->mclk_strobe_mode_threshold &&
2917 0 : (memory_clock <= pi->mclk_strobe_mode_threshold))
2918 0 : memory_level->StrobeEnable = 1;
2919 :
2920 0 : if (pi->mem_gddr5) {
2921 0 : memory_level->StrobeRatio =
2922 0 : si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2923 0 : if (pi->mclk_edc_enable_threshold &&
2924 0 : (memory_clock > pi->mclk_edc_enable_threshold))
2925 0 : memory_level->EdcReadEnable = true;
2926 :
2927 0 : if (pi->mclk_edc_wr_enable_threshold &&
2928 0 : (memory_clock > pi->mclk_edc_wr_enable_threshold))
2929 0 : memory_level->EdcWriteEnable = true;
2930 :
2931 0 : if (memory_level->StrobeEnable) {
2932 0 : if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2933 0 : ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2934 0 : dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2935 : else
2936 0 : dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2937 : } else {
2938 0 : dll_state_on = pi->dll_default_on;
2939 : }
2940 : } else {
2941 0 : memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2942 0 : dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2943 : }
2944 :
2945 0 : ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2946 0 : if (ret)
2947 0 : return ret;
2948 :
2949 0 : memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2950 0 : memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2951 0 : memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2952 0 : memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2953 :
2954 0 : memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2955 0 : memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2956 0 : memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2957 0 : memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2958 0 : memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2959 0 : memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2960 0 : memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2961 0 : memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2962 0 : memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2963 0 : memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2964 0 : memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2965 :
2966 0 : return 0;
2967 0 : }
2968 :
2969 0 : static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2970 : SMU7_Discrete_DpmTable *table)
2971 : {
2972 0 : struct ci_power_info *pi = ci_get_pi(rdev);
2973 0 : struct atom_clock_dividers dividers;
2974 0 : SMU7_Discrete_VoltageLevel voltage_level;
2975 0 : u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2976 0 : u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2977 0 : u32 dll_cntl = pi->clock_registers.dll_cntl;
2978 0 : u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2979 : int ret;
2980 :
2981 0 : table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2982 :
2983 0 : if (pi->acpi_vddc)
2984 0 : table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2985 : else
2986 0 : table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2987 :
2988 0 : table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2989 :
2990 0 : table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2991 :
2992 0 : ret = radeon_atom_get_clock_dividers(rdev,
2993 : COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2994 : table->ACPILevel.SclkFrequency, false, ÷rs);
2995 0 : if (ret)
2996 0 : return ret;
2997 :
2998 0 : table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2999 0 : table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3000 0 : table->ACPILevel.DeepSleepDivId = 0;
3001 :
3002 0 : spll_func_cntl &= ~SPLL_PWRON;
3003 0 : spll_func_cntl |= SPLL_RESET;
3004 :
3005 0 : spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
3006 0 : spll_func_cntl_2 |= SCLK_MUX_SEL(4);
3007 :
3008 0 : table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
3009 0 : table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
3010 0 : table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
3011 0 : table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
3012 0 : table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
3013 0 : table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3014 0 : table->ACPILevel.CcPwrDynRm = 0;
3015 0 : table->ACPILevel.CcPwrDynRm1 = 0;
3016 :
3017 0 : table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
3018 0 : table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
3019 0 : table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
3020 0 : table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
3021 0 : table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
3022 0 : table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
3023 0 : table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
3024 0 : table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
3025 0 : table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
3026 0 : table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
3027 0 : table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
3028 :
3029 0 : table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
3030 0 : table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
3031 :
3032 0 : if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
3033 0 : if (pi->acpi_vddci)
3034 0 : table->MemoryACPILevel.MinVddci =
3035 0 : cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
3036 : else
3037 0 : table->MemoryACPILevel.MinVddci =
3038 0 : cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
3039 : }
3040 :
3041 0 : if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
3042 0 : table->MemoryACPILevel.MinMvdd = 0;
3043 : else
3044 0 : table->MemoryACPILevel.MinMvdd =
3045 0 : cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3046 :
3047 0 : mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
3048 0 : mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
3049 :
3050 0 : dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
3051 :
3052 0 : table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3053 0 : table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3054 0 : table->MemoryACPILevel.MpllAdFuncCntl =
3055 0 : cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3056 0 : table->MemoryACPILevel.MpllDqFuncCntl =
3057 0 : cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3058 0 : table->MemoryACPILevel.MpllFuncCntl =
3059 0 : cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3060 0 : table->MemoryACPILevel.MpllFuncCntl_1 =
3061 0 : cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3062 0 : table->MemoryACPILevel.MpllFuncCntl_2 =
3063 0 : cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3064 0 : table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3065 0 : table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3066 :
3067 0 : table->MemoryACPILevel.EnabledForThrottle = 0;
3068 0 : table->MemoryACPILevel.EnabledForActivity = 0;
3069 0 : table->MemoryACPILevel.UpH = 0;
3070 0 : table->MemoryACPILevel.DownH = 100;
3071 0 : table->MemoryACPILevel.VoltageDownH = 0;
3072 0 : table->MemoryACPILevel.ActivityLevel =
3073 0 : cpu_to_be16((u16)pi->mclk_activity_target);
3074 :
3075 0 : table->MemoryACPILevel.StutterEnable = false;
3076 0 : table->MemoryACPILevel.StrobeEnable = false;
3077 0 : table->MemoryACPILevel.EdcReadEnable = false;
3078 0 : table->MemoryACPILevel.EdcWriteEnable = false;
3079 0 : table->MemoryACPILevel.RttEnable = false;
3080 :
3081 0 : return 0;
3082 0 : }
3083 :
3084 :
3085 0 : static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3086 : {
3087 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3088 0 : struct ci_ulv_parm *ulv = &pi->ulv;
3089 :
3090 0 : if (ulv->supported) {
3091 0 : if (enable)
3092 0 : return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3093 : 0 : -EINVAL;
3094 : else
3095 0 : return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3096 : 0 : -EINVAL;
3097 : }
3098 :
3099 0 : return 0;
3100 0 : }
3101 :
3102 0 : static int ci_populate_ulv_level(struct radeon_device *rdev,
3103 : SMU7_Discrete_Ulv *state)
3104 : {
3105 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3106 0 : u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3107 :
3108 0 : state->CcPwrDynRm = 0;
3109 0 : state->CcPwrDynRm1 = 0;
3110 :
3111 0 : if (ulv_voltage == 0) {
3112 0 : pi->ulv.supported = false;
3113 0 : return 0;
3114 : }
3115 :
3116 0 : if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3117 0 : if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3118 0 : state->VddcOffset = 0;
3119 : else
3120 0 : state->VddcOffset =
3121 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3122 : } else {
3123 0 : if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3124 0 : state->VddcOffsetVid = 0;
3125 : else
3126 0 : state->VddcOffsetVid = (u8)
3127 0 : ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3128 0 : VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3129 : }
3130 0 : state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3131 :
3132 0 : state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3133 0 : state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3134 0 : state->VddcOffset = cpu_to_be16(state->VddcOffset);
3135 :
3136 0 : return 0;
3137 0 : }
3138 :
3139 0 : static int ci_calculate_sclk_params(struct radeon_device *rdev,
3140 : u32 engine_clock,
3141 : SMU7_Discrete_GraphicsLevel *sclk)
3142 : {
3143 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3144 0 : struct atom_clock_dividers dividers;
3145 0 : u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3146 0 : u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3147 0 : u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3148 0 : u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3149 0 : u32 reference_clock = rdev->clock.spll.reference_freq;
3150 : u32 reference_divider;
3151 : u32 fbdiv;
3152 : int ret;
3153 :
3154 0 : ret = radeon_atom_get_clock_dividers(rdev,
3155 : COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3156 : engine_clock, false, ÷rs);
3157 0 : if (ret)
3158 0 : return ret;
3159 :
3160 0 : reference_divider = 1 + dividers.ref_div;
3161 0 : fbdiv = dividers.fb_div & 0x3FFFFFF;
3162 :
3163 0 : spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
3164 0 : spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
3165 0 : spll_func_cntl_3 |= SPLL_DITHEN;
3166 :
3167 0 : if (pi->caps_sclk_ss_support) {
3168 0 : struct radeon_atom_ss ss;
3169 0 : u32 vco_freq = engine_clock * dividers.post_div;
3170 :
3171 0 : if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3172 : ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3173 0 : u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3174 0 : u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3175 :
3176 0 : cg_spll_spread_spectrum &= ~CLK_S_MASK;
3177 0 : cg_spll_spread_spectrum |= CLK_S(clk_s);
3178 0 : cg_spll_spread_spectrum |= SSEN;
3179 :
3180 0 : cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
3181 0 : cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
3182 0 : }
3183 0 : }
3184 :
3185 0 : sclk->SclkFrequency = engine_clock;
3186 0 : sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3187 0 : sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3188 0 : sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3189 0 : sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3190 0 : sclk->SclkDid = (u8)dividers.post_divider;
3191 :
3192 0 : return 0;
3193 0 : }
3194 :
3195 0 : static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3196 : u32 engine_clock,
3197 : u16 sclk_activity_level_t,
3198 : SMU7_Discrete_GraphicsLevel *graphic_level)
3199 : {
3200 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3201 : int ret;
3202 :
3203 0 : ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3204 0 : if (ret)
3205 0 : return ret;
3206 :
3207 0 : ret = ci_get_dependency_volt_by_clk(rdev,
3208 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3209 0 : engine_clock, &graphic_level->MinVddc);
3210 0 : if (ret)
3211 0 : return ret;
3212 :
3213 0 : graphic_level->SclkFrequency = engine_clock;
3214 :
3215 0 : graphic_level->Flags = 0;
3216 0 : graphic_level->MinVddcPhases = 1;
3217 :
3218 0 : if (pi->vddc_phase_shed_control)
3219 0 : ci_populate_phase_value_based_on_sclk(rdev,
3220 0 : &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3221 : engine_clock,
3222 : &graphic_level->MinVddcPhases);
3223 :
3224 0 : graphic_level->ActivityLevel = sclk_activity_level_t;
3225 :
3226 0 : graphic_level->CcPwrDynRm = 0;
3227 0 : graphic_level->CcPwrDynRm1 = 0;
3228 0 : graphic_level->EnabledForThrottle = 1;
3229 0 : graphic_level->UpH = 0;
3230 0 : graphic_level->DownH = 0;
3231 0 : graphic_level->VoltageDownH = 0;
3232 0 : graphic_level->PowerThrottle = 0;
3233 :
3234 0 : if (pi->caps_sclk_ds)
3235 0 : graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3236 : engine_clock,
3237 : CISLAND_MINIMUM_ENGINE_CLOCK);
3238 :
3239 0 : graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3240 :
3241 0 : graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3242 0 : graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3243 0 : graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3244 0 : graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3245 0 : graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3246 0 : graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3247 0 : graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3248 0 : graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3249 0 : graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3250 0 : graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3251 0 : graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3252 :
3253 0 : return 0;
3254 0 : }
3255 :
3256 0 : static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3257 : {
3258 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3259 0 : struct ci_dpm_table *dpm_table = &pi->dpm_table;
3260 0 : u32 level_array_address = pi->dpm_table_start +
3261 : offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3262 : u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3263 : SMU7_MAX_LEVELS_GRAPHICS;
3264 0 : SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3265 : u32 i, ret;
3266 :
3267 0 : memset(levels, 0, level_array_size);
3268 :
3269 0 : for (i = 0; i < dpm_table->sclk_table.count; i++) {
3270 0 : ret = ci_populate_single_graphic_level(rdev,
3271 0 : dpm_table->sclk_table.dpm_levels[i].value,
3272 0 : (u16)pi->activity_target[i],
3273 0 : &pi->smc_state_table.GraphicsLevel[i]);
3274 0 : if (ret)
3275 0 : return ret;
3276 0 : if (i > 1)
3277 0 : pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3278 0 : if (i == (dpm_table->sclk_table.count - 1))
3279 0 : pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3280 : PPSMC_DISPLAY_WATERMARK_HIGH;
3281 : }
3282 0 : pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3283 :
3284 0 : pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3285 0 : pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3286 0 : ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3287 :
3288 0 : ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3289 : (u8 *)levels, level_array_size,
3290 0 : pi->sram_end);
3291 0 : if (ret)
3292 0 : return ret;
3293 :
3294 0 : return 0;
3295 0 : }
3296 :
3297 0 : static int ci_populate_ulv_state(struct radeon_device *rdev,
3298 : SMU7_Discrete_Ulv *ulv_level)
3299 : {
3300 0 : return ci_populate_ulv_level(rdev, ulv_level);
3301 : }
3302 :
3303 0 : static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3304 : {
3305 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3306 0 : struct ci_dpm_table *dpm_table = &pi->dpm_table;
3307 0 : u32 level_array_address = pi->dpm_table_start +
3308 : offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3309 : u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3310 : SMU7_MAX_LEVELS_MEMORY;
3311 0 : SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3312 : u32 i, ret;
3313 :
3314 0 : memset(levels, 0, level_array_size);
3315 :
3316 0 : for (i = 0; i < dpm_table->mclk_table.count; i++) {
3317 0 : if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3318 0 : return -EINVAL;
3319 0 : ret = ci_populate_single_memory_level(rdev,
3320 : dpm_table->mclk_table.dpm_levels[i].value,
3321 0 : &pi->smc_state_table.MemoryLevel[i]);
3322 0 : if (ret)
3323 0 : return ret;
3324 : }
3325 :
3326 0 : pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3327 :
3328 0 : if ((dpm_table->mclk_table.count >= 2) &&
3329 0 : ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3330 0 : pi->smc_state_table.MemoryLevel[1].MinVddc =
3331 0 : pi->smc_state_table.MemoryLevel[0].MinVddc;
3332 0 : pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3333 0 : pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3334 0 : }
3335 :
3336 0 : pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3337 :
3338 0 : pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3339 0 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3340 0 : ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3341 :
3342 0 : pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3343 : PPSMC_DISPLAY_WATERMARK_HIGH;
3344 :
3345 0 : ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3346 : (u8 *)levels, level_array_size,
3347 0 : pi->sram_end);
3348 0 : if (ret)
3349 0 : return ret;
3350 :
3351 0 : return 0;
3352 0 : }
3353 :
3354 0 : static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3355 : struct ci_single_dpm_table* dpm_table,
3356 : u32 count)
3357 : {
3358 : u32 i;
3359 :
3360 0 : dpm_table->count = count;
3361 0 : for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3362 0 : dpm_table->dpm_levels[i].enabled = false;
3363 0 : }
3364 :
3365 0 : static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3366 : u32 index, u32 pcie_gen, u32 pcie_lanes)
3367 : {
3368 0 : dpm_table->dpm_levels[index].value = pcie_gen;
3369 0 : dpm_table->dpm_levels[index].param1 = pcie_lanes;
3370 0 : dpm_table->dpm_levels[index].enabled = true;
3371 0 : }
3372 :
3373 0 : static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3374 : {
3375 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3376 :
3377 0 : if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3378 0 : return -EINVAL;
3379 :
3380 0 : if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3381 0 : pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3382 0 : pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3383 0 : } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3384 0 : pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3385 0 : pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3386 0 : }
3387 :
3388 0 : ci_reset_single_dpm_table(rdev,
3389 0 : &pi->dpm_table.pcie_speed_table,
3390 : SMU7_MAX_LEVELS_LINK);
3391 :
3392 0 : if (rdev->family == CHIP_BONAIRE)
3393 0 : ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3394 : pi->pcie_gen_powersaving.min,
3395 0 : pi->pcie_lane_powersaving.max);
3396 : else
3397 0 : ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3398 : pi->pcie_gen_powersaving.min,
3399 0 : pi->pcie_lane_powersaving.min);
3400 0 : ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3401 0 : pi->pcie_gen_performance.min,
3402 0 : pi->pcie_lane_performance.min);
3403 0 : ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3404 0 : pi->pcie_gen_powersaving.min,
3405 0 : pi->pcie_lane_powersaving.max);
3406 0 : ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3407 0 : pi->pcie_gen_performance.min,
3408 0 : pi->pcie_lane_performance.max);
3409 0 : ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3410 0 : pi->pcie_gen_powersaving.max,
3411 0 : pi->pcie_lane_powersaving.max);
3412 0 : ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3413 0 : pi->pcie_gen_performance.max,
3414 0 : pi->pcie_lane_performance.max);
3415 :
3416 0 : pi->dpm_table.pcie_speed_table.count = 6;
3417 :
3418 0 : return 0;
3419 0 : }
3420 :
3421 0 : static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3422 : {
3423 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3424 : struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3425 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3426 : struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3427 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3428 : struct radeon_cac_leakage_table *std_voltage_table =
3429 0 : &rdev->pm.dpm.dyn_state.cac_leakage_table;
3430 : u32 i;
3431 :
3432 0 : if (allowed_sclk_vddc_table == NULL)
3433 0 : return -EINVAL;
3434 0 : if (allowed_sclk_vddc_table->count < 1)
3435 0 : return -EINVAL;
3436 0 : if (allowed_mclk_table == NULL)
3437 0 : return -EINVAL;
3438 0 : if (allowed_mclk_table->count < 1)
3439 0 : return -EINVAL;
3440 :
3441 0 : memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3442 :
3443 0 : ci_reset_single_dpm_table(rdev,
3444 0 : &pi->dpm_table.sclk_table,
3445 : SMU7_MAX_LEVELS_GRAPHICS);
3446 0 : ci_reset_single_dpm_table(rdev,
3447 0 : &pi->dpm_table.mclk_table,
3448 : SMU7_MAX_LEVELS_MEMORY);
3449 0 : ci_reset_single_dpm_table(rdev,
3450 0 : &pi->dpm_table.vddc_table,
3451 : SMU7_MAX_LEVELS_VDDC);
3452 0 : ci_reset_single_dpm_table(rdev,
3453 0 : &pi->dpm_table.vddci_table,
3454 : SMU7_MAX_LEVELS_VDDCI);
3455 0 : ci_reset_single_dpm_table(rdev,
3456 0 : &pi->dpm_table.mvdd_table,
3457 : SMU7_MAX_LEVELS_MVDD);
3458 :
3459 0 : pi->dpm_table.sclk_table.count = 0;
3460 0 : for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3461 0 : if ((i == 0) ||
3462 0 : (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3463 0 : allowed_sclk_vddc_table->entries[i].clk)) {
3464 0 : pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3465 0 : allowed_sclk_vddc_table->entries[i].clk;
3466 0 : pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3467 0 : (i == 0) ? true : false;
3468 0 : pi->dpm_table.sclk_table.count++;
3469 0 : }
3470 : }
3471 :
3472 0 : pi->dpm_table.mclk_table.count = 0;
3473 0 : for (i = 0; i < allowed_mclk_table->count; i++) {
3474 0 : if ((i == 0) ||
3475 0 : (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3476 0 : allowed_mclk_table->entries[i].clk)) {
3477 0 : pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3478 0 : allowed_mclk_table->entries[i].clk;
3479 0 : pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3480 0 : (i == 0) ? true : false;
3481 0 : pi->dpm_table.mclk_table.count++;
3482 0 : }
3483 : }
3484 :
3485 0 : for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3486 0 : pi->dpm_table.vddc_table.dpm_levels[i].value =
3487 0 : allowed_sclk_vddc_table->entries[i].v;
3488 0 : pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3489 0 : std_voltage_table->entries[i].leakage;
3490 0 : pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3491 : }
3492 0 : pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3493 :
3494 0 : allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3495 0 : if (allowed_mclk_table) {
3496 0 : for (i = 0; i < allowed_mclk_table->count; i++) {
3497 0 : pi->dpm_table.vddci_table.dpm_levels[i].value =
3498 0 : allowed_mclk_table->entries[i].v;
3499 0 : pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3500 : }
3501 0 : pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3502 0 : }
3503 :
3504 0 : allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3505 0 : if (allowed_mclk_table) {
3506 0 : for (i = 0; i < allowed_mclk_table->count; i++) {
3507 0 : pi->dpm_table.mvdd_table.dpm_levels[i].value =
3508 0 : allowed_mclk_table->entries[i].v;
3509 0 : pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3510 : }
3511 0 : pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3512 0 : }
3513 :
3514 0 : ci_setup_default_pcie_tables(rdev);
3515 :
3516 0 : return 0;
3517 0 : }
3518 :
3519 0 : static int ci_find_boot_level(struct ci_single_dpm_table *table,
3520 : u32 value, u32 *boot_level)
3521 : {
3522 : u32 i;
3523 : int ret = -EINVAL;
3524 :
3525 0 : for(i = 0; i < table->count; i++) {
3526 0 : if (value == table->dpm_levels[i].value) {
3527 0 : *boot_level = i;
3528 : ret = 0;
3529 0 : }
3530 : }
3531 :
3532 0 : return ret;
3533 : }
3534 :
3535 0 : static int ci_init_smc_table(struct radeon_device *rdev)
3536 : {
3537 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3538 0 : struct ci_ulv_parm *ulv = &pi->ulv;
3539 0 : struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3540 0 : SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3541 : int ret;
3542 :
3543 0 : ret = ci_setup_default_dpm_tables(rdev);
3544 0 : if (ret)
3545 0 : return ret;
3546 :
3547 0 : if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3548 0 : ci_populate_smc_voltage_tables(rdev, table);
3549 :
3550 0 : ci_init_fps_limits(rdev);
3551 :
3552 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3553 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3554 :
3555 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3556 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3557 :
3558 0 : if (pi->mem_gddr5)
3559 0 : table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3560 :
3561 0 : if (ulv->supported) {
3562 0 : ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3563 0 : if (ret)
3564 0 : return ret;
3565 0 : WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3566 0 : }
3567 :
3568 0 : ret = ci_populate_all_graphic_levels(rdev);
3569 0 : if (ret)
3570 0 : return ret;
3571 :
3572 0 : ret = ci_populate_all_memory_levels(rdev);
3573 0 : if (ret)
3574 0 : return ret;
3575 :
3576 0 : ci_populate_smc_link_level(rdev, table);
3577 :
3578 0 : ret = ci_populate_smc_acpi_level(rdev, table);
3579 0 : if (ret)
3580 0 : return ret;
3581 :
3582 0 : ret = ci_populate_smc_vce_level(rdev, table);
3583 0 : if (ret)
3584 0 : return ret;
3585 :
3586 0 : ret = ci_populate_smc_acp_level(rdev, table);
3587 0 : if (ret)
3588 0 : return ret;
3589 :
3590 0 : ret = ci_populate_smc_samu_level(rdev, table);
3591 0 : if (ret)
3592 0 : return ret;
3593 :
3594 0 : ret = ci_do_program_memory_timing_parameters(rdev);
3595 0 : if (ret)
3596 0 : return ret;
3597 :
3598 0 : ret = ci_populate_smc_uvd_level(rdev, table);
3599 0 : if (ret)
3600 0 : return ret;
3601 :
3602 0 : table->UvdBootLevel = 0;
3603 0 : table->VceBootLevel = 0;
3604 0 : table->AcpBootLevel = 0;
3605 0 : table->SamuBootLevel = 0;
3606 0 : table->GraphicsBootLevel = 0;
3607 0 : table->MemoryBootLevel = 0;
3608 :
3609 0 : ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3610 0 : pi->vbios_boot_state.sclk_bootup_value,
3611 0 : (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3612 :
3613 0 : ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3614 0 : pi->vbios_boot_state.mclk_bootup_value,
3615 0 : (u32 *)&pi->smc_state_table.MemoryBootLevel);
3616 :
3617 0 : table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3618 0 : table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3619 0 : table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3620 :
3621 0 : ci_populate_smc_initial_state(rdev, radeon_boot_state);
3622 :
3623 0 : ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3624 0 : if (ret)
3625 0 : return ret;
3626 :
3627 0 : table->UVDInterval = 1;
3628 0 : table->VCEInterval = 1;
3629 0 : table->ACPInterval = 1;
3630 0 : table->SAMUInterval = 1;
3631 0 : table->GraphicsVoltageChangeEnable = 1;
3632 0 : table->GraphicsThermThrottleEnable = 1;
3633 0 : table->GraphicsInterval = 1;
3634 0 : table->VoltageInterval = 1;
3635 0 : table->ThermalInterval = 1;
3636 0 : table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3637 0 : CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3638 0 : table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3639 0 : CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3640 0 : table->MemoryVoltageChangeEnable = 1;
3641 0 : table->MemoryInterval = 1;
3642 0 : table->VoltageResponseTime = 0;
3643 0 : table->VddcVddciDelta = 4000;
3644 0 : table->PhaseResponseTime = 0;
3645 0 : table->MemoryThermThrottleEnable = 1;
3646 0 : table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3647 0 : table->PCIeGenInterval = 1;
3648 0 : if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3649 0 : table->SVI2Enable = 1;
3650 : else
3651 0 : table->SVI2Enable = 0;
3652 :
3653 0 : table->ThermGpio = 17;
3654 0 : table->SclkStepSize = 0x4000;
3655 :
3656 0 : table->SystemFlags = cpu_to_be32(table->SystemFlags);
3657 0 : table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3658 0 : table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3659 0 : table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3660 0 : table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3661 0 : table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3662 0 : table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3663 0 : table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3664 0 : table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3665 0 : table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3666 0 : table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3667 0 : table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3668 0 : table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3669 0 : table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3670 :
3671 0 : ret = ci_copy_bytes_to_smc(rdev,
3672 0 : pi->dpm_table_start +
3673 : offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3674 0 : (u8 *)&table->SystemFlags,
3675 : sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3676 0 : pi->sram_end);
3677 0 : if (ret)
3678 0 : return ret;
3679 :
3680 0 : return 0;
3681 0 : }
3682 :
3683 0 : static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3684 : struct ci_single_dpm_table *dpm_table,
3685 : u32 low_limit, u32 high_limit)
3686 : {
3687 : u32 i;
3688 :
3689 0 : for (i = 0; i < dpm_table->count; i++) {
3690 0 : if ((dpm_table->dpm_levels[i].value < low_limit) ||
3691 0 : (dpm_table->dpm_levels[i].value > high_limit))
3692 0 : dpm_table->dpm_levels[i].enabled = false;
3693 : else
3694 0 : dpm_table->dpm_levels[i].enabled = true;
3695 : }
3696 0 : }
3697 :
3698 0 : static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3699 : u32 speed_low, u32 lanes_low,
3700 : u32 speed_high, u32 lanes_high)
3701 : {
3702 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3703 0 : struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3704 : u32 i, j;
3705 :
3706 0 : for (i = 0; i < pcie_table->count; i++) {
3707 0 : if ((pcie_table->dpm_levels[i].value < speed_low) ||
3708 0 : (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3709 0 : (pcie_table->dpm_levels[i].value > speed_high) ||
3710 0 : (pcie_table->dpm_levels[i].param1 > lanes_high))
3711 0 : pcie_table->dpm_levels[i].enabled = false;
3712 : else
3713 0 : pcie_table->dpm_levels[i].enabled = true;
3714 : }
3715 :
3716 0 : for (i = 0; i < pcie_table->count; i++) {
3717 0 : if (pcie_table->dpm_levels[i].enabled) {
3718 0 : for (j = i + 1; j < pcie_table->count; j++) {
3719 0 : if (pcie_table->dpm_levels[j].enabled) {
3720 0 : if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3721 0 : (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3722 0 : pcie_table->dpm_levels[j].enabled = false;
3723 : }
3724 : }
3725 : }
3726 : }
3727 0 : }
3728 :
3729 0 : static int ci_trim_dpm_states(struct radeon_device *rdev,
3730 : struct radeon_ps *radeon_state)
3731 : {
3732 0 : struct ci_ps *state = ci_get_ps(radeon_state);
3733 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3734 : u32 high_limit_count;
3735 :
3736 0 : if (state->performance_level_count < 1)
3737 0 : return -EINVAL;
3738 :
3739 0 : if (state->performance_level_count == 1)
3740 0 : high_limit_count = 0;
3741 : else
3742 : high_limit_count = 1;
3743 :
3744 0 : ci_trim_single_dpm_states(rdev,
3745 0 : &pi->dpm_table.sclk_table,
3746 0 : state->performance_levels[0].sclk,
3747 0 : state->performance_levels[high_limit_count].sclk);
3748 :
3749 0 : ci_trim_single_dpm_states(rdev,
3750 0 : &pi->dpm_table.mclk_table,
3751 0 : state->performance_levels[0].mclk,
3752 0 : state->performance_levels[high_limit_count].mclk);
3753 :
3754 0 : ci_trim_pcie_dpm_states(rdev,
3755 0 : state->performance_levels[0].pcie_gen,
3756 0 : state->performance_levels[0].pcie_lane,
3757 0 : state->performance_levels[high_limit_count].pcie_gen,
3758 0 : state->performance_levels[high_limit_count].pcie_lane);
3759 :
3760 0 : return 0;
3761 0 : }
3762 :
3763 0 : static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3764 : {
3765 : struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3766 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3767 : struct radeon_clock_voltage_dependency_table *vddc_table =
3768 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3769 : u32 requested_voltage = 0;
3770 : u32 i;
3771 :
3772 0 : if (disp_voltage_table == NULL)
3773 0 : return -EINVAL;
3774 0 : if (!disp_voltage_table->count)
3775 0 : return -EINVAL;
3776 :
3777 0 : for (i = 0; i < disp_voltage_table->count; i++) {
3778 0 : if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3779 0 : requested_voltage = disp_voltage_table->entries[i].v;
3780 : }
3781 :
3782 0 : for (i = 0; i < vddc_table->count; i++) {
3783 0 : if (requested_voltage <= vddc_table->entries[i].v) {
3784 : requested_voltage = vddc_table->entries[i].v;
3785 0 : return (ci_send_msg_to_smc_with_parameter(rdev,
3786 : PPSMC_MSG_VddC_Request,
3787 0 : requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3788 : 0 : -EINVAL;
3789 : }
3790 : }
3791 :
3792 0 : return -EINVAL;
3793 0 : }
3794 :
3795 0 : static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3796 : {
3797 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3798 : PPSMC_Result result;
3799 :
3800 0 : ci_apply_disp_minimum_voltage_request(rdev);
3801 :
3802 0 : if (!pi->sclk_dpm_key_disabled) {
3803 0 : if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3804 0 : result = ci_send_msg_to_smc_with_parameter(rdev,
3805 : PPSMC_MSG_SCLKDPM_SetEnabledMask,
3806 : pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3807 0 : if (result != PPSMC_Result_OK)
3808 0 : return -EINVAL;
3809 : }
3810 : }
3811 :
3812 0 : if (!pi->mclk_dpm_key_disabled) {
3813 0 : if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3814 0 : result = ci_send_msg_to_smc_with_parameter(rdev,
3815 : PPSMC_MSG_MCLKDPM_SetEnabledMask,
3816 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3817 0 : if (result != PPSMC_Result_OK)
3818 0 : return -EINVAL;
3819 : }
3820 : }
3821 : #if 0
3822 : if (!pi->pcie_dpm_key_disabled) {
3823 : if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3824 : result = ci_send_msg_to_smc_with_parameter(rdev,
3825 : PPSMC_MSG_PCIeDPM_SetEnabledMask,
3826 : pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3827 : if (result != PPSMC_Result_OK)
3828 : return -EINVAL;
3829 : }
3830 : }
3831 : #endif
3832 0 : return 0;
3833 0 : }
3834 :
3835 0 : static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3836 : struct radeon_ps *radeon_state)
3837 : {
3838 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3839 0 : struct ci_ps *state = ci_get_ps(radeon_state);
3840 0 : struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3841 0 : u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3842 0 : struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3843 0 : u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3844 : u32 i;
3845 :
3846 0 : pi->need_update_smu7_dpm_table = 0;
3847 :
3848 0 : for (i = 0; i < sclk_table->count; i++) {
3849 0 : if (sclk == sclk_table->dpm_levels[i].value)
3850 : break;
3851 : }
3852 :
3853 0 : if (i >= sclk_table->count) {
3854 0 : pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3855 0 : } else {
3856 : /* XXX check display min clock requirements */
3857 : if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3858 : pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3859 : }
3860 :
3861 0 : for (i = 0; i < mclk_table->count; i++) {
3862 0 : if (mclk == mclk_table->dpm_levels[i].value)
3863 : break;
3864 : }
3865 :
3866 0 : if (i >= mclk_table->count)
3867 0 : pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3868 :
3869 0 : if (rdev->pm.dpm.current_active_crtc_count !=
3870 0 : rdev->pm.dpm.new_active_crtc_count)
3871 0 : pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3872 0 : }
3873 :
3874 0 : static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3875 : struct radeon_ps *radeon_state)
3876 : {
3877 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3878 0 : struct ci_ps *state = ci_get_ps(radeon_state);
3879 0 : u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3880 0 : u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3881 0 : struct ci_dpm_table *dpm_table = &pi->dpm_table;
3882 : int ret;
3883 :
3884 0 : if (!pi->need_update_smu7_dpm_table)
3885 0 : return 0;
3886 :
3887 0 : if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3888 0 : dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3889 :
3890 0 : if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3891 0 : dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3892 :
3893 0 : if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3894 0 : ret = ci_populate_all_graphic_levels(rdev);
3895 0 : if (ret)
3896 0 : return ret;
3897 : }
3898 :
3899 0 : if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3900 0 : ret = ci_populate_all_memory_levels(rdev);
3901 0 : if (ret)
3902 0 : return ret;
3903 : }
3904 :
3905 0 : return 0;
3906 0 : }
3907 :
3908 0 : static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3909 : {
3910 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3911 : const struct radeon_clock_and_voltage_limits *max_limits;
3912 : int i;
3913 :
3914 0 : if (rdev->pm.dpm.ac_power)
3915 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3916 : else
3917 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3918 :
3919 0 : if (enable) {
3920 0 : pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3921 :
3922 0 : for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3923 0 : if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3924 0 : pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3925 :
3926 0 : if (!pi->caps_uvd_dpm)
3927 : break;
3928 : }
3929 : }
3930 :
3931 0 : ci_send_msg_to_smc_with_parameter(rdev,
3932 : PPSMC_MSG_UVDDPM_SetEnabledMask,
3933 0 : pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3934 :
3935 0 : if (pi->last_mclk_dpm_enable_mask & 0x1) {
3936 0 : pi->uvd_enabled = true;
3937 0 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3938 0 : ci_send_msg_to_smc_with_parameter(rdev,
3939 : PPSMC_MSG_MCLKDPM_SetEnabledMask,
3940 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3941 0 : }
3942 : } else {
3943 0 : if (pi->last_mclk_dpm_enable_mask & 0x1) {
3944 0 : pi->uvd_enabled = false;
3945 0 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3946 0 : ci_send_msg_to_smc_with_parameter(rdev,
3947 : PPSMC_MSG_MCLKDPM_SetEnabledMask,
3948 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3949 0 : }
3950 : }
3951 :
3952 0 : return (ci_send_msg_to_smc(rdev, enable ?
3953 0 : PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3954 : 0 : -EINVAL;
3955 : }
3956 :
3957 0 : static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3958 : {
3959 0 : struct ci_power_info *pi = ci_get_pi(rdev);
3960 : const struct radeon_clock_and_voltage_limits *max_limits;
3961 : int i;
3962 :
3963 0 : if (rdev->pm.dpm.ac_power)
3964 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3965 : else
3966 0 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3967 :
3968 0 : if (enable) {
3969 0 : pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3970 0 : for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3971 0 : if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3972 0 : pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3973 :
3974 0 : if (!pi->caps_vce_dpm)
3975 : break;
3976 : }
3977 : }
3978 :
3979 0 : ci_send_msg_to_smc_with_parameter(rdev,
3980 : PPSMC_MSG_VCEDPM_SetEnabledMask,
3981 0 : pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3982 0 : }
3983 :
3984 0 : return (ci_send_msg_to_smc(rdev, enable ?
3985 0 : PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3986 : 0 : -EINVAL;
3987 : }
3988 :
3989 : #if 0
3990 : static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3991 : {
3992 : struct ci_power_info *pi = ci_get_pi(rdev);
3993 : const struct radeon_clock_and_voltage_limits *max_limits;
3994 : int i;
3995 :
3996 : if (rdev->pm.dpm.ac_power)
3997 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3998 : else
3999 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4000 :
4001 : if (enable) {
4002 : pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4003 : for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4004 : if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4005 : pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4006 :
4007 : if (!pi->caps_samu_dpm)
4008 : break;
4009 : }
4010 : }
4011 :
4012 : ci_send_msg_to_smc_with_parameter(rdev,
4013 : PPSMC_MSG_SAMUDPM_SetEnabledMask,
4014 : pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4015 : }
4016 : return (ci_send_msg_to_smc(rdev, enable ?
4017 : PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
4018 : 0 : -EINVAL;
4019 : }
4020 :
4021 : static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4022 : {
4023 : struct ci_power_info *pi = ci_get_pi(rdev);
4024 : const struct radeon_clock_and_voltage_limits *max_limits;
4025 : int i;
4026 :
4027 : if (rdev->pm.dpm.ac_power)
4028 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4029 : else
4030 : max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4031 :
4032 : if (enable) {
4033 : pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4034 : for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4035 : if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4036 : pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4037 :
4038 : if (!pi->caps_acp_dpm)
4039 : break;
4040 : }
4041 : }
4042 :
4043 : ci_send_msg_to_smc_with_parameter(rdev,
4044 : PPSMC_MSG_ACPDPM_SetEnabledMask,
4045 : pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4046 : }
4047 :
4048 : return (ci_send_msg_to_smc(rdev, enable ?
4049 : PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4050 : 0 : -EINVAL;
4051 : }
4052 : #endif
4053 :
4054 0 : static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4055 : {
4056 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4057 : u32 tmp;
4058 :
4059 0 : if (!gate) {
4060 0 : if (pi->caps_uvd_dpm ||
4061 0 : (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4062 0 : pi->smc_state_table.UvdBootLevel = 0;
4063 : else
4064 0 : pi->smc_state_table.UvdBootLevel =
4065 0 : rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4066 :
4067 0 : tmp = RREG32_SMC(DPM_TABLE_475);
4068 0 : tmp &= ~UvdBootLevel_MASK;
4069 0 : tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
4070 0 : WREG32_SMC(DPM_TABLE_475, tmp);
4071 0 : }
4072 :
4073 0 : return ci_enable_uvd_dpm(rdev, !gate);
4074 : }
4075 :
4076 0 : static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4077 : {
4078 : u8 i;
4079 : u32 min_evclk = 30000; /* ??? */
4080 : struct radeon_vce_clock_voltage_dependency_table *table =
4081 0 : &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4082 :
4083 0 : for (i = 0; i < table->count; i++) {
4084 0 : if (table->entries[i].evclk >= min_evclk)
4085 0 : return i;
4086 : }
4087 :
4088 0 : return table->count - 1;
4089 0 : }
4090 :
4091 0 : static int ci_update_vce_dpm(struct radeon_device *rdev,
4092 : struct radeon_ps *radeon_new_state,
4093 : struct radeon_ps *radeon_current_state)
4094 : {
4095 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4096 : int ret = 0;
4097 : u32 tmp;
4098 :
4099 0 : if (radeon_current_state->evclk != radeon_new_state->evclk) {
4100 0 : if (radeon_new_state->evclk) {
4101 : /* turn the clocks on when encoding */
4102 0 : cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4103 :
4104 0 : pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4105 0 : tmp = RREG32_SMC(DPM_TABLE_475);
4106 0 : tmp &= ~VceBootLevel_MASK;
4107 0 : tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
4108 0 : WREG32_SMC(DPM_TABLE_475, tmp);
4109 :
4110 0 : ret = ci_enable_vce_dpm(rdev, true);
4111 0 : } else {
4112 : /* turn the clocks off when not encoding */
4113 0 : cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4114 :
4115 0 : ret = ci_enable_vce_dpm(rdev, false);
4116 : }
4117 : }
4118 0 : return ret;
4119 : }
4120 :
4121 : #if 0
4122 : static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4123 : {
4124 : return ci_enable_samu_dpm(rdev, gate);
4125 : }
4126 :
4127 : static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4128 : {
4129 : struct ci_power_info *pi = ci_get_pi(rdev);
4130 : u32 tmp;
4131 :
4132 : if (!gate) {
4133 : pi->smc_state_table.AcpBootLevel = 0;
4134 :
4135 : tmp = RREG32_SMC(DPM_TABLE_475);
4136 : tmp &= ~AcpBootLevel_MASK;
4137 : tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4138 : WREG32_SMC(DPM_TABLE_475, tmp);
4139 : }
4140 :
4141 : return ci_enable_acp_dpm(rdev, !gate);
4142 : }
4143 : #endif
4144 :
4145 0 : static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4146 : struct radeon_ps *radeon_state)
4147 : {
4148 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4149 : int ret;
4150 :
4151 0 : ret = ci_trim_dpm_states(rdev, radeon_state);
4152 0 : if (ret)
4153 0 : return ret;
4154 :
4155 0 : pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4156 0 : ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4157 0 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4158 0 : ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4159 0 : pi->last_mclk_dpm_enable_mask =
4160 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4161 0 : if (pi->uvd_enabled) {
4162 0 : if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4163 0 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4164 : }
4165 0 : pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4166 0 : ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4167 :
4168 0 : return 0;
4169 0 : }
4170 :
4171 0 : static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4172 : u32 level_mask)
4173 : {
4174 : u32 level = 0;
4175 :
4176 0 : while ((level_mask & (1 << level)) == 0)
4177 0 : level++;
4178 :
4179 0 : return level;
4180 : }
4181 :
4182 :
4183 0 : int ci_dpm_force_performance_level(struct radeon_device *rdev,
4184 : enum radeon_dpm_forced_level level)
4185 : {
4186 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4187 : u32 tmp, levels, i;
4188 : int ret;
4189 :
4190 0 : if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
4191 0 : if ((!pi->pcie_dpm_key_disabled) &&
4192 0 : pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4193 : levels = 0;
4194 : tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4195 0 : while (tmp >>= 1)
4196 0 : levels++;
4197 0 : if (levels) {
4198 0 : ret = ci_dpm_force_state_pcie(rdev, level);
4199 0 : if (ret)
4200 0 : return ret;
4201 0 : for (i = 0; i < rdev->usec_timeout; i++) {
4202 0 : tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4203 0 : CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4204 0 : if (tmp == levels)
4205 : break;
4206 0 : udelay(1);
4207 : }
4208 : }
4209 : }
4210 0 : if ((!pi->sclk_dpm_key_disabled) &&
4211 0 : pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4212 : levels = 0;
4213 : tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4214 0 : while (tmp >>= 1)
4215 0 : levels++;
4216 0 : if (levels) {
4217 0 : ret = ci_dpm_force_state_sclk(rdev, levels);
4218 0 : if (ret)
4219 0 : return ret;
4220 0 : for (i = 0; i < rdev->usec_timeout; i++) {
4221 0 : tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4222 0 : CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4223 0 : if (tmp == levels)
4224 : break;
4225 0 : udelay(1);
4226 : }
4227 : }
4228 : }
4229 0 : if ((!pi->mclk_dpm_key_disabled) &&
4230 0 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4231 : levels = 0;
4232 : tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4233 0 : while (tmp >>= 1)
4234 0 : levels++;
4235 0 : if (levels) {
4236 0 : ret = ci_dpm_force_state_mclk(rdev, levels);
4237 0 : if (ret)
4238 0 : return ret;
4239 0 : for (i = 0; i < rdev->usec_timeout; i++) {
4240 0 : tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4241 0 : CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4242 0 : if (tmp == levels)
4243 : break;
4244 0 : udelay(1);
4245 : }
4246 : }
4247 : }
4248 0 : } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
4249 0 : if ((!pi->sclk_dpm_key_disabled) &&
4250 0 : pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4251 0 : levels = ci_get_lowest_enabled_level(rdev,
4252 : pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4253 0 : ret = ci_dpm_force_state_sclk(rdev, levels);
4254 0 : if (ret)
4255 0 : return ret;
4256 0 : for (i = 0; i < rdev->usec_timeout; i++) {
4257 0 : tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4258 0 : CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4259 0 : if (tmp == levels)
4260 : break;
4261 0 : udelay(1);
4262 : }
4263 : }
4264 0 : if ((!pi->mclk_dpm_key_disabled) &&
4265 0 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4266 0 : levels = ci_get_lowest_enabled_level(rdev,
4267 : pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4268 0 : ret = ci_dpm_force_state_mclk(rdev, levels);
4269 0 : if (ret)
4270 0 : return ret;
4271 0 : for (i = 0; i < rdev->usec_timeout; i++) {
4272 0 : tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4273 0 : CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4274 0 : if (tmp == levels)
4275 : break;
4276 0 : udelay(1);
4277 : }
4278 : }
4279 0 : if ((!pi->pcie_dpm_key_disabled) &&
4280 0 : pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4281 0 : levels = ci_get_lowest_enabled_level(rdev,
4282 : pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4283 0 : ret = ci_dpm_force_state_pcie(rdev, levels);
4284 0 : if (ret)
4285 0 : return ret;
4286 0 : for (i = 0; i < rdev->usec_timeout; i++) {
4287 0 : tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4288 0 : CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4289 0 : if (tmp == levels)
4290 : break;
4291 0 : udelay(1);
4292 : }
4293 : }
4294 0 : } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
4295 0 : if (!pi->pcie_dpm_key_disabled) {
4296 : PPSMC_Result smc_result;
4297 :
4298 0 : smc_result = ci_send_msg_to_smc(rdev,
4299 : PPSMC_MSG_PCIeDPM_UnForceLevel);
4300 0 : if (smc_result != PPSMC_Result_OK)
4301 0 : return -EINVAL;
4302 0 : }
4303 0 : ret = ci_upload_dpm_level_enable_mask(rdev);
4304 0 : if (ret)
4305 0 : return ret;
4306 : }
4307 :
4308 0 : rdev->pm.dpm.forced_level = level;
4309 :
4310 0 : return 0;
4311 0 : }
4312 :
4313 0 : static int ci_set_mc_special_registers(struct radeon_device *rdev,
4314 : struct ci_mc_reg_table *table)
4315 : {
4316 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4317 : u8 i, j, k;
4318 : u32 temp_reg;
4319 :
4320 0 : for (i = 0, j = table->last; i < table->last; i++) {
4321 0 : if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4322 0 : return -EINVAL;
4323 0 : switch(table->mc_reg_address[i].s1 << 2) {
4324 : case MC_SEQ_MISC1:
4325 0 : temp_reg = RREG32(MC_PMG_CMD_EMRS);
4326 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4327 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4328 0 : for (k = 0; k < table->num_entries; k++) {
4329 0 : table->mc_reg_table_entry[k].mc_data[j] =
4330 0 : ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4331 : }
4332 0 : j++;
4333 0 : if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4334 0 : return -EINVAL;
4335 :
4336 0 : temp_reg = RREG32(MC_PMG_CMD_MRS);
4337 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4338 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4339 0 : for (k = 0; k < table->num_entries; k++) {
4340 0 : table->mc_reg_table_entry[k].mc_data[j] =
4341 0 : (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4342 0 : if (!pi->mem_gddr5)
4343 0 : table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4344 : }
4345 0 : j++;
4346 0 : if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4347 0 : return -EINVAL;
4348 :
4349 0 : if (!pi->mem_gddr5) {
4350 0 : table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4351 0 : table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4352 0 : for (k = 0; k < table->num_entries; k++) {
4353 0 : table->mc_reg_table_entry[k].mc_data[j] =
4354 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4355 : }
4356 0 : j++;
4357 0 : if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4358 0 : return -EINVAL;
4359 : }
4360 : break;
4361 : case MC_SEQ_RESERVE_M:
4362 0 : temp_reg = RREG32(MC_PMG_CMD_MRS1);
4363 0 : table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4364 0 : table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4365 0 : for (k = 0; k < table->num_entries; k++) {
4366 0 : table->mc_reg_table_entry[k].mc_data[j] =
4367 0 : (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4368 : }
4369 0 : j++;
4370 0 : if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4371 0 : return -EINVAL;
4372 : break;
4373 : default:
4374 : break;
4375 : }
4376 :
4377 : }
4378 :
4379 0 : table->last = j;
4380 :
4381 0 : return 0;
4382 0 : }
4383 :
4384 0 : static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4385 : {
4386 : bool result = true;
4387 :
4388 0 : switch(in_reg) {
4389 : case MC_SEQ_RAS_TIMING >> 2:
4390 0 : *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
4391 0 : break;
4392 : case MC_SEQ_DLL_STBY >> 2:
4393 0 : *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
4394 0 : break;
4395 : case MC_SEQ_G5PDX_CMD0 >> 2:
4396 0 : *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
4397 0 : break;
4398 : case MC_SEQ_G5PDX_CMD1 >> 2:
4399 0 : *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
4400 0 : break;
4401 : case MC_SEQ_G5PDX_CTRL >> 2:
4402 0 : *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
4403 0 : break;
4404 : case MC_SEQ_CAS_TIMING >> 2:
4405 0 : *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
4406 0 : break;
4407 : case MC_SEQ_MISC_TIMING >> 2:
4408 0 : *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4409 0 : break;
4410 : case MC_SEQ_MISC_TIMING2 >> 2:
4411 0 : *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4412 0 : break;
4413 : case MC_SEQ_PMG_DVS_CMD >> 2:
4414 0 : *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4415 0 : break;
4416 : case MC_SEQ_PMG_DVS_CTL >> 2:
4417 0 : *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4418 0 : break;
4419 : case MC_SEQ_RD_CTL_D0 >> 2:
4420 0 : *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4421 0 : break;
4422 : case MC_SEQ_RD_CTL_D1 >> 2:
4423 0 : *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4424 0 : break;
4425 : case MC_SEQ_WR_CTL_D0 >> 2:
4426 0 : *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4427 0 : break;
4428 : case MC_SEQ_WR_CTL_D1 >> 2:
4429 0 : *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4430 0 : break;
4431 : case MC_PMG_CMD_EMRS >> 2:
4432 0 : *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4433 0 : break;
4434 : case MC_PMG_CMD_MRS >> 2:
4435 0 : *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4436 0 : break;
4437 : case MC_PMG_CMD_MRS1 >> 2:
4438 0 : *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4439 0 : break;
4440 : case MC_SEQ_PMG_TIMING >> 2:
4441 0 : *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4442 0 : break;
4443 : case MC_PMG_CMD_MRS2 >> 2:
4444 0 : *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4445 0 : break;
4446 : case MC_SEQ_WR_CTL_2 >> 2:
4447 0 : *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4448 0 : break;
4449 : default:
4450 : result = false;
4451 0 : break;
4452 : }
4453 :
4454 0 : return result;
4455 : }
4456 :
4457 0 : static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4458 : {
4459 : u8 i, j;
4460 :
4461 0 : for (i = 0; i < table->last; i++) {
4462 0 : for (j = 1; j < table->num_entries; j++) {
4463 0 : if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4464 0 : table->mc_reg_table_entry[j].mc_data[i]) {
4465 0 : table->valid_flag |= 1 << i;
4466 0 : break;
4467 : }
4468 : }
4469 : }
4470 0 : }
4471 :
4472 0 : static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4473 : {
4474 : u32 i;
4475 0 : u16 address;
4476 :
4477 0 : for (i = 0; i < table->last; i++) {
4478 0 : table->mc_reg_address[i].s0 =
4479 0 : ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4480 0 : address : table->mc_reg_address[i].s1;
4481 : }
4482 0 : }
4483 :
4484 0 : static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4485 : struct ci_mc_reg_table *ci_table)
4486 : {
4487 : u8 i, j;
4488 :
4489 0 : if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4490 0 : return -EINVAL;
4491 0 : if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4492 0 : return -EINVAL;
4493 :
4494 0 : for (i = 0; i < table->last; i++)
4495 0 : ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4496 :
4497 0 : ci_table->last = table->last;
4498 :
4499 0 : for (i = 0; i < table->num_entries; i++) {
4500 0 : ci_table->mc_reg_table_entry[i].mclk_max =
4501 0 : table->mc_reg_table_entry[i].mclk_max;
4502 0 : for (j = 0; j < table->last; j++)
4503 0 : ci_table->mc_reg_table_entry[i].mc_data[j] =
4504 0 : table->mc_reg_table_entry[i].mc_data[j];
4505 : }
4506 0 : ci_table->num_entries = table->num_entries;
4507 :
4508 0 : return 0;
4509 0 : }
4510 :
4511 0 : static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4512 : struct ci_mc_reg_table *table)
4513 : {
4514 : u8 i, k;
4515 : u32 tmp;
4516 : bool patch;
4517 :
4518 0 : tmp = RREG32(MC_SEQ_MISC0);
4519 0 : patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4520 :
4521 0 : if (patch &&
4522 0 : ((rdev->pdev->device == 0x67B0) ||
4523 0 : (rdev->pdev->device == 0x67B1))) {
4524 0 : for (i = 0; i < table->last; i++) {
4525 0 : if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4526 0 : return -EINVAL;
4527 0 : switch(table->mc_reg_address[i].s1 >> 2) {
4528 : case MC_SEQ_MISC1:
4529 0 : for (k = 0; k < table->num_entries; k++) {
4530 0 : if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4531 0 : (table->mc_reg_table_entry[k].mclk_max == 137500))
4532 0 : table->mc_reg_table_entry[k].mc_data[i] =
4533 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4534 : 0x00000007;
4535 : }
4536 : break;
4537 : case MC_SEQ_WR_CTL_D0:
4538 0 : for (k = 0; k < table->num_entries; k++) {
4539 0 : if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4540 0 : (table->mc_reg_table_entry[k].mclk_max == 137500))
4541 0 : table->mc_reg_table_entry[k].mc_data[i] =
4542 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4543 : 0x0000D0DD;
4544 : }
4545 : break;
4546 : case MC_SEQ_WR_CTL_D1:
4547 0 : for (k = 0; k < table->num_entries; k++) {
4548 0 : if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4549 0 : (table->mc_reg_table_entry[k].mclk_max == 137500))
4550 0 : table->mc_reg_table_entry[k].mc_data[i] =
4551 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4552 : 0x0000D0DD;
4553 : }
4554 : break;
4555 : case MC_SEQ_WR_CTL_2:
4556 0 : for (k = 0; k < table->num_entries; k++) {
4557 0 : if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4558 0 : (table->mc_reg_table_entry[k].mclk_max == 137500))
4559 0 : table->mc_reg_table_entry[k].mc_data[i] = 0;
4560 : }
4561 : break;
4562 : case MC_SEQ_CAS_TIMING:
4563 0 : for (k = 0; k < table->num_entries; k++) {
4564 0 : if (table->mc_reg_table_entry[k].mclk_max == 125000)
4565 0 : table->mc_reg_table_entry[k].mc_data[i] =
4566 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4567 : 0x000C0140;
4568 0 : else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4569 0 : table->mc_reg_table_entry[k].mc_data[i] =
4570 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4571 : 0x000C0150;
4572 : }
4573 : break;
4574 : case MC_SEQ_MISC_TIMING:
4575 0 : for (k = 0; k < table->num_entries; k++) {
4576 0 : if (table->mc_reg_table_entry[k].mclk_max == 125000)
4577 0 : table->mc_reg_table_entry[k].mc_data[i] =
4578 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4579 : 0x00000030;
4580 0 : else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4581 0 : table->mc_reg_table_entry[k].mc_data[i] =
4582 0 : (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4583 : 0x00000035;
4584 : }
4585 : break;
4586 : default:
4587 : break;
4588 : }
4589 : }
4590 :
4591 0 : WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4592 0 : tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4593 0 : tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4594 0 : WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4595 0 : WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4596 0 : }
4597 :
4598 0 : return 0;
4599 0 : }
4600 :
4601 0 : static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4602 : {
4603 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4604 : struct atom_mc_reg_table *table;
4605 0 : struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4606 0 : u8 module_index = rv770_get_memory_module_index(rdev);
4607 : int ret;
4608 :
4609 0 : table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4610 0 : if (!table)
4611 0 : return -ENOMEM;
4612 :
4613 0 : WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4614 0 : WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4615 0 : WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4616 0 : WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4617 0 : WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4618 0 : WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4619 0 : WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4620 0 : WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4621 0 : WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4622 0 : WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4623 0 : WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4624 0 : WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4625 0 : WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4626 0 : WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4627 0 : WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4628 0 : WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4629 0 : WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4630 0 : WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4631 0 : WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4632 0 : WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4633 :
4634 0 : ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4635 0 : if (ret)
4636 : goto init_mc_done;
4637 :
4638 0 : ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4639 0 : if (ret)
4640 : goto init_mc_done;
4641 :
4642 0 : ci_set_s0_mc_reg_index(ci_table);
4643 :
4644 0 : ret = ci_register_patching_mc_seq(rdev, ci_table);
4645 0 : if (ret)
4646 : goto init_mc_done;
4647 :
4648 0 : ret = ci_set_mc_special_registers(rdev, ci_table);
4649 0 : if (ret)
4650 : goto init_mc_done;
4651 :
4652 0 : ci_set_valid_flag(ci_table);
4653 :
4654 : init_mc_done:
4655 0 : kfree(table);
4656 :
4657 0 : return ret;
4658 0 : }
4659 :
4660 0 : static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4661 : SMU7_Discrete_MCRegisters *mc_reg_table)
4662 : {
4663 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4664 : u32 i, j;
4665 :
4666 0 : for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4667 0 : if (pi->mc_reg_table.valid_flag & (1 << j)) {
4668 0 : if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4669 0 : return -EINVAL;
4670 0 : mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4671 0 : mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4672 0 : i++;
4673 0 : }
4674 : }
4675 :
4676 0 : mc_reg_table->last = (u8)i;
4677 :
4678 0 : return 0;
4679 0 : }
4680 :
4681 0 : static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4682 : SMU7_Discrete_MCRegisterSet *data,
4683 : u32 num_entries, u32 valid_flag)
4684 : {
4685 : u32 i, j;
4686 :
4687 0 : for (i = 0, j = 0; j < num_entries; j++) {
4688 0 : if (valid_flag & (1 << j)) {
4689 0 : data->value[i] = cpu_to_be32(entry->mc_data[j]);
4690 0 : i++;
4691 0 : }
4692 : }
4693 0 : }
4694 :
4695 0 : static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4696 : const u32 memory_clock,
4697 : SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4698 : {
4699 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4700 : u32 i = 0;
4701 :
4702 0 : for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4703 0 : if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4704 : break;
4705 : }
4706 :
4707 0 : if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4708 0 : --i;
4709 :
4710 0 : ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4711 0 : mc_reg_table_data, pi->mc_reg_table.last,
4712 0 : pi->mc_reg_table.valid_flag);
4713 0 : }
4714 :
4715 0 : static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4716 : SMU7_Discrete_MCRegisters *mc_reg_table)
4717 : {
4718 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4719 : u32 i;
4720 :
4721 0 : for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4722 0 : ci_convert_mc_reg_table_entry_to_smc(rdev,
4723 0 : pi->dpm_table.mclk_table.dpm_levels[i].value,
4724 0 : &mc_reg_table->data[i]);
4725 0 : }
4726 :
4727 0 : static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4728 : {
4729 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4730 : int ret;
4731 :
4732 0 : memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4733 :
4734 0 : ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4735 0 : if (ret)
4736 0 : return ret;
4737 0 : ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4738 :
4739 0 : return ci_copy_bytes_to_smc(rdev,
4740 0 : pi->mc_reg_table_start,
4741 : (u8 *)&pi->smc_mc_reg_table,
4742 : sizeof(SMU7_Discrete_MCRegisters),
4743 0 : pi->sram_end);
4744 0 : }
4745 :
4746 0 : static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4747 : {
4748 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4749 :
4750 0 : if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4751 0 : return 0;
4752 :
4753 0 : memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4754 :
4755 0 : ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4756 :
4757 0 : return ci_copy_bytes_to_smc(rdev,
4758 0 : pi->mc_reg_table_start +
4759 : offsetof(SMU7_Discrete_MCRegisters, data[0]),
4760 0 : (u8 *)&pi->smc_mc_reg_table.data[0],
4761 0 : sizeof(SMU7_Discrete_MCRegisterSet) *
4762 0 : pi->dpm_table.mclk_table.count,
4763 0 : pi->sram_end);
4764 0 : }
4765 :
4766 0 : static void ci_enable_voltage_control(struct radeon_device *rdev)
4767 : {
4768 0 : u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4769 :
4770 0 : tmp |= VOLT_PWRMGT_EN;
4771 0 : WREG32_SMC(GENERAL_PWRMGT, tmp);
4772 0 : }
4773 :
4774 0 : static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4775 : struct radeon_ps *radeon_state)
4776 : {
4777 0 : struct ci_ps *state = ci_get_ps(radeon_state);
4778 : int i;
4779 : u16 pcie_speed, max_speed = 0;
4780 :
4781 0 : for (i = 0; i < state->performance_level_count; i++) {
4782 0 : pcie_speed = state->performance_levels[i].pcie_gen;
4783 0 : if (max_speed < pcie_speed)
4784 0 : max_speed = pcie_speed;
4785 : }
4786 :
4787 0 : return max_speed;
4788 : }
4789 :
4790 0 : static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4791 : {
4792 : u32 speed_cntl = 0;
4793 :
4794 0 : speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4795 0 : speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4796 :
4797 0 : return (u16)speed_cntl;
4798 : }
4799 :
4800 0 : static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4801 : {
4802 : u32 link_width = 0;
4803 :
4804 0 : link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4805 0 : link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4806 :
4807 0 : switch (link_width) {
4808 : case RADEON_PCIE_LC_LINK_WIDTH_X1:
4809 0 : return 1;
4810 : case RADEON_PCIE_LC_LINK_WIDTH_X2:
4811 0 : return 2;
4812 : case RADEON_PCIE_LC_LINK_WIDTH_X4:
4813 0 : return 4;
4814 : case RADEON_PCIE_LC_LINK_WIDTH_X8:
4815 0 : return 8;
4816 : case RADEON_PCIE_LC_LINK_WIDTH_X12:
4817 : /* not actually supported */
4818 0 : return 12;
4819 : case RADEON_PCIE_LC_LINK_WIDTH_X0:
4820 : case RADEON_PCIE_LC_LINK_WIDTH_X16:
4821 : default:
4822 0 : return 16;
4823 : }
4824 0 : }
4825 :
4826 0 : static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4827 : struct radeon_ps *radeon_new_state,
4828 : struct radeon_ps *radeon_current_state)
4829 : {
4830 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4831 : enum radeon_pcie_gen target_link_speed =
4832 0 : ci_get_maximum_link_speed(rdev, radeon_new_state);
4833 : enum radeon_pcie_gen current_link_speed;
4834 :
4835 0 : if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4836 0 : current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4837 : else
4838 : current_link_speed = pi->force_pcie_gen;
4839 :
4840 0 : pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4841 0 : pi->pspp_notify_required = false;
4842 0 : if (target_link_speed > current_link_speed) {
4843 : switch (target_link_speed) {
4844 : #ifdef CONFIG_ACPI
4845 : case RADEON_PCIE_GEN3:
4846 : if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4847 : break;
4848 : pi->force_pcie_gen = RADEON_PCIE_GEN2;
4849 : if (current_link_speed == RADEON_PCIE_GEN2)
4850 : break;
4851 : case RADEON_PCIE_GEN2:
4852 : if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4853 : break;
4854 : #endif
4855 : default:
4856 0 : pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4857 : break;
4858 : }
4859 0 : } else {
4860 0 : if (target_link_speed < current_link_speed)
4861 0 : pi->pspp_notify_required = true;
4862 : }
4863 0 : }
4864 :
4865 0 : static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4866 : struct radeon_ps *radeon_new_state,
4867 : struct radeon_ps *radeon_current_state)
4868 : {
4869 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4870 : enum radeon_pcie_gen target_link_speed =
4871 0 : ci_get_maximum_link_speed(rdev, radeon_new_state);
4872 : u8 request;
4873 :
4874 0 : if (pi->pspp_notify_required) {
4875 0 : if (target_link_speed == RADEON_PCIE_GEN3)
4876 0 : request = PCIE_PERF_REQ_PECI_GEN3;
4877 0 : else if (target_link_speed == RADEON_PCIE_GEN2)
4878 0 : request = PCIE_PERF_REQ_PECI_GEN2;
4879 : else
4880 : request = PCIE_PERF_REQ_PECI_GEN1;
4881 :
4882 0 : if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4883 0 : (ci_get_current_pcie_speed(rdev) > 0))
4884 0 : return;
4885 :
4886 : #ifdef CONFIG_ACPI
4887 : radeon_acpi_pcie_performance_request(rdev, request, false);
4888 : #endif
4889 : }
4890 0 : }
4891 :
4892 0 : static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4893 : {
4894 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4895 : struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4896 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4897 : struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4898 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4899 : struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4900 0 : &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4901 :
4902 0 : if (allowed_sclk_vddc_table == NULL)
4903 0 : return -EINVAL;
4904 0 : if (allowed_sclk_vddc_table->count < 1)
4905 0 : return -EINVAL;
4906 0 : if (allowed_mclk_vddc_table == NULL)
4907 0 : return -EINVAL;
4908 0 : if (allowed_mclk_vddc_table->count < 1)
4909 0 : return -EINVAL;
4910 0 : if (allowed_mclk_vddci_table == NULL)
4911 0 : return -EINVAL;
4912 0 : if (allowed_mclk_vddci_table->count < 1)
4913 0 : return -EINVAL;
4914 :
4915 0 : pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4916 0 : pi->max_vddc_in_pp_table =
4917 0 : allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4918 :
4919 0 : pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4920 0 : pi->max_vddci_in_pp_table =
4921 0 : allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4922 :
4923 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4924 0 : allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4925 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4926 0 : allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4927 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4928 0 : allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4929 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4930 0 : allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4931 :
4932 0 : return 0;
4933 0 : }
4934 :
4935 0 : static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4936 : {
4937 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4938 0 : struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4939 : u32 leakage_index;
4940 :
4941 0 : for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4942 0 : if (leakage_table->leakage_id[leakage_index] == *vddc) {
4943 0 : *vddc = leakage_table->actual_voltage[leakage_index];
4944 0 : break;
4945 : }
4946 : }
4947 0 : }
4948 :
4949 0 : static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4950 : {
4951 0 : struct ci_power_info *pi = ci_get_pi(rdev);
4952 0 : struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4953 : u32 leakage_index;
4954 :
4955 0 : for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4956 0 : if (leakage_table->leakage_id[leakage_index] == *vddci) {
4957 0 : *vddci = leakage_table->actual_voltage[leakage_index];
4958 0 : break;
4959 : }
4960 : }
4961 0 : }
4962 :
4963 0 : static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4964 : struct radeon_clock_voltage_dependency_table *table)
4965 : {
4966 : u32 i;
4967 :
4968 0 : if (table) {
4969 0 : for (i = 0; i < table->count; i++)
4970 0 : ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4971 : }
4972 0 : }
4973 :
4974 0 : static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4975 : struct radeon_clock_voltage_dependency_table *table)
4976 : {
4977 : u32 i;
4978 :
4979 0 : if (table) {
4980 0 : for (i = 0; i < table->count; i++)
4981 0 : ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4982 : }
4983 0 : }
4984 :
4985 0 : static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4986 : struct radeon_vce_clock_voltage_dependency_table *table)
4987 : {
4988 : u32 i;
4989 :
4990 0 : if (table) {
4991 0 : for (i = 0; i < table->count; i++)
4992 0 : ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4993 : }
4994 0 : }
4995 :
4996 0 : static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4997 : struct radeon_uvd_clock_voltage_dependency_table *table)
4998 : {
4999 : u32 i;
5000 :
5001 0 : if (table) {
5002 0 : for (i = 0; i < table->count; i++)
5003 0 : ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
5004 : }
5005 0 : }
5006 :
5007 0 : static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
5008 : struct radeon_phase_shedding_limits_table *table)
5009 : {
5010 : u32 i;
5011 :
5012 0 : if (table) {
5013 0 : for (i = 0; i < table->count; i++)
5014 0 : ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
5015 : }
5016 0 : }
5017 :
5018 0 : static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
5019 : struct radeon_clock_and_voltage_limits *table)
5020 : {
5021 0 : if (table) {
5022 0 : ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
5023 0 : ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
5024 0 : }
5025 0 : }
5026 :
5027 0 : static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
5028 : struct radeon_cac_leakage_table *table)
5029 : {
5030 : u32 i;
5031 :
5032 0 : if (table) {
5033 0 : for (i = 0; i < table->count; i++)
5034 0 : ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
5035 : }
5036 0 : }
5037 :
5038 0 : static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
5039 : {
5040 :
5041 0 : ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5042 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5043 0 : ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5044 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5045 0 : ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5046 0 : &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5047 0 : ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5048 0 : &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5049 0 : ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5050 0 : &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5051 0 : ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5052 0 : &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5053 0 : ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5054 0 : &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5055 0 : ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5056 0 : &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5057 0 : ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5058 0 : &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5059 0 : ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5060 0 : &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5061 0 : ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5062 0 : &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5063 0 : ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5064 0 : &rdev->pm.dpm.dyn_state.cac_leakage_table);
5065 :
5066 0 : }
5067 :
5068 0 : static void ci_get_memory_type(struct radeon_device *rdev)
5069 : {
5070 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5071 : u32 tmp;
5072 :
5073 0 : tmp = RREG32(MC_SEQ_MISC0);
5074 :
5075 0 : if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
5076 : MC_SEQ_MISC0_GDDR5_VALUE)
5077 0 : pi->mem_gddr5 = true;
5078 : else
5079 0 : pi->mem_gddr5 = false;
5080 :
5081 0 : }
5082 :
5083 0 : static void ci_update_current_ps(struct radeon_device *rdev,
5084 : struct radeon_ps *rps)
5085 : {
5086 0 : struct ci_ps *new_ps = ci_get_ps(rps);
5087 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5088 :
5089 0 : pi->current_rps = *rps;
5090 0 : pi->current_ps = *new_ps;
5091 0 : pi->current_rps.ps_priv = &pi->current_ps;
5092 0 : }
5093 :
5094 0 : static void ci_update_requested_ps(struct radeon_device *rdev,
5095 : struct radeon_ps *rps)
5096 : {
5097 0 : struct ci_ps *new_ps = ci_get_ps(rps);
5098 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5099 :
5100 0 : pi->requested_rps = *rps;
5101 0 : pi->requested_ps = *new_ps;
5102 0 : pi->requested_rps.ps_priv = &pi->requested_ps;
5103 0 : }
5104 :
5105 0 : int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5106 : {
5107 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5108 0 : struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5109 : struct radeon_ps *new_ps = &requested_ps;
5110 :
5111 0 : ci_update_requested_ps(rdev, new_ps);
5112 :
5113 0 : ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5114 :
5115 0 : return 0;
5116 0 : }
5117 :
5118 0 : void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5119 : {
5120 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5121 0 : struct radeon_ps *new_ps = &pi->requested_rps;
5122 :
5123 0 : ci_update_current_ps(rdev, new_ps);
5124 0 : }
5125 :
5126 :
5127 0 : void ci_dpm_setup_asic(struct radeon_device *rdev)
5128 : {
5129 : int r;
5130 :
5131 0 : r = ci_mc_load_microcode(rdev);
5132 0 : if (r)
5133 0 : DRM_ERROR("Failed to load MC firmware!\n");
5134 0 : ci_read_clock_registers(rdev);
5135 0 : ci_get_memory_type(rdev);
5136 0 : ci_enable_acpi_power_management(rdev);
5137 0 : ci_init_sclk_t(rdev);
5138 0 : }
5139 :
5140 0 : int ci_dpm_enable(struct radeon_device *rdev)
5141 : {
5142 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5143 0 : struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5144 : int ret;
5145 :
5146 0 : if (ci_is_smc_running(rdev))
5147 0 : return -EINVAL;
5148 0 : if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5149 0 : ci_enable_voltage_control(rdev);
5150 0 : ret = ci_construct_voltage_tables(rdev);
5151 0 : if (ret) {
5152 0 : DRM_ERROR("ci_construct_voltage_tables failed\n");
5153 0 : return ret;
5154 : }
5155 : }
5156 0 : if (pi->caps_dynamic_ac_timing) {
5157 0 : ret = ci_initialize_mc_reg_table(rdev);
5158 0 : if (ret)
5159 0 : pi->caps_dynamic_ac_timing = false;
5160 : }
5161 0 : if (pi->dynamic_ss)
5162 0 : ci_enable_spread_spectrum(rdev, true);
5163 0 : if (pi->thermal_protection)
5164 0 : ci_enable_thermal_protection(rdev, true);
5165 0 : ci_program_sstp(rdev);
5166 0 : ci_enable_display_gap(rdev);
5167 0 : ci_program_vc(rdev);
5168 0 : ret = ci_upload_firmware(rdev);
5169 0 : if (ret) {
5170 0 : DRM_ERROR("ci_upload_firmware failed\n");
5171 0 : return ret;
5172 : }
5173 0 : ret = ci_process_firmware_header(rdev);
5174 0 : if (ret) {
5175 0 : DRM_ERROR("ci_process_firmware_header failed\n");
5176 0 : return ret;
5177 : }
5178 0 : ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5179 0 : if (ret) {
5180 0 : DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5181 0 : return ret;
5182 : }
5183 0 : ret = ci_init_smc_table(rdev);
5184 0 : if (ret) {
5185 0 : DRM_ERROR("ci_init_smc_table failed\n");
5186 0 : return ret;
5187 : }
5188 0 : ret = ci_init_arb_table_index(rdev);
5189 0 : if (ret) {
5190 0 : DRM_ERROR("ci_init_arb_table_index failed\n");
5191 0 : return ret;
5192 : }
5193 0 : if (pi->caps_dynamic_ac_timing) {
5194 0 : ret = ci_populate_initial_mc_reg_table(rdev);
5195 0 : if (ret) {
5196 0 : DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5197 0 : return ret;
5198 : }
5199 : }
5200 0 : ret = ci_populate_pm_base(rdev);
5201 0 : if (ret) {
5202 0 : DRM_ERROR("ci_populate_pm_base failed\n");
5203 0 : return ret;
5204 : }
5205 0 : ci_dpm_start_smc(rdev);
5206 0 : ci_enable_vr_hot_gpio_interrupt(rdev);
5207 0 : ret = ci_notify_smc_display_change(rdev, false);
5208 0 : if (ret) {
5209 0 : DRM_ERROR("ci_notify_smc_display_change failed\n");
5210 0 : return ret;
5211 : }
5212 0 : ci_enable_sclk_control(rdev, true);
5213 0 : ret = ci_enable_ulv(rdev, true);
5214 0 : if (ret) {
5215 0 : DRM_ERROR("ci_enable_ulv failed\n");
5216 0 : return ret;
5217 : }
5218 0 : ret = ci_enable_ds_master_switch(rdev, true);
5219 0 : if (ret) {
5220 0 : DRM_ERROR("ci_enable_ds_master_switch failed\n");
5221 0 : return ret;
5222 : }
5223 0 : ret = ci_start_dpm(rdev);
5224 0 : if (ret) {
5225 0 : DRM_ERROR("ci_start_dpm failed\n");
5226 0 : return ret;
5227 : }
5228 0 : ret = ci_enable_didt(rdev, true);
5229 0 : if (ret) {
5230 0 : DRM_ERROR("ci_enable_didt failed\n");
5231 0 : return ret;
5232 : }
5233 0 : ret = ci_enable_smc_cac(rdev, true);
5234 0 : if (ret) {
5235 0 : DRM_ERROR("ci_enable_smc_cac failed\n");
5236 0 : return ret;
5237 : }
5238 0 : ret = ci_enable_power_containment(rdev, true);
5239 0 : if (ret) {
5240 0 : DRM_ERROR("ci_enable_power_containment failed\n");
5241 0 : return ret;
5242 : }
5243 :
5244 0 : ret = ci_power_control_set_level(rdev);
5245 0 : if (ret) {
5246 0 : DRM_ERROR("ci_power_control_set_level failed\n");
5247 0 : return ret;
5248 : }
5249 :
5250 0 : ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5251 :
5252 0 : ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5253 0 : if (ret) {
5254 0 : DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5255 0 : return ret;
5256 : }
5257 :
5258 0 : ci_thermal_start_thermal_controller(rdev);
5259 :
5260 0 : ci_update_current_ps(rdev, boot_ps);
5261 :
5262 0 : return 0;
5263 0 : }
5264 :
5265 0 : static int ci_set_temperature_range(struct radeon_device *rdev)
5266 : {
5267 : int ret;
5268 :
5269 0 : ret = ci_thermal_enable_alert(rdev, false);
5270 0 : if (ret)
5271 0 : return ret;
5272 0 : ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5273 0 : if (ret)
5274 0 : return ret;
5275 0 : ret = ci_thermal_enable_alert(rdev, true);
5276 : if (ret)
5277 0 : return ret;
5278 :
5279 : return ret;
5280 0 : }
5281 :
5282 0 : int ci_dpm_late_enable(struct radeon_device *rdev)
5283 : {
5284 : int ret;
5285 :
5286 0 : ret = ci_set_temperature_range(rdev);
5287 0 : if (ret)
5288 0 : return ret;
5289 :
5290 0 : ci_dpm_powergate_uvd(rdev, true);
5291 :
5292 0 : return 0;
5293 0 : }
5294 :
5295 0 : void ci_dpm_disable(struct radeon_device *rdev)
5296 : {
5297 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5298 0 : struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5299 :
5300 0 : ci_dpm_powergate_uvd(rdev, false);
5301 :
5302 0 : if (!ci_is_smc_running(rdev))
5303 0 : return;
5304 :
5305 0 : ci_thermal_stop_thermal_controller(rdev);
5306 :
5307 0 : if (pi->thermal_protection)
5308 0 : ci_enable_thermal_protection(rdev, false);
5309 0 : ci_enable_power_containment(rdev, false);
5310 0 : ci_enable_smc_cac(rdev, false);
5311 0 : ci_enable_didt(rdev, false);
5312 0 : ci_enable_spread_spectrum(rdev, false);
5313 0 : ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5314 0 : ci_stop_dpm(rdev);
5315 0 : ci_enable_ds_master_switch(rdev, false);
5316 0 : ci_enable_ulv(rdev, false);
5317 0 : ci_clear_vc(rdev);
5318 0 : ci_reset_to_default(rdev);
5319 0 : ci_dpm_stop_smc(rdev);
5320 0 : ci_force_switch_to_arb_f0(rdev);
5321 0 : ci_enable_thermal_based_sclk_dpm(rdev, false);
5322 :
5323 0 : ci_update_current_ps(rdev, boot_ps);
5324 0 : }
5325 :
5326 0 : int ci_dpm_set_power_state(struct radeon_device *rdev)
5327 : {
5328 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5329 0 : struct radeon_ps *new_ps = &pi->requested_rps;
5330 0 : struct radeon_ps *old_ps = &pi->current_rps;
5331 : int ret;
5332 :
5333 0 : ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5334 0 : if (pi->pcie_performance_request)
5335 0 : ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5336 0 : ret = ci_freeze_sclk_mclk_dpm(rdev);
5337 0 : if (ret) {
5338 0 : DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5339 0 : return ret;
5340 : }
5341 0 : ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5342 0 : if (ret) {
5343 0 : DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5344 0 : return ret;
5345 : }
5346 0 : ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5347 0 : if (ret) {
5348 0 : DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5349 0 : return ret;
5350 : }
5351 :
5352 0 : ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5353 0 : if (ret) {
5354 0 : DRM_ERROR("ci_update_vce_dpm failed\n");
5355 0 : return ret;
5356 : }
5357 :
5358 0 : ret = ci_update_sclk_t(rdev);
5359 0 : if (ret) {
5360 0 : DRM_ERROR("ci_update_sclk_t failed\n");
5361 0 : return ret;
5362 : }
5363 0 : if (pi->caps_dynamic_ac_timing) {
5364 0 : ret = ci_update_and_upload_mc_reg_table(rdev);
5365 0 : if (ret) {
5366 0 : DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5367 0 : return ret;
5368 : }
5369 : }
5370 0 : ret = ci_program_memory_timing_parameters(rdev);
5371 0 : if (ret) {
5372 0 : DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5373 0 : return ret;
5374 : }
5375 0 : ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5376 0 : if (ret) {
5377 0 : DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5378 0 : return ret;
5379 : }
5380 0 : ret = ci_upload_dpm_level_enable_mask(rdev);
5381 0 : if (ret) {
5382 0 : DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5383 0 : return ret;
5384 : }
5385 0 : if (pi->pcie_performance_request)
5386 0 : ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5387 :
5388 0 : return 0;
5389 0 : }
5390 :
5391 : #if 0
5392 : void ci_dpm_reset_asic(struct radeon_device *rdev)
5393 : {
5394 : ci_set_boot_state(rdev);
5395 : }
5396 : #endif
5397 :
5398 0 : void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5399 : {
5400 0 : ci_program_display_gap(rdev);
5401 0 : }
5402 :
5403 : union power_info {
5404 : struct _ATOM_POWERPLAY_INFO info;
5405 : struct _ATOM_POWERPLAY_INFO_V2 info_2;
5406 : struct _ATOM_POWERPLAY_INFO_V3 info_3;
5407 : struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5408 : struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5409 : struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5410 : };
5411 :
5412 : union pplib_clock_info {
5413 : struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5414 : struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5415 : struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5416 : struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5417 : struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5418 : struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5419 : };
5420 :
5421 : union pplib_power_state {
5422 : struct _ATOM_PPLIB_STATE v1;
5423 : struct _ATOM_PPLIB_STATE_V2 v2;
5424 : };
5425 :
5426 0 : static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5427 : struct radeon_ps *rps,
5428 : struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5429 : u8 table_rev)
5430 : {
5431 0 : rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5432 0 : rps->class = le16_to_cpu(non_clock_info->usClassification);
5433 0 : rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5434 :
5435 0 : if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5436 0 : rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5437 0 : rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5438 0 : } else {
5439 0 : rps->vclk = 0;
5440 0 : rps->dclk = 0;
5441 : }
5442 :
5443 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5444 0 : rdev->pm.dpm.boot_ps = rps;
5445 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5446 0 : rdev->pm.dpm.uvd_ps = rps;
5447 0 : }
5448 :
5449 0 : static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5450 : struct radeon_ps *rps, int index,
5451 : union pplib_clock_info *clock_info)
5452 : {
5453 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5454 0 : struct ci_ps *ps = ci_get_ps(rps);
5455 0 : struct ci_pl *pl = &ps->performance_levels[index];
5456 :
5457 0 : ps->performance_level_count = index + 1;
5458 :
5459 0 : pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5460 0 : pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5461 0 : pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5462 0 : pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5463 :
5464 0 : pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5465 0 : pi->sys_pcie_mask,
5466 0 : pi->vbios_boot_state.pcie_gen_bootup_value,
5467 0 : clock_info->ci.ucPCIEGen);
5468 0 : pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5469 0 : pi->vbios_boot_state.pcie_lane_bootup_value,
5470 0 : le16_to_cpu(clock_info->ci.usPCIELane));
5471 :
5472 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5473 0 : pi->acpi_pcie_gen = pl->pcie_gen;
5474 0 : }
5475 :
5476 0 : if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5477 0 : pi->ulv.supported = true;
5478 0 : pi->ulv.pl = *pl;
5479 0 : pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5480 0 : }
5481 :
5482 : /* patch up boot state */
5483 0 : if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5484 0 : pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5485 0 : pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5486 0 : pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5487 0 : pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5488 0 : }
5489 :
5490 0 : switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5491 : case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5492 0 : pi->use_pcie_powersaving_levels = true;
5493 0 : if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5494 0 : pi->pcie_gen_powersaving.max = pl->pcie_gen;
5495 0 : if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5496 0 : pi->pcie_gen_powersaving.min = pl->pcie_gen;
5497 0 : if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5498 0 : pi->pcie_lane_powersaving.max = pl->pcie_lane;
5499 0 : if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5500 0 : pi->pcie_lane_powersaving.min = pl->pcie_lane;
5501 : break;
5502 : case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5503 0 : pi->use_pcie_performance_levels = true;
5504 0 : if (pi->pcie_gen_performance.max < pl->pcie_gen)
5505 0 : pi->pcie_gen_performance.max = pl->pcie_gen;
5506 0 : if (pi->pcie_gen_performance.min > pl->pcie_gen)
5507 0 : pi->pcie_gen_performance.min = pl->pcie_gen;
5508 0 : if (pi->pcie_lane_performance.max < pl->pcie_lane)
5509 0 : pi->pcie_lane_performance.max = pl->pcie_lane;
5510 0 : if (pi->pcie_lane_performance.min > pl->pcie_lane)
5511 0 : pi->pcie_lane_performance.min = pl->pcie_lane;
5512 : break;
5513 : default:
5514 : break;
5515 : }
5516 0 : }
5517 :
5518 0 : static int ci_parse_power_table(struct radeon_device *rdev)
5519 : {
5520 0 : struct radeon_mode_info *mode_info = &rdev->mode_info;
5521 : struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5522 : union pplib_power_state *power_state;
5523 : int i, j, k, non_clock_array_index, clock_array_index;
5524 : union pplib_clock_info *clock_info;
5525 : struct _StateArray *state_array;
5526 : struct _ClockInfoArray *clock_info_array;
5527 : struct _NonClockInfoArray *non_clock_info_array;
5528 : union power_info *power_info;
5529 : int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5530 0 : u16 data_offset;
5531 0 : u8 frev, crev;
5532 : u8 *power_state_offset;
5533 : struct ci_ps *ps;
5534 :
5535 0 : if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5536 : &frev, &crev, &data_offset))
5537 0 : return -EINVAL;
5538 0 : power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5539 :
5540 0 : state_array = (struct _StateArray *)
5541 0 : (mode_info->atom_context->bios + data_offset +
5542 0 : le16_to_cpu(power_info->pplib.usStateArrayOffset));
5543 0 : clock_info_array = (struct _ClockInfoArray *)
5544 0 : (mode_info->atom_context->bios + data_offset +
5545 0 : le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5546 0 : non_clock_info_array = (struct _NonClockInfoArray *)
5547 0 : (mode_info->atom_context->bios + data_offset +
5548 0 : le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5549 :
5550 0 : rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5551 0 : state_array->ucNumEntries, GFP_KERNEL);
5552 0 : if (!rdev->pm.dpm.ps)
5553 0 : return -ENOMEM;
5554 0 : power_state_offset = (u8 *)state_array->states;
5555 0 : for (i = 0; i < state_array->ucNumEntries; i++) {
5556 : u8 *idx;
5557 0 : power_state = (union pplib_power_state *)power_state_offset;
5558 0 : non_clock_array_index = power_state->v2.nonClockInfoIndex;
5559 : non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5560 0 : &non_clock_info_array->nonClockInfo[non_clock_array_index];
5561 0 : if (!rdev->pm.power_state[i].clock_info)
5562 0 : return -EINVAL;
5563 0 : ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5564 0 : if (ps == NULL) {
5565 0 : kfree(rdev->pm.dpm.ps);
5566 0 : return -ENOMEM;
5567 : }
5568 0 : rdev->pm.dpm.ps[i].ps_priv = ps;
5569 0 : ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5570 : non_clock_info,
5571 0 : non_clock_info_array->ucEntrySize);
5572 : k = 0;
5573 0 : idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5574 0 : for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5575 0 : clock_array_index = idx[j];
5576 0 : if (clock_array_index >= clock_info_array->ucNumEntries)
5577 : continue;
5578 0 : if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5579 : break;
5580 0 : clock_info = (union pplib_clock_info *)
5581 0 : ((u8 *)&clock_info_array->clockInfo[0] +
5582 0 : (clock_array_index * clock_info_array->ucEntrySize));
5583 0 : ci_parse_pplib_clock_info(rdev,
5584 0 : &rdev->pm.dpm.ps[i], k,
5585 : clock_info);
5586 0 : k++;
5587 0 : }
5588 0 : power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5589 0 : }
5590 0 : rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5591 :
5592 : /* fill in the vce power states */
5593 0 : for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5594 : u32 sclk, mclk;
5595 0 : clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5596 0 : clock_info = (union pplib_clock_info *)
5597 0 : &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5598 0 : sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5599 0 : sclk |= clock_info->ci.ucEngineClockHigh << 16;
5600 0 : mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5601 0 : mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5602 0 : rdev->pm.dpm.vce_states[i].sclk = sclk;
5603 0 : rdev->pm.dpm.vce_states[i].mclk = mclk;
5604 : }
5605 :
5606 0 : return 0;
5607 0 : }
5608 :
5609 0 : static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5610 : struct ci_vbios_boot_state *boot_state)
5611 : {
5612 0 : struct radeon_mode_info *mode_info = &rdev->mode_info;
5613 : int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5614 : ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5615 0 : u8 frev, crev;
5616 0 : u16 data_offset;
5617 :
5618 0 : if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5619 : &frev, &crev, &data_offset)) {
5620 : firmware_info =
5621 0 : (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5622 0 : data_offset);
5623 0 : boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5624 0 : boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5625 0 : boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5626 0 : boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5627 0 : boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5628 0 : boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5629 0 : boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5630 :
5631 0 : return 0;
5632 : }
5633 0 : return -EINVAL;
5634 0 : }
5635 :
5636 0 : void ci_dpm_fini(struct radeon_device *rdev)
5637 : {
5638 : int i;
5639 :
5640 0 : for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5641 0 : kfree(rdev->pm.dpm.ps[i].ps_priv);
5642 : }
5643 0 : kfree(rdev->pm.dpm.ps);
5644 0 : kfree(rdev->pm.dpm.priv);
5645 0 : kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5646 0 : r600_free_extended_power_table(rdev);
5647 0 : }
5648 :
5649 0 : int ci_dpm_init(struct radeon_device *rdev)
5650 : {
5651 : int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5652 : SMU7_Discrete_DpmTable *dpm_table;
5653 : struct radeon_gpio_rec gpio;
5654 0 : u16 data_offset, size;
5655 0 : u8 frev, crev;
5656 : struct ci_power_info *pi;
5657 : int ret;
5658 0 : u32 mask;
5659 :
5660 0 : pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5661 0 : if (pi == NULL)
5662 0 : return -ENOMEM;
5663 0 : rdev->pm.dpm.priv = pi;
5664 :
5665 0 : ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5666 0 : if (ret)
5667 0 : pi->sys_pcie_mask = 0;
5668 : else
5669 0 : pi->sys_pcie_mask = mask;
5670 0 : pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5671 :
5672 0 : pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5673 0 : pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5674 0 : pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5675 0 : pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5676 :
5677 0 : pi->pcie_lane_performance.max = 0;
5678 0 : pi->pcie_lane_performance.min = 16;
5679 0 : pi->pcie_lane_powersaving.max = 0;
5680 0 : pi->pcie_lane_powersaving.min = 16;
5681 :
5682 0 : ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5683 0 : if (ret) {
5684 0 : ci_dpm_fini(rdev);
5685 0 : return ret;
5686 : }
5687 :
5688 0 : ret = r600_get_platform_caps(rdev);
5689 0 : if (ret) {
5690 0 : ci_dpm_fini(rdev);
5691 0 : return ret;
5692 : }
5693 :
5694 0 : ret = r600_parse_extended_power_table(rdev);
5695 0 : if (ret) {
5696 0 : ci_dpm_fini(rdev);
5697 0 : return ret;
5698 : }
5699 :
5700 0 : ret = ci_parse_power_table(rdev);
5701 0 : if (ret) {
5702 0 : ci_dpm_fini(rdev);
5703 0 : return ret;
5704 : }
5705 :
5706 0 : pi->dll_default_on = false;
5707 0 : pi->sram_end = SMC_RAM_END;
5708 :
5709 0 : pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5710 0 : pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5711 0 : pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5712 0 : pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5713 0 : pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5714 0 : pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5715 0 : pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5716 0 : pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5717 :
5718 0 : pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5719 :
5720 0 : pi->sclk_dpm_key_disabled = 0;
5721 0 : pi->mclk_dpm_key_disabled = 0;
5722 0 : pi->pcie_dpm_key_disabled = 0;
5723 0 : pi->thermal_sclk_dpm_enabled = 0;
5724 :
5725 : /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5726 0 : if ((rdev->pdev->device == 0x6658) &&
5727 0 : (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5728 0 : pi->mclk_dpm_key_disabled = 1;
5729 0 : }
5730 :
5731 0 : pi->caps_sclk_ds = true;
5732 :
5733 0 : pi->mclk_strobe_mode_threshold = 40000;
5734 0 : pi->mclk_stutter_mode_threshold = 40000;
5735 0 : pi->mclk_edc_enable_threshold = 40000;
5736 0 : pi->mclk_edc_wr_enable_threshold = 40000;
5737 :
5738 0 : ci_initialize_powertune_defaults(rdev);
5739 :
5740 0 : pi->caps_fps = false;
5741 :
5742 0 : pi->caps_sclk_throttle_low_notification = false;
5743 :
5744 0 : pi->caps_uvd_dpm = true;
5745 0 : pi->caps_vce_dpm = true;
5746 :
5747 0 : ci_get_leakage_voltages(rdev);
5748 0 : ci_patch_dependency_tables_with_leakage(rdev);
5749 0 : ci_set_private_data_variables_based_on_pptable(rdev);
5750 :
5751 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5752 0 : kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5753 0 : if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5754 0 : ci_dpm_fini(rdev);
5755 0 : return -ENOMEM;
5756 : }
5757 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5758 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5759 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5760 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5761 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5762 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5763 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5764 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5765 0 : rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5766 :
5767 0 : rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5768 0 : rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5769 0 : rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5770 :
5771 0 : rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5772 0 : rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5773 0 : rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5774 0 : rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5775 :
5776 0 : if (rdev->family == CHIP_HAWAII) {
5777 0 : pi->thermal_temp_setting.temperature_low = 94500;
5778 0 : pi->thermal_temp_setting.temperature_high = 95000;
5779 0 : pi->thermal_temp_setting.temperature_shutdown = 104000;
5780 0 : } else {
5781 0 : pi->thermal_temp_setting.temperature_low = 99500;
5782 0 : pi->thermal_temp_setting.temperature_high = 100000;
5783 0 : pi->thermal_temp_setting.temperature_shutdown = 104000;
5784 : }
5785 :
5786 0 : pi->uvd_enabled = false;
5787 :
5788 0 : dpm_table = &pi->smc_state_table;
5789 :
5790 0 : gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5791 0 : if (gpio.valid) {
5792 0 : dpm_table->VRHotGpio = gpio.shift;
5793 0 : rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5794 0 : } else {
5795 0 : dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5796 0 : rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5797 : }
5798 :
5799 0 : gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5800 0 : if (gpio.valid) {
5801 0 : dpm_table->AcDcGpio = gpio.shift;
5802 0 : rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5803 0 : } else {
5804 0 : dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5805 0 : rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5806 : }
5807 :
5808 0 : gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5809 0 : if (gpio.valid) {
5810 0 : u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5811 :
5812 0 : switch (gpio.shift) {
5813 : case 0:
5814 0 : tmp &= ~GNB_SLOW_MODE_MASK;
5815 0 : tmp |= GNB_SLOW_MODE(1);
5816 0 : break;
5817 : case 1:
5818 0 : tmp &= ~GNB_SLOW_MODE_MASK;
5819 0 : tmp |= GNB_SLOW_MODE(2);
5820 0 : break;
5821 : case 2:
5822 0 : tmp |= GNB_SLOW;
5823 0 : break;
5824 : case 3:
5825 0 : tmp |= FORCE_NB_PS1;
5826 0 : break;
5827 : case 4:
5828 0 : tmp |= DPM_ENABLED;
5829 0 : break;
5830 : default:
5831 : DRM_DEBUG("Invalid PCC GPIO: %u!\n", gpio.shift);
5832 : break;
5833 : }
5834 0 : WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5835 0 : }
5836 :
5837 0 : pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5838 0 : pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5839 0 : pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5840 0 : if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5841 0 : pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5842 0 : else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5843 0 : pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5844 :
5845 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5846 0 : if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5847 0 : pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5848 0 : else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5849 0 : pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5850 : else
5851 0 : rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5852 : }
5853 :
5854 0 : if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5855 0 : if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5856 0 : pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5857 0 : else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5858 0 : pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5859 : else
5860 0 : rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5861 : }
5862 :
5863 0 : pi->vddc_phase_shed_control = true;
5864 :
5865 : #if defined(CONFIG_ACPI)
5866 : pi->pcie_performance_request =
5867 : radeon_acpi_is_pcie_performance_request_supported(rdev);
5868 : #else
5869 0 : pi->pcie_performance_request = false;
5870 : #endif
5871 :
5872 0 : if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5873 : &frev, &crev, &data_offset)) {
5874 0 : pi->caps_sclk_ss_support = true;
5875 0 : pi->caps_mclk_ss_support = true;
5876 0 : pi->dynamic_ss = true;
5877 0 : } else {
5878 0 : pi->caps_sclk_ss_support = false;
5879 0 : pi->caps_mclk_ss_support = false;
5880 0 : pi->dynamic_ss = true;
5881 : }
5882 :
5883 0 : if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5884 0 : pi->thermal_protection = true;
5885 : else
5886 0 : pi->thermal_protection = false;
5887 :
5888 0 : pi->caps_dynamic_ac_timing = true;
5889 :
5890 0 : pi->uvd_power_gated = false;
5891 :
5892 : /* make sure dc limits are valid */
5893 0 : if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5894 0 : (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5895 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5896 0 : rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5897 :
5898 0 : pi->fan_ctrl_is_in_default_mode = true;
5899 :
5900 0 : return 0;
5901 0 : }
5902 :
5903 0 : void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5904 : struct seq_file *m)
5905 : {
5906 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5907 0 : struct radeon_ps *rps = &pi->current_rps;
5908 0 : u32 sclk = ci_get_average_sclk_freq(rdev);
5909 0 : u32 mclk = ci_get_average_mclk_freq(rdev);
5910 :
5911 0 : seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5912 0 : seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5913 0 : seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5914 : sclk, mclk);
5915 0 : }
5916 :
5917 0 : void ci_dpm_print_power_state(struct radeon_device *rdev,
5918 : struct radeon_ps *rps)
5919 : {
5920 0 : struct ci_ps *ps = ci_get_ps(rps);
5921 : struct ci_pl *pl;
5922 : int i;
5923 :
5924 0 : r600_dpm_print_class_info(rps->class, rps->class2);
5925 0 : r600_dpm_print_cap_info(rps->caps);
5926 0 : printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5927 0 : for (i = 0; i < ps->performance_level_count; i++) {
5928 0 : pl = &ps->performance_levels[i];
5929 0 : printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5930 : i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5931 : }
5932 0 : r600_dpm_print_ps_status(rdev, rps);
5933 0 : }
5934 :
5935 0 : u32 ci_dpm_get_current_sclk(struct radeon_device *rdev)
5936 : {
5937 0 : u32 sclk = ci_get_average_sclk_freq(rdev);
5938 :
5939 0 : return sclk;
5940 : }
5941 :
5942 0 : u32 ci_dpm_get_current_mclk(struct radeon_device *rdev)
5943 : {
5944 0 : u32 mclk = ci_get_average_mclk_freq(rdev);
5945 :
5946 0 : return mclk;
5947 : }
5948 :
5949 0 : u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5950 : {
5951 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5952 0 : struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5953 :
5954 0 : if (low)
5955 0 : return requested_state->performance_levels[0].sclk;
5956 : else
5957 0 : return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5958 0 : }
5959 :
5960 0 : u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5961 : {
5962 0 : struct ci_power_info *pi = ci_get_pi(rdev);
5963 0 : struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5964 :
5965 0 : if (low)
5966 0 : return requested_state->performance_levels[0].mclk;
5967 : else
5968 0 : return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5969 0 : }
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